diff --git a/bsp/imx6ul/KConfig b/bsp/imx6ul/KConfig new file mode 100644 index 0000000000000000000000000000000000000000..1c54a2697470b7f28f089dc234b3a9155ff489be --- /dev/null +++ b/bsp/imx6ul/KConfig @@ -0,0 +1,26 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config BOARD_IMX6UL + bool + select ARCH_ARM_CORTEX_A7 + default y + +source "$RTT_DIR/KConfig" +source "$PKGS_DIR/KConfig" + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/imx6ul/Makefile b/bsp/imx6ul/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..f9b884d9d3b458e1fa3d932e0bba91c2e8f027e2 --- /dev/null +++ b/bsp/imx6ul/Makefile @@ -0,0 +1,10 @@ +scons:=python ${SCONS}\scons.py + +all: + @$(scons) + +clean: + @$(scons) -c + +copy: + @$(scons) --copy -s diff --git a/bsp/imx6ul/README.md b/bsp/imx6ul/README.md new file mode 100644 index 0000000000000000000000000000000000000000..3dc29e5c935e799f670a1bed885d8cce8f3c1ade --- /dev/null +++ b/bsp/imx6ul/README.md @@ -0,0 +1,17 @@ +# i.MX6 SoloX + +Freescale's Smart Application Blueprint for Rapid Engineering (SABRE) board for smart devices + +Rev.B + +CPU: MCIMX6X4EVM10AB + +* ARM Cortex-A9 @ 1GHz +* ARM Cortex-M4 @ 200MHz + +* Freescale PF0200 PMIC +* 1GB DDR3 +* 32 MB x2 QuadSPI Flash + +* Freescale MMA8451 3-Axis Accelerometer +* Freescale MAG3110 3D Magnetometer diff --git a/bsp/imx6ul/SConscript b/bsp/imx6ul/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..fe0ae941ae9a759ae478de901caec1c961e56af8 --- /dev/null +++ b/bsp/imx6ul/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ul/SConstruct b/bsp/imx6ul/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..d3363ef87ecb14fb05df42adbf97d3d9872a8cd4 --- /dev/null +++ b/bsp/imx6ul/SConstruct @@ -0,0 +1,30 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-imx6.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/imx6ul/applications/SConscript b/bsp/imx6ul/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..01eb940dfb35f92c503a78b0b49a4354590f9f3a --- /dev/null +++ b/bsp/imx6ul/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/imx6ul/applications/application.c b/bsp/imx6ul/applications/application.c new file mode 100644 index 0000000000000000000000000000000000000000..d9580cda2330e4672f55051bbcd8eef42802d541 --- /dev/null +++ b/bsp/imx6ul/applications/application.c @@ -0,0 +1,45 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-11-20 Bernard the first version + */ + +#include + +#include +#include + +void show_freq(void) +{ + rt_kprintf("CPU: %d MHz\n", get_main_clock(CPU_CLK)/1000000); + rt_kprintf("DDR: %d MHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000000); + rt_kprintf("IPG: %d MHz\n", get_main_clock(IPG_CLK)/1000000); +} + +void init_thread(void* parameter) +{ + rt_kprintf("Freescale i.MX6 Platform SDK %s\n", SDK_VERSION_STRING); + show_freq(); + + rt_components_init(); +} + +int rt_application_init() +{ + rt_thread_t tid; + + tid = rt_thread_create("init", init_thread, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX/3, 10); + if (tid != RT_NULL) rt_thread_startup(tid); + + return 0; +} + diff --git a/bsp/imx6ul/applications/startup.c b/bsp/imx6ul/applications/startup.c new file mode 100644 index 0000000000000000000000000000000000000000..be041e0c0fb3e32aa1286f3f9d44586df824da0e --- /dev/null +++ b/bsp/imx6ul/applications/startup.c @@ -0,0 +1,74 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-12-05 Bernard the first version + */ + +#include +#include + +#include + +extern int rt_application_init(void); +extern void rt_hw_board_init(void); + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + // platform_init(); + // print_version(); + + /* initialzie hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize board */ + rt_hw_board_init(); + + /* show RT-Thread version */ + rt_show_version(); + + /* initialize memory system */ +#ifdef RT_USING_HEAP + rt_system_heap_init(HEAP_BEGIN, HEAP_END); +#endif + + /* initialize scheduler system */ + rt_system_scheduler_init(); + + /* initialize timer and soft timer thread */ + rt_system_timer_init(); + rt_system_timer_thread_init(); + + /* initialize application */ + rt_application_init(); + + /* initialize idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* invoke rtthread_startup */ + rtthread_startup(); + + return 0; +} diff --git a/bsp/imx6ul/drivers/Kconfig b/bsp/imx6ul/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/bsp/imx6ul/drivers/SConscript b/bsp/imx6ul/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..57eb65e971eec565340e04ed66d05d9ac4c6553d --- /dev/null +++ b/bsp/imx6ul/drivers/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('iomux/*.c') + +CPPPATH = [cwd, cwd + '/iomux'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/imx6ul/drivers/board.c b/bsp/imx6ul/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..75df0356300aa5bacf8faa2d8f60e48667466f54 --- /dev/null +++ b/bsp/imx6ul/drivers/board.c @@ -0,0 +1,79 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2016, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-11-20 Bernard the first version + */ + +#include +#include + +#include "board.h" + +#include +#include + +#include +#include +#include + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + epit_get_compare_event(HW_EPIT1); +} + +int rt_hw_timer_init(void) +{ + uint32_t freq; + + // Make sure the timer is off. + HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0; + + HW_ARMGLOBALTIMER_CONTROL.B.FCR0 =1; + + HW_ARMGLOBALTIMER_CONTROL.B.FCR1 =0; + + HW_ARMGLOBALTIMER_CONTROL.B.DBG_ENABLE =0; + + // Clear counter. + HW_ARMGLOBALTIMER_COUNTER_HI_WR(0); + HW_ARMGLOBALTIMER_COUNTER_LO_WR(0); + + // Now turn on the timer. + HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1; + + freq = get_main_clock(IPG_CLK); + + epit_init(HW_EPIT1, CLKSRC_IPG_CLK, freq / 1000000, + SET_AND_FORGET, 10000, WAIT_MODE_EN | STOP_MODE_EN); + + epit_counter_enable(HW_EPIT1, 10000, IRQ_MODE); + + rt_hw_interrupt_install(IMX_INT_EPIT1, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IMX_INT_EPIT1); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); + +/** + * This function will initialize hardware board + */ +void rt_hw_board_init(void) +{ + enable_neon_fpu(); + disable_strict_align_check(); + + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +/*@}*/ diff --git a/bsp/imx6ul/drivers/board.h b/bsp/imx6ul/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..b063e498790f5c9e540e889c51b729715c8fbf78 --- /dev/null +++ b/bsp/imx6ul/drivers/board.h @@ -0,0 +1,36 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard the first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include + +#define CONFIG_MX6 +#define CONFIG_MX6UL + +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) +#endif + +#define HEAP_END (void*)(0x80000000 + 32 * 1024 * 1024) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/imx6ul/drivers/iomux/iomux_config.c b/bsp/imx6ul/drivers/iomux/iomux_config.c new file mode 100644 index 0000000000000000000000000000000000000000..dc0cbc5cb1e74a21deab92f8e60143ab859c633b --- /dev/null +++ b/bsp/imx6ul/drivers/iomux/iomux_config.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +// File: iomux_config.c + +/* ------------------------------------------------------------------------------ + * + * This code was generated by a tool. + * Runtime Version:3.4.0.0 + * + * Changes to this file may cause incorrect behavior and will be lost if + * the code is regenerated. + * + * ------------------------------------------------------------------------------ +*/ + +#include "iomux_config.h" + +// Function to configure iomux for i.MX6SL board MCIMX6SLEVK rev. B. +void iomux_config(void) +{ + uart1_iomux_config(); +} diff --git a/bsp/imx6ul/drivers/iomux/iomux_config.h b/bsp/imx6ul/drivers/iomux/iomux_config.h new file mode 100644 index 0000000000000000000000000000000000000000..50be6390b319199d6a45be55c83b44c51cffda89 --- /dev/null +++ b/bsp/imx6ul/drivers/iomux/iomux_config.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +// File: iomux_config.h + +/* ------------------------------------------------------------------------------ + * + * This code was generated by a tool. + * Runtime Version:3.4.0.0 + * + * Changes to this file may cause incorrect behavior and will be lost if + * the code is regenerated. + * + * ------------------------------------------------------------------------------ +*/ + +#ifndef _IOMUX_CONFIG_H_ +#define _IOMUX_CONFIG_H_ + +// Board and Module IOMUXC configuration function prototypes. + +#if defined(__cplusplus) +extern "C" { +#endif + +// Board IOMUXC configuration function. +void iomux_config(void); + +// Module IOMUXC configuration functions. +void uart1_iomux_config(void); + +#if defined(__cplusplus) +} +#endif + +#endif // _IOMUX_CONFIG_H_ diff --git a/bsp/imx6ul/drivers/iomux/uart_iomux_config.c b/bsp/imx6ul/drivers/iomux/uart_iomux_config.c new file mode 100644 index 0000000000000000000000000000000000000000..bad8e945c338faf7f60a2cf078567dae946be0af --- /dev/null +++ b/bsp/imx6ul/drivers/iomux/uart_iomux_config.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +// File: uart_iomux_config.c + +/* ------------------------------------------------------------------------------ + * + * This code was generated by a tool. + * Runtime Version:3.4.0.0 + * + * Changes to this file may cause incorrect behavior and will be lost if + * the code is regenerated. + * + * ------------------------------------------------------------------------------ +*/ + +#include "iomux_config.h" +#include "registers/regsuart.h" +#include "iomux_register.h" +#include "io.h" +#include + +#define MX6UL_PAD_UART1_TX_DATA__UART1_TX1 (IOMUXC_BASE_ADDR+0x084) +#define MX6UL_PAD_UART1_RX_DATA__UART1_RX1 (IOMUXC_BASE_ADDR+0x088) +#define IOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT1 (IOMUXC_BASE_ADDR+0x624) + +void uart1_iomux_config(void) +{ + /* UART1 TXD */ + MX6UL_PAD_UART1_TX_DATA__UART1_TX(0x10b0); + /* UART1 RXD */ + MX6UL_PAD_UART1_RX_DATA__UART1_RX(0x10b0); +} + +void uart2_iomux_config(void) +{ +} + +void uart3_iomux_config(void) +{ +} + +void uart4_iomux_config(void) +{ +} + +void uart5_iomux_config(void) +{ +} + +void uart6_iomux_config(void) +{ +} + +void uart7_iomux_config(void) +{ +} + +void uart8_iomux_config(void) +{ +} + + +void uart_iomux_config(int instance) +{ + switch (instance) + { + case HW_UART1: + return uart1_iomux_config(); + + case HW_UART2: + return uart2_iomux_config(); + + case HW_UART3: + return uart3_iomux_config(); + + case HW_UART4: + return uart4_iomux_config(); + + case HW_UART5: + return uart5_iomux_config(); + + case HW_UART6: + return uart5_iomux_config(); + + case HW_UART7: + return uart5_iomux_config(); + + case HW_UART8: + return uart5_iomux_config(); + + default: + assert(false); + } +} + diff --git a/bsp/imx6ul/drivers/serial.c b/bsp/imx6ul/drivers/serial.c new file mode 100644 index 0000000000000000000000000000000000000000..dcb4e16e12d4537a41a334f6e3f7994c6535d857 --- /dev/null +++ b/bsp/imx6ul/drivers/serial.c @@ -0,0 +1,202 @@ +/* + * serial.c UART driver + * + * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * Maintainer: bernard.xiong + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#include +#include +#include + +#include + +#include "serial.h" + +struct hw_uart_device +{ + uint32_t instance; + int irqno; +}; + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hw_uart_device *uart; + uint32_t baudrate; + uint8_t parity, stopbits, datasize, flowcontrol; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + baudrate = cfg->baud_rate; + switch (cfg->data_bits) + { + case DATA_BITS_8: + datasize = EIGHTBITS; + break; + case DATA_BITS_7: + datasize = SEVENBITS; + break; + } + if (cfg->stop_bits == STOP_BITS_1) stopbits = STOPBITS_ONE; + else if (cfg->stop_bits == STOP_BITS_2) stopbits = STOPBITS_TWO; + + parity = PARITY_NONE; + flowcontrol = FLOWCTRL_OFF; + + /* Initialize UART */ + uart_init(uart->instance, baudrate, parity, stopbits, datasize, flowcontrol); + + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart"); + rt_hw_interrupt_mask(uart->irqno); + + /* Set the IRQ mode for the Rx FIFO */ + uart_set_FIFO_mode(uart->instance, RX_FIFO, 1, IRQ_MODE); + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + rt_hw_interrupt_mask(uart->irqno); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + rt_hw_interrupt_umask(uart->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + uart_putchar(uart->instance, (uint8_t*)&c); + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + ch = uart_getchar(uart->instance); + if (ch == NONE_CHAR) ch = -1; + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + HW_UART0, + IMX_INT_UART0 +}; +static struct rt_serial_device _serial0; +#endif + +#ifdef RT_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = +{ + HW_UART1, + IMX_INT_UART1 +}; +static struct rt_serial_device _serial1; +#endif + +int rt_hw_uart_init(void) +{ + struct hw_uart_device *uart; + struct serial_configure config; + + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + +#ifdef RT_USING_UART0 + uart = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif + +#ifdef RT_USING_UART1 + uart = &_uart1_device; + _serial1.ops = &_uart_ops; + _serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); +#endif + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/imx6ul/drivers/serial.h b/bsp/imx6ul/drivers/serial.h new file mode 100644 index 0000000000000000000000000000000000000000..52e6f07ea399abdcc21a3d21b334db69fe77dddc --- /dev/null +++ b/bsp/imx6ul/drivers/serial.h @@ -0,0 +1,39 @@ +/* + * UART driver + * + * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * Maintainer: bernard.xiong + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#include + +int rt_hw_uart_init(void); + +#endif + + diff --git a/bsp/imx6ul/imx6.lds b/bsp/imx6ul/imx6.lds new file mode 100644 index 0000000000000000000000000000000000000000..d8d7480006d3052342f8134253b3e03f47459ee1 --- /dev/null +++ b/bsp/imx6ul/imx6.lds @@ -0,0 +1,99 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +SECTIONS +{ + . = 0x80100000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(16 * 1024); + .l1_page_table : + { + __l1_page_table_start = .; + . += 16K; + } + + __data_start = .; + . = ALIGN(4); + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(4); + __bss_start = __data_end; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/imx6ul/platform/SConscript b/bsp/imx6ul/platform/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..34834e639167c66b03d176f3b6966d6daf6d6b7d --- /dev/null +++ b/bsp/imx6ul/platform/SConscript @@ -0,0 +1,26 @@ +from building import * + +cwd = GetCurrentDir() +src = Split(''' +drivers/epit.c +drivers/gpt.c +drivers/imx_timer.c +drivers/imx_i2c.c +drivers/imx_uart.c +cpu/armv7_cache.c +cpu/gic.c +cpu/ccm_pll2.c +cpu/mmu.c +cpu/cortex_a_gcc.S +''') + +CPPPATH = [ cwd + '/cpu', +cwd + '/include', +cwd + '/include/mx6ul', +cwd + '/include/mx6ul/registers' +] +CPPDEFINES = ['CHIP_MX6UL'] + +group = DefineGroup('Platform', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/imx6ul/platform/cpu/arm_cp_registers.h b/bsp/imx6ul/platform/cpu/arm_cp_registers.h new file mode 100644 index 0000000000000000000000000000000000000000..cce58197f3296f67a235b699d93bb7c98354740e --- /dev/null +++ b/bsp/imx6ul/platform/cpu/arm_cp_registers.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +//! @addtogroup cortexa9 +//! @{ + +/*! + * @file arm_cp_registers.h + * @brief Definitions for ARM coprocessor registers. + */ + +#ifndef __ARM_CP_REGISTERS_H__ +#define __ARM_CP_REGISTERS_H__ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @name ACTLR +//@{ +#define BM_ACTLR_SMP (1 << 6) +//@} + +//! @name DFSR +//@{ +#define BM_DFSR_WNR (1 << 11) //!< Write not Read bit. 0=read, 1=write. +#define BM_DFSR_FS4 (0x400) //!< Fault status bit 4.. +#define BP_DFSR_FS4 (10) //!< Bit position for FS[4]. +#define BM_DFSR_FS (0xf) //!< Fault status bits [3:0]. +//@} + +//! @name SCTLR +//@{ +#define BM_SCTLR_TE (1 << 30) //!< Thumb exception enable. +#define BM_SCTLR_AFE (1 << 29) //!< Access flag enable. +#define BM_SCTLR_TRE (1 << 28) //!< TEX remap enable. +#define BM_SCTLR_NMFI (1 << 27) //!< Non-maskable FIQ support. +#define BM_SCTLR_EE (1 << 25) //!< Exception endianess. +#define BM_SCTLR_VE (1 << 24) //!< Interrupt vectors enable. +#define BM_SCTLR_FI (1 << 21) //!< Fast interrupt configurable enable. +#define BM_SCTLR_RR (1 << 14) //!< Round Robin +#define BM_SCTLR_V (1 << 13) //!< Vectors +#define BM_SCTLR_I (1 << 12) //!< Instruction cache enable +#define BM_SCTLR_Z (1 << 11) //!< Branch prediction enable +#define BM_SCTLR_SW (1 << 10) //!< SWP and SWPB enable +#define BM_SCTLR_CP15BEN (1 << 5) //!< CP15 barrier enable +#define BM_SCTLR_C (1 << 2) //!< Data cache enable +#define BM_SCTLR_A (1 << 1) //!< Alignment check enable +#define BM_SCTLR_M (1 << 0) //!< MMU enable +//@} + +//! @} + +#endif // __ARM_CP_REGISTERS_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// + diff --git a/bsp/imx6ul/platform/cpu/armv7_cache.c b/bsp/imx6ul/platform/cpu/armv7_cache.c new file mode 100644 index 0000000000000000000000000000000000000000..e030bcb07071ae928fba403be09732e6d86697e7 --- /dev/null +++ b/bsp/imx6ul/platform/cpu/armv7_cache.c @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cortex_a.h" +#include "arm_cp_registers.h" + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Check if dcache is enabled or disabled +int arm_dcache_state_query() +{ + uint32_t sctlr; // System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + if (sctlr & BM_SCTLR_C) + { + return 1; + } + + return 0; +} + +void arm_dcache_enable() +{ + uint32_t sctlr; // System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + if (!(sctlr & BM_SCTLR_C)) + { + // set C bit (data caching enable) + sctlr |= BM_SCTLR_C; + + // write modified sctlr + _ARM_MCR(15, 0, sctlr, 1, 0, 0); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); + } +} + +void arm_dcache_disable() +{ + uint32_t sctlr; // System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + // set C bit (data caching enable) + sctlr &= ~BM_SCTLR_C; + + // write modified sctlr + _ARM_MCR(15, 0, sctlr, 1, 0, 0); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void arm_dcache_invalidate() +{ + uint32_t csid; // Cache Size ID + uint32_t wayset; // wayset parameter + int num_sets; // number of sets + int num_ways; // number of ways + + _ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID + + // Fill number of sets and number of ways from csid register This walues are decremented by 1 + num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT) + + // Invalidation all lines (all Sets in all ways) + while (num_ways >= 0) + { + num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT) + while (num_sets >= 0 ) + { + wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_sets << 3SETWAY_WAY_SHIFT) + // invalidate line if we know set and way + _ARM_MCR(15, 0, wayset, 7, 6, 2); + num_sets--; + } + num_ways--; + } + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void arm_dcache_invalidate_line(const void * addr) +{ + uint32_t csidr = 0, line_size = 0; + uint32_t va; + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK + + // Invalidate data cache line by va to PoC (Point of Coherency). + _ARM_MCR(15, 0, va, 7, 6, 1); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void arm_dcache_invalidate_mlines(const void * addr, size_t length) +{ + uint32_t va; + uint32_t csidr = 0, line_size = 0; + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + + // align the address with line + const void * end_addr = (const void *)((uint32_t)addr + length); + + do + { + // Clean data cache line to PoC (Point of Coherence) by va. + va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK + _ARM_MCR(15, 0, va, 7, 6, 1); + // increment addres to next line and decrement lenght + addr = (const void *) ((uint32_t)addr + line_size); + } while (addr < end_addr); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void arm_dcache_flush() +{ + uint32_t csid; // Cache Size ID + uint32_t wayset; // wayset parameter + int num_sets; // number of sets + int num_ways; // number of ways + + _ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID + + // Fill number of sets and number of ways from csid register This walues are decremented by 1 + num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`) + while (num_ways >= 0) + { + num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT ) + while (num_sets >= 0 ) + { + wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT) + // FLUSH (clean) line if we know set and way + _ARM_MCR(15, 0, wayset, 7, 10, 2); + num_sets--; + } + num_ways--; + } + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void arm_dcache_flush_line(const void * addr) +{ + uint32_t csidr = 0, line_size = 0; + uint32_t va; + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK + + // Clean data cache line to PoC (Point of Coherence) by va. + _ARM_MCR(15, 0, va, 7, 10, 1); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void arm_dcache_flush_mlines(const void * addr, size_t length) +{ + uint32_t va; + uint32_t csidr = 0, line_size = 0; + const void * end_addr = (const void *)((uint32_t)addr + length); + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + + do + { + // Clean data cache line to PoC (Point of Coherence) by va. + va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK + _ARM_MCR(15, 0, va, 7, 10, 1); + + // increment addres to next line and decrement lenght + addr = (const void *) ((uint32_t)addr + line_size); + } while (addr < end_addr); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +int arm_icache_state_query() +{ + uint32_t sctlr; // System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + if (sctlr & BM_SCTLR_I) + { + return 1; + } + + return 0; +} + +void arm_icache_enable() +{ + uint32_t sctlr ;// System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + // ignore the operation if I is enabled already + if(!(sctlr & BM_SCTLR_I)) + { + // set I bit (instruction caching enable) + sctlr |= BM_SCTLR_I; + + // write modified sctlr + _ARM_MCR(15, 0, sctlr, 1, 0, 0); + + // synchronize context on this processor + _ARM_ISB(); + } +} + +void arm_icache_disable() +{ + uint32_t sctlr ;// System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + // Clear I bit (instruction caching enable) + sctlr &= ~BM_SCTLR_I; + + // write modified sctlr + _ARM_MCR(15, 0, sctlr, 1, 0, 0); + + // synchronize context on this processor + _ARM_ISB(); +} + +void arm_icache_invalidate() +{ + uint32_t SBZ = 0x0u; + + _ARM_MCR(15, 0, SBZ, 7, 5, 0); + + // synchronize context on this processor + _ARM_ISB(); +} + +void arm_icache_invalidate_is() +{ + uint32_t SBZ = 0x0u; + + _ARM_MCR(15, 0, SBZ, 7, 1, 0); + + // synchronize context on this processor + _ARM_ISB(); +} + +void arm_icache_invalidate_line(const void * addr) +{ + uint32_t csidr = 0, line_size = 0; + uint32_t va; + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK + + // Invalidate instruction cache by va to PoU (Point of unification). + _ARM_MCR(15, 0, va, 7, 5, 1); + + // synchronize context on this processor + _ARM_ISB(); +} + +void arm_icache_invalidate_mlines(const void * addr, size_t length) +{ + uint32_t va; + uint32_t csidr = 0, line_size = 0; + const void * end_addr = (const void *)((uint32_t)addr + length); + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + + do + { + // Clean data cache line to PoC (Point of Coherence) by va. + va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK + _ARM_MCR(15, 0, va, 7, 5, 1); + // increment addres to next line and decrement lenght + addr = (const void *) ((uint32_t)addr + line_size); + } while (addr < end_addr); + + // synchronize context on this processor + _ARM_ISB(); +} + + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/cpu/ccm_pll.h b/bsp/imx6ul/platform/cpu/ccm_pll.h new file mode 100644 index 0000000000000000000000000000000000000000..8bd9cccdf2715c15eb96a570dfcfaaf0972260e6 --- /dev/null +++ b/bsp/imx6ul/platform/cpu/ccm_pll.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CCM_PLL_H_ +#define _CCM_PLL_H_ + +#include "sdk_types.h" + +//! @addtogroup diag_clocks +//! @{ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +#define CLK_SRC_32K 32768 + +//! @brief Create a clock gate bit mask value. +//! @param x 0..15, for CG0 to CG15 +#define CG(x) (3 << (x*2)) + +//! @brief Constants for CCM CCGR register fields. +enum _clock_gate_constants +{ + CLOCK_ON = 0x3, //!< Clock always on in both run and stop modes. + CLOCK_ON_RUN = 0x1, //!< Clock on only in run mode. + CLOCK_OFF = 0x0 //!< Clocked gated off. +}; + +//! @brief Low power mdoes. +typedef enum _lp_modes { + RUN_MODE, + WAIT_MODE, + STOP_MODE, +} lp_modes_t; + +//! @brief Main clock sources. +typedef enum _main_clocks { + CPU_CLK, + AXI_CLK, + MMDC_CH0_AXI_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + MMDC_CH1_AXI_CLK, +} main_clocks_t; + +//! @brief Peripheral clocks. +typedef enum _peri_clocks { + UART1_MODULE_CLK, + UART2_MODULE_CLK, + UART3_MODULE_CLK, + UART4_MODULE_CLK, + UART5_MODULE_CLK, + UART6_MODULE_CLK, + UART7_MODULE_CLK, + UART8_MODULE_CLK, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSTICK1_CLK, + MSTICK2_CLK, + RAWNAND_CLK, + USB_CLK, + VPU_CLK, + SPI_CLK, + CAN_CLK +} peri_clocks_t; + +//! @brief Available PLLs. +typedef enum plls { + PLL1, + PLL2, + PLL3, + PLL4, + PLL5, +} plls_t; + +extern const uint32_t PLL1_OUTPUT; +extern const uint32_t PLL2_OUTPUT[]; +extern const uint32_t PLL3_OUTPUT[]; +extern const uint32_t PLL4_OUTPUT; +extern const uint32_t PLL5_OUTPUT; + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @brief Set/unset clock gating for a peripheral. +//! @param base_address configure clock gating for that module from the base address. +//! @param gating_mode clock gating mode: CLOCK_ON or CLOCK_OFF. +void clock_gating_config(uint32_t base_address, uint32_t gating_mode); + +//! @brief Returns the frequency of a clock in megahertz. +uint32_t get_main_clock(main_clocks_t clk); + +//! @brief Returns the frequency of a clock in megahertz. +uint32_t get_peri_clock(peri_clocks_t clk); + +//! @brief Inits clock sources. +void ccm_init(void); + +//! @brief Prepare and enter in a low power mode. +//! @param lp_mode low power mode : WAIT_MODE or STOP_MODE. +void ccm_enter_low_power(lp_modes_t lp_mode); + +//! @brief Mask/unmask an interrupt source that can wake up the processor when in a +//! low power mode. +//! +//! @param irq_id ID of the interrupt to mask/unmask. +//! @param doEnable Pass true to unmask the source ID. +void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable); + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/cpu/ccm_pll2.c b/bsp/imx6ul/platform/cpu/ccm_pll2.c new file mode 100644 index 0000000000000000000000000000000000000000..b92a325f69a11c1347fe6a95af6c28e5a7cc2ba1 --- /dev/null +++ b/bsp/imx6ul/platform/cpu/ccm_pll2.c @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "sdk.h" +#include "registers/regsccm.h" +#include "registers/regsccmanalog.h" +#include "registers/regsuart.h" +#include "registers/regsepit.h" +#include "registers/regsspba.h" +#include "registers/regssdmaarm.h" +#include "registers/regsgpt.h" +#include "registers/regsi2c.h" +#include "registers/regsecspi.h" +#include "ccm_pll.h" +//#include "hardware.h" +//#include "soc_memory_map.h" +#define HW_ANADIG_REG_CORE (ANATOP_IPS_BASE_ADDR + 0x140) +#define HW_ANADIG_PLL_SYS_RW (ANATOP_IPS_BASE_ADDR + 0x000) +#define HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(x) ((((x)-700)/25) << 0) +#define HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(x) ((((x)-700)/25) << 18) +#define HW_ANADIG_REG_CORE_V_CORE_MSK 0x1F +#define HW_ANADIG_REG_CORE_V_SOC_MSK (0x1F << 18) + +uint32_t g_arm_clk = 528000000; + +const uint32_t PLL2_OUTPUT[] = { 528000000, 396000000, 352000000, 198000000 }; +const uint32_t PLL3_OUTPUT[] = { 480000000, 720000000, 540000000, 508235294, 454736842 }; +const uint32_t PLL4_OUTPUT = 650000000; +const uint32_t PLL5_OUTPUT = 650000000; + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +void set_soc_core_voltage(unsigned int v_core_mv, unsigned int v_soc_mv) +{ + unsigned int val, val_v_core, val_v_soc; + + val = reg32_read(HW_ANADIG_REG_CORE); + val &= ~HW_ANADIG_REG_CORE_V_CORE_MSK; + val &= ~HW_ANADIG_REG_CORE_V_SOC_MSK; + + val_v_core = HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(v_core_mv); + val_v_soc = HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(v_soc_mv); + + val |= val_v_core | val_v_soc; + reg32_write(HW_ANADIG_REG_CORE, val); +} + +void setup_clk(void) +{ + uint32_t div_select; + uint32_t temp; + uint32_t arm_clk = g_arm_clk/1000000; + + switch(arm_clk) + { + case 400: + div_select = 33; + set_soc_core_voltage(1150, 1175); + return; + case 528: + div_select = 44; + set_soc_core_voltage(1250, 1250); + break; + case 756: + div_select = 63; + set_soc_core_voltage(1250, 1250); + printf("ARM Clock set to 756MHz\r\n"); + break; + default: + return; + } + + // first, make sure ARM_PODF is clear + HW_CCM_CACRR_WR(0); + // write the div_select value into HW_ANADIG_PLL_SYS_RW + // this will re-program the PLL to the new freq + + temp = readl(HW_ANADIG_PLL_SYS_RW); + temp |= 0x10000;// set BYBASS + writel(temp, HW_ANADIG_PLL_SYS_RW); + + temp = readl(HW_ANADIG_PLL_SYS_RW); + temp &= ~(0x0000007F); + temp |= div_select; // Update div + writel(temp, HW_ANADIG_PLL_SYS_RW); + + /* Wait for PLL to lock */ + while(!(readl(HW_ANADIG_PLL_SYS_RW) & 0x80000000)); + + /*disable BYPASS*/ + temp = readl(HW_ANADIG_PLL_SYS_RW); + temp &= ~0x10000; + writel(temp, HW_ANADIG_PLL_SYS_RW); +} + +void ccm_init(void) +{ + HW_CCM_CCGR0_WR(0xffffffff); + HW_CCM_CCGR1_WR(0xffffffff); // EPIT, ESAI, GPT enabled by driver + HW_CCM_CCGR2_WR(0xffffffff); // I2C enabled by driver + HW_CCM_CCGR3_WR(0xffffffff); + HW_CCM_CCGR4_WR(0xffffffff); // GPMI, Perfmon enabled by driver + HW_CCM_CCGR5_WR(0xffffffff); // UART, SATA enabled by driver + HW_CCM_CCGR6_WR(0xffffffff); + + /* + * Keep default settings at reset. + * pre_periph_clk_sel is by default at 0, so the selected output + * of PLL2 is the main output at 528MHz. + * => by default, ahb_podf divides by 4 => AHB_CLK@132MHz. + * => by default, ipg_podf divides by 2 => IPG_CLK@66MHz. + */ + HW_CCM_CBCDR.U = BF_CCM_CBCDR_AHB_PODF(3) + | BF_CCM_CBCDR_AXI_PODF(1) + | BF_CCM_CBCDR_IPG_PODF(1); + + setup_clk(); + + /* Power up 480MHz PLL */ + reg32_write_mask(HW_CCM_ANALOG_PLL_USB1_ADDR, 0x00001000, 0x00001000); + + /* Enable 480MHz PLL */ + reg32_write_mask(HW_CCM_ANALOG_PLL_USB1_ADDR, 0x00002000, 0x00002000); + + reg32_write_mask(HW_CCM_CSCDR1_ADDR, 0x00000000, 0x0000003F); +} + +uint32_t get_main_clock(main_clocks_t clock) +{ + uint32_t ret_val = 0; + uint32_t pre_periph_clk_sel = HW_CCM_CBCMR.B.PRE_PERIPH_CLK_SEL; + + switch (clock) { + case CPU_CLK: + ret_val = g_arm_clk; + break; + case AXI_CLK: + ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AXI_PODF + 1); + break; + case MMDC_CH0_AXI_CLK: + ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH0_AXI_PODF + 1); + break; + case AHB_CLK: + ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1); + break; + case IPG_CLK: + ret_val = + PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + + 1) / (HW_CCM_CBCDR.B.IPG_PODF + 1); + break; + case IPG_PER_CLK: + ret_val = + PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + + 1) / (HW_CCM_CBCDR.B.IPG_PODF + + 1) / (HW_CCM_CSCMR1.B.PERCLK_PODF + 1); + break; + default: + break; + } + + return ret_val; +} + +uint32_t get_peri_clock(peri_clocks_t clock) +{ + uint32_t ret_val = 0; + + switch (clock) + { + case UART1_MODULE_CLK: + case UART2_MODULE_CLK: + case UART3_MODULE_CLK: + case UART4_MODULE_CLK: + case UART5_MODULE_CLK: + case UART6_MODULE_CLK: + case UART7_MODULE_CLK: + case UART8_MODULE_CLK: + // UART source clock is a fixed PLL3 / 6 + ret_val = PLL3_OUTPUT[0] / 6 / (HW_CCM_CSCDR1.B.UART_CLK_PODF + 1); + break; + case SPI_CLK: + ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCDR2.B.ECSPI_CLK_PODF + 1); + break; + case RAWNAND_CLK: + ret_val = + PLL3_OUTPUT[0] / (HW_CCM_CS2CDR.B.ENFC_CLK_PRED + 1) / (HW_CCM_CS2CDR.B.ENFC_CLK_PODF + + 1); + break; + case CAN_CLK: + // For i.mx6dq/sdl CAN source clock is a fixed PLL3 / 8 + ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCMR2.B.CAN_CLK_PODF + 1); + break; + default: + break; + } + + return ret_val; +} + +void ccm_ccgr_config(uint32_t ccm_ccgrx, uint32_t cgx_offset, uint32_t gating_mode) +{ + if (gating_mode == CLOCK_ON) + { + *(volatile uint32_t *)(ccm_ccgrx) |= cgx_offset; + } + else + { + *(volatile uint32_t *)(ccm_ccgrx) &= ~cgx_offset; + } +} + +void clock_gating_config(uint32_t base_address, uint32_t gating_mode) +{ + uint32_t ccm_ccgrx = 0; + uint32_t cgx_offset = 0; + + switch (base_address) + { + case REGS_UART1_BASE: + ccm_ccgrx = HW_CCM_CCGR5_ADDR; + cgx_offset = CG(12); + break; + case REGS_UART2_BASE: + ccm_ccgrx = HW_CCM_CCGR0_ADDR; + cgx_offset = CG(14); + break; + case REGS_UART3_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(5); + break; + case REGS_UART4_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(12); + break; + case REGS_UART5_BASE: + ccm_ccgrx = HW_CCM_CCGR3_ADDR; + cgx_offset = CG(1); + break; + case REGS_UART6_BASE: + ccm_ccgrx = HW_CCM_CCGR3_ADDR; + cgx_offset = CG(3); + break; + case REGS_UART7_BASE: + ccm_ccgrx = HW_CCM_CCGR5_ADDR; + cgx_offset = CG(13); + break; + case REGS_UART8_BASE: + ccm_ccgrx = HW_CCM_CCGR6_ADDR; + cgx_offset = CG(7); + break; + case REGS_SPBA_BASE: + ccm_ccgrx = HW_CCM_CCGR5_ADDR; + cgx_offset = CG(6); + break; + case REGS_SDMAARM_BASE: + ccm_ccgrx = HW_CCM_CCGR5_ADDR; + cgx_offset = CG(3); + break; + case REGS_EPIT1_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(6); + break; + case REGS_EPIT2_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(7); + break; + case REGS_GPT1_BASE: + case REGS_GPT2_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(10)|CG(11); + break; + case REGS_I2C1_BASE: + ccm_ccgrx = HW_CCM_CCGR2_ADDR; + cgx_offset = CG(3); + break; + case REGS_I2C2_BASE: + ccm_ccgrx = HW_CCM_CCGR2_ADDR; + cgx_offset = CG(4); + break; + case REGS_I2C3_BASE: + ccm_ccgrx = HW_CCM_CCGR2_ADDR; + cgx_offset = CG(5); + break; + case REGS_ECSPI1_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(0); + break; + case REGS_ECSPI2_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(1); + break; + case REGS_ECSPI3_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(2); + break; + case REGS_ECSPI4_BASE: + ccm_ccgrx = HW_CCM_CCGR1_ADDR; + cgx_offset = CG(3); + break; + default: + break; + } + + // apply changes only if a valid address was found + if (ccm_ccgrx != 0) + { + ccm_ccgr_config(ccm_ccgrx, cgx_offset, gating_mode); + } +} +//////////////////////////////////////////////////////////////////////////////// +// End of file +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/cpu/cortex_a.h b/bsp/imx6ul/platform/cpu/cortex_a.h new file mode 100644 index 0000000000000000000000000000000000000000..cb815615bd0ae2b529b130e0a6a6720b7a2f7857 --- /dev/null +++ b/bsp/imx6ul/platform/cpu/cortex_a.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__CORTEX_A_H__) +#define __CORTEX_A9H__ + +#include +#include +#include + +//! @addtogroup cortexa9 +//! @{ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @name Instruction macros +//@{ +#define _ARM_NOP() asm volatile ("nop\n\t") +#define _ARM_WFI() asm volatile ("wfi\n\t") +#define _ARM_WFE() asm volatile ("wfe\n\t") +#define _ARM_SEV() asm volatile ("sev\n\t") +#define _ARM_DSB() asm volatile ("dsb\n\t") +#define _ARM_ISB() asm volatile ("isb\n\t") + +#define _ARM_MRC(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + asm volatile ("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r" (Rt)) + +#define _ARM_MCR(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + asm volatile ("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" :: [input] "r" (Rt)) +//@} + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif +//! @name Misc +//@{ +//! @brief Enable or disable the IRQ and FIQ state. +bool arm_set_interrupt_state(bool enable); + +//! @brief Get current CPU ID. +int cpu_get_current(void); + +//! @brief Enable the NEON MPE. +void enable_neon_fpu(void); + +//! @brief Disable aborts on unaligned accesses. +void disable_strict_align_check(void); + +//! @brief Get base address of private perpherial space. +//! +//! @return The address of the ARM CPU's private peripherals. +uint32_t get_arm_private_peripheral_base(void); +//@} + +//! @name Data cache operations +//@{ + +//! @brief Check if dcache is enabled or disabled. +int arm_dcache_state_query(); + +//! @brief Enables data cache at any available cache level. +//! +//! Works only if MMU is enabled! +void arm_dcache_enable(); + +//! @brief Disables the data cache at any available cache level. +void arm_dcache_disable(); + +//! @brief Invalidates the entire data cache. +void arm_dcache_invalidate(); + +//! @brief Invalidate a line of data cache. +void arm_dcache_invalidate_line(const void * addr); + +//! @brief Invalidate a number of lines of data cache. +//! +//! Number of lines depends on length parameter and size of line. +//! Size of line for A9 L1 cache is 32B. +void arm_dcache_invalidate_mlines(const void * addr, size_t length); + +//! @brief Flush (clean) all lines of cache (all sets in all ways). +void arm_dcache_flush(); + +//! @brief Flush (clean) one line of cache. +void arm_dcache_flush_line(const void * addr); + +// @brief Flush (clean) multiple lines of cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_dcache_flush_mlines(const void * addr, size_t length); +//@} + +//! @name Instrution cache operations +//@{ + +//! @brief Check if icache is enabled or disabled. +int arm_icache_state_query(); + +//! @brief Enables instruction cache at any available cache level. +//! +//! Works without enabled MMU too! +void arm_icache_enable(); + +//! @brief Disables the instruction cache at any available cache level. +void arm_icache_disable(); + +//! @brief Invalidates the entire instruction cache. +void arm_icache_invalidate(); + +//! @brief Invalidates the entire instruction cache inner shareable. +void arm_icache_invalidate_is(); + +//! @brief Invalidate a line of the instruction cache. +void arm_icache_invalidate_line(const void * addr); + +//! @brief Invalidate a number of lines of instruction cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_icache_invalidate_mlines(const void * addr, size_t length); +//@} + +//! @name TLB operations +//@{ +//! @brief Invalidate entire unified TLB. +void arm_unified_tlb_invalidate(void); + +//! @brief Invalidate entire unified TLB Inner Shareable. +void arm_unified_tlb_invalidate_is(void); +//@} + +//! @name Branch predictor operations +//@{ +//! @brief Enable branch prediction. +void arm_branch_prediction_enable(void); + +//! @brief Disable branch prediction. +void arm_branch_prediction_disable(void); + +//! @brief Invalidate entire branch predictor array. +void arm_branch_target_cache_invalidate(void); + +//! @brief Invalidate entire branch predictor array Inner Shareable +void arm_branch_target_cache_invalidate_is(void); +//@} + +//! @name SCU +//@{ +//! @brief Enables the SCU. +void scu_enable(void); + +//! @brief Set this CPU as participating in SMP. +void scu_join_smp(void); + +//! @brief Set this CPU as not participating in SMP. +void scu_leave_smp(void); + +//! @brief Determine which CPUs are participating in SMP. +//! +//! The return value is 1 bit per core: +//! - bit 0 - CPU 0 +//! - bit 1 - CPU 1 +//! - etc... +unsigned int scu_get_cpus_in_smp(void); + +//! @brief Enable the broadcasting of cache & TLB maintenance operations. +//! +//! When enabled AND in SMP, broadcast all "inner sharable" +//! cache and TLM maintenance operations to other SMP cores +void scu_enable_maintenance_broadcast(void); + +//! @brief Disable the broadcasting of cache & TLB maintenance operations. +void scu_disable_maintenance_broadcast(void); + +//! @brief Invalidates the SCU copy of the tag rams for the specified core. +//! +//! Typically only done at start-up. +//! Possible flow: +//! - Invalidate L1 caches +//! - Invalidate SCU copy of TAG RAMs +//! - Join SMP +//! +//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc... +//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways. +void scu_secure_invalidate(unsigned int cpu, unsigned int ways); +//@} + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif // __CORTEX_A_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/cpu/cortex_a_gcc.S b/bsp/imx6ul/platform/cpu/cortex_a_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..ce34242fc9818bd188990629dc4687fe87a14f6a --- /dev/null +++ b/bsp/imx6ul/platform/cpu/cortex_a_gcc.S @@ -0,0 +1,327 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file cortexA9.s + * @brief This file contains cortexA9 functions + * + */ + + .code 32 + .section ".text","ax" + +/* + * bool arm_set_interrupt_state(bool enable) + */ + .global arm_set_interrupt_state + .func arm_set_interrupt_state +arm_set_interrupt_state: + mrs r2,CPSR @ read CPSR (Current Program Status Register) + teq r0,#0 + bicne r1,r2,#0xc0 @ disable IRQ and FIQ + orreq r1,r2,#0xc0 @ enable IRQ and FIQ + msr CPSR_c,r1 + tst r2,#0x80 + movne r0,#0 + moveq r0,#1 + bx lr + .endfunc + + .global cpu_get_current + @ int cpu_get_current(void)@ + @ get current CPU ID + .func cpu_get_current +cpu_get_current: + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #3 + BX lr + .endfunc @cpu_get_current()@ + + .global enable_neon_fpu + .func enable_neon_fpu +enable_neon_fpu: + /* set NSACR, both Secure and Non-secure access are allowed to NEON */ + MRC p15, 0, r0, c1, c1, 2 + ORR r0, r0, #(0x3<<10) @ enable fpu/neon + MCR p15, 0, r0, c1, c1, 2 + /* Set the CPACR for access to CP10 and CP11*/ + LDR r0, =0xF00000 + MCR p15, 0, r0, c1, c0, 2 + /* Set the FPEXC EN bit to enable the FPU */ + MOV r3, #0x40000000 + @VMSR FPEXC, r3 + MCR p10, 7, r3, c8, c0, 0 + .endfunc + + .global disable_strict_align_check + .func disable_strict_align_check +disable_strict_align_check: + /*Ray's note: disable strict alignment fault checking. + without disabling this, data abort will happen when accessing + the BPB structure of file system since it is packed.*/ + + push {r0, lr} + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(0x1<<1) @clear A bit of SCTLR + mcr p15, 0, r0, c1, c0, 0 + + pop {r0, pc} + .endfunc + + .global disable_L1_cache + .func disable_L1_cache +disable_L1_cache: + push {r0-r6, lr} + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(0x1<<12) + bic r0, r0, #(0x1<<11) + bic r0, r0, #(0x1<<2) + bic r0, r0, #(0x1<<0) + mcr p15, 0, r0, c1, c0, 0 + + pop {r0-r6, pc} + + .endfunc + + .global get_arm_private_peripheral_base + @ uint32_t get_arm_private_peripheral_base(void)@ + .func get_arm_private_peripheral_base +get_arm_private_peripheral_base: + + @ Get base address of private perpherial space + mrc p15, 4, r0, c15, c0, 0 @ Read periph base address + bx lr + + .endfunc @get_arm_private_peripheral_base()@ + +@ ------------------------------------------------------------ +@ TLB +@ ------------------------------------------------------------ + + .global arm_unified_tlb_invalidate + @ void arm_unified_tlb_invalidate(void)@ + .func arm_unified_tlb_invalidate +arm_unified_tlb_invalidate: + mov r0, #1 + mcr p15, 0, r0, c8, c7, 0 @ TLBIALL - Invalidate entire unified TLB + dsb + bx lr + .endfunc + + .global arm_unified_tlb_invalidate_is + @ void arm_unified_tlb_invalidate_is(void)@ + .func arm_unified_tlb_invalidate_is +arm_unified_tlb_invalidate_is: + mov r0, #1 + mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS - Invalidate entire unified TLB Inner Shareable + dsb + bx lr + .endfunc + +@ ------------------------------------------------------------ +@ Branch Prediction +@ ------------------------------------------------------------ + + .global arm_branch_prediction_enable + @ void arm_branch_prediction_enable(void) + .func arm_branch_prediction_enable +arm_branch_prediction_enable: + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR + orr r0, r0, #(1 << 11) @ Set the Z bit (bit 11) + mcr p15, 0,r0, c1, c0, 0 @ Write SCTLR + bx lr + .endfunc + + .global arm_branch_prediction_disable + @ void arm_branch_prediction_disable(void) + .func arm_branch_prediction_disable +arm_branch_prediction_disable: + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR + bic r0, r0, #(1 << 11) @ Clear the Z bit (bit 11) + mcr p15, 0,r0, c1, c0, 0 @ Write SCTLR + bx lr + .endfunc + + .global arm_branch_target_cache_invalidate + @ void arm_branch_target_cache_invalidate(void) + .func arm_branch_target_cache_invalidate +arm_branch_target_cache_invalidate: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 @ BPIALL - Invalidate entire branch predictor array + bx lr + .endfunc + + .global arm_branch_target_cache_invalidate_is + @ void arm_branch_target_cache_invalidate_is(void) + .func arm_branch_target_cache_invalidate_is +arm_branch_target_cache_invalidate_is: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 @ BPIALLIS - Invalidate entire branch predictor array Inner Shareable + bx lr + .endfunc + +@ ------------------------------------------------------------ +@ SCU +@ ------------------------------------------------------------ + + @ SCU offset from base of private peripheral space --> 0x000 + + .global scu_enable + @ void scu_enable(void) + @ Enables the SCU + .func scu_enable +scu_enable: + + mrc p15, 4, r0, c15, c0, 0 @ Read periph base address + + ldr r1, [r0, #0x0] @ Read the SCU Control Register + orr r1, r1, #0x1 @ Set bit 0 (The Enable bit) + str r1, [r0, #0x0] @ Write back modifed value + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_join_smp + @ void scu_join_smp(void) + @ Set this CPU as participating in SMP + .func scu_join_smp +scu_join_smp: + + @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR + orr r0, r0, #0x040 @ Set bit 6 + mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_leave_smp + @ void scu_leave_smp(void) + @ Set this CPU as NOT participating in SMP + .func scu_leave_smp +scu_leave_smp: + + @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR + bic r0, r0, #0x040 @ Clear bit 6 + mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_get_cpus_in_smp + @ unsigned int scu_get_cpus_in_smp(void) + @ The return value is 1 bit per core: + @ bit 0 - CPU 0 + @ bit 1 - CPU 1 + @ etc... + .func scu_get_cpus_in_smp +scu_get_cpus_in_smp: + + mrc p15, 4, r0, c15, c0, 0 @ Read periph base address + + ldr r0, [r0, #0x004] @ Read SCU Configuration register + mov r0, r0, lsr #4 @ Bits 7:4 gives the cores in SMP mode, shift then mask + and r0, r0, #0x0F + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_enable_maintenance_broadcast + @ void scu_enable_maintenance_broadcast(void) + @ Enable the broadcasting of cache & TLB maintenance operations + @ When enabled AND in SMP, broadcast all "inner sharable" + @ cache and TLM maintenance operations to other SMP cores + .func scu_enable_maintenance_broadcast +scu_enable_maintenance_broadcast: + mrc p15, 0, r0, c1, c0, 1 @ Read Aux Ctrl register + orr r0, r0, #0x01 @ Set the FW bit (bit 0) + mcr p15, 0, r0, c1, c0, 1 @ Write Aux Ctrl register + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_disable_maintenance_broadcast + @ void scu_disable_maintenance_broadcast(void) + @ Disable the broadcasting of cache & TLB maintenance operations + .func scu_disable_maintenance_broadcast +scu_disable_maintenance_broadcast: + mrc p15, 0, r0, c1, c0, 1 @ Read Aux Ctrl register + bic r0, r0, #0x01 @ Clear the FW bit (bit 0) + mcr p15, 0, r0, c1, c0, 1 @ Write Aux Ctrl register + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_secure_invalidate + @ void scu_secure_invalidate(unsigned int cpu, unsigned int ways) + @ cpu: 0x0=CPU 0 0x1=CPU 1 etc... + @ This function invalidates the SCU copy of the tag rams + @ for the specified core. typically only done at start-up. + @ Possible flow: + @ - Invalidate L1 caches + @ - Invalidate SCU copy of TAG RAMs + @ - Join SMP + .func scu_secure_invalidate +scu_secure_invalidate: + and r0, r0, #0x03 @ Mask off unused bits of CPU ID + mov r0, r0, lsl #2 @ Convert into bit offset (four bits per core) + + and r1, r1, #0x0F @ Mask off unused bits of ways + mov r1, r1, lsl r0 @ Shift ways into the correct CPU field + + mrc p15, 4, r2, c15, c0, 0 @ Read periph base address + + str r1, [r2, #0x0C] @ Write to SCU Invalidate All in Secure State + + bx lr + + .endfunc + +@ ------------------------------------------------------------ +@ End of cortexA9.s +@ ------------------------------------------------------------ + .end diff --git a/bsp/imx6ul/platform/cpu/gic.c b/bsp/imx6ul/platform/cpu/gic.c new file mode 100644 index 0000000000000000000000000000000000000000..2f140e02c64c20e1ddcca30c89d383b27263bc17 --- /dev/null +++ b/bsp/imx6ul/platform/cpu/gic.c @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include "gic.h" +#include "gic_registers.h" +#include "cortex_a.h" + +//////////////////////////////////////////////////////////////////////////////// +// Prototypes +//////////////////////////////////////////////////////////////////////////////// + +static inline gicd_t * gic_get_gicd(void); +static inline gicc_t * gic_get_gicc(void); +static inline uint32_t irq_get_register_offset(uint32_t irqID); +static inline uint32_t irq_get_bit_offset(uint32_t irqID); +static inline uint32_t irq_get_bit_mask(uint32_t irqID); + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +static inline gicd_t * gic_get_gicd(void) +{ + uint32_t base = get_arm_private_peripheral_base() + kGICDBaseOffset; + return (gicd_t *)base; +} + +static inline gicc_t * gic_get_gicc(void) +{ + uint32_t base = get_arm_private_peripheral_base() + kGICCBaseOffset; + return (gicc_t *)base; +} + +static inline uint32_t irq_get_register_offset(uint32_t irqID) +{ + return irqID / 32; +} + +static inline uint32_t irq_get_bit_offset(uint32_t irqID) +{ + return irqID & 0x1f; +} + +static inline uint32_t irq_get_bit_mask(uint32_t irqID) +{ + return 1 << irq_get_bit_offset(irqID); +} + +void gic_enable(bool enableIt) +{ + gicd_t * gicd = gic_get_gicd(); + + if (enableIt) + { + // Enable both secure and non-secure. + gicd->CTLR |= kBM_GICD_CTLR_EnableGrp0 | kBM_GICD_CTLR_EnableGrp1; + } + else + { + // Clear the enable bits. + gicd->CTLR &= ~(kBM_GICD_CTLR_EnableGrp0 | kBM_GICD_CTLR_EnableGrp1); + } +} + +void gic_set_irq_security(uint32_t irqID, bool isSecure) +{ + gicd_t * gicd = gic_get_gicd(); + + uint32_t reg = irq_get_register_offset(irqID); + uint32_t mask = irq_get_bit_mask(irqID); + + uint32_t value = gicd->IGROUPRn[reg]; + if (!isSecure) + { + value &= ~mask; + } + else + { + value |= mask; + } + gicd->IGROUPRn[reg] = value; +} + +void gic_enable_irq(uint32_t irqID, bool isEnabled) +{ + gicd_t * gicd = gic_get_gicd(); + + uint32_t reg = irq_get_register_offset(irqID); + uint32_t mask = irq_get_bit_mask(irqID); + + // Select set-enable or clear-enable register based on enable flag. + if (isEnabled) + { + gicd->ISENABLERn[reg] = mask; + } + else + { + gicd->ICENABLERn[reg] = mask; + } +} + +void gic_set_irq_priority(uint32_t ID, uint32_t priority) +{ + gicd_t * gicd = gic_get_gicd(); + + // Update the priority register. The priority registers are byte accessible, and the register + // struct has the priority registers as a byte array, so we can just index directly by the + // interrupt ID. + gicd->IPRIORITYRn[ID] = priority & 0xff; +} + +void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt) +{ + // Make sure the CPU number is valid. + assert(cpuNumber <= 7); + + gicd_t * gicd = gic_get_gicd(); + uint8_t cpuMask = 1 << cpuNumber; + + // Like the priority registers, the target registers are byte accessible, and the register + // struct has the them as a byte array, so we can just index directly by the + // interrupt ID. + if (enableIt) + { + gicd->ITARGETSRn[irqID] |= (cpuMask & 0xff); + } + else + { + gicd->ITARGETSRn[irqID] &= ~(cpuMask & 0xff); + } +} + +void gic_send_sgi(uint32_t irqID, uint32_t target_list, uint32_t filter_list) +{ + gicd_t * gicd = gic_get_gicd(); + + gicd->SGIR = (filter_list << kBP_GICD_SGIR_TargetListFilter) + | (target_list << kBP_GICD_SGIR_CPUTargetList) + | (irqID & 0xf); +} + +void gic_cpu_enable(bool enableIt) +{ + gicc_t * gicc = gic_get_gicc(); + + if (enableIt) + { + gicc->CTLR |= kBM_GICC_CTLR_EnableS | kBM_GICC_CTLR_EnableNS; + } + else + { + gicc->CTLR &= ~(kBM_GICC_CTLR_EnableS | kBM_GICC_CTLR_EnableNS); + } +} + +void gic_set_cpu_priority_mask(uint32_t priority) +{ + gicc_t * gicc = gic_get_gicc(); + gicc->PMR = priority & 0xff; +} + +uint32_t gic_read_irq_ack(void) +{ + gicc_t * gicc = gic_get_gicc(); + return gicc->IAR; +} + +void gic_write_end_of_irq(uint32_t irqID) +{ + gicc_t * gicc = gic_get_gicc(); + gicc->EOIR = irqID; +} + +void gic_init(void) +{ + gicd_t * gicd = gic_get_gicd(); + + // First disable the distributor. + gic_enable(false); + + // Clear all pending interrupts. + int i; + for (i = 0; i < 32; ++i) + { + gicd->ICPENDRn[i] = 0xffffffff; + } + + // Set all interrupts to secure. + for (i = 0; i < 8; ++i) + { + gicd->IGROUPRn[i] = 0; + } + + // Init the GIC CPU interface. + gic_init_cpu(); + + // Now enable the distributor. + gic_enable(true); +} + +void gic_init_cpu(void) +{ + // Init the GIC CPU interface. + gic_set_cpu_priority_mask(0xff); + + // Disable preemption. + gicc_t * gicc = gic_get_gicc(); + gicc->BPR = 7; + + // Enable signaling the CPU. + gic_cpu_enable(true); +} + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/cpu/gic_registers.h b/bsp/imx6ul/platform/cpu/gic_registers.h new file mode 100644 index 0000000000000000000000000000000000000000..20d41716f29e586293594432cd94e2a7b651cfca --- /dev/null +++ b/bsp/imx6ul/platform/cpu/gic_registers.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "sdk_types.h" + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Offsets to the GIC registers. +enum _gic_base_offsets +{ + kGICDBaseOffset = 0x1000, //!< GIC distributor offset. +#if defined(CHIP_MX6UL) + kGICCBaseOffset = 0x2000 //!< GIC CPU interface offset. +#else + kGICCBaseOffset = 0x100 //!< GIC CPU interface offset. +#endif +}; + +//! @brief GIC distributor registers. +//! +//! Uses the GICv2 register names, but does not include GICv2 registers. +//! +//! The IPRIORITYRn and ITARGETSRn registers are byte accessible, so their types are uint8_t +//! instead of uint32_t to reflect this. These members are indexed directly with the interrupt +//! number. +struct _gicd_registers +{ + uint32_t CTLR; //!< Distributor Control Register. + uint32_t TYPER; //!< Interrupt Controller Type Register. + uint32_t IIDR; //!< Distributor Implementer Identification Register. + uint32_t _reserved0[29]; + uint32_t IGROUPRn[8]; //!< Interrupt Group Registers. + uint32_t _reserved1[24]; + uint32_t ISENABLERn[32]; //!< Interrupt Set-Enable Registers. + uint32_t ICENABLERn[32]; //!< Interrupt Clear-Enable Registers. + uint32_t ISPENDRn[32]; //!< Interrupt Set-Pending Registers. + uint32_t ICPENDRn[32]; //!< Interrupt Clear-Pending Registers. + uint32_t ICDABRn[32]; //!< Active Bit Registers. + uint32_t _reserved2[32]; + uint8_t IPRIORITYRn[255 * sizeof(uint32_t)]; //!< Interrupt Priority Registers. (Byte accessible) + uint32_t _reserved3; + uint8_t ITARGETSRn[255 * sizeof(uint32_t)]; //!< Interrupt Processor Targets Registers. (Byte accessible) + uint32_t _reserved4; + uint32_t ICFGRn[64]; //!< Interrupt Configuration Registers. + uint32_t _reserved5[128]; + uint32_t SGIR; //!< Software Generated Interrupt Register +}; + +//! @brief Bitfields constants for the GICD_CTLR register. +enum _gicd_ctlr_fields +{ + kBM_GICD_CTLR_EnableGrp1 = (1 << 1), + kBM_GICD_CTLR_EnableGrp0 = (1 << 0) +}; + +//! @brief Bitfields constants for the GICD_SGIR register. +enum _gicd_sgir_fields +{ + kBP_GICD_SGIR_TargetListFilter = 24, + kBM_GICD_SGIR_TargetListFilter = (0x3 << kBP_GICD_SGIR_TargetListFilter), + + kBP_GICD_SGIR_CPUTargetList = 16, + kBM_GICD_SGIR_CPUTargetList = (0xff << kBP_GICD_SGIR_CPUTargetList), + + kBP_GICD_SGIR_NSATT = 15, + kBM_GICD_SGIR_NSATT = (1 << kBP_GICD_SGIR_NSATT), + + kBP_GICD_SGIR_SGIINTID = 0, + kBM_GICD_SGIR_SGIINTID = 0xf +}; + +//! @brief GIC CPU interface registers. +//! +//! Uses the GICv2 register names. Does not include GICv2 registers. +struct _gicc_registers +{ + uint32_t CTLR; //!< CPU Interface Control Register. + uint32_t PMR; //!< Interrupt Priority Mask Register. + uint32_t BPR; //!< Binary Point Register. + uint32_t IAR; //!< Interrupt Acknowledge Register. + uint32_t EOIR; //!< End of Interrupt Register. + uint32_t RPR; //!< Running Priority Register. + uint32_t HPPIR; //!< Highest Priority Pending Interrupt Register. + uint32_t ABPR; //!< Aliased Binary Point Register. (only visible with a secure access) + uint32_t _reserved[56]; + uint32_t IIDR; //!< CPU Interface Identification Register. +}; + +//! @brief Bitfields constants for the GICC_CTLR register. +enum _gicc_ctlr_fields +{ + kBP_GICC_CTLR_EnableS = 0, + kBM_GICC_CTLR_EnableS = (1 << 0), + + kBP_GICC_CTLR_EnableNS = 1, + kBM_GICC_CTLR_EnableNS = (1 << 1), + + kBP_GICC_CTLR_AckCtl = 2, + kBM_GICC_CTLR_AckCtl = (1 << 2), + + kBP_GICC_CTLR_FIQEn = 3, + kBM_GICC_CTLR_FIQEn = (1 << 3), + + kBP_GICC_CTLR_SBPR = 4, + kBM_GICC_CTLR_SBPR = (1 << 4) +}; + +//! @brier Type for the GIC distributor registers. +typedef volatile struct _gicd_registers gicd_t; + +//! @brier Type for the GIC CPU interface registers. +typedef volatile struct _gicc_registers gicc_t; + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/cpu/mmu.c b/bsp/imx6ul/platform/cpu/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..0cf20c9942bc484e444fcade8238609c0c95ca8d --- /dev/null +++ b/bsp/imx6ul/platform/cpu/mmu.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file mmu.c + * @brief System memory arangement. + */ +#include "cortex_a.h" +#include "mmu.h" +#include "arm_cp_registers.h" + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Size in bytes of the first-level page table. +#define MMU_L1_PAGE_TABLE_SIZE (16 * 1024) + +//! @brief First-level 1MB section descriptor entry. +typedef union mmu_l1_section { + uint32_t u; + struct { + uint32_t id:2; //!< ID + uint32_t b:1; //!< Bufferable + uint32_t c:1; //!< Cacheable + uint32_t xn:1; //!< Execute-not + uint32_t domain:4; //!< Domain + uint32_t _impl_defined:1; //!< Implementation defined, should be zero. + uint32_t ap1_0:2; //!< Access permissions AP[1:0] + uint32_t tex:3; //!< TEX remap + uint32_t ap2:1; //!< Access permissions AP[2] + uint32_t s:1; //!< Shareable + uint32_t ng:1; //!< Not-global + uint32_t _zero:1; //!< Should be zero. + uint32_t ns:1; //!< Non-secure + uint32_t address:12; //!< Physical base address + }; +} mmu_l1_section_t; + +enum { + kMMU_L1_Section_ID = 2, //!< ID value for a 1MB section first-level entry. + kMMU_L1_Section_Address_Shift = 20 //!< Bit offset of the physical base address field. +}; + +//////////////////////////////////////////////////////////////////////////////// +// Externs +//////////////////////////////////////////////////////////////////////////////// + +extern char __l1_page_table_start; + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +void mmu_enable() +{ + // invalidate all tlb + arm_unified_tlb_invalidate(); + + // read SCTLR + uint32_t sctlr; + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + // set MMU enable bit + sctlr |= BM_SCTLR_M; + + // write modified SCTLR + _ARM_MCR(15, 0, sctlr, 1, 0, 0); +} + +void mmu_disable() +{ + // read current SCTLR + uint32_t sctlr; + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + // clear MMU enable bit + sctlr &=~ BM_SCTLR_M; + + // write modified SCTLR + _ARM_MCR(15, 0, sctlr, 1, 0, 0); +} + +void mmu_init() +{ + // Get the L1 page table base address. + uint32_t * table = (uint32_t *)&__l1_page_table_start; + uint32_t share_attr = kShareable; + + // write table address to TTBR0 + _ARM_MCR(15, 0, table, 2, 0, 0); + + // set Client mode for all Domains + uint32_t dacr = 0x55555555; + _ARM_MCR(15, 0, dacr, 3, 0, 0); // MCR p15, 0, , c3, c0, 0 ; Write DACR + + // Clear the L1 table. + bzero(table, MMU_L1_PAGE_TABLE_SIZE); + + // Create default mappings. + mmu_map_l1_range(0x00000000, 0x00000000, 0x00900000, kStronglyOrdered, kShareable, kRWAccess); // ROM and peripherals + mmu_map_l1_range(0x00900000, 0x00900000, 0x00100000, kStronglyOrdered, kShareable, kRWAccess); // OCRAM + mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kStronglyOrdered, kShareable, kRWAccess); // More peripherals + + // Check whether SMP is enabled. If it is not, then we don't want to make SDRAM shareable. + uint32_t actlr = 0x0; + _ARM_MRC(15, 0, actlr, 1, 0, 1); + if (actlr & BM_ACTLR_SMP) + { + share_attr = kShareable; + } + else + { + share_attr = kNonshareable; + } + +#if defined(CHIP_MX6DQ) || defined(CHIP_MX6SDL) + mmu_map_l1_range(0x10000000, 0x10000000, 0x80000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 2GB DDR +#elif defined(CHIP_MX6SL) || defined(CHIP_MX6UL) + mmu_map_l1_range(0x80000000, 0x80000000, 0x40000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 1GB DDR +#else +#error Unknown chip type! +#endif +} + +void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access) +{ + register mmu_l1_section_t entry; + entry.u = 0; + + // Set constant attributes. + entry.id = kMMU_L1_Section_ID; + entry.xn = 0; // Allow execution + entry.domain = 0; // Domain 0 + entry.ng = 0; // Global + entry.ns = 0; // Secure + + // Set attributes based on the selected memory type. + switch (memoryType) + { + case kStronglyOrdered: + entry.c = 0; + entry.b = 0; + entry.tex = 0; + entry.s = 1; // Ignored + break; + case kDevice: + if (isShareable) + { + entry.c = 0; + entry.b = 1; + entry.tex = 0; + entry.s = 1; // Ignored + } + else + { + entry.c = 0; + entry.b = 0; + entry.tex = 2; + entry.s = 0; // Ignored + } + break; + case kOuterInner_WB_WA: + entry.c = 1; + entry.b = 1; + entry.tex = 1; + entry.s = isShareable; + break; + case kOuterInner_WT: + entry.c = 1; + entry.b = 0; + entry.tex = 0; + entry.s = isShareable; + break; + case kNoncacheable: + entry.c = 0; + entry.b = 0; + entry.tex = 1; + entry.s = isShareable; + break; + } + + // Set attributes from specified access mode. + switch (access) + { + case kNoAccess: + entry.ap2 = 0; + entry.ap1_0 = 0; + break; + case kROAccess: + entry.ap2 = 1; + entry.ap1_0 = 3; + break; + case kRWAccess: + entry.ap2 = 0; + entry.ap1_0 = 3; + break; + } + + // Get the L1 page table base address. + uint32_t * table = (uint32_t *)&__l1_page_table_start; + + // Convert addresses to 12-bit bases. + uint32_t vbase = va >> kMMU_L1_Section_Address_Shift; + uint32_t pbase = pa >> kMMU_L1_Section_Address_Shift; + uint32_t entries = length >> kMMU_L1_Section_Address_Shift; + + // Fill in L1 page table entries. + for (; entries > 0; ++pbase, ++vbase, --entries) + { + entry.address = pbase; + table[vbase] = entry.u; + } + + // Invalidate TLB + arm_unified_tlb_invalidate(); +} + +bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress) +{ + uint32_t pa = 0; + + // VA to PA translation with privileged read permission check + _ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 0); + + // Read PA register + _ARM_MRC(15, 0, pa, 7, 4, 0); + + // First bit of returned value is Result of conversion (0 is successful translation) + if (pa & 1) + { + // We can try write permission also + // VA to PA translation with privileged write permission check + _ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 1); + + // Read PA register + _ARM_MRC(15, 0, pa, 7, 4, 0); + + // First bit of returned value is Result of conversion (0 is successful translation) + if (pa & 1) + { + return false; + } + } + + if (physicalAddress) + { + // complete address returning base + offset + pa = (pa & 0xfffff000) | (virtualAddress & 0x00000fff); + *physicalAddress = pa; + } + + return true; +} + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/cpu/mmu.h b/bsp/imx6ul/platform/cpu/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..961c17f5412868411c4497d43880fa700df62d51 --- /dev/null +++ b/bsp/imx6ul/platform/cpu/mmu.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +//! @addtogroup diag_mmu +//! @{ + +/*! + * @file mmu.h + * @brief System memory arrangement. + */ + +#ifndef _MMU_H_ +#define _MMU_H_ + +#include "sdk.h" + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Memory region attributes. +typedef enum _mmu_memory_type +{ + kStronglyOrdered, + kDevice, + kOuterInner_WB_WA, + kOuterInner_WT, + kNoncacheable, +} mmu_memory_type_t; + +//! @brief Memory region shareability options. +typedef enum _mmu_shareability +{ + kShareable = 1, + kNonshareable = 0 +} mmu_shareability_t; + +//! @brief Access permissions for a memory region. +typedef enum _mmu_access +{ + kNoAccess, + kROAccess, + kRWAccess +} mmu_access_t; + +//////////////////////////////////////////////////////////////////////////////// +// Prototypes +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable the MMU. + * + * The L1 page tables and MMU settings must have already been configured by + * calling mmu_init() before the MMU is enabled. + */ +void mmu_enable(); + +/*! + * @brief Disable the MMU. + */ +void mmu_disable(); + +/*! + * @brief Set up the default first-level page table. + * + * Initializes the L1 page table with the following regions: + * - 0x00000000...0x00900000 : ROM and peripherals, strongly-ordered + * - 0x00900000...0x00a00000 : OCRAM, strongly-ordered + * - For MX6DQ or MX6SDL: 0x10000000...0x90000000 : DDR, normal, outer inner, write-back, write-allocate + * - For MX6SL: 0x80000000...0xc0000000 : DDR, normal, outer inner, write-back, write-allocate + * + * If the CPU is participating in SMP, then the DDR regions are made shareable. Otherwise they + * are marked as non-shareable. + * + * The TTBR0 register is set to the base of the L1 table. + * + * All memory domains are configured to allow client access. However, note that only domain 0 is + * used by mmu_map_l1_range(). + */ +void mmu_init(); + +/*! + * @brief Maps a range of memory in the first-level page table. + * + * Entries in the first-level page table are filled in for the range of virtual addresses + * starting at @a va and continuing for @a length bytes. These virtual addreses are mapped + * to the physical addresses starting at @a pa and continuing for @a length bytes. All table + * entries for the range of mapped memory have the same attributes, which are selected with + * the @a memoryType, @a isShareable, and @a access parameters. + * + * @param pa The base physical address of the range to which the virtual address will be mapped. + * @param va The base virtual address of the range. + * @param length The size of the range to be mapped, in bytes. This value must be divisible by 1MB. + * @param memoryType The type of the memory region. This controls caching, buffering, ordering of + * memory accesses, and other attributes of the region. + * @param isShareable The shareability of the physical memory. Ignored for strongly-ordered memory. + * @param access Access permissions. + */ +void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access); + +/*! + * @brief Convert virtual address to physical. + * + * First attempts a priviledged read translation for the current security mode. If that fails, + * a priviledged write translation, also for the current security mode, is attempted. If this + * second attempt at translation fails, then false will be returned. + * + * @param virtualAddress Virtual address to convert to a physical address. + * @param[out] physicalAddress This parameter is filled in with the physical address corresponding + * to the virtual address passed in @a virtualAddress. + * @retval true The address returned through @a physicalAddress is valid. + * @retval false The conversion failed for some reason. + */ +bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress); + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif // _MMU_H_ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// + diff --git a/bsp/imx6ul/platform/drivers/epit.c b/bsp/imx6ul/platform/drivers/epit.c new file mode 100644 index 0000000000000000000000000000000000000000..efc88c7865adea2aae21c1774ceae40eb7791fc4 --- /dev/null +++ b/bsp/imx6ul/platform/drivers/epit.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file epit.c + * @brief EPIT driver source file. + * + * @ingroup diag_timer + */ + +#include "epit.h" + +#include "imx_timer.h" +#include "interrupt.h" +#include "ccm_pll.h" +#include "registers/regsepit.h" + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +void epit_reload_counter(uint32_t instance, uint32_t load_val) +{ + // set the load register especially if RLD=reload_mode=SET_AND_FORGET=1 + HW_EPIT_LR_WR(instance, load_val); +} + +uint32_t epit_get_counter_value(uint32_t instance) +{ + return HW_EPIT_CNR_RD(instance); +} + +void epit_set_compare_event(uint32_t instance, uint32_t compare_val) +{ + HW_EPIT_CMPR_WR(instance, compare_val); +} + +uint32_t epit_get_compare_event(uint32_t instance) +{ + uint32_t status_register; + + // get the status + status_register = HW_EPIT_SR_RD(instance); + + // clear it if found set + if (status_register & BM_EPIT_SR_OCIF) + { + HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF); + } + + // return the read value before the bit was cleared + return status_register & BM_EPIT_SR_OCIF; +} + +void epit_counter_disable(uint32_t instance) +{ + /* temporary workaround for the discovered issue when disabling the + * counter during end of count/reload/set compare flag ??. + * Set to the max value so that it ensures that the counter couldn't + * reach 0 when it is disabled. + */ + HW_EPIT_LR_WR(instance, 0xFFFFFFFF); + + // disable the counter + HW_EPIT_CR_CLR(instance, BM_EPIT_CR_EN); + + // ensure to leave the counter in a proper state + // by disabling the output compare interrupt + HW_EPIT_CR_CLR(instance, BM_EPIT_CR_OCIEN); + + // and clearing possible remaining compare event + HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF); +} + +void epit_counter_enable(uint32_t instance, uint32_t load_val, uint32_t irq_mode) +{ + // set the load register especially if RLD=reload_mode=SET_AND_FORGET=1 + // and if the value is different from 0 which is the lowest counter value + if (load_val != 0) + { + HW_EPIT_LR_WR(instance, load_val); + } + + // ensure to start the counter in a proper state + // by clearing possible remaining compare event + HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF); + + // set the mode when the output compare event occur: IRQ or polling + if (irq_mode == IRQ_MODE) + { + HW_EPIT_CR_SET(instance, BM_EPIT_CR_OCIEN); + } + else + { + // polling + HW_EPIT_CR_CLR(instance, BM_EPIT_CR_OCIEN); + } + + // finally, enable the counter + HW_EPIT_CR_SET(instance, BM_EPIT_CR_EN); +} + +void epit_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool enableIt) +{ + uint32_t irq_id = EPIT_IRQS(instance); + + if (enableIt) + { + // register the IRQ sub-routine + register_interrupt_routine(irq_id, irq_subroutine); + + // enable the IRQ + enable_interrupt(irq_id, CPU_0, 0); + } + else + { + // disable the IRQ + disable_interrupt(irq_id, CPU_0); + } +} + +void epit_init(uint32_t instance, uint32_t clock_src, uint32_t prescaler, + uint32_t reload_mode, uint32_t load_val, uint32_t low_power_mode) +{ + uint32_t control_reg_tmp = 0; + uint32_t base = REGS_EPIT_BASE(instance); + + // enable the source clocks to the EPIT port + clock_gating_config(base, CLOCK_ON); + + // start with a known state by disabling and reseting the module + HW_EPIT_CR_WR(instance, BM_EPIT_CR_SWR); + + // wait for the reset to complete + while ((HW_EPIT_CR(instance).B.SWR) != 0) ; + + // set the reference source clock for the counter + control_reg_tmp |= BF_EPIT_CR_CLKSRC(clock_src); + + // set the counter clock prescaler value - 0 to 4095 + control_reg_tmp |= BF_EPIT_CR_PRESCALAR(prescaler-1); + + // set the reload mode + if (reload_mode == SET_AND_FORGET) + { + control_reg_tmp |= BM_EPIT_CR_RLD; + } + + // set behavior for low power mode + if (low_power_mode & WAIT_MODE_EN) + { + control_reg_tmp |= BM_EPIT_CR_WAITEN; + } + if (low_power_mode & STOP_MODE_EN) + { + control_reg_tmp |= BM_EPIT_CR_STOPEN; + } + + // make the counter start from a known value when enabled, this is loaded from + // EPITLR register if RLD=reload_mode=1 or 0xFFFFFFFF if RLD=reload_mode=0 + control_reg_tmp |= BM_EPIT_CR_IOVW | BM_EPIT_CR_ENMOD; + + // finally write the control register + HW_EPIT_CR_WR(instance, control_reg_tmp); + + // initialize the load register especially if RLD=reload_mode=SET_AND_FORGET=1 + // and if the value is different from 0 which is the lowest counter value + if (load_val != 0) + { + HW_EPIT_LR_WR(instance, load_val); + } +} + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/drivers/gpt.c b/bsp/imx6ul/platform/drivers/gpt.c new file mode 100644 index 0000000000000000000000000000000000000000..558bf03104f68e77bca06d44c631aeab39494c7b --- /dev/null +++ b/bsp/imx6ul/platform/drivers/gpt.c @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file gpt.c + * @brief GPT driver source file. + * + * @ingroup diag_timer + */ + +#include "sdk.h" +#include "gpt.h" + +#include "imx_timer.h" +#include "registers/regsgpt.h" +#include "interrupt.h" +#include "ccm_pll.h" + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +static inline void gpt_clear_all_events(void) +{ + HW_GPT_SR_WR(kGPTAllEvents); +} + +uint32_t gpt_get_rollover_event(void) +{ + // clear it if found set + if (HW_GPT_SR.B.ROV) + { + HW_GPT_SR_WR(BM_GPT_SR_ROV); + return kGPTRollover; + } + + // return the read value before the bit was cleared + return 0; +} + +uint32_t gpt_get_capture_event(uint8_t flag, uint32_t * capture_val) +{ + // get the capture status bit + flag &= kGPTInputCapture1 | kGPTInputCapture2; + uint32_t status_register = HW_GPT_SR_RD() & flag; + + // Read the captured timer value. + if (capture_val) + { + if (status_register == kGPTInputCapture1) + { + *(uint32_t *) capture_val = HW_GPT_ICR1.B.CAPT; + } + else if (status_register == kGPTInputCapture2) + { + *(uint32_t *) capture_val = HW_GPT_ICR2.B.CAPT; + } + } + + // Clear the flag. + HW_GPT_SR_WR(status_register); + + // return the read value before the bit was cleared + return status_register; +} + +void gpt_set_capture_event(uint8_t cap_input, uint8_t cap_input_mode) +{ + // set the new input mode + switch (cap_input) + { + case kGPTInputCapture1: + HW_GPT_CR.B.IM1 = cap_input_mode; + break; + + case kGPTInputCapture2: + HW_GPT_CR.B.IM2 = cap_input_mode; + break; + } +} + +uint32_t gpt_get_compare_event(uint8_t flag) +{ + // get the active compare flags + flag &= kGPTOutputCompare1 | kGPTOutputCompare2 | kGPTOutputCompare3; + uint32_t status_register = HW_GPT_SR_RD() & flag; + + // clear flags which are active + if (status_register) + { + HW_GPT_SR_WR(status_register); + } + + // return the read value before the flags were cleared + return status_register; +} + +void gpt_set_compare_event(uint8_t cmp_output, uint8_t cmp_output_mode, uint32_t cmp_value) +{ + // set the value to compare with + switch (cmp_output) + { + case kGPTOutputCompare1: + BW_GPT_CR_OM1(cmp_output_mode); + HW_GPT_OCR1_WR(cmp_value); + break; + + case kGPTOutputCompare2: + BW_GPT_CR_OM2(cmp_output_mode); + HW_GPT_OCR2_WR(cmp_value); + break; + + case kGPTOutputCompare3: + BW_GPT_CR_OM3(cmp_output_mode); + HW_GPT_OCR3_WR(cmp_value); + break; + } +} + +void gpt_counter_disable(void) +{ + // disable the counter + HW_GPT_CR.B.EN = 0; + + // ensure to leave the counter in a proper state by disabling the interrupt sources + HW_GPT_IR_WR(0); + + // and by clearing possible remaining events + gpt_clear_all_events(); +} + +void gpt_counter_enable(uint32_t irq_mode) +{ + // ensure to start the counter in a proper state by clearing possible remaining events + gpt_clear_all_events(); + + // enable the interrupts or clear the register for polling + HW_GPT_IR_WR(irq_mode & kGPTAllEvents); + + // finally, enable the counter + HW_GPT_CR.B.EN = 1; +} + +void gpt_setup_interrupt(void (*irq_subroutine)(void), bool enableIt) +{ + uint32_t irq_id = IMX_INT_GPT; + + if (enableIt) + { + // register the IRQ sub-routine + register_interrupt_routine(irq_id, irq_subroutine); + + // enable the IRQ + enable_interrupt(irq_id, CPU_0, 0); + } + else + { + // disable the IRQ + disable_interrupt(irq_id, CPU_0); + } +} + +void gpt_init(uint32_t clock_src, uint32_t prescaler, uint32_t counter_mode, uint32_t low_power_mode) +{ + uint32_t control_reg_tmp = 0; + uint32_t base = GPT_BASE_ADDR; + + // enable the source clocks to the GPT port + clock_gating_config(base, CLOCK_ON); + + // start with a known state by disabling and reseting the module + HW_GPT_CR_WR(BM_GPT_CR_SWR); + + // wait for the reset to complete + while (HW_GPT_CR.B.SWR != 0) ; + + // set the reference source clock for the counter + if (clock_src == CLKSRC_CKIL) + { + // CKIL source is 0x4 for GPT but 0x3 for EPIT + clock_src++; + } + control_reg_tmp |= BF_GPT_CR_CLKSRC(clock_src); + + // the prescaler can be changed at any time, and + // this affects the output clock immediately + HW_GPT_PR_WR(BF_GPT_PR_PRESCALER(prescaler - 1)); + + // set the counter mode + control_reg_tmp |= BF_GPT_CR_FRR(counter_mode); + + // set behavior for low power mode + if (low_power_mode & WAIT_MODE_EN) + { + control_reg_tmp |= BM_GPT_CR_WAITEN; + } + if (low_power_mode & STOP_MODE_EN) + { + control_reg_tmp |= BM_GPT_CR_STOPEN; + } + + // specify from where the counter starts to count when enabled + // this code makes it start from 0 + control_reg_tmp |= BM_GPT_CR_ENMOD; + + // finally write the control register + HW_GPT_CR_WR(control_reg_tmp); +} + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/drivers/imx_i2c.c b/bsp/imx6ul/platform/drivers/imx_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..a862bc6b19e19545135a2b83674f10d167fb8152 --- /dev/null +++ b/bsp/imx6ul/platform/drivers/imx_i2c.c @@ -0,0 +1,540 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file imx_i2c.c + * @brief Main driver for the I2C controller. It initializes the controller + * and handles the master mode. + * + * @ingroup diag_i2c + */ + +#include "sdk.h" +#include "imx_i2c.h" +#include "imx_i2c_internal.h" +#include "registers/regsi2c.h" +#include "ccm_pll.h" +#include "interrupt.h" + +//! Set this macro to 1 to enable tracing of data send and receive. +#define TRACE_I2C 0 + +//! @brief Get the irq id of I2C by instance number. +//! @param x I2C instance number, from 1 through 3. +#define I2C_IRQS(x) ( (x) == HW_I2C1 ? IMX_INT_I2C1 : (x) == HW_I2C2 ? IMX_INT_I2C2 : (x) == HW_I2C3 ? IMX_INT_I2C3 : 0xFFFFFFFF) + +//////////////////////////////////////////////////////////////////////////////// +// Constants +//////////////////////////////////////////////////////////////////////////////// + +static const uint16_t i2c_freq_div[50][2] = { + { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, + { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, + { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, + { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, + { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, + { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, + { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, + { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, + { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, + { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, + { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, + { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, + { 3072, 0x1E }, { 3840, 0x1F } +}; + +//////////////////////////////////////////////////////////////////////////////// +// Prototypes +//////////////////////////////////////////////////////////////////////////////// + +static inline int is_bus_free(unsigned int instance); +static int wait_till_busy(uint32_t instance); +static inline void imx_send_stop(unsigned int instance); +static int wait_op_done(uint32_t instance, int is_tx); +static int tx_byte(uint8_t * data, uint32_t instance); +static int rx_bytes(uint8_t * data, uint32_t instance, int sz); +static void set_i2c_clock(uint32_t instance, uint32_t baud); + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +unsigned i2c_get_request_instance(const imx_i2c_request_t * rq) +{ + // First see if there device info is set. + if (rq->device) + { + // Use the instance number in the device info. + return rq->device->port; + } + + // Check if the ctl_addr is within the range of instances. + if (rq->ctl_addr >= 1 && rq->ctl_addr <= HW_I2C_INSTANCE_COUNT) + { + // Valid instance number, so use it directly. + return rq->ctl_addr; + } + else + { + // Not a valid instance, so treat it as a base address. + return REGS_I2C_INSTANCE(rq->ctl_addr); + } +} + +/*! + * @brief Loop status register for IBB to go 0. + * + * The loop also breaks on max number of iterations. + * + * @param instance Instance number of the I2C module. + * + * @return 0 if successful; -1 otherwise + */ +static inline int is_bus_free(unsigned int instance) +{ + int i = WAIT_RXAK_LOOPS; + + while (HW_I2C_I2SR(instance).B.IBB && (--i > 0)); + + if (i <= 0) { + debug_printf("Error: I2C Bus not free!\n"); + return -1; + } + + return 0; +} + +/*! + * @brief Loop status register for IBB to go 1. + * + * It breaks the loop if there's an arbitration lost occurred or the maximum + * number of iterations has been reached. + * + * @param instance Instance number of the I2C module. + * + * @return 0 if successful; -1 otherwise + */ +static int wait_till_busy(uint32_t instance) +{ + int i = WAIT_BUSY_LOOPS; + + while (!HW_I2C_I2SR(instance).B.IBB && (--i > 0)) { + if (HW_I2C_I2SR(instance).B.IAL) { + debug_printf("Error: arbitration lost!\n"); + return -1; + } + } + + if (i <= 0) { + debug_printf("I2C Error: timeout in %s; %d\n", __FUNCTION__, __LINE__); + return -1; + } + + return 0; +} + +/*! + * Generates a STOP signal, called by rx and tx routines + * + * @param instance Instance number of the I2C module. + * + * @return none + */ +static inline void imx_send_stop(unsigned int instance) +{ + HW_I2C_I2CR(instance).B.MSTA = 0; +} + +/*! + * @brief Wait for operation done. + * + * This function loops until we get an interrupt. On timeout it returns -1. + * It reports arbitration lost if IAL bit of I2SR register is set + * Clears the interrupt + * If operation is transfer byte function will make sure we received an ack + * + * @param instance Instance number of the I2C module. + * @param is_tx Pass 1 for transfering, 0 for receiving + * + * @return 0 if successful; negative integer otherwise + */ +static int wait_op_done(uint32_t instance, int is_tx) +{ + hw_i2c_i2sr_t v; + int i = WAIT_RXAK_LOOPS; + + // Loop until we get an interrupt + do { + v.U = HW_I2C_I2SR_RD(instance); + } while (!v.B.IIF && (--i > 0)); + + // If timeout error occurred return error + if (i <= 0) { + debug_printf("I2C Error: timeout unexpected\n"); + return -1; + } + + // Clear the interrupts + HW_I2C_I2SR_WR(instance, 0); + + // Check for arbitration lost + if (v.B.IAL) { + debug_printf("Error %d: Arbitration lost\n", __LINE__); + return ERR_ARB_LOST; + } + + // Check for ACK received in transmit mode + if (is_tx) { + if (v.B.RXAK) { + // No ACK received, generate STOP by clearing MSTA bit + debug_printf("Error %d: no ack received\n", __LINE__); + + // Generate a STOP signal + imx_send_stop(instance); + return ERR_NO_ACK; + } + } + + return 0; +} + +/*! + * @brief Implements a loop to send a byte to I2C slave. + * + * For master transmit. Always expect a RXAK signal to be set! + * + * @param data return buffer for data + * @param instance Instance number of the I2C module. + * + * @return 0 if successful; -1 otherwise + */ +static int tx_byte(uint8_t * data, uint32_t instance) +{ +#if TRACE_I2C + debug_printf("%s(data=0x%02x, instance=%d)\n", __FUNCTION__, *data, instance); +#endif // TRACE_I2C + + // clear both IAL and IIF bits + HW_I2C_I2SR_WR(instance, 0); + + // write to data register + HW_I2C_I2DR_WR(instance, *data); + + // wait for transfer of byte to complete + return wait_op_done(instance, 1); +} + +/*! + * @brief Implements a loop to receive bytes from I2C slave. + * + * For master receive. + * + * @param data return buffer for data + * @param instance Instance number of the I2C module. + * @param sz number of bytes to receive + * + * @return 0 if successful; -1 otherwise + */ +static int rx_bytes(uint8_t * data, uint32_t instance, int sz) +{ + int i; + + for (i = 0; sz > 0; sz--, i++) { + if (wait_op_done(instance, 0) != 0) { + return -1; + } + + // the next two if-statements setup for the next read control register value + if (sz == 1) { + // last byte --> generate STOP + // generate STOP by clearing MSTA bit + imx_send_stop(instance); + } + + if (sz == 2) { + // 2nd last byte --> set TXAK bit to NOT generate ACK + HW_I2C_I2CR(instance).B.TXAK = 1; + } + + // read the true data + data[i] = HW_I2C_I2DR_RD(instance); +#if TRACE_I2C + + debug_printf("OK 0x%02x\n", data[i]); +#endif // TRACE_I2C + } + + return 0; +} + +static void set_i2c_clock(uint32_t instance, uint32_t baud) +{ + // Adjust the divider to get the closest SCL frequency to baud rate + uint32_t src_clk = get_main_clock(IPG_PER_CLK); + uint32_t divider = src_clk / baud; + uint8_t index = 0; + + if (divider < i2c_freq_div[0][0]) + { + divider = i2c_freq_div[0][0]; + index = 0; + debug_printf("Warning :can't find a smaller divider than %d.\n", divider); + debug_printf("SCL frequency is set at %d - expected was %d.\n", src_clk/divider, baud); + } + else if (divider > i2c_freq_div[49][0]) + { + divider = i2c_freq_div[49][0]; + index = 49; + debug_printf("Warning: can't find a bigger divider than %d.\n", divider); + debug_printf("SCL frequency is set at %d - expected was %d.\n", src_clk/divider, baud); + } + else + { + for (index = 0; i2c_freq_div[index][0] < divider; index++); + divider = i2c_freq_div[index][0]; + } + + HW_I2C_IFDR_WR(instance, BF_I2C_IFDR_IC(i2c_freq_div[index][1])); +} + +int i2c_xfer(const imx_i2c_request_t *rq, int dir) +{ + uint32_t reg; + uint32_t ret = 0; + uint16_t i2cr; + uint8_t i; + uint8_t data; + uint32_t instance = i2c_get_request_instance(rq); + uint8_t address = (rq->device ? rq->device->address : rq->dev_addr) << 1; + + if (rq->buffer_sz == 0 || rq->buffer == NULL) { + debug_printf("Invalid register address size=%x, buffer size=%x, buffer=%x\n", + rq->reg_addr_sz, rq->buffer_sz, (unsigned int)rq->buffer); + return ERR_INVALID_REQUEST; + } + + // clear the status register + HW_I2C_I2SR_WR(instance, 0); + + // enable the I2C controller + HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN); + + // Check if bus is free, if not return error + if (is_bus_free(instance) != 0) { + return -1; + } + + // If the request has device info attached and it has a non-zero bit rate, then + // change the clock to the specified rate. + if (rq->device && rq->device->freq) + { + set_i2c_clock(instance, rq->device->freq); + } + + // Step 1: Select master mode, assert START signal and also indicate TX mode + HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN | BM_I2C_I2CR_MSTA | BM_I2C_I2CR_MTX); + + // make sure bus is busy after the START signal + if (wait_till_busy(instance) != 0) { + debug_printf("1\n"); + return -1; + } + + // Step 2: send slave address + read/write at the LSB + data = address | I2C_WRITE; + + if ((ret = tx_byte(&data, instance)) != 0) { + debug_printf("START TX ERR %d\n", ret); + + if (ret == ERR_NO_ACK) { + return ERR_NO_ACK_ON_START; + } else { + return ret; + } + } + + // Step 3: send I2C device register address + if (rq->reg_addr_sz > 4) { + debug_printf("Warning register address size %d should less than 4\n", rq->reg_addr_sz); + return ERR_INVALID_REQUEST; + } + + reg = rq->reg_addr; + + for (i = 0; i < rq->reg_addr_sz; i++, reg >>= 8) { + data = reg & 0xFF; + +#if TRACE_I2C + debug_printf("sending I2C=%d device register: data=0x%x, byte %d\n", instance, data, i); +#endif // TRACE_I2C + + if (tx_byte(&data, instance) != 0) { + return -1; + } + } + + // Step 4: read/write data + if (dir == I2C_READ) { + // do repeat-start + HW_I2C_I2CR(instance).B.RSTA = 1; + + // make sure bus is busy after the REPEATED START signal + if (wait_till_busy(instance) != 0) { + return ERR_TX; + } + + // send slave address again, but indicate read operation + data = address | I2C_READ; + + if (tx_byte(&data, instance) != 0) { + return -1; + } + + // change to receive mode + i2cr = HW_I2C_I2CR_RD(instance) & ~BM_I2C_I2CR_MTX; + + // if only one byte to read, make sure don't send ack + if (rq->buffer_sz == 1) { + i2cr |= BM_I2C_I2CR_TXAK; + } + HW_I2C_I2CR_WR(instance, i2cr); + + // dummy read + data = HW_I2C_I2DR_RD(instance); + + // now reading ... + if (rx_bytes(rq->buffer, instance, rq->buffer_sz) != 0) { + return -1; + } + } else { + // I2C_WRITE + for (i = 0; i < rq->buffer_sz; i++) { + // send device register value + data = rq->buffer[i]; + + if ((ret = tx_byte(&data, instance)) != 0) { + break; + } + } + } + + // generate STOP by clearing MSTA bit + imx_send_stop(instance); + + // Check if bus is free, if not return error + if (is_bus_free(instance) != 0) { + debug_printf("WARNING: bus is not free\n"); + } + + // disable the controller + HW_I2C_I2CR_WR(instance, 0); + + return ret; +} + +int i2c_read(const imx_i2c_request_t *rq) +{ + return i2c_xfer(rq, I2C_READ); +} + +int i2c_write(const imx_i2c_request_t *rq) +{ + return i2c_xfer(rq, I2C_WRITE); +} + +void i2c_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool state) +{ + uint32_t irq_id = I2C_IRQS(instance); + + if (state) { + // register the IRQ sub-routine + register_interrupt_routine(irq_id, irq_subroutine); + + // enable the IRQ at the ARM core level + enable_interrupt(irq_id, CPU_0, 0); + + // clear the status register + HW_I2C_I2SR_WR(instance, 0); + + // and enable the interrupts in the I2C controller + HW_I2C_I2CR(instance).B.IIEN = 1; + } else { + // disable the IRQ at the ARM core level + disable_interrupt(irq_id, CPU_0); + + // and disable the interrupts in the I2C controller + HW_I2C_I2CR(instance).B.IIEN = 0; + + // clear the status register + HW_I2C_I2SR_WR(instance, 0); + } +} + +int i2c_init(uint32_t base, uint32_t baud) +{ + int instance; + + // Accept either an instance or base address for the base param. + if (base >= 1 && base <= HW_I2C_INSTANCE_COUNT) + { + instance = base; + } + else + { + instance = REGS_I2C_INSTANCE(base); + } + + // enable the source clocks to the I2C port + clock_gating_config(REGS_I2C_BASE(instance), CLOCK_ON); + + // Set iomux configuration + i2c_iomux_config(instance); + + // reset I2C + HW_I2C_I2CR_WR(instance, 0); + + // Set clock. + set_i2c_clock(instance, baud); + + // set an I2C slave address + HW_I2C_IADR_WR(instance, IMX6_DEFAULT_SLAVE_ID); + + // clear the status register + HW_I2C_I2SR_WR(instance, 0); + + // enable the I2C controller + HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN); + + return 0; +} + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/drivers/imx_i2c_internal.h b/bsp/imx6ul/platform/drivers/imx_i2c_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..184d9bb9505e8b859b3caccf76957489116fdf89 --- /dev/null +++ b/bsp/imx6ul/platform/drivers/imx_i2c_internal.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IMX_I2C_INTERNAL_H__ +#define __IMX_I2C_INTERNAL_H__ + +#include "imx_i2c.h" +#include "registers/regsi2c.h" + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! Max number of operations to wait to receive ack. +#define WAIT_RXAK_LOOPS 1000000 + +//! Max number of operations to wait until busy. +#define WAIT_BUSY_LOOPS 100000 + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Setup I2C interrupt. + * + * It enables or disables the related HW module interrupt, and attached the related + * sub-routine into the vector table. + * + * @param port Pointer to the I2C module structure. + * @param state Enable or disable the interrupt. Pass true to enable. + */ +void i2c_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool state); + +/*! + * @brief I2C interrupt routine for slave transfers. + */ +void i2c_slave_interrupt_routine(void); + +//! @brief Returns the I2C controller instance from a request struct. +unsigned i2c_get_request_instance(const imx_i2c_request_t * rq); + +#if defined(__cplusplus) +} +#endif + +#endif // __IMX_I2C_INTERNAL_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/drivers/imx_timer.c b/bsp/imx6ul/platform/drivers/imx_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..f348070157425bbb7bd1268e1386449b6ed71595 --- /dev/null +++ b/bsp/imx6ul/platform/drivers/imx_timer.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file timer.c + * @brief Basic timer functions + * + * @ingroup diag_timer + */ + +#include + +#include "imx_timer.h" +#include "sdk.h" +#include "epit.h" +#include "registers/regsarmglobaltimer.h" +#include "ccm_pll.h" + +//////////////////////////////////////////////////////////////////////////////// +// Prototypes +//////////////////////////////////////////////////////////////////////////////// + +static void time_init_global_timer(); + +//////////////////////////////////////////////////////////////////////////////// +// Variables +//////////////////////////////////////////////////////////////////////////////// + +uint32_t g_microsecondTimerMultiple=8; + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +void hal_delay_us(uint32_t usecs) +{ + uint32_t instance = g_system_timer_port; + if (usecs == 0) { + return; + } + + /* enable the counter first */ + epit_counter_enable(instance, usecs, POLLING_MODE); + + /* wait for the compare event */ + while (!epit_get_compare_event(instance)) ; + + /* disable the counter to save power */ + epit_counter_disable(instance); +} + +void system_time_init(void) +{ + uint32_t freq; + // Init microsecond tick counter. + time_init_global_timer(); + + /* EPIT1 is used for the delay function */ + /* Initialize the EPIT timer used for system time functions */ + /* typical IPG_CLK is in MHz, so divide it to get a reference + clock of 1MHz => 1us per count */ + freq = get_main_clock(IPG_CLK); + epit_init(g_system_timer_port, CLKSRC_IPG_CLK, freq / 1000000, + SET_AND_FORGET, 1000, WAIT_MODE_EN | STOP_MODE_EN); +} + +#if defined(CHIP_MX6UL) +//! Init the ARM global timer to a microsecond-frequency clock. +void time_init_global_timer() +{ + // Make sure the timer is off. + HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0; + + HW_ARMGLOBALTIMER_CONTROL.B.FCR0 =1; + + HW_ARMGLOBALTIMER_CONTROL.B.FCR1 =0; + + HW_ARMGLOBALTIMER_CONTROL.B.DBG_ENABLE =0; + + // Clear counter. + HW_ARMGLOBALTIMER_COUNTER_HI_WR(0); + HW_ARMGLOBALTIMER_COUNTER_LO_WR(0); + + // Now turn on the timer. + HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1; +} + +uint64_t time_get_microseconds() +{ + // First read upper. + uint32_t upper = HW_ARMGLOBALTIMER_COUNTER_HI_RD(); + uint32_t lower = HW_ARMGLOBALTIMER_COUNTER_LO_RD(); + + return (((uint64_t)upper << 32) | (uint64_t)lower)/8; +} +#else +//! Init the ARM global timer to a microsecond-frequency clock. +void time_init_global_timer() +{ + // The ARM private peripheral clock is half the CPU clock. + uint32_t periphClock = get_main_clock(CPU_CLK) / 2; + uint32_t prescaler = (periphClock / 1000000) - 1; + + // Divide down the prescaler until it fits into 8 bits. We add up the number of ticks + // it takes to equal a microsecond interval. + g_microsecondTimerMultiple = 1; + while (prescaler > 0xff) + { + prescaler /= 2; + ++g_microsecondTimerMultiple; + } + + // Make sure the timer is off. + HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0; + + // Clear counter. + HW_ARMGLOBALTIMER_COUNTERn_WR(0, 0); + HW_ARMGLOBALTIMER_COUNTERn_WR(1, 0); + + // Set prescaler and clear other flags. + HW_ARMGLOBALTIMER_CONTROL_WR(BF_ARMGLOBALTIMER_CONTROL_PRESCALER(prescaler)); + + // Now turn on the timer. + HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1; +} + +uint64_t time_get_microseconds() +{ + // First read upper. + uint32_t upper = HW_ARMGLOBALTIMER_COUNTERn_RD(1); + uint32_t lower; + + while (true) + { + // Read lower. + lower = HW_ARMGLOBALTIMER_COUNTERn_RD(0); + + // Read upper again. + uint32_t newUpper = HW_ARMGLOBALTIMER_COUNTERn_RD(1); + + // If the first and second read of the upper bits are the same, then return. + if (newUpper == upper) + { + return (((uint64_t)upper << 32) | (uint64_t)lower) / g_microsecondTimerMultiple; + } + + // Otherwise, start over again. + upper = newUpper; + } + + return 0; +} +#endif +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// + diff --git a/bsp/imx6ul/platform/drivers/imx_uart.c b/bsp/imx6ul/platform/drivers/imx_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..7485dd5e666433a7c4a4ee86a0d1f2a5aa5ad998 --- /dev/null +++ b/bsp/imx6ul/platform/drivers/imx_uart.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file imx_uart.c + * @brief UART driver. + + * @ingroup diag_uart + */ + +#include "sdk.h" +#include "registers/regsuart.h" +#include "imx_uart.h" +#include "ccm_pll.h" +#include "interrupt.h" + +#define UART_UFCR_RFDIV BF_UART_UFCR_RFDIV(4) +//#define UART_UFCR_RFDIV UART_UFCR_RFDIV_4 +//#define UART_UFCR_RFDIV UART_UFCR_RFDIV_7 + +uint32_t uart_get_reffreq(uint32_t instance) +{ + uint32_t div = UART_UFCR_RFDIV; + uint32_t ret = 0; + uint32_t freq = get_peri_clock(UART_MODULE_CLK(instance)); + + if (div == BF_UART_UFCR_RFDIV(4)) + ret = freq / 2; + else if (div == BF_UART_UFCR_RFDIV(2)) + ret = freq / 4; + else if (div == BF_UART_UFCR_RFDIV(6)) + ret = freq / 7; + + return ret; +} + +uint8_t uart_putchar(uint32_t instance, uint8_t * ch) +{ + /* Wait for Tx FIFO not full */ + while (HW_UART_UTS(instance).B.TXFULL); + + HW_UART_UTXD_WR(instance, *ch); + + return *ch; +} + +uint8_t uart_getchar(uint32_t instance) +{ + uint32_t read_data; + + /* If Rx FIFO has no data ready */ + if (!(HW_UART_USR2(instance).B.RDR)) + return NONE_CHAR; + + read_data = HW_UART_URXD_RD(instance); + + /* If error are detected */ + if (read_data & 0x7C00) + return NONE_CHAR; + + return (uint8_t) read_data; +} + +void uart_set_FIFO_mode(uint32_t instance, uint8_t fifo, uint8_t trigger_level, + uint8_t service_mode) +{ + if (fifo == TX_FIFO) { + /* Configure the TX_FIFO trigger level */ + HW_UART_UFCR_CLR(instance,BM_UART_UFCR_TXTL); + HW_UART_UFCR_SET(instance, BF_UART_UFCR_TXTL(trigger_level)); + /* Configure the TX_FIFO service mode */ + /* Default mode is polling: IRQ and DMA requests are disabled */ + HW_UART_UCR1_CLR(instance,(BM_UART_UCR1_TRDYEN | BM_UART_UCR1_TXDMAEN)); + if (service_mode == DMA_MODE) + HW_UART_UCR1_SET(instance,BM_UART_UCR1_TXDMAEN); + else if (service_mode == IRQ_MODE) + HW_UART_UCR1_SET(instance,BM_UART_UCR1_TRDYEN); + } else { /* fifo = RX_FIFO */ + /* Configure the RX_FIFO trigger level */ + HW_UART_UFCR_CLR(instance,BM_UART_UFCR_RXTL); + HW_UART_UFCR_SET(instance,BF_UART_UFCR_RXTL(trigger_level)); + /* Configure the RX_FIFO service mode */ + /* Default mode is polling: IRQ and DMA requests are disabled */ + HW_UART_UCR1_CLR(instance,(BM_UART_UCR1_RRDYEN | BM_UART_UCR1_RXDMAEN)); + if (service_mode == DMA_MODE) + HW_UART_UCR1_SET(instance,BM_UART_UCR1_RXDMAEN); + else if (service_mode == IRQ_MODE) + HW_UART_UCR1_SET(instance,BM_UART_UCR1_RRDYEN); + } +} + +void uart_set_loopback_mode(uint32_t instance, uint8_t state) +{ + if (state == TRUE) + HW_UART_UTS_SET(instance, BM_UART_UTS_LOOP); + else + HW_UART_UTS_CLR(instance, BM_UART_UTS_LOOP); +} + +void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), uint8_t state) +{ + uint32_t irq_id = UART_IRQS(instance); + + if (state == TRUE) { + /* register the IRQ sub-routine */ + register_interrupt_routine(irq_id, irq_subroutine); + /* enable the IRQ */ + enable_interrupt(irq_id, CPU_0, 0); + } else + /* disable the IRQ */ + disable_interrupt(irq_id, CPU_0); +} + +void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity, + uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol) +{ + uint32_t base = REGS_UART_BASE(instance); + + /* configure the I/O for the port */ + uart_iomux_config(instance); + + /* enable the source clocks to the UART port */ + clock_gating_config(base, CLOCK_ON); + + /* Wait for UART to finish transmitting before changing the configuration */ + while (!(HW_UART_UTS(instance).B.TXEMPTY)) ; + + /* Disable UART */ + HW_UART_UCR1_CLR(instance,BM_UART_UCR1_UARTEN ); + + /* Configure FIFOs trigger level to half-full and half-empty */ + HW_UART_UFCR_WR(instance, BF_UART_UFCR_RXTL(16) | UART_UFCR_RFDIV | BF_UART_UFCR_TXTL(16)); + + /* Setup One Millisecond timer */ + HW_UART_ONEMS_WR(instance, uart_get_reffreq(instance) / 1000); + + /* Set parity */ + if (parity == PARITY_NONE) + HW_UART_UCR2_CLR(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE)); + else if (parity == PARITY_ODD) + HW_UART_UCR2_SET(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE)); + else { /* parity == PARITY_EVEN */ + HW_UART_UCR2_SET(instance, BM_UART_UCR2_PREN); + HW_UART_UCR2_CLR(instance, BM_UART_UCR2_PROE); + } + + /* Set stop bit */ + if (stopbits == STOPBITS_ONE) + HW_UART_UCR2_CLR(instance, BM_UART_UCR2_STPB); + else /* stopbits == STOPBITS_TWO */ + HW_UART_UCR2_SET(instance, BM_UART_UCR2_STPB); + + /* Set data size */ + if (datasize == EIGHTBITS) + HW_UART_UCR2_SET(instance, BM_UART_UCR2_WS); + else /* stopbits == STOPBITS_TWO */ + HW_UART_UCR2_CLR(instance, BM_UART_UCR2_WS); + + /* Configure the flow control */ + if (flowcontrol == FLOWCTRL_ON) { + /* transmit done when RTS asserted */ + HW_UART_UCR2_CLR(instance, BM_UART_UCR2_IRTS ); + /* CTS controlled by the receiver */ + HW_UART_UCR2_SET(instance, BM_UART_UCR2_CTSC ); + } else { /* flowcontrol == FLOWCTRL_OFF */ + /* Ignore RTS */ + HW_UART_UCR2_SET(instance, BM_UART_UCR2_IRTS); + /* CTS controlled by the CTS bit */ + HW_UART_UCR2_CLR(instance, BM_UART_UCR2_CTSC); + } + + /* the reference manual says that this bit must always be set */ + HW_UART_UCR3_SET(instance, BM_UART_UCR3_RXDMUXSEL); + + /* Enable UART */ + HW_UART_UCR1_SET(instance, BM_UART_UCR1_UARTEN); + + /* Enable FIFOs and does software reset to clear status flags, reset + the transmit and receive state machine, and reset the FIFOs */ + HW_UART_UCR2_SET(instance, BM_UART_UCR2_TXEN | BM_UART_UCR2_RXEN | BM_UART_UCR2_SRST); + + /* Set the numerator value minus one of the BRM ratio */ + HW_UART_UBIR_WR(instance, (baudrate / 100) - 1); + + /* Set the denominator value minus one of the BRM ratio */ + HW_UART_UBMR_WR(instance, ((uart_get_reffreq(instance) / 1600) - 1)); + + /* Optional: prevent the UART to enter debug state. Useful when debugging + the code with a JTAG and without active IRQ */ + HW_UART_UTS_SET(instance, BM_UART_UTS_DBGEN); +} + diff --git a/bsp/imx6ul/platform/include/epit.h b/bsp/imx6ul/platform/include/epit.h new file mode 100644 index 0000000000000000000000000000000000000000..86955f80acea9a2fdc40243580e56f7ce40e1fe3 --- /dev/null +++ b/bsp/imx6ul/platform/include/epit.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +//! @addtogroup diag_epit +//! @{ + +/*! + * @file epit.h + * @brief EPIT driver public interface. + */ + +#ifndef __EPIT_H__ +#define __EPIT_H__ + +#include "imx_timer.h" +#include "sdk.h" + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Free running reload mode. +//! +//! When the counter reaches zero it rolls over to 0xFFFF_FFFF. +#define FREE_RUNNING 0 + +//! @brief Set and forget reload mode. +//! +//! When the counter reaches zero it reloads from the modulus register. +#define SET_AND_FORGET 1 + +//! @brief Pass to epit_counter_enable() to enable interrupts. +#define IRQ_MODE 1 + +//! @brief Get the irq id of RPIT by instance number. +//! @param x I2C instance number, from 1 through 2. +#define EPIT_IRQS(x) ( (x) == HW_EPIT1 ? IMX_INT_EPIT1 : (x) == HW_EPIT2 ? IMX_INT_EPIT2 : 0xFFFFFFFF) + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize the EPIT timer. + * + * @param instance the EPIT instance number. + * @param clock_src Source clock of the counter: CLKSRC_OFF, CLKSRC_IPG_CLK, + * CLKSRC_PER_CLK, CLKSRC_CKIL. + * @param prescaler Prescaler of source clock from 1 to 4096. + * @param reload_mode Counter reload mode: FREE_RUNNING or SET_AND_FORGET. + * @param load_val Load value from where the counter start. + * @param low_power_mode Low power during which the timer is enabled: + * WAIT_MODE_EN and/or STOP_MODE_EN. + */ +void epit_init(uint32_t instance, uint32_t clock_src, uint32_t prescaler, + uint32_t reload_mode, uint32_t load_val, uint32_t low_power_mode); + +/*! + * @brief Setup EPIT interrupt. + * + * It enables or disables the related HW module interrupt, and attached the related sub-routine + * into the vector table. + * + * @param instance the EPIT instance number. + * @param irq_subroutine the EPIT interrupt interrupt routine. + * @param enableIt True to enable the interrupt, false to disable. + */ +void epit_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool enableIt); + +/*! + * @brief Enable the EPIT module. + * + * Used typically when the epit_init is done, and other interrupt related settings are ready. + * + * In interrupt mode, when the interrupt fires you should call epit_get_compare_event() to + * clear the compare flag. + * + * @param instance the EPIT instance number. + * @param load_val Load value from where the counter starts. + * @param irq_mode Interrupt mode: IRQ_MODE or POLLING_MODE. + */ +void epit_counter_enable(uint32_t instance, uint32_t load_val, uint32_t irq_mode); + +/*! + * @brief Disable the counter. + * + * It saves energy when not used. + * + * @param instance the EPIT instance number. + */ +void epit_counter_disable(uint32_t instance); + +/*! + * @brief Get the output compare status flag and clear it if set. + * + * This function can typically be used for polling method, but + * is also used to clear the status compare flag in IRQ mode. + * + * @param instance the EPIT instance number. + * @return Value of the compare event flag. + */ +uint32_t epit_get_compare_event(uint32_t instance); + +/*! + * @brief Set the output compare register. + * + * + * @param instance the EPIT instance number. + * @param Value of the compare register. + */ +void epit_set_compare_event(uint32_t instance, uint32_t compare_val); + +/*! + * @brief Get the counter value. + * + * + * @param instance the EPIT instance number. + * @return Value of the counter register. + */ +uint32_t epit_get_counter_value(uint32_t instance); + +/*! + * @brief Reload the counter with a known value. + * + * @param instance the EPIT instance number. + * @param load_val Value loaded into the timer counter. + */ +void epit_reload_counter(uint32_t instance, uint32_t load_val); + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif //__EPIT_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/gic.h b/bsp/imx6ul/platform/include/gic.h new file mode 100644 index 0000000000000000000000000000000000000000..f3eee8499c6e2528618fa1ed49ef89e81f43e72a --- /dev/null +++ b/bsp/imx6ul/platform/include/gic.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __GIC_H__ +#define __GIC_H__ + +#include "sdk_types.h" + +//! @addtogroup gic +//! @{ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Options for sending a software generated interrupt. +//! +//! These options are used for the @a filter_list parameter of the gic_send_sgi() +//! function. They control how to select which CPUs that the interrupt is +//! sent to. +enum _gicd_sgi_filter +{ + //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter. + kGicSgiFilter_UseTargetList = 0, + + //! Forward the interrupt to all CPU interfaces except that of the processor that requested + //! the interrupt. + kGicSgiFilter_AllOtherCPUs = 1, + + //! Forward the interrupt only to the CPU interface of the processor that requested the + //! interrupt. + kGicSgiFilter_OnlyThisCPU = 2 +}; + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @name Initialization +//@{ +//! @brief Init interrupt handling. +//! +//! This function is intended to be called only by the primary CPU init code, so it will +//! only be called once during system bootup. +//! +//! Also inits the current CPU. You don't need to call gic_init_cpu() separately. +//! +//! @post The interrupt distributor and the current CPU interface are enabled. All interrupts +//! that were pending are cleared, and all interrupts are made secure (group 0). +void gic_init(void); + +//! @brief Init the current CPU's GIC interface. +//! +//! @post Enables the CPU interface and sets the priority mask to 255. Interrupt preemption +//! is disabled by setting the Binary Point to a value of 7. +void gic_init_cpu(void); +//@} + +//! @name GIC Interrupt Distributor Functions +//@{ +//! @brief Enable or disable the GIC Distributor. +//! +//! Enables or disables the GIC distributor passing both secure (group 0) and non-secure +//! (group 1) interrupts to the CPU interfaces. +//! +//! @param enableIt Pass true to enable or false to disable. +void gic_enable(bool enableIt); + +//! @brief Set the security mode for an interrupt. +//! +//! @param irqID The interrupt number. +//! @param isSecure Whether the interrupt is taken to secure mode. +void gic_set_irq_security(uint32_t irqID, bool isSecure); + +//! @brief Enable or disable an interrupt. +//! +//! @param irqID The number of the interrupt to control. +//! @param isEnabled Pass true to enable or false to disable. +void gic_enable_irq(uint32_t irqID, bool isEnabled); + +//! @brief Set whether a CPU will receive a particular interrupt. +//! +//! @param irqID The interrupt number. +//! @param cpuNumber The CPU number. The first CPU core is 0. +//! @param enableIt Whether to send the interrupt to the specified CPU. Pass true to enable +//! or false to disable. +void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt); + +//! @brief Set an interrupt's priority. +//! +//! @param irq_id The interrupt number. +//! @param priority The priority for the interrupt. In the range of 0 through 0xff, with +//! 0 being the highest priority. +void gic_set_irq_priority(uint32_t irq_id, uint32_t priority); + +//! @brief Send a software generated interrupt to a specific CPU. +//! +//! @param irq_id The interrupt number to send. +//! @param target_list Each bit indicates a CPU to which the interrupt will be forwarded. +//! Bit 0 is CPU 0, bit 1 is CPU 1, and so on. If the value is 0, then the interrupt +//! will not be forwarded to any CPUs. This parameter is only used if @a filter_list +//! is set to #kGicSgiFilter_UseTargetList. +//! @param filter_list One of the enums of the #_gicd_sgi_filter enumeration. The selected +//! option determines which CPUs the interrupt will be sent to. If the value +//! is #kGicSgiFilter_UseTargetList, then the @a target_list parameter is used. +void gic_send_sgi(uint32_t irq_id, uint32_t target_list, uint32_t filter_list); +//@} + +//! @name GIC CPU Interface Functions +//@{ +//! @brief Enable or disable the interface to the GIC for the current CPU. +//! +//! @param enableIt Pass true to enable or false to disable. +void gic_cpu_enable(bool enableIt); + +//! @brief Set the mask of which interrupt priorities the CPU will receive. +//! +//! @param priority The lowest priority that will be passed to the current CPU. Pass 0xff to +//! allow all priority interrupts to signal the CPU. +void gic_set_cpu_priority_mask(uint32_t priority); + +//! @brief Acknowledge starting of interrupt handling and get the interrupt number. +//! +//! Normally, this function is called at the beginning of the IRQ handler. It tells the GIC +//! that you are starting to handle an interupt, and returns the number of the interrupt you +//! need to handle. After the interrupt is handled, you should call gic_write_end_of_irq() +//! to signal that the interrupt is completely handled. +//! +//! In some cases, a spurious interrupt might happen. One possibility is if another CPU handles +//! the interrupt. When a spurious interrupt occurs, the end of the interrupt should be indicated +//! but nothing else. +//! +//! @return The number for the highest priority interrupt available for the calling CPU. If +//! the return value is 1022 or 1023, a spurious interrupt has occurred. +uint32_t gic_read_irq_ack(void); + +//! @brief Signal the end of handling an interrupt. +//! +//! @param irq_id The number of the interrupt for which handling has finished. +void gic_write_end_of_irq(uint32_t irq_id); +//@} + + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif // __GIC_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/gpt.h b/bsp/imx6ul/platform/include/gpt.h new file mode 100644 index 0000000000000000000000000000000000000000..bc239281c4998c8ee9823a91d619c4aac1729c4c --- /dev/null +++ b/bsp/imx6ul/platform/include/gpt.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +//! @addtogroup diag_gpt +//! @{ + +/*! + * @file gpt.h + * @brief GPT driver public interface. + */ + +#ifndef __GPT_H__ +#define __GPT_H__ + +#include "imx_timer.h" +#include "sdk.h" + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Possible events for the GPT. +//! +//! These constants are intended to be combined together to form a bitmask. Several +//! of the GPT driver APIs use such a bitmask. For instance, gpt_counter_enable() +//! accepts a bitmask that selects the events for which interrupts should be enabled. +//! +//! Note that the values of these enums happen to be the bitmasks for the respective +//! fields in the HW_GPT_SR and HW_GPT_IR registers, so a mask constructed from them +//! can be used directly with register values. +enum _gpt_events +{ + kGPTNoEvent = 0, //!< No events enabled. + kGPTRollover = 1 << 5, //!< Rollover event. + kGPTInputCapture1 = 1 << 3, //!< Input capture 1 event. + kGPTInputCapture2 = 1 << 4, //!< Input capture 2 event. + kGPTOutputCompare1 = 1 << 0, //!< Output compare 1 event. + kGPTOutputCompare2 = 1 << 1, //!< Output compare 2 event. + kGPTOutputCompare3 = 1 << 2, //!< Output compare 3 event. + + //! Combined mask of all GPT events. + kGPTAllEvents = kGPTRollover | kGPTInputCapture1 | kGPTInputCapture2 + | kGPTOutputCompare1 | kGPTOutputCompare2 | kGPTOutputCompare3 +}; + +//! @brief GPT counter modes. +enum _gpt_counter_mode +{ + RESTART_MODE = 0, + FREE_RUN_MODE = 1 +}; + +//! @brief Supported input capture modes. +enum _gpt_capture_modes +{ + INPUT_CAP_DISABLE = 0, //!< input capture event disabled + INPUT_CAP_RISING_EDGE = 1, //!< input capture event on a rising edge + INPUT_CAP_FALLING_EDGE = 2, //!< input capture event on a falling edge + INPUT_CAP_BOTH_EDGE = 3 //!< input capture event on a both edge +}; + +//! @brief Supported output modes. +enum _gpt_compare_modes +{ + OUTPUT_CMP_DISABLE = 0, //!< output disconnected from pad + OUTPUT_CMP_TOGGLE = 1, //!< output toggle mode + OUTPUT_CMP_CLEAR = 2, //!< output set low mode + OUTPUT_CMP_SET = 3, //!< output set high mode + OUTPUT_CMP_LOWPULSE = 4 //!< output set high mode +}; + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize the GPT timer. + * + * @param clock_src Source clock of the counter: CLKSRC_OFF, CLKSRC_IPG_CLK, + * CLKSRC_PER_CLK, CLKSRC_CKIL, CLKSRC_CLKIN. + * @param prescaler Prescaler of the source clock from 1 to 4096. + * @param counter_mode Counter mode: FREE_RUN_MODE or RESTART_MODE. + * @param low_power_mode Low power during which the timer is enabled: + * WAIT_MODE_EN and/or STOP_MODE_EN. + */ +void gpt_init(uint32_t clock_src, uint32_t prescaler, uint32_t counter_mode, uint32_t low_power_mode); + +/*! + * @brief Setup GPT interrupt. + * + * It enables or disables the related HW module interrupt, and attached the + * related sub-routine into the vector table. + * + * @param irq_subroutine the GPT interrupt interrupt routine. + * @param enableIt Pass true to enable the interrupt. + */ +void gpt_setup_interrupt(void (*irq_subroutine)(void), bool enableIt); + +/*! + * @brief Enable the GPT module. + * + * Used typically when the gpt_init is done, and other interrupt related settings are ready. + * + * If a value of #kGPTNoEvent is passed for @a irq_mode, then no interrupts will be enabled. + * This effectively puts the timer into polling mode, where you must call gpt_get_x_event() + * to check for an event having occurred. + * + * @param irq_mode Mask of events to enable interrupts for, such as #kGPTRollover or + * #kGPTOutputCompare1. See the #_gpt_events enum for the complete list. Pass + * #kGPTNoEvent to prevent any interrupts from being enabled, which effectively puts + * the timer into polling mode. + */ +void gpt_counter_enable(uint32_t irq_mode); + +/*! + * @brief Disable the counter. + * + * It saves power when not used. + * + */ +void gpt_counter_disable(void); + +/*! + * @brief Get rollover event flag and clear it if set. + * + * This function can typically be used for polling method, but + * is also used to clear the status compare flag in IRQ mode. + * + * @return Either 0 of kGPTRollover. + */ +uint32_t gpt_get_rollover_event(void); + +/*! + * @brief Get a captured value when an event occured, and clear the flag if set. + * + * Use this function to check for an input capture event having occurred, either in + * the event ISR or to check manually in polling mode. Pass the input channel to check + * in the @a flag parameter. If that channel fired, its captured timer value will be + * read and placed in @a capture_val (if not NULL). The event that fired will be cleared + * and its event mask returned as the return value from the function. If no event + * occurred, the function returns 0. + * + * @param flag Which channel to check, either #kGPTInputCapture1 or #kGPTInputCapture2. + * Only one channel may be specified. + * @param capture_val The capture register value is returned through this parameter if + * the specified event occurred. May be NULL if not required. + * @return Mask of input specified capture event that occurred, or 0 if no event occurred. + */ +uint32_t gpt_get_capture_event(uint8_t flag, uint32_t * capture_val); + +/*! + * @brief Set the input capture mode. + * + * @param cap_input The input capture channel to configure, either #kGPTInputCapture1 + * or #kGPTInputCapture2. + * @param cap_input_mode Capture input mode: #INPUT_CAP_DISABLE, #INPUT_CAP_BOTH_EDGE, + * #INPUT_CAP_FALLING_EDGE, #INPUT_CAP_RISING_EDGE. + */ +void gpt_set_capture_event(uint8_t cap_input, uint8_t cap_input_mode); + +/*! + * @brief Get a compare event flag and clear it if set. + * + * This function can typically be used for polling method, but + * is also used to clear the status compare flag in IRQ mode. + * + * @param flag Checked compare event flag such GPTSR_OF1, GPTSR_OF2, GPTSR_OF3. + * @return The value of the compare event flag. + */ +uint32_t gpt_get_compare_event(uint8_t flag); + +/*! + * @brief Set a compare event by programming the compare register and + * compare output mode. + * + * @param cmp_output The channel to configure. Must be one of #kGPTOutputCompare1, + * #kGPTOutputCompare2, or #kGPTOutputCompare3. + * @param cmp_output_mode Compare output mode: #OUTPUT_CMP_DISABLE, #OUTPUT_CMP_TOGGLE, + * #OUTPUT_CMP_CLEAR, #OUTPUT_CMP_SET, #OUTPUT_CMP_LOWPULSE. + * @param cmp_value Compare value for the compare register. + */ +void gpt_set_compare_event(uint8_t cmp_output, uint8_t cmp_output_mode, uint32_t cmp_value); + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif //__GPT_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/hab_defines.h b/bsp/imx6ul/platform/include/hab_defines.h new file mode 100644 index 0000000000000000000000000000000000000000..1fcf5d54440343f5a07da9979fecca9ed07c4e24 --- /dev/null +++ b/bsp/imx6ul/platform/include/hab_defines.h @@ -0,0 +1,2222 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file hab_defines.h + * @brief defines for data structures and macros used for enabling secure boot + * + * @ingroup diag_init + */ +#ifndef HAB_DEFINES_H +#define HAB_DEFINES_H +/*=========================================================================== + INCLUDE FILES +=============================================================================*/ +#include /* for integer types */ +#include /* for bool type */ +#include /* for NULL and offsetof() */ +/*=========================================================================== + CONSTANTS +=============================================================================*/ +/** @addtogroup struct + * @{ + */ + +#define HDR_BYTES 4 /* cannot use sizeof(hab_hdr_t) in preprocessor */ + +/** @name External data structure tags + * @anchor dat_tag + * + * Tag values 0x00 .. 0xef are reserved for HAB. Values 0xf0 .. 0xff + * are available for custom use. + */ +/*@{*/ +#define HAB_TAG_IVT 0xd1 /**< Image Vector Table */ +#define HAB_TAG_DCD 0xd2 /**< Device Configuration Data */ +#define HAB_TAG_CSF 0xd4 /**< Command Sequence File */ +#define HAB_TAG_CRT 0xd7 /**< Certificate */ +#define HAB_TAG_SIG 0xd8 /**< Signature */ +#define HAB_TAG_EVT 0xdb /**< Event */ +#define HAB_TAG_RVT 0xdd /**< ROM Vector Table */ +#define HAB_TAG_WRP 0x81 /**< Wrapped Key */ +#define HAB_TAG_MAC 0xac /**< Message Authentication Code */ +/* Values 00 ... 7e reserved for internal use. Values b0 ... cf reserved for + * CSF commands. Values e0 ... ef reserved for key types. + * + * Available values: 82, 84, 87, 88, 8b, 8d, 8e, 90, 93, 95, 96, 99, 9a, + * 9c, 9f, a0, a3, a5, a6, a9, aa, af + * + * Custom values: f0, f3, f5, f6, f9, fa, fc, ff + */ +/*@}*/ + +/** @name HAB version */ +/*@{*/ +#define HAB_MAJOR_VERSION 4 /**< Major version of this HAB release */ +#define HAB_MINOR_VERSION 1 /**< Minor version of this HAB release */ +#define HAB_VER_MAJ_WIDTH 4 /**< Major version field width */ +#define HAB_VER_MAJ_SHIFT 4 /**< Major version field offset */ +#define HAB_VER_MIN_WIDTH 4 /**< Minor version field width */ +#define HAB_VER_MIN_SHIFT 0 /**< Minor version field offset */ +/** Full version of this HAB release @hideinitializer */ +#define HAB_VERSION HAB_VER(HAB_MAJOR_VERSION, HAB_MINOR_VERSION) +/** Base version for this HAB release @hideinitializer */ +#define HAB_BASE_VERSION HAB_VER(HAB_MAJOR_VERSION, 0) + +/*@}*/ + +/* @} struct */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup cmd + * @{ + */ + +/** @name Command tags + * @anchor cmd_tag + * + * Tag values 0xb0 .. 0xcf are reserved for HAB. Values 0xf0 .. 0xff + * are available for custom use. + */ +/*@{*/ +#define HAB_CMD_SET 0xb1 /**< Set */ +#define HAB_CMD_INS_KEY 0xbe /**< Install Key */ +#define HAB_CMD_AUT_DAT 0xca /**< Authenticate Data */ +#define HAB_CMD_WRT_DAT 0xcc /**< Write Data */ +#define HAB_CMD_CHK_DAT 0xcf /**< Check Data */ +#define HAB_CMD_NOP 0xc0 /**< No Operation */ +#define HAB_CMD_INIT 0xb4 /**< Initialise */ +#define HAB_CMD_UNLK 0xb2 /**< Unlock */ +#ifdef HAB_FUTURE +#define HAB_CMD_RMV_KEY /**< Remove Key */ +#define HAB_CMD_INS_REF /**< Install Reference Data */ +#define HAB_CMD_INS_PLG /**< Install Plugin */ +#define HAB_CMD_RMV_PLG /**< Remove Plugin */ +#define HAB_CMD_CHK_VER /**< Check SW Version */ +#endif +/* Remaining values: b7, b8, bb, bd, c3, c5, c6, c9 */ +/*@}*/ + +/* @} cmd */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup pcl + * @{ + */ + +/** @name Protocol tags + * @anchor pcl_tag + * + * Tag values 0x00 .. 0xef are reserved for HAB. Values 0xf0 .. 0xff are + * available for custom use. + */ +/*@{*/ +#define HAB_PCL_SRK 0x03 /**< SRK certificate format */ +#define HAB_PCL_X509 0x09 /**< X.509v3 certificate format */ +#define HAB_PCL_CMS 0xc5 /**< CMS/PKCS#7 signature format */ +#define HAB_PCL_BLOB 0xbb /**< SHW-specific wrapped key format */ +#define HAB_PCL_AEAD 0xa3 /**< Proprietary AEAD MAC format */ +#ifdef HAB_FUTURE +#define HAB_PCL_WTLS 0x05 /**< OMA WTLS certificate format */ +#define HAB_PCL_FSL 0x0f /**< FSL bound signature protocol */ +#define HAB_PCL_HMAC 0x30 /**< NIST HMAC message authentication */ +#define HAB_PCL_CBCMAC 0x33 /**< CBC-MAC message authentication */ +#endif +/*@}*/ + +/* Available values: 06, 0a, 0c, 11, 12, 14, 17, 18, 1b, 1d, 1e, 21, 22, 24, + * 27, 28, 2b, 2d, 2e, 35, 36, 39, 3a, 3c, 3f, 41, 42, 44, 47, 48, 4b, 4d, 4e, + * 50, 53, 55, 56, 59, 5a, 5c, 5f, 60, 63, 65, 66, 69, 6a, 6c, 6f, 71, 72, 74, + * 77, 78, 7b, 7d, 7e, 81, 82, 84, 87, 88, 8b, 8d, 8e, 90, 93, 95, 96, 99, 9a, + * 9c, 9f, a0, a5, a6, a9, aa, ac, af, b1, b2, b4, b7, b8, bd, be, c0, c3, c6, + * c9, ca, cc, cf, d1, d2, d4, d7, d8, db, dd, de, e1, e2, e4, e7, e8, eb, ed, + * ee + * + * Custom values: f0, f3, f5, f6, f9, fa, fc, ff + */ + +/* @} pcl */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup alg + * @{ + */ + +/** @name Algorithm types + * @anchor alg_typ + * + * The most-significant nibble of an algorithm ID denotes the algorithm + * type. Algorithms of the same type share the same interface. + * + * Types 0x0 .. 0xc are reserved for HAB. Types 0xd .. 0xf are available for + * custom use. Within each reserved type N in 0 .. c, tag values 0xN0 .. 0xNc + * are reserved for HAB. Values 0xNd .. 0xNf are available for custom use. + */ +/*@{*/ +#define HAB_ALG_ANY 0x0 /**< Algorithm type ANY */ +#define HAB_ALG_HASH 0x1 /**< Hash algorithm type */ +#define HAB_ALG_SIG 0x2 /**< Signature algorithm type */ +#define HAB_ALG_FF 0x3 /**< Finite field arithmetic */ +#define HAB_ALG_EC 0x4 /**< Elliptic curve arithmetic */ +#define HAB_ALG_CIPHER 0x5 /**< Cipher algorithm type */ +#define HAB_ALG_MODE 0x6 /**< Cipher/hash modes */ +#define HAB_ALG_WRAP 0x7 /**< Key wrap algorithm type */ +/*@}*/ + +/** @name Algorithm type ANY + * + * Algorithms of type ANY have no common interface: the protocol must know + * what to do. + */ +/*@{*/ +#ifdef HAB_FUTURE +#define HAB_ALG_RANDOM /**< Random number generation */ +#endif +/* Available values: 03, 05, 06, 09, 0a, 0c, 0f + */ +/*@}*/ + +/** @name Hash algorithms */ +/*@{*/ +#define HAB_ALG_SHA1 0x11 /**< SHA-1 algorithm ID */ +#define HAB_ALG_SHA256 0x17 /**< SHA-256 algorithm ID */ +#define HAB_ALG_SHA512 0x1b /**< SHA-512 algorithm ID */ +/* Available values: 0x14, 0x12, 18, 1d, 1e + */ +/*@}*/ + +/** @name Signature algorithms */ +/*@{*/ +#define HAB_ALG_PKCS1 0x21 /**< PKCS#1 RSA signature algorithm */ +#ifdef HAB_FUTURE +#define HAB_ALG_DSA /**< NIST DSA signature algorithm */ +#define HAB_ALG_ECDSA /**< NIST ECDSA signature algorithm */ +#endif +/* Available values: 22, 24, 27, 28, 2b, 2d, 2e + */ +/*@}*/ + +/** @name Cipher algorithms */ +/*@{*/ +#define HAB_ALG_AES 0x55 /**< AES algorithm ID */ +/* Available values: 50, 53, 56, 59, 5a, 5c, 5f + */ +/*@}*/ + +/** @name Cipher or hash modes */ +/*@{*/ +#define HAB_MODE_CCM 0x66 /**< Counter with CBC-MAC */ +#ifdef HAB_FUTURE +#define HAB_MODE_HMAC /**< HMAC hash mode */ +#endif +/* Available values: 60, 63, 65, 69, 6a, 6c, 6f + */ +/*@}*/ + +/** @name Key wrap algorithms */ +/*@{*/ +#define HAB_ALG_BLOB 0x71 /**< SHW-specific key wrap */ +/* Available values: 72, 74, 77, 78, 7b, 7d, 7e + */ +/*@}*/ + +/* Available values: 81, 82, 84, 87, 88, 8b, 8d, 8e, 90, 93, 95, 96, 99, 9a, + * 9c, 9f, a0, a3, a5, a6, a9, aa, ac, af, b1, b2, b4, b7, b8, bb, bd, be, c0, + * c3, c5, c6, c9, ca, cc, cf, d1, d2, d4, d7, d8, db, dd, de, e1, e2, e4, e7, + * e8, eb, ed, ee, f0, f3, f5, f6, f9, fa, fc, ff + */ + +/* @} alg */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup eng + * @{ + */ + +/** @name Engine plugin tags + * @anchor eng_tag + * + * Tag values 0x00 .. 0xef and 0xff are reserved for HAB. Values 0xf0 .. 0xfe + * are available for custom use. + */ +/*@{*/ +#define HAB_ENG_ANY 0x00 /**< First compatible engine will be + * selected automatically (no engine + * configuration parameters are allowed). + */ +#define HAB_ENG_SCC 0x03 /**< Security controller */ +#define HAB_ENG_RTIC 0x05 /**< Run-time integrity checker */ +#define HAB_ENG_SAHARA 0x06 /**< Crypto accelerator */ +#define HAB_ENG_CSU 0x0a /**< Central Security Unit */ +#define HAB_ENG_SRTC 0x0c /**< Secure clock */ +#ifdef HAB_FUTURE +#define HAB_ENG_RNG 0x09 /**< Standalone random number generator */ +#define HAB_ENG_SJC 0x0f /**< Secure JTAG controller */ +#define HAB_ENG_WDOG 0x11 /**< Watchdog timer */ +#define HAB_ENG_SRC 0x12 /**< System Reset Controller */ +#define HAB_ENG_SPBA 0x14 /**< Shared Peripheral Bus Arbiter */ +#define HAB_ENG_IIM 0x17 /**< Fuse controller */ +#define HAB_ENG_IOMUX 0x18 /**< IO multiplexer */ +#endif +#define HAB_ENG_DCP 0x1b /**< Data Co-Processor */ +#define HAB_ENG_CAAM 0x1d /**< Cryptographic Acceleration and + Assurance Module */ +#define HAB_ENG_SNVS 0x1e /**< Secure Non-Volatile Storage */ +#define HAB_ENG_OCOTP 0x21 /**< Fuse controller */ +/** @cond rom */ +#define HAB_ENG_DTCP 0x22 /**< DTCP co-processor */ +#define HAB_ENG_ROM 0x36 /**< Protected ROM area */ +#define HAB_ENG_HDCP 0x24 /**< HDCP co-processor */ +#define HAB_ENG_RTL 0x77 /**< @rom RTL simulation engine */ +/** @endcond */ +#define HAB_ENG_SW 0xff /**< Software engine */ +/* Available values: 27, 28, 2b, 2d, 2e, 30, 33, 35, + * 39, 3a, 3c, 3f, 41, 42, 44, 47, 48, 4b, 4d, 4e, 50, 53, 55, 56, 59, 5a, + * 5c, 5f, 60, 63, 65, 66, 69, 6a, 6c, 6f, 71, 72, 74, 78, 7b, 7d, 7e, 81, + * 82, 84, 87, 88, 8b, 8d, 8e, 90, 93, 95, 96, 99, 9a, 9c, 9f, a0, a3, a5, a6, + * a9, aa, ac, af, b1, b2, b4, b7, b8, bb, bd, be, c0, c3, c5, c6, c9, ca, cc, + * cf, d1, d2, d4, d7, d8, db, dd, de, e1, e2, e4, e7, e8, eb, ed, ee + * + * Custom values: f0, f3, f5, f6, f9, fa, fc + */ +/*@}*/ + +/* @} eng */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup sah + * @{ + */ + +/** Maximum data blocks in a single hash */ +#define HAB_SAHARA_BLOCK_MAX 12 + +/** @cond rom */ +/** @rom DMA storage requirement + * + * This figure is derived in several parts: + * - each hash operation needs a 6-word descriptor structure + * - each data block needs a 3-word link structure + * - the result needs a 3-word link structure + * - at least 40 bytes are required for SHA-256 result and memory manager + * overhead: 64 bytes allows some small overhead. + */ +#define HAB_SAHARA_DMA_MIN_BYTES (24 + HAB_SAHARA_BLOCK_MAX * 12 + 12 + 64) +/** @endcond */ + +/* @} sah */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup dcp + * @{ + */ + +/** Maximum data blocks in a single hash */ +#define HAB_DCP_BLOCK_MAX 6 + +/** @cond rom */ +/** @rom DMA storage requirement + * + * This figure is derived in two parts: + * - each data block needs an 8-word work packet (descriptor) + * - at least 40 bytes are required for SHA-256 result and memory manager + * overhead: 64 bytes allows some small overhead. + */ +#define HAB_DCP_DMA_MIN_BYTES (64 + HAB_DCP_BLOCK_MAX * 32) +/** @endcond */ + +/* @} dcp */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup rtic + * @{ + */ + +/** Maximum data blocks in a single hash */ +#define HAB_RTIC_BLOCK_MAX 2 + +/* @} rtic */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup scc + * @{ + */ + +/** @cond rom */ +/** @rom DMA storage requirement + * + * This figure is derived in several stages, and assumes plaintext and + * ciphertext buffers are both allocated in the DMA region : + * - 4 blocks of plaintext required + * - 4 blocks of ciphertext required + * - each block is 16 bytes long + * - the plaintext address must be block-aligned (up to 15 bytes overhead) + * - the ciphertext address must be block-aligned (up to 3 bytes overhead) + * - at least 8 bytes of memory manager overhead: allow 32 for comfort + */ +#define HAB_SCC_DMA_MIN_BYTES ( (4+4)*16 + 15 + 3 + 32) +/** @endcond */ + +/* @} scc */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup caam + * @{ + */ + +/** Maximum data blocks in an @ref cmd_aut_dat command */ +#define HAB_CAAM_BLOCK_MAX 8 + +/** @cond rom */ +/** @rom Hash DMA storage requirement + * + * This figure is derived in several parts: + * - each hash operation needs + * - a 7-word descriptor, and + * - a 32-byte result buffer (for SHA-256), + * - giving a base requirement of (7*4 + 32) = 60 bytes + * - each data block needs a 4-word link structure + * - memory manager overhead is at least 8 bytes: 16 bytes allows flexibility + */ +#define HAB_CAAM_HSH_DMA_MIN_BYTES (60 + HAB_CAAM_BLOCK_MAX * 16 + 16) + +/** @rom AEAD DMA storage requirement + * + * This figure is derived in several parts: + * - each AEAD operation needs + * - a 16-word descriptor, + * - a 32-byte initial context value (B0 and CTR0), and + * - a 16-byte MAC value, + * - giving a base requirement of (16*4 + 32 + 16) = 112 bytes + * - each data block needs a 4-word link structure + * - memory manager overhead is at least 8 bytes: 16 bytes allows flexibility + */ +#define HAB_CAAM_CCM_DMA_MIN_BYTES (112 + HAB_CAAM_BLOCK_MAX * 16 + 16) + +/** @rom RNG DMA storage requirement + * + * This figure is derived in several parts: + * - each DRNG test operation allocates a DMA area with + * - a 1-word header, and + * - a 3-word job ring area, and + * - a 54-word descriptor, + * - requiring a total 58*4 = 232 bytes + * - each DRNG test operation also allocates a DMA area with + * - a 1-word header, and + * - a 32-byte result buffer + * - requiring a total 4 + 32 = 36 bytes + */ +#define HAB_CAAM_RNG_DMA_MIN_BYTES (232 + 32) +/** @endcond */ + +/* @} caam */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup key + * @{ + */ + +/** @name Key types + * @anchor key_types + * + * Tag values 0xe0 .. 0xef are reserved for HAB. Values 0xf0 .. 0xff + * are available for custom use. + */ +/*@{*/ +#define HAB_KEY_PUBLIC 0xe1 /**< Public key type: data present */ +#define HAB_KEY_SECRET 0xe2 /**< Secret key type: data present */ +#define HAB_KEY_MASTER 0xed /**< Master KEK type */ +#define HAB_KEY_HASH 0xee /**< Any key type: hash only */ +/* Available values: e4, e7, e8, eb + * + * Custom values: f0, f3, f5, f6, f9, fa, fc, ff + */ +/*@}*/ + +/** @name Public key store indices */ +/*@{*/ +#define HAB_IDX_SRK 0 /**< Super-Root Key index */ +#define HAB_IDX_CSFK 1 /**< CSF key index */ +/*@}*/ + +/** @name Key Counts */ +/*@{*/ +#define HAB_SRK_MIN 1 /**< Minimum Super-Root Key count */ +#define HAB_SRK_MAX 4 /**< Maximum Super-Root Key count */ +#define HAB_KEY_PUBLIC_MAX 5 /**< Maximum installed public key count + * (incl Super-Root Key) + */ +#define HAB_KEY_SECRET_MAX 4 /**< Maximum installed secret key count + * (excl Master KEKs) + */ +/*@}*/ + +/* @} key */ + +/*---------------------------------------------------------------------------*/ + +#ifdef HAB_FUTURE +/** @addtogroup key_ecdsa + * @{ + */ + +/** @name Bitfield definitions */ +/*@{*/ +#define HAB_KEY_ECDSA_FLG_WIDTH 8 /**< Width of @a flg field */ +#define HAB_KEY_ECDSA_FLG_SHIFT 0 /**< Offset of @a flg field */ +#define HAB_KEY_ECDSA_TYP_WIDTH 8 /**< Width of @a typ field */ +#define HAB_KEY_ECDSA_TYP_SHIFT 24 /**< Offset of @a typ field */ +#define HAB_KEY_ECDSA_SIZ_WIDTH 8 /**< Width of @a siz field */ +#define HAB_KEY_ECDSA_SIZ_SHIFT 16 /**< Offset of @a siz field */ +#define HAB_KEY_ECDSA_REDBITS_WIDTH 16 /**< Width of @a red_bits field */ +#define HAB_KEY_ECDSA_REDBITS_SHIFT 0 /**< Offset of @a red_bits field */ +/*@}*/ + +/* @} key_ecdsa */ +#endif + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup key_pkcs1 + * @{ + */ + +/** @name Bitfield definitions */ +/*@{*/ +#define HAB_KEY_PKCS1_FLG_WIDTH 8 /**< Width of @a flg field */ +#define HAB_KEY_PKCS1_FLG_SHIFT 0 /**< Offset of @a flg field */ +#define HAB_KEY_PKCS1_MODBYTES_WIDTH 16 /**< Width of mod_bytes field */ +#define HAB_KEY_PKCS1_MODBYTES_SHIFT 16 /**< Offset of mod_bytes field */ +#define HAB_KEY_PKCS1_EXPBYTES_WIDTH 16 /**< Width of exp_bytes field */ +#define HAB_KEY_PKCS1_EXPBYTES_SHIFT 0 /**< Offset of exp_bytes field */ +/*@}*/ + +/** @name Binding flag bitfield definitions */ +/*@}*/ +#define HAB_KEY_BND_FLG_WIDTH 5 /**< Width of binding flags */ +#define HAB_KEY_BND_FLG_SHIFT 2 /**< Offset of binding flags */ +/*@}*/ + +/* @} key_pkcs1 */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup cmd_wrt_dat + * @{ + */ + +/** @name Parameter bitfield definitions. + * + * Apply to both @ref cmd_wrt_dat and @ref cmd_chk_dat commands. */ +/*@{*/ +#define HAB_CMD_WRT_DAT_FLAGS_WIDTH 5 /**< @a flags field width */ +#define HAB_CMD_WRT_DAT_FLAGS_SHIFT 3 /**< @a flags field offset */ +#define HAB_CMD_WRT_DAT_BYTES_WIDTH 3 /**< @a bytes field width */ +#define HAB_CMD_WRT_DAT_BYTES_SHIFT 0 /**< @a bytes field offset */ +/*@}*/ + +/* @} cmd_wrt_dat */ + +/*---------------------------------------------------------------------------*/ + +/** @addtogroup bnd_obj + * @{ + */ + +/** @name Binding object IDs + * @anchor bnd_ids + * + * The ASN.1 object identifiers used to identify HAB binding attributes are + * defined in the following arc: + * +@verbatim + id-fsl OBJECT IDENTIFIER ::= { + joint-iso-itu-t(2) country(16) us(840) organization(1) fsl(123456) } + + id-habBnd OBJECT IDENTIFIER ::= { + id-fsl hab(32) binding-objects(16) } + + id-habBnd-dat OBJECT IDENTIFIER ::= { + id-habBnd dat(1) } + + id-habBnd-cfg OBJECT IDENTIFIER ::= { + id-habBnd cfg(3) } + + id-habBnd-fid OBJECT IDENTIFIER ::= { + id-habBnd fid(5) } + + id-habBnd-mid OBJECT IDENTIFIER ::= { + id-habBnd mid(6) } + + id-habBnd-cid OBJECT IDENTIFIER ::= { + id-habBnd cid(9) } +@endverbatim + * + * The ASN.1 object identifiers used to identify HAB binding attributes are + * single component extensions of id-habBnd using a component value less than + * 128 (so that the component can be DER-encoded in a single byte). + * + * The DER encoding of an object identifier in this arc is the concatenation + * of the DER prefix with the single byte identifier for the required binding + * object. Binding object attribute values are encoded as an ASN.1 SET with + * a single OCTET STRING member. + */ +/*@{*/ + +/** DER prefix + * + * @todo update description and encoding of binding object identifiers with + * real fsl value instead of fsl(123456) encoded as 0x87, 0xc4, 0x40, and + * confirm chosen values for hab(32) and binding-objects(16). + */ +#define HAB_BND_DER_PREFIX \ + {0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x87, 0xc4, 0x40, 0x20, 0x10} +#define HAB_BND_DAT 0x01 /**< Data type (mandatory) */ +#define HAB_BND_CFG 0x03 /**< Security configuration */ +#define HAB_BND_FID 0x05 /**< Fabrication UID */ +#define HAB_BND_MID 0x06 /**< Manufacturing ID */ +#define HAB_BND_CID 0x09 /**< Caller ID */ +/* Available values: 0a, 0c, 0f, 11, 12, 14, 17, 18, 1b, 1d, 1e, 21, 22, 24, + * 27, 28, 2b, 2d, 2e, 30, 33, 35, 36, 39, 3a, 3c, 3f, 41, 42, 44, 47, 48, 4b, + * 4d, 4e, 50, 53, 55, 56, 59, 5a, 5c, 5f, 60, 63, 65, 66, 69, 6a, 6c, 6f, 71, + * 72, 74, 77, 78, 7b, 7d, 7e + */ +/*@}*/ + + +/** @name Caller IDs + * + * Only the ROM caller ID is defined, but other caller IDs may be defined by + * later boot stages. + */ +/*@{*/ +#define HAB_CID_ROM 0 /**< ROM Caller ID */ +/*@}*/ + +/* @} bnd_obj */ + +#ifdef HAB_FUTURE +/** @addtogroup sig_fsl + * @{ + */ + +#define HAB_BND_DAT_BYTES 512 /**< Maximum binding data size */ + +/* @} sig_fsl */ +#endif + +/*=========================================================================== + MACROS +=============================================================================*/ +/* + * Helper macros + */ +#define HAB_CMD_UNS 0xff + +#define DEFAULT_IMG_KEY_IDX 2 + +#define GEN_MASK(width) \ + ((1UL << (width)) - 1) + +#define GEN_FIELD(f, width, shift) \ + (((f) & GEN_MASK(width)) << (shift)) + +#define PACK_UINT32(a, b, c, d) \ + ((uint32_t) ( (((uint32_t)(a) & 0xFF) << 24) \ + |(((uint32_t)(b) & 0xFF) << 16) \ + |(((uint32_t)(c) & 0xFF) << 8) \ + |(((uint32_t)(d) & 0xFF)) ) ) + +#define EXPAND_UINT32(w) \ + (uint8_t)((w)>>24), (uint8_t)((w)>>16), (uint8_t)((w)>>8), (uint8_t)(w) + +#define EXPAND_UINT16(w) \ + (uint8_t)((w)>>8), (uint8_t)(w) + +#define HDR(tag, bytes, par) \ + (uint8_t)(tag), (uint8_t)((bytes)>>8), (uint8_t)(bytes), (uint8_t)(par) + +#define HAB_VER(maj, min) \ + (GEN_FIELD((maj), HAB_VER_MAJ_WIDTH, HAB_VER_MAJ_SHIFT) \ + | GEN_FIELD((min), HAB_VER_MIN_WIDTH, HAB_VER_MIN_SHIFT)) + +#define DCD_DATA(addr, data) EXPAND_UINT32(addr), EXPAND_UINT32(data) + +/* + * CSF header + */ + +#define CSF_HDR(bytes, HABVER) \ + HDR(HAB_TAG_CSF, (bytes), HABVER) + + +/* + * DCD header + */ + +#define DCD_HDR(bytes, HABVER) \ + HDR(HAB_TAG_DCD, (bytes), HABVER) + +/* + * IVT header (goes in the struct's hab_hdr_t field, not a byte array) + */ +#define IVT_HDR(bytes, HABVER) \ + {HAB_TAG_IVT, {(uint8_t)((bytes)>>8), (uint8_t)(bytes)}, HABVER} + +/* + * Write Data + */ + +#define WRT_DAT(flags, bytes, address, val_msk) \ + HDR(HAB_CMD_WRT_DAT, WRT_DAT_BYTES, WRT_DAT_PAR((flags), (bytes))), \ + EXPAND_UINT32(address), \ + EXPAND_UINT32(val_msk) + +#define WRT_DAT_BYTES 12 + +#define MULTI_WRT_DAT(flags, bytes, address1, val_msk1, address2, \ + val_msk2, address3, val_msk3) \ + HDR(HAB_CMD_WRT_DAT, MULTI_WRT_DAT_BYTES, WRT_DAT_PAR((flags), (bytes))), \ + EXPAND_UINT32(address1), \ + EXPAND_UINT32(val_msk1), \ + EXPAND_UINT32(address2), \ + EXPAND_UINT32(val_msk2), \ + EXPAND_UINT32(address3), \ + EXPAND_UINT32(val_msk3) + +#define MULTI_WRT_DAT_BYTES 28 + +#define WRT_DAT_PAR(flags, bytes) \ + (GEN_FIELD((flags), \ + HAB_CMD_WRT_DAT_FLAGS_WIDTH, \ + HAB_CMD_WRT_DAT_FLAGS_SHIFT) \ + | GEN_FIELD((bytes), \ + HAB_CMD_WRT_DAT_BYTES_WIDTH, \ + HAB_CMD_WRT_DAT_BYTES_SHIFT)) + +/* + * Check Data (forever) + */ + +#define CHK_DAT_FOREVER(flags, bytes, address, mask) \ + HDR(HAB_CMD_CHK_DAT, CHK_DAT_FOREVER_BYTES, WRT_DAT_PAR((flags), (bytes))), \ + EXPAND_UINT32(address), \ + EXPAND_UINT32(mask) + +#define CHK_DAT_FOREVER_BYTES 12 + +/* + * Check Data (polled) + */ +#define HAB_CMD_CHK_DAT_COUNT 100 + +#define CHK_DAT(flags, bytes, address, mask, count) \ + HDR(HAB_CMD_CHK_DAT, CHK_DAT_BYTES, WRT_DAT_PAR((flags), (bytes))), \ + EXPAND_UINT32(address), \ + EXPAND_UINT32(mask), \ + EXPAND_UINT32(count) + +#define CHK_DAT_BYTES 16 + +/* + * Set (generic - used internally only, or to generate invalid commands) + */ + +#define SET(bytes, itm, value) \ + HDR(HAB_CMD_SET, (bytes), (itm)), \ + EXPAND_UINT32(value) + +/* + * Set (MID location) + */ + +#define SET_MID(bank, row, bit, fuses) \ + HDR(HAB_CMD_SET, SET_MID_BYTES, HAB_VAR_CFG_ITM_MID), \ + (bank), (row), (bit), (fuses) + +#define SET_MID_BYTES 8 + +/* + * Set (default ENG) + */ + +#define SET_ENG(alg, eng, cfg) \ + HDR(HAB_CMD_SET, SET_ENG_BYTES, HAB_VAR_CFG_ITM_ENG), \ + 0, (alg), (eng), (cfg) + +#define SET_ENG_BYTES 8 + +/* + * Init (engine) + */ + +#define INIT(eng) \ + HDR(HAB_CMD_INIT, INIT_BYTES, (eng)) + +#define INIT_BYTES 4 + +/* + * Unlk (engine) + */ + +#define UNLK(eng, ...) \ + UNLK_ ## eng(__VA_ARGS__) + +#define UNLK_BYTES(eng, ...) \ + UNLK_BYTES_ ## eng(__VA_ARGS__) + +#define UNLK_HDR(eng, ...) \ + HDR(HAB_CMD_UNLK, UNLK_BYTES_ ## eng(__VA_ARGS__), eng) + +#define UNLK_FLG(flg) \ + 0, 0, 0, (uint8_t)(flg) + +#define UNLK_FLG_BYTES 4 + +#define UNLK_HAB_ENG_SRTC(dnc) UNLK_HDR(HAB_ENG_SRTC) +#define UNLK_BYTES_HAB_ENG_SRTC(dnc) HDR_BYTES + +#define UNLK_HAB_ENG_SNVS(flg) UNLK_HDR(HAB_ENG_SNVS), UNLK_FLG(flg) +#define UNLK_BYTES_HAB_ENG_SNVS(flg) (HDR_BYTES + UNLK_FLG_BYTES) + +#define UNLK_HAB_ENG_CAAM(flg) UNLK_HDR(HAB_ENG_CAAM), UNLK_FLG(flg) +#define UNLK_BYTES_HAB_ENG_CAAM(flg) (HDR_BYTES + UNLK_FLG_BYTES) + +/* The next definition uses a GCC extension employing ## to swallow the + * trailing comma in case the macro is called with only the fixed arguments + * (i.e. flg here). This extension appears to work in the GNU compatible mode + * of RVDS and GHS compilers. + */ +#define UNLK_HAB_ENG_OCOTP(flg, ...) \ + UNLK_HDR(HAB_ENG_OCOTP, flg), UNLK_FLG(flg), ## __VA_ARGS__ + +#define UNLK_BYTES_HAB_ENG_OCOTP(flg, ...) \ + (HDR_BYTES + UNLK_FLG_BYTES \ + + ( ((flg) & (HAB_OCOTP_UNLOCK_FIELD_RETURN \ + |HAB_OCOTP_UNLOCK_JTAG \ + |HAB_OCOTP_UNLOCK_SCS)) \ + ? STUB_FAB_UID_BYTES \ + : 0 )) + +#if 0 +/* Note: no comma after HDR(). Supplied by _VAL macro if needed */ +#define UNLK(eng, val) \ + HDR(HAB_CMD_UNLK, UNLK_BYTES_ ## eng, (eng)) \ + UNLK_VAL_ ## eng(val) + +#define UNLK_BYTES(eng) \ + UNLK_BYTES_ ## eng + +#define UNLK_BYTES_HAB_ENG_SRTC HDR_BYTES +#define UNLK_VAL_HAB_ENG_SRTC(val) /* no val field */ +#define UNLK_BYTES_HAB_ENG_SNVS (HDR_BYTES + 4) +#define UNLK_VAL_HAB_ENG_SNVS(val) ,0,0,0,((val)&0xff) +#define UNLK_BYTES_HAB_ENG_CAAM (HDR_BYTES + 4) +#define UNLK_VAL_HAB_ENG_CAAM(val) ,0,0,0,((val)&0xff) +#endif + +/* + * NOP + */ + +#define NOP() \ + HDR(HAB_CMD_NOP, NOP_BYTES, 0xae) /* third param is ignored */ + +#define NOP_BYTES 4 + +/* + * Install Key (generic - used internally only) + */ + +#define INS_KEY(bytes, flg, pcl, alg, src, tgt, crt) \ + HDR(HAB_CMD_INS_KEY, (bytes), (flg)), \ + (pcl), (alg), (src), (tgt), \ + EXPAND_UINT32(crt) + +#define INS_KEY_BASE_BYTES 12 + +/* + * Install Key (SRK) + */ + +#define INS_SRK(flg, alg, src, crt) \ + INS_KEY(INS_SRK_BYTES, (flg), \ + HAB_PCL_SRK, (alg), (src), HAB_IDX_SRK, \ + (crt)) + +#define INS_SRK_BYTES INS_KEY_BASE_BYTES + +/* + * Install Key (CSFK) + */ + +#define INS_CSFK(flg, pcl, crt) \ + INS_KEY(INS_CSFK_BYTES, (flg) | HAB_CMD_INS_KEY_CSF, \ + (pcl), HAB_ALG_ANY, HAB_IDX_SRK, HAB_IDX_CSFK, \ + (crt)) + +#define INS_CSFK_BYTES INS_KEY_BASE_BYTES + +/* + * Install Key (IMGK - no hash) + */ + +#define INS_IMGK(flg, pcl, src, tgt, crt) \ + INS_KEY(INS_IMGK_BYTES, (flg), \ + (pcl), HAB_ALG_ANY, (src), (tgt), \ + (crt)) + +#define INS_IMGK_BYTES INS_KEY_BASE_BYTES + + +/* + * Install Key (IMGK - with hash). Must be followed by the crt_hsh contents + * (e.g. using #include). The length field depends on using one of the + * standard HAB algorithm names, with no adornments like casts or + * parentheses. Note that the length macro cannot be used here: the ## + * must appear in the body of this macro to prevent the alg parameter from + * being expanded first. + */ + +#define INS_IMGK_HASH(flg, pcl, alg, src, tgt, crt) \ + INS_KEY(INS_KEY_BASE_BYTES + BYTES_ ## alg, (flg) | HAB_CMD_INS_KEY_HSH, \ + (pcl), (alg), (src), (tgt), \ + (crt)) + +/* + * Same as above but the hash length is fixed to the length of SHA1, + * but the algorithm remains unchanged. + */ +#define INS_IMGK_INV_HASH(flg, pcl, alg, src, tgt, crt) \ + INS_KEY(INS_IMGK_HASH_BYTES(HAB_ALG_SHA1), (flg) | HAB_CMD_INS_KEY_HSH, \ + (pcl), (alg), (src), (tgt), \ + (crt)) + + +#define INS_IMGK_HASH_BYTES(alg) \ + (INS_KEY_BASE_BYTES + BYTES_ ## alg) + +#define BYTES_HAB_ALG_SHA1 20 +#define BYTES_HAB_ALG_SHA256 32 +#define BYTES_HAB_ALG_SHA512 64 +/* dummy value for invalid hash alg - same as default hash algorithm */ +#define DEFAULT_HASH_ALG_BYTES BYTES_HAB_ALG_SHA256 +#define BYTES_HAB_ALG_PKCS1 DEFAULT_HASH_ALG_BYTES + +/* + * Authenticate Data (generic - used internally only) + */ + +#define AUT_DAT(bytes, flg, key, pcl, eng, cfg, sig_start) \ + HDR(HAB_CMD_AUT_DAT, (bytes), (flg)), \ + (key), (pcl), (eng), (cfg), \ + EXPAND_UINT32(sig_start) + +#define AUT_DAT_BASE_BYTES 12 + +/* + * Authenticate Data (CSF) + */ + +#define AUT_CSF(flg, pcl, eng, cfg, sig_start) \ + AUT_DAT(AUT_CSF_BYTES, (flg), \ + HAB_IDX_CSFK, (pcl), (eng), (cfg), \ + (sig_start)) + +#define AUT_CSF_BYTES AUT_DAT_BASE_BYTES + +/* + * Authenticate Data (Image) + */ + +#define AUT_IMG(blocks, flg, key, pcl, eng, cfg, sig_start) \ + AUT_DAT(AUT_IMG_BYTES(blocks), (flg), \ + (key), (pcl), (eng), (cfg), \ + (sig_start)) + +#define AUT_IMG_BYTES(blocks) \ + (AUT_DAT_BASE_BYTES + 8*(blocks)) + +/** Supported widths of data commands. + * @ingroup cmd_wrt_dat + */ +typedef enum hab_data_width +{ + HAB_DATA_WIDTH_BYTE = 1, /**< 8-bit value */ + HAB_DATA_WIDTH_HALF = 2, /**< 16-bit value */ + HAB_DATA_WIDTH_WORD = 4 /**< 32-bit value */ +} hab_data_width_t; + + +/** Flags for Write Data commands. + * @ingroup cmd_wrt_dat + */ +typedef enum hab_cmd_wrt_dat_flg +{ + HAB_CMD_WRT_DAT_MSK = 1, /**< Mask/value flag: if set, only specific + * bits may be overwritten at target address + * (otherwise all bits may be overwritten) + */ + HAB_CMD_WRT_DAT_SET = 2 /**< Set/clear flag: if #HAB_CMD_WRT_DAT_MSK + * set, bits at the target address overwritten + * with this flag (otherwise it is ignored) + */ +} hab_cmd_wrt_dat_flg_t; + +/** Flags for Check Data commands. + * @ingroup cmd_chk_dat + */ +typedef enum hab_cmd_chk_dat_flg +{ + HAB_CMD_CHK_DAT_SET = 2, /**< Set/clear flag: bits set in mask must + * match this flag + */ + HAB_CMD_CHK_DAT_ANY = 4 /**< Any/all flag: if clear, all bits set in + * mask must match (otherwise any bit + * suffices) + */ +} hab_cmd_chk_dat_flg_t; + +/** Flags for Authenticate Data commands. + * @ingroup cmd_aut_dat + */ +typedef enum hab_cmd_aut_dat_flg +{ + HAB_CMD_AUT_DAT_CLR = 0, /**< No flags set */ + HAB_CMD_AUT_DAT_ABS = 1 /**< Absolute signature address */ +} hab_cmd_aut_dat_flg_t; + +/** Flags for Install Key commands. + * @ingroup cmd_ins_key + */ +typedef enum hab_cmd_ins_key_flg +{ + HAB_CMD_INS_KEY_CLR = 0, /**< No flags set */ + HAB_CMD_INS_KEY_ABS = 1, /**< Absolute certificate address */ + HAB_CMD_INS_KEY_CSF = 2, /**< Install CSF key */ + HAB_CMD_INS_KEY_DAT = 4, /**< Key binds to Data Type */ + HAB_CMD_INS_KEY_CFG = 8, /**< Key binds to Configuration */ + HAB_CMD_INS_KEY_FID = 16, /**< Key binds to Fabrication UID */ + HAB_CMD_INS_KEY_MID = 32, /**< Key binds to Manufacturing ID */ + HAB_CMD_INS_KEY_CID = 64, /**< Key binds to Caller ID */ + HAB_CMD_INS_KEY_HSH = 128 /**< Certificate hash present */ +} hab_cmd_ins_key_flg_t; + +/** Key flags. + * @ingroup key_pkcs1 + * + * @ifrom + * + * The binding flags given here align with those in #hab_cmd_ins_key_flg + * + * @endrom + * + */ +typedef enum hab_key_flg +{ + /* Two more flag values available */ + HAB_KEY_FLG_DAT = 4, /**< Key binds to Data Type */ + HAB_KEY_FLG_CFG = 8, /**< Key binds to Configuration */ + HAB_KEY_FLG_FID = 16, /**< Key binds to Fabrication UID */ + HAB_KEY_FLG_MID = 32, /**< Key binds to Manufacturing ID */ + HAB_KEY_FLG_CID = 64, /**< Key binds to Caller ID */ + HAB_KEY_FLG_CA = 128 /**< CA key */ +} hab_key_flg_t; + +/** Secret key flags. + * @ingroup crt_blob + */ +typedef enum hab_key_secret_flg +{ + /* Seven more flag values available */ + HAB_KEY_FLG_KEK = 128 /**< KEK */ +} hab_key_secret_flg_t; + +/** Binding data types + * @ingroup bnd_obj + */ +typedef enum hab_dat { + HAB_DAT_CSF = 0x0f, /**< CSF signature */ + HAB_DAT_IMG = 0x33, /**< Image signature */ +#ifdef HAB_FUTURE + HAB_DAT_PLG = 0x3c, /**< Plugin signature */ +#endif + HAB_DAT_MAX +} hab_dat_t; + +/* Available values: 55, 5a, 66, 69, 96, 99, a5, aa, c3, cc, f0, ff + */ + +/** Target check types + * @ingroup chk_tgt + */ +typedef enum hab_target { + HAB_TGT_MEMORY = 0x0f, /**< Check memory white list */ + HAB_TGT_PERIPHERAL = 0xf0, /**< Check peripheral white list */ + HAB_TGT_ANY = 0x55, /**< Check memory & peripheral white list */ + HAB_TGT_MAX +} hab_target_t; + +/** Security configuration types + * @ingroup status + */ +typedef enum hab_config { +/** @cond rom */ + HAB_CFG_FAB = 0x00, /**< @rom Un-programmed IC */ +/** @endcond */ + HAB_CFG_RETURN = 0x33, /**< Field Return IC */ + HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */ + HAB_CFG_CLOSED = 0xcc /**< Secure IC */ +} hab_config_t; +/* Available values: 0f, 3c, 55, 5a, 66, 69, 96, 99, a5, aa, ff + */ + +/** Security state types + * @ingroup status + */ +typedef enum hab_state { + HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */ + HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */ + HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */ + HAB_STATE_TRUSTED = 0x99, /**< Trusted state */ + HAB_STATE_SECURE = 0xaa, /**< Secure state */ + HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */ + HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */ + HAB_STATE_NONE = 0xf0, /**< No security state machine */ + HAB_STATE_MAX +} hab_state_t; +/* Available values: 00, 0f, 3c, 5a, 69, 96, a5, c3 + */ + +/** HAB status types + * @ingroup status + */ +typedef enum hab_status { + HAB_STS_ANY = 0x00, /**< Match any status in + * hab_rvt.report_event() + */ + HAB_FAILURE = 0x33, /**< Operation failed */ + HAB_WARNING = 0x69, /**< Operation completed with warning */ + HAB_SUCCESS = 0xf0, /**< Operation completed successfully */ + HAB_STS_MAX +} hab_status_t; + +/** Failure or warning reasons + * @ingroup evt + * + * Values 0x80 ... 0xff are reserved for internal use. + */ +typedef enum hab_reason { + HAB_RSN_ANY = 0x00, /**< Match any reason in + * hab_rvt.report_event() + */ + HAB_ENG_FAIL = 0x30, /**< Engine failure. */ + HAB_INV_ADDRESS = 0x22, /**< Invalid address: access denied. */ + HAB_INV_ASSERTION = 0x0c, /**< Invalid assertion. */ + HAB_INV_CALL = 0x28, /**< Function called out of sequence. */ + HAB_INV_CERTIFICATE = 0x21, /**< Invalid certificate. */ + HAB_INV_COMMAND = 0x06, /**< Invalid command: command malformed. */ + HAB_INV_CSF = 0x11, /**< Invalid @ref csf. */ + HAB_INV_DCD = 0x27, /**< Invalid @ref dcd. */ + HAB_INV_INDEX = 0x0f, /**< Invalid index: access denied. */ + HAB_INV_IVT = 0x05, /**< Invalid @ref ivt. */ + HAB_INV_KEY = 0x1d, /**< Invalid key. */ + HAB_INV_RETURN = 0x1e, /**< Failed callback function. */ + HAB_INV_SIGNATURE = 0x18, /**< Invalid signature. */ + HAB_INV_SIZE = 0x17, /**< Invalid data size. */ + HAB_MEM_FAIL = 0x2e, /**< Memory failure. */ + HAB_OVR_COUNT = 0x2b, /**< Expired poll count. */ + HAB_OVR_STORAGE = 0x2d, /**< Exhausted storage region. */ + HAB_UNS_ALGORITHM = 0x12, /**< Unsupported algorithm. */ + HAB_UNS_COMMAND = 0x03, /**< Unsupported command. */ + HAB_UNS_ENGINE = 0x0a, /**< Unsupported engine. */ + HAB_UNS_ITEM = 0x24, /**< Unsupported configuration item. */ + HAB_UNS_KEY = 0x1b, /**< Unsupported key type or parameters. */ + HAB_UNS_PROTOCOL = 0x14, /**< Unsupported protocol. */ + HAB_UNS_STATE = 0x09, /**< Unsuitable state. */ + HAB_RSN_MAX +} hab_reason_t; +/* Available values: 33, 35, 36, 39, 3a, 3c, 3f, 41, 42, 44, + * 47, 48, 4b, 4d, 4e, 50, 53, 55, 56, 59, 5a, 5c, 5f, 60, 63, 65, 66, 69, 6a, + * 6c, 6f, 71, 72, 74, 77, 78, 7b, 7d, 7e + */ + +/** Audit logging contexts. + * @ingroup evt + * + * This list is sorted in order of increasing priority: where two contexts + * might apply, the latter one is used. + * + * Values 0x40 .. 0x5f are reserved for internal use. + */ +typedef enum hab_context { + HAB_CTX_ANY = 0x00, /**< Match any context in + * hab_rvt.report_event() + */ +/** @cond rom */ + HAB_CTX_FAB = 0xff, /**< @rom Event logged in hab_fab_test() */ +/** @endcond */ + HAB_CTX_ENTRY = 0xe1, /**< Event logged in hab_rvt.entry() */ + HAB_CTX_TARGET = 0x33, /**< Event logged in hab_rvt.check_target() */ + HAB_CTX_AUTHENTICATE = 0x0a, /**< Event logged in + * hab_rvt.authenticate_image() + */ + HAB_CTX_DCD = 0xdd, /**< Event logged in hab_rvt.run_dcd() */ + HAB_CTX_CSF = 0xcf, /**< Event logged in hab_rvt.run_csf() */ + HAB_CTX_COMMAND = 0xc0, /**< Event logged executing @ref csf or @ref + * dcd command + */ + HAB_CTX_AUT_DAT = 0xdb, /**< Authenticated data block */ + HAB_CTX_ASSERT = 0xa0, /**< Event logged in hab_rvt.assert() */ + HAB_CTX_EXIT = 0xee, /**< Event logged in hab_rvt.exit() */ + HAB_CTX_MAX +} hab_context_t; + +/** Assertion types. + * @ingroup assert + */ +typedef enum hab_assertion { + HAB_ASSERT_BLOCK = 0, /**< Assert that a memory block was authenticated */ + HAB_ASSERT_MAX +} hab_assertion_t; + +/** RTIC configuration flags + * @ingroup rtic + */ +typedef enum hab_rtic_config { + HAB_RTIC_IN_SWAP8 = 0x01, /**< Set BYTE SWAP bit (reverse bytes within + * word on input to RTIC) */ + HAB_RTIC_IN_SWAP16 = 0x02, /**< Set HALF WORD SWAP bit (reverse + * half-words within word on input to + * RTIC) */ + HAB_RTIC_OUT_SWAP8 = 0x08, /**< Set HASH RESULT BYTE SWAP bit (reverse + * bytes within word on output from RTIC) */ + HAB_RTIC_KEEP = 0x80 /**< Retain reference hash value for later + * monitoring */ +} hab_rtic_config_t; + +/** SAHARA configuration flags + * @ingroup sah + */ +typedef enum hab_sahara_config { + HAB_SAHARA_IN_SWAP8 = 0x01, /**< Set MESS BYTE SWAP bit (reverse message + * bytes within word on input to + * SAHARA) */ + HAB_SAHARA_IN_SWAP16 = 0x02, /**< Set MESS HALF WORD SWAP bit (reverse + * message half-words within word on input + * to SAHARA) */ + /* no SWAP32 for SAHARA message - leave 0x04 value unassigned */ + /* no SWAP8 for SAHARA descriptors/links - leave 0x08 value unassigned */ + HAB_SAHARA_DSC_BE8_16 = 0x10, /**< Interpret descriptors and links as for + * BE-8 16-bit memory. */ + HAB_SAHARA_DSC_BE8_32 = 0x20 /**< Interpret descriptors and links as for + * BE-8 32-bit memory. */ +} hab_sahara_config_t; + +/** CAAM configuration flags + * @ingroup caam + */ +typedef enum hab_caam_config { + HAB_CAAM_IN_SWAP8 = 0x01, /**< Set Message Byte Swap Input bit (reverse + * message bytes within word on input to + * CAAM) */ + HAB_CAAM_IN_SWAP16 = 0x02, /**< Set Message Half Word Swap Input bit + * (reverse message half-words within word + * on input to CAAM) */ + /* no SWAP32 for CAAM message - leave 0x04 value unassigned */ + HAB_CAAM_OUT_SWAP8 = 0x08, /**< Set Message Byte Swap Output bit + * (reverse message bytes within word on + * output from CAAM) */ + HAB_CAAM_OUT_SWAP16 = 0x10, /**< Set Message Half Word Swap Output bit + * (reverse message half-words within word + * on output from CAAM) */ + /* no SWAP32 for CAAM message - leave 0x20 value unassigned */ + HAB_CAAM_DSC_SWAP8 = 0x40, /**< Set Control Byte Swap Input/Output bits + * (reverse descriptor/link bytes within + * word on input to or output from CAAM) */ + HAB_CAAM_DSC_SWAP16 = 0x80 /**< Set Control Half Word Swap Input/Output + * bits (reverse descriptor/link half-words + * within word on input to or output from + * CAAM) */ +} hab_caam_config_t; + +/** CAAM unlock flags + * @ingroup caam + */ +typedef enum hab_caam_unlock_flag { + HAB_CAAM_UNLOCK_MID = 0x01, /**< Leave Job Ring and DECO master ID + * registers unlocked */ + HAB_CAAM_UNLOCK_RNG = 0x02 /**< Leave RNG state handle 0 + * uninstantiated, do not generate + * descriptor keys, do not set AES DPA + * mask, do not block state handle 0 test + * instantiation */ +} hab_caam_unlock_flag_t; + +/** SNVS unlock flags + * @ingroup snvs + */ +typedef enum hab_snvs_unlock_flag { + HAB_SNVS_UNLOCK_LP_SWR = 0x01, /**< Leave LP SW reset unlocked */ + HAB_SNVS_UNLOCK_ZMK_WRITE = 0x02 /**< Leave Zeroisable Master Key write + * unlocked */ +} hab_snvs_unlock_flag_t; + +/** SNVS master keys + * @ingroup snvs + * + * @remark Note that the first two master key selections are completely + * interchangeable. + */ +typedef enum hab_snvs_keys { + HAB_SNVS_OTPMK = 0, /**< OTP master key */ + HAB_SNVS_OTPMK_ALIAS = 1, /**< OTP master key (alias) */ + HAB_SNVS_ZMK = 2, /**< Zeroisable master key */ + HAB_SNVS_CMK = 3 /**< Combined master key */ +} hab_snvs_keys_t; + + +/** OCOTP unlock flags + * @ingroup ocotp + */ +typedef enum hab_ocotp_unlock_flag { + HAB_OCOTP_UNLOCK_FIELD_RETURN = 0x01, /**< Leave Field Return activation + * unlocked */ + HAB_OCOTP_UNLOCK_SRK_REVOKE = 0x02, /**< Leave SRK revocation unlocked */ + HAB_OCOTP_UNLOCK_SCS = 0x04, /**< Leave SCS register unlocked */ + HAB_OCOTP_UNLOCK_JTAG = 0x08 /**< Unlock JTAG using SCS HAB_JDE + * bit */ +} hab_ocotp_unlock_flag_t; + +/** DCP configuration flags + * @ingroup dcp + * + * @warning The byte-swapping controls produce unpredictable results unless + * the input data block lengths are multiples of 4 bytes. + */ +typedef enum hab_dcp_config { + HAB_DCP_IN_SWAP8 = 0x01, /**< Set INPUT BYTE SWAP bit (reverse bytes + * within words on input to DCP) */ + /* no SWAP16 for DCP - leave 0x02 value unassigned */ + HAB_DCP_IN_SWAP32 = 0x04, /**< Set INPUT WORD SWAP bit (ignored for + * hashing) */ + HAB_DCP_OUT_SWAP8 = 0x08, /**< Set OUPUT BYTE SWAP bit (reverse bytes + * within words on output from DCP) */ + /* no SWAP16 for DCP - leave 0x10 value unassigned */ + HAB_DCP_OUT_SWAP32 = 0x20 /**< Set OUTPUT WORD SWAP bit (ignored for + * hashing) */ +} hab_dcp_config_t; + +#ifdef HAB_FUTURE +/** EC key specification types. + * @ingroup key_ecdsa + */ +typedef enum hab_ec_spec { + /** Named curve specification. The curve specification is a DER-encoded + * object identifier. Supported object identifiers are listed under @ref + * key_ecdsa_profile "ECDSA key profile". + */ + HAB_EC_SPEC_NAMED_CURVE = 0x01 +} hab_ec_spec_t; +#endif + +/** Variable configuration items + * @ingroup cmd_set + */ +typedef enum hab_var_cfg_itm { + HAB_VAR_CFG_ITM_MID = 0x01, /**< Manufacturing ID (MID) fuse locations */ + HAB_VAR_CFG_ITM_ENG = 0x03 /**< Preferred engine for a given algorithm */ +} hab_var_cfg_itm_t; + +/*=========================================================================== + ENUMS +=============================================================================*/ + +/*=========================================================================== + STRUCTURES AND OTHER TYPEDEFS +=============================================================================*/ + +/** Header field components + * @ingroup hdr + */ +typedef struct hab_hdr { + uint8_t tag; /**< Tag field */ + uint8_t len[2]; /**< Length field in bytes (big-endian) */ + uint8_t par; /**< Parameters field */ +} hab_hdr_t; + +/** Loader callback. + * @ingroup auth_img + * + * @par Purpose + * + * This function must be supplied by the library caller if required. It is + * intended to finalise image loading in those boot modes where only a portion + * of the image is loaded to a temporary initial location prior to device + * configuration. + * + * @par Operation + * + * This function is called during hab_rvt.authenticate_image() between running + * the @ref dcd and @ref csf. The operation of this function is defined by + * the caller. + * + * @param[in,out] start Initial (possibly partial) image load address on + * entry. Final image load address on exit. + * + * @param[in,out] bytes Initial (possibly partial) image size on entry. Final + * image size on exit. + * + * @param[in] boot_data Initial @ref ivt Boot Data load address. + * + * @remark The interpretation of the Boot Data is defined by the caller. + * Different boot components or modes may use different boot data, or even + * different loader callback functions. + * + * @warning It should not be assumed by this function that the Boot Data is + * valid or authentic. + * + * @warning It is the responsibility of the loader callback to check the final + * image load addresses using hab_rvt.check_target() prior to copying any image + * data. + * + * @pre The (possibly partial) image has been loaded in the initial load + * address, and the Boot Data is within the initial image. + * + * @pre The @ref dcd has been run, if provided. + * + * @post The final image load addresses pass hab_rvt.check_target(). + * + * @retval #HAB_SUCCESS if all operations completed successfully, + * + * @retval #HAB_FAILURE otherwise. + */ +typedef hab_status_t (*hab_loader_callback_f)( + void** start, + size_t* bytes, + const void* boot_data); + +/*---------------------------------------------------------------------------*/ + +/** Image entry function prototype + * @ingroup rvt + * + * This typedef serves as the return type for hab_rvt.authenticate_image(). It + * specifies a void-void function pointer, but can be cast to another function + * pointer type if required. + */ +typedef void (*hab_image_entry_f)(void); + +/*---------------------------------------------------------------------------*/ + +/** @ref rvt structure + * @ingroup rvt + * + * @par Format + * + * The @ref rvt consists of a @ref hdr followed by a list of addresses as + * described further below. + */ +struct hab_rvt { + + /** @ref hdr with tag #HAB_TAG_RVT, length and HAB version fields + * (see @ref data) + */ + hab_hdr_t hdr; + + /** Enter and initialise HAB library. + * @ingroup entry + * + * @par Purpose + * + * This function initialises the HAB library and @ref shw plugins. It is + * intended for use by post-ROM boot stage components, via the @ref rvt, + * prior to calling any other HAB functions other than + * hab_rvt.report_event() and hab_rvt.report_status(). + * + * @ifrom It is also intended for use by the boot ROM via hab_rvt.entry(). + * @endrom + * + * @par Operation + * + * This function performs the following operations every time it is called: + * + * - Initialise the HAB library internal state + * - Initialise the internal secret key store (cleared at the next + * hab_rvt.exit()) + * - Run the entry sequence of each available @ref shw plugin + * + * When first called from boot ROM, this function also performs the + * following operations prior to those given above: + * + * - Initialise the internal public key store (persists beyond + * hab_rvt.exit()) + * - Run the self-test sequence of each available @ref shw plugin + * - If a state machine is present and enabled, change the security state + * as follows: + * - If the IC is configured as #HAB_CFG_OPEN or #HAB_CFG_RETURN, move to + * #HAB_STATE_NONSECURE + * - If the IC is configured as #HAB_CFG_CLOSED, move to + * #HAB_STATE_TRUSTED + * - Otherwise, leave the security state unchanged + * + * If any failure occurs in the operations above: + * + * - An audit event is logged + * - All remaining operations are abandoned (except that all @ref shw + * self-test and entry sequences are still executed) + * - If a state machine is present and enabled, the security state is set + * as follows: + * - @ifrom Unless the IC is configured as #HAB_CFG_FAB,@endrom move to + * #HAB_STATE_NONSECURE. Note that if a security violation has been + * detected by the HW, the final state will be #HAB_STATE_FAIL_SOFT or + * #HAB_STATE_FAIL_HARD depending on the HW configuration. + * + * @warning Boot sequences may comprise several images with each launching + * the next as well as alternative images should one boot device or boot + * image be unavailable or unusable. The authentication of each image in + * a boot sequence must be bracketed by its own hab_rvt.entry() + * ... hab_rvt.exit() pair in order to ensure that security state + * information gathered for one image cannot be misapplied to another + * image. + * + * @ifrom + * + * @warning This applies to each boot path in boot ROM as well, except for + * the fabrication test path. + * + * @endrom + * + * @post HAB library internal state is initialised. + * + * @post Available @ref shw plugins are initialised. + * + * @post If a failure or warning occurs during @ref shw plugin + * initialisation, an audit event is logged with the relevant @ref eng + * tag. The status and reason logged are described in the relevant @ref + * shw plugin documentation. + * + * @post Security state is initialised, if a state machine is present and + * enabled. + * + * @retval #HAB_SUCCESS on an IC not configured as #HAB_CFG_CLOSED, + * although unsuccessful operations will still generate audit log events, + * + * @retval #HAB_SUCCESS on other ICs if all commands completed + * without failure (even if warnings were generated), + * + * @retval #HAB_FAILURE otherwise. + */ + hab_status_t (*entry)(void); + + /** Finalise and exit HAB library. + * @ingroup exit + * + * @par Purpose + * + * This function finalises the HAB library and @ref shw plugins. It is + * intended for use by post-ROM boot stage components, via the @ref rvt, + * after calling other HAB functions and prior to launching the next boot + * stage or switching to another boot path. + * + * @ifrom It is also intended for use by the boot ROM via hab_rvt.exit(). + * @endrom + * + * @par Operation + * + * This function performs the following operations: + * + * - Finalise the HAB library internal state + * - Clear the internal secret key store + * - Run the finalisation sequence of each available @ref shw plugin + * + * If any failure occurs, an audit event is logged and all remaining + * operations are abandoned (except that all @ref shw exit sequences are + * still executed). + * + * @warning See warnings for hab_rvt.entry(). + * + * @post #HAB_ASSERT_BLOCK records are cleared from audit log. Note that + * other event records are not cleared. + * + * @post Any public keys installed by @ref csf commands remain active. + * + * @post Any secret keys installed by @ref csf commands are deleted. + * + * @post Available @ref shw plugins are in their final state as described + * in the relevant sections. + * + * @post If a failure or warning occurs, an audit event is logged with the + * @ref eng tag of the @ref shw plugin concerned. The status and reason + * logged are described in the relevant @ref shw plugin documentation. + * + * @retval #HAB_SUCCESS on an IC not configured as #HAB_CFG_CLOSED, + * although unsuccessful operations will still generate audit log events, + * + * @retval #HAB_SUCCESS on other ICs if all commands completed + * without failure (even if warnings were generated), + * + * @retval #HAB_FAILURE otherwise. + */ + hab_status_t (*exit)(void); + + /** Check target address + * @ingroup chk_tgt + * + * @par Purpose + * + * This function reports whether or not a given target region is allowed + * for either peripheral configuration or image loading in memory. It is + * intended for use by post-ROM boot stage components, via the @ref rvt, + * in order to avoid configuring security-sensitive peripherals, or + * loading images over sensitive memory regions or outside recognised + * memory devices in the address map. + * + * @ifrom It is also available for use by the boot ROM, both directly via + * hab_rvt.check_target() and indirectly via hab_rvt.authenticate_image(). + * @endrom + * + * @par Operation + * + * The lists of allowed target regions vary by IC and core, and should be + * taken from the @ref ref_rug. + * + * @ifrom The allowed register sets for peripheral configuration and memory + * regions for image loading are defined in the @ref hal by + * #hab_hal_peripheral and #hab_hal_memory respectively. @endrom + * + * @param[in] type Type of target (memory, peripheral or any in which both + * the memory and peripheral regions are checked) + * + * @param[in] start Address of target region + * + * @param[in] bytes Size of target region + * + * @post if the given target region goes beyond the allowed regions, an + * audit event is logged with status #HAB_FAILURE and reason + * #HAB_INV_ADDRESS, together with the call parameters. See the @ref evt + * record documentation for details. + * + * @post For successful commands, no audit event is logged. + * + * @retval #HAB_SUCCESS on an IC not configured as #HAB_CFG_CLOSED, + * although unsuccessful operations will still generate audit log events, + * + * @retval #HAB_SUCCESS if the given target region lies wholly within the + * allowed regions for the requested type of target. + * + * @retval #HAB_FAILURE otherwise + */ + hab_status_t (*check_target)(hab_target_t type, + const void* start, + size_t bytes); + + /** Authenticate image. + * @ingroup auth_img + * + * @par Purpose + * + * This function combines DCD, CSF and Assert functions in a standard + * sequence in order to authenticate a loaded image. It is intended for + * use by post-ROM boot stage components, via the @ref rvt. Support for + * images partially loaded to an initial location is provided via a + * callback function. + * + * @ifrom It is also available for use by the boot ROM via + * hab_rvt.authenticate_image(). @endrom + * + * @par Operation + * + * This function performs the following sequence of operations: + * - Check that the initial image load addresses pass + * hab_rvt.check_target(). + * - Check that the IVT offset lies within the initial image bounds. + * - Check that the @ref ivt @a self and @a entry pointers are not NULL + * - Check the @ref ivt header for consistency and compatability. + * - If provided in the @ref ivt, calculate the @ref dcd initial location, + * check that it lies within the initial image bounds, and run the @ref + * dcd commands. + * - If provided in the @ref ivt, calculate the Boot Data initial location + * and check that it lies within the initial image bounds. + * - If provided in the parameters, invoke the callback function with the + * initial image bounds and initial location of the @ref ivt Boot Data. + * + * From this point on, the full image is assumed to be in its final + * location. The following operations will be performed on all IC + * configurations (#hab_config), but will be only enforced on an IC + * configured as #HAB_CFG_CLOSED: + * - Check that the final image load addresses pass hab_rvt.check_target(). + * - Check that the CSF lies within the image bounds, and run the CSF + * commands. + * - Check that all of the following data have been authenticated (using + * their final locations): + * - IVT; + * - DCD (if provided); + * - Boot Data (initial byte if provided); + * - Entry point (initial word). + * + * @param[in] cid Caller ID, used to identify which SW issued this call. + * + * @param[in] ivt_offset Offset in bytes of the IVT from the image start + * address. + * + * @param[in,out] start Initial (possibly partial) image load address on + * entry. Final image load address on exit. + * + * @param[in,out] bytes Initial (possibly partial) image size on entry. + * Final image size on exit. + * + * @param[in] loader Callback function to load the full image to its final + * load address. Set to NULL if not required. + * + * @remark Caller ID may be bound to signatures verified using keys + * installed with #HAB_CMD_INS_KEY_CID flag. See @ref cmd_ins_key and @ref + * bnd_obj for details. + * + * @remark A @a loader callback function may be supplied even if the image + * is already loaded to its final location on entry. + * + * @remark Boot Data (boot_data in @ref ivt) will be ignored if the + * @a loader callback function point is set to Null. + * + * @warning The @a loader callback function should lie within existing + * authenticated areas. @ifrom Or within the ROM. @endrom + * + * @warning It is the responsibility of the caller to check the initial + * image load addresses using hab_rvt.check_target() prior to loading the + * initial image and calling this function. + * + * @warning After completion of hab_rvt.authenticate_image(), the caller + * should test using hab_rvt.assert() that the Boot Data was + * authenticated. + * + * @post The post-conditions of the functions hab_rvt.check_target(), + * hab_rvt.run_dcd(), hab_rvt.run_csf() and hab_rvt.assert() apply also to + * this function. In particular, any audit events logged within the given + * functions have the context field appropriate to that function rather + * than #HAB_CTX_AUTHENTICATE. In addition, the side-effects and + * post-conditions of any callback function supplied apply. + * + * @post If a failure or warning occurs outside these contexts, an audit + * event is logged with status: + * - #HAB_FAILURE, with further reasons: + * - #HAB_INV_ADDRESS: initial or final image addresses outside allowed + * regions + * - #HAB_INV_ADDRESS: IVT, DCD, Boot Data or CSF outside image bounds + * - #HAB_INV_ADDRESS: IVT @a self or @a entry pointer is NULL + * - #HAB_INV_CALL: hab_rvt.entry() not run successfully prior to call + * - #HAB_INV_IVT: IVT malformed + * - #HAB_INV_IVT: IVT version number is less than HAB library version + * - #HAB_INV_RETURN: Callback function failed + * + * @retval entry field from @ref ivt on an IC not configured as + * #HAB_CFG_CLOSED provided that the following conditions are met + * (other unsuccessful operations will generate audit log events): + * - the @a start pointer and the pointer it locates are not NULL + * - the initial @ref ivt location is not NULL + * - the @ref ivt @ref hdr (given in the @a hdr field) is valid + * - the final @ref ivt location (given by the @a self field) is not NULL + * - any loader callback completed successfully, + * + * @retval entry field from @ref ivt on other ICs if all operations + * completed without failure (even if warnings were generated), + * + * @retval NULL otherwise. + */ + hab_image_entry_f (*authenticate_image)(uint8_t cid, + ptrdiff_t ivt_offset, + void** start, + size_t* bytes, + hab_loader_callback_f loader); + + /** Execute a boot configuration script. + * @ingroup run_dcd + * + * @par Purpose + * + * This function configures the IC based upon a @ref dcd table. It is + * intended for use by post-ROM boot stage components, via the @ref rvt. + * This function may be invoked as often as required for each boot stage. + * + * @ifrom It is also intended for use by the boot ROM, both directly via + * hab_rvt.run_dcd() and indirectly via hab_rvt.authenticate_image(). + * @endrom + * + * The difference between the configuration functionality in this function + * and hab_rvt.run_csf() arises because the @ref dcd table is not + * authenticated prior to running the commands. Hence, there is a more + * limited range of commands allowed, and a limited range of parameters to + * allowed commands. + * + * @par Operation + * + * This function performs the following operations: + * - Checks the @ref hdr for compatibility and consistency + * - Makes an internal copy of the @ref dcd table + * - Executes the commands in sequence from the internal copy of the @ref + * dcd + * + * If any failure occurs, an audit event is logged and all remaining + * operations are abandoned. + * + * @param[in] dcd Address of the @ref dcd. + * + * @warning It is the responsibility of the caller to ensure that the @a + * dcd parameter points to a valid memory location. + * + * @warning The @ref dcd must be authenticated by a subsequent @ref csf + * command prior to launching the next boot image, in order to avoid + * unauthorised configurations which may subvert secure operation. + * Although the content of the next boot stage's CSF may be out of scope + * for the hab_rvt.run_dcd() caller, it is possible to enforce this + * constraint by using hab_rvt.assert() to ensure that both the DCD and + * any pointers used to locate it have been authenticated. + * + * @warning Each invocation of hab_rvt.run_dcd() must occur between a pair + * of hab_rvt.entry() and hab_rvt.exit() calls, although multiple + * hab_rvt.run_dcd() calls (and other HAB calls) may be made in one + * bracket. This constraint applies whether hab_rvt.run_dcd() is + * successful or not: a subsequent call to hab_rvt.exit() is required + * prior to launching the authenticated image or switching to another boot + * target. + * + * @post Many commands may cause side-effects. See the @ref dcd + * documentation. + * + * @post If a failure or warning occurs within a command handler, an audit + * event is logged with the offending command, copied from the DCD. The + * status and reason logged are described in the relevant command + * documentation. + * + * @post For other failures or warning, the status logged is: + * - #HAB_WARNING, with further reasons: + * - #HAB_UNS_COMMAND: unsupported command encountered, where DCD + * version and HAB library version differ + * - #HAB_FAILURE, with further reasons: + * - #HAB_INV_ADDRESS: NULL @a dcd parameter + * - #HAB_INV_CALL: hab_rvt.entry() not run successfully prior to call + * - #HAB_INV_COMMAND: command not allowed in DCD + * - #HAB_UNS_COMMAND: unrecognised command encountered, where DCD + * version and HAB library version match + * - #HAB_INV_DCD: DCD malformed or too large + * - #HAB_INV_DCD: DCD version number is less than HAB library version + * @retval #HAB_SUCCESS on an IC not configured as #HAB_CFG_CLOSED, + * although unsuccessful operations will still generate audit log events, + * + * @retval #HAB_SUCCESS on other ICs if all commands completed + * without failure (even if warnings were generated), + * + * @retval #HAB_FAILURE otherwise. + */ + hab_status_t (*run_dcd)(const uint8_t* dcd); + + /** Execute an authentication script. + * @ingroup run_csf + * + * @par Purpose + * + * This function authenticates SW images and configures the IC based upon + * a @ref csf. It is intended for use by post-ROM boot stage components, + * via the @ref rvt. This function may be invoked as often as required + * for each boot stage. + * + * @ifrom It is also available for use by the boot ROM via hab_rvt.run_csf, + * although it is anticipated that the boot ROM will mostly call this + * function indirectly via hab_rvt.authenticate_image(). @endrom + * + * @par Operation + * + * This function performs the following operations: + * - Checks the @ref hdr for compatibility and consistency + * - Makes an internal copy of the @ref csf + * - Executes the commands in sequence from the internal copy of the @ref + * csf + * + * The internal copy of the @ref csf is authenticated by an explicit + * command in the sequence. Prior to authentication, a limited set of + * commands is available to: + * - Install a Super-Root key (unless previously installed) + * - Install a CSF key (unless previously installed) + * - Specify any variable configuration items + * - Authenticate the CSF + * + * Subsequent to CSF authentication, the full set of commands is available. + * + * If any failure occurs, an audit event is logged and all remaining + * operations are abandoned. + * + * @param[in] csf Address of the @ref csf. + * + * @param[in] cid Caller ID, used to identify which SW issued this call. + * + * @remark Caller ID may be bound to signatures verified using keys + * installed with #HAB_CMD_INS_KEY_CID flag. See @ref cmd_ins_key and @ref + * bnd_obj for details. + * + * @warning It is the responsibility of the caller to ensure that the @a + * csf parameter points to a valid memory location. + * + * @warning Each invocation of hab_rvt.run_csf() must occur between a pair + * of hab_rvt.entry() and hab_rvt.exit() calls, although multiple + * hab_rvt.run_csf() calls (and other HAB calls) may be made in one + * bracket. This constraint applies whether hab_rvt.run_csf() is + * successful or not: a subsequent call to hab_rvt.exit() is required + * prior to launching the authenticated image or switching to another boot + * target. + * + * @post Many commands may cause side-effects. See the @ref csf + * documentation. In particular, note that keys installed by the @ref csf + * remain available for use in subsequent operations. + * + * @post If a failure or warning occurs within a command handler, an audit + * event is logged with the offending command, copied from the CSF. The + * status and reason logged are described in the relevant command + * documentation. + * + * @post For other failures or warning, the status logged is: + * - #HAB_WARNING, with further reasons: + * - #HAB_UNS_COMMAND: unsupported command encountered, where CSF + * version and HAB library version differ + * - #HAB_FAILURE, with further reasons: + * - #HAB_INV_ADDRESS: NULL @a csf parameter + * - #HAB_INV_CALL: hab_rvt.entry() not run successfully prior to call + * - #HAB_INV_COMMAND: command not allowed prior to CSF authentication + * - #HAB_UNS_COMMAND: unrecognised command encountered, where CSF + * version and HAB library version match + * - #HAB_INV_CSF: CSF not authenticated + * - #HAB_INV_CSF: CSF malformed or too large + * - #HAB_INV_CSF: CSF version number is less than HAB library version + * + * @retval #HAB_SUCCESS on an IC not configured as #HAB_CFG_CLOSED, + * although unsuccessful operations will still generate audit log events, + * + * @retval #HAB_SUCCESS on other ICs if all commands completed + * without failure (even if warnings were generated), + * + * @retval #HAB_FAILURE otherwise. + */ + hab_status_t (*run_csf)(const uint8_t* csf, + uint8_t cid); + + /** Test an assertion against the audit log. + * @ingroup assert + * + * @par Purpose + * + * This function allows the audit log to be interrogated. It is intended + * for use by post-ROM boot stage components, via the @ref rvt, to + * determine the state of authentication operations. This function may be + * invoked as often as required for each boot stage. + * + * @ifrom It is also available for use by the boot ROM, both directly via + * hab_rvt.assert() and indirectly via hab_rvt.authenticate_image(). + * @endrom + * + * @par Operation + * + * This function checks the required assertion as detailed below. + * + * @param[in] type Assertion type. + * + * @param[in] data Assertion data. + * + * @param[in] count Data size or count. + * + * @par Memory block authentication: + * For #HAB_ASSERT_BLOCK assertion type, hab_rvt.assert() checks that the + * given memory block has been authenticated after running a CSF. The + * parameters are interpreted as follows: + * + * @par + * - @a data: memory block starting address + * - @a count: memory block size (in bytes) + * + * @par + * + * A simple interpretation of "memory block has been authenticated" is + * taken, such that the given block must lie wholly within a single + * contiguous block authenticated while running a CSF. A given memory + * block covered by the union of several neighboring or overlapping + * authenticated blocks could fail the test with this interpretation, but + * it is assumed that such cases will not arise in practice. + * + * @post If the assertion fails, an audit event is logged with status + * #HAB_FAILURE and reason #HAB_INV_ASSERTION, together with the call + * parameters. See the @ref evt record documentation for details. + * + * @post For successful commands, no audit event is logged. + * + * @retval #HAB_SUCCESS on an IC not configured as #HAB_CFG_CLOSED, + * although unsuccessful operations will still generate audit log events, + * + * @retval #HAB_SUCCESS on other ICs if the assertion is confirmed + * + * @retval #HAB_FAILURE otherwise + */ + hab_status_t (*assert)(hab_assertion_t type, + const void* data, + uint32_t count); + + /** Report an event from the audit log. + * @ingroup event + * + * @par Purpose + * + * This function allows the audit log to be interrogated. It is intended + * for use by post-ROM boot stage components, via the @ref rvt, to + * determine the state of authentication operations. This function may + * be called outside an hab_rvt.entry() / hab_rvt.exit() pair. + * + * @ifrom It is also available for use by the boot ROM, where it may be + * used to report boot failures as part of a tethered boot + * protocol. @endrom + * + * @par Operation + * + * This function performs the following operations: + * - Scans the audit log for a matching event + * - Copies the required details to the output parameters (if found) + * + * @param[in] status Status level of required event. + * + * @param[in] index Index of required event at given status level. + * + * @param[out] event @ref evt record. + * + * @param[in,out] bytes Size of @a event buffer on entry, size of event + * record on exit. + * + * @remark Use @a status = #HAB_STS_ANY to match any logged event, + * regardless of the status value logged. + * + * @remark Use @a index = 0 to return the first matching event, @a index = + * 1 to return the second matching event, and so on. + * + * @remark The data logged with each event is context-dependent. Refer to + * @ref evt record documentation. + * + * @warning Parameter @a bytes may not be NULL. + * + * @warning If the @a event buffer is a NULL pointer or too small to fit + * the event record, the required size is written to @a bytes, but no + * part of the event record is copied to the output buffer. + * + * @retval #HAB_SUCCESS if the required event is found, and the event + * record is copied to the output buffer. + * + * @retval #HAB_SUCCESS if the required event is found and @a event buffer + * passed is a NULL pointer. + * + * @retval #HAB_FAILURE otherwise + */ + hab_status_t (*report_event)(hab_status_t status, + uint32_t index, + uint8_t* event, + size_t* bytes); + + /** Report security status. + * @ingroup status + * + * @par Purpose + * + * This function reports the security configuration and state of the IC as + * well as searching the audit log to determine the status of the boot + * process. It is intended for use by post-ROM boot stage components, via + * the @ref rvt. This function may be called outside an + * hab_rvt.entry() / hab_rvt.exit() pair. + * + * @ifrom It is also available for use by the boot ROM, and should be used + * rather than the HAL function hab_hal_read_sec_cfg(). @endrom + * + * @par Operation + * + * This function reads the fuses which indicate the security + * configuration. The fusemap varies by IC, and should be taken from the + * @ref ref_rug. It also uses the @ref shw state machine, if present and + * enabled, to report on the security state. + * + * @param[out] config Security configuration, NULL if not required + * + * @param[out] state Security state, NULL if not required + * + * @remark If no @ref shw state machine is present and enabled, the state + * #HAB_STATE_NONE will be output. + * + * @retval #HAB_SUCCESS if no warning or failure audit events have been + * logged. + * + * @retval #HAB_WARNING otherwise, if only warning events have been logged. + * + * @retval #HAB_FAILURE otherwise + */ + hab_status_t (*report_status)(hab_config_t* config, hab_state_t* state); + + /** Enter failsafe boot mode. + * @ingroup safe + * + * @par Purpose + * + * This function provides a safe path when image authentication has failed + * and all possible boot paths have been exhausted. It is intended for + * use by post-ROM boot stage components, via the @ref rvt. + * + * @ifrom It is also available for use by the boot ROM via + * hab_rvt.failsafe(). @endrom + * + * @par Operation + * + * The precise details of this function vary by IC and core, and should be + * taken from @ref ref_rug. + * + * @warning This function does not return. + * + * @remark Since this function does not return, it implicitly performs the + * functionality of hab_rvt.exit() in order to ensure an appropriate + * configuration of the @ref shw plugins. + * + * @remark Two typical implementations are: + * - a low-level provisioning protocol in which an image is downloaded to + * RAM from an external host, authenticated and launched. The downloaded + * image may communicate with tools on the external host to report the + * reasons for boot failure, and may re-provision the end-product with + * authentic boot images. + * - a failsafe boot mode which does not allow execution to leave the ROM + * until the IC is reset. + */ + void (*failsafe)(void); +}; + +/** @ref rvt type + * @ingroup rvt + */ +typedef struct hab_rvt hab_rvt_t; + +/*---------------------------------------------------------------------------*/ + +/** @ref ivt structure + * @ingroup ivt + * + * @par Format + * + * An @ref ivt consists of a @ref hdr followed by a list of addresses as + * described further below. + * + * @warning The @a entry address may not be NULL. + * + * @warning On an IC not configured as #HAB_CFG_CLOSED, the + * @a csf address may be NULL. If it is not NULL, the @ref csf will be + * processed, but any failures should be non-fatal. + * + * @warning On an IC configured as #HAB_CFG_CLOSED, the @a + * csf address may not be NULL, and @ref csf failures are typically fatal. + * + * @remark The Boot Data located using the @a boot_data field is interpreted + * by the HAB caller in a boot-mode specific manner. This may be used by the + * boot ROM as to determine the load address and boot device configuration for + * images loaded from block devices (see @ref ref_rug for details). + * + * @remark All addresses given in the IVT, including the Boot Data (if + * present) are those for the final load location. + * + * @anchor ila + * + * @par Initial load addresses + * + * The @a self field is used to calculate addresses in boot modes where an + * initial portion of the image is loaded to an initial location. In such + * cases, the IVT, Boot Data (if present) and DCD (if present) are used in + * configuring the IC and loading the full image to its final location. Only + * the IVT, Boot Data (if present) and DCD (if present) are required to be + * within the initial image portion. + * + * The method for calculating an initial load address for the DCD is + * illustrated in the following C fragment. Similar calculations apply to + * other fields. + * +@verbatim + hab_ivt_t* ivt_initial = ; + const void* dcd_initial = ivt_initial->dcd; + if (ivt_initial->dcd != NULL) + dcd_initial = (const uint8_t*)ivt_initial + + (ivt_initial->dcd - ivt_initial->self) +@endverbatim + */ +struct hab_ivt { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + hab_hdr_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + hab_image_entry_f entry; + /** Reserved in this version of HAB: should be NULL. */ + const void* reserved1; + /** Absolute address of the image DCD: may be NULL. */ + const void* dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + const void* boot_data; + /** Absolute address of the IVT.*/ + const void* self; + /** Absolute address of the image CSF.*/ + const void* csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +}; + +/** @ref ivt type + * @ingroup ivt + */ +typedef struct hab_ivt hab_ivt_t; + +/*=========================================================================== + FUNCTION PROTOTYPES +=============================================================================*/ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* HAB_DEFINES_H */ diff --git a/bsp/imx6ul/platform/include/imx_i2c.h b/bsp/imx6ul/platform/include/imx_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..5f91a1a5f2cf72bd6ebc68dc893e4f4be55c322b --- /dev/null +++ b/bsp/imx6ul/platform/include/imx_i2c.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IMX_I2C_H__ +#define __IMX_I2C_H__ + +#include "sdk_types.h" + +//! @addtogroup diag_i2c + +//! @{ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Read/write address bits +//! +//! Bit 0 of the i2c device address cycle to indicate r/w. 0 is for write, 1 is for read. +enum _i2c_rq { + I2C_WRITE = 0, + I2C_READ = 1 +}; + +//! @brief I2C Error Codes +enum _i2c_err { + ERR_TX = -1, + ERR_RX = -2, + ERR_ARB_LOST = -3, + ERR_NO_ACK = -4, + ERR_XFER = -5, + ERR_RX_ACK = -6, + ERR_NO_ACK_ON_START = -7, + ERR_INVALID_REQUEST = -8 +}; + +//! Default slave address used for the MX6. +enum _i2c_slave_id { + IMX6_DEFAULT_SLAVE_ID = 0x60 +}; + +//! @brief Info required to talk to an I2C device. +//! +//! Pairs an I2C port number with a device address. +//! +//! While the device address is often fixed and known in advance by the driver, +//! some devices have configurable addresses that can be changed with pin +//! settings. Thus, the same device may have different adresses on different +//! boards depending on how these pins are tied. +//! +//! Note that the @a address member's value is @i not pre-shifted. The 7-bit +//! address is right aligned within the byte, and the top bit is always set to 0. +typedef struct i2c_device_info { + uint8_t port; //!< I2C controller instance to which the device is connected. Starts at 1. + uint8_t address; //!< I2C device address in lower 7 bits. + uint32_t freq; //!< Maximum transfer speed in bits per second. +} i2c_device_info_t; + +/*! + * @brief An I2C transfer descriptor. + * + * To perform an I2C transfer, the caller first fills in an instance of this struct. Then + * i2c_xfer() is called, passing a pointer to the #imx_i2c_request_t struct. + * + * @a ctl_addr should be set to either a valid controller instance number from 1 through + * the number of I2C instances on the chip, or the base address of the controller. + * + * If @a device is set to a non-NULL value, it is a pointer to an #i2c_device_info_t struct + * to use instead of the @a ctl_addr and @a dev_addr members of this struct. + */ +typedef struct imx_i2c_request { + uint32_t ctl_addr; //!< Either the I2C controller base address or instance number starting at 1. + uint32_t dev_addr; //!< The I2C device address. + uint32_t reg_addr; //!< The register address within the target device. + uint32_t reg_addr_sz; //!< Number of bytes for the address of I2C device register. + uint8_t *buffer; //!< Buffer to hold the data. + uint32_t buffer_sz; //!< The number of bytes for read/write. + int32_t (*slave_receive) (const struct imx_i2c_request *rq); //!< Function for slave to receive data from master. + int32_t (*slave_transmit) (const struct imx_i2c_request *rq); //!< Function for slave to transmit data to master. + const i2c_device_info_t * device; //!< Optional pointer to device info struct. Overrides @a ctl_addr and @a dev_addr if set. +} imx_i2c_request_t; + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize the I2C module + * + * Mainly enable the I2C clock, module itself and the I2C clock prescaler. + * + * @param base Either the base address of I2C module or the module's instance number. (also assigned for I2Cx_CLK) + * @param baud The desired data rate in bits per second. + * + * @return 0 if successful; non-zero otherwise + */ +int i2c_init(uint32_t base, uint32_t baud); + +/*! + * @brief Perform a single I2C transfer in the selected direction. + * + * This is a rather simple function that can be used for most I2C devices. + * + * Common steps for both READ and WRITE: + * - step 1: issue start signal + * - step 2: put I2C device addr on the bus (always 1 byte write. the dir always I2C_WRITE) + * - step 3: offset of the I2C device write (offset within the device. can be 1-4 bytes) + * + * For READ: + * - step 4: do repeat-start + * - step 5: send slave address again, but indicate a READ operation by setting LSB bit + * - Step 6: change to receive mode + * - Step 7: dummy read + * - Step 8: reading + * + * For WRITE: + * - Step 4: do data write + * - Step 5: generate STOP by clearing MSTA bit + * + * @param rq Pointer to #imx_i2c_request_t. + * @param dir #I2C_READ or #I2C_WRITE + * + * @return 0 on success; non-zero otherwise + */ +int i2c_xfer(const imx_i2c_request_t *rq, int dir); + +/*! + * @brief Perform I2C read transfer. + * + * @param rq Pointer to #imx_i2c_request_t. + */ +int i2c_read(const imx_i2c_request_t *rq); + +/*! + * @brief Perform I2C write transfer. + * + * @param rq Pointer to #imx_i2c_request_t. + */ +int i2c_write(const imx_i2c_request_t *rq); + +/*! + * @brief I2C handler for the slave mode. + * + * The function is based on the flow chart for typical I2C polling routine described in the + * I2C controller chapter of the reference manual. + * + * @param rq Pointer to #imx_i2c_request_t. + */ +void i2c_slave_handler(const imx_i2c_request_t *rq); + +/*! + * @brief Handle the I2C transfers in slave mode. + * + * The slave mode behaves like any device with g_addr_cycle of address + g_data_cycle of data. + * Master read = + * START - SLAVE_ID/W - ACK - MEM_ADDR - ACK - START - SLAVE_ID/R - ACK - DATAx - NACK - STOP + * + * Example for a 16-bit address access: + * - 1st IRQ - receive the slave address and Write flag from master. + * - 2nd IRQ - receive the lower byte of the requested 16-bit address. + * - 3rd IRQ - receive the higher byte of the requested 16-bit address. + * - 4th IRQ - receive the slave address and Read flag from master. + * - 5th and next IRQ - transmit the data as long as NACK and STOP is not asserted. + * + * Master write = + * START - SLAVE_ID/W - ACK - MEM_ADDR - ACK - DATAx - NACK - STOP + * + * - 1st IRQ - receive the slave address and Write flag from master. + * - 2nd IRQ - receive the lower byte of the requested 16-bit address. + * - 3rd IRQ - receive the higher byte of the requested 16-bit address. + * - 4th and next IRQ - receive the data as long STOP is not asserted. + * + * @param port Pointer to the I2C module structure. + * @param rq Pointer to #imx_i2c_request_t. + */ +void i2c_slave_xfer(imx_i2c_request_t *rq); + +//////////////////////////////////////////////////////////////////////////////// +// Board support +//////////////////////////////////////////////////////////////////////////////// + +//! @name Board support functions +//! +//! These functions are called by the driver in order to factor out board +//! specific functionality. They must be defined by the board support +//! library or the application. +//@{ +//! @brief Configure IOMUX for the I2C driver. +void i2c_iomux_config(int instance); +//@} + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif /* __IMX_I2C_H__ */ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/imx_timer.h b/bsp/imx6ul/platform/include/imx_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..ab1882349876a6ba187e6cd07e6937c11e5be349 --- /dev/null +++ b/bsp/imx6ul/platform/include/imx_timer.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +//! @addtogroup diag_timer +//! @{ + +/*! + * @file timer.h + * @brief various defines used by the timer driver. + */ + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#include "sdk.h" + +//////////////////////////////////////////////////////////////////////////////// +// Constants +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Options for low power mode support for the timers. +//! +//! These constants are bit masks that are or'd together to select in which low +//! power modes the timer will continue counting. +enum _timer_low_power_modes +{ + WAIT_MODE_EN = 1, //!< Timer is enabled in wait mode. + STOP_MODE_EN = 2 //!< Timer is enabled in stop mode. +}; + +//! @brief Available clock sources for the timers. +enum _timer_clock_sources +{ + CLKSRC_OFF = 0, //!< clock source is OFF + CLKSRC_IPG_CLK = 1, //!< clock source is peripheral clock + CLKSRC_PER_CLK = 2, //!< clock source is high-freq reference clock + CLKSRC_CLKIN = 3, //!< clock source is external from a CLKIN input + CLKSRC_CKIL = 3 //!< clock source is low-freq reference clock +}; + +//! @brief Do not enable interrupts. +#define POLLING_MODE 0 + +//////////////////////////////////////////////////////////////////////////////// +// Externs +//////////////////////////////////////////////////////////////////////////////// +extern uint32_t g_system_timer_port; + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @brief Delay for a given number of microseconds. +//! +//! system_time_init() must have been called before using this function. +//! +//! @param usecs Delay in microseconds. +void hal_delay_us(uint32_t usecs); + +//! @brief Init system timer facilities. +//! +//! Inits the EPIT timer used for delay, and inits the microsecond counter. +void system_time_init(void); + +//! @brief Return the current microsecond counter value. +//! +//! @return The number of microseconds elapsed since system_time_init() +//! was called. This value may roll over before reaching all ones. +uint64_t time_get_microseconds(); + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif // __TIMER_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/imx_uart.h b/bsp/imx6ul/platform/include/imx_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..b663bdaef3fa0858c006de1c0d8992c94f1d562b --- /dev/null +++ b/bsp/imx6ul/platform/include/imx_uart.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*! + * @file imx_uart.h + * @brief various defines used by imx_uart.c + */ + +#ifndef __IMX_UART_H__ +#define __IMX_UART_H__ + +#include "sdk.h" + +//! @addtogroup diag_uart +//! @{ + +////////////////////////////////////////////////////////////////////////// +//Constants +///////////////////////////////////////////////////////////////////////// + +/* UART specific defines */ +//! @brief Modes of the PARITY for UART transfer. +enum _uart_parity +{ + PARITY_NONE = 0, //!< PARITY mode is PARITY_NONE. + PARITY_EVEN = 2, //!< PARITY mode is PARITY_EVEN. + PARITY_ODD = 3 //!< PARITY mode is PARITY_ODD. +}; + +//! @brief Number of stopbits after a character. +enum _uart_stopbits +{ + STOPBITS_ONE = 0, //!< One stopbits after a character. + STOPBITS_TWO = 1 //!< Two stopbits after a character. +}; + +//! @brief Flow control mode for UART transfer. +enum _uart_flowctrl +{ + FLOWCTRL_OFF = 0, //!< Flow control off for UART transfer. + FLOWCTRL_ON = 1 //!< Flow control on for UART transfer. +}; + +//! @brief Specify the FIFO for UART transfer. +enum _uart_fifo +{ + TX_FIFO = 0, //!< Config the TX fifo for UART transfer. + RX_FIFO = 1 //!< Config the RX fifo for UART transfer. +}; + +//! @brief Specify the number of bits in a data +enum _uart_bits +{ + SEVENBITS = 0, //!< Config seven bits in a data. + EIGHTBITS = 1 //!< Config eight bits in a data. +}; + +//! @brief Specify the service mode +#define DMA_MODE 2 //!< Config the service mode for dma request. +#define IRQ_MODE 1 //!< Config the service mode for interrupt. + +#define UART_MODULE_CLK(x) ((x) == HW_UART1 ? UART1_MODULE_CLK : (x) == HW_UART2 ? UART2_MODULE_CLK : (x) == HW_UART3 ? UART3_MODULE_CLK : (x) == HW_UART4 ? UART4_MODULE_CLK : -1) + +#define UART_IRQS(x) ((x) == HW_UART1 ? IMX_INT_UART1 : (x) == HW_UART2 ? IMX_INT_UART2 : (x) == HW_UART3 ? IMX_INT_UART3 : (x) == HW_UART4 ? IMX_INT_UART4 : (x) == HW_UART5 ? IMX_INT_UART5 : 0xFFFFFFFF) + +////////////////////////////////////////////////////////////////////////// +//API +///////////////////////////////////////////////////////////////////////// + + +/*! + * @brief Initialize the UART port + * + * @param instance the UART instance number. + * @param baudrate serial baud rate such 9600, 57600, 115200, etc. + * @param parity enable parity checking: PARITY_NONE, PARITY_EVEN, + * PARITY_ODD. + * @param stopbits number of stop bits: STOPBITS_ONE, STOPBITS_TWO. + * @param datasize number of bits in a data: SEVENBITS, EIGHTBITS, + * NINEBITS (like RS-485 but not supported). + * @param flowcontrol enable (RTS/CTS) hardware flow control: + * FLOWCTRL_ON, FLOWCTRL_OFF. + */ +void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity,uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol); + +/*! + * @brief Output a character to UART port + * + * @param instance the UART instance number. + * @param ch pointer to the character for output + * @return the character that has been sent + */ +uint8_t uart_putchar(uint32_t instance, uint8_t * ch); + +/*! + * @brief Receive a character on the UART port + * + * @param instance the UART instance number. + * @return a character received from the UART port; if the RX FIFO + * is empty or errors are detected, it returns NONE_CHAR + */ +uint8_t uart_getchar(uint32_t instance); + +/*! + * @brief Configure the RX or TX FIFO level and trigger mode + * + * @param instance the UART instance number. + * @param fifo FIFO to configure: RX_FIFO or TX_FIFO. + * @param trigger_level set the trigger level of the FIFO to generate + * an IRQ or a DMA request: number of characters. + * @param service_mode FIFO served with DMA or IRQ or polling (default). + */ +void uart_set_FIFO_mode(uint32_t instance, uint8_t fifo, uint8_t trigger_level, + uint8_t service_mode); + +/*! + * @brief Enables UART loopback test mode + * + * @param instance the UART instance number. + * @param state enable/disable the loopback mode + */ +void uart_set_loopback_mode(uint32_t instance, uint8_t state); + +/*! + * @brief Setup UART interrupt. It enables or disables the related HW module + * interrupt, and attached the related sub-routine into the vector table. + * + * @param instance the UART instance number. + * @param irq_subroutine the UART interrupt interrupt routine. + * @param state ENABLE or DISABLE the interrupt. + */ +void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), uint8_t state); + + +/*! + * @brief Obtain UART reference frequency + * + * @param instance the UART instance number. + * @return reference frequency in Hz + */ +uint32_t uart_get_reffreq(uint32_t instance); + +//! @name Board support functions +//! +//! These functions are called by the driver in order to factor out board +//! specific functionality. They must be defined by the board support +//! library or the application. +//@{ +//! @brief Configure IOMUX for the UART driver. +void uart_iomux_config(int instance); +//@} + +//! @} + +#endif //__IMX_UART_H__ diff --git a/bsp/imx6ul/platform/include/interrupt.h b/bsp/imx6ul/platform/include/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..318e34f3bd65e1c757a32d4df24e63ac9dcbb7b0 --- /dev/null +++ b/bsp/imx6ul/platform/include/interrupt.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2009-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include "sdk_types.h" +#include "irq_numbers.h" + +//! @addtogroup diag_interrupt +//! @{ + +/*! + * @file interrupt.h + * @brief Interface for the interrupt manager. + */ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief +typedef enum { + CPU_0, + CPU_1, + CPU_2, + CPU_3, +} cpuid_e; + +//! @brief Interrupt service routine. +typedef void (*irq_hdlr_t) (void); + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @brief Enable an interrupt. +//! +//! Sets the interrupt priority and makes it non-secure. Then the interrupt is +//! enabled on the CPU specified by @a cpu_id. +//! +//! @param irq_id The interrupt number to enable. +//! @param cpu_id The index of the CPU for which the interrupt will be enabled. +//! @param priority The interrupt priority, from 0-255. Lower numbers have higher priority. +void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority); + +//! @brief Disable an interrupt on the specified CPU. +//! +//! @param irq_id The interrupt number to disabled. +//! @param cpu_id The index of the CPU for which the interrupt will be disabled. +void disable_interrupt(uint32_t irq_id, uint32_t cpu_id); + +//! @brief Set the interrupt service routine for the specified interrupt. +//! +//! @param irq_id The interrupt number. +//! @param isr Function that will be called to handle the interrupt. +void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr); + +//! @brief Interrupt handler that simply prints a message. +void default_interrupt_routine(void); + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/io.h b/bsp/imx6ul/platform/include/io.h new file mode 100644 index 0000000000000000000000000000000000000000..e4f2dc595ac92d6abe6b930d6ab7c57920ee724e --- /dev/null +++ b/bsp/imx6ul/platform/include/io.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file io.h + * @brief Register access macros. + * + * @ingroup diag_init + */ +#ifndef __IO_H__ +#define __IO_H__ + +#include "sdk_types.h" +#include +#include +#include +#include "sdk.h" + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @name Register read functions +//@{ +#define reg8_read(addr) *((volatile uint8_t *)(addr)) +#define reg16_read(addr) *((volatile uint16_t *)(addr)) +#define reg32_read(addr) *((volatile uint32_t *)(addr)) +//@} + +//! @name Register write functions +//@{ +#define reg8_write(addr,val) *((volatile uint8_t *)(addr)) = (val) +#define reg16_write(addr,val) *((volatile uint16_t *)(addr)) = (val) +#define reg32_write(addr,val) *((volatile uint32_t *)(addr)) = (val) +//@} + +//! @name Memory read functions +//@{ +#define mem8_read(addr) *((volatile uint8_t *)(addr)) +#define mem16_read(addr) *((volatile uint16_t *)(addr)) +#define mem32_read(addr) *((volatile uint32_t *)(addr)) +//@} + +//! @name Memory write functions +//@{ +#define mem8_write(addr,val) *((volatile uint8_t *)(addr)) = (val) +#define mem16_write(addr,val) *((volatile uint16_t *)(addr)) = (val) +#define mem32_write(addr,val) *((volatile uint32_t *)(addr)) = (val) +//@} + +//! @name Read functions +//@{ +#define readb(a) reg8_read(a) +#define readw(a) reg16_read(a) +#define readl(a) reg32_read(a) +//@} + +//! @name Write functrions +//! +//! The prefered method to access registers. +//@{ +#define writeb(v, a) reg8_write(a, v) +#define writew(v, a) reg16_write(a, v) +#define writel(v, a) reg32_write(a, v) +//@} + +//! @name Bit set/clear functions +//@{ +#define reg8setbit(addr,bitpos) \ + reg8_write((addr),(reg8_read((addr)) | (1<<(bitpos)))) + +#define reg16setbit(addr,bitpos) \ + reg16_write((addr),(reg16_read((addr)) | (1<<(bitpos)))) + +#define reg32setbit(addr,bitpos) \ + reg32_write((addr),(reg32_read((addr)) | (1<<(bitpos)))) + +#define reg8clrbit(addr,bitpos) \ + reg8_write((addr),(reg8_read((addr)) & (0xFF ^ (1<<(bitpos))))) + +#define reg16clrbit(addr,bitpos) \ + reg16_write((addr),(reg16_read((addr)) & (0xFFFF ^ (1<<(bitpos))))) + +#define reg32clrbit(addr,bitpos) \ + reg32_write((addr),(reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos))))) +//@} + +//! @name Masked write functions +//@{ +#define reg8_write_mask(addr, data, mask) \ + reg8_write((addr),((reg8_read(addr) & (~mask)) | (mask & data))) + +#define reg16_write_mask(addr, data, mask) \ + reg16_write((addr),((reg16_read(addr) & (~mask)) | (mask & data))) + +#define reg32_write_mask(addr, data, mask) \ + reg32_write((addr),((reg32_read(addr) & (~mask)) | (mask & data))) + +#define gen_msk32(start, end) ((0xFFFFFFFF << (start)) ^ (0xFFFFFFFF << ((end + 1)))) +#define reg32_set_field(addr, start, end, val) \ + reg32_write_mask(addr, (val) << (start), gen_msk32((start, end))) +//@} + +/*! + * This macro is used to get certain bit field from a number + */ +#define GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1)) + +/*! + * This macro is used to set certain bit field inside a number + */ +#define SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh)) + +#endif // __IO_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/mx6ul/ccm_pll_reg_define.h b/bsp/imx6ul/platform/include/mx6ul/ccm_pll_reg_define.h new file mode 100644 index 0000000000000000000000000000000000000000..87237ad1a2de539ae88c1bee20337462b97a4cd6 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/ccm_pll_reg_define.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. +*/ + +#ifndef _CCM_PLL_REG_DEFINE_H_ +#define _CCM_PLL_REG_DEFINE_H_ + +//######################################### +//# DPLLIP peripheral defines +//######################################### +#define DPLLIP_DP_CTL_OFFSET 0x000 +#define DPLLIP_DP_CONFIG_OFFSET 0x004 +#define DPLLIP_DP_OP_OFFSET 0x008 +#define DPLLIP_DP_MFD_OFFSET 0x00C +#define DPLLIP_DP_MFN_OFFSET 0x010 +#define DPLLIP_DP_MFNMINUS_OFFSET 0x014 +#define DPLLIP_DP_MFNPLUS_OFFSET 0x018 +#define DPLLIP_DP_HFS_OP_OFFSET 0x01C +#define DPLLIP_DP_HFS_MFD_OFFSET 0x020 +#define DPLLIP_DP_HFS_MFN_OFFSET 0x024 +#define DPLLIP_DP_MFN_TOGC_OFFSET 0x028 +#define DPLLIP_DP_DESTAT_OFFSET 0x02C + +#define DPLLIP1_DP_CONFIG DPLLIP1_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET +#define DPLLIP1_DP_CTL DPLLIP1_BASE_ADDR+DPLLIP_DP_CTL_OFFSET +#define DPLLIP1_DP_OP DPLLIP1_BASE_ADDR+DPLLIP_DP_OP_OFFSET +#define DPLLIP1_DP_MFD DPLLIP1_BASE_ADDR+DPLLIP_DP_MFD_OFFSET +#define DPLLIP1_DP_MFN DPLLIP1_BASE_ADDR+DPLLIP_DP_MFN_OFFSET + +#define DPLLIP2_DP_CONFIG DPLLIP2_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET +#define DPLLIP2_DP_CTL DPLLIP2_BASE_ADDR+DPLLIP_DP_CTL_OFFSET +#define DPLLIP2_DP_OP DPLLIP2_BASE_ADDR+DPLLIP_DP_OP_OFFSET +#define DPLLIP2_DP_MFD DPLLIP2_BASE_ADDR+DPLLIP_DP_MFD_OFFSET +#define DPLLIP2_DP_MFN DPLLIP2_BASE_ADDR+DPLLIP_DP_MFN_OFFSET + +#define DPLLIP3_DP_CONFIG DPLLIP3_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET +#define DPLLIP3_DP_CTL DPLLIP3_BASE_ADDR+DPLLIP_DP_CTL_OFFSET +#define DPLLIP3_DP_OP DPLLIP3_BASE_ADDR+DPLLIP_DP_OP_OFFSET +#define DPLLIP3_DP_MFD DPLLIP3_BASE_ADDR+DPLLIP_DP_MFD_OFFSET +#define DPLLIP3_DP_MFN DPLLIP3_BASE_ADDR+DPLLIP_DP_MFN_OFFSET + +//######################################### +//# CCM peripheral defines +//######################################### +#define CCM_CCR_OFFSET 0x00 +#define CCM_CCDR_OFFSET 0x04 +#define CCM_CSR_OFFSET 0x08 +#define CCM_CCSR_OFFSET 0x0C +#define CCM_CACRR_OFFSET 0x10 +#define CCM_CBCDR_OFFSET 0x14 +#define CCM_CBCMR_OFFSET 0X18 +#define CCM_CSCMR1_OFFSET 0x1c +#define CCM_CSCMR2_OFFSET 0x20 +#define CCM_CSCDR1_OFFSET 0x24 +#define CCM_CS1CDR_OFFSET 0x28 +#define CCM_CS2CDR_OFFSET 0x2c +#define CCM_CDCDR_OFFSET 0x30 +#define CCM_CHSCCDR_OFFSET 0x34 +#define CCM_CSCDR2_OFFSET 0x38 +#define CCM_CSCDR3_OFFSET 0x3c +#define CCM_CSCDR4_OFFSET 0x40 +#define CCM_CWDR_OFFSET 0x44 +#define CCM_CDHIPR_OFFSET 0x48 +#define CCM_CDCR_OFFSET 0x4c +#define CCM_CTOR_OFFSET 0x50 +#define CCM_CLPCR_OFFSET 0x54 +#define CCM_CISR_OFFSET 0x58 +#define CCM_CIMR_OFFSET 0x5c +#define CCM_CCOSR_OFFSET 0x60 +#define CCM_CGPR_OFFSET 0x64 +#define CCM_CCGR0_OFFSET 0x68 +#define CCM_CCGR1_OFFSET 0x6c +#define CCM_CCGR2_OFFSET 0x70 +#define CCM_CCGR3_OFFSET 0x74 +#define CCM_CCGR4_OFFSET 0x78 +#define CCM_CCGR5_OFFSET 0x7c +#define CCM_CCGR6_OFFSET 0x80 +#define CCM_CCGR7_OFFSET 0x84 +#define CCM_CMEOR_OFFSET 0x88 + +#define CCM_CCR CCM_BASE_ADDR+CCM_CCR_OFFSET +#define CCM_CCDR CCM_BASE_ADDR+CCM_CCDR_OFFSET +#define CCM_CSR CCM_BASE_ADDR+CCM_CSR_OFFSET +#define CCM_CCSR CCM_BASE_ADDR+CCM_CCSR_OFFSET +#define CCM_CACRR CCM_BASE_ADDR+CCM_CACRR_OFFSET +#define CCM_CBCDR CCM_BASE_ADDR+CCM_CBCDR_OFFSET +#define CCM_CBCMR CCM_BASE_ADDR+CCM_CBCMR_OFFSET +#define CCM_CSCMR1 CCM_BASE_ADDR+CCM_CSCMR1_OFFSET +#define CCM_CSCMR2 CCM_BASE_ADDR+CCM_CSCMR2_OFFSET +#define CCM_CSCDR1 CCM_BASE_ADDR+CCM_CSCDR1_OFFSET +#define CCM_CS1CDR CCM_BASE_ADDR+CCM_CS1CDR_OFFSET +#define CCM_CS2CDR CCM_BASE_ADDR+CCM_CS2CDR_OFFSET +#define CCM_CDCDR CCM_BASE_ADDR+CCM_CDCDR_OFFSET +#define CCM_CHSCCDR CCM_BASE_ADDR+CCM_CHSCCDR_OFFSET +#define CCM_CSCDR2 CCM_BASE_ADDR+CCM_CSCDR2_OFFSET +#define CCM_CSCDR3 CCM_BASE_ADDR+CCM_CSCDR3_OFFSET +#define CCM_CSCDR4 CCM_BASE_ADDR+CCM_CSCDR4_OFFSET +#define CCM_CWDR CCM_BASE_ADDR+CCM_CWDR_OFFSET +#define CCM_CDHIPR CCM_BASE_ADDR+CCM_CDHIPR_OFFSET +#define CCM_CDCR CCM_BASE_ADDR+CCM_CDCR_OFFSET +#define CCM_CTOR CCM_BASE_ADDR+CCM_CTOR_OFFSET +#define CCM_CLPCR CCM_BASE_ADDR+CCM_CLPCR_OFFSET +#define CCM_CISR CCM_BASE_ADDR+CCM_CISR_OFFSET +#define CCM_CIMR CCM_BASE_ADDR+CCM_CIMR_OFFSET +#define CCM_CCOSR CCM_BASE_ADDR+CCM_CCOSR_OFFSET +#define CCM_CGPR CCM_BASE_ADDR+CCM_CGPR_OFFSET +#define CCM_CCGR0 CCM_BASE_ADDR+CCM_CCGR0_OFFSET +#define CCM_CCGR1 CCM_BASE_ADDR+CCM_CCGR1_OFFSET +#define CCM_CCGR2 CCM_BASE_ADDR+CCM_CCGR2_OFFSET +#define CCM_CCGR3 CCM_BASE_ADDR+CCM_CCGR3_OFFSET +#define CCM_CCGR4 CCM_BASE_ADDR+CCM_CCGR4_OFFSET +#define CCM_CCGR5 CCM_BASE_ADDR+CCM_CCGR5_OFFSET +#define CCM_CCGR6 CCM_BASE_ADDR+CCM_CCGR6_OFFSET +#define CCM_CCGR7 CCM_BASE_ADDR+CCM_CCGR7_OFFSET +#define CCM_CMEOR CCM_BASE_ADDR+CCM_CMEOR_OFFSET + +//######################################### +//# CCM peripheral defines used by prog_pll.c and hardware.c +//######################################### +#define CLKCTL_CCGR1 CCM_CCGR1_OFFSET +#define CLKCTL_CSCMR1 CCM_CSCMR1_OFFSET +#define CLKCTL_CSCDR1 CCM_CSCDR1_OFFSET +#define CLKCTL_CBCMR CCM_CBCMR_OFFSET +#define CLKCTL_CBCDR CCM_CBCDR_OFFSET +#define CLKCTL_CCSR CCM_CCSR_OFFSET +#define CLKCTL_CDHIPR CCM_CDHIPR_OFFSET +#define CLKCTL_CACRR CCM_CACRR_OFFSET +#define CLKCTL_CSCDR2 CCM_CSCDR2_OFFSET +#define CLKCTL_CS1CDR CCM_CS1CDR_OFFSET +#define CLKCTL_CS2CDR CCM_CS2CDR_OFFSET + +#define CLKCTL_CSCMR2 CCM_CSCMR2_OFFSET + +#define PLL1_BASE_ADDR DPLLIP1_BASE_ADDR +#define PLL2_BASE_ADDR DPLLIP2_BASE_ADDR +#define PLL3_BASE_ADDR DPLLIP3_BASE_ADDR +#define PLL4_BASE_ADDR DPLLIP4_BASE_ADDR + +#define PLL_DP_CTL DPLLIP_DP_CTL_OFFSET +#define PLL_DP_CONFIG DPLLIP_DP_CONFIG_OFFSET +#define PLL_DP_OP DPLLIP_DP_OP_OFFSET +#define PLL_DP_MFD DPLLIP_DP_MFD_OFFSET +#define PLL_DP_MFN DPLLIP_DP_MFN_OFFSET +#define PLL_DP_MFNMINUS DPLLIP_DP_MFNMINUS_OFFSET +#define PLL_DP_MFNPLUS DPLLIP_DP_MFNPLUS_OFFSET +#define PLL_DP_HFS_OP DPLLIP_DP_HFS_OP_OFFSET +#define PLL_DP_HFS_MFD DPLLIP_DP_HFS_MFD_OFFSET +#define PLL_DP_HFS_MFN DPLLIP_DP_HFS_MFN_OFFSET +#define PLL_DP_TOGC DPLLIP_DP_MFN_TOGC_OFFSET +#define PLL_DP_DESTAT DPLLIP_DP_DESTAT_OFFSET + +#endif diff --git a/bsp/imx6ul/platform/include/mx6ul/fsl_bitaccess.h b/bsp/imx6ul/platform/include/mx6ul/fsl_bitaccess.h new file mode 100644 index 0000000000000000000000000000000000000000..ef70794521776f645b068a17452871b796f18171 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/fsl_bitaccess.h @@ -0,0 +1,472 @@ +/* + * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_BITACCESS_H +#define _FSL_BITACCESS_H 1 + +#include +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* + * Macros for single instance registers + */ + +#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) +#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) +#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) + +#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) +#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) +#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) + +#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BF_RD(reg, field) HW_##reg.B.field +#define BF_WR(reg, field, v) BW_##reg##_##field(v) + +#define BF_CS1(reg, f1, v1) \ + (HW_##reg##_CLR(BM_##reg##_##f1), \ + HW_##reg##_SET(BF_##reg##_##f1(v1))) + +#define BF_CS2(reg, f1, v1, f2, v2) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +/* + * Macros for multiple instance registers + */ + +#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) +#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) +#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) + +#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) +#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) +#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) + +#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym + +#define BF_RDn(reg, n, field) HW_##reg(n).B.field +#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) + +#define BF_CS1n(reg, n, f1, v1) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) + +#define BF_CS2n(reg, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +/* + * Macros for single instance MULTI-BLOCK registers + */ + +#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) +#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) +#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) + +#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) +#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) +#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) + +#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field +#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) + +#define BFn_CS1(reg, blk, f1, v1) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) + +#define BFn_CS2(reg, blk, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +/* + * Macros for MULTI-BLOCK multiple instance registers + */ + +#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) +#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) +#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) + +#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) +#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) +#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) + +#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field +#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) + +#define BFn_CS1n(reg, blk, n, f1, v1) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) + +#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +#endif /* _FSL_BITACCESS_H */ + +/******************************************************************************/ diff --git a/bsp/imx6ul/platform/include/mx6ul/functions.h b/bsp/imx6ul/platform/include/mx6ul/functions.h new file mode 100644 index 0000000000000000000000000000000000000000..ab162a082b824c71953b284806192dda8cf9312e --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/functions.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. +*/ + +/*! + * @file functions.h + * @brief This header file contains functions info. + * + */ +#ifndef FUNCTIONS_H +#define FUNCTIONS_H + +//---------------------------------------------------------------------- +// Some Genaral Macros +//---------------------------------------------------------------------- +//#define FALSE 0 +//#define TRUE 1 + +#define DUMMY_INFO 0xf00f00 + +#define reg8_read(addr) *((BYTE *)(addr)) +#define reg16_read(addr) *((HALF *)(addr)) +#define reg32_read(addr) *(WORD *)((addr)) + +#define reg32_read_bit(addr,bitpos) (reg32_read(addr) & (1<<(bitpos))) + +#define reg8_write(addr,val) *((BYTE *)(addr)) = (val) +#define reg16_write(addr,val) *((HALF *)(addr)) = (val) +#define reg32_write(addr,val) *((WORD *)(addr)) = (val) + +#define mem8_read(addr) *((BYTE *)(addr)) +#define mem16_read(addr) *((HALF *)(addr)) +#define mem32_read(addr) *(WORD *)((addr)) + +#define mem8_write(addr,val) *((BYTE *)(addr)) = (val) +#define mem16_write(addr,val) *((HALF *)(addr)) = (val) +#define mem32_write(addr,val) *((WORD *)(addr)) = (val) + +#define reg8setbit(addr,bitpos) \ + reg8_write((addr),(reg8_read((addr)) | (1<<(bitpos)))) + +#define reg16setbit(addr,bitpos) \ + reg16_write((addr),(reg16_read((addr)) | (1<<(bitpos)))) + +#define reg32setbit(addr,bitpos) \ + reg32_write((addr),(reg32_read((addr)) | (1<<(bitpos)))) + +#define reg8clrbit(addr,bitpos) \ + reg8_write((addr),(reg8_read((addr)) & (0xFF ^ (1<<(bitpos))))) + +#define reg16clrbit(addr,bitpos) \ + reg16_write((addr),(reg16_read((addr)) & (0xFFFF ^ (1<<(bitpos))))) + +#define reg32clrbit(addr,bitpos) \ + reg32_write((addr),(reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos))))) + +// ##### EXPORTED TYPE DEFINITIONS ################################################# {{{1 + +typedef volatile unsigned long WORD; +typedef volatile unsigned short HALF; +typedef volatile unsigned char BYTE; + +//---------------------------------------------------------------------- +// Write With Mask (write only certain bits) +//---------------------------------------------------------------------- +void reg8_write_mask(WORD addr, BYTE wdata, BYTE mask); +void reg16_write_mask(WORD addr, HALF wdata, HALF mask); +void reg32_write_mask(WORD addr, WORD wdata, WORD mask); + +#endif //FUNCTIONS_H diff --git a/bsp/imx6ul/platform/include/mx6ul/gpio_define.h b/bsp/imx6ul/platform/include/mx6ul/gpio_define.h new file mode 100644 index 0000000000000000000000000000000000000000..72050f371c8c66e7075022cba53262cb3dadff30 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/gpio_define.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. +*/ + +#ifndef _GPIO_DEFINE_H_ +#define _GPIO_DEFINE_H_ + +#if 0 +#define GPIO_DR_OFFSET 0x0000 +#define GPIO_GDIR_OFFSET 0x0004 +#define GPIO_PSR_OFFSET 0x0008 +#endif + +typedef enum { + GPIO_PORT1 = 0, + GPIO_PORT2 = 1, + GPIO_PORT3 = 2, + GPIO_PORT4 = 3, + GPIO_PORT5 = 4, + GPIO_PORT6 = 5, + GPIO_PORT7 = 6, +} GPIO_PORT; + +typedef struct { + unsigned int DR; + unsigned int GDIR; + unsigned int PSR; + unsigned int ICR1; + unsigned int ICR2; + unsigned int IMR; + unsigned int ISR; + unsigned int EDGE_SEL; +} CSP_GPIO_REGS, *PCSP_GPIO_REGS; + +#define GPIO_GDIR_INPUT 0 // GPIO pin is input +#define GPIO_GDIR_OUTPUT 1 // GPIO pin is output + +#define GPIO_LOW_LEVEL 0 // GPIO pin is low +#define GPIO_HIGH_LEVEL 1 // GPIO pin is high + +#define GPIO_ICR_LOW_LEVEL 0 // Interrupt is low-level +#define GPIO_ICR_HIGH_LEVEL 1 // Interrupt is high-level +#define GPIO_ICR_RISE_EDGE 2 // Interrupt is rising edge +#define GPIO_ICR_FALL_EDGE 3 // Interrupt is falling edge + +#define GPIO_IMR_MASKED 0 // Interrupt is masked +#define GPIO_IMR_UNMASKED 1 // Interrupt is unmasked + +#define GPIO_EDGE_SEL_DISABLE 0 // Edge select is disabled +#define GPIO_EDGE_SEL_ENABLE 1 // Edge select is enabled + +#define GPIO_PIN_MASK(pin) (1U << (pin)) +#define GPIO_PIN_VAL(val, pin) ((val) << (pin)) +#define GPIO_ICR_MASK(pin) (0x3U << ((pin) << 1)) +#define GPIO_ICR_VAL(val, pin) ((val) << ((pin) << 1)) + +//######################################### +//# GPIO peripheral defines +//######################################### +#define GPIO_DR0_OFFSET 0x00 // 32bit gpio pta data direction reg +#define GPIO_GDIR0_OFFSET 0x04 // 32bit gpio pta output config 1 reg +#define GPIO_PSR0_OFFSET 0x08 // 32bit gpio pta output config 2 reg +#define GPIO_ICR1_OFFSET 0x0C // 32bit gpio pta input config A1 reg +#define GPIO_ICR2_OFFSET 0x10 // 32bit gpio pta input config A2 reg +#define GPIO_IMR_OFFSET 0x14 // 32bit gpio pta input config B1 reg +#define GPIO_ISR_OFFSET 0x18 // GPIO Interrupt Status Register +#define GPIO_EDGE_SEL_OFFSET 0x1C // GPIO Edge Detect Register + +#define GPIO1_DR GPIO1_BASE_ADDR+0x00 +#define GPIO1_GDIR GPIO1_BASE_ADDR+0x04 +#define GPIO1_PSR GPIO1_BASE_ADDR+0x08 +#define GPIO1_ICR1 GPIO1_BASE_ADDR+0x0C +#define GPIO1_ICR2 GPIO1_BASE_ADDR+0x10 +#define GPIO1_IMR GPIO1_BASE_ADDR+0x14 +#define GPIO1_ISR GPIO1_BASE_ADDR+0x18 +#define GPIO1_EDGE_SEL GPIO1_BASE_ADDR+0x1C + +#define GPIO2_DR GPIO2_BASE_ADDR+0x00 +#define GPIO2_GDIR GPIO2_BASE_ADDR+0x04 +#define GPIO2_PSR GPIO2_BASE_ADDR+0x08 +#define GPIO2_ICR1 GPIO2_BASE_ADDR+0x0C +#define GPIO2_ICR2 GPIO2_BASE_ADDR+0x10 +#define GPIO2_IMR GPIO2_BASE_ADDR+0x14 +#define GPIO2_ISR GPIO2_BASE_ADDR+0x18 +#define GPIO2_EDGE_SEL GPIO2_BASE_ADDR+0x1C + +#define GPIO3_DR GPIO3_BASE_ADDR+0x00 +#define GPIO3_GDIR GPIO3_BASE_ADDR+0x04 +#define GPIO3_PSR GPIO3_BASE_ADDR+0x08 +#define GPIO3_ICR1 GPIO3_BASE_ADDR+0x0C +#define GPIO3_ICR2 GPIO3_BASE_ADDR+0x10 +#define GPIO3_IMR GPIO3_BASE_ADDR+0x14 +#define GPIO3_ISR GPIO3_BASE_ADDR+0x18 +#define GPIO3_EDGE_SEL GPIO3_BASE_ADDR+0x1C + +#define GPIO4_DR GPIO4_BASE_ADDR+0x00 +#define GPIO4_GDIR GPIO4_BASE_ADDR+0x04 +#define GPIO4_PSR GPIO4_BASE_ADDR+0x08 +#define GPIO4_ICR1 GPIO4_BASE_ADDR+0x0C +#define GPIO4_ICR2 GPIO4_BASE_ADDR+0x10 +#define GPIO4_IMR GPIO4_BASE_ADDR+0x14 +#define GPIO4_ISR GPIO4_BASE_ADDR+0x18 +#define GPIO4_EDGE_SEL GPIO4_BASE_ADDR+0x1C + +#define GPIO5_DR GPIO5_BASE_ADDR+0x00 +#define GPIO5_GDIR GPIO5_BASE_ADDR+0x04 +#define GPIO5_PSR GPIO5_BASE_ADDR+0x08 +#define GPIO5_ICR1 GPIO5_BASE_ADDR+0x0C +#define GPIO5_ICR2 GPIO5_BASE_ADDR+0x10 +#define GPIO5_IMR GPIO5_BASE_ADDR+0x14 +#define GPIO5_ISR GPIO5_BASE_ADDR+0x18 +#define GPIO5_EDGE_SEL GPIO5_BASE_ADDR+0x1C + +#define GPIO6_DR GPIO6_BASE_ADDR+0x00 +#define GPIO6_GDIR GPIO6_BASE_ADDR+0x04 +#define GPIO6_PSR GPIO6_BASE_ADDR+0x08 +#define GPIO6_ICR1 GPIO6_BASE_ADDR+0x0C +#define GPIO6_ICR2 GPIO6_BASE_ADDR+0x10 +#define GPIO6_IMR GPIO6_BASE_ADDR+0x14 +#define GPIO6_ISR GPIO6_BASE_ADDR+0x18 +#define GPIO6_EDGE_SEL GPIO6_BASE_ADDR+0x1C + +#define GPIO7_DR GPIO7_BASE_ADDR+0x00 +#define GPIO7_GDIR GPIO7_BASE_ADDR+0x04 +#define GPIO7_PSR GPIO7_BASE_ADDR+0x08 +#define GPIO7_ICR1 GPIO7_BASE_ADDR+0x0C +#define GPIO7_ICR2 GPIO7_BASE_ADDR+0x10 +#define GPIO7_IMR GPIO7_BASE_ADDR+0x14 +#define GPIO7_ISR GPIO7_BASE_ADDR+0x18 +#define GPIO7_EDGE_SEL GPIO7_BASE_ADDR+0x1C + +#endif diff --git a/bsp/imx6ul/platform/include/mx6ul/hardware.h b/bsp/imx6ul/platform/include/mx6ul/hardware.h new file mode 100644 index 0000000000000000000000000000000000000000..86507e399020650b7539369b402d63bd2c4364cb --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/hardware.h @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. +*/ + +/*! + * @file hardware.h + * @brief header file with chip defines to be included by all the tests/utils + * + * @ingroup diag_init + */ + +#ifndef HARDWARE_H_ +#define HARDWARE_H_ +#include "soc_memory_map.h" +#include "functions.h" +#include "io.h" +#include "iomux_define.h" +#include "iomux_register.h" + +#include "iomux_config.h" +#include "gpio_define.h" +#include "ccm_pll_reg_define.h" +#include "imx_i2c.h" +#include "imx_spi.h" +#include "imx_sata.h" +#include "pmic.h" +#include "regsgpmi.h" +#include "regsapbh.h" + +#define ESDCTL_ESDSCR_OFFSET 0x1C +// PLL definitions +#define HW_ANADIG_USB1_PLL_480_CTRL_RW (ANATOP_IPS_BASE_ADDR+0x10) +#define HW_ANADIG_PLL_528_RW (ANATOP_IPS_BASE_ADDR+0x30) +#define HW_ANADIG_PLL_528_NUM (ANATOP_IPS_BASE_ADDR+0x50) +#define HW_ANADIG_PLL_528_DENOM (ANATOP_IPS_BASE_ADDR+0x60) +#define HW_ANADIG_PFD_528_RW (ANATOP_IPS_BASE_ADDR+0x100) +#define HW_ANADIG_PLL_SYS_RW (ANATOP_IPS_BASE_ADDR+0x000) + +#define HW_ANADIG_REG_CORE (ANATOP_IPS_BASE_ADDR + 0x140) +#define HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(x) ((((x)-700)/25) << 0) +#define HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(x) ((((x)-700)/25) << 18) +#define HW_ANADIG_REG_CORE_V_CORE_MSK 0x1F +#define HW_ANADIG_REG_CORE_V_SOC_MSK (0x1F << 18) + +// audio defines +#define WM8960_I2C_DEV_ADDR (0x34>>1) +#define WM8960_I2C_BASE_ADDR I2C2_BASE_ADDR + +#define WM8958_I2C_DEV_ADDR (0x34>>1) +#define WM8958_I2C_BASE_ADDR I2C1_BASE_ADDR + +#define WM8962_I2C_DEV_ADDR (0x34>>1) +#define WM8962_I2C_BASE_ADDR I2C4_BASE_ADDR + +#define SGTL5000_I2C_BASE I2C1_BASE_ADDR // audio codec on i2c1 +#define SGTL5000_I2C_ID 0x0A + +// SGTL5000 specific register values +#define CHIP_REF_CTRL_REG_VALUE 0x01FF // VDDA/2 +#define CHIP_LINE_OUT_CTRL_REG_VALUE 0x0322 // VDDIO/2 +#define CHIP_LINE_OUT_VOL_REG_VALUE 0x0F0F // based on VDDA and VDDIO values +#define CHIP_CLK_TOP_CTRL_REG_VALUE 0 // pass through, Input OSC 13.5MHz, default configuration for sample rate, 48KHz +#define CHIP_PLL_CTRL_REG_VALUE ((14 << 11) | (1154)) +#define CHIP_CLK_CTRL_REG_VALUE ((0x2 << 2) | (0x3)) +#define CHIP_CLK_CTRL_REG_MCLK_FREQ_VALUE 0x3 /*12MHz =256*Fs */ +#define CHIP_PLL_CTRL_REG_VALUE2 ((16 << 11) | (786)) // for CodecInit2 + +#define SI476x_I2C_BASE I2C2_BASE_ADDR +#define SI476x_I2C_ID (0xC6 >> 1) + +#define OS81050_I2C_BASE I2C3_BASE_ADDR +#define OS81050_I2C_ID (0x40 >> 1) + +#define ADV7180_I2C_BASE I2C3_BASE_ADDR +#define ADV7180_I2C_ID (0x42 >> 1) + +#if defined(SABRE_LITE) +#define P1003_TSC_I2C_BASE I2C3_BASE_ADDR +#else //default SABRE_AI +#define P1003_TSC_I2C_BASE I2C2_BASE_ADDR +#endif +#define P1003_TSC_I2C_ID 4 + +// MAX7310 I2C settings +/* For the SABRE AI board which has 3 MAX7310 */ +#ifdef SABRE_AI +#define MAX7310_NBR 3 +#define MAX7310_I2C_BASE_ID0 I2C3_BASE_ADDR +#define MAX7310_I2C_ID0 0x30 +#define MAX7310_ID0_DEF_DIR 0x00 // init direction for the I/O +#define MAX7310_ID0_DEF_VAL 0xFF // init value for the output + /* Number 1 controls: CTRL_0, CTRL_1, CTRL_2, CTRL_3, CTRL_4, PORT3_P116, + PORT2_P81, PORT3_P101 + */ +#define MAX7310_I2C_BASE_ID1 I2C3_BASE_ADDR +#define MAX7310_I2C_ID1 0x32 +#define MAX7310_ID1_DEF_DIR 0x00 // init direction for the I/O + /*Set the max7310_id1 's default value for ctrl_x */ +#define MAX7310_ID1_DEF_VAL 0xE7 // init value for the output + +#define MAX7310_I2C_BASE_ID2 I2C3_BASE_ADDR +#define MAX7310_I2C_ID2 0x34 +#define MAX7310_ID2_DEF_DIR 0x00 // init direction for the I/O + /*Set the max7310_id1 's default value for ctrl_x */ +#define MAX7310_ID2_DEF_VAL 0x57 // init value for the output +/* For the EVB board which has 2 MAX7310 */ +#endif +#ifdef EVB +#define MAX7310_NBR 2 + /* Number 1 controls: BACKLIGHT_ON, PORT3_P114, CPU_PER_RST_B, PORT3_P110, + PORT3_P105, PORT3_P112, PORT3_P107, PORT3_P109. + */ +#define MAX7310_I2C_BASE_ID0 I2C3_BASE_ADDR +#define MAX7310_I2C_ID0 (0x36 >> 1) +#define MAX7310_ID0_DEF_DIR 0x00 // init direction for the I/O +#define MAX7310_ID0_DEF_VAL 0xFF // init value for the output + /* Number 1 controls: CTRL_0, CTRL_1, CTRL_2, CTRL_3, CTRL_4, PORT3_P116, + PORT2_P81, PORT3_P101 + */ +#define MAX7310_I2C_BASE_ID1 I2C3_BASE_ADDR +#define MAX7310_I2C_ID1 (0x3E >> 1) +#define MAX7310_ID1_DEF_DIR 0x00 // init direction for the I/O + /*Set the max7310_id1 's default value for ctrl_x */ +#define MAX7310_ID1_DEF_VAL 0x09 // init value for the output +#endif +/* use that defined for boards that doesn't have any MAX7310 */ +#if defined(SMART_DEVICE) || defined(SABRE_LITE) + /* dummy value for build */ +#define MAX7310_NBR 0 +#endif + +/* create an array of I2C requests for all used expanders on the board */ +struct imx_i2c_request max7310_i2c_req_array[MAX7310_NBR]; + +#define MMA8450_I2C_ID 0x1C +#define MMA8451_I2C_ID 0x1C +#define MAG3112_I2C_ID 0x1D +#define MAG3110_I2C_ID 0x0E +#define ISL29023_I2C_ID 0x44 +#define FXLS8471Q_I2C_ID 0x1E + +#define MAX11801_I2C_BASE I2C3_BASE_ADDR +#define MAX11801_I2C_ID (0x90 >> 1) + +#ifdef SABRE_AI +#define CS42888_I2C_BASE I2C2_BASE_ADDR +#endif +#ifdef EVB +#define CS42888_I2C_BASE I2C1_BASE_ADDR +#endif +/* use that defined for boards that doesn't have any CS42888 */ +#if defined(SMART_DEVICE) || defined(SABRE_LITE) +#define CS42888_I2C_BASE DUMMY_VALUE_NOT_USED +#endif +#define CS42888_I2C_ID (0x90 >> 1) + +#define AT24Cx_I2C_BASE I2C3_BASE_ADDR +#define AT24Cx_I2C_ID 0x50 + +// USB test defines +#define USBH1_BASE_ADDR (USBOH2_USB_BASE_ADDR + 0x200) +#define USBH2_BASE_ADDR (USBOH2_USB_BASE_ADDR + 0x400) +#define USBH3_BASE_ADDR (USBOH2_USB_BASE_ADDR + 0x600) +#define USB_OTG_MIRROR_REG (USBOH2_USB_BASE_ADDR+0x804) +#define USB_CLKONOFF_CTRL (USBOH2_USB_BASE_ADDR+0x824) +#define USBH2_VIEWPORT (USBH2_BASE_ADDR + 0x170) +#define USB_CTRL_1 (USBOH2_USB_BASE_ADDR + 0x810) +#define UH2_PORTSC1 (USBH2_BASE_ADDR + 0x184) + +#define IIM_BASE_ADDR 0x0 +#define M4IF_REGISTERS_BASE_ADDR 0x0 +#define ESDHC1_BASE_ADDR 0x0 +#define ESDHC2_BASE_ADDR 0x1 +#define ESDHC3_BASE_ADDR 0x2 +#define DPLLIP1_BASE_ADDR 0x0 +#define DPLLIP2_BASE_ADDR 0x1 +#define DPLLIP3_BASE_ADDR 0x2 +#define DPLLIP4_BASE_ADDR 0x3 + +#define USDHC_ADMA_BUFFER 0x00910000 + +/*qh and td pointers defintion*/ +#define QH_BUFFER 0x00908000 // internal RAM +#define TD_BUFFER 0x00908100 // internal RAM + +// input CKIL clock +#define __CLK_TCK 32768 +#define FREQ_24MHZ 24000000 +#define CKIH 22579200 + +// I2C specific defines +// For LTC Board ID +#define BOARD_ID_I2C_BASE I2C2_BASE_ADDR + +// register defines for the SRTC function of the SNVS +#define SRTC_LPSCMR (SNVS_BASE_ADDR + 0x50) +#define SRTC_LPSCLR (SNVS_BASE_ADDR + 0x54) +#define SRTC_LPCR (SNVS_BASE_ADDR + 0x38) +#define SRTC_HPCMR (SNVS_BASE_ADDR + 0x24) +#define SRTC_HPCLR (SNVS_BASE_ADDR + 0x28) +#define SRTC_HPCR (SNVS_BASE_ADDR + 0x08) + +//provide macros for test enter and exit outputs +#define TEST_ENTER(name) printf ("Running test: %s\n", name) + +#define TEST_EXIT(name) do {printf (" ..Test: %s\n", name); \ + } while (0) +enum main_clocks { + CPU_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + DDR_CLK, + NFC_CLK, + USB_CLK, + VPU_CLK, +}; + +enum peri_clocks { + UART1_BAUD, + UART2_BAUD, + UART3_BAUD, + UART4_BAUD, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSTICK1_CLK, + MSTICK2_CLK, + SPI1_CLK = ECSPI1_BASE_ADDR, + SPI2_CLK = ECSPI2_BASE_ADDR, +}; + +enum plls { + PLL1, + PLL2, + PLL3, + PLL4, +}; + +enum display_type { + DISP_DEV_NULL = 0, + DISP_DEV_TFTLCD, + DISP_DEV_LVDS, + DISP_DEV_VGA, + DISP_DEV_HDMI, + DISP_DEV_TV, + DISP_DEV_MIPI, +}; + +enum lvds_panel_bit_mode { + LVDS_PANEL_18BITS_MODE = 0x0, + LVDS_PANEL_24BITS_MODE = 0x1, +}; + +enum shift_reg_bit{ + HDMI_nRST = 1, + ENET1_nRST = 2, + ENET2_nRST = 4, + CAN1_2_STBY = 8, + BT_nPWD = 16, + CSI_RST = 32, + CSI_PWDN = 64, + LCD_nPWREN = 128, + ALL_BITS = 0xFF, +}; + +void set_shift_reg(enum shift_reg_bit b, bool state); +void peri_pwr_en(bool enable); +void pf0100_enable_vgen5_3v3(void); +void pf0100_disable_vgen5_3v3(void); +void pf0100_enable_vgen2_1v5(void); +void pf0100_disable_vgen2_1v5(void); +void sd3_reset(void); +u32 pll_clock(enum plls pll); +u32 get_main_clock(enum main_clocks clk); +u32 get_peri_clock(enum peri_clocks clk); +void clock_setup(u32 core_clk, u32 ahb_div); +void io_cfg_i2c(u32 module_base); +void usdhc_iomux_config(u32 module_base); +bool usdhc_card_detected(unsigned int base_address); +bool usdhc_write_protected(unsigned int base_address); +void freq_populate(void); +void show_freq(void); +void show_ddr_config(void); +void board_init(void); +void reset_usb_hub(void); +void usb_clock_enable(void); +void usb_init_phy(void); +void imx_enet_setup(void); +void esai_iomux(void); +void gpmi_nand_pinmux_config(void); +void gpmi_nand_clk_setup(void); +void imx_enet_iomux(int id); +void imx_enet_power_on_reset(void); +void imx_enet_hw_init(int id); +void usb_iomux_config(void); +void usb_vbus_power_on(void); +void usb_vbus_power_off(void); +void imx_ar8031_reset(void); +void imx_KSZ9021RN_reset(void); +int read_mac(u8 * mac_data); +int program_mac(u8 * fuse_data); +void mlb_io_config(void); +int esai_codec_power_on(void); +void hdmi_pgm_iomux(void); +void hdmi_clock_set(unsigned int pclk); +void lvds_power_on(char *panel_name); +void sata_clock_disable(void); +void sata_power_off(void); +void weim_nor_flash_cs_setup(void); +void show_boot_switch_info(void); +void hdmi_power_on(void); +void camera_power_on(void); +void camera_power_off(void); +void camera_reset(void); +void camera_clock_setting(void); +void audio_codec_power_on(void); + +extern void gpio_backlight_lvds_en(void); +extern void init_clock(u32 rate); +extern void hal_delay_us(unsigned int); +extern int max7310_init(unsigned int, unsigned int, unsigned int); +extern void max7310_set_gpio_output(unsigned int, unsigned int, unsigned int); + +extern void AUDMUXRoute(int intPort, int extPort, int Master); // defined in ssi.c driver + +extern int mx6ul_evk_show_headphone(void); + +extern imx_spi_init_func_t spi_init_flash; +extern imx_spi_xfer_func_t spi_xfer_flash; +extern struct imx_spi_dev imx_spi_nor; + +extern u32 usbh_EHCI_test_mode_base; +extern u32 usbh_dev_enum_test_base; +extern u32 usbo_dev_enum_test_base; +extern u32 usbh_hub251x_test_base; +extern int ipu_display_panel[]; +extern u32 ddr_density, ddr_num_of_cs; +extern u32 mmcsd_bus_width, mmc_sd_base_address; + +/* list of tests */ +extern int spi_nor_test_enable; +extern int pmic_mc13892_test_enable; +extern int pf0100_i2c_device_id_test_enable; +extern int fec_test_enable; +extern int lan9220_test_enable; +extern int enet_test_enable; +extern int ksz8081rnb_test_enable; +extern int KSZ9021RN_test_enable; +extern int ds90ur124_test_enable; +extern int adv7180_test_enable; +extern int ard_mb_reset_test_enable; +extern int ard_mb_expander_reset_test_enable; +extern int si476x_test_enable; +extern int esai_test_enable; +extern int weim_nor_flash_test_enable; +extern int max7310_i2c_device_id_test_enable; +extern int nand_test_enable; +extern int usbh_EHCI_test_mode_test_enable; +extern int usbh_dev_enum_test_enable; +extern int usbo_dev_enum_test_enable; +extern int usbh_hub251x_test_enable; +extern int i2s_audio_test_enable; +extern int gps_test_enable; +extern int gpio_keyboard_test_enable; +extern int smbus_test_enable; +extern int touch_screen_test_enable; +extern int ipu_display_test_enable; +extern int ddr_test_enable; +extern int mlb_os81050_test_enable; +extern int i2c_id_check_test_enable; +extern int i2c_device_id_check_mag3112_test_enable; +extern int i2c_device_id_check_mag3110_test_enable; +extern int i2c_device_id_check_isl29023_test_enable; +extern int i2c_device_id_check_mma8451_test_enable; +extern int i2c_device_id_check_cs42888_test_enable; +extern int i2c_device_id_check_p1003_test_enable; +extern int mmcsd_test_enable; +extern int eeprom_test_enable; +extern int mipi_test_enable; +extern int touch_button_test_enable; +extern int android_buttons_test_enable; +extern int can_test_enable; +extern int camera_flashtest_enable; +extern int camera_test_enable; +extern int epd_test_enable; +extern int lcd_test_enable; +extern int lvds_test_enable; + +#define PMIC_MC13892_I2C_BASE I2C2_BASE_ADDR +#define PMIC_LTC3589_I2C_BASE I2C2_BASE_ADDR +#define PMIC_DA9053_I2C_BASE I2C1_BASE_ADDR +#define PMIC_PF0100_I2C_BASE I2C1_BASE_ADDR + +#endif /*HARDWARE_H_ */ diff --git a/bsp/imx6ul/platform/include/mx6ul/hdmi_regs.h b/bsp/imx6ul/platform/include/mx6ul/hdmi_regs.h new file mode 100644 index 0000000000000000000000000000000000000000..a0982709e85d144838729cca13fcb88fedb9a5a2 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/hdmi_regs.h @@ -0,0 +1,555 @@ +/* + * Copyright (C) 2010-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. + */ + +/*! + * @file hdmi_regs.h + * @brief registers defination of hdmi tx module. + * @ingroup diag_hdmi + */ + +#ifndef __HDMI_REGS_H__ +#define __HDMI_REGS_H__ + +#include "soc_memory_map.h" + +// ANALOG registers +#define HW_ANADIG_PLL_VIDEO ANATOP_BASE_ADDR + 0x0a0 +#define HW_ANADIG_PLL_VIDEO_NUM ANATOP_BASE_ADDR + 0x0b0 +#define HW_ANADIG_PLL_VIDEO_DENUM ANATOP_BASE_ADDR + 0x0c0 + +// HDMI PHY REGISTERS +#define CREGS_PLL_DIV_ADDR 0x06 +#define CREGS_PLL_GMP_CNTRL_ADDR 0x15 +#define CREGS_PLL_PROP_INT_CNTRL_ADDR 0x10 +#define CREGS_PATTERNGEN 0x1B +#define CREGS_PGMODE 0x1C +#define CREGS_DIGTXMODE 0x1E + +// +// Hdmi controller registers +// + +// Identification Registers +#define HDMI_DESIGN_ID HDMI_ARB_BASE_ADDR+0x0000 +#define HDMI_REVISION_ID HDMI_ARB_BASE_ADDR+0x0001 +#define HDMI_PRODUCT_ID0 HDMI_ARB_BASE_ADDR+0x0002 +#define HDMI_PRODUCT_ID1 HDMI_ARB_BASE_ADDR+0x0003 +#define HDMI_CONFIG0_ID HDMI_ARB_BASE_ADDR+0x0004 +#define HDMI_CONFIG1_ID HDMI_ARB_BASE_ADDR+0x0005 +#define HDMI_CONFIG2_ID HDMI_ARB_BASE_ADDR+0x0006 +#define HDMI_CONFIG3_ID HDMI_ARB_BASE_ADDR+0x0007 + +// Interrupt Registers +#define HDMI_IH_FC_STAT0 HDMI_ARB_BASE_ADDR+0x0100 +#define HDMI_IH_FC_STAT1 HDMI_ARB_BASE_ADDR+0x0101 +#define HDMI_IH_FC_STAT2 HDMI_ARB_BASE_ADDR+0x0102 +#define HDMI_IH_AS_STAT0 HDMI_ARB_BASE_ADDR+0x0103 +#define HDMI_IH_PHY_STAT0 HDMI_ARB_BASE_ADDR+0x0104 +#define HDMI_IH_I2CM_STAT0 HDMI_ARB_BASE_ADDR+0x0105 +#define HDMI_IH_CEC_STAT0 HDMI_ARB_BASE_ADDR+0x0106 +#define HDMI_IH_VP_STAT0 HDMI_ARB_BASE_ADDR+0x0107 +#define HDMI_IH_I2CMPHY_STAT0 HDMI_ARB_BASE_ADDR+0x0108 +#define HDMI_IH_AHBDMAAUD_STAT0 HDMI_ARB_BASE_ADDR+0x0180 +#define HDMI_IH_MUTE_FC_STAT1 HDMI_ARB_BASE_ADDR+0x0181 +#define HDMI_IH_MUTE_FC_STAT2 HDMI_ARB_BASE_ADDR+0x0182 +#define HDMI_IH_MUTE_AS_STAT0 HDMI_ARB_BASE_ADDR+0x0183 +#define HDMI_IH_MUTE_PHY_STAT0 HDMI_ARB_BASE_ADDR+0x0184 +#define HDMI_IH_MUTE_I2CM_STAT0 HDMI_ARB_BASE_ADDR+0x0185 +#define HDMI_IH_MUTE_CEC_STAT0 HDMI_ARB_BASE_ADDR+0x0186 +#define HDMI_IH_MUTE_VP_STAT0 HDMI_ARB_BASE_ADDR+0x0187 +#define HDMI_IH_MUTE_I2CMPHY_STAT0 HDMI_ARB_BASE_ADDR+0x0188 +#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 HDMI_ARB_BASE_ADDR+0x0189 +#define HDMI_IH_MUTE HDMI_ARB_BASE_ADDR+0x01FF + +// Video Sample Registers +#define HDMI_TX_INVID0 HDMI_ARB_BASE_ADDR+0x0200 +#define HDMI_TX_INSTUFFING HDMI_ARB_BASE_ADDR+0x0201 +#define HDMI_TX_GYDATA0 HDMI_ARB_BASE_ADDR+0x0202 +#define HDMI_TX_GYDATA1 HDMI_ARB_BASE_ADDR+0x0203 +#define HDMI_TX_RCRDATA0 HDMI_ARB_BASE_ADDR+0x0204 +#define HDMI_TX_RCRDATA1 HDMI_ARB_BASE_ADDR+0x0205 +#define HDMI_TX_BCBDATA0 HDMI_ARB_BASE_ADDR+0x0206 +#define HDMI_TX_BCBDATA1 HDMI_ARB_BASE_ADDR+0x0207 + +// Video Packetizer Registers +#define HDMI_VP_STATUS HDMI_ARB_BASE_ADDR+0x0800 +#define HDMI_VP_PR_CD HDMI_ARB_BASE_ADDR+0x0801 +#define HDMI_VP_STUFF HDMI_ARB_BASE_ADDR+0x0802 +#define HDMI_VP_REMAP HDMI_ARB_BASE_ADDR+0x0803 +#define HDMI_VP_CONF HDMI_ARB_BASE_ADDR+0x0804 +#define HDMI_VP_STAT HDMI_ARB_BASE_ADDR+0x0805 +#define HDMI_VP_INT HDMI_ARB_BASE_ADDR+0x0806 +#define HDMI_VP_MASK HDMI_ARB_BASE_ADDR+0x0807 +#define HDMI_VP_POL HDMI_ARB_BASE_ADDR+0x0808 + +// Frame Composer Registers +#define HDMI_FC_INVIDCONF HDMI_ARB_BASE_ADDR+0x1000 +#define HDMI_FC_INHACTV0 HDMI_ARB_BASE_ADDR+0x1001 +#define HDMI_FC_INHACTV1 HDMI_ARB_BASE_ADDR+0x1002 +#define HDMI_FC_INHBLANK0 HDMI_ARB_BASE_ADDR+0x1003 +#define HDMI_FC_INHBLANK1 HDMI_ARB_BASE_ADDR+0x1004 +#define HDMI_FC_INVACTV0 HDMI_ARB_BASE_ADDR+0x1005 +#define HDMI_FC_INVACTV1 HDMI_ARB_BASE_ADDR+0x1006 +#define HDMI_FC_INVBLANK HDMI_ARB_BASE_ADDR+0x1007 +#define HDMI_FC_HSYNCINDELAY0 HDMI_ARB_BASE_ADDR+0x1008 +#define HDMI_FC_HSYNCINDELAY1 HDMI_ARB_BASE_ADDR+0x1009 +#define HDMI_FC_HSYNCINWIDTH0 HDMI_ARB_BASE_ADDR+0x100A +#define HDMI_FC_HSYNCINWIDTH1 HDMI_ARB_BASE_ADDR+0x100B +#define HDMI_FC_VSYNCINDELAY HDMI_ARB_BASE_ADDR+0x100C +#define HDMI_FC_VSYNCINWIDTH HDMI_ARB_BASE_ADDR+0x100D +#define HDMI_FC_INFREQ0 HDMI_ARB_BASE_ADDR+0x100E +#define HDMI_FC_INFREQ1 HDMI_ARB_BASE_ADDR+0x100F +#define HDMI_FC_INFREQ2 HDMI_ARB_BASE_ADDR+0x1010 +#define HDMI_FC_CTRLDUR HDMI_ARB_BASE_ADDR+0x1011 +#define HDMI_FC_EXCTRLDUR HDMI_ARB_BASE_ADDR+0x1012 +#define HDMI_FC_EXCTRLSPAC HDMI_ARB_BASE_ADDR+0x1013 +#define HDMI_FC_CH0PREAM HDMI_ARB_BASE_ADDR+0x1014 +#define HDMI_FC_CH1PREAM HDMI_ARB_BASE_ADDR+0x1015 +#define HDMI_FC_CH2PREAM HDMI_ARB_BASE_ADDR+0x1016 +#define HDMI_FC_AVICONF3 HDMI_ARB_BASE_ADDR+0x1017 +#define HDMI_FC_GCP HDMI_ARB_BASE_ADDR+0x1018 +#define HDMI_FC_AVICONF0 HDMI_ARB_BASE_ADDR+0x1019 +#define HDMI_FC_AVICONF1 HDMI_ARB_BASE_ADDR+0x101A +#define HDMI_FC_AVICONF2 HDMI_ARB_BASE_ADDR+0x101B +#define HDMI_FC_AVIVID HDMI_ARB_BASE_ADDR+0x101C +#define HDMI_FC_AVIETB0 HDMI_ARB_BASE_ADDR+0x101D +#define HDMI_FC_AVIETB1 HDMI_ARB_BASE_ADDR+0x101E +#define HDMI_FC_AVISBB0 HDMI_ARB_BASE_ADDR+0x101F +#define HDMI_FC_AVISBB1 HDMI_ARB_BASE_ADDR+0x1020 +#define HDMI_FC_AVIELB0 HDMI_ARB_BASE_ADDR+0x1021 +#define HDMI_FC_AVIELB1 HDMI_ARB_BASE_ADDR+0x1022 +#define HDMI_FC_AVISRB0 HDMI_ARB_BASE_ADDR+0x1023 +#define HDMI_FC_AVISRB1 HDMI_ARB_BASE_ADDR+0x1024 +#define HDMI_FC_AUDICONF0 HDMI_ARB_BASE_ADDR+0x1025 +#define HDMI_FC_AUDICONF1 HDMI_ARB_BASE_ADDR+0x1026 +#define HDMI_FC_AUDICONF2 HDMI_ARB_BASE_ADDR+0x1027 +#define HDMI_FC_AUDICONF3 HDMI_ARB_BASE_ADDR+0x1028 +#define HDMI_FC_VSDIEEEID0 HDMI_ARB_BASE_ADDR+0x1029 +#define HDMI_FC_VSDSIZE HDMI_ARB_BASE_ADDR+0x102A +#define HDMI_FC_VSDIEEEID1 HDMI_ARB_BASE_ADDR+0x1030 +#define HDMI_FC_VSDIEEEID2 HDMI_ARB_BASE_ADDR+0x1031 +#define HDMI_FC_VSDPAYLOAD0 HDMI_ARB_BASE_ADDR+0x1032 +#define HDMI_FC_VSDPAYLOAD1 HDMI_ARB_BASE_ADDR+0x1033 +#define HDMI_FC_VSDPAYLOAD2 HDMI_ARB_BASE_ADDR+0x1034 +#define HDMI_FC_VSDPAYLOAD3 HDMI_ARB_BASE_ADDR+0x1035 +#define HDMI_FC_VSDPAYLOAD4 HDMI_ARB_BASE_ADDR+0x1036 +#define HDMI_FC_VSDPAYLOAD5 HDMI_ARB_BASE_ADDR+0x1037 +#define HDMI_FC_VSDPAYLOAD6 HDMI_ARB_BASE_ADDR+0x1038 +#define HDMI_FC_VSDPAYLOAD7 HDMI_ARB_BASE_ADDR+0x1039 +#define HDMI_FC_VSDPAYLOAD8 HDMI_ARB_BASE_ADDR+0x103A +#define HDMI_FC_VSDPAYLOAD9 HDMI_ARB_BASE_ADDR+0x103B +#define HDMI_FC_VSDPAYLOAD10 HDMI_ARB_BASE_ADDR+0x103C +#define HDMI_FC_VSDPAYLOAD11 HDMI_ARB_BASE_ADDR+0x103D +#define HDMI_FC_VSDPAYLOAD12 HDMI_ARB_BASE_ADDR+0x103E +#define HDMI_FC_VSDPAYLOAD13 HDMI_ARB_BASE_ADDR+0x103F +#define HDMI_FC_VSDPAYLOAD14 HDMI_ARB_BASE_ADDR+0x1040 +#define HDMI_FC_VSDPAYLOAD15 HDMI_ARB_BASE_ADDR+0x1041 +#define HDMI_FC_VSDPAYLOAD16 HDMI_ARB_BASE_ADDR+0x1042 +#define HDMI_FC_VSDPAYLOAD17 HDMI_ARB_BASE_ADDR+0x1043 +#define HDMI_FC_VSDPAYLOAD18 HDMI_ARB_BASE_ADDR+0x1044 +#define HDMI_FC_VSDPAYLOAD19 HDMI_ARB_BASE_ADDR+0x1045 +#define HDMI_FC_VSDPAYLOAD20 HDMI_ARB_BASE_ADDR+0x1046 +#define HDMI_FC_VSDPAYLOAD21 HDMI_ARB_BASE_ADDR+0x1047 +#define HDMI_FC_VSDPAYLOAD22 HDMI_ARB_BASE_ADDR+0x1048 +#define HDMI_FC_VSDPAYLOAD23 HDMI_ARB_BASE_ADDR+0x1049 +#define HDMI_FC_SPDVENDORNAME0 HDMI_ARB_BASE_ADDR+0x104A +#define HDMI_FC_SPDVENDORNAME1 HDMI_ARB_BASE_ADDR+0x104B +#define HDMI_FC_SPDVENDORNAME2 HDMI_ARB_BASE_ADDR+0x104C +#define HDMI_FC_SPDVENDORNAME3 HDMI_ARB_BASE_ADDR+0x104D +#define HDMI_FC_SPDVENDORNAME4 HDMI_ARB_BASE_ADDR+0x104E +#define HDMI_FC_SPDVENDORNAME5 HDMI_ARB_BASE_ADDR+0x104F +#define HDMI_FC_SPDVENDORNAME6 HDMI_ARB_BASE_ADDR+0x1050 +#define HDMI_FC_SPDVENDORNAME7 HDMI_ARB_BASE_ADDR+0x1051 +#define HDMI_FC_SDPPRODUCTNAME0 HDMI_ARB_BASE_ADDR+0x1052 +#define HDMI_FC_SDPPRODUCTNAME1 HDMI_ARB_BASE_ADDR+0x1053 +#define HDMI_FC_SDPPRODUCTNAME2 HDMI_ARB_BASE_ADDR+0x1054 +#define HDMI_FC_SDPPRODUCTNAME3 HDMI_ARB_BASE_ADDR+0x1055 +#define HDMI_FC_SDPPRODUCTNAME4 HDMI_ARB_BASE_ADDR+0x1056 +#define HDMI_FC_SDPPRODUCTNAME5 HDMI_ARB_BASE_ADDR+0x1057 +#define HDMI_FC_SDPPRODUCTNAME6 HDMI_ARB_BASE_ADDR+0x1058 +#define HDMI_FC_SDPPRODUCTNAME7 HDMI_ARB_BASE_ADDR+0x1059 +#define HDMI_FC_SDPPRODUCTNAME8 HDMI_ARB_BASE_ADDR+0x105A +#define HDMI_FC_SDPPRODUCTNAME9 HDMI_ARB_BASE_ADDR+0x105B +#define HDMI_FC_SDPPRODUCTNAME10 HDMI_ARB_BASE_ADDR+0x105C +#define HDMI_FC_SDPPRODUCTNAME11 HDMI_ARB_BASE_ADDR+0x105D +#define HDMI_FC_SDPPRODUCTNAME12 HDMI_ARB_BASE_ADDR+0x105E +#define HDMI_FC_SDPPRODUCTNAME13 HDMI_ARB_BASE_ADDR+0x105F +#define HDMI_FC_SDPPRODUCTNAME14 HDMI_ARB_BASE_ADDR+0x1060 +#define HDMI_FC_SPDPRODUCTNAME15 HDMI_ARB_BASE_ADDR+0x1061 +#define HDMI_FC_SPDDEVICEINF HDMI_ARB_BASE_ADDR+0x1062 +#define HDMI_FC_AUDSCONF HDMI_ARB_BASE_ADDR+0x1063 +#define HDMI_FC_AUDSSTAT HDMI_ARB_BASE_ADDR+0x1064 +#define HDMI_FC_AUDSV HDMI_ARB_BASE_ADDR+0x1065 +#define HDMI_FC_AUDSU HDMI_ARB_BASE_ADDR+0x1066 +#define HDMI_FC_AUDSCHNLS0 HDMI_ARB_BASE_ADDR+0x1067 +#define HDMI_FC_AUDSCHNLS1 HDMI_ARB_BASE_ADDR+0x1068 +#define HDMI_FC_AUDSCHNLS2 HDMI_ARB_BASE_ADDR+0x1069 +#define HDMI_FC_AUDSCHNLS3 HDMI_ARB_BASE_ADDR+0x106A +#define HDMI_FC_AUDSCHNLS4 HDMI_ARB_BASE_ADDR+0x106B +#define HDMI_FC_AUDSCHNLS5 HDMI_ARB_BASE_ADDR+0x106C +#define HDMI_FC_AUDSCHNLS6 HDMI_ARB_BASE_ADDR+0x106D +#define HDMI_FC_AUDSCHNLS7 HDMI_ARB_BASE_ADDR+0x106E +#define HDMI_FC_AUDSCHNLS8 HDMI_ARB_BASE_ADDR+0x106F +#define HDMI_FC_DATACH0FILL HDMI_ARB_BASE_ADDR+0x1070 +#define HDMI_FC_DATACH1FILL HDMI_ARB_BASE_ADDR+0x1071 +#define HDMI_FC_DATACH2FILL HDMI_ARB_BASE_ADDR+0x1072 +#define HDMI_FC_CTRLQHIGH HDMI_ARB_BASE_ADDR+0x1073 +#define HDMI_FC_CTRLQLOW HDMI_ARB_BASE_ADDR+0x1074 +#define HDMI_FC_ACP0 HDMI_ARB_BASE_ADDR+0x1075 +#define HDMI_FC_ACP28 HDMI_ARB_BASE_ADDR+0x1076 +#define HDMI_FC_ACP27 HDMI_ARB_BASE_ADDR+0x1077 +#define HDMI_FC_ACP26 HDMI_ARB_BASE_ADDR+0x1078 +#define HDMI_FC_ACP25 HDMI_ARB_BASE_ADDR+0x1079 +#define HDMI_FC_ACP24 HDMI_ARB_BASE_ADDR+0x107A +#define HDMI_FC_ACP23 HDMI_ARB_BASE_ADDR+0x107B +#define HDMI_FC_ACP22 HDMI_ARB_BASE_ADDR+0x107C +#define HDMI_FC_ACP21 HDMI_ARB_BASE_ADDR+0x107D +#define HDMI_FC_ACP20 HDMI_ARB_BASE_ADDR+0x107E +#define HDMI_FC_ACP19 HDMI_ARB_BASE_ADDR+0x107F +#define HDMI_FC_ACP18 HDMI_ARB_BASE_ADDR+0x1080 +#define HDMI_FC_ACP17 HDMI_ARB_BASE_ADDR+0x1081 +#define HDMI_FC_ACP16 HDMI_ARB_BASE_ADDR+0x1082 +#define HDMI_FC_ACP15 HDMI_ARB_BASE_ADDR+0x1083 +#define HDMI_FC_ACP14 HDMI_ARB_BASE_ADDR+0x1084 +#define HDMI_FC_ACP13 HDMI_ARB_BASE_ADDR+0x1085 +#define HDMI_FC_ACP12 HDMI_ARB_BASE_ADDR+0x1086 +#define HDMI_FC_ACP11 HDMI_ARB_BASE_ADDR+0x1087 +#define HDMI_FC_ACP10 HDMI_ARB_BASE_ADDR+0x1088 +#define HDMI_FC_ACP9 HDMI_ARB_BASE_ADDR+0x1089 +#define HDMI_FC_ACP8 HDMI_ARB_BASE_ADDR+0x108A +#define HDMI_FC_ACP7 HDMI_ARB_BASE_ADDR+0x108B +#define HDMI_FC_ACP6 HDMI_ARB_BASE_ADDR+0x108C +#define HDMI_FC_ACP5 HDMI_ARB_BASE_ADDR+0x108D +#define HDMI_FC_ACP4 HDMI_ARB_BASE_ADDR+0x108E +#define HDMI_FC_ACP3 HDMI_ARB_BASE_ADDR+0x108F +#define HDMI_FC_ACP2 HDMI_ARB_BASE_ADDR+0x1090 +#define HDMI_FC_ACP1 HDMI_ARB_BASE_ADDR+0x1091 +#define HDMI_FC_ISCR1_0 HDMI_ARB_BASE_ADDR+0x1092 +#define HDMI_FC_ISCR1_16 HDMI_ARB_BASE_ADDR+0x1093 +#define HDMI_FC_ISCR1_15 HDMI_ARB_BASE_ADDR+0x1094 +#define HDMI_FC_ISCR1_14 HDMI_ARB_BASE_ADDR+0x1095 +#define HDMI_FC_ISCR1_13 HDMI_ARB_BASE_ADDR+0x1096 +#define HDMI_FC_ISCR1_12 HDMI_ARB_BASE_ADDR+0x1097 +#define HDMI_FC_ISCR1_11 HDMI_ARB_BASE_ADDR+0x1098 +#define HDMI_FC_ISCR1_10 HDMI_ARB_BASE_ADDR+0x1099 +#define HDMI_FC_ISCR1_9 HDMI_ARB_BASE_ADDR+0x109A +#define HDMI_FC_ISCR1_8 HDMI_ARB_BASE_ADDR+0x109B +#define HDMI_FC_ISCR1_7 HDMI_ARB_BASE_ADDR+0x109C +#define HDMI_FC_ISCR1_6 HDMI_ARB_BASE_ADDR+0x109D +#define HDMI_FC_ISCR1_5 HDMI_ARB_BASE_ADDR+0x109E +#define HDMI_FC_ISCR1_4 HDMI_ARB_BASE_ADDR+0x109F +#define HDMI_FC_ISCR1_3 HDMI_ARB_BASE_ADDR+0x10A0 +#define HDMI_FC_ISCR1_2 HDMI_ARB_BASE_ADDR+0x10A1 +#define HDMI_FC_ISCR1_1 HDMI_ARB_BASE_ADDR+0x10A2 +#define HDMI_FC_ISCR2_15 HDMI_ARB_BASE_ADDR+0x10A3 +#define HDMI_FC_ISCR2_14 HDMI_ARB_BASE_ADDR+0x10A4 +#define HDMI_FC_ISCR2_13 HDMI_ARB_BASE_ADDR+0x10A5 +#define HDMI_FC_ISCR2_12 HDMI_ARB_BASE_ADDR+0x10A6 +#define HDMI_FC_ISCR2_11 HDMI_ARB_BASE_ADDR+0x10A7 +#define HDMI_FC_ISCR2_10 HDMI_ARB_BASE_ADDR+0x10A8 +#define HDMI_FC_ISCR2_9 HDMI_ARB_BASE_ADDR+0x10A9 +#define HDMI_FC_ISCR2_8 HDMI_ARB_BASE_ADDR+0x10AA +#define HDMI_FC_ISCR2_7 HDMI_ARB_BASE_ADDR+0x10AB +#define HDMI_FC_ISCR2_6 HDMI_ARB_BASE_ADDR+0x10AC +#define HDMI_FC_ISCR2_5 HDMI_ARB_BASE_ADDR+0x10AD +#define HDMI_FC_ISCR2_4 HDMI_ARB_BASE_ADDR+0x10AE +#define HDMI_FC_ISCR2_3 HDMI_ARB_BASE_ADDR+0x10AF +#define HDMI_FC_ISCR2_2 HDMI_ARB_BASE_ADDR+0x10B0 +#define HDMI_FC_ISCR2_1 HDMI_ARB_BASE_ADDR+0x10B1 +#define HDMI_FC_ISCR2_0 HDMI_ARB_BASE_ADDR+0x10B2 +#define HDMI_FC_DATAUTO0 HDMI_ARB_BASE_ADDR+0x10B3 +#define HDMI_FC_DATAUTO1 HDMI_ARB_BASE_ADDR+0x10B4 +#define HDMI_FC_DATAUTO2 HDMI_ARB_BASE_ADDR+0x10B5 +#define HDMI_FC_DATMAN HDMI_ARB_BASE_ADDR+0x10B6 +#define HDMI_FC_DATAUTO3 HDMI_ARB_BASE_ADDR+0x10B7 +#define HDMI_FC_RDRB0 HDMI_ARB_BASE_ADDR+0x10B8 +#define HDMI_FC_RDRB1 HDMI_ARB_BASE_ADDR+0x10B9 +#define HDMI_FC_RDRB2 HDMI_ARB_BASE_ADDR+0x10BA +#define HDMI_FC_RDRB3 HDMI_ARB_BASE_ADDR+0x10BB +#define HDMI_FC_RDRB4 HDMI_ARB_BASE_ADDR+0x10BC +#define HDMI_FC_RDRB5 HDMI_ARB_BASE_ADDR+0x10BD +#define HDMI_FC_RDRB6 HDMI_ARB_BASE_ADDR+0x10BE +#define HDMI_FC_RDRB7 HDMI_ARB_BASE_ADDR+0x10BF +#define HDMI_FC_STAT0 HDMI_ARB_BASE_ADDR+0x10D0 +#define HDMI_FC_INT0 HDMI_ARB_BASE_ADDR+0x10D1 +#define HDMI_FC_MASK0 HDMI_ARB_BASE_ADDR+0x10D2 +#define HDMI_FC_POL0 HDMI_ARB_BASE_ADDR+0x10D3 +#define HDMI_FC_STAT1 HDMI_ARB_BASE_ADDR+0x10D4 +#define HDMI_FC_INT1 HDMI_ARB_BASE_ADDR+0x10D5 +#define HDMI_FC_MASK1 HDMI_ARB_BASE_ADDR+0x10D6 +#define HDMI_FC_POL1 HDMI_ARB_BASE_ADDR+0x10D7 +#define HDMI_FC_STAT2 HDMI_ARB_BASE_ADDR+0x10D8 +#define HDMI_FC_INT2 HDMI_ARB_BASE_ADDR+0x10D9 +#define HDMI_FC_MASK2 HDMI_ARB_BASE_ADDR+0x10DA +#define HDMI_FC_POL2 HDMI_ARB_BASE_ADDR+0x10DB +#define HDMI_FC_PRCONF HDMI_ARB_BASE_ADDR+0x10E0 + +#define HDMI_FC_GMD_STAT HDMI_ARB_BASE_ADDR+0x1100 +#define HDMI_FC_GMD_EN HDMI_ARB_BASE_ADDR+0x1101 +#define HDMI_FC_GMD_UP HDMI_ARB_BASE_ADDR+0x1102 +#define HDMI_FC_GMD_CONF HDMI_ARB_BASE_ADDR+0x1103 +#define HDMI_FC_GMD_HB HDMI_ARB_BASE_ADDR+0x1104 +#define HDMI_FC_GMD_PB0 HDMI_ARB_BASE_ADDR+0x1105 +#define HDMI_FC_GMD_PB1 HDMI_ARB_BASE_ADDR+0x1106 +#define HDMI_FC_GMD_PB2 HDMI_ARB_BASE_ADDR+0x1107 +#define HDMI_FC_GMD_PB3 HDMI_ARB_BASE_ADDR+0x1108 +#define HDMI_FC_GMD_PB4 HDMI_ARB_BASE_ADDR+0x1109 +#define HDMI_FC_GMD_PB5 HDMI_ARB_BASE_ADDR+0x110A +#define HDMI_FC_GMD_PB6 HDMI_ARB_BASE_ADDR+0x110B +#define HDMI_FC_GMD_PB7 HDMI_ARB_BASE_ADDR+0x110C +#define HDMI_FC_GMD_PB8 HDMI_ARB_BASE_ADDR+0x110D +#define HDMI_FC_GMD_PB9 HDMI_ARB_BASE_ADDR+0x110E +#define HDMI_FC_GMD_PB10 HDMI_ARB_BASE_ADDR+0x110F +#define HDMI_FC_GMD_PB11 HDMI_ARB_BASE_ADDR+0x1110 +#define HDMI_FC_GMD_PB12 HDMI_ARB_BASE_ADDR+0x1111 +#define HDMI_FC_GMD_PB13 HDMI_ARB_BASE_ADDR+0x1112 +#define HDMI_FC_GMD_PB14 HDMI_ARB_BASE_ADDR+0x1113 +#define HDMI_FC_GMD_PB15 HDMI_ARB_BASE_ADDR+0x1114 +#define HDMI_FC_GMD_PB16 HDMI_ARB_BASE_ADDR+0x1115 +#define HDMI_FC_GMD_PB17 HDMI_ARB_BASE_ADDR+0x1116 +#define HDMI_FC_GMD_PB18 HDMI_ARB_BASE_ADDR+0x1117 +#define HDMI_FC_GMD_PB19 HDMI_ARB_BASE_ADDR+0x1118 +#define HDMI_FC_GMD_PB20 HDMI_ARB_BASE_ADDR+0x1119 +#define HDMI_FC_GMD_PB21 HDMI_ARB_BASE_ADDR+0x111A +#define HDMI_FC_GMD_PB22 HDMI_ARB_BASE_ADDR+0x111B +#define HDMI_FC_GMD_PB23 HDMI_ARB_BASE_ADDR+0x111C +#define HDMI_FC_GMD_PB24 HDMI_ARB_BASE_ADDR+0x111D +#define HDMI_FC_GMD_PB25 HDMI_ARB_BASE_ADDR+0x111E +#define HDMI_FC_GMD_PB26 HDMI_ARB_BASE_ADDR+0x111F +#define HDMI_FC_GMD_PB27 HDMI_ARB_BASE_ADDR+0x1120 + +#define HDMI_FC_DBGFORCE HDMI_ARB_BASE_ADDR+0x1200 +#define HDMI_FC_DBGAUD0CH0 HDMI_ARB_BASE_ADDR+0x1201 +#define HDMI_FC_DBGAUD1CH0 HDMI_ARB_BASE_ADDR+0x1202 +#define HDMI_FC_DBGAUD2CH0 HDMI_ARB_BASE_ADDR+0x1203 +#define HDMI_FC_DBGAUD0CH1 HDMI_ARB_BASE_ADDR+0x1204 +#define HDMI_FC_DBGAUD1CH1 HDMI_ARB_BASE_ADDR+0x1205 +#define HDMI_FC_DBGAUD2CH1 HDMI_ARB_BASE_ADDR+0x1206 +#define HDMI_FC_DBGAUD0CH2 HDMI_ARB_BASE_ADDR+0x1207 +#define HDMI_FC_DBGAUD1CH2 HDMI_ARB_BASE_ADDR+0x1208 +#define HDMI_FC_DBGAUD2CH2 HDMI_ARB_BASE_ADDR+0x1209 +#define HDMI_FC_DBGAUD0CH3 HDMI_ARB_BASE_ADDR+0x120A +#define HDMI_FC_DBGAUD1CH3 HDMI_ARB_BASE_ADDR+0x120B +#define HDMI_FC_DBGAUD2CH3 HDMI_ARB_BASE_ADDR+0x120C +#define HDMI_FC_DBGAUD0CH4 HDMI_ARB_BASE_ADDR+0x120D +#define HDMI_FC_DBGAUD1CH4 HDMI_ARB_BASE_ADDR+0x120E +#define HDMI_FC_DBGAUD2CH4 HDMI_ARB_BASE_ADDR+0x120F +#define HDMI_FC_DBGAUD0CH5 HDMI_ARB_BASE_ADDR+0x1210 +#define HDMI_FC_DBGAUD1CH5 HDMI_ARB_BASE_ADDR+0x1211 +#define HDMI_FC_DBGAUD2CH5 HDMI_ARB_BASE_ADDR+0x1212 +#define HDMI_FC_DBGAUD0CH6 HDMI_ARB_BASE_ADDR+0x1213 +#define HDMI_FC_DBGAUD1CH6 HDMI_ARB_BASE_ADDR+0x1214 +#define HDMI_FC_DBGAUD2CH6 HDMI_ARB_BASE_ADDR+0x1215 +#define HDMI_FC_DBGAUD0CH7 HDMI_ARB_BASE_ADDR+0x1216 +#define HDMI_FC_DBGAUD1CH7 HDMI_ARB_BASE_ADDR+0x1217 +#define HDMI_FC_DBGAUD2CH7 HDMI_ARB_BASE_ADDR+0x1218 +#define HDMI_FC_DBGTMDS0 HDMI_ARB_BASE_ADDR+0x1219 +#define HDMI_FC_DBGTMDS1 HDMI_ARB_BASE_ADDR+0x121A +#define HDMI_FC_DBGTMDS2 HDMI_ARB_BASE_ADDR+0x121B + +// HDMI Source PHY Registers +#define HDMI_PHY_CONF0 HDMI_ARB_BASE_ADDR+0x3000 +#define HDMI_PHY_TST0 HDMI_ARB_BASE_ADDR+0x3001 +#define HDMI_PHY_TST1 HDMI_ARB_BASE_ADDR+0x3002 +#define HDMI_PHY_TST2 HDMI_ARB_BASE_ADDR+0x3003 +#define HDMI_PHY_STAT0 HDMI_ARB_BASE_ADDR+0x3004 +#define HDMI_PHY_INT0 HDMI_ARB_BASE_ADDR+0x3005 +#define HDMI_PHY_MASK0 HDMI_ARB_BASE_ADDR+0x3006 +#define HDMI_PHY_POL0 HDMI_ARB_BASE_ADDR+0x3007 + +// HDMI Master PHY Registers +#define HDMI_PHY_I2CM_SLAVE_ADDR HDMI_ARB_BASE_ADDR+0x3020 +#define HDMI_PHY_I2CM_ADDRESS_ADDR HDMI_ARB_BASE_ADDR+0x3021 +#define HDMI_PHY_I2CM_DATAO_1_ADDR HDMI_ARB_BASE_ADDR+0x3022 +#define HDMI_PHY_I2CM_DATAO_0_ADDR HDMI_ARB_BASE_ADDR+0x3023 +#define HDMI_PHY_I2CM_DATAI_1_ADDR HDMI_ARB_BASE_ADDR+0x3024 +#define HDMI_PHY_I2CM_DATAI_0_ADDR HDMI_ARB_BASE_ADDR+0x3025 +#define HDMI_PHY_I2CM_OPERATION_ADDR HDMI_ARB_BASE_ADDR+0x3026 +#define HDMI_PHY_I2CM_INT_ADDR HDMI_ARB_BASE_ADDR+0x3027 +#define HDMI_PHY_I2CM_CTLINT_ADDR HDMI_ARB_BASE_ADDR+0x3028 +#define HDMI_PHY_I2CM_DIV_ADDR HDMI_ARB_BASE_ADDR+0x3029 +#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR HDMI_ARB_BASE_ADDR+0x302a +#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x302b +#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x302c +#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x302d +#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x302e +#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x302f +#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x3030 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x3031 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x3032 + +// Generic Parallel Audio Interface Registers +#define HDMI_GP_CONF0 HDMI_ARB_BASE_ADDR+0x3500 +#define HDMI_GP_CONF1 HDMI_ARB_BASE_ADDR+0x3501 +#define HDMI_GP_CONF2 HDMI_ARB_BASE_ADDR+0x3502 +#define HDMI_GP_STAT HDMI_ARB_BASE_ADDR+0x3503 +#define HDMI_GP_INT HDMI_ARB_BASE_ADDR+0x3504 +#define HDMI_GP_MASK HDMI_ARB_BASE_ADDR+0x3505 +#define HDMI_GP_POL HDMI_ARB_BASE_ADDR+0x3506 + +// Audio DMA Registers (TBD) +#define HDMI_AHB_DMA_CONF0 HDMI_ARB_BASE_ADDR+0x3600 +#define HDMI_AHB_DMA_START HDMI_ARB_BASE_ADDR+0x3601 +#define HDMI_AHB_DMA_STOP HDMI_ARB_BASE_ADDR+0x3602 +#define HDMI_AHB_DMA_THRSLD HDMI_ARB_BASE_ADDR+0x3603 +#define HDMI_AHB_DMA_STRADDR0 HDMI_ARB_BASE_ADDR+0x3604 +#define HDMI_AHB_DMA_STRADDR1 HDMI_ARB_BASE_ADDR+0x3605 +#define HDMI_AHB_DMA_STRADDR2 HDMI_ARB_BASE_ADDR+0x3606 +#define HDMI_AHB_DMA_STRADDR3 HDMI_ARB_BASE_ADDR+0x3607 +#define HDMI_AHB_DMA_STPADDR0 HDMI_ARB_BASE_ADDR+0x3608 +#define HDMI_AHB_DMA_STPADDR1 HDMI_ARB_BASE_ADDR+0x3609 +#define HDMI_AHB_DMA_STPADDR2 HDMI_ARB_BASE_ADDR+0x360a +#define HDMI_AHB_DMA_STPADDR3 HDMI_ARB_BASE_ADDR+0x360b +#define HDMI_AHB_DMA_BSTADDR0 HDMI_ARB_BASE_ADDR+0x360c +#define HDMI_AHB_DMA_BSTADDR1 HDMI_ARB_BASE_ADDR+0x360d +#define HDMI_AHB_DMA_BSTADDR2 HDMI_ARB_BASE_ADDR+0x360e +#define HDMI_AHB_DMA_BSTADDR3 HDMI_ARB_BASE_ADDR+0x360f +#define HDMI_AHB_DMA_MBLENGTH0 HDMI_ARB_BASE_ADDR+0x3610 +#define HDMI_AHB_DMA_MBLENGTH1 HDMI_ARB_BASE_ADDR+0x3611 +#define HDMI_AHB_DMA_STAT HDMI_ARB_BASE_ADDR+0x3612 +#define HDMI_AHB_DMA_INT HDMI_ARB_BASE_ADDR+0x3613 +#define HDMI_AHB_DMA_MASK HDMI_ARB_BASE_ADDR+0x3614 +#define HDMI_AHB_DMA_POL HDMI_ARB_BASE_ADDR+0x3615 + +// Main Controller Registers +#define HDMI_MC_SFRDIV HDMI_ARB_BASE_ADDR+0x4000 +#define HDMI_MC_CLKDIS HDMI_ARB_BASE_ADDR+0x4001 +#define HDMI_MC_SWRSTZ HDMI_ARB_BASE_ADDR+0x4002 +#define HDMI_MC_OPCTRL HDMI_ARB_BASE_ADDR+0x4003 +#define HDMI_MC_FLOWCTRL HDMI_ARB_BASE_ADDR+0x4004 +#define HDMI_MC_PHYRSTZ HDMI_ARB_BASE_ADDR+0x4005 +#define HDMI_MC_LOCKONCLOCK HDMI_ARB_BASE_ADDR+0x4006 +#define HDMI_MC_HEACPHY_RST HDMI_ARB_BASE_ADDR+0x4007 + +// Color Space Converter Registers +#define HDMI_CSC_CFG HDMI_ARB_BASE_ADDR+0x4100 +#define HDMI_CSC_SCALE HDMI_ARB_BASE_ADDR+0x4101 +#define HDMI_CSC_COEF_A1_MSB HDMI_ARB_BASE_ADDR+0x4102 +#define HDMI_CSC_COEF_A1_LSB HDMI_ARB_BASE_ADDR+0x4103 +#define HDMI_CSC_COEF_A2_MSB HDMI_ARB_BASE_ADDR+0x4104 +#define HDMI_CSC_COEF_A2_LSB HDMI_ARB_BASE_ADDR+0x4105 +#define HDMI_CSC_COEF_A3_MSB HDMI_ARB_BASE_ADDR+0x4106 +#define HDMI_CSC_COEF_A3_LSB HDMI_ARB_BASE_ADDR+0x4107 +#define HDMI_CSC_COEF_A4_MSB HDMI_ARB_BASE_ADDR+0x4108 +#define HDMI_CSC_COEF_A4_LSB HDMI_ARB_BASE_ADDR+0x4109 +#define HDMI_CSC_COEF_B1_MSB HDMI_ARB_BASE_ADDR+0x410A +#define HDMI_CSC_COEF_B1_LSB HDMI_ARB_BASE_ADDR+0x410B +#define HDMI_CSC_COEF_B2_MSB HDMI_ARB_BASE_ADDR+0x410C +#define HDMI_CSC_COEF_B2_LSB HDMI_ARB_BASE_ADDR+0x410D +#define HDMI_CSC_COEF_B3_MSB HDMI_ARB_BASE_ADDR+0x410E +#define HDMI_CSC_COEF_B3_LSB HDMI_ARB_BASE_ADDR+0x410F +#define HDMI_CSC_COEF_B4_MSB HDMI_ARB_BASE_ADDR+0x4110 +#define HDMI_CSC_COEF_B4_LSB HDMI_ARB_BASE_ADDR+0x4111 +#define HDMI_CSC_COEF_C1_MSB HDMI_ARB_BASE_ADDR+0x4112 +#define HDMI_CSC_COEF_C1_LSB HDMI_ARB_BASE_ADDR+0x4113 +#define HDMI_CSC_COEF_C2_MSB HDMI_ARB_BASE_ADDR+0x4114 +#define HDMI_CSC_COEF_C2_LSB HDMI_ARB_BASE_ADDR+0x4115 +#define HDMI_CSC_COEF_C3_MSB HDMI_ARB_BASE_ADDR+0x4116 +#define HDMI_CSC_COEF_C3_LSB HDMI_ARB_BASE_ADDR+0x4117 +#define HDMI_CSC_COEF_C4_MSB HDMI_ARB_BASE_ADDR+0x4118 +#define HDMI_CSC_COEF_C4_LSB HDMI_ARB_BASE_ADDR+0x4119 + +// HDCP Encryption Engine Registers +#define HDMI_A_HDCPCFG0 HDMI_ARB_BASE_ADDR+0x5000 +#define HDMI_A_HDCPCFG1 HDMI_ARB_BASE_ADDR+0x5001 +#define HDMI_A_HDCPOBS0 HDMI_ARB_BASE_ADDR+0x5002 +#define HDMI_A_HDCPOBS1 HDMI_ARB_BASE_ADDR+0x5003 +#define HDMI_A_HDCPOBS2 HDMI_ARB_BASE_ADDR+0x5004 +#define HDMI_A_HDCPOBS3 HDMI_ARB_BASE_ADDR+0x5005 +#define HDMI_A_APIINTCLR HDMI_ARB_BASE_ADDR+0x5006 +#define HDMI_A_APIINTSTAT HDMI_ARB_BASE_ADDR+0x5007 +#define HDMI_A_APIINTMSK HDMI_ARB_BASE_ADDR+0x5008 +#define HDMI_A_VIDPOLCFG HDMI_ARB_BASE_ADDR+0x5009 +#define HDMI_A_OESSWCFG HDMI_ARB_BASE_ADDR+0x500A +#define HDMI_A_TIMER1SETUP0 HDMI_ARB_BASE_ADDR+0x500B +#define HDMI_A_TIMER1SETUP1 HDMI_ARB_BASE_ADDR+0x500C +#define HDMI_A_TIMER2SETUP0 HDMI_ARB_BASE_ADDR+0x500D +#define HDMI_A_TIMER2SETUP1 HDMI_ARB_BASE_ADDR+0x500E +#define HDMI_A_100MSCFG HDMI_ARB_BASE_ADDR+0x500F +#define HDMI_A_2SCFG0 HDMI_ARB_BASE_ADDR+0x5010 +#define HDMI_A_2SCFG1 HDMI_ARB_BASE_ADDR+0x5011 +#define HDMI_A_5SCFG0 HDMI_ARB_BASE_ADDR+0x5012 +#define HDMI_A_5SCFG1 HDMI_ARB_BASE_ADDR+0x5013 +#define HDMI_A_SRMVERLSB HDMI_ARB_BASE_ADDR+0x5014 +#define HDMI_A_SRMVERMSB HDMI_ARB_BASE_ADDR+0x5015 +#define HDMI_A_SRMCTRL HDMI_ARB_BASE_ADDR+0x5016 +#define HDMI_A_SFRSETUP HDMI_ARB_BASE_ADDR+0x5017 +#define HDMI_A_I2CHSETUP HDMI_ARB_BASE_ADDR+0x5018 +#define HDMI_A_INTSETUP HDMI_ARB_BASE_ADDR+0x5019 +#define HDMI_A_PRESETUP HDMI_ARB_BASE_ADDR+0x501A +#define HDMI_A_SRM_BASE HDMI_ARB_BASE_ADDR+0x5020 + +// CEC Engine Registers +#define HDMI_CEC_CTRL HDMI_ARB_BASE_ADDR+0x7D00 +#define HDMI_CEC_STAT HDMI_ARB_BASE_ADDR+0x7D01 +#define HDMI_CEC_MASK HDMI_ARB_BASE_ADDR+0x7D02 +#define HDMI_CEC_POLARITY HDMI_ARB_BASE_ADDR+0x7D03 +#define HDMI_CEC_INT HDMI_ARB_BASE_ADDR+0x7D04 +#define HDMI_CEC_ADDR_L HDMI_ARB_BASE_ADDR+0x7D05 +#define HDMI_CEC_ADDR_H HDMI_ARB_BASE_ADDR+0x7D06 +#define HDMI_CEC_TX_CNT HDMI_ARB_BASE_ADDR+0x7D07 +#define HDMI_CEC_RX_CNT HDMI_ARB_BASE_ADDR+0x7D08 +#define HDMI_CEC_TX_DATA0 HDMI_ARB_BASE_ADDR+0x7D10 +#define HDMI_CEC_TX_DATA1 HDMI_ARB_BASE_ADDR+0x7D11 +#define HDMI_CEC_TX_DATA2 HDMI_ARB_BASE_ADDR+0x7D12 +#define HDMI_CEC_TX_DATA3 HDMI_ARB_BASE_ADDR+0x7D13 +#define HDMI_CEC_TX_DATA4 HDMI_ARB_BASE_ADDR+0x7D14 +#define HDMI_CEC_TX_DATA5 HDMI_ARB_BASE_ADDR+0x7D15 +#define HDMI_CEC_TX_DATA6 HDMI_ARB_BASE_ADDR+0x7D16 +#define HDMI_CEC_TX_DATA7 HDMI_ARB_BASE_ADDR+0x7D17 +#define HDMI_CEC_TX_DATA8 HDMI_ARB_BASE_ADDR+0x7D18 +#define HDMI_CEC_TX_DATA9 HDMI_ARB_BASE_ADDR+0x7D19 +#define HDMI_CEC_TX_DATA10 HDMI_ARB_BASE_ADDR+0x7D1a +#define HDMI_CEC_TX_DATA11 HDMI_ARB_BASE_ADDR+0x7D1b +#define HDMI_CEC_TX_DATA12 HDMI_ARB_BASE_ADDR+0x7D1c +#define HDMI_CEC_TX_DATA13 HDMI_ARB_BASE_ADDR+0x7D1d +#define HDMI_CEC_TX_DATA14 HDMI_ARB_BASE_ADDR+0x7D1e +#define HDMI_CEC_TX_DATA15 HDMI_ARB_BASE_ADDR+0x7D1f +#define HDMI_CEC_RX_DATA0 HDMI_ARB_BASE_ADDR+0x7D20 +#define HDMI_CEC_RX_DATA1 HDMI_ARB_BASE_ADDR+0x7D21 +#define HDMI_CEC_RX_DATA2 HDMI_ARB_BASE_ADDR+0x7D22 +#define HDMI_CEC_RX_DATA3 HDMI_ARB_BASE_ADDR+0x7D23 +#define HDMI_CEC_RX_DATA4 HDMI_ARB_BASE_ADDR+0x7D24 +#define HDMI_CEC_RX_DATA5 HDMI_ARB_BASE_ADDR+0x7D25 +#define HDMI_CEC_RX_DATA6 HDMI_ARB_BASE_ADDR+0x7D26 +#define HDMI_CEC_RX_DATA7 HDMI_ARB_BASE_ADDR+0x7D27 +#define HDMI_CEC_RX_DATA8 HDMI_ARB_BASE_ADDR+0x7D28 +#define HDMI_CEC_RX_DATA9 HDMI_ARB_BASE_ADDR+0x7D29 +#define HDMI_CEC_RX_DATA10 HDMI_ARB_BASE_ADDR+0x7D2a +#define HDMI_CEC_RX_DATA11 HDMI_ARB_BASE_ADDR+0x7D2b +#define HDMI_CEC_RX_DATA12 HDMI_ARB_BASE_ADDR+0x7D2c +#define HDMI_CEC_RX_DATA13 HDMI_ARB_BASE_ADDR+0x7D2d +#define HDMI_CEC_RX_DATA14 HDMI_ARB_BASE_ADDR+0x7D2e +#define HDMI_CEC_RX_DATA15 HDMI_ARB_BASE_ADDR+0x7D2f +#define HDMI_CEC_LOCK HDMI_ARB_BASE_ADDR+0x7D30 +#define HDMI_CEC_WKUPCTRL HDMI_ARB_BASE_ADDR+0x7D31 + +// I2C Master Registers (E-DDC) +#define HDMI_I2CM_SLAVE HDMI_ARB_BASE_ADDR+0x7E00 +#define HDMI_I2CMESS HDMI_ARB_BASE_ADDR+0x7E01 +#define HDMI_I2CM_DATAO HDMI_ARB_BASE_ADDR+0x7E02 +#define HDMI_I2CM_DATAI HDMI_ARB_BASE_ADDR+0x7E03 +#define HDMI_I2CM_OPERATION HDMI_ARB_BASE_ADDR+0x7E04 +#define HDMI_I2CM_INT HDMI_ARB_BASE_ADDR+0x7E05 +#define HDMI_I2CM_CTLINT HDMI_ARB_BASE_ADDR+0x7E06 +#define HDMI_I2CM_DIV HDMI_ARB_BASE_ADDR+0x7E07 +#define HDMI_I2CM_SEGADDR HDMI_ARB_BASE_ADDR+0x7E08 +#define HDMI_I2CM_SOFTRSTZ HDMI_ARB_BASE_ADDR+0x7E09 +#define HDMI_I2CM_SEGPTR HDMI_ARB_BASE_ADDR+0x7E0A +#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x7E0B +#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x7E0C +#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x7E0D +#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x7E0E +#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x7E0F +#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x7E10 +#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x7E11 +#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x7E12 + +// Random Number Generator Registers (RNG) +#define HDMI_RNG_BASE HDMI_ARB_BASE_ADDR+0x8000 + +#endif //HDMI_COMMON_H diff --git a/bsp/imx6ul/platform/include/mx6ul/iim_fuse.h b/bsp/imx6ul/platform/include/mx6ul/iim_fuse.h new file mode 100644 index 0000000000000000000000000000000000000000..41e1518f31ab16ae93c4fb105fdff531985acfca --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/iim_fuse.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. +*/ + +#ifndef __IIM_FUSE_H__ +#define __IIM_FUSE_H__ + +#define IIM_STAT_OFF 0x00 +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) +#define IIM_STATM_OFF 0x04 +#define IIM_ERR_OFF 0x08 +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) +#define IIM_EMASK_OFF 0x0C +#define IIM_FCTL_OFF 0x10 +#define IIM_UA_OFF 0x14 +#define IIM_LA_OFF 0x18 +#define IIM_SDAT_OFF 0x1C +#define IIM_PREV_OFF 0x20 +#define IIM_SREV_OFF 0x24 +#define IIM_PREG_P_OFF 0x28 +#define IIM_SCS0_OFF 0x2C +#define IIM_SCS1_P_OFF 0x30 +#define IIM_SCS2_OFF 0x34 +#define IIM_SCS3_P_OFF 0x38 + +//unsigned int sense_fuse(int bank, int row); +//int fuse_blow(int bank, int row, int bit); + +#endif // __IIM_FUSE_H__ diff --git a/bsp/imx6ul/platform/include/mx6ul/imx6ul-pinfunc.h b/bsp/imx6ul/platform/include/mx6ul/imx6ul-pinfunc.h new file mode 100644 index 0000000000000000000000000000000000000000..dc66fe20edaba30ae0460eb97f07a89c35bd595e --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/imx6ul-pinfunc.h @@ -0,0 +1,915 @@ +/* + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX6UL_PINFUNC_H +#define __DTS_IMX6UL_PINFUNC_H + +#define PIN_CFG(mux_ctl_offset, pad_ctl_offset, select_input_offset, mux_mode, daisy, pad_setting) \ + do {\ + writel(mux_mode, IOMUXC_BASE_ADDR + mux_ctl_offset);\ + if (select_input_offset != 0)\ + writel(daisy, IOMUXC_BASE_ADDR + select_input_offset);\ + writel(pad_setting, IOMUXC_BASE_ADDR + pad_ctl_offset);\ + } while(0); + +/* + * The pin function ID is a tuple of + * + */ +#define MX6UL_PAD_JTAG_MOD__SJC_MOD(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_JTAG_MOD__GPT2_CLK(p) PIN_CFG(0x0044, 0x02D0, 0x05A0, 0x1, 0x0, p) +#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY(p) PIN_CFG(0x0044, 0x02D0, 0x04C0, 0x4, 0x0, p) +#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_JTAG_TMS__SJC_TMS(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1(p) PIN_CFG(0x0048, 0x02D4, 0x0598, 0x1, 0x0, p) +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_JTAG_TMS__CCM_WAIT(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_JTAG_TDO__SJC_TDO(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2(p) PIN_CFG(0x004C, 0x02D8, 0x059C, 0x1, 0x0, p) +#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC(p) PIN_CFG(0x004C, 0x02D8, 0x05FC, 0x2, 0x0, p) +#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_JTAG_TDO__CCM_STOP(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_JTAG_TDI__SJC_TDI(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK(p) PIN_CFG(0x0050, 0x02DC, 0x05F8, 0x2, 0x0, p) +#define MX6UL_PAD_JTAG_TDI__PWM6_OUT(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_JTAG_TDI__MQS_LEFT(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_JTAG_TCK__SJC_TCK(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_JTAG_TCK__PWM7_OUT(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL(p) PIN_CFG(0x005C, 0x02E8, 0x05AC, 0x0, 0x1, p) +#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1(p) PIN_CFG(0x005C, 0x02E8, 0x058C, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID(p) PIN_CFG(0x005C, 0x02E8, 0x04B8, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1(p) PIN_CFG(0x005C, 0x02E8, 0x0574, 0x3, 0x0, p) +#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA(p) PIN_CFG(0x0060, 0x02EC, 0x05B0, 0x0, 0x1, p) +#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC(p) PIN_CFG(0x0060, 0x02EC, 0x0664, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2(p) PIN_CFG(0x0060, 0x02EC, 0x057C, 0x3, 0x0, p) +#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL(p) PIN_CFG(0x0064, 0x02F0, 0x05A4, 0x0, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP(p) PIN_CFG(0x0064, 0x02F0, 0x066C, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_GPIO1_IO02__UART1_TX(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA(p) PIN_CFG(0x0068, 0x02F4, 0x05A8, 0x0, 0x1, p) +#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC(p) PIN_CFG(0x0068, 0x02F4, 0x0660, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B(p) PIN_CFG(0x0068, 0x02F4, 0x0668, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_GPIO1_IO03__UART1_RX(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1(p) PIN_CFG(0x006C, 0x02F8, 0x0574, 0x0, 0x1, p) +#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO04__UART5_TX(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2(p) PIN_CFG(0x0070, 0x02FC, 0x057C, 0x0, 0x1, p) +#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID(p) PIN_CFG(0x0070, 0x02FC, 0x04BC, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD(p) PIN_CFG(0x0070, 0x02FC, 0x0530, 0x3, 0x0, p) +#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO05__UART5_RX(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO(p) PIN_CFG(0x0074, 0x0300, 0x0578, 0x0, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO(p) PIN_CFG(0x0074, 0x0300, 0x0580, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP(p) PIN_CFG(0x0074, 0x0300, 0x069C, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK(p) PIN_CFG(0x0078, 0x0304, 0x0528, 0x3, 0x0, p) +#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B(p) PIN_CFG(0x0078, 0x0304, 0x0674, 0x4, 0x1, p) +#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO07__CCM_STOP(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC(p) PIN_CFG(0x007C, 0x0308, 0x052C, 0x3, 0x1, p) +#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY(p) PIN_CFG(0x007C, 0x0308, 0x04C0, 0x6, 0x1, p) +#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN(p) PIN_CFG(0x0080, 0x030C, 0x0618, 0x2, 0x0, p) +#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC(p) PIN_CFG(0x0080, 0x030C, 0x0524, 0x3, 0x1, p) +#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART1_TX_DATA__UART1_TX(p) PIN_CFG(0x0084, 0x0310, 0x0624, 0x0, 0x2, p) +#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL(p) PIN_CFG(0x0084, 0x0310, 0x05B4, 0x2, 0x0, p) +#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART1_RX_DATA__UART1_RX(p) PIN_CFG(0x0088, 0x0314, 0x0624, 0x0, 0x3, p) +#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03(p) PIN_CFG(0x0088, 0x0314, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA(p) PIN_CFG(0x0088, 0x0314, 0x05B8, 0x2, 0x0, p) +#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03(p) PIN_CFG(0x0088, 0x0314, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK(p) PIN_CFG(0x0088, 0x0314, 0x0594, 0x4, 0x0, p) +#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17(p) PIN_CFG(0x0088, 0x0314, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN(p) PIN_CFG(0x0088, 0x0314, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS(p) PIN_CFG(0x008C, 0x0318, 0x0620, 0x0, 0x2, p) +#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP(p) PIN_CFG(0x008C, 0x0318, 0x066C, 0x2, 0x1, p) +#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS(p) PIN_CFG(0x0090, 0x031C, 0x0620, 0x0, 0x3, p) +#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B(p) PIN_CFG(0x0090, 0x031C, 0x0668, 0x2, 0x1, p) +#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART2_TX_DATA__UART2_TX(p) PIN_CFG(0x0094, 0x0320, 0x062C, 0x0, 0x0, p) +#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02(p) PIN_CFG(0x0094, 0x0320, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL(p) PIN_CFG(0x0094, 0x0320, 0x05BC, 0x2, 0x0, p) +#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06(p) PIN_CFG(0x0094, 0x0320, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1(p) PIN_CFG(0x0094, 0x0320, 0x058C, 0x4, 0x1, p) +#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20(p) PIN_CFG(0x0094, 0x0320, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0(p) PIN_CFG(0x0094, 0x0320, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART2_RX_DATA__UART2_RX(p) PIN_CFG(0x0098, 0x0324, 0x062C, 0x0, 0x1, p) +#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA(p) PIN_CFG(0x0098, 0x0324, 0x05C0, 0x2, 0x0, p) +#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2(p) PIN_CFG(0x0098, 0x0324, 0x0590, 0x4, 0x0, p) +#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS(p) PIN_CFG(0x009C, 0x0328, 0x0628, 0x0, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x12, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS(p) PIN_CFG(0x00A0, 0x032C, 0x0628, 0x0, 0x1, p) +#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_UART2_RTS_B__ENET1_COL(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX(p) PIN_CFG(0x00A0, 0x032C, 0x0588, 0x12, 0x0, p) +#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART3_TX_DATA__UART3_TX(p) PIN_CFG(0x00A4, 0x0330, 0x0634, 0x0, 0x0, p) +#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS(p) PIN_CFG(0x00A4, 0x0330, 0x0628, 0x4, 0x2, p) +#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x7, 0x0, p) +#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART3_RX_DATA__UART3_RX(p) PIN_CFG(0x00A8, 0x0334, 0x0634, 0x0, 0x1, p) +#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS(p) PIN_CFG(0x00A8, 0x0334, 0x0628, 0x4, 0x3, p) +#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS(p) PIN_CFG(0x00AC, 0x0338, 0x0630, 0x0, 0x0, p) +#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x12, 0x0, p) +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS(p) PIN_CFG(0x00B0, 0x033C, 0x0630, 0x0, 0x1, p) +#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX(p) PIN_CFG(0x00B0, 0x033C, 0x0584, 0x12, 0x0, p) +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART4_TX_DATA__UART4_TX(p) PIN_CFG(0x00B4, 0x0340, 0x063C, 0x0, 0x0, p) +#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL(p) PIN_CFG(0x00B4, 0x0340, 0x05A4, 0x12, 0x1, p) +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART4_RX_DATA__UART4_RX(p) PIN_CFG(0x00B8, 0x0344, 0x063C, 0x0, 0x1, p) +#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA(p) PIN_CFG(0x00B8, 0x0344, 0x05A8, 0x12, 0x2, p) +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_UART5_TX_DATA__UART5_TX(p) PIN_CFG(0x00BC, 0x0348, 0x0644, 0x0, 0x4, p) +#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL(p) PIN_CFG(0x00BC, 0x0348, 0x05AC, 0x12, 0x2, p) +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART5_RX_DATA__UART5_RX(p) PIN_CFG(0x00C0, 0x034C, 0x0644, 0x0, 0x5, p) +#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA(p) PIN_CFG(0x00C0, 0x034C, 0x05B0, 0x12, 0x2, p) +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS(p) PIN_CFG(0x00C4, 0x0350, 0x0638, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS(p) PIN_CFG(0x00C8, 0x0354, 0x0638, 0x1, 0x1, p) +#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX(p) PIN_CFG(0x00C8, 0x0354, 0x0584, 0x4, 0x1, p) +#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS(p) PIN_CFG(0x00CC, 0x0358, 0x0640, 0x1, 0x3, p) +#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS(p) PIN_CFG(0x00D0, 0x035C, 0x0640, 0x1, 0x4, p) +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX(p) PIN_CFG(0x00D0, 0x035C, 0x0588, 0x4, 0x1, p) +#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS(p) PIN_CFG(0x00D4, 0x0360, 0x0648, 0x1, 0x2, p) +#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO(p) PIN_CFG(0x00D4, 0x0360, 0x0580, 0x4, 0x1, p) +#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS(p) PIN_CFG(0x00D8, 0x0364, 0x0648, 0x1, 0x3, p) +#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS(p) PIN_CFG(0x00DC, 0x0368, 0x0650, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1(p) PIN_CFG(0x00DC, 0x0368, 0x0574, 0x14, 0x2, p) +#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS(p) PIN_CFG(0x00E0, 0x036C, 0x0650, 0x1, 0x1, p) +#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_TX(p) PIN_CFG(0x00E4, 0x0370, 0x064C, 0x1, 0x1, p) +#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL(p) PIN_CFG(0x00E4, 0x0370, 0x05B4, 0x3, 0x1, p) +#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO(p) PIN_CFG(0x00E4, 0x0370, 0x0578, 0x4, 0x1, p) +#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_RX(p) PIN_CFG(0x00E8, 0x0374, 0x064C, 0x1, 0x2, p) +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA(p) PIN_CFG(0x00E8, 0x0374, 0x05B8, 0x3, 0x1, p) +#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET2_RX_EN__UART7_TX(p) PIN_CFG(0x00EC, 0x0378, 0x0654, 0x1, 0x0, p) +#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL(p) PIN_CFG(0x00EC, 0x0378, 0x05BC, 0x3, 0x1, p) +#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_RX(p) PIN_CFG(0x00F0, 0x037C, 0x0654, 0x1, 0x1, p) +#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA(p) PIN_CFG(0x00F0, 0x037C, 0x05C0, 0x3, 0x1, p) +#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_TX(p) PIN_CFG(0x00F4, 0x0380, 0x065C, 0x1, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK(p) PIN_CFG(0x00F4, 0x0380, 0x0564, 0x3, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET2_TX_EN__UART8_RX(p) PIN_CFG(0x00F8, 0x0384, 0x065C, 0x1, 0x1, p) +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI(p) PIN_CFG(0x00F8, 0x0384, 0x056C, 0x3, 0x0, p) +#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS(p) PIN_CFG(0x00FC, 0x0388, 0x0658, 0x1, 0x0, p) +#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO(p) PIN_CFG(0x00FC, 0x0388, 0x0568, 0x3, 0x0, p) +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2(p) PIN_CFG(0x00FC, 0x0388, 0x057C, 0x14, 0x2, p) +#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS(p) PIN_CFG(0x0100, 0x038C, 0x0658, 0x1, 0x1, p) +#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_CLK__LCDIF_CLK(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_CLK__UART4_TX(p) PIN_CFG(0x0104, 0x0390, 0x063C, 0x2, 0x2, p) +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_CLK__EIM_CS2_B(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_CLK__GPIO3_IO00(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_ENABLE__UART4_RX(p) PIN_CFG(0x0108, 0x0394, 0x063C, 0x2, 0x3, p) +#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC(p) PIN_CFG(0x0108, 0x0394, 0x060C, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC(p) PIN_CFG(0x010C, 0x0398, 0x05DC, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS(p) PIN_CFG(0x010C, 0x0398, 0x0638, 0x2, 0x2, p) +#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK(p) PIN_CFG(0x010C, 0x0398, 0x0608, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY(p) PIN_CFG(0x0110, 0x039C, 0x05DC, 0x1, 0x1, p) +#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS(p) PIN_CFG(0x0110, 0x039C, 0x0638, 0x2, 0x3, p) +#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_RESET__LCDIF_RESET(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_RESET__LCDIF_CS(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_RESET__GPIO3_IO04(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA00__PWM1_OUT(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA00__I2C3_SDA(p) PIN_CFG(0x0118, 0x03A4, 0x05B8, 0x4, 0x2, p) +#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA01__PWM2_OUT(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA01__I2C3_SCL(p) PIN_CFG(0x011C, 0x03A8, 0x05B4, 0x4, 0x2, p) +#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA02__PWM3_OUT(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA02__I2C4_SDA(p) PIN_CFG(0x0120, 0x03AC, 0x05C0, 0x4, 0x2, p) +#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA03__PWM4_OUT(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA03__I2C4_SCL(p) PIN_CFG(0x0124, 0x03B0, 0x05BC, 0x4, 0x2, p) +#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS(p) PIN_CFG(0x0128, 0x03B4, 0x0658, 0x1, 0x2, p) +#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS(p) PIN_CFG(0x012C, 0x03B8, 0x0658, 0x1, 0x3, p) +#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS(p) PIN_CFG(0x0130, 0x03BC, 0x0650, 0x1, 0x2, p) +#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS(p) PIN_CFG(0x0134, 0x03C0, 0x0650, 0x1, 0x3, p) +#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK(p) PIN_CFG(0x0134, 0x03C0, 0x061C, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA08__SPDIF_IN(p) PIN_CFG(0x0138, 0x03C4, 0x0618, 0x1, 0x2, p) +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA08__EIM_DATA00(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA09__EIM_DATA01(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA10__EIM_DATA02(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA11__EIM_DATA03(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC(p) PIN_CFG(0x0148, 0x03D4, 0x060C, 0x1, 0x1, p) +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA12__EIM_DATA04(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK(p) PIN_CFG(0x014C, 0x03D8, 0x0608, 0x1, 0x1, p) +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA13__EIM_DATA05(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA14__EIM_DATA06(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA15__EIM_DATA07(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA16__UART7_TX(p) PIN_CFG(0x0158, 0x03E4, 0x0654, 0x1, 0x2, p) +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA16__EIM_DATA08(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA17__UART7_RX(p) PIN_CFG(0x015C, 0x03E8, 0x0654, 0x1, 0x3, p) +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA17__EIM_DATA09(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA18__PWM5_OUT(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA18__EIM_DATA10(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA19__EIM_DATA11(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA19__PWM6_OUT(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA20__EIM_DATA12(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA20__UART8_TX(p) PIN_CFG(0x0168, 0x03F4, 0x065C, 0x1, 0x2, p) +#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK(p) PIN_CFG(0x0168, 0x03F4, 0x0534, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA21__UART8_RX(p) PIN_CFG(0x016C, 0x03F8, 0x065C, 0x1, 0x3, p) +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA21__EIM_DATA13(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI(p) PIN_CFG(0x0170, 0x03FC, 0x053C, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA22__EIM_DATA14(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_LCD_DATA23__MQS_LEFT(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO(p) PIN_CFG(0x0174, 0x0400, 0x0538, 0x2, 0x0, p) +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_LCD_DATA23__EIM_DATA15(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK(p) PIN_CFG(0x0178, 0x0404, 0x0670, 0x1, 0x2, p) +#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD(p) PIN_CFG(0x017C, 0x0408, 0x0678, 0x1, 0x2, p) +#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_WE_B__KPP_COL00(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0(p) PIN_CFG(0x0180, 0x040C, 0x067C, 0x1, 0x2, p) +#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_DATA00__EIM_AD08(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1(p) PIN_CFG(0x0184, 0x0410, 0x0680, 0x1, 0x2, p) +#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DATA01__KPP_COL01(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_DATA01__EIM_AD09(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2(p) PIN_CFG(0x0188, 0x0414, 0x0684, 0x1, 0x1, p) +#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_DATA02__EIM_AD10(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3(p) PIN_CFG(0x018C, 0x0418, 0x0688, 0x1, 0x2, p) +#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DATA03__KPP_COL02(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_DATA03__EIM_AD11(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4(p) PIN_CFG(0x0190, 0x041C, 0x068C, 0x1, 0x1, p) +#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK(p) PIN_CFG(0x0190, 0x041C, 0x0564, 0x3, 0x1, p) +#define MX6UL_PAD_NAND_DATA04__EIM_AD12(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DATA04__UART2_TX(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5(p) PIN_CFG(0x0194, 0x0420, 0x0690, 0x1, 0x1, p) +#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI(p) PIN_CFG(0x0194, 0x0420, 0x056C, 0x3, 0x1, p) +#define MX6UL_PAD_NAND_DATA05__EIM_AD13(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DATA05__UART2_RX(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6(p) PIN_CFG(0x0198, 0x0424, 0x0694, 0x1, 0x1, p) +#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO(p) PIN_CFG(0x0198, 0x0424, 0x0568, 0x3, 0x1, p) +#define MX6UL_PAD_NAND_DATA06__EIM_AD14(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7(p) PIN_CFG(0x019C, 0x0428, 0x0698, 0x1, 0x1, p) +#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_DATA07__EIM_AD15(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_ALE__PWM3_OUT(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_ALE__EIM_ADDR17(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_ALE__GPIO4_IO10(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_WP_B__PWM4_OUT(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_WP_B__EIM_BCLK(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_READY_B__UART3_TX(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK(p) PIN_CFG(0x01AC, 0x0438, 0x0554, 0x3, 0x1, p) +#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_CE0_B__UART3_RX(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI(p) PIN_CFG(0x01B0, 0x043C, 0x055C, 0x3, 0x1, p) +#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO(p) PIN_CFG(0x01B4, 0x0440, 0x0558, 0x3, 0x1, p) +#define MX6UL_PAD_NAND_CLE__EIM_ADDR16(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_CLE__GPIO4_IO15(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_NAND_DQS__CSI_FIELD(p) PIN_CFG(0x01B8, 0x0444, 0x0530, 0x1, 0x1, p) +#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_NAND_DQS__PWM5_OUT(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_NAND_DQS__EIM_WAIT(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_NAND_DQS__GPIO4_IO16(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_SD1_CMD__USDHC1_CMD(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_SD1_CMD__SPDIF_OUT(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_SD1_CMD__EIM_ADDR19(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_SD1_CMD__GPIO2_IO16(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_SD1_CLK__USDHC1_CLK(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_SD1_CLK__SPDIF_IN(p) PIN_CFG(0x01C0, 0x044C, 0x0618, 0x3, 0x3, p) +#define MX6UL_PAD_SD1_CLK__EIM_ADDR20(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_SD1_CLK__GPIO2_IO17(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x1, 0x0, p) +#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC(p) PIN_CFG(0x01C4, 0x0450, 0x05FC, 0x2, 0x1, p) +#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1(p) PIN_CFG(0x01C8, 0x0454, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_SD1_DATA1__GPT2_CLK(p) PIN_CFG(0x01C8, 0x0454, 0x05A0, 0x1, 0x1, p) +#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK(p) PIN_CFG(0x01C8, 0x0454, 0x05F8, 0x2, 0x1, p) +#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX(p) PIN_CFG(0x01C8, 0x0454, 0x0584, 0x3, 0x3, p) +#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22(p) PIN_CFG(0x01C8, 0x0454, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19(p) PIN_CFG(0x01C8, 0x0454, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR(p) PIN_CFG(0x01C8, 0x0454, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1(p) PIN_CFG(0x01CC, 0x0458, 0x0598, 0x1, 0x1, p) +#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2(p) PIN_CFG(0x01D0, 0x045C, 0x059C, 0x1, 0x1, p) +#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX(p) PIN_CFG(0x01D0, 0x045C, 0x0588, 0x3, 0x3, p) +#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_MCLK__CSI_MCLK(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B(p) PIN_CFG(0x01D4, 0x0460, 0x0674, 0x1, 0x0, p) +#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_MCLK__I2C1_SDA(p) PIN_CFG(0x01D4, 0x0460, 0x05A8, 0x3, 0x0, p) +#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_MCLK__UART6_TX(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK(p) PIN_CFG(0x01D8, 0x0464, 0x0528, 0x0, 0x1, p) +#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP(p) PIN_CFG(0x01D8, 0x0464, 0x069C, 0x1, 0x2, p) +#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL(p) PIN_CFG(0x01D8, 0x0464, 0x05A4, 0x3, 0x2, p) +#define MX6UL_PAD_CSI_PIXCLK__EIM_OE(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_PIXCLK__UART6_RX(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC(p) PIN_CFG(0x01DC, 0x0468, 0x052C, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK(p) PIN_CFG(0x01DC, 0x0468, 0x0670, 0x1, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA(p) PIN_CFG(0x01DC, 0x0468, 0x05B0, 0x3, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__EIM_RW(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC(p) PIN_CFG(0x01E0, 0x046C, 0x0524, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD(p) PIN_CFG(0x01E0, 0x046C, 0x0678, 0x1, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL(p) PIN_CFG(0x01E0, 0x046C, 0x05AC, 0x3, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA00__CSI_DATA02(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0(p) PIN_CFG(0x01E4, 0x0470, 0x067C, 0x1, 0x0, p) +#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK(p) PIN_CFG(0x01E4, 0x0470, 0x0544, 0x3, 0x0, p) +#define MX6UL_PAD_CSI_DATA00__EIM_AD00(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_DATA00__UART5_TX(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA01__CSI_DATA03(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1(p) PIN_CFG(0x01E8, 0x0474, 0x0680, 0x1, 0x0, p) +#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_CSI_DATA01__EIM_AD01(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_DATA01__UART5_RX(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA02__CSI_DATA04(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2(p) PIN_CFG(0x01EC, 0x0478, 0x0684, 0x1, 0x2, p) +#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI(p) PIN_CFG(0x01EC, 0x0478, 0x054C, 0x3, 0x1, p) +#define MX6UL_PAD_CSI_DATA02__EIM_AD02(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__CSI_DATA05(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3(p) PIN_CFG(0x01F0, 0x047C, 0x0688, 0x1, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO(p) PIN_CFG(0x01F0, 0x047C, 0x0548, 0x3, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__EIM_AD03(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA04__CSI_DATA06(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4(p) PIN_CFG(0x01F4, 0x0480, 0x068C, 0x1, 0x2, p) +#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK(p) PIN_CFG(0x01F4, 0x0480, 0x0534, 0x3, 0x1, p) +#define MX6UL_PAD_CSI_DATA04__EIM_AD04(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC(p) PIN_CFG(0x01F4, 0x0480, 0x05EC, 0x6, 0x1, p) +#define MX6UL_PAD_CSI_DATA04__USDHC1_WP(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA05__CSI_DATA07(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5(p) PIN_CFG(0x01F8, 0x0484, 0x0690, 0x1, 0x2, p) +#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x3, 0x0, p) +#define MX6UL_PAD_CSI_DATA05__EIM_AD05(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK(p) PIN_CFG(0x01F8, 0x0484, 0x05E8, 0x6, 0x1, p) +#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA06__CSI_DATA08(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6(p) PIN_CFG(0x01FC, 0x0488, 0x0694, 0x1, 0x2, p) +#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI(p) PIN_CFG(0x01FC, 0x0488, 0x053C, 0x3, 0x1, p) +#define MX6UL_PAD_CSI_DATA06__EIM_AD06(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x8, 0x0, p) +#define MX6UL_PAD_CSI_DATA07__CSI_DATA09(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x0, 0x0, p) +#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7(p) PIN_CFG(0x0200, 0x048C, 0x0698, 0x1, 0x2, p) +#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x2, 0x0, p) +#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO(p) PIN_CFG(0x0200, 0x048C, 0x0538, 0x3, 0x1, p) +#define MX6UL_PAD_CSI_DATA07__EIM_AD07(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x4, 0x0, p) +#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x6, 0x0, p) +#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x8, 0x0, p) + +/* + * The TAMPER Pin can be used for GPIO, which depends on + * TAMPER_PIN_DISABLE[1:0] settings. + */ +#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00(p) PIN_CFG(0x001C, 0x02A8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01(p) PIN_CFG(0x0020, 0x02AC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02(p) PIN_CFG(0x0024, 0x02B0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03(p) PIN_CFG(0x0028, 0x02B4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04(p) PIN_CFG(0x002C, 0x02B8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05(p) PIN_CFG(0x0030, 0x02BC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06(p) PIN_CFG(0x0034, 0x02C0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07(p) PIN_CFG(0x0038, 0x02C4, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08(p) PIN_CFG(0x003C, 0x02C8, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09(p) PIN_CFG(0x0040, 0x02CC, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10(p) PIN_CFG(0x0014, 0x02A0, 0x0000, 0x5, 0x0, p) +#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11(p) PIN_CFG(0x0018, 0x02A4, 0x0000, 0x5, 0x0, p) + +#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/bsp/imx6ul/platform/include/mx6ul/iomux_define.h b/bsp/imx6ul/platform/include/mx6ul/iomux_define.h new file mode 100644 index 0000000000000000000000000000000000000000..f7c68064374855281924cce20150258a2714373a --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/iomux_define.h @@ -0,0 +1,107 @@ +#ifndef _IOMUX_DEFINE_H_ +#define _IOMUX_DEFINE_H_ + +#include "soc_memory_map.h" + +// IOMUXC_SW_MUX_CTL_PAD_* +// SION +#define SION_DISABLED 0x0 +#define SION_ENABLED 0x1 +// MUX_MODE +#define ALT0 0x0 +#define ALT1 0x1 +#define ALT2 0x2 +#define ALT3 0x3 +#define ALT4 0x4 +#define ALT5 0x5 +#define ALT6 0x6 +#define ALT7 0x7 + +// IOMUXC_SW_PAD_CTL_PAD_* +// IOMUXC_SW_PAD_CTL_GRP_* +// LVE +#define LVE_DISABLED 0x0 +#define LVE_ENABLED 0x1 +// HYS +#define HYS_DISABLED 0x0 +#define HYS_ENABLED 0x1 +// PUS +#define PUS_100KOHM_PD 0x0 +#define PUS_47KOHM_PU 0x1 +#define PUS_100KOHM_PU 0x2 +#define PUS_22KOHM_PU 0x3 +// PUE +#define PUE_KEEP 0x0 +#define PUE_PULL 0x1 +// PKE +#define PKE_DISABLED 0x0 +#define PKE_ENABLED 0x1 +// ODE +#define ODE_DISABLED 0x0 +#define ODE_ENABLED 0x1 +// SPEED +#define SPD_TBD 0x0 +#define SPD_50MHZ 0x1 +#define SPD_100MHZ 0x2 +#define SPD_200MHZ 0x3 +// DSE +#define DSE_DISABLED 0x0 +#define DSE_240OHM 0x1 +#define DSE_120OHM 0x2 +#define DSE_80OHM 0x3 +#define DSE_60OHM 0x4 +#define DSE_48OHM 0x5 +#define DSE_40OHM 0x6 +#define DSE_34OHM 0x7 +// SRE +#define SRE_SLOW 0x0 +#define SRE_FAST 0x1 +// ODT +#define ODT_OFF 0x0 +#define ODT_120OHM 0x1 +#define ODT_60OHM 0x2 +#define ODT_40OHM 0x3 +#define ODT_30OHM 0x4 +#define ODT_RES5 0x5 +#define ODT_20OHM 0x6 +#define ODT_RES7 0x7 +// DDR_INPUT +#define DDR_INPUT_CMOS 0x0 +#define DDR_INPUT_DIFF 0x1 +// DDR_SEL +#define DDR_SEL_LPDDR1_DDR3_DDR2_ODT 0x0 +#define DDR_SEL_DDR2 0x1 +#define DDR_SEL_LPDDR2 0x2 +#define DDR_SEL_RES0 0x3 +// DO_TRIM +#define DO_TRIM_RES0 0x0 +#define DO_TRIM_RES1 0x1 + +#define MK_PAD(HYS, PUS, PUE, PKE, ODE, SPEED, DSE, SRE) ( \ + ((HYS & 0x1) << 16) | \ + ((PUS & 0x3) << 14) | \ + ((PUE & 0x1) << 13) | \ + ((PKE & 0x1) << 12) | \ + ((ODE & 0x1) << 11) | \ + ((SPEED & 0x3) << 6 ) | \ + ((DSE & 0x7) << 3 ) | \ + ((SRE & 0x1) << 0 ) ) + +#define PAD_ENET_INPUT MK_PAD(1, 0, 0, 0, 0, 3, 5, 1) +#define PAD_ENET_OUTPUT MK_PAD(0, 0, 0, 0, 0, 3, 5, 1) +#define PAD_ENET_CTRL MK_PAD(0, 0, 0, 0, 0, 0, 3, 1) +#define PAD_GPIO_OUTPUT MK_PAD(0, 0, 0, 0, 0, 0, 2, 0) +#define PAD_GPIO_INPUT MK_PAD(0, 1, 1, 1, 0, 0, 2, 0) +#define PAD_UART_OUTPUT MK_PAD(0, 0, 0, 0, 0, 0, 2, 0) +#define PAD_UART_INPUT MK_PAD(0, 2, 0, 0, 0, 0, 2, 0) +#define PAD_I2C MK_PAD(0, 2, 0, 0, 1, 0, 2, 0) +#define PAD_I2C4 MK_PAD(0, 2, 0, 0, 1, 0, 4, 0) +#define PAD_LCD_DATA MK_PAD(0, 0, 0, 0, 0, 2, 3, 1) +#define PAD_AUDMUX MK_PAD(0, 0, 0, 0, 0, 0, 5, 1) +#define PAD_CAN MK_PAD(0, 0, 0, 0, 0, 0, 2, 0) +#define PAD_SDHC_DATA MK_PAD(0, 1, 1, 1, 0, 2, 3, 1) +#define PAD_QSPI MK_PAD(0, 0, 0, 0, 0, 3, 3, 1) +#define PAD_QSPI_PU MK_PAD(0, 1, 1, 1, 0, 3, 3, 1) + +#endif + diff --git a/bsp/imx6ul/platform/include/mx6ul/iomux_register.h b/bsp/imx6ul/platform/include/mx6ul/iomux_register.h new file mode 100644 index 0000000000000000000000000000000000000000..c75a6617c977f0486ad964516eb2e348910048e4 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/iomux_register.h @@ -0,0 +1,5 @@ +#ifndef _IOMUX_REGISTER_H_ +#define _IOMUX_REGISTER_H_ +#include "imx6ul-pinfunc.h" +#endif + diff --git a/bsp/imx6ul/platform/include/mx6ul/irq_numbers.h b/bsp/imx6ul/platform/include/mx6ul/irq_numbers.h new file mode 100644 index 0000000000000000000000000000000000000000..a962db8c1b40b989ddc0d9dcec3ca6d85fefe7e4 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/irq_numbers.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__IRQ_NUMBERS_H__) +#define __IRQ_NUMBERS_H__ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief i.MX6 interrupt numbers. +//! +//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series. +//! Use these numbers when specifying an interrupt to the GIC. +//! +//! The first 16 interrupts are special in that they are reserved for software interrupts generated +//! by the SWI instruction. +enum _imx_interrupts +{ + SW_INTERRUPT_0 = 0, //!< Software interrupt 0. + SW_INTERRUPT_1 = 1, //!< Software interrupt 1. + SW_INTERRUPT_2 = 2, //!< Software interrupt 2. + SW_INTERRUPT_3 = 3, //!< Software interrupt 3. + SW_INTERRUPT_4 = 4, //!< Software interrupt 4. + SW_INTERRUPT_5 = 5, //!< Software interrupt 5. + SW_INTERRUPT_6 = 6, //!< Software interrupt 6. + SW_INTERRUPT_7 = 7, //!< Software interrupt 7. + SW_INTERRUPT_8 = 8, //!< Software interrupt 8. + SW_INTERRUPT_9 = 9, //!< Software interrupt 9. + SW_INTERRUPT_10 = 10, //!< Software interrupt 10. + SW_INTERRUPT_11 = 11, //!< Software interrupt 11. + SW_INTERRUPT_12 = 12, //!< Software interrupt 12. + SW_INTERRUPT_13 = 13, //!< Software interrupt 13. + SW_INTERRUPT_14 = 14, //!< Software interrupt 14. + SW_INTERRUPT_15 = 15, //!< Software interrupt 15. + RSVD_INTERRUPT_16 = 16, //!< Reserved. + RSVD_INTERRUPT_17 = 17, //!< Reserved. + RSVD_INTERRUPT_18 = 18, //!< Reserved. + RSVD_INTERRUPT_19 = 19, //!< Reserved. + RSVD_INTERRUPT_20 = 20, //!< Reserved. + RSVD_INTERRUPT_21 = 21, //!< Reserved. + RSVD_INTERRUPT_22 = 22, //!< Reserved. + RSVD_INTERRUPT_23 = 23, //!< Reserved. + RSVD_INTERRUPT_24 = 24, //!< Reserved. + RSVD_INTERRUPT_25 = 25, //!< Reserved. + RSVD_INTERRUPT_26 = 26, //!< Reserved. + RSVD_INTERRUPT_27 = 27, //!< Reserved. + RSVD_INTERRUPT_28 = 28, //!< Reserved. + RSVD_INTERRUPT_29 = 29, //!< Reserved. + RSVD_INTERRUPT_30 = 30, //!< Reserved. + RSVD_INTERRUPT_31 = 31, //!< Reserved. + IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. + IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM + IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels. + IMX_INT_TSC = 35, //!< TSC + IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request. + IMX_INT_LCDIF = 37, //!< LCDIF interrupt request. + IMX_INT_BEE = 38, //!< BEE interrupt request. + IMX_INT_CSI = 39, //!< CMOS Sensor Interface interrupt request. + IMX_INT_PXP = 40, //!< PXP interrupt request. + IMX_INT_SCTR1 = 41, //!< SCTR1 + IMX_INT_SCTR2 = 42, //!< SCTR2 + IMX_INT_WDOG3 = 43, //!< WDOG3 timer reset interrupt request. + IMX_INT_INTERRUPT_44 = 44, //!< Reserved. + IMX_INT_APBH_DMA = 45, //!< APBH DMA + IMX_INT_EIM = 46, //!< EIM interrupt request. + IMX_INT_NAND_BCH = 47, //!< Reserved. + IMX_INT_NAND_GPMI = 48, //!< Reserved. + IMX_INT_UART6 = 49, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_50 = 50, //!< Reserved. + IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt. + IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt. + IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. + IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request. + IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request. + IMX_INT_SAI3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request. + IMX_INT_SAI4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request. + IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests. + IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests. + IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests. + IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests. + IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests. + IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request. + IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request. + IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request. + IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request. + IMX_INT_I2C4 = 67, //!< Reserved. + IMX_INT_I2C1 = 68, //!< I2C1 interrupt request. + IMX_INT_I2C2 = 69, //!< I2C2 interrupt request. + IMX_INT_I2C3 = 70, //!< I2C3 interrupt request. + IMX_INT_UART7 = 71, //!< Logical OR of UART5 interrupt requests. + IMX_INT_UART8 = 72, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_73 = 73, //!< Reserved. + IMX_INT_USB_OTG2 = 74, //!< USB Host 1 interrupt request. + IMX_INT_USB_OTG1 = 75, //!< USB OTG1 interrupt request. + IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request. + IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request. + IMX_INT_CAAM_JQ2 = 78, //!< SSI1 interrupt request. + IMX_INT_CAAM_ERR = 79, //!< SSI2 interrupt request. + IMX_INT_CAAM_RTIC = 80, //!< SSI3 interrupt request. + IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request. + IMX_INT_ASRC = 82, //!< Reserved. + IMX_INT_INTERRUPT_83 = 83, //!< Reserved. + IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts. + IMX_INT_INTERRUPT_85 = 85, //!< Reserved. + IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request. + IMX_INT_GPT1 = 87, // + IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt. + IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt. + IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request. + IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request. + IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request. + IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request. + IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request. + IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request. + IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request. + IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request. + IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15. + IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31. + IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15. + IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31. + IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15. + IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31. + IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15. + IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31. + IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15. + IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31. + IMX_INT_INTERRUPT_108 = 108, //!< Reserved. + IMX_INT_INTERRUPT_109 = 109, //!< Reserved. + IMX_INT_INTERRUPT_110 = 110, //!< Reserved. + IMX_INT_INTERRUPT_111 = 111, //!< Reserved. + IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request. + IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request. + IMX_INT_KPP = 114, //!< Key Pad interrupt request. + IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1. + IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2. + IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1. + IMX_INT_INTERRUPT_122 = 122, //!< Reserved. + IMX_INT_SRC = 123, //!< SRC interrupt request. + IMX_INT_INTERRUPT_124 = 124, //!< Logical OR of all L2 interrupt requests. + IMX_INT_INTERRUPT_125 = 125, //!< Parity Check error interrupt request. + IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts. + IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs. + IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC. + IMX_INT_SAI1 = 129, //!< EPDC interrupt request. + IMX_INT_SAI2 = 130, //!< EPDC interrupt request. + IMX_INT_INTERRUPT_131 = 131, //!< DCP general interrupt request. + IMX_INT_ADC1 = 132, //!< DCP channel 0 interrupt request. + IMX_INT_ADC2 = 133, //!< DCP secure interrupt request. + IMX_INT_INTERRUPT_134 = 134, //!< Reserved. + IMX_INT_INTERRUPT_135 = 135, //!< Reserved. + IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register. + IMX_INT_CAAM_0 = 137, //!< Reserved. + IMX_INT_CAAM_1 = 138, //!< Reserved. + IMX_INT_QSPI = 139, //!< Reserved. + IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request. + IMX_INT_GPT2 = 141, //!< Reserved. + IMX_INT_CAN1 = 142, //!< Reserved. + IMX_INT_CAN2 = 143, //!< Reserved. + IMX_INT_SIM1 = 144, //!< Reserved. + IMX_INT_SIM2 = 145, //!< Reserved. + IMX_INT_PWM5 = 146, //!< Fast Ethernet Controller interrupt request. + IMX_INT_PWM6 = 147, //!< Reserved. + IMX_INT_PWM7 = 148, //!< Reserved. + IMX_INT_PWM8 = 149, //!< Reserved. + IMX_INT_ENET1 = 150, //!< Reserved. + IMX_INT_ENET1_TIMER = 151, //!< Reserved. + IMX_INT_ENET2 = 152, //!< Reserved. + IMX_INT_ENET2_TIMER = 153, //!< Reserved. + IMX_INT_INTERRUPT_154 = 154, //!< Reserved. + IMX_INT_INTERRUPT_155 = 155, //!< Reserved. + IMX_INT_INTERRUPT_156 = 156, //!< Reserved. + IMX_INT_INTERRUPT_157 = 157, //!< Reserved. + IMX_INT_INTERRUPT_158 = 158, //!< Reserved. + IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request. + IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts. +}; + + +#endif // __IRQ_NUMBERS_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/mx6ul/plat_startup.h b/bsp/imx6ul/platform/include/mx6ul/plat_startup.h new file mode 100644 index 0000000000000000000000000000000000000000..2c02ec7f580f4ea3ee817c19d8fbb987f8f6b9a5 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/plat_startup.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. +*/ + +/*! + * @file plat_startup.inc + * @brief This file contains start-up DCD. + * + * @ingroup diag_init + */ + /* *INDENT-OFF* */ +#ifndef _PLAT_STARTUP_H_ +#define _PLAT_STARTUP_H_ + +#include "soc_memory_map.h" +#define IMAGE_ENTRY_ADDR 0x80000000 +#define IMAGE_SIZE 4*1024*1024 + +#define L2CC_REG1_CTRL 0x00A02100 +#define L2CC_INV_REG 0x00A0277C +#define L2CC_TAG_RAM_CTRL 0x00A02108 +#define L2CC_DAT_RAM_CTRL 0x00A0210C +#define L2CC_PREFETCH_CTRL 0x00A02F60 + +#define ROM_API_TABLE_BASE_ADDR (0x00000180) +#define ROM_API_HWCNFG_SETUP_OFFSET (0x08) + +#define PLATFORM_INIT plat_dcd_startup + +#define ASM_REG32_WR(i, addr, val) \ + ldr r0, =addr; \ + ldr r1, =val; \ + str r1, [r0]; + +// image starts at 0x00907000 +//flash header & DCD @ 0x400 +.macro plat_dcd_startup + b startup + .org 0x400 +/* First IVT to copy the plugin that initializes the system into OCRAM */ +ivt_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40 +app_code_jump_v: .long 0x00907458 // Plugin entry point, address after the second IVT table +reserv1: .long 0x0 +dcd_ptr: .long 0x0 +boot_data_ptr: .long 0x00907420 +self_ptr: .long 0x00907400 +app_code_csf: .long 0x0 // reserve 4K for csf +reserv2: .long 0x0 +boot_data: .long 0x00907000 +image_len: .long 16*1024 +plugin: .long 0x1 // Enable plugin flag + +/* Second IVT to give entry point into the bootloader copied to DDR */ +ivt2_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40 +app2_code_jump_v: .long startup // Entry point for the bootloader +reserv3: .long 0x0 +dcd2_ptr: .long 0x0 +boot_data2_ptr: .long boot_data2 +self_ptr2: .long ivt2_header +app_code_csf2: .long 0x0 // reserve 4K for csf +reserv4: .long 0x0 +boot_data2: .long IMAGE_ENTRY_ADDR +image_len2: .long IMAGE_SIZE +plugin2: .long 0x0 + +// Here starts the plugin code +plugin_start: +// Save the return address and the function arguments + push {r0-r4, lr} + +#if defined(EVB) || defined(SABRE_LITE) +ASM_REG32_WR(0, 0x020bc000, 0x30) + + +ASM_REG32_WR(0, 0x020c4068, 0xffffffff) +ASM_REG32_WR(0, 0x020c406c, 0xffffffff) +ASM_REG32_WR(0, 0x020c4070, 0xffffffff) +ASM_REG32_WR(0, 0x020c4074, 0xffffffff) +ASM_REG32_WR(0, 0x020c4078, 0xffffffff) +ASM_REG32_WR(0, 0x020c407c, 0xffffffff) +ASM_REG32_WR(0, 0x020c4080, 0xffffffff) +ASM_REG32_WR(0, 0x020c4084, 0xffffffff) + +ASM_REG32_WR(0, 0x020E04B4, 0x000C0000) +ASM_REG32_WR(0, 0x020E04AC, 0x00000000) +ASM_REG32_WR(0, 0x020E027C, 0x00000030) +ASM_REG32_WR(0, 0x020E0250, 0x00000030) +ASM_REG32_WR(0, 0x020E024C, 0x00000030) +ASM_REG32_WR(0, 0x020E0490, 0x00000030) +ASM_REG32_WR(0, 0x020E0288, 0x00000030) +ASM_REG32_WR(0, 0x020E0270, 0x00000000) +ASM_REG32_WR(0, 0x020E0260, 0x00000030) +ASM_REG32_WR(0, 0x020E0264, 0x00000030) +ASM_REG32_WR(0, 0x020E04A0, 0x00000030) +ASM_REG32_WR(0, 0x020E0494, 0x00020000) +ASM_REG32_WR(0, 0x020E0280, 0x00000030) +ASM_REG32_WR(0, 0x020E0284, 0x00000030) +ASM_REG32_WR(0, 0x020E04B0, 0x00020000) +ASM_REG32_WR(0, 0x020E0498, 0x00000030) +ASM_REG32_WR(0, 0x020E04A4, 0x00000030) +ASM_REG32_WR(0, 0x020E0244, 0x00000030) +ASM_REG32_WR(0, 0x020E0248, 0x00000030) +ASM_REG32_WR(0, 0x021B001C, 0x00008000) +ASM_REG32_WR(0, 0x021B0800, 0xA1390003) +ASM_REG32_WR(0, 0x021B080C, 0x001b001E) +ASM_REG32_WR(0, 0x021B083C, 0x42400240) +ASM_REG32_WR(0, 0x021B0848, 0x00003A3E) +ASM_REG32_WR(0, 0x021B0850, 0x00003230) +ASM_REG32_WR(0, 0x021B081C, 0x33333333) +ASM_REG32_WR(0, 0x021B0820, 0x33333333) +ASM_REG32_WR(0, 0x021B082C, 0xf3333333) +ASM_REG32_WR(0, 0x021B0830, 0xf3333333) +ASM_REG32_WR(0, 0x021B08C0, 0x00922012) +ASM_REG32_WR(0, 0x021B08b8, 0x00000800) +ASM_REG32_WR(0, 0x021B0004, 0x0002002D) +ASM_REG32_WR(0, 0x021B0008, 0x1B333000) +ASM_REG32_WR(0, 0x021B000C, 0x676B54B3) +ASM_REG32_WR(0, 0x021B0010, 0xB68E0A83) +ASM_REG32_WR(0, 0x021B0014, 0x01FF00DB) +ASM_REG32_WR(0, 0x021B0018, 0x00211740) +ASM_REG32_WR(0, 0x021B001C, 0x00008000) +ASM_REG32_WR(0, 0x021B002C, 0x000026D2) +ASM_REG32_WR(0, 0x021B0030, 0x006C1023) +ASM_REG32_WR(0, 0x021B0040, 0x0000005F) +ASM_REG32_WR(0, 0x021B0000, 0x85180000) +ASM_REG32_WR(0, 0x021B001C, 0x02008032) +ASM_REG32_WR(0, 0x021B001C, 0x00008033) +ASM_REG32_WR(0, 0x021B001C, 0x00048031) +ASM_REG32_WR(0, 0x021B001C, 0x15208030) +ASM_REG32_WR(0, 0x021B001C, 0x04008040) +ASM_REG32_WR(0, 0x021B0020, 0x00000800) +ASM_REG32_WR(0, 0x021B0818, 0x00000227) +ASM_REG32_WR(0, 0x021B0004, 0x0002552D) +ASM_REG32_WR(0, 0x021B0404, 0x00011006) +ASM_REG32_WR(0, 0x021B001C, 0x00000000) + + +#else + #error "Please add the DDR initialization code for this board, unless you can make sure the existing code can be shared." +#endif + +read_obds: +/******************** + The following is to fill in those arguments for this ROM function + pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) + + This function is used to copy data from the storage media into DDR. + + start - Initial (possibly partial) image load address on entry. Final image load address on exit. + bytes - Initial (possibly partial) image size on entry. Final image size on exit. + boot_data - Initial @ref ivt Boot Data load address. +*/ + + adr r0, DDR_DEST_ADDR + adr r1, COPY_SIZE + adr r2, BOOT_DATA + +/* + * check the _pu_irom_api_table for the address + */ +before_calling_rom___pu_irom_hwcnfg_setup: + //mov r4, #0x2000 + //add r4, r4, #0xed + //blx r4 // This address might change in future ROM versions. + ldr r3, =ROM_API_TABLE_BASE_ADDR /* Address of rom_api_table is 0xc0 */ + ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] /* hwcnfg setup function address is 3rd entry in the api table address 0xc8 */ + blx r4 /* call into ROM function */ +after_calling_rom___pu_irom_hwcnfg_setup: + + /* SDRAM has been setup, binary image has been copied to SDRAM */ + b startup // Jump to our code directly + +DDR_DEST_ADDR: .word IMAGE_ENTRY_ADDR +COPY_SIZE: .word IMAGE_SIZE +BOOT_DATA: .word IMAGE_ENTRY_ADDR + .word IMAGE_SIZE //real data to be copied by the pu_irom_hwcnfg_setup() + .word 0 + +.endm //plat_dcd_startup + +// #define PLATFORM_ASM_STARTUP platform_asm_startup +.macro platform_asm_startup + +config_L2_cache: + disable_L2_cache + +init_aips_start: + init_aips + +init_reloc_start: + /* Check if need to copy image to Redboot ROM space */ + ldr r0, =0xFFFFF000 + and r0, r0, pc + ldr r1, =IMAGE_ENTRY_ADDR + cmp r0, r1 + beq skip_SDRAM_copy + + add r2, r0, #IMAGE_SIZE + +1: ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + ble 1b + /* Jump to SDRAM */ + ldr r1, =0xFFFF + and r0, pc, r1 /* offset of pc */ + ldr r1, =(IMAGE_ENTRY_ADDR + 0x8) + add pc, r0, r1 + nop + nop + nop + nop + +skip_SDRAM_copy: +.endm //platform_asm_startup + +/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS_TZ1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + ldr r0, =AIPS_TZ2_BASE_ADDR + str r1, [r0, #0x00] + str r1, [r0, #0x04] + +.endm /* init_aips */ + +.macro clean_L1_DCache + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 // select DCache + mrc p15, 1, r0, c0, c0, 0 // read CCSIDR + mov r0, r0, ASR #13 + ldr r3, =0x3FFF + and r0, r0, r3 + cmp r0, #0x7F + moveq r6, #0x1000 // 4KB * 4way = 16KB + beq clean_and_invalidate_L1_dcache + cmp r0, #0xFF + moveq r6, #0x2000 // 32KB + beq clean_and_invalidate_L1_dcache + movne r6, #0x4000 // 64KB + +clean_and_invalidate_L1_dcache: + mov r2, #0x00000000 + mov r3, #0x40000000 + mov r4, #0x80000000 + mov r5, #0xC0000000 + +clean_and_invalidate_L1_dcache_byset: + mcr p15, 0, r2, c7, c14, 2 //clean and invalidate dcache on way 0 + mcr p15, 0, r3, c7, c14, 2 //clean and invalidate dcache on way 1 + mcr p15, 0, r4, c7, c14, 2 //clean and invalidate dcache on way 2 + mcr p15, 0, r5, c7, c14, 2 //clean and invalidate dcache on way 3 + add r2, r2, #0x20 + add r3, r3, #0x20 + add r4, r4, #0x20 + add r5, r5, #0x20 + + cmp r2, r6 + bne clean_and_invalidate_L1_dcache_byset + +.endm + +.macro enable_L1_cache + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 // invalidate BTAC + mcr p15, 0, r0, c7, c5, 0 // invalidate icache + + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 // select DCache + mrc p15, 1, r0, c0, c0, 0 // read CCSIDR + mov r0, r0, ASR #13 + ldr r3, =0x3FFF + and r0, r0, r3 + cmp r0, #0x7F + moveq r6, #0x1000 // 4KB * 4way = 16KB + beq invalidate_dcache + cmp r0, #0xFF + moveq r6, #0x2000 // 32KB + beq invalidate_dcache + movne r6, #0x4000 // 64KB + +invalidate_dcache: + mov r2, #0x00000000 + mov r3, #0x40000000 + mov r4, #0x80000000 + mov r5, #0xC0000000 + +invalidate_dcache_byset: + mcr p15, 0, r2, c7, c6, 2 //invalidate dcache on way 0 + mcr p15, 0, r3, c7, c6, 2 //invalidate dcache on way 1 + mcr p15, 0, r4, c7, c6, 2 //invalidate dcache on way 2 + mcr p15, 0, r5, c7, c6, 2 //invalidate dcache on way 3 + add r2, r2, #0x20 + add r3, r3, #0x20 + add r4, r4, #0x20 + add r5, r5, #0x20 + + cmp r2, r6 + bne invalidate_dcache_byset + + ldr r0, =0x00930000 //where to store the TLB page table + mcr p15, 0, r0, c2, c0, 0 + ldr r0, =0x55555555 + mcr p15, 0, r0, c3, c0, 0 + + mrc p15, 0, r0, c1, c0, 0 // read CP15 register 1 into r0 + orr r0, r0, #(0x1<<12) // enable I Cache + orr r0, r0, #(0x1<<11) // turn on BP + orr r0, r0, #(0x1<<2) // enable D Cache + /*Attention: If you want to enable MMU, must set up the TLB tables first!!*/ + bic r0, r0, #(0x1<<0) // disable MMU + mcr p15, 0, r0, c1, c0, 0 // write CP15 register 1 +.endm + +.macro disable_L1_cache + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(0x1<<12) + bic r0, r0, #(0x1<<11) + bic r0, r0, #(0x1<<2) + bic r0, r0, #(0x1<<0) + mcr p15, 0, r0, c1, c0, 0 +.endm + +.macro disable_L1_DCache + mrc p15, 0, r0, c1, c0, 0 + ands r0, r0, #(0x1<<11) //check if L1 DCache has been disabled + beq disable_L1_DCache_done + bic r0, r0, #(0x1<<11) + bic r0, r0, #(0x1<<0) //disable MMU + mcr p15, 0, r0, c1, c0, 0 + clean_L1_DCache +disable_L1_DCache_done: +.endm + +.macro enable_L2_cache + /* set latency: 4x cycles read, 2x cycles write, (3x cycles setup)*/ + ldr r1,= L2CC_TAG_RAM_CTRL + ldr r0,=0x0132 + str r0,[r1] + ldr r1, =L2CC_DAT_RAM_CTRL + ldr r0,=0x0132 + str r0,[r1] + + /* invalidate L2Cache by way */ + ldr r1, =L2CC_INV_REG + ldr r0, =0xffff + str r0,[r1] +l2cc_inv_done: + ldr r2,[r1] + mov r0,#0x0 + cmp r2,r0 + bne l2cc_inv_done + + /* turn on l2 cache */ + ldr r1, =L2CC_REG1_CTRL + mov r0,#1 + str r0,[r1] +.endm + +.macro disable_L2_cache + ldr r1, =L2CC_REG1_CTRL + mov r0,#0 + str r0,[r1] +.endm + +#endif //_PLAT_STARTUP_H_ diff --git a/bsp/imx6ul/platform/include/mx6ul/registers.h b/bsp/imx6ul/platform/include/mx6ul/registers.h new file mode 100644 index 0000000000000000000000000000000000000000..0fcaecf15cc9e685fa009c78e545cd481a44fb2b --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers.h @@ -0,0 +1,3989 @@ +/* + * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. +*/ + +//################################################# +//# +//# Description: +//# This file lists instances offset memory location +//# +//################################################# + +//######################################### +//# ARM PLATFORM INTERNALS - SCU REGISTERS +//######################################### +#define SCU_CONTROL SCU_BASE_ADDR // SCU Control Register +#define SCU_CONFIG SCU_BASE_ADDR+0x04 // SCU Control Register +#define SCU_CPU_PWR_STAT SCU_BASE_ADDR+0x08 // SCU Control Register +#define SCU_INVAL_SECURE SCU_BASE_ADDR+0x0C // SCU Control Register +#define SCU_FILTERSTART SCU_BASE_ADDR+0x40 // Filtering Start Address Register +#define SCU_FILTEREND SCU_BASE_ADDR+0x44 // Filtering End Address Register + +//######################################### +//# BOOT ROM +//######################################### +#define BOOTROM1_ADDR_BOT_OFFSET 0x00000000 // boot rom section 1 bottom address +//######################################### +//# WDOG +//######################################### +#define WDOG_WCR_OFFSET 0x00 // 16bit watchdog control reg +#define WDOG_WSR_OFFSET 0x02 // 16bit watchdog service reg +#define WDOG_WRSR_OFFSET 0x04 // 16bit watchdog reset status reg +#define WDOG_WICR_OFFSET 0x06 // Watchdog Interrupt Control Register +//######################################### +//# GPT +//######################################### +#define GPT_GPTCR_OFFSET 0x00 // 32bit timer 1 control reg +#define GPT_GPTPR_OFFSET 0x04 // 32bit timer 1 prescaler reg +#define GPT_GPTSR_OFFSET 0x08 // 32bit timer 1 compare reg +#define GPT_GPTIR_OFFSET 0x0C // 32bit timer 1 capture reg +#define GPT_GPTOCR1_OFFSET 0x10 // 32bit timer 1 counter reg +#define GPT_GPTOCR2_OFFSET 0x14 // 32bit timer 1 status reg +#define GPT_GPTOCR3_OFFSET 0x18 // 32 bit read & write +#define GPT_GPTICR1_OFFSET 0x1C // 32 bit read +#define GPT_GPTICR2_OFFSET 0x20 // 32 bit read +#define GPT_GPTCNT_OFFSET 0x24 // 32 bit read +//######################################### +//# EPIT +//######################################### +#define EPIT_EPITCR_OFFSET 0x00 // 32bit timer 3 control reg +#define EPIT_EPITSR_OFFSET 0x04 // 32bit timer 3 prescaler reg +#define EPIT_EPITLR_OFFSET 0x08 // 32bit timer 3 compare reg +#define EPIT_EPITCMPR_OFFSET 0x0C // 32bit timer 3 capture reg +#define EPIT_EPITCNR_OFFSET 0x10 // 32bit timer 3 counter reg +//######################################### +//# PWM +//######################################### +#define PWM_PWMCR_OFFSET 0x00 // 32bit pwm control reg +#define PWM_PWMSR_OFFSET 0x04 // 32bit pwm sample reg +#define PWM_PWMIR_OFFSET 0x08 // 32bit pwm period reg +#define PWM_PWMSAR_OFFSET 0x0C // 32bit pwm counter reg +#define PWM_PWMPR_OFFSET 0x10 // 32bit pwm test reg +#define PWM_PWMCNR_OFFSET 0x14 +//######################################### +//# KPP +//######################################### +#define KPP_KPCR_OFFSET 0x00 // 16bit kpp keypad control reg +#define KPP_KPSR_OFFSET 0x02 // 16bit kpp keypad status reg +#define KPP_KDDR_OFFSET 0x04 // 16bit kpp keypad data directon reg +#define KPP_KPDR_OFFSET 0x06 // 16bit kpp keypad data reg +//######################################### +//# I2C +//######################################### +#define I2C_IADR_OFFSET 0x00 // 16bit i2c address reg +#define I2C_IFDR_OFFSET 0x04 // 16bit i2c frequency divider reg +#define I2C_I2CR_OFFSET 0x08 // 16bit i2c control reg +#define I2C_I2SR_OFFSET 0x0C // 16bit i2c status reg +#define I2C_I2DR_OFFSET 0x10 // 16bit i2c data i/o reg +//######################################### +//# GPIO +//######################################### +#define GPIO_DR0_OFFSET 0x00 // 32bit gpio pta data direction reg +#define GPIO_GDIR0_OFFSET 0x04 // 32bit gpio pta output config 1 reg +#define GPIO_PSR0_OFFSET 0x08 // 32bit gpio pta output config 2 reg +#define GPIO_ICR1_OFFSET 0x0C // 32bit gpio pta input config A1 reg +#define GPIO_ICR2_OFFSET 0x10 // 32bit gpio pta input config A2 reg +#define GPIO_IMR_OFFSET 0x14 // 32bit gpio pta input config B1 reg +#define GPIO_ISR_OFFSET 0x18 // GPIO Interrupt Status Register +#define GPIO_EDGE_SEL_OFFSET 0x1C // GPIO Edge Detect Register + +#define GPIO1_DR GPIO1_IPS_BASE_ADDR+0x00 +#define GPIO1_GDIR GPIO1_IPS_BASE_ADDR+0x04 +#define GPIO1_PSR GPIO1_IPS_BASE_ADDR+0x08 +#define GPIO1_ICR1 GPIO1_IPS_BASE_ADDR+0x0C +#define GPIO1_ICR2 GPIO1_IPS_BASE_ADDR+0x10 +#define GPIO1_IMR GPIO1_IPS_BASE_ADDR+0x14 +#define GPIO1_ISR GPIO1_IPS_BASE_ADDR+0x18 +#define GPIO1_EDGE_SEL GPIO1_IPS_BASE_ADDR+0x1C + +#define GPIO2_DR GPIO2_IPS_BASE_ADDR+0x00 +#define GPIO2_GDIR GPIO2_IPS_BASE_ADDR+0x04 +#define GPIO2_PSR GPIO2_IPS_BASE_ADDR+0x08 +#define GPIO2_ICR1 GPIO2_IPS_BASE_ADDR+0x0C +#define GPIO2_ICR2 GPIO2_IPS_BASE_ADDR+0x10 +#define GPIO2_IMR GPIO2_IPS_BASE_ADDR+0x14 +#define GPIO2_ISR GPIO2_IPS_BASE_ADDR+0x18 +#define GPIO2_EDGE_SEL GPIO2_IPS_BASE_ADDR+0x1C + +#define GPIO3_DR GPIO3_IPS_BASE_ADDR+0x00 +#define GPIO3_GDIR GPIO3_IPS_BASE_ADDR+0x04 +#define GPIO3_PSR GPIO3_IPS_BASE_ADDR+0x08 +#define GPIO3_ICR1 GPIO3_IPS_BASE_ADDR+0x0C +#define GPIO3_ICR2 GPIO3_IPS_BASE_ADDR+0x10 +#define GPIO3_IMR GPIO3_IPS_BASE_ADDR+0x14 +#define GPIO3_ISR GPIO3_IPS_BASE_ADDR+0x18 +#define GPIO3_EDGE_SEL GPIO3_IPS_BASE_ADDR+0x1C + +#define GPIO4_DR GPIO4_IPS_BASE_ADDR+0x00 +#define GPIO4_GDIR GPIO4_IPS_BASE_ADDR+0x04 +#define GPIO4_PSR GPIO4_IPS_BASE_ADDR+0x08 +#define GPIO4_ICR1 GPIO4_IPS_BASE_ADDR+0x0C +#define GPIO4_ICR2 GPIO4_IPS_BASE_ADDR+0x10 +#define GPIO4_IMR GPIO4_IPS_BASE_ADDR+0x14 +#define GPIO4_ISR GPIO4_IPS_BASE_ADDR+0x18 +#define GPIO4_EDGE_SEL GPIO4_IPS_BASE_ADDR+0x1C + +#define GPIO5_DR GPIO5_IPS_BASE_ADDR+0x00 +#define GPIO5_GDIR GPIO5_IPS_BASE_ADDR+0x04 +#define GPIO5_PSR GPIO5_IPS_BASE_ADDR+0x08 +#define GPIO5_ICR1 GPIO5_IPS_BASE_ADDR+0x0C +#define GPIO5_ICR2 GPIO5_IPS_BASE_ADDR+0x10 +#define GPIO5_IMR GPIO5_IPS_BASE_ADDR+0x14 +#define GPIO5_ISR GPIO5_IPS_BASE_ADDR+0x18 +#define GPIO5_EDGE_SEL GPIO5_IPS_BASE_ADDR+0x1C + +#define GPIO6_DR GPIO6_IPS_BASE_ADDR+0x00 +#define GPIO6_GDIR GPIO6_IPS_BASE_ADDR+0x04 +#define GPIO6_PSR GPIO6_IPS_BASE_ADDR+0x08 +#define GPIO6_ICR1 GPIO6_IPS_BASE_ADDR+0x0C +#define GPIO6_ICR2 GPIO6_IPS_BASE_ADDR+0x10 +#define GPIO6_IMR GPIO6_IPS_BASE_ADDR+0x14 +#define GPIO6_ISR GPIO6_IPS_BASE_ADDR+0x18 +#define GPIO6_EDGE_SEL GPIO6_IPS_BASE_ADDR+0x1C + +#define GPIO7_DR GPIO7_IPS_BASE_ADDR+0x00 +#define GPIO7_GDIR GPIO7_IPS_BASE_ADDR+0x04 +#define GPIO7_PSR GPIO7_IPS_BASE_ADDR+0x08 +#define GPIO7_ICR1 GPIO7_IPS_BASE_ADDR+0x0C +#define GPIO7_ICR2 GPIO7_IPS_BASE_ADDR+0x10 +#define GPIO7_IMR GPIO7_IPS_BASE_ADDR+0x14 +#define GPIO7_ISR GPIO7_IPS_BASE_ADDR+0x18 +#define GPIO7_EDGE_SEL GPIO7_IPS_BASE_ADDR+0x1C + +//######################################### +//# ESAI +//######################################### +#define ESAI_ETDR_OFFSET 0x00 +#define ESAI_ERDR_OFFSET 0x04 +#define ESAI_ECR_OFFSET 0x08 +#define ESAI_ESR_OFFSET 0x0c +#define ESAI_TFCR_OFFSET 0x10 +#define ESAI_TFSR_OFFSET 0x14 +#define ESAI_RFCR_OFFSET 0x18 +#define ESAI_RFSR_OFFSET 0x1c +#define ESAI_TX0_OFFSET 0x80 +#define ESAI_TX1_OFFSET 0x84 +#define ESAI_TX2_OFFSET 0x88 +#define ESAI_TX3_OFFSET 0x8c +#define ESAI_TX4_OFFSET 0x90 +#define ESAI_TX5_OFFSET 0x94 +#define ESAI_TSR_OFFSET 0x98 +#define ESAI_RX0_OFFSET 0xA0 +#define ESAI_RX1_OFFSET 0xA4 +#define ESAI_RX2_OFFSET 0xA8 +#define ESAI_RX3_OFFSET 0xAC +#define ESAI_SAISR_OFFSET 0xCC +#define ESAI_SAICR_OFFSET 0xD0 +#define ESAI_TCR_OFFSET 0xD4 +#define ESAI_TCCR_OFFSET 0xD8 +#define ESAI_RCR_OFFSET 0xDC +#define ESAI_RCCR_OFFSET 0xE0 +#define ESAI_TSMA_OFFSET 0xE4 +#define ESAI_TSMB_OFFSET 0xE8 +#define ESAI_RSMA_OFFSET 0xEC +#define ESAI_RSMB_OFFSET 0xF0 +#define ESAI_PDRC_OFFSET 0xF4 +#define ESAI_PRRC_OFFSET 0xF8 +#define ESAI_PCRC_OFFSET 0xFC + +//######################################### +//# ECSPI +//######################################### +#define ECSPI_RXDATA_OFFSET 0x00 // 32bit CSPI receive data reg +#define ECSPI_TXDATA_OFFSET 0x04 // 32bit CSPI transmit data reg +#define ECSPI_CONREG_OFFSET 0x08 // 32bit CSPI control reg +#define ECSPI_CONFIG_OFFSET 0x0C +#define ECSPI_INTREG_OFFSET 0x10 // 32bit CSPI interrupt stat/ctr reg +#define ECSPI_DMAREG_OFFSET 0x14 // 32bit CSPI test reg +#define ECSPI_STATREG_OFFSET 0x18 // 32bit CSPI sample period ctrl reg +#define ECSPI_PERIODREG_OFFSET 0x1C // 32bit CSPI dma ctrl reg +#define ECSPI_TESTREG_OFFSET 0x20 // 32bit CSPI soft reset reg +#define ECSPI_MSG0REG_OFFSET 0x24 +#define ECSPI_MSG1REG_OFFSET 0x28 +#define ECSPI_MSG2REG_OFFSET 0x2c +#define ECSPI_MSG3REG_OFFSET 0x30 +#define ECSPI_MSG4REG_OFFSET 0x34 +#define ECSPI_MSG5REG_OFFSET 0x38 +#define ECSPI_MSG6REG_OFFSET 0x3c +#define ECSPI_MSG7REG_OFFSET 0x40 +#define ECSPI_MSG8REG_OFFSET 0x44 +#define ECSPI_MSG9REG_OFFSET 0x48 +#define ECSPI_MSG10REG_OFFSET 0x4c +#define ECSPI_MSG11REG_OFFSET 0x50 +#define ECSPI_MSG12REG_OFFSET 0x54 +#define ECSPI_MSG13REG_OFFSET 0x58 +#define ECSPI_MSG14REG_OFFSET 0x5c +#define ECSPI_MSG15REG_OFFSET 0x60 +//######################################### +//# PERFMON 1/2/3 +//######################################### +#define HW_PERFMON_CTRL_OFFSET 0x00 +#define HW_PERFMON_CTRL_SET_OFFSET 0x04 +#define HW_PERFMON_CTRL_CLR_OFFSET 0x08 +#define HW_PERFMON_CTRL_TOG_OFFSET 0x0C +#define HW_PERFMON_MASTER_ON_OFFSET 0x10 +#define HW_PERFMON_TRAP_ADDR_LOW_OFFSET 0x20 +#define HW_PERFMON_TRAP_ADDR_HIGH_OFFSET 0x30 +#define HW_PERFMON_LAT_THRESHOLD 0x40 +#define HW_PERFMON_ACTIVE_CYCLE_OFFSET 0x50 +#define HW_PERFMON_TRANSFER_COUNT_OFFSET 0x60 +#define HW_PERFMON_TOTAL_LATENCY_OFFSET 0x70 +#define HW_PERFMON_DATA_COUNT_OFFSET 0x80 +#define HW_PERFMON_MAX_LATENCY_OFFSET 0x90 +#define HW_PERFMON_DEBUG_OFFSET 0xA0 +#define HW_PERFMON_VERSION_OFFSET 0xB0 + +//######################################### +//# uSDHC +//######################################### +#define USDHC_DSADDR_OFFSET 0x00 // 32bit SDHC control reg +#define USDHC_BLKATTR_OFFSET 0x04 // 32bit SDHC status reg +#define USDHC_CMDARG_OFFSET 0x08 // 32bit SDHC clock rate reg +#define USDHC_XFERTYP_OFFSET 0x0C // 32bit SDHC cmd/data control reg +#define USDHC_CMDRSP0_OFFSET 0x10 // 32bit SDHC response time out reg +#define USDHC_CMDRSP1_OFFSET 0x14 // 32bit SDHC read time out reg +#define USDHC_CMDRSP2_OFFSET 0x18 // 32bit SDHC block length reg +#define USDHC_CMDRSP3_OFFSET 0x1C // 32bit SDHC number of blocks reg +#define USDHC_DATPORT_OFFSET 0x20 // 32bit SDHC revision number reg +#define USDHC_PRSSTATE_OFFSET 0x24 // 32bit SDHC interrupt mask reg +#define USDHC_PROCTL_OFFSET 0x28 // 32bit SDHC command code reg +#define USDHC_SYSCTRL_OFFSET 0x2C // 32bit SDHC argument (high+low) reg +#define USDHC_IRQSTAT_OFFSET 0x30 // 32bit SDHC response fifo reg +#define USDHC_IRQSTATEN_OFFSET 0x34 // 32bit SDHC buffer access reg +#define USDHC_IRQSIGEN_OFFSET 0x38 // 32bit SDHC remaining NUM reg +#define USDHC_AUTOC12ERR_OFFSET 0x3C // 32bit SDHC remaining block bytes reg +#define USDHC_HOSTCAPBLT_OFFSET 0x40 +#define USDHC_WML_OFFSET 0x44 +#define USDHC_FEVTR_OFFSET 0x50 +#define USDHC_HOSTVER_OFFSET 0xfc + +//######################################### +//# SSI +//######################################### +#define SSI_STX0_OFFSET 0x00 // 32bit SSI tx reg 0 +#define SSI_STX1_OFFSET 0x04 // 32bit SSI tx reg 1 +#define SSI_SRX0_OFFSET 0x08 // 32bit SSI rx reg 0 +#define SSI_SRX1_OFFSET 0x0C // 32bit SSI rx reg 1 +#define SSI_SCR_OFFSET 0x10 // 32bit SSI control reg +#define SSI_SISR_OFFSET 0x14 // 32bit SSI intr status reg +#define SSI_SIER_OFFSET 0x18 // 32bit SSI intr enable reg +#define SSI_STCR_OFFSET 0x1C // 32bit SSI tx config reg +#define SSI_SRCR_OFFSET 0x20 // 32bit SSI rx config reg +#define SSI_STCCR_OFFSET 0x24 // 32bit SSI tx clock control reg +#define SSI_SRCCR_OFFSET 0x28 // 32bit SSI rx clock control reg +#define SSI_SFCSR_OFFSET 0x2C // 32bit SSI fifo control/status reg +#define SSI_STR_OFFSET 0x30 // 32bit SSI test reg +#define SSI_SOR_OFFSET 0x34 // 32bit SSI option reg +#define SSI_SACNT_OFFSET 0x38 // 32bit SSI ac97 control reg +#define SSI_SACADD_OFFSET 0x3C // 32bit SSI ac97 cmd addr reg +#define SSI_SACDAT_OFFSET 0x40 // 32bit SSI ac97 cmd data reg +#define SSI_SATAG_OFFSET 0x44 // 32bit SSI ac97 tag reg +#define SSI_STMSK_OFFSET 0x48 // 32bit SSI tx time slot mask reg +#define SSI_SRMSK_OFFSET 0x4C // 32bit SSI rx time slot mask reg +#define SSI_SACCST_OFFSET 0x50 +#define SSI_SACCEN_OFFSET 0x54 +#define SSI_SACCDIS_OFFSET 0x58 +//######################################### +//# UART +//######################################### +#define UART_URXD_OFFSET 0x00 // 32bit UART receiver reg +#define UART_UTXD_OFFSET 0x40 // 32bit UART transmitter reg +#define UART_UCR1_OFFSET 0x80 // 32bit UART control 1 reg +#define UART_UCR2_OFFSET 0x84 // 32bit UART control 2 reg +#define UART_UCR3_OFFSET 0x88 // 32bit UART control 3 reg +#define UART_UCR4_OFFSET 0x8C // 32bit UART control 4 reg +#define UART_UFCR_OFFSET 0x90 // 32bit UART fifo control reg +#define UART_USR1_OFFSET 0x94 // 32bit UART status 1 reg +#define UART_USR2_OFFSET 0x98 // 32bit UART status 2 reg +#define UART_UESC_OFFSET 0x9C // 32bit UART escape char reg +#define UART_UTIM_OFFSET 0xA0 // 32bit UART escape timer reg +#define UART_UBIR_OFFSET 0xA4 // 32bit UART BRM incremental reg +#define UART_UBMR_OFFSET 0xA8 // 32bit UART BRM modulator reg +#define UART_UBRC_OFFSET 0xAC // 32bit UART baud rate count reg +#define UART_ONEMS_OFFSET 0xB0 // 32bit UART one ms reg +#define UART_UTS_OFFSET 0xB4 // 32bit UART test reg +//######################################### +//# AUDMUX +//######################################### +#define AUDMUX_PTCR1_OFFSET 0x00 // Port Timing Control Register 1 +#define AUDMUX_PDCR1_OFFSET 0x04 // Port Data Control Register 1 +#define AUDMUX_PTCR2_OFFSET 0x08 // Port Timing Control Register 2 +#define AUDMUX_PDCR2_OFFSET 0x0C // Port Data Control Register 2 +#define AUDMUX_PTCR3_OFFSET 0x10 // Port Timing Control Register 3 +#define AUDMUX_PDCR3_OFFSET 0x14 // Port Data Control Register 3 +#define AUDMUX_PTCR4_OFFSET 0x18 // Port Timing Control Register 4 +#define AUDMUX_PDCR4_OFFSET 0x1C // Port Data Control Register 4 +#define AUDMUX_PTCR5_OFFSET 0x20 // Port Timing Control Register 5 +#define AUDMUX_PDCR5_OFFSET 0x24 // Port Data Control Register 5 +#define AUDMUX_PTCR6_OFFSET 0x28 // Port Timing Control Register 6 +#define AUDMUX_PDCR6_OFFSET 0x2C // Port Data Control Register 6 +#define AUDMUX_PTCR7_OFFSET 0x30 // Port Timing Control Register 7 +#define AUDMUX_PDCR7_OFFSET 0x34 // Port Data Control Register 7 +#define AUDMUX_CNMCR_OFFSET 0x38 // CE Bus Network Mode Control Register +//######################################### +//# SPBA +//######################################### +#define SPBA_PER0_START_ADDR_OFFSET 0x00 // 32bit gpio pta data direction reg +#define SPBA_PER1_START_ADDR_OFFSET 0x4000 // 32bit gpio pta output config 1 reg +#define SPBA_PER2_START_ADDR_OFFSET 0x8000 // 32bit gpio pta output config 2 reg +#define SPBA_PER3_START_ADDR_OFFSET 0xC000 +#define SPBA_PER4_START_ADDR_OFFSET 0x10000 +#define SPBA_PER5_START_ADDR_OFFSET 0x14000 +#define SPBA_PER6_START_ADDR_OFFSET 0x18000 +#define SPBA_PER7_START_ADDR_OFFSET 0x1C000 +#define SPBA_PER8_START_ADDR_OFFSET 0x20000 +#define SPBA_PER9_START_ADDR_OFFSET 0x24000 +#define SPBA_PER10_START_ADDR_OFFSET 0x28000 +#define SPBA_PER11_START_ADDR_OFFSET 0x2C000 +#define SPBA_PER12_START_ADDR_OFFSET 0x30000 +#define SPBA_PER13_START_ADDR_OFFSET 0x34000 +#define SPBA_PER14_START_ADDR_OFFSET 0x38000 +#define SPBA_REG_ADDR_OFFSET 0x3C000 +#define SPBA_PRR0_OFFSET 0x00 +#define SPBA_PRR1_OFFSET 0x04 +#define SPBA_PRR2_OFFSET 0x08 +#define SPBA_PRR3_OFFSET 0x0C +#define SPBA_PRR4_OFFSET 0x10 +#define SPBA_PRR5_OFFSET 0x14 +#define SPBA_PRR6_OFFSET 0x18 +#define SPBA_PRR7_OFFSET 0x1C +#define SPBA_PRR8_OFFSET 0x20 +#define SPBA_PRR9_OFFSET 0x24 +#define SPBA_PRR10_OFFSET 0x28 +#define SPBA_PRR11_OFFSET 0x2C +#define SPBA_PRR12_OFFSET 0x30 +#define SPBA_PRR13_OFFSET 0x34 +#define SPBA_PRR14_OFFSET 0x38 + +//######################################### +//# DCIC +//######################################### +#define DCICC_REG_OFFSET 0x0 //DCICC +#define DCICIC_REG_OFFSET 0x4 //DCICIC +#define DCICS_REG_OFFSET 0x8 //DCICS +#define DCI_RES_C_REG_OFFSET 0xc //RESERVED +#define DCICRC0_REG_OFFSET 0x10 //DCICRCm +#define DCICRS0_REG_OFFSET 0x14 //DCICRSm +#define DCICRRS0_REG_OFFSET 0x18 //DCICRRSm +#define DCICRCS0_REG_OFFSET 0x1c //DCICRCSm +#define DCICRC1_REG_OFFSET 0x20 //DCICRCm +#define DCICRS1_REG_OFFSET 0x24 //DCICRSm +#define DCICRRS1_REG_OFFSET 0x28 //DCICRRSm +#define DCICRCS1_REG_OFFSET 0x2c //DCICRCSm +#define DCICRC2_REG_OFFSET 0x30 //DCICRCm +#define DCICRS2_REG_OFFSET 0x34 //DCICRSm +#define DCICRRS2_REG_OFFSET 0x38 //DCICRRSm +#define DCICRCS2_REG_OFFSET 0x3c //DCICRCSm +#define DCICRC3_REG_OFFSET 0x40 //DCICRCm +#define DCICRS3_REG_OFFSET 0x44 //DCICRSm +#define DCICRRS3_REG_OFFSET 0x48 //DCICRRSm +#define DCICRCS3_REG_OFFSET 0x4c //DCICRCSm +#define DCICRC4_REG_OFFSET 0x50 //DCICRCm +#define DCICRS4_REG_OFFSET 0x54 //DCICRSm +#define DCICRRS4_REG_OFFSET 0x58 //DCICRRSm +#define DCICRCS4_REG_OFFSET 0x5c //DCICRCSm +#define DCICRC5_REG_OFFSET 0x60 //DCICRCm +#define DCICRS5_REG_OFFSET 0x64 //DCICRSm +#define DCICRRS5_REG_OFFSET 0x68 //DCICRRSm +#define DCICRCS5_REG_OFFSET 0x6c //DCICRCSm +#define DCICRC6_REG_OFFSET 0x70 //DCICRCm +#define DCICRS6_REG_OFFSET 0x74 //DCICRSm +#define DCICRRS6_REG_OFFSET 0x78 //DCICRRSm +#define DCICRCS6_REG_OFFSET 0x7c //DCICRCSm +#define DCICRC7_REG_OFFSET 0x80 //DCICRCm +#define DCICRS7_REG_OFFSET 0x84 //DCICRSm +#define DCICRRS7_REG_OFFSET 0x88 //DCICRRSm +#define DCICRCS7_REG_OFFSET 0x8c //DCICRCSm +#define DCICRC8_REG_OFFSET 0x90 //DCICRCm +#define DCICRS8_REG_OFFSET 0x94 //DCICRSm +#define DCICRRS8_REG_OFFSET 0x98 //DCICRRSm +#define DCICRCS8_REG_OFFSET 0x9c //DCICRCSm +#define DCICRC9_REG_OFFSET 0xa0 //DCICRCm +#define DCICRS9_REG_OFFSET 0xa4 //DCICRSm +#define DCICRRS9_REG_OFFSET 0xa8 //DCICRRSm +#define DCICRCS9_REG_OFFSET 0xac //DCICRCSm +#define DCICRC10_REG_OFFSET 0xb0 //DCICRCm +#define DCICRS10_REG_OFFSET 0xb4 //DCICRSm +#define DCICRRS10_REG_OFFSET 0xb8 //DCICRRSm +#define DCICRCS10_REG_OFFSET 0xbc //DCICRCSm +#define DCICRC11_REG_OFFSET 0xc0 //DCICRCm +#define DCICRS11_REG_OFFSET 0xc4 //DCICRSm +#define DCICRRS11_REG_OFFSET 0xc8 //DCICRRSm +#define DCICRCS11_REG_OFFSET 0xcc //DCICRCSm +#define DCICRC12_REG_OFFSET 0xd0 //DCICRCm +#define DCICRS12_REG_OFFSET 0xd4 //DCICRSm +#define DCICRRS12_REG_OFFSET 0xd8 //DCICRRSm +#define DCICRCS12_REG_OFFSET 0xdc //DCICRCSm +#define DCICRC13_REG_OFFSET 0xe0 //DCICRCm +#define DCICRS13_REG_OFFSET 0xe4 //DCICRSm +#define DCICRRS13_REG_OFFSET 0xe8 //DCICRRSm +#define DCICRCS13_REG_OFFSET 0xec //DCICRCSm +#define DCICRC14_REG_OFFSET 0xf0 //DCICRCm +#define DCICRS14_REG_OFFSET 0xf4 //DCICRSm +#define DCICRRS14_REG_OFFSET 0xf8 //DCICRRSm +#define DCICRCS14_REG_OFFSET 0xfc //DCICRCSm +#define DCICRC15_REG_OFFSET 0x100 //DCICRCm +#define DCICRS15_REG_OFFSET 0x104 //DCICRSm +#define DCICRRS15_REG_OFFSET 0x108 //DCICRRSm +#define DCICRCS15_REG_OFFSET 0x10c //DCICRCSm + +//######################################### +//# IPU +//######################################### +#define IPU_REGISTERS_OFFSET 0x00200000 +#define IPU_MEMORY_OFFSET IPU_REGISTERS_OFFSET + 0x00100000 +#define IPU_IPU_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x00000000 +#define IPU_SISG_CTRL0_OFFSET IPU_REGISTERS_OFFSET + 0x00000004 +#define IPU_SISG_CTRL1_OFFSET IPU_REGISTERS_OFFSET + 0x00000008 +#define IPU_SISG_SET_1_OFFSET IPU_REGISTERS_OFFSET + 0x0000000C +#define IPU_SISG_SET_2_OFFSET IPU_REGISTERS_OFFSET + 0x00000010 +#define IPU_SISG_SET_3_OFFSET IPU_REGISTERS_OFFSET + 0x00000014 +#define IPU_SISG_SET_4_OFFSET IPU_REGISTERS_OFFSET + 0x00000018 +#define IPU_SISG_SET_5_OFFSET IPU_REGISTERS_OFFSET + 0x0000001C +#define IPU_SISG_SET_6_OFFSET IPU_REGISTERS_OFFSET + 0x00000020 +#define IPU_SISG_CLR_1_OFFSET IPU_REGISTERS_OFFSET + 0x00000024 +#define IPU_SISG_CLR_2_OFFSET IPU_REGISTERS_OFFSET + 0x00000028 +#define IPU_SISG_CLR_3_OFFSET IPU_REGISTERS_OFFSET + 0x0000002C +#define IPU_SISG_CLR_4_OFFSET IPU_REGISTERS_OFFSET + 0x00000030 +#define IPU_SISG_CLR_5_OFFSET IPU_REGISTERS_OFFSET + 0x00000034 +#define IPU_SISG_CLR_6_OFFSET IPU_REGISTERS_OFFSET + 0x00000038 +#define IPU_IPU_INT_CTRL_1_OFFSET IPU_REGISTERS_OFFSET + 0x0000003C +#define IPU_IPU_INT_CTRL_2_OFFSET IPU_REGISTERS_OFFSET + 0x00000040 +#define IPU_IPU_INT_CTRL_3_OFFSET IPU_REGISTERS_OFFSET + 0x00000044 +#define IPU_IPU_INT_CTRL_4_OFFSET IPU_REGISTERS_OFFSET + 0x00000048 +#define IPU_IPU_INT_CTRL_5_OFFSET IPU_REGISTERS_OFFSET + 0x0000004C +#define IPU_IPU_INT_CTRL_6_OFFSET IPU_REGISTERS_OFFSET + 0x00000050 +#define IPU_IPU_INT_CTRL_7_OFFSET IPU_REGISTERS_OFFSET + 0x00000054 +#define IPU_IPU_INT_CTRL_8_OFFSET IPU_REGISTERS_OFFSET + 0x00000058 +#define IPU_IPU_INT_CTRL_9_OFFSET IPU_REGISTERS_OFFSET + 0x0000005C +#define IPU_IPU_INT_CTRL_10_OFFSET IPU_REGISTERS_OFFSET + 0x00000060 +#define IPU_IPU_INT_CTRL_11_OFFSET IPU_REGISTERS_OFFSET + 0x00000064 +#define IPU_IPU_INT_CTRL_12_OFFSET IPU_REGISTERS_OFFSET + 0x00000068 +#define IPU_IPU_INT_CTRL_13_OFFSET IPU_REGISTERS_OFFSET + 0x0000006C +#define IPU_IPU_INT_CTRL_14_OFFSET IPU_REGISTERS_OFFSET + 0x00000070 +#define IPU_IPU_INT_CTRL_15_OFFSET IPU_REGISTERS_OFFSET + 0x00000074 +#define IPU_IPU_SDMA_EVENT_1_OFFSET IPU_REGISTERS_OFFSET + 0x00000078 +#define IPU_IPU_SDMA_EVENT_2_OFFSET IPU_REGISTERS_OFFSET + 0x0000007C +#define IPU_IPU_SDMA_EVENT_3_OFFSET IPU_REGISTERS_OFFSET + 0x00000080 +#define IPU_IPU_SDMA_EVENT_4_OFFSET IPU_REGISTERS_OFFSET + 0x00000084 +#define IPU_IPU_SDMA_EVENT_5_OFFSET IPU_REGISTERS_OFFSET + 0x00000088 +#define IPU_IPU_SDMA_EVENT_6_OFFSET IPU_REGISTERS_OFFSET + 0x0000008C +#define IPU_IPU_SDMA_EVENT_7_OFFSET IPU_REGISTERS_OFFSET + 0x00000090 +#define IPU_IPU_SDMA_EVENT_8_OFFSET IPU_REGISTERS_OFFSET + 0x00000094 +#define IPU_IPU_SDMA_EVENT_9_OFFSET IPU_REGISTERS_OFFSET + 0x00000098 +#define IPU_IPU_SDMA_EVENT_10_OFFSET IPU_REGISTERS_OFFSET + 0x0000009C +#define IPU_IPU_SRM_PRI1_OFFSET IPU_REGISTERS_OFFSET + 0x000000A0 +#define IPU_IPU_SRM_PRI2_OFFSET IPU_REGISTERS_OFFSET + 0x000000A4 +#define IPU_IPU_FS_PROC_FLOW1_OFFSET IPU_REGISTERS_OFFSET + 0x000000A8 +#define IPU_IPU_FS_PROC_FLOW2_OFFSET IPU_REGISTERS_OFFSET + 0x000000AC +#define IPU_IPU_FS_PROC_FLOW3_OFFSET IPU_REGISTERS_OFFSET + 0x000000B0 +#define IPU_IPU_FS_DISP_FLOW1_OFFSET IPU_REGISTERS_OFFSET + 0x000000B4 +#define IPU_IPU_FS_DISP_FLOW2_OFFSET IPU_REGISTERS_OFFSET + 0x000000B8 +#define IPU_IPU_SKIP_OFFSET IPU_REGISTERS_OFFSET + 0x000000BC +#define IPU_IPU_DISP_ALT_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x000000C0 +#define IPU_DP_CUR_POS_ALT_OFFSET IPU_REGISTERS_OFFSET + 0x000000C4 +#define IPU_IPU_DISP_GEN_OFFSET IPU_REGISTERS_OFFSET + 0x000000C8 +#define IPU_IPU_DISP_ALT1_OFFSET IPU_REGISTERS_OFFSET + 0x000000CC +#define IPU_IPU_DISP_ALT2_OFFSET IPU_REGISTERS_OFFSET + 0x000000D0 +#define IPU_IPU_DISP_ALT3_OFFSET IPU_REGISTERS_OFFSET + 0x000000D4 +#define IPU_IPU_DISP_ALT4_OFFSET IPU_REGISTERS_OFFSET + 0x000000D8 +#define IPU_IPU_SNOOP_OFFSET IPU_REGISTERS_OFFSET + 0x000000DC +#define IPU_IPU_MEM_RST_OFFSET IPU_REGISTERS_OFFSET + 0x000000E0 +#define IPU_IPU_PM_OFFSET IPU_REGISTERS_OFFSET + 0x000000E4 +#define IPU_IPU_INT_STAT_1_OFFSET IPU_REGISTERS_OFFSET + 0x000000E8 +#define IPU_IPU_INT_STAT_2_OFFSET IPU_REGISTERS_OFFSET + 0x000000EC +#define IPU_IPU_INT_STAT_3_OFFSET IPU_REGISTERS_OFFSET + 0x000000F0 +#define IPU_IPU_INT_STAT_4_OFFSET IPU_REGISTERS_OFFSET + 0x000000F4 +#define IPU_IPU_INT_STAT_5_OFFSET IPU_REGISTERS_OFFSET + 0x000000F8 +#define IPU_IPU_INT_STAT_6_OFFSET IPU_REGISTERS_OFFSET + 0x000000FC +#define IPU_IPU_INT_STAT_7_OFFSET IPU_REGISTERS_OFFSET + 0x00000100 +#define IPU_IPU_INT_STAT_8_OFFSET IPU_REGISTERS_OFFSET + 0x00000104 +#define IPU_IPU_INT_STAT_9_OFFSET IPU_REGISTERS_OFFSET + 0x00000108 +#define IPU_IPU_INT_STAT_10_OFFSET IPU_REGISTERS_OFFSET + 0x0000010C +#define IPU_IPU_INT_STAT_11_OFFSET IPU_REGISTERS_OFFSET + 0x00000110 +#define IPU_IPU_INT_STAT_12_OFFSET IPU_REGISTERS_OFFSET + 0x00000114 +#define IPU_IPU_INT_STAT_13_OFFSET IPU_REGISTERS_OFFSET + 0x00000118 +#define IPU_IPU_INT_STAT_14_OFFSET IPU_REGISTERS_OFFSET + 0x0000011C +#define IPU_IPU_INT_STAT_15_OFFSET IPU_REGISTERS_OFFSET + 0x00000120 +#define IPU_IPU_CUR_BUF_0_OFFSET IPU_REGISTERS_OFFSET + 0x00000124 +#define IPU_IPU_CUR_BUF_1_OFFSET IPU_REGISTERS_OFFSET + 0x00000128 +#define IPU_IPU_ALT_CUR_BUF_0_OFFSET IPU_REGISTERS_OFFSET + 0x0000012C +#define IPU_IPU_ALT_CUR_BUF_1_OFFSET IPU_REGISTERS_OFFSET + 0x00000130 +#define IPU_IPU_SRM_STAT_OFFSET IPU_REGISTERS_OFFSET + 0x00000134 +#define IPU_IPU_PROC_TASKS_STAT_OFFSET IPU_REGISTERS_OFFSET + 0x00000138 +#define IPU_IPU_DISP_TASKS_STAT_OFFSET IPU_REGISTERS_OFFSET + 0x0000013C +#define IPU_IPU_CH_BUF0_RDY0_OFFSET IPU_REGISTERS_OFFSET + 0x00000140 +#define IPU_IPU_CH_BUF0_RDY1_OFFSET IPU_REGISTERS_OFFSET + 0x00000144 +#define IPU_IPU_CH_BUF1_RDY0_OFFSET IPU_REGISTERS_OFFSET + 0x00000148 +#define IPU_IPU_CH_BUF1_RDY1_OFFSET IPU_REGISTERS_OFFSET + 0x0000014C +#define IPU_IPU_CH_DB_MODE_SEL_0_OFFSET IPU_REGISTERS_OFFSET + 0x00000150 +#define IPU_IPU_CH_DB_MODE_SEL_1_OFFSET IPU_REGISTERS_OFFSET + 0x00000154 +#define IPU_IPU_ALT_CH_BUF0_RDY0_OFFSET IPU_REGISTERS_OFFSET + 0x00000158 +#define IPU_IPU_ALT_CH_BUF0_RDY1_OFFSET IPU_REGISTERS_OFFSET + 0x0000015C +#define IPU_IPU_ALT_CH_BUF1_RDY0_OFFSET IPU_REGISTERS_OFFSET + 0x00000160 +#define IPU_IPU_ALT_CH_BUF1_RDY1_OFFSET IPU_REGISTERS_OFFSET + 0x00000164 +#define IPU_IPU_ALT_CH_DB_MODE_SEL_0_OFFSET IPU_REGISTERS_OFFSET + 0x00000168 +#define IPU_IPU_ALT_CH_DB_MODE_SEL_1_OFFSET IPU_REGISTERS_OFFSET + 0x0000016C +#define IPU_IDMAC_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x00008000 +#define IPU_IDMAC_CH_EN_1_OFFSET IPU_REGISTERS_OFFSET + 0x00008004 +#define IPU_IDMAC_CH_EN_2_OFFSET IPU_REGISTERS_OFFSET + 0x00008008 +#define IPU_IDMAC_SEP_ALPHA_OFFSET IPU_REGISTERS_OFFSET + 0x0000800C +#define IPU_IDMAC_ALT_SEP_ALPHA_OFFSET IPU_REGISTERS_OFFSET + 0x00008010 +#define IPU_IDMAC_CH_PRI_1_OFFSET IPU_REGISTERS_OFFSET + 0x00008014 +#define IPU_IDMAC_CH_PRI_2_OFFSET IPU_REGISTERS_OFFSET + 0x00008018 +#define IPU_IDMAC_WM_EN_1_OFFSET IPU_REGISTERS_OFFSET + 0x0000801C +#define IPU_IDMAC_WM_EN_2_OFFSET IPU_REGISTERS_OFFSET + 0x00008020 +#define IPU_IDMAC_LOCK_EN_2_OFFSET IPU_REGISTERS_OFFSET + 0x00008024 +#define IPU_IDMAC_SUB_ADDR_0_OFFSET IPU_REGISTERS_OFFSET + 0x00008028 +#define IPU_IDMAC_SUB_ADDR_1_OFFSET IPU_REGISTERS_OFFSET + 0x0000802C +#define IPU_IDMAC_SUB_ADDR_2_OFFSET IPU_REGISTERS_OFFSET + 0x00008030 +#define IPU_IDMAC_BNDM_EN_1_OFFSET IPU_REGISTERS_OFFSET + 0x00008034 +#define IPU_IDMAC_BNDM_EN_2_OFFSET IPU_REGISTERS_OFFSET + 0x00008038 +#define IPU_IDMAC_SC_CORD_OFFSET IPU_REGISTERS_OFFSET + 0x0000803C +#define IPU_IDMAC_CH_BUSY_1_OFFSET IPU_REGISTERS_OFFSET + 0x00008040 +#define IPU_IDMAC_CH_BUSY_2_OFFSET IPU_REGISTERS_OFFSET + 0x00008044 +#define IPU_ISP_C0_OFFSET IPU_REGISTERS_OFFSET + 0x00010000 +#define IPU_ISP_C1_OFFSET IPU_REGISTERS_OFFSET + 0x00010004 +#define IPU_ISP_FS_OFFSET IPU_REGISTERS_OFFSET + 0x00010008 +#define IPU_ISP_BI_OFFSET IPU_REGISTERS_OFFSET + 0x0001000C +#define IPU_ISP_OCO_OFFSET IPU_REGISTERS_OFFSET + 0x00010010 +#define IPU_ISP_BPR1_OFFSET IPU_REGISTERS_OFFSET + 0x00010014 +#define IPU_ISP_BPR2_OFFSET IPU_REGISTERS_OFFSET + 0x00010018 +#define IPU_ISP_BPR3_OFFSET IPU_REGISTERS_OFFSET + 0x0001001C +#define IPU_ISP_CG_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010020 +#define IPU_ISP_CG_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010024 +#define IPU_ISP_ROC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010028 +#define IPU_ISP_ROC_1_OFFSET IPU_REGISTERS_OFFSET + 0x0001002C +#define IPU_ISP_ROC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00010030 +#define IPU_ISP_RRO_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010034 +#define IPU_ISP_RRO_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010038 +#define IPU_ISP_RRO_2_OFFSET IPU_REGISTERS_OFFSET + 0x0001003C +#define IPU_ISP_RRO_3_OFFSET IPU_REGISTERS_OFFSET + 0x00010040 +#define IPU_ISP_RRO_4_OFFSET IPU_REGISTERS_OFFSET + 0x00010044 +#define IPU_ISP_RRO_5_OFFSET IPU_REGISTERS_OFFSET + 0x00010048 +#define IPU_ISP_RRO_6_OFFSET IPU_REGISTERS_OFFSET + 0x0001004C +#define IPU_ISP_RRO_7_OFFSET IPU_REGISTERS_OFFSET + 0x00010050 +#define IPU_ISP_GRO_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010054 +#define IPU_ISP_GRO_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010058 +#define IPU_ISP_GRO_2_OFFSET IPU_REGISTERS_OFFSET + 0x0001005C +#define IPU_ISP_GRO_3_OFFSET IPU_REGISTERS_OFFSET + 0x00010060 +#define IPU_ISP_GRO_4_OFFSET IPU_REGISTERS_OFFSET + 0x00010064 +#define IPU_ISP_GRO_5_OFFSET IPU_REGISTERS_OFFSET + 0x00010068 +#define IPU_ISP_GRO_6_OFFSET IPU_REGISTERS_OFFSET + 0x0001006C +#define IPU_ISP_GRO_7_OFFSET IPU_REGISTERS_OFFSET + 0x00010070 +#define IPU_ISP_BRO_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010074 +#define IPU_ISP_BRO_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010078 +#define IPU_ISP_BRO_2_OFFSET IPU_REGISTERS_OFFSET + 0x0001007C +#define IPU_ISP_BRO_3_OFFSET IPU_REGISTERS_OFFSET + 0x00010080 +#define IPU_ISP_BRO_4_OFFSET IPU_REGISTERS_OFFSET + 0x00010084 +#define IPU_ISP_BRO_5_OFFSET IPU_REGISTERS_OFFSET + 0x00010088 +#define IPU_ISP_BRO_6_OFFSET IPU_REGISTERS_OFFSET + 0x0001008C +#define IPU_ISP_BRO_7_OFFSET IPU_REGISTERS_OFFSET + 0x00010090 +#define IPU_ISP_GAMMA_C_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010094 +#define IPU_ISP_GAMMA_C_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010098 +#define IPU_ISP_GAMMA_C_2_OFFSET IPU_REGISTERS_OFFSET + 0x0001009C +#define IPU_ISP_GAMMA_C_3_OFFSET IPU_REGISTERS_OFFSET + 0x000100A0 +#define IPU_ISP_GAMMA_C_4_OFFSET IPU_REGISTERS_OFFSET + 0x000100A4 +#define IPU_ISP_GAMMA_C_5_OFFSET IPU_REGISTERS_OFFSET + 0x000100A8 +#define IPU_ISP_GAMMA_C_6_OFFSET IPU_REGISTERS_OFFSET + 0x000100AC +#define IPU_ISP_GAMMA_C_7_OFFSET IPU_REGISTERS_OFFSET + 0x000100B0 +#define IPU_ISP_GAMMA_S_0_OFFSET IPU_REGISTERS_OFFSET + 0x000100B4 +#define IPU_ISP_GAMMA_S_1_OFFSET IPU_REGISTERS_OFFSET + 0x000100B8 +#define IPU_ISP_GAMMA_S_2_OFFSET IPU_REGISTERS_OFFSET + 0x000100BC +#define IPU_ISP_GAMMA_S_3_OFFSET IPU_REGISTERS_OFFSET + 0x000100C0 +#define IPU_ISP_CSCA_0_OFFSET IPU_REGISTERS_OFFSET + 0x000100C4 +#define IPU_ISP_CSCA_1_OFFSET IPU_REGISTERS_OFFSET + 0x000100C8 +#define IPU_ISP_CSCA_2_OFFSET IPU_REGISTERS_OFFSET + 0x000100CC +#define IPU_ISP_CSCA_3_OFFSET IPU_REGISTERS_OFFSET + 0x000100D0 +#define IPU_ISP_CSC_0_OFFSET IPU_REGISTERS_OFFSET + 0x000100D4 +#define IPU_ISP_CSC_1_OFFSET IPU_REGISTERS_OFFSET + 0x000100D8 +#define IPU_ISP_CNS_C_0_OFFSET IPU_REGISTERS_OFFSET + 0x000100DC +#define IPU_ISP_CNS_C_1_OFFSET IPU_REGISTERS_OFFSET + 0x000100E0 +#define IPU_ISP_CNS_C_2_OFFSET IPU_REGISTERS_OFFSET + 0x000100E4 +#define IPU_ISP_CNS_C_3_OFFSET IPU_REGISTERS_OFFSET + 0x000100E8 +#define IPU_ISP_CNS_C_4_OFFSET IPU_REGISTERS_OFFSET + 0x000100EC +#define IPU_ISP_CNS_C_5_OFFSET IPU_REGISTERS_OFFSET + 0x000100F0 +#define IPU_ISP_CNS_C_6_OFFSET IPU_REGISTERS_OFFSET + 0x000100F4 +#define IPU_ISP_CNS_C_7_OFFSET IPU_REGISTERS_OFFSET + 0x000100F8 +#define IPU_ISP_CNS_S_0_OFFSET IPU_REGISTERS_OFFSET + 0x000100FC +#define IPU_ISP_CNS_S_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010100 +#define IPU_ISP_CNS_S_2_OFFSET IPU_REGISTERS_OFFSET + 0x00010104 +#define IPU_ISP_CNS_S_3_OFFSET IPU_REGISTERS_OFFSET + 0x00010108 +#define IPU_ISP_MTF_ROC_C_0_OFFSET IPU_REGISTERS_OFFSET + 0x0001010C +#define IPU_ISP_MTF_ROC_C_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010110 +#define IPU_ISP_MTF_ROC_C_2_OFFSET IPU_REGISTERS_OFFSET + 0x00010114 +#define IPU_ISP_MTF_ROC_C_3_OFFSET IPU_REGISTERS_OFFSET + 0x00010118 +#define IPU_ISP_MTF_ROC_S_0_OFFSET IPU_REGISTERS_OFFSET + 0x0001011C +#define IPU_ISP_MTF_ROC_S_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010120 +#define IPU_ISP_HFE_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010124 +#define IPU_ISP_HFE_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010128 +#define IPU_ISP_HFE_2_OFFSET IPU_REGISTERS_OFFSET + 0x0001012C +#define IPU_ISP_HFE_S_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010130 +#define IPU_ISP_HFE_S_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010134 +#define IPU_ISP_HFE_S_2_OFFSET IPU_REGISTERS_OFFSET + 0x00010138 +#define IPU_ISP_HFE_S_3_OFFSET IPU_REGISTERS_OFFSET + 0x0001013C +#define IPU_ISP_HFE_C_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010140 +#define IPU_ISP_HFE_C_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010144 +#define IPU_ISP_HFE_C_2_OFFSET IPU_REGISTERS_OFFSET + 0x00010148 +#define IPU_ISP_HFE_C_3_OFFSET IPU_REGISTERS_OFFSET + 0x0001014C +#define IPU_ISP_STC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010150 +#define IPU_ISP_STC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00010154 +#define IPU_ISP_FC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00010158 +#define IPU_ISP_FC_1_OFFSET IPU_REGISTERS_OFFSET + 0x0001015C +#define IPU_ISP_FS_SWSX_OFFSET IPU_REGISTERS_OFFSET + 0x00010160 +#define IPU_ISP_FS_SYSZ_OFFSET IPU_REGISTERS_OFFSET + 0x00010164 +#define IPU_ISP_FS_CWCX_OFFSET IPU_REGISTERS_OFFSET + 0x00010168 +#define IPU_ISP_FS_CYCZ_OFFSET IPU_REGISTERS_OFFSET + 0x0001016C +#define IPU_ISP_FS_MWMX_OFFSET IPU_REGISTERS_OFFSET + 0x00010170 +#define IPU_ISP_FS_MYMZ_OFFSET IPU_REGISTERS_OFFSET + 0x00010174 +#define IPU_ISP_FS_BPRS_OFFSET IPU_REGISTERS_OFFSET + 0x00010178 +#define IPU_DP_COM_CONF_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x00018000 +#define IPU_DP_GRAPH_WIND_CTRL_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x00018004 +#define IPU_DP_FG_POS_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x00018008 +#define IPU_DP_CUR_POS_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x0001800C +#define IPU_DP_CUR_MAP_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x00018010 +#define IPU_DP_GAMMA_C_SYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00018014 +#define IPU_DP_GAMMA_C_SYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00018018 +#define IPU_DP_GAMMA_C_SYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0001801C +#define IPU_DP_GAMMA_C_SYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00018020 +#define IPU_DP_GAMMA_C_SYNC_4_OFFSET IPU_REGISTERS_OFFSET + 0x00018024 +#define IPU_DP_GAMMA_C_SYNC_5_OFFSET IPU_REGISTERS_OFFSET + 0x00018028 +#define IPU_DP_GAMMA_C_SYNC_6_OFFSET IPU_REGISTERS_OFFSET + 0x0001802C +#define IPU_DP_GAMMA_C_SYNC_7_OFFSET IPU_REGISTERS_OFFSET + 0x00018030 +#define IPU_DP_GAMMA_S_SYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00018034 +#define IPU_DP_GAMMA_S_SYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00018038 +#define IPU_DP_GAMMA_S_SYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0001803C +#define IPU_DP_GAMMA_S_SYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00018040 +#define IPU_DP_CSCA_SYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00018044 +#define IPU_DP_CSCA_SYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00018048 +#define IPU_DP_CSCA_SYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0001804C +#define IPU_DP_CSCA_SYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00018050 +#define IPU_DP_CSC_SYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00018054 +#define IPU_DP_CSC_SYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00018058 +#define IPU_DP_COM_CONF_ASYNC_OFFSET IPU_REGISTERS_OFFSET + 0x0001805C +#define IPU_DP_GRAPH_WIND_CTRL_ASYNC_OFFSET IPU_REGISTERS_OFFSET + 0x00018060 +#define IPU_DP_FG_POS_ASYNC_OFFSET IPU_REGISTERS_OFFSET + 0x00018064 +#define IPU_DP_CUR_POS_ASYNC_OFFSET IPU_REGISTERS_OFFSET + 0x00018068 +#define IPU_DP_CUR_MAP_ASYNC_OFFSET IPU_REGISTERS_OFFSET + 0x0001806C +#define IPU_DP_GAMMA_C_ASYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00018070 +#define IPU_DP_GAMMA_C_ASYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00018074 +#define IPU_DP_GAMMA_C_ASYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00018078 +#define IPU_DP_GAMMA_C_ASYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x0001807C +#define IPU_DP_GAMMA_C_ASYNC_4_OFFSET IPU_REGISTERS_OFFSET + 0x00018080 +#define IPU_DP_GAMMA_C_ASYNC_5_OFFSET IPU_REGISTERS_OFFSET + 0x00018084 +#define IPU_DP_GAMMA_C_ASYNC_6_OFFSET IPU_REGISTERS_OFFSET + 0x00018088 +#define IPU_DP_GAMMA_C_ASYNC_7_OFFSET IPU_REGISTERS_OFFSET + 0x0001808C +#define IPU_DP_GAMMA_S_ASYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x00018090 +#define IPU_DP_GAMMA_S_ASYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00018094 +#define IPU_DP_GAMMA_S_ASYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00018098 +#define IPU_DP_GAMMA_S_ASYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x0001809C +#define IPU_DP_CSCA_ASYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x000180A0 +#define IPU_DP_CSCA_ASYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x000180A4 +#define IPU_DP_CSCA_ASYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x000180A8 +#define IPU_DP_CSCA_ASYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x000180AC +#define IPU_DP_CSC_ASYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x000180B0 +#define IPU_DP_CSC_ASYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x000180B4 +#define IPU_DP_DEBUG_CNT_OFFSET IPU_REGISTERS_OFFSET + 0x000180B8 +#define IPU_DP_DEBUG_STAT_OFFSET IPU_REGISTERS_OFFSET + 0x000180BC +#define IPU_IC_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x00020000 +#define IPU_IC_PRP_ENC_RSC_OFFSET IPU_REGISTERS_OFFSET + 0x00020004 +#define IPU_IC_PRP_VF_RSC_OFFSET IPU_REGISTERS_OFFSET + 0x00020008 +#define IPU_IC_PP_RSC_OFFSET IPU_REGISTERS_OFFSET + 0x0002000C +#define IPU_IC_CMBP_1_OFFSET IPU_REGISTERS_OFFSET + 0x00020010 +#define IPU_IC_CMBP_2_OFFSET IPU_REGISTERS_OFFSET + 0x00020014 +#define IPU_IC_IDMAC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00020018 +#define IPU_IC_IDMAC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0002001C +#define IPU_IC_IDMAC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00020020 +#define IPU_IC_IDMAC_4_OFFSET IPU_REGISTERS_OFFSET + 0x00020024 +#define IPU_CSI0_SENS_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x00030000 +#define IPU_CSI0_SENS_FRM_SIZE_OFFSET IPU_REGISTERS_OFFSET + 0x00030004 +#define IPU_CSI0_ACT_FRM_SIZE_OFFSET IPU_REGISTERS_OFFSET + 0x00030008 +#define IPU_CSI0_OUT_FRM_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x0003000C +#define IPU_CSI0_TST_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x00030010 +#define IPU_CSI0_CCIR_CODE_1_OFFSET IPU_REGISTERS_OFFSET + 0x00030014 +#define IPU_CSI0_CCIR_CODE_2_OFFSET IPU_REGISTERS_OFFSET + 0x00030018 +#define IPU_CSI0_CCIR_CODE_3_OFFSET IPU_REGISTERS_OFFSET + 0x0003001C +#define IPU_CSI0_DI_OFFSET IPU_REGISTERS_OFFSET + 0x00030020 +#define IPU_CSI0_SKIP_OFFSET IPU_REGISTERS_OFFSET + 0x00030024 +#define IPU_CSI0_CPD_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x00030028 +#define IPU_CSI0_CPD_RC_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003002C +#define IPU_CSI0_CPD_RC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00030030 +#define IPU_CSI0_CPD_RC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00030034 +#define IPU_CSI0_CPD_RC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00030038 +#define IPU_CSI0_CPD_RC_4_OFFSET IPU_REGISTERS_OFFSET + 0x0003003C +#define IPU_CSI0_CPD_RC_5_OFFSET IPU_REGISTERS_OFFSET + 0x00030040 +#define IPU_CSI0_CPD_RC_6_OFFSET IPU_REGISTERS_OFFSET + 0x00030044 +#define IPU_CSI0_CPD_RC_7_OFFSET IPU_REGISTERS_OFFSET + 0x00030048 +#define IPU_CSI0_CPD_RS_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003004C +#define IPU_CSI0_CPD_RS_1_OFFSET IPU_REGISTERS_OFFSET + 0x00030050 +#define IPU_CSI0_CPD_RS_2_OFFSET IPU_REGISTERS_OFFSET + 0x00030054 +#define IPU_CSI0_CPD_RS_3_OFFSET IPU_REGISTERS_OFFSET + 0x00030058 +#define IPU_CSI0_CPD_GRC_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003005C +#define IPU_CSI0_CPD_GRC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00030060 +#define IPU_CSI0_CPD_GRC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00030064 +#define IPU_CSI0_CPD_GRC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00030068 +#define IPU_CSI0_CPD_GRC_4_OFFSET IPU_REGISTERS_OFFSET + 0x0003006C +#define IPU_CSI0_CPD_GRC_5_OFFSET IPU_REGISTERS_OFFSET + 0x00030070 +#define IPU_CSI0_CPD_GRC_6_OFFSET IPU_REGISTERS_OFFSET + 0x00030074 +#define IPU_CSI0_CPD_GRC_7_OFFSET IPU_REGISTERS_OFFSET + 0x00030078 +#define IPU_CSI0_CPD_GRS_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003007C +#define IPU_CSI0_CPD_GRS_1_OFFSET IPU_REGISTERS_OFFSET + 0x00030080 +#define IPU_CSI0_CPD_GRS_2_OFFSET IPU_REGISTERS_OFFSET + 0x00030084 +#define IPU_CSI0_CPD_GRS_3_OFFSET IPU_REGISTERS_OFFSET + 0x00030088 +#define IPU_CSI0_CPD_GBC_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003008C +#define IPU_CSI0_CPD_GBC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00030090 +#define IPU_CSI0_CPD_GBC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00030094 +#define IPU_CSI0_CPD_GBC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00030098 +#define IPU_CSI0_CPD_GBC_4_OFFSET IPU_REGISTERS_OFFSET + 0x0003009C +#define IPU_CSI0_CPD_GBC_5_OFFSET IPU_REGISTERS_OFFSET + 0x000300A0 +#define IPU_CSI0_CPD_GBC_6_OFFSET IPU_REGISTERS_OFFSET + 0x000300A4 +#define IPU_CSI0_CPD_GBC_7_OFFSET IPU_REGISTERS_OFFSET + 0x000300A8 +#define IPU_CSI0_CPD_GBS_0_OFFSET IPU_REGISTERS_OFFSET + 0x000300AC +#define IPU_CSI0_CPD_GBS_1_OFFSET IPU_REGISTERS_OFFSET + 0x000300B0 +#define IPU_CSI0_CPD_GBS_2_OFFSET IPU_REGISTERS_OFFSET + 0x000300B4 +#define IPU_CSI0_CPD_GBS_3_OFFSET IPU_REGISTERS_OFFSET + 0x000300B8 +#define IPU_CSI0_CPD_BC_0_OFFSET IPU_REGISTERS_OFFSET + 0x000300BC +#define IPU_CSI0_CPD_BC_1_OFFSET IPU_REGISTERS_OFFSET + 0x000300C0 +#define IPU_CSI0_CPD_BC_2_OFFSET IPU_REGISTERS_OFFSET + 0x000300C4 +#define IPU_CSI0_CPD_BC_3_OFFSET IPU_REGISTERS_OFFSET + 0x000300C8 +#define IPU_CSI0_CPD_BC_4_OFFSET IPU_REGISTERS_OFFSET + 0x000300CC +#define IPU_CSI0_CPD_BC_5_OFFSET IPU_REGISTERS_OFFSET + 0x000300D0 +#define IPU_CSI0_CPD_BC_6_OFFSET IPU_REGISTERS_OFFSET + 0x000300D4 +#define IPU_CSI0_CPD_BC_7_OFFSET IPU_REGISTERS_OFFSET + 0x000300D8 +#define IPU_CSI0_CPD_BS_0_OFFSET IPU_REGISTERS_OFFSET + 0x000300DC +#define IPU_CSI0_CPD_BS_1_OFFSET IPU_REGISTERS_OFFSET + 0x000300E0 +#define IPU_CSI0_CPD_BS_2_OFFSET IPU_REGISTERS_OFFSET + 0x000300E4 +#define IPU_CSI0_CPD_BS_3_OFFSET IPU_REGISTERS_OFFSET + 0x000300E8 +#define IPU_CSI0_CPD_OFFSET1_OFFSET IPU_REGISTERS_OFFSET + 0x000300EC +#define IPU_CSI0_CPD_OFFSET2_OFFSET IPU_REGISTERS_OFFSET + 0x000300F0 +#define IPU_CSI1_SENS_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x00038000 +#define IPU_CSI1_SENS_FRM_SIZE_OFFSET IPU_REGISTERS_OFFSET + 0x00038004 +#define IPU_CSI1_ACT_FRM_SIZE_OFFSET IPU_REGISTERS_OFFSET + 0x00038008 +#define IPU_CSI1_OUT_FRM_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x0003800C +#define IPU_CSI1_TST_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x00038010 +#define IPU_CSI1_CCIR_CODE_1_OFFSET IPU_REGISTERS_OFFSET + 0x00038014 +#define IPU_CSI1_CCIR_CODE_2_OFFSET IPU_REGISTERS_OFFSET + 0x00038018 +#define IPU_CSI1_CCIR_CODE_3_OFFSET IPU_REGISTERS_OFFSET + 0x0003801C +#define IPU_CSI1_DI_OFFSET IPU_REGISTERS_OFFSET + 0x00038020 +#define IPU_CSI1_SKIP_OFFSET IPU_REGISTERS_OFFSET + 0x00038024 +#define IPU_CSI1_CPD_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x00038028 +#define IPU_CSI1_CPD_RC_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003802C +#define IPU_CSI1_CPD_RC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00038030 +#define IPU_CSI1_CPD_RC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00038034 +#define IPU_CSI1_CPD_RC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00038038 +#define IPU_CSI1_CPD_RC_4_OFFSET IPU_REGISTERS_OFFSET + 0x0003803C +#define IPU_CSI1_CPD_RC_5_OFFSET IPU_REGISTERS_OFFSET + 0x00038040 +#define IPU_CSI1_CPD_RC_6_OFFSET IPU_REGISTERS_OFFSET + 0x00038044 +#define IPU_CSI1_CPD_RC_7_OFFSET IPU_REGISTERS_OFFSET + 0x00038048 +#define IPU_CSI1_CPD_RS_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003804C +#define IPU_CSI1_CPD_RS_1_OFFSET IPU_REGISTERS_OFFSET + 0x00038050 +#define IPU_CSI1_CPD_RS_2_OFFSET IPU_REGISTERS_OFFSET + 0x00038054 +#define IPU_CSI1_CPD_RS_3_OFFSET IPU_REGISTERS_OFFSET + 0x00038058 +#define IPU_CSI1_CPD_GRC_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003805C +#define IPU_CSI1_CPD_GRC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00038060 +#define IPU_CSI1_CPD_GRC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00038064 +#define IPU_CSI1_CPD_GRC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00038068 +#define IPU_CSI1_CPD_GRC_4_OFFSET IPU_REGISTERS_OFFSET + 0x0003806C +#define IPU_CSI1_CPD_GRC_5_OFFSET IPU_REGISTERS_OFFSET + 0x00038070 +#define IPU_CSI1_CPD_GRC_6_OFFSET IPU_REGISTERS_OFFSET + 0x00038074 +#define IPU_CSI1_CPD_GRC_7_OFFSET IPU_REGISTERS_OFFSET + 0x00038078 +#define IPU_CSI1_CPD_GRS_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003807C +#define IPU_CSI1_CPD_GRS_1_OFFSET IPU_REGISTERS_OFFSET + 0x00038080 +#define IPU_CSI1_CPD_GRS_2_OFFSET IPU_REGISTERS_OFFSET + 0x00038084 +#define IPU_CSI1_CPD_GRS_3_OFFSET IPU_REGISTERS_OFFSET + 0x00038088 +#define IPU_CSI1_CPD_GBC_0_OFFSET IPU_REGISTERS_OFFSET + 0x0003808C +#define IPU_CSI1_CPD_GBC_1_OFFSET IPU_REGISTERS_OFFSET + 0x00038090 +#define IPU_CSI1_CPD_GBC_2_OFFSET IPU_REGISTERS_OFFSET + 0x00038094 +#define IPU_CSI1_CPD_GBC_3_OFFSET IPU_REGISTERS_OFFSET + 0x00038098 +#define IPU_CSI1_CPD_GBC_4_OFFSET IPU_REGISTERS_OFFSET + 0x0003809C +#define IPU_CSI1_CPD_GBC_5_OFFSET IPU_REGISTERS_OFFSET + 0x000380A0 +#define IPU_CSI1_CPD_GBC_6_OFFSET IPU_REGISTERS_OFFSET + 0x000380A4 +#define IPU_CSI1_CPD_GBC_7_OFFSET IPU_REGISTERS_OFFSET + 0x000380A8 +#define IPU_CSI1_CPD_GBS_0_OFFSET IPU_REGISTERS_OFFSET + 0x000380AC +#define IPU_CSI1_CPD_GBS_1_OFFSET IPU_REGISTERS_OFFSET + 0x000380B0 +#define IPU_CSI1_CPD_GBS_2_OFFSET IPU_REGISTERS_OFFSET + 0x000380B4 +#define IPU_CSI1_CPD_GBS_3_OFFSET IPU_REGISTERS_OFFSET + 0x000380B8 +#define IPU_CSI1_CPD_BC_0_OFFSET IPU_REGISTERS_OFFSET + 0x000380BC +#define IPU_CSI1_CPD_BC_1_OFFSET IPU_REGISTERS_OFFSET + 0x000380C0 +#define IPU_CSI1_CPD_BC_2_OFFSET IPU_REGISTERS_OFFSET + 0x000380C4 +#define IPU_CSI1_CPD_BC_3_OFFSET IPU_REGISTERS_OFFSET + 0x000380C8 +#define IPU_CSI1_CPD_BC_4_OFFSET IPU_REGISTERS_OFFSET + 0x000380CC +#define IPU_CSI1_CPD_BC_5_OFFSET IPU_REGISTERS_OFFSET + 0x000380D0 +#define IPU_CSI1_CPD_BC_6_OFFSET IPU_REGISTERS_OFFSET + 0x000380D4 +#define IPU_CSI1_CPD_BC_7_OFFSET IPU_REGISTERS_OFFSET + 0x000380D8 +#define IPU_CSI1_CPD_BS_0_OFFSET IPU_REGISTERS_OFFSET + 0x000380DC +#define IPU_CSI1_CPD_BS_1_OFFSET IPU_REGISTERS_OFFSET + 0x000380E0 +#define IPU_CSI1_CPD_BS_2_OFFSET IPU_REGISTERS_OFFSET + 0x000380E4 +#define IPU_CSI1_CPD_BS_3_OFFSET IPU_REGISTERS_OFFSET + 0x000380E8 +#define IPU_CSI1_CPD_OFFSET1_OFFSET IPU_REGISTERS_OFFSET + 0x000380EC +#define IPU_CSI1_CPD_OFFSET2_OFFSET IPU_REGISTERS_OFFSET + 0x000380F0 +#define IPU_DI0_GENERAL_OFFSET IPU_REGISTERS_OFFSET + 0x00040000 +#define IPU_DI0_BS_CLKGEN0_OFFSET IPU_REGISTERS_OFFSET + 0x00040004 +#define IPU_DI0_BS_CLKGEN1_OFFSET IPU_REGISTERS_OFFSET + 0x00040008 +#define IPU_DI0_SW_GEN0_1_OFFSET IPU_REGISTERS_OFFSET + 0x0004000C +#define IPU_DI0_SW_GEN0_2_OFFSET IPU_REGISTERS_OFFSET + 0x00040010 +#define IPU_DI0_SW_GEN0_3_OFFSET IPU_REGISTERS_OFFSET + 0x00040014 +#define IPU_DI0_SW_GEN0_4_OFFSET IPU_REGISTERS_OFFSET + 0x00040018 +#define IPU_DI0_SW_GEN0_5_OFFSET IPU_REGISTERS_OFFSET + 0x0004001C +#define IPU_DI0_SW_GEN0_6_OFFSET IPU_REGISTERS_OFFSET + 0x00040020 +#define IPU_DI0_SW_GEN0_7_OFFSET IPU_REGISTERS_OFFSET + 0x00040024 +#define IPU_DI0_SW_GEN0_8_OFFSET IPU_REGISTERS_OFFSET + 0x00040028 +#define IPU_DI0_SW_GEN0_9_OFFSET IPU_REGISTERS_OFFSET + 0x0004002C +#define IPU_DI0_SW_GEN1_1_OFFSET IPU_REGISTERS_OFFSET + 0x00040030 +#define IPU_DI0_SW_GEN1_2_OFFSET IPU_REGISTERS_OFFSET + 0x00040034 +#define IPU_DI0_SW_GEN1_3_OFFSET IPU_REGISTERS_OFFSET + 0x00040038 +#define IPU_DI0_SW_GEN1_4_OFFSET IPU_REGISTERS_OFFSET + 0x0004003C +#define IPU_DI0_SW_GEN1_5_OFFSET IPU_REGISTERS_OFFSET + 0x00040040 +#define IPU_DI0_SW_GEN1_6_OFFSET IPU_REGISTERS_OFFSET + 0x00040044 +#define IPU_DI0_SW_GEN1_7_OFFSET IPU_REGISTERS_OFFSET + 0x00040048 +#define IPU_DI0_SW_GEN1_8_OFFSET IPU_REGISTERS_OFFSET + 0x0004004C +#define IPU_DI0_SW_GEN1_9_OFFSET IPU_REGISTERS_OFFSET + 0x00040050 +#define IPU_DI0_SYNC_AS_GEN_OFFSET IPU_REGISTERS_OFFSET + 0x00040054 +#define IPU_DI0_DW_GEN_0_OFFSET IPU_REGISTERS_OFFSET + 0x00040058 +#define IPU_DI0_DW_GEN_1_OFFSET IPU_REGISTERS_OFFSET + 0x0004005C +#define IPU_DI0_DW_GEN_2_OFFSET IPU_REGISTERS_OFFSET + 0x00040060 +#define IPU_DI0_DW_GEN_3_OFFSET IPU_REGISTERS_OFFSET + 0x00040064 +#define IPU_DI0_DW_GEN_4_OFFSET IPU_REGISTERS_OFFSET + 0x00040068 +#define IPU_DI0_DW_GEN_5_OFFSET IPU_REGISTERS_OFFSET + 0x0004006C +#define IPU_DI0_DW_GEN_6_OFFSET IPU_REGISTERS_OFFSET + 0x00040070 +#define IPU_DI0_DW_GEN_7_OFFSET IPU_REGISTERS_OFFSET + 0x00040074 +#define IPU_DI0_DW_GEN_8_OFFSET IPU_REGISTERS_OFFSET + 0x00040078 +#define IPU_DI0_DW_GEN_9_OFFSET IPU_REGISTERS_OFFSET + 0x0004007C +#define IPU_DI0_DW_GEN_10_OFFSET IPU_REGISTERS_OFFSET + 0x00040080 +#define IPU_DI0_DW_GEN_11_OFFSET IPU_REGISTERS_OFFSET + 0x00040084 +#define IPU_DI0_DW_SET0_0_OFFSET IPU_REGISTERS_OFFSET + 0x00040088 +#define IPU_DI0_DW_SET0_1_OFFSET IPU_REGISTERS_OFFSET + 0x0004008C +#define IPU_DI0_DW_SET0_2_OFFSET IPU_REGISTERS_OFFSET + 0x00040090 +#define IPU_DI0_DW_SET0_3_OFFSET IPU_REGISTERS_OFFSET + 0x00040094 +#define IPU_DI0_DW_SET0_4_OFFSET IPU_REGISTERS_OFFSET + 0x00040098 +#define IPU_DI0_DW_SET0_5_OFFSET IPU_REGISTERS_OFFSET + 0x0004009C +#define IPU_DI0_DW_SET0_6_OFFSET IPU_REGISTERS_OFFSET + 0x000400A0 +#define IPU_DI0_DW_SET0_7_OFFSET IPU_REGISTERS_OFFSET + 0x000400A4 +#define IPU_DI0_DW_SET0_8_OFFSET IPU_REGISTERS_OFFSET + 0x000400A8 +#define IPU_DI0_DW_SET0_9_OFFSET IPU_REGISTERS_OFFSET + 0x000400AC +#define IPU_DI0_DW_SET0_10_OFFSET IPU_REGISTERS_OFFSET + 0x000400B0 +#define IPU_DI0_DW_SET0_11_OFFSET IPU_REGISTERS_OFFSET + 0x000400B4 +#define IPU_DI0_DW_SET1_0_OFFSET IPU_REGISTERS_OFFSET + 0x000400B8 +#define IPU_DI0_DW_SET1_1_OFFSET IPU_REGISTERS_OFFSET + 0x000400BC +#define IPU_DI0_DW_SET1_2_OFFSET IPU_REGISTERS_OFFSET + 0x000400C0 +#define IPU_DI0_DW_SET1_3_OFFSET IPU_REGISTERS_OFFSET + 0x000400C4 +#define IPU_DI0_DW_SET1_4_OFFSET IPU_REGISTERS_OFFSET + 0x000400C8 +#define IPU_DI0_DW_SET1_5_OFFSET IPU_REGISTERS_OFFSET + 0x000400CC +#define IPU_DI0_DW_SET1_6_OFFSET IPU_REGISTERS_OFFSET + 0x000400D0 +#define IPU_DI0_DW_SET1_7_OFFSET IPU_REGISTERS_OFFSET + 0x000400D4 +#define IPU_DI0_DW_SET1_8_OFFSET IPU_REGISTERS_OFFSET + 0x000400D8 +#define IPU_DI0_DW_SET1_9_OFFSET IPU_REGISTERS_OFFSET + 0x000400DC +#define IPU_DI0_DW_SET1_10_OFFSET IPU_REGISTERS_OFFSET + 0x000400E0 +#define IPU_DI0_DW_SET1_11_OFFSET IPU_REGISTERS_OFFSET + 0x000400E4 +#define IPU_DI0_DW_SET2_0_OFFSET IPU_REGISTERS_OFFSET + 0x000400E8 +#define IPU_DI0_DW_SET2_1_OFFSET IPU_REGISTERS_OFFSET + 0x000400EC +#define IPU_DI0_DW_SET2_2_OFFSET IPU_REGISTERS_OFFSET + 0x000400F0 +#define IPU_DI0_DW_SET2_3_OFFSET IPU_REGISTERS_OFFSET + 0x000400F4 +#define IPU_DI0_DW_SET2_4_OFFSET IPU_REGISTERS_OFFSET + 0x000400F8 +#define IPU_DI0_DW_SET2_5_OFFSET IPU_REGISTERS_OFFSET + 0x000400FC +#define IPU_DI0_DW_SET2_6_OFFSET IPU_REGISTERS_OFFSET + 0x00040100 +#define IPU_DI0_DW_SET2_7_OFFSET IPU_REGISTERS_OFFSET + 0x00040104 +#define IPU_DI0_DW_SET2_8_OFFSET IPU_REGISTERS_OFFSET + 0x00040108 +#define IPU_DI0_DW_SET2_9_OFFSET IPU_REGISTERS_OFFSET + 0x0004010C +#define IPU_DI0_DW_SET2_10_OFFSET IPU_REGISTERS_OFFSET + 0x00040110 +#define IPU_DI0_DW_SET2_11_OFFSET IPU_REGISTERS_OFFSET + 0x00040114 +#define IPU_DI0_DW_SET3_0_OFFSET IPU_REGISTERS_OFFSET + 0x00040118 +#define IPU_DI0_DW_SET3_1_OFFSET IPU_REGISTERS_OFFSET + 0x0004011C +#define IPU_DI0_DW_SET3_2_OFFSET IPU_REGISTERS_OFFSET + 0x00040120 +#define IPU_DI0_DW_SET3_3_OFFSET IPU_REGISTERS_OFFSET + 0x00040124 +#define IPU_DI0_DW_SET3_4_OFFSET IPU_REGISTERS_OFFSET + 0x00040128 +#define IPU_DI0_DW_SET3_5_OFFSET IPU_REGISTERS_OFFSET + 0x0004012C +#define IPU_DI0_DW_SET3_6_OFFSET IPU_REGISTERS_OFFSET + 0x00040130 +#define IPU_DI0_DW_SET3_7_OFFSET IPU_REGISTERS_OFFSET + 0x00040134 +#define IPU_DI0_DW_SET3_8_OFFSET IPU_REGISTERS_OFFSET + 0x00040138 +#define IPU_DI0_DW_SET3_9_OFFSET IPU_REGISTERS_OFFSET + 0x0004013C +#define IPU_DI0_DW_SET3_10_OFFSET IPU_REGISTERS_OFFSET + 0x00040140 +#define IPU_DI0_DW_SET3_11_OFFSET IPU_REGISTERS_OFFSET + 0x00040144 +#define IPU_DI0_STP_REP_1_OFFSET IPU_REGISTERS_OFFSET + 0x00040148 +#define IPU_DI0_STP_REP_2_OFFSET IPU_REGISTERS_OFFSET + 0x0004014C +#define IPU_DI0_STP_REP_3_OFFSET IPU_REGISTERS_OFFSET + 0x00040150 +#define IPU_DI0_STP_REP_4_OFFSET IPU_REGISTERS_OFFSET + 0x00040154 +#define IPU_DI0_STP_REP_9_OFFSET IPU_REGISTERS_OFFSET + 0x00040158 +#define IPU_DI0_SER_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x0004015C +#define IPU_DI0_SSC_OFFSET IPU_REGISTERS_OFFSET + 0x00040160 +#define IPU_DI0_POL_OFFSET IPU_REGISTERS_OFFSET + 0x00040164 +#define IPU_DI0_AW0_OFFSET IPU_REGISTERS_OFFSET + 0x00040168 +#define IPU_DI0_AW1_OFFSET IPU_REGISTERS_OFFSET + 0x0004016C +#define IPU_DI1_GENERAL_OFFSET IPU_REGISTERS_OFFSET + 0x00048000 +#define IPU_DI1_BS_CLKGEN0_OFFSET IPU_REGISTERS_OFFSET + 0x00048004 +#define IPU_DI1_BS_CLKGEN1_OFFSET IPU_REGISTERS_OFFSET + 0x00048008 +#define IPU_DI1_SW_GEN0_1_OFFSET IPU_REGISTERS_OFFSET + 0x0004800C +#define IPU_DI1_SW_GEN0_2_OFFSET IPU_REGISTERS_OFFSET + 0x00048010 +#define IPU_DI1_SW_GEN0_3_OFFSET IPU_REGISTERS_OFFSET + 0x00048014 +#define IPU_DI1_SW_GEN0_4_OFFSET IPU_REGISTERS_OFFSET + 0x00048018 +#define IPU_DI1_SW_GEN0_5_OFFSET IPU_REGISTERS_OFFSET + 0x0004801C +#define IPU_DI1_SW_GEN0_6_OFFSET IPU_REGISTERS_OFFSET + 0x00048020 +#define IPU_DI1_SW_GEN0_7_OFFSET IPU_REGISTERS_OFFSET + 0x00048024 +#define IPU_DI1_SW_GEN0_8_OFFSET IPU_REGISTERS_OFFSET + 0x00048028 +#define IPU_DI1_SW_GEN0_9_OFFSET IPU_REGISTERS_OFFSET + 0x0004802C +#define IPU_DI1_SW_GEN1_1_OFFSET IPU_REGISTERS_OFFSET + 0x00048030 +#define IPU_DI1_SW_GEN1_2_OFFSET IPU_REGISTERS_OFFSET + 0x00048034 +#define IPU_DI1_SW_GEN1_3_OFFSET IPU_REGISTERS_OFFSET + 0x00048038 +#define IPU_DI1_SW_GEN1_4_OFFSET IPU_REGISTERS_OFFSET + 0x0004803C +#define IPU_DI1_SW_GEN1_5_OFFSET IPU_REGISTERS_OFFSET + 0x00048040 +#define IPU_DI1_SW_GEN1_6_OFFSET IPU_REGISTERS_OFFSET + 0x00048044 +#define IPU_DI1_SW_GEN1_7_OFFSET IPU_REGISTERS_OFFSET + 0x00048048 +#define IPU_DI1_SW_GEN1_8_OFFSET IPU_REGISTERS_OFFSET + 0x0004804C +#define IPU_DI1_SW_GEN1_9_OFFSET IPU_REGISTERS_OFFSET + 0x00048050 +#define IPU_DI1_SYNC_AS_GEN_OFFSET IPU_REGISTERS_OFFSET + 0x00048054 +#define IPU_DI1_DW_GEN_0_OFFSET IPU_REGISTERS_OFFSET + 0x00048058 +#define IPU_DI1_DW_GEN_1_OFFSET IPU_REGISTERS_OFFSET + 0x0004805C +#define IPU_DI1_DW_GEN_2_OFFSET IPU_REGISTERS_OFFSET + 0x00048060 +#define IPU_DI1_DW_GEN_3_OFFSET IPU_REGISTERS_OFFSET + 0x00048064 +#define IPU_DI1_DW_GEN_4_OFFSET IPU_REGISTERS_OFFSET + 0x00048068 +#define IPU_DI1_DW_GEN_5_OFFSET IPU_REGISTERS_OFFSET + 0x0004806C +#define IPU_DI1_DW_GEN_6_OFFSET IPU_REGISTERS_OFFSET + 0x00048070 +#define IPU_DI1_DW_GEN_7_OFFSET IPU_REGISTERS_OFFSET + 0x00048074 +#define IPU_DI1_DW_GEN_8_OFFSET IPU_REGISTERS_OFFSET + 0x00048078 +#define IPU_DI1_DW_GEN_9_OFFSET IPU_REGISTERS_OFFSET + 0x0004807C +#define IPU_DI1_DW_GEN_10_OFFSET IPU_REGISTERS_OFFSET + 0x00048080 +#define IPU_DI1_DW_GEN_11_OFFSET IPU_REGISTERS_OFFSET + 0x00048084 +#define IPU_DI1_DW_SET0_0_OFFSET IPU_REGISTERS_OFFSET + 0x00048088 +#define IPU_DI1_DW_SET0_1_OFFSET IPU_REGISTERS_OFFSET + 0x0004808C +#define IPU_DI1_DW_SET0_2_OFFSET IPU_REGISTERS_OFFSET + 0x00048090 +#define IPU_DI1_DW_SET0_3_OFFSET IPU_REGISTERS_OFFSET + 0x00048094 +#define IPU_DI1_DW_SET0_4_OFFSET IPU_REGISTERS_OFFSET + 0x00048098 +#define IPU_DI1_DW_SET0_5_OFFSET IPU_REGISTERS_OFFSET + 0x0004809C +#define IPU_DI1_DW_SET0_6_OFFSET IPU_REGISTERS_OFFSET + 0x000480A0 +#define IPU_DI1_DW_SET0_7_OFFSET IPU_REGISTERS_OFFSET + 0x000480A4 +#define IPU_DI1_DW_SET0_8_OFFSET IPU_REGISTERS_OFFSET + 0x000480A8 +#define IPU_DI1_DW_SET0_9_OFFSET IPU_REGISTERS_OFFSET + 0x000480AC +#define IPU_DI1_DW_SET0_10_OFFSET IPU_REGISTERS_OFFSET + 0x000480B0 +#define IPU_DI1_DW_SET0_11_OFFSET IPU_REGISTERS_OFFSET + 0x000480B4 +#define IPU_DI1_DW_SET1_0_OFFSET IPU_REGISTERS_OFFSET + 0x000480B8 +#define IPU_DI1_DW_SET1_1_OFFSET IPU_REGISTERS_OFFSET + 0x000480BC +#define IPU_DI1_DW_SET1_2_OFFSET IPU_REGISTERS_OFFSET + 0x000480C0 +#define IPU_DI1_DW_SET1_3_OFFSET IPU_REGISTERS_OFFSET + 0x000480C4 +#define IPU_DI1_DW_SET1_4_OFFSET IPU_REGISTERS_OFFSET + 0x000480C8 +#define IPU_DI1_DW_SET1_5_OFFSET IPU_REGISTERS_OFFSET + 0x000480CC +#define IPU_DI1_DW_SET1_6_OFFSET IPU_REGISTERS_OFFSET + 0x000480D0 +#define IPU_DI1_DW_SET1_7_OFFSET IPU_REGISTERS_OFFSET + 0x000480D4 +#define IPU_DI1_DW_SET1_8_OFFSET IPU_REGISTERS_OFFSET + 0x000480D8 +#define IPU_DI1_DW_SET1_9_OFFSET IPU_REGISTERS_OFFSET + 0x000480DC +#define IPU_DI1_DW_SET1_10_OFFSET IPU_REGISTERS_OFFSET + 0x000480E0 +#define IPU_DI1_DW_SET1_11_OFFSET IPU_REGISTERS_OFFSET + 0x000480E4 +#define IPU_DI1_DW_SET2_0_OFFSET IPU_REGISTERS_OFFSET + 0x000480E8 +#define IPU_DI1_DW_SET2_1_OFFSET IPU_REGISTERS_OFFSET + 0x000480EC +#define IPU_DI1_DW_SET2_2_OFFSET IPU_REGISTERS_OFFSET + 0x000480F0 +#define IPU_DI1_DW_SET2_3_OFFSET IPU_REGISTERS_OFFSET + 0x000480F4 +#define IPU_DI1_DW_SET2_4_OFFSET IPU_REGISTERS_OFFSET + 0x000480F8 +#define IPU_DI1_DW_SET2_5_OFFSET IPU_REGISTERS_OFFSET + 0x000480FC +#define IPU_DI1_DW_SET2_6_OFFSET IPU_REGISTERS_OFFSET + 0x00048100 +#define IPU_DI1_DW_SET2_7_OFFSET IPU_REGISTERS_OFFSET + 0x00048104 +#define IPU_DI1_DW_SET2_8_OFFSET IPU_REGISTERS_OFFSET + 0x00048108 +#define IPU_DI1_DW_SET2_9_OFFSET IPU_REGISTERS_OFFSET + 0x0004810C +#define IPU_DI1_DW_SET2_10_OFFSET IPU_REGISTERS_OFFSET + 0x00048110 +#define IPU_DI1_DW_SET2_11_OFFSET IPU_REGISTERS_OFFSET + 0x00048114 +#define IPU_DI1_DW_SET3_0_OFFSET IPU_REGISTERS_OFFSET + 0x00048118 +#define IPU_DI1_DW_SET3_1_OFFSET IPU_REGISTERS_OFFSET + 0x0004811C +#define IPU_DI1_DW_SET3_2_OFFSET IPU_REGISTERS_OFFSET + 0x00048120 +#define IPU_DI1_DW_SET3_3_OFFSET IPU_REGISTERS_OFFSET + 0x00048124 +#define IPU_DI1_DW_SET3_4_OFFSET IPU_REGISTERS_OFFSET + 0x00048128 +#define IPU_DI1_DW_SET3_5_OFFSET IPU_REGISTERS_OFFSET + 0x0004812C +#define IPU_DI1_DW_SET3_6_OFFSET IPU_REGISTERS_OFFSET + 0x00048130 +#define IPU_DI1_DW_SET3_7_OFFSET IPU_REGISTERS_OFFSET + 0x00048134 +#define IPU_DI1_DW_SET3_8_OFFSET IPU_REGISTERS_OFFSET + 0x00048138 +#define IPU_DI1_DW_SET3_9_OFFSET IPU_REGISTERS_OFFSET + 0x0004813C +#define IPU_DI1_DW_SET3_10_OFFSET IPU_REGISTERS_OFFSET + 0x00048140 +#define IPU_DI1_DW_SET3_11_OFFSET IPU_REGISTERS_OFFSET + 0x00048144 +#define IPU_DI1_STP_REP_1_OFFSET IPU_REGISTERS_OFFSET + 0x00048148 +#define IPU_DI1_STP_REP_2_OFFSET IPU_REGISTERS_OFFSET + 0x0004814C +#define IPU_DI1_STP_REP_3_OFFSET IPU_REGISTERS_OFFSET + 0x00048150 +#define IPU_DI1_STP_REP_4_OFFSET IPU_REGISTERS_OFFSET + 0x00048154 +#define IPU_DI1_STP_REP_9_OFFSET IPU_REGISTERS_OFFSET + 0x00048158 +#define IPU_DI1_SER_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x0004815C +#define IPU_DI1_SSC_OFFSET IPU_REGISTERS_OFFSET + 0x00048160 +#define IPU_DI1_POL_OFFSET IPU_REGISTERS_OFFSET + 0x00048164 +#define IPU_DI1_AW0_OFFSET IPU_REGISTERS_OFFSET + 0x00048168 +#define IPU_DI1_AW1_OFFSET IPU_REGISTERS_OFFSET + 0x0004816C +#define IPU_SMFC_MAP_OFFSET IPU_REGISTERS_OFFSET + 0x00050000 +#define IPU_SMFC_WMC_OFFSET IPU_REGISTERS_OFFSET + 0x00050004 +#define IPU_SMFC_BS_OFFSET IPU_REGISTERS_OFFSET + 0x00050008 +#define IPU_DC_READ_CH_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x00058000 +#define IPU_DC_READ_CH_ADDR_OFFSET IPU_REGISTERS_OFFSET + 0x00058004 +#define IPU_DC_RL0_CH_0_OFFSET IPU_REGISTERS_OFFSET + 0x00058008 +#define IPU_DC_RL1_CH_0_OFFSET IPU_REGISTERS_OFFSET + 0x0005800C +#define IPU_DC_RL2_CH_0_OFFSET IPU_REGISTERS_OFFSET + 0x00058010 +#define IPU_DC_RL3_CH_0_OFFSET IPU_REGISTERS_OFFSET + 0x00058014 +#define IPU_DC_RL4_CH_0_OFFSET IPU_REGISTERS_OFFSET + 0x00058018 +#define IPU_DC_WR_CH_CONF_1_OFFSET IPU_REGISTERS_OFFSET + 0x0005801C +#define IPU_DC_WR_CH_ADDR_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058020 +#define IPU_DC_RL0_CH_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058024 +#define IPU_DC_RL1_CH_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058028 +#define IPU_DC_RL2_CH_1_OFFSET IPU_REGISTERS_OFFSET + 0x0005802C +#define IPU_DC_RL3_CH_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058030 +#define IPU_DC_RL4_CH_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058034 +#define IPU_DC_WR_CH_CONF_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058038 +#define IPU_DC_WR_CH_ADDR_2_OFFSET IPU_REGISTERS_OFFSET + 0x0005803C +#define IPU_DC_RL0_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058040 +#define IPU_DC_RL1_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058044 +#define IPU_DC_RL2_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058048 +#define IPU_DC_RL3_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x0005804C +#define IPU_DC_RL4_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058050 +#define IPU_DC_CMD_CH_CONF_3_OFFSET IPU_REGISTERS_OFFSET + 0x00058054 +#define IPU_DC_CMD_CH_CONF_4_OFFSET IPU_REGISTERS_OFFSET + 0x00058058 +#define IPU_DC_WR_CH_CONF_5_OFFSET IPU_REGISTERS_OFFSET + 0x0005805C +#define IPU_DC_WR_CH_ADDR_5_OFFSET IPU_REGISTERS_OFFSET + 0x00058060 +#define IPU_DC_RL0_CH_5_OFFSET IPU_REGISTERS_OFFSET + 0x00058064 +#define IPU_DC_RL1_CH_5_OFFSET IPU_REGISTERS_OFFSET + 0x00058068 +#define IPU_DC_RL2_CH_5_OFFSET IPU_REGISTERS_OFFSET + 0x0005806C +#define IPU_DC_RL3_CH_5_OFFSET IPU_REGISTERS_OFFSET + 0x00058070 +#define IPU_DC_RL4_CH_5_OFFSET IPU_REGISTERS_OFFSET + 0x00058074 +#define IPU_DC_WR_CH_CONF_6_OFFSET IPU_REGISTERS_OFFSET + 0x00058078 +#define IPU_DC_WR_CH_ADDR_6_OFFSET IPU_REGISTERS_OFFSET + 0x0005807C +#define IPU_DC_RL0_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x00058080 +#define IPU_DC_RL1_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x00058084 +#define IPU_DC_RL2_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x00058088 +#define IPU_DC_RL3_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x0005808C +#define IPU_DC_RL4_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x00058090 +#define IPU_DC_WR_CH_CONF1_8_OFFSET IPU_REGISTERS_OFFSET + 0x00058094 +#define IPU_DC_WR_CH_CONF2_8_OFFSET IPU_REGISTERS_OFFSET + 0x00058098 +#define IPU_DC_RL1_CH_8_OFFSET IPU_REGISTERS_OFFSET + 0x0005809C +#define IPU_DC_RL2_CH_8_OFFSET IPU_REGISTERS_OFFSET + 0x000580A0 +#define IPU_DC_RL3_CH_8_OFFSET IPU_REGISTERS_OFFSET + 0x000580A4 +#define IPU_DC_RL4_CH_8_OFFSET IPU_REGISTERS_OFFSET + 0x000580A8 +#define IPU_DC_RL5_CH_8_OFFSET IPU_REGISTERS_OFFSET + 0x000580AC +#define IPU_DC_RL6_CH_8_OFFSET IPU_REGISTERS_OFFSET + 0x000580B0 +#define IPU_DC_WR_CH_CONF1_9_OFFSET IPU_REGISTERS_OFFSET + 0x000580B4 +#define IPU_DC_WR_CH_CONF2_9_OFFSET IPU_REGISTERS_OFFSET + 0x000580B8 +#define IPU_DC_RL1_CH_9_OFFSET IPU_REGISTERS_OFFSET + 0x000580BC +#define IPU_DC_RL2_CH_9_OFFSET IPU_REGISTERS_OFFSET + 0x000580C0 +#define IPU_DC_RL3_CH_9_OFFSET IPU_REGISTERS_OFFSET + 0x000580C4 +#define IPU_DC_RL4_CH_9_OFFSET IPU_REGISTERS_OFFSET + 0x000580C8 +#define IPU_DC_RL5_CH_9_OFFSET IPU_REGISTERS_OFFSET + 0x000580CC +#define IPU_DC_RL6_CH_9_OFFSET IPU_REGISTERS_OFFSET + 0x000580D0 +#define IPU_DC_GEN_OFFSET IPU_REGISTERS_OFFSET + 0x000580D4 +#define IPU_DC_DISP_CONF1_0_OFFSET IPU_REGISTERS_OFFSET + 0x000580D8 +#define IPU_DC_DISP_CONF1_1_OFFSET IPU_REGISTERS_OFFSET + 0x000580DC +#define IPU_DC_DISP_CONF1_2_OFFSET IPU_REGISTERS_OFFSET + 0x000580E0 +#define IPU_DC_DISP_CONF1_3_OFFSET IPU_REGISTERS_OFFSET + 0x000580E4 +#define IPU_DC_DISP_CONF2_0_OFFSET IPU_REGISTERS_OFFSET + 0x000580E8 +#define IPU_DC_DISP_CONF2_1_OFFSET IPU_REGISTERS_OFFSET + 0x000580EC +#define IPU_DC_DISP_CONF2_2_OFFSET IPU_REGISTERS_OFFSET + 0x000580F0 +#define IPU_DC_DISP_CONF2_3_OFFSET IPU_REGISTERS_OFFSET + 0x000580F4 +#define IPU_DC_DI0_CONF_0_OFFSET IPU_REGISTERS_OFFSET + 0x000580F8 +#define IPU_DC_DI0_CONF_1_OFFSET IPU_REGISTERS_OFFSET + 0x000580FC +#define IPU_DC_DI0_CONF_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058100 +#define IPU_DC_DI1_CONF_0_OFFSET IPU_REGISTERS_OFFSET + 0x00058104 +#define IPU_DC_DI1_CONF_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058108 +#define IPU_DC_DI1_CONF_2_OFFSET IPU_REGISTERS_OFFSET + 0x0005810C +#define IPU_DC_MAP_CONF_0_OFFSET IPU_REGISTERS_OFFSET + 0x00058110 +#define IPU_DC_MAP_CONF_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058114 +#define IPU_DC_MAP_CONF_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058118 +#define IPU_DC_MAP_CONF_3_OFFSET IPU_REGISTERS_OFFSET + 0x0005811C +#define IPU_DC_MAP_CONF_4_OFFSET IPU_REGISTERS_OFFSET + 0x00058120 +#define IPU_DC_MAP_CONF_5_OFFSET IPU_REGISTERS_OFFSET + 0x00058124 +#define IPU_DC_MAP_CONF_6_OFFSET IPU_REGISTERS_OFFSET + 0x00058128 +#define IPU_DC_MAP_CONF_7_OFFSET IPU_REGISTERS_OFFSET + 0x0005812C +#define IPU_DC_MAP_CONF_8_OFFSET IPU_REGISTERS_OFFSET + 0x00058130 +#define IPU_DC_MAP_CONF_9_OFFSET IPU_REGISTERS_OFFSET + 0x00058134 +#define IPU_DC_MAP_CONF_10_OFFSET IPU_REGISTERS_OFFSET + 0x00058138 +#define IPU_DC_MAP_CONF_11_OFFSET IPU_REGISTERS_OFFSET + 0x0005813C +#define IPU_DC_MAP_CONF_12_OFFSET IPU_REGISTERS_OFFSET + 0x00058140 +#define IPU_DC_MAP_CONF_13_OFFSET IPU_REGISTERS_OFFSET + 0x00058144 +#define IPU_DC_MAP_CONF_14_OFFSET IPU_REGISTERS_OFFSET + 0x00058148 +#define IPU_DC_MAP_CONF_15_OFFSET IPU_REGISTERS_OFFSET + 0x0005814C +#define IPU_DC_MAP_CONF_16_OFFSET IPU_REGISTERS_OFFSET + 0x00058150 +#define IPU_DC_MAP_CONF_17_OFFSET IPU_REGISTERS_OFFSET + 0x00058154 +#define IPU_DC_MAP_CONF_18_OFFSET IPU_REGISTERS_OFFSET + 0x00058158 +#define IPU_DC_MAP_CONF_19_OFFSET IPU_REGISTERS_OFFSET + 0x0005815C +#define IPU_DC_MAP_CONF_20_OFFSET IPU_REGISTERS_OFFSET + 0x00058160 +#define IPU_DC_MAP_CONF_21_OFFSET IPU_REGISTERS_OFFSET + 0x00058164 +#define IPU_DC_MAP_CONF_22_OFFSET IPU_REGISTERS_OFFSET + 0x00058168 +#define IPU_DC_MAP_CONF_23_OFFSET IPU_REGISTERS_OFFSET + 0x0005816C +#define IPU_DC_MAP_CONF_24_OFFSET IPU_REGISTERS_OFFSET + 0x00058170 +#define IPU_DC_MAP_CONF_25_OFFSET IPU_REGISTERS_OFFSET + 0x00058174 +#define IPU_DC_MAP_CONF_26_OFFSET IPU_REGISTERS_OFFSET + 0x00058178 +#define IPU_DC_UGDE0_0_OFFSET IPU_REGISTERS_OFFSET + 0x0005817C +#define IPU_DC_UGDE0_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058180 +#define IPU_DC_UGDE0_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058184 +#define IPU_DC_UGDE0_3_OFFSET IPU_REGISTERS_OFFSET + 0x00058188 +#define IPU_DC_UGDE1_0_OFFSET IPU_REGISTERS_OFFSET + 0x0005818C +#define IPU_DC_UGDE1_1_OFFSET IPU_REGISTERS_OFFSET + 0x00058190 +#define IPU_DC_UGDE1_2_OFFSET IPU_REGISTERS_OFFSET + 0x00058194 +#define IPU_DC_UGDE1_3_OFFSET IPU_REGISTERS_OFFSET + 0x00058198 +#define IPU_DC_UGDE2_0_OFFSET IPU_REGISTERS_OFFSET + 0x0005819C +#define IPU_DC_UGDE2_1_OFFSET IPU_REGISTERS_OFFSET + 0x000581A0 +#define IPU_DC_UGDE2_2_OFFSET IPU_REGISTERS_OFFSET + 0x000581A4 +#define IPU_DC_UGDE2_3_OFFSET IPU_REGISTERS_OFFSET + 0x000581A8 +#define IPU_DC_UGDE3_0_OFFSET IPU_REGISTERS_OFFSET + 0x000581AC +#define IPU_DC_UGDE3_1_OFFSET IPU_REGISTERS_OFFSET + 0x000581B0 +#define IPU_DC_UGDE3_2_OFFSET IPU_REGISTERS_OFFSET + 0x000581B4 +#define IPU_DC_UGDE3_3_OFFSET IPU_REGISTERS_OFFSET + 0x000581B8 +#define IPU_DC_LLA0_OFFSET IPU_REGISTERS_OFFSET + 0x000581BC +#define IPU_DC_LLA1_OFFSET IPU_REGISTERS_OFFSET + 0x000581C0 +#define IPU_DC_WR_CH_ADDR_5_ALT_OFFSET IPU_REGISTERS_OFFSET + 0x000581C4 +#define IPU_DMFC_RD_CHAN_OFFSET IPU_REGISTERS_OFFSET + 0x00060000 +#define IPU_DMFC_WR_CHAN_OFFSET IPU_REGISTERS_OFFSET + 0x00060004 +#define IPU_DMFC_WR_CHAN_DEF_OFFSET IPU_REGISTERS_OFFSET + 0x00060008 +#define IPU_DMFC_DP_CHAN_OFFSET IPU_REGISTERS_OFFSET + 0x0006000C +#define IPU_DMFC_DP_CHAN_DEF_OFFSET IPU_REGISTERS_OFFSET + 0x00060010 +#define IPU_DMFC_GENERAL1_OFFSET IPU_REGISTERS_OFFSET + 0x00060014 +#define IPU_DMFC_GENERAL2_OFFSET IPU_REGISTERS_OFFSET + 0x00060018 +#define IPU_DMFC_IC_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x0006001C +#define CPMEM_WORD0_DATA0_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000000 +#define CPMEM_WORD0_DATA1_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000004 +#define CPMEM_WORD0_DATA2_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000008 +#define CPMEM_WORD0_DATA3_INT_OFFSET IPU_REGISTERS_OFFSET + 0x0100000C +#define CPMEM_WORD0_DATA4_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000010 +#define CPMEM_WORD0_DATA0_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000000 +#define CPMEM_WORD0_DATA1_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000004 +#define CPMEM_WORD0_DATA2_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000008 +#define CPMEM_WORD0_DATA3_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x0100000C +#define CPMEM_WORD0_DATA4_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000010 +#define CPMEM_WORD1_DATA0_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000020 +#define CPMEM_WORD1_DATA1_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000024 +#define CPMEM_WORD1_DATA2_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000028 +#define CPMEM_WORD1_DATA3_INT_OFFSET IPU_REGISTERS_OFFSET + 0x0100002C +#define CPMEM_WORD1_DATA4_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000030 +#define CPMEM_WORD1_DATA0_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000020 +#define CPMEM_WORD1_DATA1_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000024 +#define CPMEM_WORD1_DATA2_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000028 +#define CPMEM_WORD1_DATA3_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x0100002C +#define CPMEM_WORD1_DATA4_N_INT_OFFSET IPU_REGISTERS_OFFSET + 0x01000030 +#define IPU_IC_TPMEM_ENC_CSC1_WORD0_OFFSET IPU_REGISTERS_OFFSET + 0x01061688 +#define IPU_IC_TPMEM_ENC_CSC1_WORD1_OFFSET IPU_REGISTERS_OFFSET + 0x0106168C +#define IPU_IC_TPMEM_ENC_CSC1_WORD2_OFFSET IPU_REGISTERS_OFFSET + 0x01061690 +#define IPU_IC_TPMEM_ENC_CSC1_WORD3_OFFSET IPU_REGISTERS_OFFSET + 0x01061694 +#define IPU_IC_TPMEM_ENC_CSC1_WORD4_OFFSET IPU_REGISTERS_OFFSET + 0x01061698 +#define IPU_IC_TPMEM_ENC_CSC1_WORD5_OFFSET IPU_REGISTERS_OFFSET + 0x0106169c +#define IPU_IC_TPMEM_VIEW_CSC1_WORD0_OFFSET IPU_REGISTERS_OFFSET + 0x01062D28 +#define IPU_IC_TPMEM_VIEW_CSC1_WORD1_OFFSET IPU_REGISTERS_OFFSET + 0x01062D2C +#define IPU_IC_TPMEM_VIEW_CSC1_WORD2_OFFSET IPU_REGISTERS_OFFSET + 0x01062D30 +#define IPU_IC_TPMEM_VIEW_CSC1_WORD3_OFFSET IPU_REGISTERS_OFFSET + 0x01062D34 +#define IPU_IC_TPMEM_VIEW_CSC1_WORD4_OFFSET IPU_REGISTERS_OFFSET + 0x01062D38 +#define IPU_IC_TPMEM_VIEW_CSC1_WORD5_OFFSET IPU_REGISTERS_OFFSET + 0x01062D3C +#define IPU_IC_TPMEM_VIEW_CSC2_WORD0_OFFSET IPU_REGISTERS_OFFSET + 0x01062D40 +#define IPU_IC_TPMEM_VIEW_CSC2_WORD1_OFFSET IPU_REGISTERS_OFFSET + 0x01062D44 +#define IPU_IC_TPMEM_VIEW_CSC2_WORD2_OFFSET IPU_REGISTERS_OFFSET + 0x01062D48 +#define IPU_IC_TPMEM_VIEW_CSC2_WORD3_OFFSET IPU_REGISTERS_OFFSET + 0x01062D4C +#define IPU_IC_TPMEM_VIEW_CSC2_WORD4_OFFSET IPU_REGISTERS_OFFSET + 0x01062D50 +#define IPU_IC_TPMEM_VIEW_CSC2_WORD5_OFFSET IPU_REGISTERS_OFFSET + 0x01062D54 +#define IPU_IC_TPMEM_POST_CSC1_WORD0_OFFSET IPU_REGISTERS_OFFSET + 0x010643E0 +#define IPU_IC_TPMEM_POST_CSC1_WORD1_OFFSET IPU_REGISTERS_OFFSET + 0x010643E4 +#define IPU_IC_TPMEM_POST_CSC1_WORD2_OFFSET IPU_REGISTERS_OFFSET + 0x010643E8 +#define IPU_IC_TPMEM_POST_CSC1_WORD3_OFFSET IPU_REGISTERS_OFFSET + 0x010643EC +#define IPU_IC_TPMEM_POST_CSC1_WORD4_OFFSET IPU_REGISTERS_OFFSET + 0x010643F0 +#define IPU_IC_TPMEM_POST_CSC1_WORD5_OFFSET IPU_REGISTERS_OFFSET + 0x010643F4 +#define IPU_IC_TPMEM_POST_CSC2_WORD0_OFFSET IPU_REGISTERS_OFFSET + 0x010643F8 +#define IPU_IC_TPMEM_POST_CSC2_WORD1_OFFSET IPU_REGISTERS_OFFSET + 0x010643FC +#define IPU_IC_TPMEM_POST_CSC2_WORD2_OFFSET IPU_REGISTERS_OFFSET + 0x01064400 +#define IPU_IC_TPMEM_POST_CSC2_WORD3_OFFSET IPU_REGISTERS_OFFSET + 0x01064404 +#define IPU_IC_TPMEM_POST_CSC2_WORD4_OFFSET IPU_REGISTERS_OFFSET + 0x01064408 +#define IPU_IC_TPMEM_POST_CSC2_WORD5_OFFSET IPU_REGISTERS_OFFSET + 0x0106440C +#define SRM_DP_COM_CONF_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x01040000 +#define SRM_DP_GRAPH_WIND_CTRL_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x01040004 +#define SRM_DP_FG_POS_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x01040008 +#define SRM_DP_CUR_POS_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x0104000C +#define SRM_DP_CUR_MAP_SYNC_OFFSET IPU_REGISTERS_OFFSET + 0x01040010 +#define SRM_DP_GAMMA_C_SYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040014 +#define SRM_DP_GAMMA_C_SYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040018 +#define SRM_DP_GAMMA_C_SYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104001C +#define SRM_DP_GAMMA_C_SYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040020 +#define SRM_DP_GAMMA_C_SYNC_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040024 +#define SRM_DP_GAMMA_C_SYNC_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040028 +#define SRM_DP_GAMMA_C_SYNC_6_OFFSET IPU_REGISTERS_OFFSET + 0x0104002C +#define SRM_DP_GAMMA_C_SYNC_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040030 +#define SRM_DP_GAMMA_S_SYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040034 +#define SRM_DP_GAMMA_S_SYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040038 +#define SRM_DP_GAMMA_S_SYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104003C +#define SRM_DP_GAMMA_S_SYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040040 +#define SRM_DP_CSCA_SYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040044 +#define SRM_DP_CSCA_SYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040048 +#define SRM_DP_CSCA_SYNC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104004C +#define SRM_DP_CSCA_SYNC_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040050 +#define SRM_DP_CSC_SYNC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040054 +#define SRM_DP_CSC_SYNC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040058 +#define SRM_DP_COM_CONF_ASYNC0_OFFSET IPU_REGISTERS_OFFSET + 0x0104005C +#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0_OFFSET IPU_REGISTERS_OFFSET + 0x01040060 +#define SRM_DP_FG_POS_ASYNC0_OFFSET IPU_REGISTERS_OFFSET + 0x01040064 +#define SRM_DP_CUR_POS_ASYNC0_OFFSET IPU_REGISTERS_OFFSET + 0x01040068 +#define SRM_DP_CUR_MAP_ASYNC0_OFFSET IPU_REGISTERS_OFFSET + 0x0104006C +#define SRM_DP_GAMMA_C_ASYNC0_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040070 +#define SRM_DP_GAMMA_C_ASYNC0_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040074 +#define SRM_DP_GAMMA_C_ASYNC0_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040078 +#define SRM_DP_GAMMA_C_ASYNC0_3_OFFSET IPU_REGISTERS_OFFSET + 0x0104007C +#define SRM_DP_GAMMA_C_ASYNC0_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040080 +#define SRM_DP_GAMMA_C_ASYNC0_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040084 +#define SRM_DP_GAMMA_C_ASYNC0_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040088 +#define SRM_DP_GAMMA_C_ASYNC0_7_OFFSET IPU_REGISTERS_OFFSET + 0x0104008C +#define SRM_DP_GAMMA_S_ASYNC0_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040090 +#define SRM_DP_GAMMA_S_ASYNC0_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040094 +#define SRM_DP_GAMMA_S_ASYNC0_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040098 +#define SRM_DP_GAMMA_S_ASYNC0_3_OFFSET IPU_REGISTERS_OFFSET + 0x0104009C +#define SRM_DP_CSCA_ASYNC0_0_OFFSET IPU_REGISTERS_OFFSET + 0x010400A0 +#define SRM_DP_CSCA_ASYNC0_1_OFFSET IPU_REGISTERS_OFFSET + 0x010400A4 +#define SRM_DP_CSCA_ASYNC0_2_OFFSET IPU_REGISTERS_OFFSET + 0x010400A8 +#define SRM_DP_CSCA_ASYNC0_3_OFFSET IPU_REGISTERS_OFFSET + 0x010400AC +#define SRM_DP_CSC_ASYNC0_0_OFFSET IPU_REGISTERS_OFFSET + 0x010400B0 +#define SRM_DP_CSC_ASYNC0_1_OFFSET IPU_REGISTERS_OFFSET + 0x010400B4 +#define SRM_DP_COM_CONF_ASYNC1_OFFSET IPU_REGISTERS_OFFSET + 0x010400B8 +#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1_OFFSET IPU_REGISTERS_OFFSET + 0x010400BC +#define SRM_DP_FG_POS_ASYNC1_OFFSET IPU_REGISTERS_OFFSET + 0x010400C0 +#define SRM_DP_CUR_POS_ASYNC1_OFFSET IPU_REGISTERS_OFFSET + 0x010400C4 +#define SRM_DP_CUR_MAP_ASYNC1_OFFSET IPU_REGISTERS_OFFSET + 0x010400C8 +#define SRM_DP_GAMMA_C_ASYNC1_0_OFFSET IPU_REGISTERS_OFFSET + 0x010400CC +#define SRM_DP_GAMMA_C_ASYNC1_1_OFFSET IPU_REGISTERS_OFFSET + 0x010400D0 +#define SRM_DP_GAMMA_C_ASYNC1_2_OFFSET IPU_REGISTERS_OFFSET + 0x010400D4 +#define SRM_DP_GAMMA_C_ASYNC1_3_OFFSET IPU_REGISTERS_OFFSET + 0x010400D8 +#define SRM_DP_GAMMA_C_ASYNC1_4_OFFSET IPU_REGISTERS_OFFSET + 0x010400DC +#define SRM_DP_GAMMA_C_ASYNC1_5_OFFSET IPU_REGISTERS_OFFSET + 0x010400E0 +#define SRM_DP_GAMMA_C_ASYNC1_6_OFFSET IPU_REGISTERS_OFFSET + 0x010400E4 +#define SRM_DP_GAMMA_C_ASYNC1_7_OFFSET IPU_REGISTERS_OFFSET + 0x010400E8 +#define SRM_DP_GAMMA_S_ASYNC1_0_OFFSET IPU_REGISTERS_OFFSET + 0x010400EC +#define SRM_DP_GAMMA_S_ASYNC1_1_OFFSET IPU_REGISTERS_OFFSET + 0x010400F0 +#define SRM_DP_GAMMA_S_ASYNC1_2_OFFSET IPU_REGISTERS_OFFSET + 0x010400F4 +#define SRM_DP_GAMMA_S_ASYNC1_3_OFFSET IPU_REGISTERS_OFFSET + 0x010400F8 +#define SRM_DP_CSCA_ASYNC1_0_OFFSET IPU_REGISTERS_OFFSET + 0x010400FC +#define SRM_DP_CSCA_ASYNC1_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040100 +#define SRM_DP_CSCA_ASYNC1_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040104 +#define SRM_DP_CSCA_ASYNC1_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040108 +#define SRM_DP_CSC_ASYNC1_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104010C +#define SRM_DP_CSC_ASYNC1_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040110 +#define SRM_ISP_C0_OFFSET IPU_REGISTERS_OFFSET + 0x01040114 +#define SRM_ISP_C1_OFFSET IPU_REGISTERS_OFFSET + 0x01040118 +#define SRM_ISP_FS_OFFSET IPU_REGISTERS_OFFSET + 0x0104011C +#define SRM_ISP_BI_OFFSET IPU_REGISTERS_OFFSET + 0x01040120 +#define SRM_ISP_OCO_OFFSET IPU_REGISTERS_OFFSET + 0x01040128 +#define SRM_ISP_BPR1_OFFSET IPU_REGISTERS_OFFSET + 0x01040128 +#define SRM_ISP_BPR2_OFFSET IPU_REGISTERS_OFFSET + 0x0104012C +#define SRM_ISP_BPR3_OFFSET IPU_REGISTERS_OFFSET + 0x01040130 +#define SRM_ISP_CG_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040134 +#define SRM_ISP_CG_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040138 +#define SRM_ISP_ROC_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104013C +#define SRM_ISP_ROC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040140 +#define SRM_ISP_ROC_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040144 +#define SRM_ISP_RRO_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040148 +#define SRM_ISP_RRO_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104014C +#define SRM_ISP_RRO_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040150 +#define SRM_ISP_RRO_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040154 +#define SRM_ISP_RRO_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040158 +#define SRM_ISP_RRO_5_OFFSET IPU_REGISTERS_OFFSET + 0x0104015C +#define SRM_ISP_RRO_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040160 +#define SRM_ISP_RRO_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040164 +#define SRM_ISP_GRO_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040168 +#define SRM_ISP_GRO_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104016C +#define SRM_ISP_GRO_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040170 +#define SRM_ISP_GRO_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040174 +#define SRM_ISP_GRO_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040178 +#define SRM_ISP_GRO_5_OFFSET IPU_REGISTERS_OFFSET + 0x0104017C +#define SRM_ISP_GRO_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040180 +#define SRM_ISP_GRO_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040184 +#define SRM_ISP_BRO_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040188 +#define SRM_ISP_BRO_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104018C +#define SRM_ISP_BRO_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040190 +#define SRM_ISP_BRO_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040194 +#define SRM_ISP_BRO_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040198 +#define SRM_ISP_BRO_5_OFFSET IPU_REGISTERS_OFFSET + 0x0104019C +#define SRM_ISP_BRO_6_OFFSET IPU_REGISTERS_OFFSET + 0x010401A0 +#define SRM_ISP_BRO_7_OFFSET IPU_REGISTERS_OFFSET + 0x010401A4 +#define SRM_ISP_GAMMA_C_0_OFFSET IPU_REGISTERS_OFFSET + 0x010401A8 +#define SRM_ISP_GAMMA_C_1_OFFSET IPU_REGISTERS_OFFSET + 0x010401AC +#define SRM_ISP_GAMMA_C_2_OFFSET IPU_REGISTERS_OFFSET + 0x010401B0 +#define SRM_ISP_GAMMA_C_3_OFFSET IPU_REGISTERS_OFFSET + 0x010401B4 +#define SRM_ISP_GAMMA_C_4_OFFSET IPU_REGISTERS_OFFSET + 0x010401B8 +#define SRM_ISP_GAMMA_C_5_OFFSET IPU_REGISTERS_OFFSET + 0x010401BC +#define SRM_ISP_GAMMA_C_6_OFFSET IPU_REGISTERS_OFFSET + 0x010401C0 +#define SRM_ISP_GAMMA_C_7_OFFSET IPU_REGISTERS_OFFSET + 0x010401C4 +#define SRM_ISP_GAMMA_S_0_OFFSET IPU_REGISTERS_OFFSET + 0x010401C8 +#define SRM_ISP_GAMMA_S_1_OFFSET IPU_REGISTERS_OFFSET + 0x010401CC +#define SRM_ISP_GAMMA_S_2_OFFSET IPU_REGISTERS_OFFSET + 0x010401D0 +#define SRM_ISP_GAMMA_S_3_OFFSET IPU_REGISTERS_OFFSET + 0x010401D4 +#define SRM_ISP_CSCA_0_OFFSET IPU_REGISTERS_OFFSET + 0x010401D8 +#define SRM_ISP_CSCA_1_OFFSET IPU_REGISTERS_OFFSET + 0x010401DC +#define SRM_ISP_CSCA_2_OFFSET IPU_REGISTERS_OFFSET + 0x010401E0 +#define SRM_ISP_CSCA_3_OFFSET IPU_REGISTERS_OFFSET + 0x010401E4 +#define SRM_ISP_CSC_0_OFFSET IPU_REGISTERS_OFFSET + 0x010401E8 +#define SRM_ISP_CSC_1_OFFSET IPU_REGISTERS_OFFSET + 0x010401EC +#define SRM_ISP_CNS_C_0_OFFSET IPU_REGISTERS_OFFSET + 0x010401F0 +#define SRM_ISP_CNS_C_1_OFFSET IPU_REGISTERS_OFFSET + 0x010401F4 +#define SRM_ISP_CNS_C_2_OFFSET IPU_REGISTERS_OFFSET + 0x010401F8 +#define SRM_ISP_CNS_C_3_OFFSET IPU_REGISTERS_OFFSET + 0x010401FC +#define SRM_ISP_CNS_C_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040200 +#define SRM_ISP_CNS_C_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040204 +#define SRM_ISP_CNS_C_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040208 +#define SRM_ISP_CNS_C_7_OFFSET IPU_REGISTERS_OFFSET + 0x0104020C +#define SRM_ISP_CNS_S_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040210 +#define SRM_ISP_CNS_S_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040214 +#define SRM_ISP_CNS_S_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040218 +#define SRM_ISP_CNS_S_3_OFFSET IPU_REGISTERS_OFFSET + 0x0104021C +#define SRM_ISP_MTF_ROC_C_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040220 +#define SRM_ISP_MTF_ROC_C_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040224 +#define SRM_ISP_MTF_ROC_C_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040228 +#define SRM_ISP_MTF_ROC_C_3_OFFSET IPU_REGISTERS_OFFSET + 0x0104022C +#define SRM_ISP_MTF_ROC_S_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040230 +#define SRM_ISP_MTF_ROC_S_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040234 +#define SRM_ISP_HFE_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040238 +#define SRM_ISP_HFE_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104023C +#define SRM_ISP_HFE_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040240 +#define SRM_ISP_HFE_S_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040244 +#define SRM_ISP_HFE_S_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040248 +#define SRM_ISP_HFE_S_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104024C +#define SRM_ISP_HFE_S_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040250 +#define SRM_ISP_HFE_C_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040254 +#define SRM_ISP_HFE_C_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040258 +#define SRM_ISP_HFE_C_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104025C +#define SRM_ISP_HFE_C_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040260 +#define SRM_ISP_STC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040264 +#define SRM_ISP_STC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040268 +#define SRM_ISP_FC_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104026C +#define SRM_ISP_FC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040270 +#define SRM_CSI0_CPD_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x01040274 +#define SRM_CSI0_CPD_RC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040278 +#define SRM_CSI0_CPD_RC_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104027C +#define SRM_CSI0_CPD_RC_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040280 +#define SRM_CSI0_CPD_RC_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040284 +#define SRM_CSI0_CPD_RC_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040288 +#define SRM_CSI0_CPD_RC_5_OFFSET IPU_REGISTERS_OFFSET + 0x0104028C +#define SRM_CSI0_CPD_RC_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040290 +#define SRM_CSI0_CPD_RC_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040294 +#define SRM_CSI0_CPD_RS_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040298 +#define SRM_CSI0_CPD_RS_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104029C +#define SRM_CSI0_CPD_RS_2_OFFSET IPU_REGISTERS_OFFSET + 0x010402A0 +#define SRM_CSI0_CPD_RS_3_OFFSET IPU_REGISTERS_OFFSET + 0x010402A4 +#define SRM_CSI0_CPD_GRC_0_OFFSET IPU_REGISTERS_OFFSET + 0x010402A8 +#define SRM_CSI0_CPD_GRC_1_OFFSET IPU_REGISTERS_OFFSET + 0x010402AC +#define SRM_CSI0_CPD_GRC_2_OFFSET IPU_REGISTERS_OFFSET + 0x010402B0 +#define SRM_CSI0_CPD_GRC_3_OFFSET IPU_REGISTERS_OFFSET + 0x010402B4 +#define SRM_CSI0_CPD_GRC_4_OFFSET IPU_REGISTERS_OFFSET + 0x010402B8 +#define SRM_CSI0_CPD_GRC_5_OFFSET IPU_REGISTERS_OFFSET + 0x010402BC +#define SRM_CSI0_CPD_GRC_6_OFFSET IPU_REGISTERS_OFFSET + 0x010402C0 +#define SRM_CSI0_CPD_GRC_7_OFFSET IPU_REGISTERS_OFFSET + 0x010402C4 +#define SRM_CSI0_CPD_GRS_0_OFFSET IPU_REGISTERS_OFFSET + 0x010402C8 +#define SRM_CSI0_CPD_GRS_1_OFFSET IPU_REGISTERS_OFFSET + 0x010402CC +#define SRM_CSI0_CPD_GRS_2_OFFSET IPU_REGISTERS_OFFSET + 0x010402D0 +#define SRM_CSI0_CPD_GRS_3_OFFSET IPU_REGISTERS_OFFSET + 0x010402D4 +#define SRM_CSI0_CPD_GBC_0_OFFSET IPU_REGISTERS_OFFSET + 0x010402D8 +#define SRM_CSI0_CPD_GBC_1_OFFSET IPU_REGISTERS_OFFSET + 0x010402DC +#define SRM_CSI0_CPD_GBC_2_OFFSET IPU_REGISTERS_OFFSET + 0x010402E0 +#define SRM_CSI0_CPD_GBC_3_OFFSET IPU_REGISTERS_OFFSET + 0x010402E4 +#define SRM_CSI0_CPD_GBC_4_OFFSET IPU_REGISTERS_OFFSET + 0x010402E8 +#define SRM_CSI0_CPD_GBC_5_OFFSET IPU_REGISTERS_OFFSET + 0x010402EC +#define SRM_CSI0_CPD_GBC_6_OFFSET IPU_REGISTERS_OFFSET + 0x010402F0 +#define SRM_CSI0_CPD_GBC_7_OFFSET IPU_REGISTERS_OFFSET + 0x010402F4 +#define SRM_CSI0_CPD_GBS_0_OFFSET IPU_REGISTERS_OFFSET + 0x010402F8 +#define SRM_CSI0_CPD_GBS_1_OFFSET IPU_REGISTERS_OFFSET + 0x010402FC +#define SRM_CSI0_CPD_GBS_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040300 +#define SRM_CSI0_CPD_GBS_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040304 +#define SRM_CSI0_CPD_BC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040308 +#define SRM_CSI0_CPD_BC_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104030C +#define SRM_CSI0_CPD_BC_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040310 +#define SRM_CSI0_CPD_BC_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040314 +#define SRM_CSI0_CPD_BC_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040318 +#define SRM_CSI0_CPD_BC_5_OFFSET IPU_REGISTERS_OFFSET + 0x0104031C +#define SRM_CSI0_CPD_BC_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040320 +#define SRM_CSI0_CPD_BC_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040324 +#define SRM_CSI0_CPD_BS_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040328 +#define SRM_CSI0_CPD_BS_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104032C +#define SRM_CSI0_CPD_BS_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040330 +#define SRM_CSI0_CPD_BS_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040334 +#define SRM_CSI0_CPD_OFFSET1_OFFSET IPU_REGISTERS_OFFSET + 0x01040338 +#define SRM_CSI0_CPD_OFFSET2_OFFSET IPU_REGISTERS_OFFSET + 0x0104033C +#define SRM_CSI1_CPD_CTRL_OFFSET IPU_REGISTERS_OFFSET + 0x01040340 +#define SRM_CSI1_CPD_RC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040344 +#define SRM_CSI1_CPD_RC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040348 +#define SRM_CSI1_CPD_RC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104034C +#define SRM_CSI1_CPD_RC_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040350 +#define SRM_CSI1_CPD_RC_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040354 +#define SRM_CSI1_CPD_RC_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040358 +#define SRM_CSI1_CPD_RC_6_OFFSET IPU_REGISTERS_OFFSET + 0x0104035C +#define SRM_CSI1_CPD_RC_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040360 +#define SRM_CSI1_CPD_RS_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040364 +#define SRM_CSI1_CPD_RS_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040368 +#define SRM_CSI1_CPD_RS_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104036C +#define SRM_CSI1_CPD_RS_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040370 +#define SRM_CSI1_CPD_GRC_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040374 +#define SRM_CSI1_CPD_GRC_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040378 +#define SRM_CSI1_CPD_GRC_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104037C +#define SRM_CSI1_CPD_GRC_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040380 +#define SRM_CSI1_CPD_GRC_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040384 +#define SRM_CSI1_CPD_GRC_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040388 +#define SRM_CSI1_CPD_GRC_6_OFFSET IPU_REGISTERS_OFFSET + 0x0104038C +#define SRM_CSI1_CPD_GRC_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040390 +#define SRM_CSI1_CPD_GRS_0_OFFSET IPU_REGISTERS_OFFSET + 0x01040394 +#define SRM_CSI1_CPD_GRS_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040398 +#define SRM_CSI1_CPD_GRS_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104039C +#define SRM_CSI1_CPD_GRS_3_OFFSET IPU_REGISTERS_OFFSET + 0x010403A0 +#define SRM_CSI1_CPD_GBC_0_OFFSET IPU_REGISTERS_OFFSET + 0x010403A4 +#define SRM_CSI1_CPD_GBC_1_OFFSET IPU_REGISTERS_OFFSET + 0x010403A8 +#define SRM_CSI1_CPD_GBC_2_OFFSET IPU_REGISTERS_OFFSET + 0x010403AC +#define SRM_CSI1_CPD_GBC_3_OFFSET IPU_REGISTERS_OFFSET + 0x010403B0 +#define SRM_CSI1_CPD_GBC_4_OFFSET IPU_REGISTERS_OFFSET + 0x010403B4 +#define SRM_CSI1_CPD_GBC_5_OFFSET IPU_REGISTERS_OFFSET + 0x010403B8 +#define SRM_CSI1_CPD_GBC_6_OFFSET IPU_REGISTERS_OFFSET + 0x010403BC +#define SRM_CSI1_CPD_GBC_7_OFFSET IPU_REGISTERS_OFFSET + 0x010403C0 +#define SRM_CSI1_CPD_GBS_0_OFFSET IPU_REGISTERS_OFFSET + 0x010403C4 +#define SRM_CSI1_CPD_GBS_1_OFFSET IPU_REGISTERS_OFFSET + 0x010403C8 +#define SRM_CSI1_CPD_GBS_2_OFFSET IPU_REGISTERS_OFFSET + 0x010403CC +#define SRM_CSI1_CPD_GBS_3_OFFSET IPU_REGISTERS_OFFSET + 0x010403D0 +#define SRM_CSI1_CPD_BC_0_OFFSET IPU_REGISTERS_OFFSET + 0x010403D4 +#define SRM_CSI1_CPD_BC_1_OFFSET IPU_REGISTERS_OFFSET + 0x010403D8 +#define SRM_CSI1_CPD_BC_2_OFFSET IPU_REGISTERS_OFFSET + 0x010403DC +#define SRM_CSI1_CPD_BC_3_OFFSET IPU_REGISTERS_OFFSET + 0x010403E0 +#define SRM_CSI1_CPD_BC_4_OFFSET IPU_REGISTERS_OFFSET + 0x010403E4 +#define SRM_CSI1_CPD_BC_5_OFFSET IPU_REGISTERS_OFFSET + 0x010403E8 +#define SRM_CSI1_CPD_BC_6_OFFSET IPU_REGISTERS_OFFSET + 0x010403EC +#define SRM_CSI1_CPD_BC_7_OFFSET IPU_REGISTERS_OFFSET + 0x010403F0 +#define SRM_CSI1_CPD_BS_0_OFFSET IPU_REGISTERS_OFFSET + 0x010403F4 +#define SRM_CSI1_CPD_BS_1_OFFSET IPU_REGISTERS_OFFSET + 0x010403F8 +#define SRM_CSI1_CPD_BS_2_OFFSET IPU_REGISTERS_OFFSET + 0x010403FC +#define SRM_CSI1_CPD_BS_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040400 +#define SRM_CSI1_CPD_OFFSET1_OFFSET IPU_REGISTERS_OFFSET + 0x01040404 +#define SRM_CSI1_CPD_OFFSET2_OFFSET IPU_REGISTERS_OFFSET + 0x01040408 +#define SRM_DI0_GENERAL_OFFSET IPU_REGISTERS_OFFSET + 0x01040444 +#define SRM_DI0_BS_CLKGEN0_OFFSET IPU_REGISTERS_OFFSET + 0x01040448 +#define SRM_DI0_BS_CLKGEN1_OFFSET IPU_REGISTERS_OFFSET + 0x0104044C +#define SRM_DI0_SW_GEN0_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040450 +#define SRM_DI0_SW_GEN0_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040454 +#define SRM_DI0_SW_GEN0_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040458 +#define SRM_DI0_SW_GEN0_4_OFFSET IPU_REGISTERS_OFFSET + 0x0104045C +#define SRM_DI0_SW_GEN0_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040460 +#define SRM_DI0_SW_GEN0_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040464 +#define SRM_DI0_SW_GEN0_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040468 +#define SRM_DI0_SW_GEN0_8_OFFSET IPU_REGISTERS_OFFSET + 0x0104046C +#define SRM_DI0_SW_GEN0_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040470 +#define SRM_DI0_SW_GEN1_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040474 +#define SRM_DI0_SW_GEN1_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040478 +#define SRM_DI0_SW_GEN1_3_OFFSET IPU_REGISTERS_OFFSET + 0x0104047C +#define SRM_DI0_SW_GEN1_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040480 +#define SRM_DI0_SW_GEN1_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040484 +#define SRM_DI0_SW_GEN1_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040488 +#define SRM_DI0_SW_GEN1_7_OFFSET IPU_REGISTERS_OFFSET + 0x0104048C +#define SRM_DI0_SW_GEN1_8_OFFSET IPU_REGISTERS_OFFSET + 0x01040490 +#define SRM_DI0_SW_GEN1_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040494 +#define SRM_DI0_SYNC_AS_GEN_OFFSET IPU_REGISTERS_OFFSET + 0x01040498 +#define SRM_DI0_DW_GEN_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104049C +#define SRM_DI0_DW_GEN_1_OFFSET IPU_REGISTERS_OFFSET + 0x010404A0 +#define SRM_DI0_DW_GEN_2_OFFSET IPU_REGISTERS_OFFSET + 0x010404A4 +#define SRM_DI0_DW_GEN_3_OFFSET IPU_REGISTERS_OFFSET + 0x010404A8 +#define SRM_DI0_DW_GEN_4_OFFSET IPU_REGISTERS_OFFSET + 0x010404AC +#define SRM_DI0_DW_GEN_5_OFFSET IPU_REGISTERS_OFFSET + 0x010404B0 +#define SRM_DI0_DW_GEN_6_OFFSET IPU_REGISTERS_OFFSET + 0x010404B4 +#define SRM_DI0_DW_GEN_7_OFFSET IPU_REGISTERS_OFFSET + 0x010404B8 +#define SRM_DI0_DW_GEN_8_OFFSET IPU_REGISTERS_OFFSET + 0x010404BC +#define SRM_DI0_DW_GEN_9_OFFSET IPU_REGISTERS_OFFSET + 0x010404C0 +#define SRM_DI0_DW_GEN_10_OFFSET IPU_REGISTERS_OFFSET + 0x010404C4 +#define SRM_DI0_DW_GEN_11_OFFSET IPU_REGISTERS_OFFSET + 0x010404C8 +#define SRM_DI0_DW_SET0_0_OFFSET IPU_REGISTERS_OFFSET + 0x010404CC +#define SRM_DI0_DW_SET0_1_OFFSET IPU_REGISTERS_OFFSET + 0x010404D0 +#define SRM_DI0_DW_SET0_2_OFFSET IPU_REGISTERS_OFFSET + 0x010404D4 +#define SRM_DI0_DW_SET0_3_OFFSET IPU_REGISTERS_OFFSET + 0x010404D8 +#define SRM_DI0_DW_SET0_4_OFFSET IPU_REGISTERS_OFFSET + 0x010404DC +#define SRM_DI0_DW_SET0_5_OFFSET IPU_REGISTERS_OFFSET + 0x010404E0 +#define SRM_DI0_DW_SET0_6_OFFSET IPU_REGISTERS_OFFSET + 0x010404E4 +#define SRM_DI0_DW_SET0_7_OFFSET IPU_REGISTERS_OFFSET + 0x010404E8 +#define SRM_DI0_DW_SET0_8_OFFSET IPU_REGISTERS_OFFSET + 0x010404EC +#define SRM_DI0_DW_SET0_9_OFFSET IPU_REGISTERS_OFFSET + 0x010404F0 +#define SRM_DI0_DW_SET0_10_OFFSET IPU_REGISTERS_OFFSET + 0x010404F4 +#define SRM_DI0_DW_SET0_11_OFFSET IPU_REGISTERS_OFFSET + 0x010404F8 +#define SRM_DI0_DW_SET1_0_OFFSET IPU_REGISTERS_OFFSET + 0x010404FC +#define SRM_DI0_DW_SET1_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040500 +#define SRM_DI0_DW_SET1_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040504 +#define SRM_DI0_DW_SET1_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040508 +#define SRM_DI0_DW_SET1_4_OFFSET IPU_REGISTERS_OFFSET + 0x0104050C +#define SRM_DI0_DW_SET1_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040510 +#define SRM_DI0_DW_SET1_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040514 +#define SRM_DI0_DW_SET1_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040518 +#define SRM_DI0_DW_SET1_8_OFFSET IPU_REGISTERS_OFFSET + 0x0104051C +#define SRM_DI0_DW_SET1_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040520 +#define SRM_DI0_DW_SET1_10_OFFSET IPU_REGISTERS_OFFSET + 0x01040524 +#define SRM_DI0_DW_SET1_11_OFFSET IPU_REGISTERS_OFFSET + 0x01040528 +#define SRM_DI0_DW_SET2_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104052C +#define SRM_DI0_DW_SET2_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040530 +#define SRM_DI0_DW_SET2_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040534 +#define SRM_DI0_DW_SET2_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040538 +#define SRM_DI0_DW_SET2_4_OFFSET IPU_REGISTERS_OFFSET + 0x0104053C +#define SRM_DI0_DW_SET2_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040540 +#define SRM_DI0_DW_SET2_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040544 +#define SRM_DI0_DW_SET2_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040548 +#define SRM_DI0_DW_SET2_8_OFFSET IPU_REGISTERS_OFFSET + 0x0104054C +#define SRM_DI0_DW_SET2_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040550 +#define SRM_DI0_DW_SET2_10_OFFSET IPU_REGISTERS_OFFSET + 0x01040554 +#define SRM_DI0_DW_SET2_11_OFFSET IPU_REGISTERS_OFFSET + 0x01040558 +#define SRM_DI0_DW_SET3_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104055C +#define SRM_DI0_DW_SET3_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040560 +#define SRM_DI0_DW_SET3_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040564 +#define SRM_DI0_DW_SET3_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040568 +#define SRM_DI0_DW_SET3_4_OFFSET IPU_REGISTERS_OFFSET + 0x0104056C +#define SRM_DI0_DW_SET3_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040570 +#define SRM_DI0_DW_SET3_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040574 +#define SRM_DI0_DW_SET3_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040578 +#define SRM_DI0_DW_SET3_8_OFFSET IPU_REGISTERS_OFFSET + 0x0104057C +#define SRM_DI0_DW_SET3_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040580 +#define SRM_DI0_DW_SET3_10_OFFSET IPU_REGISTERS_OFFSET + 0x01040584 +#define SRM_DI0_DW_SET3_11_OFFSET IPU_REGISTERS_OFFSET + 0x01040588 +#define SRM_DI0_STP_REP_1_OFFSET IPU_REGISTERS_OFFSET + 0x0104058C +#define SRM_DI0_STP_REP_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040590 +#define SRM_DI0_STP_REP_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040594 +#define SRM_DI0_STP_REP_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040598 +#define SRM_DI0_STP_REP_9_OFFSET IPU_REGISTERS_OFFSET + 0x0104059C +#define SRM_DI0_SER_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x010405A0 +#define SRM_DI0_SSC_OFFSET IPU_REGISTERS_OFFSET + 0x010405A4 +#define SRM_DI0_POL_OFFSET IPU_REGISTERS_OFFSET + 0x010405A8 +#define SRM_DI0_AW0_OFFSET IPU_REGISTERS_OFFSET + 0x010405AC +#define SRM_DI0_AW1_OFFSET IPU_REGISTERS_OFFSET + 0x010405B0 +#define SRM_DI1_GENERAL_OFFSET IPU_REGISTERS_OFFSET + 0x010405B4 +#define SRM_DI1_BS_CLKGEN0_OFFSET IPU_REGISTERS_OFFSET + 0x010405B8 +#define SRM_DI1_BS_CLKGEN1_OFFSET IPU_REGISTERS_OFFSET + 0x010405BC +#define SRM_DI1_SW_GEN0_1_OFFSET IPU_REGISTERS_OFFSET + 0x010405C0 +#define SRM_DI1_SW_GEN0_2_OFFSET IPU_REGISTERS_OFFSET + 0x010405C4 +#define SRM_DI1_SW_GEN0_3_OFFSET IPU_REGISTERS_OFFSET + 0x010405C8 +#define SRM_DI1_SW_GEN0_4_OFFSET IPU_REGISTERS_OFFSET + 0x010405CC +#define SRM_DI1_SW_GEN0_5_OFFSET IPU_REGISTERS_OFFSET + 0x010405D0 +#define SRM_DI1_SW_GEN0_6_OFFSET IPU_REGISTERS_OFFSET + 0x010405D4 +#define SRM_DI1_SW_GEN0_7_OFFSET IPU_REGISTERS_OFFSET + 0x010405D8 +#define SRM_DI1_SW_GEN0_8_OFFSET IPU_REGISTERS_OFFSET + 0x010405DC +#define SRM_DI1_SW_GEN0_9_OFFSET IPU_REGISTERS_OFFSET + 0x010405E0 +#define SRM_DI1_SW_GEN1_1_OFFSET IPU_REGISTERS_OFFSET + 0x010405E4 +#define SRM_DI1_SW_GEN1_2_OFFSET IPU_REGISTERS_OFFSET + 0x010405E8 +#define SRM_DI1_SW_GEN1_3_OFFSET IPU_REGISTERS_OFFSET + 0x010405EC +#define SRM_DI1_SW_GEN1_4_OFFSET IPU_REGISTERS_OFFSET + 0x010405F0 +#define SRM_DI1_SW_GEN1_5_OFFSET IPU_REGISTERS_OFFSET + 0x010405F4 +#define SRM_DI1_SW_GEN1_6_OFFSET IPU_REGISTERS_OFFSET + 0x010405F8 +#define SRM_DI1_SW_GEN1_7_OFFSET IPU_REGISTERS_OFFSET + 0x010405FC +#define SRM_DI1_SW_GEN1_8_OFFSET IPU_REGISTERS_OFFSET + 0x01040600 +#define SRM_DI1_SW_GEN1_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040604 +#define SRM_DI1_SYNC_AS_GEN_OFFSET IPU_REGISTERS_OFFSET + 0x01040608 +#define SRM_DI1_DW_GEN_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104060C +#define SRM_DI1_DW_GEN_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040610 +#define SRM_DI1_DW_GEN_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040614 +#define SRM_DI1_DW_GEN_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040618 +#define SRM_DI1_DW_GEN_4_OFFSET IPU_REGISTERS_OFFSET + 0x0104061C +#define SRM_DI1_DW_GEN_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040620 +#define SRM_DI1_DW_GEN_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040624 +#define SRM_DI1_DW_GEN_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040628 +#define SRM_DI1_DW_GEN_8_OFFSET IPU_REGISTERS_OFFSET + 0x0104062C +#define SRM_DI1_DW_GEN_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040630 +#define SRM_DI1_DW_GEN_10_OFFSET IPU_REGISTERS_OFFSET + 0x01040634 +#define SRM_DI1_DW_GEN_11_OFFSET IPU_REGISTERS_OFFSET + 0x01040638 +#define SRM_DI1_DW_SET0_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104063C +#define SRM_DI1_DW_SET0_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040640 +#define SRM_DI1_DW_SET0_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040644 +#define SRM_DI1_DW_SET0_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040648 +#define SRM_DI1_DW_SET0_4_OFFSET IPU_REGISTERS_OFFSET + 0x0104064C +#define SRM_DI1_DW_SET0_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040650 +#define SRM_DI1_DW_SET0_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040654 +#define SRM_DI1_DW_SET0_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040658 +#define SRM_DI1_DW_SET0_8_OFFSET IPU_REGISTERS_OFFSET + 0x0104065C +#define SRM_DI1_DW_SET0_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040660 +#define SRM_DI1_DW_SET0_10_OFFSET IPU_REGISTERS_OFFSET + 0x01040664 +#define SRM_DI1_DW_SET0_11_OFFSET IPU_REGISTERS_OFFSET + 0x01040668 +#define SRM_DI1_DW_SET1_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104066C +#define SRM_DI1_DW_SET1_1_OFFSET IPU_REGISTERS_OFFSET + 0x01040670 +#define SRM_DI1_DW_SET1_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040674 +#define SRM_DI1_DW_SET1_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040678 +#define SRM_DI1_DW_SET1_4_OFFSET IPU_REGISTERS_OFFSET + 0x0104067C +#define SRM_DI1_DW_SET1_5_OFFSET IPU_REGISTERS_OFFSET + 0x01040680 +#define SRM_DI1_DW_SET1_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040684 +#define SRM_DI1_DW_SET1_7_OFFSET IPU_REGISTERS_OFFSET + 0x01040688 +#define SRM_DI1_DW_SET1_8_OFFSET IPU_REGISTERS_OFFSET + 0x0104068C +#define SRM_DI1_DW_SET1_9_OFFSET IPU_REGISTERS_OFFSET + 0x01040690 +#define SRM_DI1_DW_SET1_10_OFFSET IPU_REGISTERS_OFFSET + 0x01040694 +#define SRM_DI1_DW_SET1_11_OFFSET IPU_REGISTERS_OFFSET + 0x01040698 +#define SRM_DI1_DW_SET2_0_OFFSET IPU_REGISTERS_OFFSET + 0x0104069C +#define SRM_DI1_DW_SET2_1_OFFSET IPU_REGISTERS_OFFSET + 0x010406A0 +#define SRM_DI1_DW_SET2_2_OFFSET IPU_REGISTERS_OFFSET + 0x010406A4 +#define SRM_DI1_DW_SET2_3_OFFSET IPU_REGISTERS_OFFSET + 0x010406A8 +#define SRM_DI1_DW_SET2_4_OFFSET IPU_REGISTERS_OFFSET + 0x010406AC +#define SRM_DI1_DW_SET2_5_OFFSET IPU_REGISTERS_OFFSET + 0x010406B0 +#define SRM_DI1_DW_SET2_6_OFFSET IPU_REGISTERS_OFFSET + 0x010406B4 +#define SRM_DI1_DW_SET2_7_OFFSET IPU_REGISTERS_OFFSET + 0x010406B8 +#define SRM_DI1_DW_SET2_8_OFFSET IPU_REGISTERS_OFFSET + 0x010406BC +#define SRM_DI1_DW_SET2_9_OFFSET IPU_REGISTERS_OFFSET + 0x010406C0 +#define SRM_DI1_DW_SET2_10_OFFSET IPU_REGISTERS_OFFSET + 0x010406C4 +#define SRM_DI1_DW_SET2_11_OFFSET IPU_REGISTERS_OFFSET + 0x010406C8 +#define SRM_DI1_DW_SET3_0_OFFSET IPU_REGISTERS_OFFSET + 0x010406CC +#define SRM_DI1_DW_SET3_1_OFFSET IPU_REGISTERS_OFFSET + 0x010406D0 +#define SRM_DI1_DW_SET3_2_OFFSET IPU_REGISTERS_OFFSET + 0x010406D4 +#define SRM_DI1_DW_SET3_3_OFFSET IPU_REGISTERS_OFFSET + 0x010406D8 +#define SRM_DI1_DW_SET3_4_OFFSET IPU_REGISTERS_OFFSET + 0x010406DC +#define SRM_DI1_DW_SET3_5_OFFSET IPU_REGISTERS_OFFSET + 0x010406E0 +#define SRM_DI1_DW_SET3_6_OFFSET IPU_REGISTERS_OFFSET + 0x010406E4 +#define SRM_DI1_DW_SET3_7_OFFSET IPU_REGISTERS_OFFSET + 0x010406E8 +#define SRM_DI1_DW_SET3_8_OFFSET IPU_REGISTERS_OFFSET + 0x010406EC +#define SRM_DI1_DW_SET3_9_OFFSET IPU_REGISTERS_OFFSET + 0x010406F0 +#define SRM_DI1_DW_SET3_10_OFFSET IPU_REGISTERS_OFFSET + 0x010406F4 +#define SRM_DI1_DW_SET3_11_OFFSET IPU_REGISTERS_OFFSET + 0x010406F8 +#define SRM_DI1_STP_REP_1_OFFSET IPU_REGISTERS_OFFSET + 0x010406FC +#define SRM_DI1_STP_REP_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040700 +#define SRM_DI1_STP_REP_3_OFFSET IPU_REGISTERS_OFFSET + 0x01040704 +#define SRM_DI1_STP_REP_4_OFFSET IPU_REGISTERS_OFFSET + 0x01040708 +#define SRM_DI1_STP_REP_9_OFFSET IPU_REGISTERS_OFFSET + 0x0104070C +#define SRM_DI1_SER_CONF_OFFSET IPU_REGISTERS_OFFSET + 0x01040710 +#define SRM_DI1_SSC_OFFSET IPU_REGISTERS_OFFSET + 0x01040714 +#define SRM_DI1_POL_OFFSET IPU_REGISTERS_OFFSET + 0x01040718 +#define SRM_DI1_AW0_OFFSET IPU_REGISTERS_OFFSET + 0x0104071C +#define SRM_DI1_AW1_OFFSET IPU_REGISTERS_OFFSET + 0x01040720 +#define SRM_DC_WR_CH_CONF_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104040C +#define SRM_DC_WR_CH_ADDR_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040410 +#define SRM_DC_RL0_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040414 +#define SRM_DC_RL1_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040418 +#define SRM_DC_RL2_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x0104041C +#define SRM_DC_RL3_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040420 +#define SRM_DC_RL4_CH_2_OFFSET IPU_REGISTERS_OFFSET + 0x01040424 +#define SRM_DC_WR_CH_CONF_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040428 +#define SRM_DC_WR_CH_ADDR_6_OFFSET IPU_REGISTERS_OFFSET + 0x0104042C +#define SRM_DC_RL0_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040430 +#define SRM_DC_RL1_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040434 +#define SRM_DC_RL2_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040438 +#define SRM_DC_RL3_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x0104043C +#define SRM_DC_RL4_CH_6_OFFSET IPU_REGISTERS_OFFSET + 0x01040440 +#define IPU_ISP_TBPR_0_OFFSET IPU_REGISTERS_OFFSET + 0x010C0000 +#define IPU_ISP_TBPR_1_OFFSET IPU_REGISTERS_OFFSET + 0x010C0004 +#define IPU_ISP_TBPR_2_OFFSET IPU_REGISTERS_OFFSET + 0x010C0008 +#define IPU_ISP_TBPR_3_OFFSET IPU_REGISTERS_OFFSET + 0x010C000C +#define IPU_ISP_TBPR_4_OFFSET IPU_REGISTERS_OFFSET + 0x010C0010 +#define IPU_ISP_TBPR_5_OFFSET IPU_REGISTERS_OFFSET + 0x010C0014 +#define IPU_ISP_TBPR_6_OFFSET IPU_REGISTERS_OFFSET + 0x010C0018 +#define IPU_ISP_TBPR_7_OFFSET IPU_REGISTERS_OFFSET + 0x010C001C +#define IPU_ISP_TBPR_8_OFFSET IPU_REGISTERS_OFFSET + 0x010C0020 +#define IPU_ISP_TBPR_9_OFFSET IPU_REGISTERS_OFFSET + 0x010C0024 +#define IPU_ISP_TBPR_10_OFFSET IPU_REGISTERS_OFFSET + 0x010C0028 +#define IPU_ISP_TBPR_11_OFFSET IPU_REGISTERS_OFFSET + 0x010C002C +#define IPU_ISP_TBPR_12_OFFSET IPU_REGISTERS_OFFSET + 0x010C0030 +#define IPU_ISP_TBPR_13_OFFSET IPU_REGISTERS_OFFSET + 0x010C0034 +#define IPU_ISP_TBPR_14_OFFSET IPU_REGISTERS_OFFSET + 0x010C0038 +#define IPU_ISP_TBPR_15_OFFSET IPU_REGISTERS_OFFSET + 0x010C003C +#define IPU_ISP_TBPR_16_OFFSET IPU_REGISTERS_OFFSET + 0x010C0040 +#define IPU_ISP_TBPR_17_OFFSET IPU_REGISTERS_OFFSET + 0x010C0044 +#define IPU_ISP_TBPR_18_OFFSET IPU_REGISTERS_OFFSET + 0x010C0048 +#define IPU_ISP_TBPR_19_OFFSET IPU_REGISTERS_OFFSET + 0x010C004C +#define IPU_ISP_TBPR_20_OFFSET IPU_REGISTERS_OFFSET + 0x010C0050 +#define IPU_ISP_TBPR_21_OFFSET IPU_REGISTERS_OFFSET + 0x010C0054 +#define IPU_ISP_TBPR_22_OFFSET IPU_REGISTERS_OFFSET + 0x010C0058 +#define IPU_ISP_TBPR_23_OFFSET IPU_REGISTERS_OFFSET + 0x010C005C +#define IPU_ISP_TBPR_24_OFFSET IPU_REGISTERS_OFFSET + 0x010C0060 +#define IPU_ISP_TBPR_25_OFFSET IPU_REGISTERS_OFFSET + 0x010C0064 +#define IPU_ISP_TBPR_26_OFFSET IPU_REGISTERS_OFFSET + 0x010C0068 +#define IPU_ISP_TBPR_27_OFFSET IPU_REGISTERS_OFFSET + 0x010C006C +#define IPU_ISP_TBPR_28_OFFSET IPU_REGISTERS_OFFSET + 0x010C0070 +#define IPU_ISP_TBPR_29_OFFSET IPU_REGISTERS_OFFSET + 0x010C0074 +#define IPU_ISP_TBPR_30_OFFSET IPU_REGISTERS_OFFSET + 0x010C0078 +#define IPU_ISP_TBPR_31_OFFSET IPU_REGISTERS_OFFSET + 0x010C007C +#define IPU_ISP_TBPR_32_OFFSET IPU_REGISTERS_OFFSET + 0x010C0080 +#define IPU_ISP_TBPR_33_OFFSET IPU_REGISTERS_OFFSET + 0x010C0084 +#define IPU_ISP_TBPR_34_OFFSET IPU_REGISTERS_OFFSET + 0x010C0088 +#define IPU_ISP_TBPR_35_OFFSET IPU_REGISTERS_OFFSET + 0x010C008C +#define IPU_ISP_TBPR_36_OFFSET IPU_REGISTERS_OFFSET + 0x010C0090 +#define IPU_ISP_TBPR_37_OFFSET IPU_REGISTERS_OFFSET + 0x010C0094 +#define IPU_ISP_TBPR_38_OFFSET IPU_REGISTERS_OFFSET + 0x010C0098 +#define IPU_ISP_TBPR_39_OFFSET IPU_REGISTERS_OFFSET + 0x010C009C +#define IPU_ISP_TBPR_40_OFFSET IPU_REGISTERS_OFFSET + 0x010C00A0 +#define IPU_ISP_TBPR_41_OFFSET IPU_REGISTERS_OFFSET + 0x010C00A4 +#define IPU_ISP_TBPR_42_OFFSET IPU_REGISTERS_OFFSET + 0x010C00A8 +#define IPU_ISP_TBPR_43_OFFSET IPU_REGISTERS_OFFSET + 0x010C00AC +#define IPU_ISP_TBPR_44_OFFSET IPU_REGISTERS_OFFSET + 0x010C00B0 +#define IPU_ISP_TBPR_45_OFFSET IPU_REGISTERS_OFFSET + 0x010C00B4 +#define IPU_ISP_TBPR_46_OFFSET IPU_REGISTERS_OFFSET + 0x010C00B8 +#define IPU_ISP_TBPR_47_OFFSET IPU_REGISTERS_OFFSET + 0x010C00BC +#define IPU_ISP_TBPR_48_OFFSET IPU_REGISTERS_OFFSET + 0x010C00C0 +#define IPU_ISP_TBPR_49_OFFSET IPU_REGISTERS_OFFSET + 0x010C00C4 +#define IPU_ISP_TBPR_50_OFFSET IPU_REGISTERS_OFFSET + 0x010C00C8 +#define IPU_ISP_TBPR_51_OFFSET IPU_REGISTERS_OFFSET + 0x010C00CC +#define IPU_ISP_TBPR_52_OFFSET IPU_REGISTERS_OFFSET + 0x010C00D0 +#define IPU_ISP_TBPR_53_OFFSET IPU_REGISTERS_OFFSET + 0x010C00D4 +#define IPU_ISP_TBPR_54_OFFSET IPU_REGISTERS_OFFSET + 0x010C00D8 +#define IPU_ISP_TBPR_55_OFFSET IPU_REGISTERS_OFFSET + 0x010C00DC +#define IPU_ISP_TBPR_56_OFFSET IPU_REGISTERS_OFFSET + 0x010C00E0 +#define IPU_ISP_TBPR_57_OFFSET IPU_REGISTERS_OFFSET + 0x010C00E4 +#define IPU_ISP_TBPR_58_OFFSET IPU_REGISTERS_OFFSET + 0x010C00E8 +#define IPU_ISP_TBPR_59_OFFSET IPU_REGISTERS_OFFSET + 0x010C00EC +#define IPU_ISP_TBPR_60_OFFSET IPU_REGISTERS_OFFSET + 0x010C00F0 +#define IPU_ISP_TBPR_61_OFFSET IPU_REGISTERS_OFFSET + 0x010C00F4 +#define IPU_ISP_TBPR_62_OFFSET IPU_REGISTERS_OFFSET + 0x010C00F8 +#define IPU_ISP_TBPR_63_OFFSET IPU_REGISTERS_OFFSET + 0x010C00FC +//######################################### +//# GPU +//######################################### +#define GPU3D_BASE_ADDRESS_OFFSET GPU_BASE_ADDR +#define GMEM_BASE_ADDRESS_OFFSET GPU_MEM_BASE_ADDR + +#define GPU3D_RBBM_RTL_RELEASE_OFFSET 0x0 +#define GPU3D_RBBM_PATCH_RELEASE_OFFSET 0x4 +#define GPU3D_RBBM_AUXILIARY_CONFIG_OFFSET 0x8 +#define GPU3D_GPU3D_GPIO_REG_OFFSET 0x1FFFE +#define GPU3D_BIOS_0_SCRATCH_OFFSET 0x10 +#define GPU3D_BIOS_1_SCRATCH_OFFSET 0x14 +#define GPU3D_BIOS_2_SCRATCH_OFFSET 0x18 +#define GPU3D_BIOS_3_SCRATCH_OFFSET 0x1C +#define GPU3D_BIOS_4_SCRATCH_OFFSET 0x20 +#define GPU3D_BIOS_5_SCRATCH_OFFSET 0x24 +#define GPU3D_BIOS_6_SCRATCH_OFFSET 0x28 +#define GPU3D_BIOS_7_SCRATCH_OFFSET 0x2C +#define GPU3D_RBBM_CNTL_OFFSET 0xEC +#define GPU3D_RBBM_SOFT_RESET_OFFSET 0xF0 +#define GPU3D_RBBM_SKEW_CNTL_OFFSET 0xF4 +#define GPU3D_MH_MMU_CONFIG_OFFSET 0x100 +#define GPU3D_MH_MMU_VA_RANGE_OFFSET 0x104 +#define GPU3D_MH_MMU_PT_BASE_OFFSET 0x108 +#define GPU3D_MH_MMU_PAGE_FAULT_OFFSET 0x10C +#define GPU3D_MH_MMU_TRAN_ERROR_OFFSET 0x110 +#define GPU3D_MH_MMU_INVALIDATE_OFFSET 0x114 +#define GPU3D_MH_MMU_MPU_BASE_OFFSET 0x118 +#define GPU3D_MH_MMU_MPU_END_OFFSET 0x11C +#define GPU3D_CP_PFP_UCODE_ADDR_OFFSET 0x300 +#define GPU3D_CP_PFP_UCODE_DATA_OFFSET 0x304 +#define GPU3D_CP_RB_BASE_OFFSET 0x700 +#define GPU3D_CP_RB_CNTL_OFFSET 0x704 +#define GPU3D_CP_RB_RPTR_ADDR_OFFSET 0x70C +#define GPU3D_CP_RB_RPTR_OFFSET 0x710 +#define GPU3D_CP_RB_WPTR_OFFSET 0x714 +#define GPU3D_CP_RB_WPTR_DELAY_OFFSET 0x718 +#define GPU3D_CP_RB_RPTR_WR_OFFSET 0x71C +#define GPU3D_CP_RB_WPTR_BASE_OFFSET 0x720 +#define GPU3D_CP_QUEUE_THRESHOLDS_OFFSET 0x754 +#define GPU3D_CP_MEQ_THRESHOLDS_OFFSET 0x758 +#define GPU3D_CP_CSQ_AVAIL_OFFSET 0x75C +#define GPU3D_CP_STQ_AVAIL_OFFSET 0x760 +#define GPU3D_CP_MEQ_AVAIL_OFFSET 0x764 +#define GPU3D_CP_CMD_INDEX_OFFSET 0x768 +#define GPU3D_CP_CMD_DATA_OFFSET 0x76C +#define GPU3D_SCRATCH_UMSK_OFFSET 0x770 +#define GPU3D_SCRATCH_ADDR_OFFSET 0x774 +#define GPU3D_CP_ME_RDADDR_OFFSET 0x7A8 +#define GPU3D_CP_STATE_DEBUG_INDEX_OFFSET 0x7B0 +#define GPU3D_CP_STATE_DEBUG_DATA_OFFSET 0x7B4 +#define GPU3D_CP_NV_FLAGS_0_OFFSET 0x7B8 +#define GPU3D_CP_NV_FLAGS_1_OFFSET 0x7BC +#define GPU3D_CP_NV_FLAGS_2_OFFSET 0x7C0 +#define GPU3D_CP_NV_FLAGS_3_OFFSET 0x7C4 +#define GPU3D_CP_INT_CNTL_OFFSET 0x7C8 +#define GPU3D_CP_INT_STATUS_OFFSET 0x7CC +#define GPU3D_CP_INT_ACK_OFFSET 0x7D0 +#define GPU3D_CP_ME_CNTL_OFFSET 0x7D8 +#define GPU3D_CP_ME_STATUS_OFFSET 0x7DC +#define GPU3D_CP_ME_RAM_WADDR_OFFSET 0x7E0 +#define GPU3D_CP_ME_RAM_RADDR_OFFSET 0x7E4 +#define GPU3D_CP_ME_RAM_DATA_OFFSET 0x7E8 +#define GPU3D_CP_DEBUG_OFFSET 0x7F0 +#define GPU3D_CP_CSQ_RB_STAT_OFFSET 0x7F4 +#define GPU3D_CP_CSQ_IB1_STAT_OFFSET 0x7F8 +#define GPU3D_CP_CSQ_IB2_STAT_OFFSET 0x7FC +#define GPU3D_RBBM_DSPLY_OFFSET 0xE44 +#define GPU3D_RBBM_RENDER_LATEST_OFFSET 0xE48 +#define GPU3D_NQWAIT_UNTIL_OFFSET 0xE50 +#define GPU3D_RBBM_PERFCOUNTER1_SELECT_OFFSET 0xE54 +#define GPU3D_RBBM_PERFCOUNTER1_LO_OFFSET 0xE5C +#define GPU3D_RBBM_PERFCOUNTER1_HI_OFFSET 0xE60 +#define GPU3D_RBBM_DEBUG_OFFSET 0xE6C +#define GPU3D_RBBM_PM_OVERRIDE1_OFFSET 0xE70 +#define GPU3D_RBBM_PM_OVERRIDE2_OFFSET 0xE74 +#define GPU3D_GC_SYS_IDLE_OFFSET 0xE78 +#define GPU3D_RBBM_DEBUG_OUT_OFFSET 0xE80 +#define GPU3D_RBBM_DEBUG_CNTL_OFFSET 0xE84 +#define GPU3D_RBBM_WAIT_IDLE_CLOCKS_OFFSET 0xEC8 +#define GPU3D_RBBM_READ_ERROR_OFFSET 0xECC +#define GPU3D_RBBM_INT_CNTL_OFFSET 0xED0 +#define GPU3D_RBBM_INT_STATUS_OFFSET 0xED4 +#define GPU3D_RBBM_INT_ACK_OFFSET 0xED8 +#define GPU3D_MASTER_INT_SIGNAL_OFFSET 0xEDC +#define GPU3D_RBBM_PERIPHID0_OFFSET 0xFE0 +#define GPU3D_RBBM_PERIPHID1_OFFSET 0xFE4 +#define GPU3D_RBBM_PERIPHID2_OFFSET 0xFE8 +#define GPU3D_RBBM_PERIPHID3_OFFSET 0xFEC +#define GPU3D_CP_NON_PREFETCH_CNTRS_OFFSET 0x1100 +#define GPU3D_CP_STQ_ST_STAT_OFFSET 0x110C +#define GPU3D_CP_PERFMON_CNTL_OFFSET 0x1110 +#define GPU3D_CP_PERFCOUNTER_SELECT_OFFSET 0x1114 +#define GPU3D_CP_PERFCOUNTER_LO_OFFSET 0x1118 +#define GPU3D_CP_PERFCOUNTER_HI_OFFSET 0x111C +#define GPU3D_CP_PROG_COUNTER_OFFSET 0x112C +#define GPU3D_CP_ST_BASE_OFFSET 0x1134 +#define GPU3D_CP_ST_BUFSZ_OFFSET 0x1138 +#define GPU3D_CP_MEQ_STAT_OFFSET 0x113C +#define GPU3D_CP_MIU_TAG_STAT_OFFSET 0x1148 +#define GPU3D_CP_BIN_MASK_LO_OFFSET 0x1150 +#define GPU3D_CP_BIN_MASK_HI_OFFSET 0x1154 +#define GPU3D_CP_BIN_SELECT_LO_OFFSET 0x1158 +#define GPU3D_CP_BIN_SELECT_HI_OFFSET 0x115C +#define GPU3D_CP_IB1_BASE_OFFSET 0x1160 +#define GPU3D_CP_IB1_BUFSZ_OFFSET 0x1164 +#define GPU3D_CP_IB2_BASE_OFFSET 0x1168 +#define GPU3D_CP_IB2_BUFSZ_OFFSET 0x116C +#define GPU3D_CP_STAT_OFFSET 0x11FC +#define GPU3D_SCRATCH_REG0_OFFSET 0x15E0 +#define GPU3D_SCRATCH_REG1_OFFSET 0x15E4 +#define GPU3D_SCRATCH_REG2_OFFSET 0x15E8 +#define GPU3D_SCRATCH_REG3_OFFSET 0x15EC +#define GPU3D_SCRATCH_REG4_OFFSET 0x15F0 +#define GPU3D_SCRATCH_REG5_OFFSET 0x15F4 +#define GPU3D_SCRATCH_REG6_OFFSET 0x15F8 +#define GPU3D_SCRATCH_REG7_OFFSET 0x15FC +#define GPU3D_BIOS_8_SCRATCH_OFFSET 0x1600 +#define GPU3D_BIOS_9_SCRATCH_OFFSET 0x1604 +#define GPU3D_BIOS_10_SCRATCH_OFFSET 0x1608 +#define GPU3D_BIOS_11_SCRATCH_OFFSET 0x160C +#define GPU3D_BIOS_12_SCRATCH_OFFSET 0x1610 +#define GPU3D_BIOS_13_SCRATCH_OFFSET 0x1614 +#define GPU3D_BIOS_14_SCRATCH_OFFSET 0x1618 +#define GPU3D_BIOS_15_SCRATCH_OFFSET 0x161C +#define GPU3D_WAIT_UNTIL_OFFSET 0x1720 +#define GPU3D_RBBM_ISYNC_CNTL_OFFSET 0x1724 +#define GPU3D_RBBM_STATUS_OFFSET 0x1740 +#define GPU3D_CP_ME_VS_EVENT_SRC_OFFSET 0x1800 +#define GPU3D_CP_ME_VS_EVENT_ADDR_OFFSET 0x1804 +#define GPU3D_CP_ME_VS_EVENT_DATA_OFFSET 0x1808 +#define GPU3D_CP_ME_VS_EVENT_ADDR_SWM_OFFSET 0x180C +#define GPU3D_CP_ME_VS_EVENT_DATA_SWM_OFFSET 0x1810 +#define GPU3D_CP_ME_PS_EVENT_SRC_OFFSET 0x1814 +#define GPU3D_CP_ME_PS_EVENT_ADDR_OFFSET 0x1818 +#define GPU3D_CP_ME_PS_EVENT_DATA_OFFSET 0x181C +#define GPU3D_CP_ME_PS_EVENT_ADDR_SWM_OFFSET 0x1820 +#define GPU3D_CP_ME_PS_EVENT_DATA_SWM_OFFSET 0x1824 +#define GPU3D_CP_ME_CF_EVENT_SRC_OFFSET 0x1828 +#define GPU3D_CP_ME_CF_EVENT_ADDR_OFFSET 0x182C +#define GPU3D_CP_ME_CF_EVENT_DATA_OFFSET 0x1830 +#define GPU3D_CP_ME_NRT_ADDR_OFFSET 0x1834 +#define GPU3D_CP_ME_NRT_DATA_OFFSET 0x1838 +#define GPU3D_CP_ME_VS_FETCH_DONE_SRC_OFFSET 0x1848 +#define GPU3D_CP_ME_VS_FETCH_DONE_ADDR_OFFSET 0x184C +#define GPU3D_CP_ME_VS_FETCH_DONE_DATA_OFFSET 0x1850 +#define GPU3D_COHER_SIZE_PM4_OFFSET 0x28A4 +#define GPU3D_COHER_BASE_PM4_OFFSET 0x28A8 +#define GPU3D_COHER_STATUS_PM4_OFFSET 0x28AC +#define GPU3D_COHER_SIZE_HOST_OFFSET 0x28BC +#define GPU3D_COHER_BASE_HOST_OFFSET 0x28C0 +#define GPU3D_COHER_STATUS_HOST_OFFSET 0x28C4 +#define GPU3D_MH_ARBITER_CONFIG_OFFSET 0x2900 +#define GPU3D_MH_CLNT_AXI_ID_REUSE_OFFSET 0x2904 +#define GPU3D_MH_INTERRUPT_MASK_OFFSET 0x2908 +#define GPU3D_MH_INTERRUPT_STATUS_OFFSET 0x290C +#define GPU3D_MH_INTERRUPT_CLEAR_OFFSET 0x2910 +#define GPU3D_MH_AXI_ERROR_OFFSET 0x2914 +#define GPU3D_MH_PERFCOUNTER0_SELECT_OFFSET 0x2918 +#define GPU3D_MH_PERFCOUNTER0_CONFIG_OFFSET 0x291C +#define GPU3D_MH_PERFCOUNTER0_LOW_OFFSET 0x2920 +#define GPU3D_MH_PERFCOUNTER0_HI_OFFSET 0x2924 +#define GPU3D_MH_PERFCOUNTER1_SELECT_OFFSET 0x2928 +#define GPU3D_MH_PERFCOUNTER1_CONFIG_OFFSET 0x292C +#define GPU3D_MH_PERFCOUNTER1_LOW_OFFSET 0x2930 +#define GPU3D_MH_PERFCOUNTER1_HI_OFFSET 0x2934 +#define GPU3D_MH_DEBUG_CTRL_OFFSET 0x2938 +#define GPU3D_MH_DEBUG_DATA_OFFSET 0x293C +#define GPU3D_MH_AXI_HALT_CONTROL_OFFSET 0x2940 +#define GPU3D_VGT_VTX_VECT_EJECT_REG_OFFSET 0x30B0 +#define GPU3D_VGT_LAST_COPY_STATE_OFFSET 0x30C0 +#define GPU3D_VGT_DEBUG_CNTL_OFFSET 0x30E0 +#define GPU3D_VGT_DEBUG_DATA_OFFSET 0x30E4 +#define GPU3D_VGT_CRC_SQ_DATA_OFFSET 0x30E8 +#define GPU3D_VGT_CRC_SQ_CTRL_OFFSET 0x30EC +#define GPU3D_VGT_CNTL_STATUS_OFFSET 0x30F0 +#define GPU3D_PA_SC_LINE_STIPPLE_STATE_OFFSET 0x3100 +#define GPU3D_PA_SC_VIZ_QUERY_STATUS_OFFSET 0x3110 +#define GPU3D_VGT_PERFCOUNTER0_SELECT_OFFSET 0x3120 +#define GPU3D_VGT_PERFCOUNTER1_SELECT_OFFSET 0x3124 +#define GPU3D_VGT_PERFCOUNTER2_SELECT_OFFSET 0x3128 +#define GPU3D_VGT_PERFCOUNTER3_SELECT_OFFSET 0x312C +#define GPU3D_VGT_PERFCOUNTER0_LOW_OFFSET 0x3130 +#define GPU3D_VGT_PERFCOUNTER0_HI_OFFSET 0x3134 +#define GPU3D_VGT_PERFCOUNTER1_LOW_OFFSET 0x3138 +#define GPU3D_VGT_PERFCOUNTER1_HI_OFFSET 0x313C +#define GPU3D_VGT_PERFCOUNTER2_LOW_OFFSET 0x3140 +#define GPU3D_VGT_PERFCOUNTER2_HI_OFFSET 0x3144 +#define GPU3D_VGT_PERFCOUNTER3_LOW_OFFSET 0x3148 +#define GPU3D_VGT_PERFCOUNTER3_HI_OFFSET 0x314C +#define GPU3D_PA_SU_DEBUG_CNTL_OFFSET 0x3200 +#define GPU3D_PA_SU_DEBUG_DATA_OFFSET 0x3204 +#define GPU3D_PA_SC_DEBUG_CNTL_OFFSET 0x3208 +#define GPU3D_PA_SC_DEBUG_DATA_OFFSET 0x320C +#define GPU3D_PA_CL_CNTL_STATUS_OFFSET 0x3210 +#define GPU3D_PA_CL_ENHANCE_OFFSET 0x3214 +#define GPU3D_PA_SU_FACE_DATA_OFFSET 0x3218 +#define GPU3D_PA_SU_PERFCOUNTER0_SELECT_OFFSET 0x3220 +#define GPU3D_PA_SU_PERFCOUNTER1_SELECT_OFFSET 0x3224 +#define GPU3D_PA_SU_PERFCOUNTER2_SELECT_OFFSET 0x3228 +#define GPU3D_PA_SU_PERFCOUNTER3_SELECT_OFFSET 0x322C +#define GPU3D_PA_SU_PERFCOUNTER0_LOW_OFFSET 0x3230 +#define GPU3D_PA_SU_PERFCOUNTER0_HI_OFFSET 0x3234 +#define GPU3D_PA_SU_PERFCOUNTER1_LOW_OFFSET 0x3238 +#define GPU3D_PA_SU_PERFCOUNTER1_HI_OFFSET 0x323C +#define GPU3D_PA_SU_PERFCOUNTER2_LOW_OFFSET 0x3240 +#define GPU3D_PA_SU_PERFCOUNTER2_HI_OFFSET 0x3244 +#define GPU3D_PA_SU_PERFCOUNTER3_LOW_OFFSET 0x3248 +#define GPU3D_PA_SU_PERFCOUNTER3_HI_OFFSET 0x324C +#define GPU3D_PA_SU_CNTL_STATUS_OFFSET 0x3250 +#define GPU3D_PA_SC_PERFCOUNTER0_SELECT_OFFSET 0x3260 +#define GPU3D_PA_SC_PERFCOUNTER0_LOW_OFFSET 0x3264 +#define GPU3D_PA_SC_PERFCOUNTER0_HI_OFFSET 0x3268 +#define GPU3D_PA_SC_CNTL_STATUS_OFFSET 0x3290 +#define GPU3D_PA_SC_ENHANCE_OFFSET 0x3294 +#define GPU3D_SQ_GPR_MANAGEMENT_OFFSET 0x3400 +#define GPU3D_SQ_FLOW_CONTROL_OFFSET 0x3404 +#define GPU3D_SQ_INST_STORE_MANAGMENT_OFFSET 0x3408 +#define GPU3D_SQ_RESOURCE_MANAGMENT_OFFSET 0x340C +#define GPU3D_SQ_ACTIVITY_METER_CNTL_OFFSET 0x3418 +#define GPU3D_SQ_ACTIVITY_METER_STATUS_OFFSET 0x341C +#define GPU3D_SQ_INPUT_ARB_PRIORITY_OFFSET 0x3420 +#define GPU3D_SQ_THREAD_ARB_PRIORITY_OFFSET 0x3424 +#define GPU3D_SQ_VS_WATCHDOG_TIMER_OFFSET 0x3428 +#define GPU3D_SQ_PS_WATCHDOG_TIMER_OFFSET 0x342C +#define GPU3D_SQ_INT_CNTL_OFFSET 0x34D0 +#define GPU3D_SQ_INT_STATUS_OFFSET 0x34D4 +#define GPU3D_SQ_INT_ACK_OFFSET 0x34D8 +#define GPU3D_SQ_DEBUG_INPUT_FSM_OFFSET 0x36B8 +#define GPU3D_SQ_DEBUG_CONST_MGR_FSM_OFFSET 0x36BC +#define GPU3D_SQ_DEBUG_TP_FSM_OFFSET 0x36C0 +#define GPU3D_SQ_DEBUG_FSM_ALU_0_OFFSET 0x36C4 +#define GPU3D_SQ_DEBUG_FSM_ALU_1_OFFSET 0x36C8 +#define GPU3D_SQ_DEBUG_EXP_ALLOC_OFFSET 0x36CC +#define GPU3D_SQ_DEBUG_PTR_BUFF_OFFSET 0x36D0 +#define GPU3D_SQ_DEBUG_GPR_VTX_OFFSET 0x36D4 +#define GPU3D_SQ_DEBUG_GPR_PIX_OFFSET 0x36D8 +#define GPU3D_SQ_DEBUG_TB_STATUS_SEL_OFFSET 0x36DC +#define GPU3D_SQ_DEBUG_VTX_TB_0_OFFSET 0x36E0 +#define GPU3D_SQ_DEBUG_VTX_TB_1_OFFSET 0x36E4 +#define GPU3D_SQ_DEBUG_VTX_TB_STATUS_REG_OFFSET 0x36E8 +#define GPU3D_SQ_DEBUG_VTX_TB_STATE_MEM_OFFSET 0x36EC +#define GPU3D_SQ_DEBUG_PIX_TB_0_OFFSET 0x36F0 +#define GPU3D_SQ_DEBUG_PIX_TB_STATUS_REG_0_OFFSET 0x36F4 +#define GPU3D_SQ_DEBUG_PIX_TB_STATUS_REG_1_OFFSET 0x36F8 +#define GPU3D_SQ_DEBUG_PIX_TB_STATUS_REG_2_OFFSET 0x36FC +#define GPU3D_SQ_DEBUG_PIX_TB_STATUS_REG_3_OFFSET 0x3700 +#define GPU3D_SQ_DEBUG_PIX_TB_STATE_MEM_OFFSET 0x3704 +#define GPU3D_SQ_PERFCOUNTER0_SELECT_OFFSET 0x3720 +#define GPU3D_SQ_PERFCOUNTER1_SELECT_OFFSET 0x3724 +#define GPU3D_SQ_PERFCOUNTER2_SELECT_OFFSET 0x3728 +#define GPU3D_SQ_PERFCOUNTER3_SELECT_OFFSET 0x372C +#define GPU3D_SQ_PERFCOUNTER0_LOW_OFFSET 0x3730 +#define GPU3D_SQ_PERFCOUNTER0_HI_OFFSET 0x3734 +#define GPU3D_SQ_PERFCOUNTER1_LOW_OFFSET 0x3738 +#define GPU3D_SQ_PERFCOUNTER1_HI_OFFSET 0x373C +#define GPU3D_SQ_PERFCOUNTER2_LOW_OFFSET 0x3740 +#define GPU3D_SQ_PERFCOUNTER2_HI_OFFSET 0x3744 +#define GPU3D_SQ_PERFCOUNTER3_LOW_OFFSET 0x3748 +#define GPU3D_SQ_PERFCOUNTER3_HI_OFFSET 0x374C +#define GPU3D_SX_PERFCOUNTER0_SELECT_OFFSET 0x3750 +#define GPU3D_SX_PERFCOUNTER0_LOW_OFFSET 0x3760 +#define GPU3D_SX_PERFCOUNTER0_HI_OFFSET 0x3764 +#define GPU3D_TC_CNTL_STATUS_OFFSET 0x3800 +#define GPU3D_TCR_CHICKEN_OFFSET 0x3808 +#define GPU3D_TCF_CHICKEN_OFFSET 0x380C +#define GPU3D_TCM_CHICKEN_OFFSET 0x3810 +#define GPU3D_TCR_PERFCOUNTER0_SELECT_OFFSET 0x3814 +#define GPU3D_TCR_PERFCOUNTER0_HI_OFFSET 0x3818 +#define GPU3D_TCR_PERFCOUNTER0_LOW_OFFSET 0x381C +#define GPU3D_TCR_PERFCOUNTER1_SELECT_OFFSET 0x3820 +#define GPU3D_TCR_PERFCOUNTER1_HI_OFFSET 0x3824 +#define GPU3D_TCR_PERFCOUNTER1_LOW_OFFSET 0x3828 +#define GPU3D_TP_TC_CLKGATE_CNTL_OFFSET 0x385C +#define GPU3D_TPC_CNTL_STATUS_OFFSET 0x3860 +#define GPU3D_TPC_DEBUG0_OFFSET 0x3864 +#define GPU3D_TPC_DEBUG1_OFFSET 0x3868 +#define GPU3D_TPC_CHICKEN_OFFSET 0x386C +#define GPU3D_TP0_CNTL_STATUS_OFFSET 0x3870 +#define GPU3D_TP0_DEBUG_OFFSET 0x3874 +#define GPU3D_TP0_CHICKEN_OFFSET 0x3878 +#define GPU3D_TP0_PERFCOUNTER0_SELECT_OFFSET 0x387C +#define GPU3D_TP0_PERFCOUNTER0_HI_OFFSET 0x3880 +#define GPU3D_TP0_PERFCOUNTER0_LOW_OFFSET 0x3884 +#define GPU3D_TP0_PERFCOUNTER1_SELECT_OFFSET 0x3888 +#define GPU3D_TP0_PERFCOUNTER1_HI_OFFSET 0x388C +#define GPU3D_TP0_PERFCOUNTER1_LOW_OFFSET 0x3890 +#define GPU3D_TCM_PERFCOUNTER0_SELECT_OFFSET 0x3950 +#define GPU3D_TCM_PERFCOUNTER0_HI_OFFSET 0x3954 +#define GPU3D_TCM_PERFCOUNTER0_LOW_OFFSET 0x3958 +#define GPU3D_TCM_PERFCOUNTER1_SELECT_OFFSET 0x395C +#define GPU3D_TCM_PERFCOUNTER1_HI_OFFSET 0x3960 +#define GPU3D_TCM_PERFCOUNTER1_LOW_OFFSET 0x3964 +#define GPU3D_TCF_PERFCOUNTER0_SELECT_OFFSET 0x3968 +#define GPU3D_TCF_PERFCOUNTER0_HI_OFFSET 0x396C +#define GPU3D_TCF_PERFCOUNTER0_LOW_OFFSET 0x3970 +#define GPU3D_TCF_PERFCOUNTER1_SELECT_OFFSET 0x3974 +#define GPU3D_TCF_PERFCOUNTER1_HI_OFFSET 0x3978 +#define GPU3D_TCF_PERFCOUNTER1_LOW_OFFSET 0x397C +#define GPU3D_TCF_PERFCOUNTER2_SELECT_OFFSET 0x3980 +#define GPU3D_TCF_PERFCOUNTER2_HI_OFFSET 0x3984 +#define GPU3D_TCF_PERFCOUNTER2_LOW_OFFSET 0x3988 +#define GPU3D_TCF_PERFCOUNTER3_SELECT_OFFSET 0x398C +#define GPU3D_TCF_PERFCOUNTER3_HI_OFFSET 0x3990 +#define GPU3D_TCF_PERFCOUNTER3_LOW_OFFSET 0x3994 +#define GPU3D_TCF_PERFCOUNTER4_SELECT_OFFSET 0x3998 +#define GPU3D_TCF_PERFCOUNTER4_HI_OFFSET 0x399C +#define GPU3D_TCF_PERFCOUNTER4_LOW_OFFSET 0x39A0 +#define GPU3D_TCF_PERFCOUNTER5_SELECT_OFFSET 0x39A4 +#define GPU3D_TCF_PERFCOUNTER5_HI_OFFSET 0x39A8 +#define GPU3D_TCF_PERFCOUNTER5_LOW_OFFSET 0x39AC +#define GPU3D_TCF_PERFCOUNTER6_SELECT_OFFSET 0x39B0 +#define GPU3D_TCF_PERFCOUNTER6_HI_OFFSET 0x39B4 +#define GPU3D_TCF_PERFCOUNTER6_LOW_OFFSET 0x39B8 +#define GPU3D_TCF_PERFCOUNTER7_SELECT_OFFSET 0x39BC +#define GPU3D_TCF_PERFCOUNTER7_HI_OFFSET 0x39C0 +#define GPU3D_TCF_PERFCOUNTER7_LOW_OFFSET 0x39C4 +#define GPU3D_TCF_PERFCOUNTER8_SELECT_OFFSET 0x39C8 +#define GPU3D_TCF_PERFCOUNTER8_HI_OFFSET 0x39CC +#define GPU3D_TCF_PERFCOUNTER8_LOW_OFFSET 0x39D0 +#define GPU3D_TCF_PERFCOUNTER9_SELECT_OFFSET 0x39D4 +#define GPU3D_TCF_PERFCOUNTER9_HI_OFFSET 0x39D8 +#define GPU3D_TCF_PERFCOUNTER9_LOW_OFFSET 0x39DC +#define GPU3D_TCF_PERFCOUNTER10_SELECT_OFFSET 0x39E0 +#define GPU3D_TCF_PERFCOUNTER10_HI_OFFSET 0x39E4 +#define GPU3D_TCF_PERFCOUNTER10_LOW_OFFSET 0x39E8 +#define GPU3D_TCF_PERFCOUNTER11_SELECT_OFFSET 0x39EC +#define GPU3D_TCF_PERFCOUNTER11_HI_OFFSET 0x39F0 +#define GPU3D_TCF_PERFCOUNTER11_LOW_OFFSET 0x39F4 +#define GPU3D_TCF_DEBUG_OFFSET 0x3B00 +#define GPU3D_TCA_FIFO_DEBUG_OFFSET 0x3B04 +#define GPU3D_TCA_PROBE_DEBUG_OFFSET 0x3B08 +#define GPU3D_TCA_TPC_DEBUG_OFFSET 0x3B0C +#define GPU3D_TCB_CORE_DEBUG_OFFSET 0x3B10 +#define GPU3D_TCB_TAG0_DEBUG_OFFSET 0x3B14 +#define GPU3D_TCB_TAG1_DEBUG_OFFSET 0x3B18 +#define GPU3D_TCB_TAG2_DEBUG_OFFSET 0x3B1C +#define GPU3D_TCB_TAG3_DEBUG_OFFSET 0x3B20 +#define GPU3D_TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_OFFSET 0x3B24 +#define GPU3D_TCB_FETCH_GEN_WALKER_DEBUG_OFFSET 0x3B2C +#define GPU3D_TCB_FETCH_GEN_PIPE0_DEBUG_OFFSET 0x3B30 +#define GPU3D_TCD_INPUT0_DEBUG_OFFSET 0x3B40 +#define GPU3D_TCD_DEGAMMA_DEBUG_OFFSET 0x3B50 +#define GPU3D_TCD_DXTMUX_SCTARB_DEBUG_OFFSET 0x3B54 +#define GPU3D_TCD_DXTC_ARB_DEBUG_OFFSET 0x3B58 +#define GPU3D_TCD_STALLS_DEBUG_OFFSET 0x3B5C +#define GPU3D_TCO_STALLS_DEBUG_OFFSET 0x3B80 +#define GPU3D_TCO_QUAD0_DEBUG0_OFFSET 0x3B84 +#define GPU3D_TCO_QUAD0_DEBUG1_OFFSET 0x3B88 +#define GPU3D_RB_BC_CONTROL_OFFSET 0x3C04 +#define GPU3D_RB_EDRAM_INFO_OFFSET 0x3C08 +#define GPU3D_RB_PERFCOUNTER0_SELECT_OFFSET 0x3C10 +#define GPU3D_RB_PERFCOUNTER0_LOW_OFFSET 0x3C20 +#define GPU3D_RB_PERFCOUNTER0_HI_OFFSET 0x3C24 +#define GPU3D_RB_CRC_RD_PORT_OFFSET 0x3C30 +#define GPU3D_RB_CRC_CONTROL_OFFSET 0x3C34 +#define GPU3D_RB_CRC_MASK_OFFSET 0x3C38 +#define GPU3D_RB_TOTAL_SAMPLES_OFFSET 0x3C3C +#define GPU3D_RB_ZPASS_SAMPLES_OFFSET 0x3C40 +#define GPU3D_RB_ZFAIL_SAMPLES_OFFSET 0x3C44 +#define GPU3D_RB_SFAIL_SAMPLES_OFFSET 0x3C48 +#define GPU3D_RB_DEBUG_0_OFFSET 0x3C98 +#define GPU3D_RB_DEBUG_1_OFFSET 0x3C9C +#define GPU3D_RB_DEBUG_2_OFFSET 0x3CA0 +#define GPU3D_RB_DEBUG_3_OFFSET 0x3CA4 +#define GPU3D_RB_DEBUG_4_OFFSET 0x3CA8 +#define GPU3D_RB_FLAG_CONTROL_OFFSET 0x3CAC +#define GPU3D_RB_BC_SPARES_OFFSET 0x3CB0 +#define GPU3D_RB_SURFACE_INFO_OFFSET 0x8000 +#define GPU3D_RB_COLOR_INFO_OFFSET 0x8004 +#define GPU3D_RB_DEPTH_INFO_OFFSET 0x8008 +#define GPU3D_COHER_DEST_BASE_0_OFFSET 0x8018 +#define GPU3D_COHER_DEST_BASE_1_OFFSET 0x801C +#define GPU3D_COHER_DEST_BASE_2_OFFSET 0x8020 +#define GPU3D_COHER_DEST_BASE_3_OFFSET 0x8024 +#define GPU3D_COHER_DEST_BASE_4_OFFSET 0x8028 +#define GPU3D_COHER_DEST_BASE_5_OFFSET 0x802C +#define GPU3D_COHER_DEST_BASE_6_OFFSET 0x8030 +#define GPU3D_COHER_DEST_BASE_7_OFFSET 0x8034 +#define GPU3D_PA_SC_SCREEN_SCISSOR_TL_OFFSET 0x8038 +#define GPU3D_PA_SC_SCREEN_SCISSOR_BR_OFFSET 0x803C +#define GPU3D_PA_SC_WINDOW_OFFSET_OFFSET 0x8200 +#define GPU3D_PA_SC_WINDOW_SCISSOR_TL_OFFSET 0x8204 +#define GPU3D_PA_SC_WINDOW_SCISSOR_BR_OFFSET 0x8208 +#define GPU3D_VGT_MAX_VTX_INDX_OFFSET 0x8400 +#define GPU3D_VGT_MIN_VTX_INDX_OFFSET 0x8404 +#define GPU3D_VGT_INDX_OFFSET_OFFSET 0x8408 +#define GPU3D_VGT_MULTI_PRIM_IB_RESET_INDX_OFFSET 0x840C +#define GPU3D_RB_COLOR_MASK_OFFSET 0x8410 +#define GPU3D_RB_BLEND_RED_OFFSET 0x8414 +#define GPU3D_RB_BLEND_GREEN_OFFSET 0x8418 +#define GPU3D_RB_BLEND_BLUE_OFFSET 0x841C +#define GPU3D_RB_BLEND_ALPHA_OFFSET 0x8420 +#define GPU3D_RB_FOG_COLOR_OFFSET 0x8424 +#define GPU3D_RB_STENCILREFMASK_BF_OFFSET 0x8430 +#define GPU3D_RB_STENCILREFMASK_OFFSET 0x8434 +#define GPU3D_RB_ALPHA_REF_OFFSET 0x8438 +#define GPU3D_PA_CL_VPORT_XSCALE_OFFSET 0x843C +#define GPU3D_PA_CL_VPORT_XOFFSET_OFFSET 0x8440 +#define GPU3D_PA_CL_VPORT_YSCALE_OFFSET 0x8444 +#define GPU3D_PA_CL_VPORT_YOFFSET_OFFSET 0x8448 +#define GPU3D_PA_CL_VPORT_ZSCALE_OFFSET 0x844C +#define GPU3D_PA_CL_VPORT_ZOFFSET_OFFSET 0x8450 +#define GPU3D_SQ_PROGRAM_CNTL_OFFSET 0x8600 +#define GPU3D_SQ_CONTEXT_MISC_OFFSET 0x8604 +#define GPU3D_SQ_INTERPOLATOR_CNTL_OFFSET 0x8608 +#define GPU3D_SQ_WRAPPING_0_OFFSET 0x860C +#define GPU3D_SQ_WRAPPING_1_OFFSET 0x8610 +#define GPU3D_GFX_COPY_STATE_OFFSET 0x87D0 +#define GPU3D_SQ_CF_RD_BASE_OFFSET 0x87D4 +#define GPU3D_SQ_PS_PROGRAM_OFFSET 0x87D8 +#define GPU3D_SQ_VS_PROGRAM_OFFSET 0x87DC +#define GPU3D_VGT_EVENT_INITIATOR_OFFSET 0x87E4 +#define GPU3D_VGT_DMA_BASE_OFFSET 0x87E8 +#define GPU3D_VGT_DMA_SIZE_OFFSET 0x87EC +#define GPU3D_VGT_DRAW_INITIATOR_OFFSET 0x87F0 +#define GPU3D_VGT_IMMED_DATA_OFFSET 0x87F4 +#define GPU3D_VGT_BIN_BASE_OFFSET 0x87F8 +#define GPU3D_VGT_BIN_SIZE_OFFSET 0x87FC +#define GPU3D_RB_DEPTHCONTROL_OFFSET 0x8800 +#define GPU3D_RB_BLENDCONTROL_OFFSET 0x8804 +#define GPU3D_RB_COLORCONTROL_OFFSET 0x8808 +#define GPU3D_VGT_CURRENT_BIN_ID_MAX_OFFSET 0x880C +#define GPU3D_PA_CL_CLIP_CNTL_OFFSET 0x8810 +#define GPU3D_PA_SU_SC_MODE_CNTL_OFFSET 0x8814 +#define GPU3D_PA_CL_VTE_CNTL_OFFSET 0x8818 +#define GPU3D_VGT_CURRENT_BIN_ID_MIN_OFFSET 0x881C +#define GPU3D_RB_MODECONTROL_OFFSET 0x8820 +#define GPU3D_PA_SU_POINT_SIZE_OFFSET 0x8A00 +#define GPU3D_PA_SU_POINT_MINMAX_OFFSET 0x8A04 +#define GPU3D_PA_SU_LINE_CNTL_OFFSET 0x8A08 +#define GPU3D_PA_SC_LINE_STIPPLE_OFFSET 0x8A0C +#define GPU3D_PA_SC_VIZ_QUERY_OFFSET 0x8A4C +#define GPU3D_VGT_ENHANCE_OFFSET 0x8A50 +#define GPU3D_PA_SC_LINE_CNTL_OFFSET 0x8C00 +#define GPU3D_PA_SC_AA_CONFIG_OFFSET 0x8C04 +#define GPU3D_PA_SU_VTX_CNTL_OFFSET 0x8C08 +#define GPU3D_PA_CL_GB_VERT_CLIP_ADJ_OFFSET 0x8C0C +#define GPU3D_PA_CL_GB_VERT_DISC_ADJ_OFFSET 0x8C10 +#define GPU3D_PA_CL_GB_HORZ_CLIP_ADJ_OFFSET 0x8C14 +#define GPU3D_PA_CL_GB_HORZ_DISC_ADJ_OFFSET 0x8C18 +#define GPU3D_SQ_VS_CONST_OFFSET 0x8C1C +#define GPU3D_SQ_PS_CONST_OFFSET 0x8C20 +#define GPU3D_PA_SC_AA_MASK_OFFSET 0x8C48 +#define GPU3D_VGT_VERTEX_REUSE_BLOCK_CNTL_OFFSET 0x8C58 +#define GPU3D_VGT_OUT_DEALLOC_CNTL_OFFSET 0x8C5C +#define GPU3D_RB_COPY_CONTROL_OFFSET 0x8C60 +#define GPU3D_RB_COPY_DEST_BASE_OFFSET 0x8C64 +#define GPU3D_RB_COPY_DEST_PITCH_OFFSET 0x8C68 +#define GPU3D_RB_COPY_DEST_INFO_OFFSET 0x8C6C +#define GPU3D_RB_COPY_DEST_PIXEL_OFFSET_OFFSET 0x8C70 +#define GPU3D_RB_DEPTH_CLEAR_OFFSET 0x8C74 +#define GPU3D_RB_SAMPLE_COUNT_CTL_OFFSET 0x8C90 +#define GPU3D_RB_SAMPLE_COUNT_ADDR_OFFSET 0x8C94 +#define GPU3D_RB_COLOR_DEST_MASK_OFFSET 0x8C98 +#define GPU3D_PA_SU_POLY_OFFSET_FRONT_SCALE_OFFSET 0x8E00 +#define GPU3D_PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET 0x8E04 +#define GPU3D_PA_SU_POLY_OFFSET_BACK_SCALE_OFFSET 0x8E08 +#define GPU3D_PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET 0x8E0C +#define GPU3D_SQ_CONSTANT_0_OFFSET 0x10000 +#define GPU3D_SQ_CONSTANT_1_OFFSET 0x10004 +#define GPU3D_SQ_CONSTANT_2_OFFSET 0x10008 +#define GPU3D_SQ_CONSTANT_3_OFFSET 0x1000C +#define GPU3D_SQ_FETCH_0_OFFSET 0x12000 +#define GPU3D_SQ_FETCH_1_OFFSET 0x12004 +#define GPU3D_SQ_FETCH_2_OFFSET 0x12008 +#define GPU3D_SQ_FETCH_3_OFFSET 0x1200C +#define GPU3D_SQ_FETCH_4_OFFSET 0x12010 +#define GPU3D_SQ_FETCH_5_OFFSET 0x12014 +#define GPU3D_SQ_CF_BOOLEANS_OFFSET 0x12400 +#define GPU3D_SQ_CF_LOOP_OFFSET 0x12420 +#define GPU3D_SQ_INSTRUCTION_ALU_0_OFFSET 0x14000 +#define GPU3D_SQ_INSTRUCTION_ALU_1_OFFSET 0x14004 +#define GPU3D_SQ_INSTRUCTION_ALU_2_OFFSET 0x14008 +#define GPU3D_SQ_INSTRUCTION_VFETCH_0_OFFSET 0x14100 +#define GPU3D_SQ_INSTRUCTION_VFETCH_1_OFFSET 0x14104 +#define GPU3D_SQ_INSTRUCTION_VFETCH_2_OFFSET 0x14108 +#define GPU3D_SQ_INSTRUCTION_TFETCH_0_OFFSET 0x1410C +#define GPU3D_SQ_INSTRUCTION_TFETCH_1_OFFSET 0x14110 +#define GPU3D_SQ_INSTRUCTION_TFETCH_2_OFFSET 0x14114 +#define GPU3D_SQ_INSTRUCTION_CF_EXEC_0_OFFSET 0x14200 +#define GPU3D_SQ_INSTRUCTION_CF_EXEC_1_OFFSET 0x14204 +#define GPU3D_SQ_INSTRUCTION_CF_EXEC_2_OFFSET 0x14208 +#define GPU3D_SQ_INSTRUCTION_CF_LOOP_0_OFFSET 0x1420C +#define GPU3D_SQ_INSTRUCTION_CF_LOOP_1_OFFSET 0x14210 +#define GPU3D_SQ_INSTRUCTION_CF_LOOP_2_OFFSET 0x14214 +#define GPU3D_SQ_INSTRUCTION_CF_JMP_CALL_0_OFFSET 0x14218 +#define GPU3D_SQ_INSTRUCTION_CF_JMP_CALL_1_OFFSET 0x1421C +#define GPU3D_SQ_INSTRUCTION_CF_JMP_CALL_2_OFFSET 0x14220 +#define GPU3D_SQ_INSTRUCTION_CF_ALLOC_0_OFFSET 0x14224 +#define GPU3D_SQ_INSTRUCTION_CF_ALLOC_1_OFFSET 0x14228 +#define GPU3D_SQ_INSTRUCTION_CF_ALLOC_2_OFFSET 0x1422C + +//######################################### +//# GPU2D - OPENVG registers +//######################################### +#define GPU2D_BASE_ADDR OPENVG_BASE_ADDR + +#define GPU2D_WR_IRQENABLE_OFFSET 0x438 +#define GPU2D_WR_IRQENABLE (GPU2D_BASE_ADDR+GPU2D_WR_IRQENABLE_OFFSET) +#define GPU2D_RD_IRQENABLE_OFFSET 0x038 +#define GPU2D_RD_IRQENABLE (GPU2D_BASE_ADDR+GPU2D_RD_IRQENABLE_OFFSET) + +//######################################### +//# L2CC Program control registers +//######################################### +#define L2CC_R0_CACHE_ID_OFFSET 0x0000 +#define L2CC_R0_CACHE_TYPE_OFFSET 0x0004 +#define L2CC_R1_CNTL_OFFSET 0x0100 +#define L2CC_R1_AUX_CNTL_OFFSET 0x0104 +#define L2CC_R2_EVENT_CNT_CNTL_OFFSET 0x0200 +#define L2CC_R2_EVENT_CNT1_CONFIG_OFFSET 0x0204 +#define L2CC_R2_EVENT_CNT0_CONFIG_OFFSET 0x0208 +#define L2CC_R2_EVENT_CNT1_VALUE_OFFSET 0x020C +#define L2CC_R2_EVENT_CNT0_VALUE_OFFSET 0x0210 +#define L2CC_R2_INT_MASK_OFFSET 0x0214 +#define L2CC_R2_MASKED_INT_STATUS_OFFSET 0x0218 +#define L2CC_R2_RAW_INT_STATUS_OFFSET 0x021C +#define L2CC_R2_INT_CLEAR_OFFSET 0x0220 +#define L2CC_R7_CACHE_SYNC_OFFSET 0x0730 +#define L2CC_R7_INVAL_BY_PA_OFFSET 0x0770 +#define L2CC_R7_INVAL_BY_WAY_OFFSET 0x077C +#define L2CC_R7_CLEAN_BY_PA_OFFSET 0x07B0 +#define L2CC_R7_CLEAN_BY_IDXWAY_OFFSET 0x07B8 +#define L2CC_R7_CLEAN_BY_WAY_OFFSET 0x07BC +#define L2CC_R7_CLEANINVAL_LINE_BY_PA_OFFSET 0x07F0 +#define L2CC_R7_CLEANINVAL_LINE_BY_IDXWAY_OFFSET 0x07FB +#define L2CC_R7_CLEANINVAL_BY_WAY_OFFSET 0x07FC +#define L2CC_R9_LOCKDOWN_BY_WAY_D_OFFSET 0x0900 +#define L2CC_R9_LOCKDOWN_BY_WAY_I_OFFSET 0x0904 +#define L2CC_R15_TEST_OPER_OFFSET 0x0F00 +#define L2CC_R15_LINE_DATA_0_OFFSET 0x0F10 +#define L2CC_R15_LINE_DATA_1_OFFSET 0x0F14 +#define L2CC_R15_LINE_DATA_2_OFFSET 0x0F18 +#define L2CC_R15_LINE_DATA_3_OFFSET 0x0F1C +#define L2CC_R15_LINE_DATA_4_OFFSET 0x0F20 +#define L2CC_R15_LINE_DATA_5_OFFSET 0x0F24 +#define L2CC_R15_LINE_DATA_6_OFFSET 0x0F28 +#define L2CC_R15_LINE_DATA_7_OFFSET 0x0F2C +#define L2CC_R15_LINE_TAG_OFFSET 0x0F30 +#define L2CC_R15_DBG_CNTL_OFFSET 0x0F40 +//######################################### +//# EVTMON +//######################################### +#define EVTMON_EMMC_OFFSET 0x000 +#define EVTMON_EMCS_OFFSET 0x004 +#define EVTMON_EMCC0_OFFSET 0x008 +#define EVTMON_EMCC1_OFFSET 0x00c +#define EVTMON_EMCC2_OFFSET 0x010 +#define EVTMON_EMCC3_OFFSET 0x014 +#define EVTMON_EMCC4_OFFSET 0x018 +#define EVTMON_EMCC5_OFFSET 0x01c +#define EVTMON_EMC0_OFFSET 0x020 +#define EVTMON_EMC1_OFFSET 0x024 +#define EVTMON_EMC2_OFFSET 0x028 +#define EVTMON_EMC3_OFFSET 0x02c +#define EVTMON_EMC4_OFFSET 0x030 +#define EVTMON_EMC5_OFFSET 0x034 +#define EVTMON_PNNC0_OFFSET 0x040 +#define EVTMON_PNNC1_OFFSET 0x044 +#define EVTMON_PNNC2_OFFSET 0x048 +#define EVTMON_CCNT_OFFSET 0x04c +#define EVTMON_PMN0_OFFSET 0x050 +#define EVTMON_PMN1_OFFSET 0x054 +#define EVTMON_PMN2_OFFSET 0x058 +#define EVTMON_PMN3_OFFSET 0x05c +#define EVTMON_PMN4_OFFSET 0x060 +#define EVTMON_PMN5_OFFSET 0x064 +//######################################### +//# Debug ROM +//######################################### + +//######################################### +//# ETB +//######################################### + +//######################################### +//# ETM +//######################################### + +//######################################### +//# TPIU +//######################################### + +//######################################### +//# CTI +//######################################### +#define CTICONTROL_OFFSET 0x000 +#define CTIINTACK_OFFSET 0x010 +#define CTIAPPSET_OFFSET 0x014 +#define CTIAPPCLEAR_OFFSET 0x018 +#define CTIAPPPULSE_OFFSET 0x01C +#define CTIINEN0_OFFSET 0x020 +#define CTIINEN1_OFFSET 0x024 +#define CTIINEN2_OFFSET 0x028 +#define CTIINEN3_OFFSET 0x02C +#define CTIINEN4_OFFSET 0x030 +#define CTIINEN5_OFFSET 0x034 +#define CTIINEN6_OFFSET 0x038 +#define CTIINEN7_OFFSET 0x03C +#define CTIOUTEN0_OFFSET 0x0A0 +#define CTIOUTEN1_OFFSET 0x0A4 +#define CTIOUTEN2_OFFSET 0x0A8 +#define CTIOUTEN3_OFFSET 0x0AC +#define CTIOUTEN4_OFFSET 0x0B0 +#define CTIOUTEN5_OFFSET 0x0B4 +#define CTIOUTEN6_OFFSET 0x0B8 +#define CTIOUTEN7_OFFSET 0x0BC +#define CTITRIGINSTATUS_OFFSET 0x130 +#define CTITRIGOUTSTATUS_OFFSET 0x134 +#define CTICHINSTATUS_OFFSET 0x138 +#define CTICHOUTSTATUS_OFFSET 0x13C +#define CTIGATE_OFFSET 0x140 +#define ASICCTL_OFFSET 0x144 +#define CTS_OFFSET 0xFA0 +#define CTC_OFFSET 0xFA4 +#define ITCR_OFFSET 0xF00 +#define ITCHINACK_OFFSET 0xEDC +#define ITTRIGINACK_OFFSET 0xEE0 +#define ITCHOUT_OFFSET 0xEE4 +#define ITTRIGOUT_OFFSET 0xEE8 +#define ITCHOUTACK_OFFSET 0xEEC +#define ITTRIGOUTACK_OFFSET 0xEF0 +#define ITCHIN_OFFSET 0xEF4 +#define ITTRIGIN_OFFSET 0xEF8 +#define CTILOCK_OFFSET 0xFB0 +#define CTILOCKSTATUS_OFFSET 0xFB4 +#define AUTHENSTATUS_OFFSET 0xFB8 +#define DEVICEID_OFFSET 0xFC8 +#define DEVICETYPEID_OFFSET 0xFCC +#define PERIPHID0_OFFSET 0xFE0 +#define PERIPHID1_OFFSET 0xFE4 +#define PERIPHID2_OFFSET 0xFE8 +#define PERIPHID3_OFFSET 0xFEC +#define PERIPHID4_OFFSET 0xFD0 +#define COMPONENTID0_OFFSET 0xFF0 +#define COMPONENTID1_OFFSET 0xFF4 +#define COMPONENTID2_OFFSET 0xFF8 +#define COMPONENTID3_OFFSET 0xFFC + +//######################################### +//# Debug Data Funnel +//######################################### + +//######################################### +//# CSD0 SDRAM/DDR +//######################################### + +//######################################### +//# CSD1 SDRAM/DDR +//######################################### + +//######################################### +//# CS0 (Flash) 128MB +//######################################### + +//######################################### +//# CS1 (Flash) 64MB +//######################################### + +//######################################### +//# CS2 (sram) +//######################################### + +//######################################### +//# CS3 (Spare) +//######################################### + +//######################################### +//# CS4 (Spare) +//######################################### + +//######################################### +//# CS5 (spare) +//######################################### + +//######################################### +//# Nand Flash +//######################################### + +//######################################### +//# MMDC registers +//######################################### + +//DDR LOGIC +#define MDCTL_OFFSET 0x00 +#define MDPDC_OFFSET 0x04 +#define MDOTC_OFFSET 0x08 +#define MDCFG0_OFFSET 0x0C +#define MDCFG1_OFFSET 0x10 +#define MDCFG2_OFFSET 0x14 +#define MDMISC_OFFSET 0x18 +#define MDSCR_OFFSET 0x1C +#define MDREF_OFFSET 0x20 +#define MDWCC_OFFSET 0x24 +#define MDRCC_OFFSET 0x28 +#define MDRWD_OFFSET 0x2C +#define MDOR_OFFSET 0x30 +#define MDMRR_OFFSET 0x34 +#define MDCFG3LP_OFFSET 0x38 +#define MDMR4_OFFSET 0x3C +#define MDASP_OFFSET 0x40 + +//ADOPT +#define ADOPT_BASE_ADDR 0x400 +#define MAARCR_OFFSET ADOPT_BASE_ADDR + 0x00 // ARCR +#define MAPSR_OFFSET ADOPT_BASE_ADDR + 0x04 // PSR (former MCR0 and PSM0) +#define MAEXIDR0_OFFSET ADOPT_BASE_ADDR + 0x08 // Exclusive ID Monitor register0 +#define MAEXIDR1_OFFSET ADOPT_BASE_ADDR + 0x0c // Exclusive ID Monitor register1 +#define MADPCR0_OFFSET ADOPT_BASE_ADDR + 0x10 // Debug and Profiling Control register0 +#define MADPCR1_OFFSET ADOPT_BASE_ADDR + 0x14 // Debug and Profiling Control register1 +#define MADPSR0_OFFSET ADOPT_BASE_ADDR + 0x18 // Debug and Profiling Control register0 +#define MADPSR1_OFFSET ADOPT_BASE_ADDR + 0x1c // Debug and Profiling Control register1 +#define MADPSR2_OFFSET ADOPT_BASE_ADDR + 0x20 // Debug and Profiling Control register2 +#define MADPSR3_OFFSET ADOPT_BASE_ADDR + 0x24 // Debug and Profiling Control register3 +#define MADPSR4_OFFSET ADOPT_BASE_ADDR + 0x28 // Debug and Profiling Control register2 +#define MADPSR5_OFFSET ADOPT_BASE_ADDR + 0x2c // Debug and Profiling Control register2 +#define MASBS0_OFFSET ADOPT_BASE_ADDR + 0x30 // Step by Step Address +#define MASBS1_OFFSET ADOPT_BASE_ADDR + 0x34 // Step by Step Controls +#define MAGENP_OFFSET ADOPT_BASE_ADDR + 0x40 // General purpose register + +//DDR_PHY +#define PHY_BASE_ADDR 0x800 +#define MPZQHWCTRL_OFFSET PHY_BASE_ADDR + 0x00 +#define MPZQSWCTRL_OFFSET PHY_BASE_ADDR + 0x04 +#define MPWLGCR_OFFSET PHY_BASE_ADDR + 0x08 +#define MPWLDECTRL0_OFFSET PHY_BASE_ADDR + 0x0C +#define MPWLDECTRL1_OFFSET PHY_BASE_ADDR + 0x10 +#define MPWLDLST_OFFSET PHY_BASE_ADDR + 0x14 +#define MPODTCTRL_OFFSET PHY_BASE_ADDR + 0x18 +#define MPREDQBY0DL_OFFSET PHY_BASE_ADDR + 0x1C +#define MPREDQBY1DL_OFFSET PHY_BASE_ADDR + 0x20 +#define MPREDQBY2DL_OFFSET PHY_BASE_ADDR + 0x24 +#define MPREDQBY3DL_OFFSET PHY_BASE_ADDR + 0x28 +#define MPWRDQBY0DL_OFFSET PHY_BASE_ADDR + 0x2C +#define MPWRDQBY1DL_OFFSET PHY_BASE_ADDR + 0x30 +#define MPWRDQBY2DL_OFFSET PHY_BASE_ADDR + 0x34 +#define MPWRDQBY3DL_OFFSET PHY_BASE_ADDR + 0x38 +#define MPDGCTRL0_OFFSET PHY_BASE_ADDR + 0x3C +#define MPDGCTRL1_OFFSET PHY_BASE_ADDR + 0x40 +#define MPDGDLST_OFFSET PHY_BASE_ADDR + 0x44 +#define MPRDDLCTL_OFFSET PHY_BASE_ADDR + 0x48 +#define MPRDDLST_OFFSET PHY_BASE_ADDR + 0x4C +#define MPWRDLCTL_OFFSET PHY_BASE_ADDR + 0x50 +#define MPWRDLST_OFFSET PHY_BASE_ADDR + 0x54 +#define MPSDCTRL_OFFSET PHY_BASE_ADDR + 0x58 +#define MPZQLP2CTL_OFFSET PHY_BASE_ADDR + 0x5C +#define MPRDDLHWCTL_OFFSET PHY_BASE_ADDR + 0x60 +#define MPWRDLHWCTL_OFFSET PHY_BASE_ADDR + 0x64 +#define MPRDDLHWST0_OFFSET PHY_BASE_ADDR + 0x68 +#define MPRDDLHWST1_OFFSET PHY_BASE_ADDR + 0x6C +#define MPWRDLHWST0_OFFSET PHY_BASE_ADDR + 0x70 +#define MPWRDLHWST1_OFFSET PHY_BASE_ADDR + 0x74 +#define MPWLHWERR_OFFSET PHY_BASE_ADDR + 0x78 +#define MPDGHWST0_OFFSET PHY_BASE_ADDR + 0x7C +#define MPDGHWST1_OFFSET PHY_BASE_ADDR + 0x80 +#define MPDGHWST2_OFFSET PHY_BASE_ADDR + 0x84 +#define MPDGHWST3_OFFSET PHY_BASE_ADDR + 0x88 +#define MPPDCMPR1_OFFSET PHY_BASE_ADDR + 0x8C +#define MPPDCMPR2_OFFSET PHY_BASE_ADDR + 0x90 +#define MPSWDAR_OFFSET PHY_BASE_ADDR + 0x94 +#define MPSWDRDR0_OFFSET PHY_BASE_ADDR + 0x98 +#define MPSWDRDR1_OFFSET PHY_BASE_ADDR + 0x9C +#define MPSWDRDR2_OFFSET PHY_BASE_ADDR + 0xA0 +#define MPSWDRDR3_OFFSET PHY_BASE_ADDR + 0xA4 +#define MPSWDRDR4_OFFSET PHY_BASE_ADDR + 0xA8 +#define MPSWDRDR5_OFFSET PHY_BASE_ADDR + 0xAC +#define MPSWDRDR6_OFFSET PHY_BASE_ADDR + 0xB0 +#define MPSWDRDR7_OFFSET PHY_BASE_ADDR + 0xB4 +#define MPMUR_OFFSET PHY_BASE_ADDR + 0xB8 +#define MPWRCADL_OFFSET PHY_BASE_ADDR + 0xBC +#define MPDCCR_OFFSET PHY_BASE_ADDR + 0xC0 +#define MPBC_OFFSET PHY_BASE_ADDR + 0xC4 + +//######################################### +//# WEIM registers +//######################################### +#define WEIM_CS0_CTL_REG 0x000 +#define WEIM_CS0_CTL_REG2 0x004 +#define WEIM_CS0_RD_CTL_REG1 0x008 +#define WEIM_CS0_RD_CTL_REG2 0x00C +#define WEIM_CS0_WR_CTL_REG 0x010 +#define WEIM_CS0_WR_CTL_REG2 0x014 +#define WEIM_CS1_CTL_REG 0x018 +#define WEIM_CS1_CTL_REG2 0x01C +#define WEIM_CS1_RD_CTL_REG1 0x020 +#define WEIM_CS1_RD_CTL_REG2 0x024 +#define WEIM_CS1_WR_CTL_REG 0x028 +#define WEIM_CS1_WR_CTL_REG2 0x02C +#define WEIM_CS2_CTL_REG 0x030 +#define WEIM_CS2_CTL_REG2 0x034 +#define WEIM_CS2_RD_CTL_REG1 0x038 +#define WEIM_CS2_RD_CTL_REG2 0x03c +#define WEIM_CS2_WR_CTL_REG 0x040 +#define WEIM_CS2_WR_CTL_REG2 0x044 +#define WEIM_CS3_CTL_REG 0x048 +#define WEIM_CS3_CTL_REG2 0x04C +#define WEIM_CS3_RD_CTL_REG1 0x050 +#define WEIM_CS3_RD_CTL_REG2 0x054 +#define WEIM_CS3_WR_CTL_REG 0x058 +#define WEIM_CS3_WR_CTL_REG2 0x05c +#define WEIM_CS4_CTL_REG 0x060 +#define WEIM_CS4_CTL_REG2 0x064 +#define WEIM_CS4_RD_CTL_REG1 0x068 +#define WEIM_CS4_RD_CTL_REG2 0x06C +#define WEIM_CS4_WR_CTL_REG 0x070 +#define WEIM_CS4_WR_CTL_REG2 0x074 +#define WEIM_CS5_CTL_REG 0x078 +#define WEIM_CS5_CTL_REG2 0x07c +#define WEIM_CS5_RD_CTL_REG1 0x080 +#define WEIM_CS5_RD_CTL_REG2 0x084 +#define WEIM_CS5_WR_CTL_REG 0x088 +#define WEIM_CS5_WR_CTL_REG2 0x08c +#define WEIM_CONFIG_REG 0x090 +#define WEIM_IP_ACCESS_REG 0x094 +#define WEIM_ERR_ADDR_REG 0x098 + +#define WEIM_CS0_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS0_CTL_REG +#define WEIM_CS0_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS0_CTL_REG2 +#define WEIM_CS0_RD_CTL_REG1_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS0_RD_CTL_REG1 +#define WEIM_CS0_RD_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS0_RD_CTL_REG2 +#define WEIM_CS0_WR_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS0_WR_CTL_REG +#define WEIM_CS0_WR_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS0_WR_CTL_REG2 +#define WEIM_CS1_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS1_CTL_REG +#define WEIM_CS1_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS1_CTL_REG2 +#define WEIM_CS1_RD_CTL_REG1_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS1_RD_CTL_REG1 +#define WEIM_CS1_RD_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS1_RD_CTL_REG2 +#define WEIM_CS1_WR_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS1_WR_CTL_REG +#define WEIM_CS1_WR_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS1_WR_CTL_REG2 +#define WEIM_CS2_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS2_CTL_REG +#define WEIM_CS2_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS2_CTL_REG2 +#define WEIM_CS2_RD_CTL_REG1_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS2_RD_CTL_REG1 +#define WEIM_CS2_RD_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS2_RD_CTL_REG2 +#define WEIM_CS2_WR_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS2_WR_CTL_REG +#define WEIM_CS2_WR_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS2_WR_CTL_REG2 +#define WEIM_CS3_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS3_CTL_REG +#define WEIM_CS3_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS3_CTL_REG2 +#define WEIM_CS3_RD_CTL_REG1_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS3_RD_CTL_REG1 +#define WEIM_CS3_RD_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS3_RD_CTL_REG2 +#define WEIM_CS3_WR_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS3_WR_CTL_REG +#define WEIM_CS3_WR_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS3_WR_CTL_REG2 +#define WEIM_CS4_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS4_CTL_REG +#define WEIM_CS4_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS4_CTL_REG2 +#define WEIM_CS4_RD_CTL_REG1_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS4_RD_CTL_REG1 +#define WEIM_CS4_RD_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS4_RD_CTL_REG2 +#define WEIM_CS4_WR_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS4_WR_CTL_REG +#define WEIM_CS4_WR_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS4_WR_CTL_REG2 +#define WEIM_CS5_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS5_CTL_REG +#define WEIM_CS5_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS5_CTL_REG2 +#define WEIM_CS5_RD_CTL_REG1_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS5_RD_CTL_REG1 +#define WEIM_CS5_RD_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS5_RD_CTL_REG2 +#define WEIM_CS5_WR_CTL_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS5_WR_CTL_REG +#define WEIM_CS5_WR_CTL_REG2_ADDR WEIM_IPS_BASE_ADDR+WEIM_CS5_WR_CTL_REG2 +#define WEIM_CONFIG_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_CONFIG_REG +#define WEIM_IP_ACCESS_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_IP_ACCESS_REG +#define WEIM_ERR_ADDR_REG_ADDR WEIM_IPS_BASE_ADDR+WEIM_ERR_ADDR_REG + +//######################################### +//# AIPS 1 off platform global module enable no.1 +//######################################### +#define AIPS_MPROT0_7_OFFSET 0x00 +#define AIPS_MPROT8_15_OFFSET 0x04 +#define AIPS_PACR0_7_OFFSET 0x20 +#define AIPS_PACR8_15_OFFSET 0x24 +#define AIPS_PACR16_23_OFFSET 0x28 +#define AIPS_PACR24_31_OFFSET 0x2C +#define AIPS_OPACR0_7_OFFSET 0x40 +#define AIPS_OPACR8_15_OFFSET 0x44 +#define AIPS_OPACR16_23_OFFSET 0x48 +#define AIPS_OPACR24_31_OFFSET 0x4C +#define AIPS_OPACR32_33_OFFSET 0x50 + +//######################################### +//# CSU +//######################################### +#define CSU_CSL0_OFFSET 0x0 +#define CSU_CSL1_OFFSET 0x4 +#define CSU_CSL2_OFFSET 0x8 +#define CSU_CSL3_OFFSET 0xC +#define CSU_CSL4_OFFSET 0x10 +#define CSU_CSL5_OFFSET 0x14 +#define CSU_CSL6_OFFSET 0x18 +#define CSU_CSL7_OFFSET 0x1C +#define CSU_CSL8_OFFSET 0x20 +#define CSU_CSL9_OFFSET 0x24 +#define CSU_CSL10_OFFSET 0x28 +#define CSU_CSL11_OFFSET 0x2C +#define CSU_CSL12_OFFSET 0x30 +#define CSU_CSL13_OFFSET 0x34 +#define CSU_CSL14_OFFSET 0x38 +#define CSU_CSL15_OFFSET 0x3C +#define CSU_CSL16_OFFSET 0x40 +#define CSU_CSL17_OFFSET 0x44 +#define CSU_CSL18_OFFSET 0x48 +#define CSU_CSL19_OFFSET 0x4C +#define CSU_CSL20_OFFSET 0x50 +#define CSU_CSL21_OFFSET 0x54 +#define CSU_CSL22_OFFSET 0x58 +#define CSU_CSL23_OFFSET 0x5C +#define CSU_CSL24_OFFSET 0x60 +#define CSU_CSL25_OFFSET 0x64 +#define CSU_CSL26_OFFSET 0x68 +#define CSU_CSL27_OFFSET 0x6C +#define CSU_CSL28_OFFSET 0x70 +#define CSU_CSL29_OFFSET 0x74 +#define CSU_CSL30_OFFSET 0x78 +#define CSU_CSL31_OFFSET 0x7C +#define CSU_CSL32_OFFSET 0x80 +#define CSU_CSL33_OFFSET 0x84 +#define CSU_CSL34_OFFSET 0x88 +#define CSU_CSL35_OFFSET 0x8C +#define CSU_CSL36_OFFSET 0x90 +#define CSU_CSL37_OFFSET 0x94 +#define CSU_CSL38_OFFSET 0x98 +#define CSU_CSL39_OFFSET 0x9C +#define CSU_CSL40_OFFSET 0xA0 +#define CSU_CSL41_OFFSET 0xA4 +#define CSU_CSL42_OFFSET 0xA8 +#define CSU_CSL43_OFFSET 0xAC +#define CSU_CSL44_OFFSET 0xB0 +#define CSU_CSL45_OFFSET 0xB4 +#define CSU_CSL46_OFFSET 0xB8 +#define CSU_CSL47_OFFSET 0xBC +#define CSU_CSL48_OFFSET 0xC0 +#define CSU_CSL49_OFFSET 0xC4 +#define CSU_CSL50_OFFSET 0xC8 +#define CSU_CSL51_OFFSET 0xCC +#define CSU_CSL52_OFFSET 0xD0 +#define CSU_CSL53_OFFSET 0xD4 +#define CSU_CSL54_OFFSET 0xD8 +#define CSU_CSL55_OFFSET 0xDC +#define CSU_CSL56_OFFSET 0xE0 +#define CSU_CSL57_OFFSET 0xE4 +#define CSU_CSL58_OFFSET 0xE8 +#define CSU_CSL59_OFFSET 0xEC +#define CSU_CSL60_OFFSET 0xF0 +#define CSU_CSL61_OFFSET 0xF4 +#define CSU_CSL62_OFFSET 0xF8 +#define CSU_CSL63_OFFSET 0xFC +#define CSU_HP0_OFFSET 0x200 +#define CSU_HP1_OFFSET 0x204 +#define CSU_SA0_OFFSET 0x218 +#define CSU_SA1_OFFSET 0x21C +#define CSU_AMASK0_OFFSET 0x230 +#define CSU_AMASK1_OFFSET 0x234 +#define CSU_AROUT0_OFFSET 0x244 +#define CSU_AROUT1_OFFSET 0x248 +#define CSU_AROUT2_OFFSET 0x24C +#define CSU_AROUT3_OFFSET 0x250 +#define CSU_AROUT4_OFFSET 0x254 +#define CSU_AROUT5_OFFSET 0x258 +#define CSU_AROUT6_OFFSET 0x25C +#define CSU_AROUT7_OFFSET 0x260 +#define CSU_AROUT8_OFFSET 0x264 +#define CSU_AROUT9_OFFSET 0x268 +#define CSU_AROUT10_OFFSET 0x26C +#define CSU_AROUT11_OFFSET 0x270 +#define CSU_AROUT12_OFFSET 0x274 +#define CSU_AROUT13_OFFSET 0x278 +#define CSU_AROUT14_OFFSET 0x27C +#define CSU_AROUT15_OFFSET 0x280 +#define CSU_AROUT16_OFFSET 0x284 +#define CSU_AROUT17_OFFSET 0x288 +#define CSU_AROUT18_OFFSET 0x28C +#define CSU_AROUT19_OFFSET 0x290 +#define CSU_AROUT20_OFFSET 0x294 +#define CSU_AROUT21_OFFSET 0x298 +#define CSU_AROUT22_OFFSET 0x29C +#define CSU_AROUT23_OFFSET 0x2A0 +#define CSU_AROUT24_OFFSET 0x2A4 +#define CSU_AROUT25_OFFSET 0x2A8 +#define CSU_AROUT26_OFFSET 0x2AC +#define CSU_AROUT27_OFFSET 0x2B0 +#define CSU_AROUT28_OFFSET 0x2B4 +#define CSU_AROUT29_OFFSET 0x2B8 +#define CSU_AROUT30_OFFSET 0x2BC +#define CSU_AROUT31_OFFSET 0x2C0 +#define CSU_ASOFT0_OFFSET 0x344 +#define CSU_ACOUNTER0_OFFSET 0x348 +#define CSU_ACONTROL0_OFFSET 0x34C +#define CSU_HPCONTROL0_OFFSET 0x358 +#define CSU_HPCONTROL1_OFFSET 0x35C +#define CSU_ICR0_OFFSET 0x368 +#define CSU_ICR1_OFFSET 0x36C +#define CSU_ISR0_OFFSET 0x378 +#define CSU_ISR1_OFFSET 0x37C +//######################################### +//# SDMA(pors IPS_HOST) +//######################################### +#define SDMA_MC0PTR_OFFSET 0x00 +#define SDMA_INTR_OFFSET 0x04 +#define SDMA_STOP_STAT_OFFSET 0x08 +#define SDMA_HSTART_OFFSET 0x0C +#define SDMA_EVTOVR_OFFSET 0x10 +#define SDMA_DSPOVR_OFFSET 0x14 +#define SDMA_HOSTOVR_OFFSET 0x18 +#define SDMA_EVTPEND_OFFSET 0x1C +#define SDMA_DSPENBL_OFFSET 0x20 +#define SDMA_RESET_OFFSET 0x24 +#define SDMA_EVTERR_OFFSET 0x28 +#define SDMA_INTRMASK_OFFSET 0x2C +#define SDMA_PSW_OFFSET 0x30 +#define SDMA_EVTERRDBG_OFFSET 0x34 +#define SDMA_CONFIG_OFFSET 0x38 +#define SDMA_LOCK_OFFSET 0x3C +#define SDMA_ONCE_ENB_OFFSET 0x40 +#define SDMA_ONCE_DATA_OFFSET 0x44 +#define SDMA_ONCE_INSTR_OFFSET 0x48 +#define SDMA_ONCE_STAT_OFFSET 0x4C +#define SDMA_ONCE_CMD_OFFSET 0x50 +#define SDMA_ILLINSTADDR_OFFSET 0x58 +#define SDMA_CHN0ADDR_OFFSET 0x5C +#define SDMA_EVT_MIRROR_OFFSET 0x60 +#define SDMA_EVT_MIRROR2_OFFSET 0x64 +#define SDMA_XTRIG_CONF1_OFFSET 0x70 +#define SDMA_XTRIG_CONF2_OFFSET 0x74 +#define SDMA_CHNPRI00_OFFSET 0x100 +#define SDMA_CHNPRI01_OFFSET 0x104 +#define SDMA_CHNPRI02_OFFSET 0x108 +#define SDMA_CHNPRI03_OFFSET 0x10C +#define SDMA_CHNPRI04_OFFSET 0x110 +#define SDMA_CHNPRI05_OFFSET 0x114 +#define SDMA_CHNPRI06_OFFSET 0x118 +#define SDMA_CHNPRI07_OFFSET 0x11C +#define SDMA_CHNPRI08_OFFSET 0x120 +#define SDMA_CHNPRI09_OFFSET 0x124 +#define SDMA_CHNPRI10_OFFSET 0x128 +#define SDMA_CHNPRI11_OFFSET 0x12C +#define SDMA_CHNPRI12_OFFSET 0x130 +#define SDMA_CHNPRI13_OFFSET 0x134 +#define SDMA_CHNPRI14_OFFSET 0x138 +#define SDMA_CHNPRI15_OFFSET 0x13C +#define SDMA_CHNPRI16_OFFSET 0x140 +#define SDMA_CHNPRI17_OFFSET 0x144 +#define SDMA_CHNPRI18_OFFSET 0x148 +#define SDMA_CHNPRI19_OFFSET 0x14C +#define SDMA_CHNPRI20_OFFSET 0x150 +#define SDMA_CHNPRI21_OFFSET 0x154 +#define SDMA_CHNPRI22_OFFSET 0x158 +#define SDMA_CHNPRI23_OFFSET 0x15C +#define SDMA_CHNPRI24_OFFSET 0x160 +#define SDMA_CHNPRI25_OFFSET 0x164 +#define SDMA_CHNPRI26_OFFSET 0x168 +#define SDMA_CHNPRI27_OFFSET 0x16C +#define SDMA_CHNPRI28_OFFSET 0x170 +#define SDMA_CHNPRI29_OFFSET 0x174 +#define SDMA_CHNPRI30_OFFSET 0x178 +#define SDMA_CHNPRI31_OFFSET 0x17C +#define SDMA_CHNENBL00_OFFSET 0x200 +#define SDMA_CHNENBL01_OFFSET 0x204 +#define SDMA_CHNENBL02_OFFSET 0x208 +#define SDMA_CHNENBL03_OFFSET 0x20C +#define SDMA_CHNENBL04_OFFSET 0x210 +#define SDMA_CHNENBL05_OFFSET 0x214 +#define SDMA_CHNENBL06_OFFSET 0x218 +#define SDMA_CHNENBL07_OFFSET 0x21C +#define SDMA_CHNENBL08_OFFSET 0x220 +#define SDMA_CHNENBL09_OFFSET 0x224 +#define SDMA_CHNENBL10_OFFSET 0x228 +#define SDMA_CHNENBL11_OFFSET 0x22C +#define SDMA_CHNENBL12_OFFSET 0x230 +#define SDMA_CHNENBL13_OFFSET 0x234 +#define SDMA_CHNENBL14_OFFSET 0x238 +#define SDMA_CHNENBL15_OFFSET 0x23C +#define SDMA_CHNENBL16_OFFSET 0x240 +#define SDMA_CHNENBL17_OFFSET 0x244 +#define SDMA_CHNENBL18_OFFSET 0x248 +#define SDMA_CHNENBL19_OFFSET 0x24C +#define SDMA_CHNENBL20_OFFSET 0x250 +#define SDMA_CHNENBL21_OFFSET 0x254 +#define SDMA_CHNENBL22_OFFSET 0x258 +#define SDMA_CHNENBL23_OFFSET 0x25C +#define SDMA_CHNENBL24_OFFSET 0x260 +#define SDMA_CHNENBL25_OFFSET 0x264 +#define SDMA_CHNENBL26_OFFSET 0x268 +#define SDMA_CHNENBL27_OFFSET 0x26C +#define SDMA_CHNENBL28_OFFSET 0x270 +#define SDMA_CHNENBL29_OFFSET 0x274 +#define SDMA_CHNENBL30_OFFSET 0x278 +#define SDMA_CHNENBL31_OFFSET 0x27C +#define SDMA_CHNENBL32_OFFSET 0x280 +#define SDMA_CHNENBL33_OFFSET 0x284 +#define SDMA_CHNENBL34_OFFSET 0x288 +#define SDMA_CHNENBL35_OFFSET 0x28C +#define SDMA_CHNENBL36_OFFSET 0x290 +#define SDMA_CHNENBL37_OFFSET 0x294 +#define SDMA_CHNENBL38_OFFSET 0x298 +#define SDMA_CHNENBL39_OFFSET 0x29C +#define SDMA_CHNENBL40_OFFSET 0x2A0 +#define SDMA_CHNENBL41_OFFSET 0x2A4 +#define SDMA_CHNENBL42_OFFSET 0x2A8 +#define SDMA_CHNENBL43_OFFSET 0x2AC +#define SDMA_CHNENBL44_OFFSET 0x2B0 +#define SDMA_CHNENBL45_OFFSET 0x2B4 +#define SDMA_CHNENBL46_OFFSET 0x2B8 +#define SDMA_CHNENBL47_OFFSET 0x2BC + +//######################################### +//# ROMCP(via IPSYNC) +//######################################### +#define ROMCP_CNTL_OFFSET 0x00F4 +#define ROMCP_ENL_OFFSET 0x00FC +#define ROMCP_ENH_OFFSET 0x00F8 +#define ROMCP_STAT_OFFSET 0x0208 +#define ROMCP_ADDR0_OFFSET 0x0100 +#define ROMCP_ADDR1_OFFSET 0x0104 +#define ROMCP_ADDR2_OFFSET 0x0108 +#define ROMCP_ADDR3_OFFSET 0x010C +#define ROMCP_ADDR4_OFFSET 0x0110 +#define ROMCP_ADDR5_OFFSET 0x0114 +#define ROMCP_ADDR6_OFFSET 0x0118 +#define ROMCP_ADDR7_OFFSET 0x011C +#define ROMCP_ADDR8_OFFSET 0x0120 +#define ROMCP_ADDR9_OFFSET 0x0124 +#define ROMCP_ADDRA_OFFSET 0x0128 +#define ROMCP_ADDRB_OFFSET 0x012C +#define ROMCP_ADDRC_OFFSET 0x0130 +#define ROMCP_ADDRD_OFFSET 0x0134 +#define ROMCP_ADDRE_OFFSET 0x0138 +#define ROMCP_ADDRF_OFFSET 0x013C +#define ROMCP_DATA0_OFFSET 0x00F0 +#define ROMCP_DATA1_OFFSET 0x00EC +#define ROMCP_DATA2_OFFSET 0x00E8 +#define ROMCP_DATA3_OFFSET 0x00E4 +#define ROMCP_DATA4_OFFSET 0x00E0 +#define ROMCP_DATA5_OFFSET 0x00DC +#define ROMCP_DATA6_OFFSET 0x00D8 +#define ROMCP_DATA7_OFFSET 0x00D4 + +//######################################### +//# USB +//######################################### +#define USB_OTG_BASE_ADDR (USBOH3_USB_BASE_ADDR+0x000) +#define USB_H1_BASE_ADDR (USBOH3_USB_BASE_ADDR+0x200) +#define USB_H2_BASE_ADDR (USBOH3_USB_BASE_ADDR+0x400) +#define USB_H3_BASE_ADDR (USBOH3_USB_BASE_ADDR+0x600) +#define USB_OTG_CTRL_REG (USBOH3_USB_BASE_ADDR+0x800) +#define USB_UH1_CTRL_REG (USBOH3_USB_BASE_ADDR+0x804) +#define USB_UH2_CTRL_REG (USBOH3_USB_BASE_ADDR+0x808) +#define USB_UH3_CTRL_REG (USBOH3_USB_BASE_ADDR+0x80C) +#define USB_UH2_HSIC_REG (USBOH3_USB_BASE_ADDR+0x810) +#define USB_UH3_HSIC_REG (USBOH3_USB_BASE_ADDR+0x814) +#define USB_OTG_UTMIPHY_0 (USBOH3_USB_BASE_ADDR+0x818) +#define USB_UH1_UTMIPHY_0 (USBOH3_USB_BASE_ADDR+0x81C) +#define USB_UH2_HSIC_DLL_CFG1 (USBOH3_USB_BASE_ADDR+0x820) +#define USB_UH2_HSIC_DLL_CFG2 (USBOH3_USB_BASE_ADDR+0x824) +#define USB_UH2_HSIC_DLL_CFG3 (USBOH3_USB_BASE_ADDR+0x828) +#define USB_UH2_HSIC_DLL_STS (USBOH3_USB_BASE_ADDR+0x82C) +#define USB_UH3_HSIC_DLL_CFG1 (USBOH3_USB_BASE_ADDR+0x830) +#define USB_UH3_HSIC_DLL_CFG2 (USBOH3_USB_BASE_ADDR+0x834) +#define USB_UH3_HSIC_DLL_CFG3 (USBOH3_USB_BASE_ADDR+0x838) +#define USB_UH3_HSIC_DLL_STS (USBOH3_USB_BASE_ADDR+0x83C) + +#define USB_H1_ID (USB_H1_BASE_ADDR+0x000) // Identification Register +#define USB_H1_HWGENERAL (USB_H1_BASE_ADDR+0x004) // General Hardware Parameters +#define USB_H1_HWHOST (USB_H1_BASE_ADDR+0x008) // Host Hardware Parameters +#define USB_H1_HWTXBUF (USB_H1_BASE_ADDR+0x010) // TX Buffer Hardware Parameters +#define USB_H1_HWRXBUF (USB_H1_BASE_ADDR+0x014) // RX Buffer Hardware Parameters +#define USB_H1_GPTIMER0LD (USB_H1_BASE_ADDR+0x080) +#define USB_H1_GPTIMER0CTRL (USB_H1_BASE_ADDR+0x084) +#define USB_H1_GPTIMER1LD (USB_H1_BASE_ADDR+0x088) +#define USB_H1_GPTIMER1CTRL (USB_H1_BASE_ADDR+0x08C) +#define USB_H1_SBUSCFG (USB_H1_BASE_ADDR+0x090) +#define USB_H1_CAPLENGTH (USB_H1_BASE_ADDR+0x100) // Capability Register Length +#define USB_H1_HCIVERSION (USB_H1_BASE_ADDR+0x102) // Host Interface Version Number +#define USB_H1_HCSPARAMS (USB_H1_BASE_ADDR+0x104) // Host Ctrl. Structural Parameters +#define USB_H1_HCCPARAMS (USB_H1_BASE_ADDR+0x108) // Host Ctrl. Capability Parameters +#define USB_H1_USBCMD (USB_H1_BASE_ADDR+0x140) // USB Command +#define USB_H1_USBSTS (USB_H1_BASE_ADDR+0x144) // USB Status +#define USB_H1_USBINTR (USB_H1_BASE_ADDR+0x148) // USB Interrupt Enable +#define USB_H1_FRINDEX (USB_H1_BASE_ADDR+0x14C) // USB Frame Index +#define USB_H1_PERIODICLISTBASE (USB_H1_BASE_ADDR+0x154) // Frame List Base Address +#define USB_H1_ASYNCLISTADDR (USB_H1_BASE_ADDR+0x158) // Next Asynchronous List Address +#define USB_H1_BURSTSIZE (USB_H1_BASE_ADDR+0x160) // Programmable Burst Size +#define USB_H1_TXFILLTUNING (USB_H1_BASE_ADDR+0x164) // Host Transmit Pre-Buffer Packet Tuning +#define USB_H1_ICUSB (USB_H1_BASE_ADDR+0x16C) // Host IC USB +#define USB_H1_CONFIGFLAG (USB_H1_BASE_ADDR+0x180) // Configured Flag Register +#define USB_H1_PORTSC1 (USB_H1_BASE_ADDR+0x184) // Port Status/Control +#define USB_H1_USBMODE (USB_H1_BASE_ADDR+0x1A8) // USB Device Mode + +#define USB_H2_ID (USB_H2_BASE_ADDR+0x000) // Identification Register +#define USB_H2_HWGENERAL (USB_H2_BASE_ADDR+0x004) // General Hardware Parameters +#define USB_H2_HWHOST (USB_H2_BASE_ADDR+0x008) // Host Hardware Parameters +#define USB_H2_HWTXBUF (USB_H2_BASE_ADDR+0x010) // TX Buffer Hardware Parameters +#define USB_H2_HWRXBUF (USB_H2_BASE_ADDR+0x014) // RX Buffer Hardware Parameters +#define USB_H2_GPTIMER0LD (USB_H2_BASE_ADDR+0x080) +#define USB_H2_GPTIMER0CTRL (USB_H2_BASE_ADDR+0x084) +#define USB_H2_GPTIMER1LD (USB_H2_BASE_ADDR+0x088) +#define USB_H2_GPTIMER1CTRL (USB_H2_BASE_ADDR+0x08C) +#define USB_H2_SBUSCFG (USB_H2_BASE_ADDR+0x090) +#define USB_H2_CAPLENGTH (USB_H2_BASE_ADDR+0x100) // Capability Register Length +#define USB_H2_HCIVERSION (USB_H2_BASE_ADDR+0x102) // Host Interface Version Number +#define USB_H2_HCSPARAMS (USB_H2_BASE_ADDR+0x104) // Host Ctrl. Structural Parameters +#define USB_H2_HCCPARAMS (USB_H2_BASE_ADDR+0x108) // Host Ctrl. Capability Parameters +#define USB_H2_USBCMD (USB_H2_BASE_ADDR+0x140) // USB Command +#define USB_H2_USBSTS (USB_H2_BASE_ADDR+0x144) // USB Status +#define USB_H2_USBINTR (USB_H2_BASE_ADDR+0x148) // USB Interrupt Enable +#define USB_H2_FRINDEX (USB_H2_BASE_ADDR+0x14C) // USB Frame Index +#define USB_H2_PERIODICLISTBASE (USB_H2_BASE_ADDR+0x154) // Frame List Base Address +#define USB_H2_ASYNCLISTADDR (USB_H2_BASE_ADDR+0x158) // Next Asynchronous List Address +#define USB_H2_BURSTSIZE (USB_H2_BASE_ADDR+0x160) // Programmable Burst Size +#define USB_H2_TXFILLTUNING (USB_H2_BASE_ADDR+0x164) // Host Transmit Pre-Buffer Packet Tuning +#define USB_H2_ICUSB (USB_H2_BASE_ADDR+0x16C) // Host IC USB +#define USB_H2_CONFIGFLAG (USB_H2_BASE_ADDR+0x180) // Configured Flag Register +#define USB_H2_PORTSC1 (USB_H2_BASE_ADDR+0x184) // Port Status/Control +#define USB_H2_USBMODE (USB_H2_BASE_ADDR+0x1A8) // USB Device Mode + +#define USB_H3_ID (USB_H3_BASE_ADDR+0x000) // Identification Register +#define USB_H3_HWGENERAL (USB_H3_BASE_ADDR+0x004) // General Hardware Parameters +#define USB_H3_HWHOST (USB_H3_BASE_ADDR+0x008) // Host Hardware Parameters +#define USB_H3_HWTXBUF (USB_H3_BASE_ADDR+0x010) // TX Buffer Hardware Parameters +#define USB_H3_HWRXBUF (USB_H3_BASE_ADDR+0x014) // RX Buffer Hardware Parameters +#define USB_H3_GPTIMER0LD (USB_H3_BASE_ADDR+0x080) +#define USB_H3_GPTIMER0CTRL (USB_H3_BASE_ADDR+0x084) +#define USB_H3_GPTIMER1LD (USB_H3_BASE_ADDR+0x088) +#define USB_H3_GPTIMER1CTRL (USB_H3_BASE_ADDR+0x08C) +#define USB_H3_SBUSCFG (USB_H3_BASE_ADDR+0x090) +#define USB_H3_CAPLENGTH (USB_H3_BASE_ADDR+0x100) // Capability Register Length +#define USB_H3_HCIVERSION (USB_H3_BASE_ADDR+0x102) // Host Interface Version Number +#define USB_H3_HCSPARAMS (USB_H3_BASE_ADDR+0x104) // Host Ctrl. Structural Parameters +#define USB_H3_HCCPARAMS (USB_H3_BASE_ADDR+0x108) // Host Ctrl. Capability Parameters +#define USB_H3_USBCMD (USB_H3_BASE_ADDR+0x140) // USB Command +#define USB_H3_USBSTS (USB_H3_BASE_ADDR+0x144) // USB Status +#define USB_H3_USBINTR (USB_H3_BASE_ADDR+0x148) // USB Interrupt Enable +#define USB_H3_FRINDEX (USB_H3_BASE_ADDR+0x14C) // USB Frame Index +#define USB_H3_PERIODICLISTBASE (USB_H3_BASE_ADDR+0x154) // Frame List Base Address +#define USB_H3_ASYNCLISTADDR (USB_H3_BASE_ADDR+0x158) // Next Asynchronous List Address +#define USB_H3_BURSTSIZE (USB_H3_BASE_ADDR+0x160) // Programmable Burst Size +#define USB_H3_TXFILLTUNING (USB_H3_BASE_ADDR+0x164) // Host Transmit Pre-Buffer Packet Tuning +#define USB_H3_ICUSB (USB_H3_BASE_ADDR+0x16C) // Host IC USB +#define USB_H3_CONFIGFLAG (USB_H3_BASE_ADDR+0x180) // Configured Flag Register +#define USB_H3_PORTSC1 (USB_H3_BASE_ADDR+0x184) // Port Status/Control +#define USB_H3_USBMODE (USB_H3_BASE_ADDR+0x1A8) // USB Device Mode + +#define USB_OTG_ID (USB_OTG_BASE_ADDR+0x000) // Identification Register +#define USB_OTG_HWGENERAL (USB_OTG_BASE_ADDR+0x004) // General Hardware Parameters +#define USB_OTG_HWHOST (USB_OTG_BASE_ADDR+0x008) // Host Hardware Parameters +#define USB_OTG_HWDEVICE (USB_OTG_BASE_ADDR+0x00C) // Device Hardware Parameters +#define USB_OTG_HWTXBUF (USB_OTG_BASE_ADDR+0x010) // TX Buffer Hardware Parameters +#define USB_OTG_HWRXBUF (USB_OTG_BASE_ADDR+0x014) // RX Buffer Hardware Parameters +#define USB_OTG_GPTIMER0LD (USB_OTG_BASE_ADDR+0x080) +#define USB_OTG_GPTIMER0CTRL (USB_OTG_BASE_ADDR+0x084) +#define USB_OTG_GPTIMER1LD (USB_OTG_BASE_ADDR+0x088) +#define USB_OTG_GPTIMER1CTRL (USB_OTG_BASE_ADDR+0x08C) +#define USB_OTG_SBUSCFG (USB_OTG_BASE_ADDR+0x090) +#define USB_OTG_EPSEL (USB_OTG_BASE_ADDR+0x094) +#define USB_OTG_CAPLENGTH (USB_OTG_BASE_ADDR+0x100) // Capability Register Length +#define USB_OTG_HCIVERSION (USB_OTG_BASE_ADDR+0x102) // Host Interface Version Number +#define USB_OTG_HCSPARAMS (USB_OTG_BASE_ADDR+0x104) // Host Ctrl. Structural Parameters +#define USB_OTG_HCCPARAMS (USB_OTG_BASE_ADDR+0x108) // Host Ctrl. Capability Parameters +#define USB_OTG_DCIVERSION (USB_OTG_BASE_ADDR+0x120) // Dev. Interface Version Number +#define USB_OTG_DCCPARAMS (USB_OTG_BASE_ADDR+0x124) // Device Ctrl. Capability Parameters +#define USB_OTG_USBCMD (USB_OTG_BASE_ADDR+0x140) // USB Command +#define USB_OTG_USBSTS (USB_OTG_BASE_ADDR+0x144) // USB Status +#define USB_OTG_USBINTR (USB_OTG_BASE_ADDR+0x148) // USB Interrupt Enable +#define USB_OTG_FRINDEX (USB_OTG_BASE_ADDR+0x14C) // USB Frame Index +#define USB_OTG_PERIODICLISTBASE (USB_OTG_BASE_ADDR+0x154) // Frame List Base Address +#define USB_OTG_ASYNCLISTADDR (USB_OTG_BASE_ADDR+0x158) // Next Asynchronous List Address +#define USB_OTG_BURSTSIZE (USB_OTG_BASE_ADDR+0x160) // Programmable Burst Size +#define USB_OTG_TXFILLTUNING (USB_OTG_BASE_ADDR+0x164) // Host Transmit Pre-Buffer Packet Tuning +#define USB_OTG_ICUSB (USB_OTG_BASE_ADDR+0x16C) // OTG IC USB +#define USB_OTG_CONFIGFLAG (USB_OTG_BASE_ADDR+0x180) // Configured Flag Register +#define USB_OTG_PORTSC1 (USB_OTG_BASE_ADDR+0x184) // Port Status/Control +#define USB_OTG_OTGSC (USB_OTG_BASE_ADDR+0x1A4) // On-The-Go (OTG) Status and Control +#define USB_OTG_USBMODE (USB_OTG_BASE_ADDR+0x1A8) // USB Device Mode +#define USB_OTG_ENPDTSETUPSTAT (USB_OTG_BASE_ADDR+0x1AC) // Endpoint Setup Status +#define USB_OTG_ENDPTPRIME (USB_OTG_BASE_ADDR+0x1B0) // Endpoint Initialization +#define USB_OTG_ENDPTFLUSH (USB_OTG_BASE_ADDR+0x1B4) // Endpoint De-Initialize +#define USB_OTG_ENDPTSTATUS (USB_OTG_BASE_ADDR+0x1B8) // Endpoint Status +#define USB_OTG_ENDPTCOMPLETE (USB_OTG_BASE_ADDR+0x1BC) // Endpoint Complete +#define USB_OTG_ENDPTCTRL0 (USB_OTG_BASE_ADDR+0x1C0) // Endpoint Control 0 +#define USB_OTG_ENDPTCTRL1 (USB_OTG_BASE_ADDR+0x1C4) // Endpoint Control 1 +#define USB_OTG_ENDPTCTRL2 (USB_OTG_BASE_ADDR+0x1C8) // Endpoint Control 2 +#define USB_OTG_ENDPTCTRL3 (USB_OTG_BASE_ADDR+0x1CC) // Endpoint Control 3 +#define USB_OTG_ENDPTCTRL4 (USB_OTG_BASE_ADDR+0x1D0) // Endpoint Control 4 +#define USB_OTG_ENDPTCTRL5 (USB_OTG_BASE_ADDR+0x1D4) // Endpoint Control 5 +#define USB_OTG_ENDPTCTRL6 (USB_OTG_BASE_ADDR+0x1D8) // Endpoint Control 6 +#define USB_OTG_ENDPTCTRL7 (USB_OTG_BASE_ADDR+0x1DC) // Endpoint Control 7 + +//######################################### +//#SJC +//######################################### +#define SJC_GPUSR1_OFFSET 0x00 +#define SJC_GPUSR2_OFFSET 0x01 +#define SJC_GPUSR3_OFFSET 0x02 +#define SJC_GPSSR_OFFSET 0x03 +#define SJC_DCR_OFFSET 0x04 +#define SJC_SSR_OFFSET 0x05 +#define SJC_CPCR_OFFSET 0x06 +#define SJC_GPCCR_OFFSET 0x07 +#define SJC_PLLBR_OFFSET 0x08 +#define SJC_GPUCR1_OFFSET 0x09 +#define SJC_GPUCR2_OFFSET 0x0A +#define SJC_GPUCR3_OFFSET 0x0B +#define SJC_GPSCR_OFFSET 0x0C +#define SJC_TESTREG_OFFSET 0x0D +#define SJC_SASR_OFFSET 0x0E +#define SJC_BISTCR1_OFFSET 0x0F +#define SJC_BISTCR2_OFFSET 0x10 +#define SJC_BISTCR3_OFFSET 0x11 +#define SJC_BISTCR4_OFFSET 0x12 +#define SJC_BISTCR5_OFFSET 0x13 +#define SJC_BISTCR6_OFFSET 0x14 +#define SJC_BISTCR7_OFFSET 0x15 +#define SJC_MBISTPASSR1_OFFSET 0x16 +#define SJC_MBISTPASSR2_OFFSET 0x17 +#define SJC_MBISTDONER1_OFFSET 0x18 +#define SJC_MBISTDONER2_OFFSET 0x19 +#define SJC_MBISTMASKR1_OFFSET 0x1A +#define SJC_MBISTMASKR2_OFFSET 0x1B +#define SJC_BISTPASSR_OFFSET 0x1C +#define SJC_BISTDONER_OFFSET 0x1D +#define SJC_MONBISTSELR_OFFSET 0x1E +#define SJC_RWVALCR_OFFSET 0x1F +//######################################### +//# CCM +//######################################### +#define CCM_CCR_OFFSET 0x00 +#define CCM_CCDR_OFFSET 0x04 +#define CCM_CSR_OFFSET 0x08 +#define CCM_CCSR_OFFSET 0x0C +#define CCM_CACRR_OFFSET 0x10 +#define CCM_CBCDR_OFFSET 0x14 +#define CCM_CBCMR_OFFSET 0X18 +#define CCM_CSCMR1_OFFSET 0x1c +#define CCM_CSCMR2_OFFSET 0x20 +#define CCM_CSCDR1_OFFSET 0x24 +#define CCM_CS1CDR_OFFSET 0x28 +#define CCM_CS2CDR_OFFSET 0x2c +#define CCM_CDCDR_OFFSET 0x30 +#define CCM_CHSCCDR_OFFSET 0x34 +#define CCM_CSCDR2_OFFSET 0x38 +#define CCM_CSCDR3_OFFSET 0x3c +#define CCM_CSCDR4_OFFSET 0x40 +#define CCM_CWDR_OFFSET 0x44 +#define CCM_CDHIPR_OFFSET 0x48 +#define CCM_CDCR_OFFSET 0x4c +#define CCM_CTOR_OFFSET 0x50 +#define CCM_CLPCR_OFFSET 0x54 +#define CCM_CISR_OFFSET 0x58 +#define CCM_CIMR_OFFSET 0x5c +#define CCM_CCOSR_OFFSET 0x60 +#define CCM_CGPR_OFFSET 0x64 +#define CCM_CCGR0_OFFSET 0x68 +#define CCM_CCGR1_OFFSET 0x6c +#define CCM_CCGR2_OFFSET 0x70 +#define CCM_CCGR3_OFFSET 0x74 +#define CCM_CCGR4_OFFSET 0x78 +#define CCM_CCGR5_OFFSET 0x7c +#define CCM_CCGR6_OFFSET 0x80 +#define CCM_CCGR7_OFFSET 0x84 +#define CCM_CMEOR_OFFSET 0x88 + +#define CCM_CCR CCM_IPS_BASE_ADDR+CCM_CCR_OFFSET +#define CCM_CCDR CCM_IPS_BASE_ADDR+CCM_CCDR_OFFSET +#define CCM_CSR CCM_IPS_BASE_ADDR+CCM_CSR_OFFSET +#define CCM_CCSR CCM_IPS_BASE_ADDR+CCM_CCSR_OFFSET +#define CCM_CACRR CCM_IPS_BASE_ADDR+CCM_CACRR_OFFSET +#define CCM_CBCDR CCM_IPS_BASE_ADDR+CCM_CBCDR_OFFSET +#define CCM_CBCMR CCM_IPS_BASE_ADDR+CCM_CBCMR_OFFSET +#define CCM_CSCMR1 CCM_IPS_BASE_ADDR+CCM_CSCMR1_OFFSET +#define CCM_CSCMR2 CCM_IPS_BASE_ADDR+CCM_CSCMR2_OFFSET +#define CCM_CSCDR1 CCM_IPS_BASE_ADDR+CCM_CSCDR1_OFFSET +#define CCM_CS1CDR CCM_IPS_BASE_ADDR+CCM_CS1CDR_OFFSET +#define CCM_CS2CDR CCM_IPS_BASE_ADDR+CCM_CS2CDR_OFFSET +#define CCM_CDCDR CCM_IPS_BASE_ADDR+CCM_CDCDR_OFFSET +#define CCM_CHSCCDR CCM_IPS_BASE_ADDR+CCM_CHSCCDR_OFFSET +#define CCM_CSCDR2 CCM_IPS_BASE_ADDR+CCM_CSCDR2_OFFSET +#define CCM_CSCDR3 CCM_IPS_BASE_ADDR+CCM_CSCDR3_OFFSET +#define CCM_CSCDR4 CCM_IPS_BASE_ADDR+CCM_CSCDR4_OFFSET +#define CCM_CWDR CCM_IPS_BASE_ADDR+CCM_CWDR_OFFSET +#define CCM_CDHIPR CCM_IPS_BASE_ADDR+CCM_CDHIPR_OFFSET +#define CCM_CDCR CCM_IPS_BASE_ADDR+CCM_CDCR_OFFSET +#define CCM_CTOR CCM_IPS_BASE_ADDR+CCM_CTOR_OFFSET +#define CCM_CLPCR CCM_IPS_BASE_ADDR+CCM_CLPCR_OFFSET +#define CCM_CISR CCM_IPS_BASE_ADDR+CCM_CISR_OFFSET +#define CCM_CIMR CCM_IPS_BASE_ADDR+CCM_CIMR_OFFSET +#define CCM_CCOSR CCM_IPS_BASE_ADDR+CCM_CCOSR_OFFSET +#define CCM_CGPR CCM_IPS_BASE_ADDR+CCM_CGPR_OFFSET +#define CCM_CCGR0 CCM_IPS_BASE_ADDR+CCM_CCGR0_OFFSET +#define CCM_CCGR1 CCM_IPS_BASE_ADDR+CCM_CCGR1_OFFSET +#define CCM_CCGR2 CCM_IPS_BASE_ADDR+CCM_CCGR2_OFFSET +#define CCM_CCGR3 CCM_IPS_BASE_ADDR+CCM_CCGR3_OFFSET +#define CCM_CCGR4 CCM_IPS_BASE_ADDR+CCM_CCGR4_OFFSET +#define CCM_CCGR5 CCM_IPS_BASE_ADDR+CCM_CCGR5_OFFSET +#define CCM_CCGR6 CCM_IPS_BASE_ADDR+CCM_CCGR6_OFFSET +#define CCM_CCGR7 CCM_IPS_BASE_ADDR+CCM_CCGR7_OFFSET +#define CCM_CMEOR CCM_IPS_BASE_ADDR+CCM_CMEOR_OFFSET + +//######################################### +//# GPC +//######################################### +#define GPC_CNTR_OFFSET 0x0 +#define GPC_PGR_OFFSET 0x4 +#define GPC_IMR1_OFFSET 0x8 +#define GPC_IMR2_OFFSET 0xc +#define GPC_IMR3_OFFSET 0x10 +#define GPC_IMR4_OFFSET 0x14 +#define GPC_ISR1_OFFSET 0x18 +#define GPC_ISR2_OFFSET 0x1c +#define GPC_ISR3_OFFSET 0x20 +#define GPC_ISR4_OFFSET 0x24 +//#define GPC_VCR_OFFSET 0x8 +//#define GPC_ALL_PU_OFFSET 0xc +//#define GPC_NEON_OFFSET 0x10 + +// GPC_DPTC_LP +#define GPC_DPTC_LP_DPTCCR_OFFSET 0x80 +#define GPC_DPTC_LP_DPTCDBG_OFFSET 0x84 +#define GPC_DPTC_LP_DCVR0_OFFSET 0x88 +#define GPC_DPTC_LP_DCVR1_OFFSET 0x8c +#define GPC_DPTC_LP_DCVR2_OFFSET 0x90 +#define GPC_DPTC_LP_DCVR3_OFFSET 0x94 + +// GPC_DPTC_GP +#define GPC_DPTC_GP_DPTCCR_OFFSET 0x100 +#define GPC_DPTC_GP_DPTCDBG_OFFSET 0x104 +#define GPC_DPTC_GP_DCVR0_OFFSET 0x108 +#define GPC_DPTC_GP_DCVR1_OFFSET 0x10c +#define GPC_DPTC_GP_DCVR2_OFFSET 0x110 +#define GPC_DPTC_GP_DCVR3_OFFSET 0x114 + +// GPC_DVFS_CORE +#define GPC_DVFS_CORE_DVFSTHRS_OFFSET 0x180 +#define GPC_DVFS_CORE_DVFSCOUN_OFFSET 0x184 +#define GPC_DVFS_CORE_DVFSSIG1_OFFSET 0x188 +#define GPC_DVFS_CORE_DVFDDIG0_OFFSET 0x18c +#define GPC_DVFS_CORE_DVFSGPC0_OFFSET 0x190 +#define GPC_DVFS_CORE_DVFSGPC1_OFFSET 0x194 +#define GPC_DVFS_CORE_DVFSGPBT_OFFSET 0x198 +#define GPC_DVFS_CORE_DVFSEMAC_OFFSET 0x19c +#define GPC_DVFS_CORE_DVFSCNTR_OFFSET 0x1a0 +#define GPC_DVFS_CORE_DVFSSLTR0_0_OFFSET 0x1a4 +#define GPC_DVFS_CORE_DVFSSLTR0_1_OFFSET 0x1a8 +#define GPC_DVFS_CORE_DVFSSLTR1_0_OFFSET 0x1ac +#define GPC_DVFS_CORE_DVFSSLTR1_1_OFFSET 0x1b0 +#define GPC_DVFS_CORE_DVFSPT0_OFFSET 0x1b4 +#define GPC_DVFS_CORE_DVFSPT1_OFFSET 0x1b8 +#define GPC_DVFS_CORE_DVFSPT2_OFFSET 0x1bc +#define GPC_DVFS_CORE_DVFSPT3_OFFSET 0x1c0 + +// GPC_DVFS_PER +#define GPC_DVFS_PER_LTR0_OFFSET 0x1c4 +#define GPC_DVFS_PER_LTR1_OFFSET 0x1c8 +#define GPC_DVFS_PER_LTR2_OFFSET 0x1cc +#define GPC_DVFS_PER_LTR3_OFFSET 0x1d0 +#define GPC_DVFS_PER_LTBR0_OFFSET 0x1d4 +#define GPC_DVFS_PER_LTBR1_OFFSET 0x1d8 +#define GPC_DVFS_PER_PMCR0_OFFSET 0x1dc +#define GPC_DVFS_PER_PMCR1_OFFSET 0x1e0 + +//GPC_PGC_GPU2D +#define GPC_PGC_GPU2D_PGCR_OFFSET 0x200 +#define GPC_PGC_GPU2D_PUPSCR_OFFSET 0x204 +#define GPC_PGC_GPU2D_PDNSCR_OFFSET 0x208 +#define GPC_PGC_GPU2D_PGSR_OFFSET 0x20c + +//GPC_PGC_IPU +#define GPC_PGC_IPU_PGCR_OFFSET 0x220 +#define GPC_PGC_IPU_PUPSCR_OFFSET 0x224 +#define GPC_PGC_IPU_PDNSCR_OFFSET 0x228 +#define GPC_PGC_IPU_PGSR_OFFSET 0x22c + +//GPC_PGC_VPU +#define GPC_PGC_VPU_PGCR_OFFSET 0x240 +#define GPC_PGC_VPU_PUPSCR_OFFSET 0x244 +#define GPC_PGC_VPU_PDNSCR_OFFSET 0x248 +#define GPC_PGC_VPU_PGSR_OFFSET 0x24c + +//GPC_PGC_GPU +#define GPC_PGC_GPU_PGCR_OFFSET 0x260 +#define GPC_PGC_GPU_PUPSCR_OFFSET 0x264 +#define GPC_PGC_GPU_PDNSCR_OFFSET 0x268 +#define GPC_PGC_GPU_PGSR_OFFSET 0x26c + +//GPC_SRPGC_NEON +#define GPC_SRPGC_NEON_SRPGCR_OFFSET 0x280 +#define GPC_SRPGC_NEON_PUPSCR_OFFSET 0x284 +#define GPC_SRPGC_NEON_PDNSCR_OFFSET 0x288 +#define GPC_SRPGC_NEON_SRPGSR_OFFSET 0x28c +#define GPC_SRPGC_NEON_SRPGDR_OFFSET 0x290 + +//GPC_SRPGC_TIGER +#define GPC_SRPGC_TIGER_SRPGCR_OFFSET 0x2a0 +#define GPC_SRPGC_TIGER_PUPSCR_OFFSET 0x2a4 +#define GPC_SRPGC_TIGER_PDNSCR_OFFSET 0x2a8 +#define GPC_SRPGC_TIGER_SRPGSR_OFFSET 0x2ac +#define GPC_SRPGC_TIGER_SRPGDR_OFFSET 0x2b0 + +//GPC_EMPGC0_TIGER +#define GPC_EMPGC0_TIGER_EMPGCR_OFFSET 0x2c0 +#define GPC_EMPGC0_TIGER_PUPSCR_OFFSET 0x2c4 +#define GPC_EMPGC0_TIGER_PDNSCR_OFFSET 0x2c8 +#define GPC_EMPGC0_TIGER_EMPGSR_OFFSET 0x2cc + +//GPC_EMPGC1_TIGER +#define GPC_EMPGC1_TIGER_EMPGCR_OFFSET 0x2d0 +#define GPC_EMPGC1_TIGER_PUPSCR_OFFSET 0x2d4 +#define GPC_EMPGC1_TIGER_PDNSCR_OFFSET 0x2d8 +#define GPC_EMPGC1_TIGER_EMPGSR_OFFSET 0x2dc + +//GPC_SRPGC_MEGAMIX +#define GPC_SRPGC_MEGAMIX_SRPGCR_OFFSET 0x2e0 +#define GPC_SRPGC_MEGAMIX_PUPSCR_OFFSET 0x2e4 +#define GPC_SRPGC_MEGAMIX_PDNSCR_OFFSET 0x2e8 +#define GPC_SRPGC_MEGAMIX_SRPGSR_OFFSET 0x2ec +#define GPC_SRPGC_MEGAMIX_SRPGDR_OFFSET 0x2f0 + +//GPC_SRPGC_EMI +#define GPC_SRPGC_EMI_SRPGCR_OFFSET 0x300 +#define GPC_SRPGC_EMI_PUPSCR_OFFSET 0x304 +#define GPC_SRPGC_EMI_PDNSCR_OFFSET 0x308 +#define GPC_SRPGC_EMI_SRPGSR_OFFSET 0x30c +#define GPC_SRPGC_EMI_SRPGDR_OFFSET 0x310 + +//######################################### +//# SRC +//######################################### +#define SRC_SCR_OFFSET 0x000 +#define SRC_SBMR_OFFSET 0x004 +#define SRC_SRSR_OFFSET 0x008 +#define SRC_SAIAR_OFFSET 0x00c +#define SRC_SAIRAR_OFFSET 0x010 +#define SRC_SISR_OFFSET 0x014 +#define SRC_SIMR_OFFSET 0x018 +#define SRC_SBMR2_OFFSET 0x01c +#define SRC_GPR1_OFFSET 0x020 +#define SRC_GPR2_OFFSET 0x024 +#define SRC_GPR3_OFFSET 0x028 +#define SRC_GPR4_OFFSET 0x02c +#define SRC_GPR5_OFFSET 0x030 +#define SRC_GPR6_OFFSET 0x034 +#define SRC_GPR7_OFFSET 0x038 +#define SRC_GPR8_OFFSET 0x03c +#define SRC_GPR9_OFFSET 0x040 +#define SRC_GPR10_OFFSET 0x044 +//######################################### +//# SPDIF +//######################################### +#define SPDIF_SCR_OFFSET 0x00 +#define SPDIF_SRCD_OFFSET 0x04 +#define SPDIF_SRPC_OFFSET 0x08 +#define SPDIF_SIE_OFFSET 0x0C +#define SPDIF_SIS_OFFSET 0x10 +#define SPDIF_SIC_OFFSET 0x10 +#define SPDIF_SRL_OFFSET 0x14 +#define SPDIF_SRR_OFFSET 0x18 +#define SPDIF_SRCSH_OFFSET 0x1C +#define SPDIF_SRCSL_OFFSET 0x20 +#define SPDIF_SRU_OFFSET 0x24 +#define SPDIF_SRQ_OFFSET 0x28 +#define SPDIF_STL_OFFSET 0x2C +#define SPDIF_STR_OFFSET 0x30 +#define SPDIF_STCSH_OFFSET 0x34 +#define SPDIF_STCSL_OFFSET 0x38 +#define SPDIF_STUH_OFFSET 0x3C +#define SPDIF_STUL_OFFSET 0x40 +#define SPDIF_SRFM_OFFSET 0x44 +#define SPDIF_STC_OFFSET 0x50 + +//######################################### +//# ARM_DEBUG_UNIT +//######################################### +#define ARM_DEBUG_DRCR_REG (CORTEX_DEBUG_UNIT + 0x090) +#define ARM_DEBUG_LAR_REG (CORTEX_DEBUG_UNIT + 0xFB0) +#define ARM_DEBUG_PRSR_REG (CORTEX_DEBUG_UNIT + 0x314) + +//######################################### +//# ARM INTERRUPT CONTROLLER +//######################################### +#define ICDDCR (IC_DISTRIBUTOR_BASE_ADDR + 0x000) +#define ICDICTR (IC_DISTRIBUTOR_BASE_ADDR + 0x004) +#define ICDIIDR (IC_DISTRIBUTOR_BASE_ADDR + 0x008) +#define ICDISR (IC_DISTRIBUTOR_BASE_ADDR + 0x080) +#define ICDISER (IC_DISTRIBUTOR_BASE_ADDR + 0x100) +#define ICDICER (IC_DISTRIBUTOR_BASE_ADDR + 0x180) +#define ICDISPR (IC_DISTRIBUTOR_BASE_ADDR + 0x200) +#define ICDICPR (IC_DISTRIBUTOR_BASE_ADDR + 0x280) +#define ICDABR (IC_DISTRIBUTOR_BASE_ADDR + 0x300) +#define ICDIPR (IC_DISTRIBUTOR_BASE_ADDR + 0x400) +#define ICDIPTR (IC_DISTRIBUTOR_BASE_ADDR + 0x800) +#define ICDICFR (IC_DISTRIBUTOR_BASE_ADDR + 0xC00) +#define ICD_PPI_STAT (IC_DISTRIBUTOR_BASE_ADDR + 0xD00) +#define ICD_SPI_STAT_0 (IC_DISTRIBUTOR_BASE_ADDR + 0xD04) +#define ICD_SPI_STAT_1 (IC_DISTRIBUTOR_BASE_ADDR + 0xD08) +#define ICD_SPI_STAT_2 (IC_DISTRIBUTOR_BASE_ADDR + 0xD0C) +#define ICD_SPI_STAT_3 (IC_DISTRIBUTOR_BASE_ADDR + 0xD10) +#define ICDSGIR (IC_DISTRIBUTOR_BASE_ADDR + 0xF00) +#define ICCICR (IC_INTERFACES_BASE_ADDR + 0x000) +#define ICCPMR (IC_INTERFACES_BASE_ADDR + 0x004) +#define ICCBPR (IC_INTERFACES_BASE_ADDR + 0x008) +#define ICCIAR (IC_INTERFACES_BASE_ADDR + 0x00c) +#define ICCEOIR (IC_INTERFACES_BASE_ADDR + 0x010) +#define ICCRPR (IC_INTERFACES_BASE_ADDR + 0x014) +#define ICCHPIR (IC_INTERFACES_BASE_ADDR + 0x018) +#define ICCABPR (IC_INTERFACES_BASE_ADDR + 0x01C) +#define ICCIIDR (IC_INTERFACES_BASE_ADDR + 0x0FC) + +//######################################### +//# ENET REGISTERS +//######################################### +//base is probably 0x400c0000 +#define ENET_OPD 0x00EC //writable bits 0..15, 16..31 are readonly==0x0001 + +//######################################### +//# SNVS REGISTERS +//######################################### +#define SNVS_HPLR 0x0000 //writable bits 0..18 +#define SNVS_HPCOMR 0x0004 //writable bits 0..31 +#define SNVS_HPCR 0x0008 //writable bits 0..16 +#define SNVS_HPSICR 0x000C //writable bits 0..5 +#define SNVS_HPSVCR 0x0010 //writable bits 0..6 +#define SNVS_HPSR 0x0014 //writable bits 0..31 +#define SNVS_HPVSR 0x0018 //writable bits 0..27 +#define SNVS_HPHACIVR 0x001c //writable bits 0..31 +#define SNVS_HPHACR 0x0020 //no writable bits +#define SNVS_HPRTCMR 0x0024 //writable bits 0..14 +#define SNVS_HPRTCLR 0x0028 //writable bits 0..31 +#define SNVS_HPTAMR 0x002C //writable bits 0..14 +#define SNVS_HPTALR 0x0030 //writable bits 0..31 +#define SNVS_LPLR 0x0034 //writable bits 0..8 +#define SNVS_LPCR 0x0038 //writable bits 0..14 +#define SNVS_LPMKCR 0x003c //writable bits 0..4 +#define SNVS_LPSVCR 0x0040 //writable bits 0..5 +#define SNVS_LPTGFCR 0x0044 //writable bits 0..31 +#define SNVS_LPTDCR 0x0048 //writable bits 0..28 +#define SNVS_LPSR 0x004c //writable bits 0..20 +#define SNVS_LPSRTCMR 0x0050 //writable bits 0..14 +#define SNVS_LPSRTCLR 0x0054 //writable bits 0..31 +#define SNVS_LPTAR 0x0058 //writable bits 0..31 +#define SNVS_LPSMCMR 0x005C //no writable bits +#define SNVS_LPSMCLR 0x0060 //no writable bits +#define SNVS_LPPGDR 0x0064 //writable bits 0..31 +#define SNVS_LPGPR 0x0068 //writable bits 0..31 +#define SNVS_LPZMKR0 0x006C //writable bits 0..31 +#define SNVS_LPZKMR1 0x0070 //writable bits 0..31 +#define SNVS_LPZKMR2 0x0074 //writable bits 0..31 +#define SNVS_LPZKMR3 0x0078 //writable bits 0..31 +#define SNVS_LPZKMR4 0x007C //writable bits 0..31 +#define SNVS_LPZKMR5 0x0080 //writable bits 0..31 +#define SNVS_LPZKMR6 0x0084 //writable bits 0..31 +#define SNVS_LPZKMR7 0x0088 //writable bits 0..31 +#define SNVS_HPVIDR1 0x0BF8 //no writable bits +#define SNVS_HPVIDR2 0x0BFC //no writable bits + +//######################################### +//# MIPI_CSI REGISTERS +//######################################### +#define MIPI_CSI2_VERSION 0x000 +#define MIPI_CSI2_N_LANES 0x004 +#define MIPI_CSI2_PHY_SHUTDOWNZ 0x008 +#define MIPI_CSI2_DPHY_RSTZ 0x00c +#define MIPI_CSI2_RESETN 0x010 +#define MIPI_CSI2_PHY_STATE 0x014 +#define MIPI_CSI2_DATA_IDS_1 0x018 +#define MIPI_CSI2_DATA_IDS_2 0x01c +#define MIPI_CSI2_ERR1 0x020 +#define MIPI_CSI2_ERR2 0x024 +#define MIPI_CSI2_MSK1 0x028 +#define MIPI_CSI2_MSK2 0x02c +#define MIPI_CSI2_PHY_TST_CTRL0 0x030 +#define MIPI_CSI2_PHY_TST_CTRL1 0x034 +#define MIPI_CSI2_SFT_RESET 0xf00 + +//######################################### +//# MIPI_DSI REGISTERS +//######################################### +#define MIPI_DSI_VERSION 0x000 +#define MIPI_DSI_PWR_UP 0x004 +#define MIPI_DSI_CLKMGR_CFG 0x008 +#define MIPI_DSI_DPI_CFG 0x00c +#define MIPI_DSI_DBI_CFG 0x010 +#define MIPI_DSI_DBI_CMDSIZE 0x014 +#define MIPI_DSI_PCKHDL_CFG 0x018 +#define MIPI_DSI_VID_MODE_CFG 0x01c +#define MIPI_DSI_VID_PKT_CFG 0x020 +#define MIPI_DSI_CMD_MODE_CFG 0x024 +#define MIPI_DSI_TMR_LINE_CFG 0x028 +#define MIPI_DSI_VTIMING_CFG 0x02c +#define MIPI_DSI_TMR_CFG 0x030 +#define MIPI_DSI_GEN_HDR 0x034 +#define MIPI_DSI_GEN_PLD_DATA 0x038 +#define MIPI_DSI_CMD_PKT_STATUS 0x03c +#define MIPI_DSI_TO_CNT_CFG 0x040 +#define MIPI_DSI_ERROR_ST0 0x044 +#define MIPI_DSI_ERROR_ST1 0x048 +#define MIPI_DSI_ERROR_MSK0 0x04c +#define MIPI_DSI_ERROR_MSK1 0x050 +#define MIPI_DSI_PHY_RSTZ 0x054 +#define MIPI_DSI_PHY_IF_CFG 0x058 +#define MIPI_DSI_PHY_IF_CTRL 0x05c +#define MIPI_DSI_PHY_STATUS 0x060 +#define MIPI_DSI_PHY_TST_CTRL0 0x064 +#define MIPI_DSI_PHY_TST_CTRL1 0x068 + +//######################################### +//# MIPI_HSI REGISTERS +//######################################### + +#define MIPI_HW_HSI_CTRL 0x000 +#define MIPI_HW_HSI_TX_CONF 0x004 +#define MIPI_HW_HSI_RX_CONF 0x008 +#define MIPI_HW_HSI_HSI_CAP 0x00c +#define MIPI_HW_HSI_TX_WML0 0x010 +#define MIPI_HW_HSI_TX_WML1 0x014 +#define MIPI_HW_HSI_TX_ARB_PRI0 0x018 +#define MIPI_HW_HSI_TX_ARB_PRI1 0x01c +#define MIPI_HW_HSI_LINE_ST 0x020 +#define MIPI_HW_HSI_ID_BIT 0x024 +#define MIPI_HW_HSI_FIFO_THR_CONF 0x028 +#define MIPI_HW_HSI_CH_SFTRST 0x02c +#define MIPI_HW_HSI_IRQSTAT 0x030 +#define MIPI_HW_HSI_IRQSTAT_EN 0x034 +#define MIPI_HW_HSI_IRQSIG_EN 0x038 +#define MIPI_HW_HSI_FIFO_THR_IRQSTAT 0x03c +#define MIPI_HW_HSI_FIFO_THR_IRQSTAT_EN 0x040 +#define MIPI_HW_HSI_FIFO_IRQSIG_EN 0x044 +#define MIPI_HW_HSI_TX_CH0_DP 0x050 +#define MIPI_HW_HSI_TX_CH1_DP 0x054 +#define MIPI_HW_HSI_TX_CH2_DP 0x058 +#define MIPI_HW_HSI_TX_CH3_DP 0x05c +#define MIPI_HW_HSI_TX_CH4_DP 0x060 +#define MIPI_HW_HSI_TX_CH5_DP 0x064 +#define MIPI_HW_HSI_TX_CH6_DP 0x068 +#define MIPI_HW_HSI_TX_CH7_DP 0x06c +#define MIPI_HW_HSI_TX_CH8_DP 0x070 +#define MIPI_HW_HSI_TX_CH9_DP 0x074 +#define MIPI_HW_HSI_TX_CH10_DP 0x078 +#define MIPI_HW_HSI_TX_CH11_DP 0x07c +#define MIPI_HW_HSI_TX_CH12_DP 0x080 +#define MIPI_HW_HSI_TX_CH13_DP 0x084 +#define MIPI_HW_HSI_TX_CH14_DP 0x088 +#define MIPI_HW_HSI_TX_CH15_DP 0x08c +#define MIPI_HW_HSI_RX_CH0_DP 0x090 +#define MIPI_HW_HSI_RX_CH1_DP 0x094 +#define MIPI_HW_HSI_RX_CH2_DP 0x098 +#define MIPI_HW_HSI_RX_CH3_DP 0x09c +#define MIPI_HW_HSI_RX_CH4_DP 0x0a0 +#define MIPI_HW_HSI_RX_CH5_DP 0x0a4 +#define MIPI_HW_HSI_RX_CH6_DP 0x0a8 +#define MIPI_HW_HSI_RX_CH7_DP 0x0ac +#define MIPI_HW_HSI_RX_CH8_DP 0x0b0 +#define MIPI_HW_HSI_RX_CH9_DP 0x0b4 +#define MIPI_HW_HSI_RX_CH10_DP 0x0b8 +#define MIPI_HW_HSI_RX_CH11_DP 0x0bc +#define MIPI_HW_HSI_RX_CH12_DP 0x0c0 +#define MIPI_HW_HSI_RX_CH13_DP 0x0c4 +#define MIPI_HW_HSI_RX_CH14_DP 0x0c8 +#define MIPI_HW_HSI_RX_CH15_DP 0x0cc +#define MIPI_HW_HSI_ERR_IRQSTAT 0x0d0 +#define MIPI_HW_HSI_ERR_IRQSTAT_EN 0x0d4 +#define MIPI_HW_HSI_ERR_IRQSIG_EN 0x0d8 +#define MIPI_HW_HSI_TDMA0_CONF 0x0dc +#define MIPI_HW_HSI_TDMA1_CONF 0x0e0 +#define MIPI_HW_HSI_TDMA2_CONF 0x0e4 +#define MIPI_HW_HSI_TDMA3_CONF 0x0e8 +#define MIPI_HW_HSI_TDMA4_CONF 0x0ec +#define MIPI_HW_HSI_TDMA5_CONF 0x0f0 +#define MIPI_HW_HSI_TDMA6_CONF 0x0f4 +#define MIPI_HW_HSI_TDMA7_CONF 0x0f8 +#define MIPI_HW_HSI_TDMA8_CONF 0x0fc +#define MIPI_HW_HSI_TDMA9_CONF 0x100 +#define MIPI_HW_HSI_TDMA10_CONF 0x104 +#define MIPI_HW_HSI_TDMA11_CONF 0x108 +#define MIPI_HW_HSI_TDMA12_CONF 0x10c +#define MIPI_HW_HSI_TDMA13_CONF 0x110 +#define MIPI_HW_HSI_TDMA14_CONF 0x114 +#define MIPI_HW_HSI_TDMA15_CONF 0x118 +#define MIPI_HW_HSI_RDMA0_CONF 0x11c +#define MIPI_HW_HSI_RDMA1_CONF 0x120 +#define MIPI_HW_HSI_RDMA2_CONF 0x124 +#define MIPI_HW_HSI_RDMA3_CONF 0x128 +#define MIPI_HW_HSI_RDMA4_CONF 0x12c +#define MIPI_HW_HSI_RDMA5_CONF 0x130 +#define MIPI_HW_HSI_RDMA6_CONF 0x134 +#define MIPI_HW_HSI_RDMA7_CONF 0x138 +#define MIPI_HW_HSI_RDMA8_CONF 0x13c +#define MIPI_HW_HSI_RDMA9_CONF 0x140 +#define MIPI_HW_HSI_RDMA10_CONF 0x144 +#define MIPI_HW_HSI_RDMA11_CONF 0x148 +#define MIPI_HW_HSI_RDMA12_CONF 0x14c +#define MIPI_HW_HSI_RDMA13_CONF 0x150 +#define MIPI_HW_HSI_RDMA14_CONF 0x154 +#define MIPI_HW_HSI_RDMA15_CONF 0x158 +#define MIPI_HW_HSI_TDMA0_STA_ADDR 0x15c +#define MIPI_HW_HSI_TDMA1_STA_ADDR 0x160 +#define MIPI_HW_HSI_TDMA2_STA_ADDR 0x164 +#define MIPI_HW_HSI_TDMA3_STA_ADDR 0x168 +#define MIPI_HW_HSI_TDMA4_STA_ADDR 0x16c +#define MIPI_HW_HSI_TDMA5_STA_ADDR 0x170 +#define MIPI_HW_HSI_TDMA6_STA_ADDR 0x174 +#define MIPI_HW_HSI_TDMA7_STA_ADDR 0x178 +#define MIPI_HW_HSI_TDMA8_STA_ADDR 0x17c +#define MIPI_HW_HSI_TDMA9_STA_ADDR 0x180 +#define MIPI_HW_HSI_TDMA10_STA_ADDR 0x184 +#define MIPI_HW_HSI_TDMA11_STA_ADDR 0x188 +#define MIPI_HW_HSI_TDMA12_STA_ADDR 0x18c +#define MIPI_HW_HSI_TDMA13_STA_ADDR 0x190 +#define MIPI_HW_HSI_TDMA14_STA_ADDR 0x194 +#define MIPI_HW_HSI_TDMA15_STA_ADDR 0x198 +#define MIPI_HW_HSI_RDMA0_STA_ADDR 0x19c +#define MIPI_HW_HSI_RDMA1_STA_ADDR 0x1a0 +#define MIPI_HW_HSI_RDMA2_STA_ADDR 0x1a4 +#define MIPI_HW_HSI_RDMA3_STA_ADDR 0x1a8 +#define MIPI_HW_HSI_RDMA4_STA_ADDR 0x1ac +#define MIPI_HW_HSI_RDMA5_STA_ADDR 0x1b0 +#define MIPI_HW_HSI_RDMA6_STA_ADDR 0x1b4 +#define MIPI_HW_HSI_RDMA7_STA_ADDR 0x1b8 +#define MIPI_HW_HSI_RDMA8_STA_ADDR 0x1bc +#define MIPI_HW_HSI_RDMA9_STA_ADDR 0x1c0 +#define MIPI_HW_HSI_RDMA10_STA_ADDR 0x1c4 +#define MIPI_HW_HSI_RDMA11_STA_ADDR 0x1c8 +#define MIPI_HW_HSI_RDMA12_STA_ADDR 0x1cc +#define MIPI_HW_HSI_RDMA13_STA_ADDR 0x1d0 +#define MIPI_HW_HSI_RDMA14_STA_ADDR 0x1d4 +#define MIPI_HW_HSI_RDMA15_STA_ADDR 0x1d8 +#define MIPI_HW_HSI_DMA_IRQSTAT 0x1dc +#define MIPI_HW_HSI_DMA_IRQSTAT_EN 0x1e0 +#define MIPI_HW_HSI_DMA_IRQSIG_EN 0x1e4 +#define MIPI_HW_HSI_DMA_ERR_IRQSTAT 0x1e8 +#define MIPI_HW_HSI_DMA_ERR_IRQSTAT_EN 0x1ec +#define MIPI_HW_HSI_DMA_ERR_IRQSIG_EN 0x1f0 +#define MIPI_HW_HSI_DMA_SINGLE_REQ_EN 0x1f4 +#define MIPI_HW_HSI_TX_FIFO_SIZE_CONF0 0x200 +#define MIPI_HW_HSI_TX_FIFO_SIZE_CONF1 0x204 +#define MIPI_HW_HSI_RX_FIFO_SIZE_CONF0 0x208 +#define MIPI_HW_HSI_RX_FIFO_SIZE_CONF1 0x20c +#define MIPI_HW_HSI_TX_FIFO_STAT 0x210 +#define MIPI_HW_HSI_RX_FIFO_STAT 0x214 +#define MIPI_HW_HSI_DLL_CTRL 0x220 +#define MIPI_HW_HSI_DLL_STAT 0x224 + +//////////////////////////////////////////////////////////////////////////////// +// Description: common definitions used by all blocks of PIO Registers for SGTL IPs +// +// Register definitions from SigmaTel, Inc. Unpublished +#ifndef SIGMATEL_DEFS +#define SIGMATEL_DEFS + +// define base address of the register block only if it is not already +// defined, which allows the compiler to override at build time for +// users who've mapped their registers to locations other than the +// physical location +// + +#ifndef REGS_BASE +#define REGS_BASE 0x00000000 +#endif + +// +// common register types +// + +#ifndef __LANGUAGE_ASM__ +typedef unsigned char reg8_t; +typedef unsigned short reg16_t; +typedef unsigned int reg32_t; +#endif + +// +// macros for single instance registers +// + +#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) +#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) +#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) + +#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) +#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) +#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) + +#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BF_RD(reg, field) HW_##reg.B.field +#define BF_WR(reg, field, v) BW_##reg##_##field(v) + +#define BF_CS1(reg, f1, v1) \ + (HW_##reg##_CLR(BM_##reg##_##f1), \ + HW_##reg##_SET(BF_##reg##_##f1(v1))) + +#define BF_CS2(reg, f1, v1, f2, v2) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +// +// macros for multiple instance registers +// + +#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) +#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) +#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) + +#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) +#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) +#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) + +#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym + +#define BF_RDn(reg, n, field) HW_##reg(n).B.field +#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) + +#define BF_CS1n(reg, n, f1, v1) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) + +#define BF_CS2n(reg, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +// +// macros for single instance MULTI-BLOCK registers +// + +#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) +#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) +#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) + +#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) +#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) +#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) + +#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field +#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) + +#define BFn_CS1(reg, blk, f1, v1) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) + +#define BFn_CS2(reg, blk, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +// +// macros for MULTI-BLOCK multiple instance registers +// + +#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) +#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) +#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) + +#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) +#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) +#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) + +#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field +#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) + +#define BFn_CS1n(reg, blk, n, f1, v1) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) + +#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +#endif // SIGMATEL_DEFS + +//////////////////////////////////////////////////////////////////////////////// +// End SigmaTel common definitions used by all blocks of PIO Registers diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regs.h b/bsp/imx6ul/platform/include/mx6ul/registers/regs.h new file mode 100644 index 0000000000000000000000000000000000000000..fe0b81e486eb565f3277996bf734f2c04b93b5bd --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regs.h @@ -0,0 +1,479 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ + +#ifndef _REGS_H +#define _REGS_H 1 + +// +// define base address of the register block only if it is not already +// defined, which allows the compiler to override at build time for +// users who've mapped their registers to locations other than the +// physical location +// + +#ifndef REGS_BASE +#define REGS_BASE 0x00000000 +#endif + +// +// common register types +// + +#ifndef __LANGUAGE_ASM__ +typedef unsigned char reg8_t; +typedef unsigned short reg16_t; +typedef unsigned int reg32_t; +#endif + +// +// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is +// used to simplify macro definitions in the module register headers. +// +#ifndef __REG_VALUE_TYPE + #ifndef __LANGUAGE_ASM__ + #define __REG_VALUE_TYPE(v, t) ((t)(v)) + #else + #define __REG_VALUE_TYPE(v, t) (v) + #endif +#endif + +// +// macros for single instance registers +// + +#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) +#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) +#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) + +#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) +#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) +#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) + +#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BF_RD(reg, field) HW_##reg.B.field +#define BF_WR(reg, field, v) BW_##reg##_##field(v) + +#define BF_CS1(reg, f1, v1) \ + (HW_##reg##_CLR(BM_##reg##_##f1), \ + HW_##reg##_SET(BF_##reg##_##f1(v1))) + +#define BF_CS2(reg, f1, v1, f2, v2) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +// +// macros for multiple instance registers +// + +#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) +#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) +#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) + +#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) +#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) +#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) + +#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym + +#define BF_RDn(reg, n, field) HW_##reg(n).B.field +#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) + +#define BF_CS1n(reg, n, f1, v1) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) + +#define BF_CS2n(reg, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +// +// macros for single instance MULTI-BLOCK registers +// + +#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) +#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) +#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) + +#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) +#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) +#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) + +#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field +#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) + +#define BFn_CS1(reg, blk, f1, v1) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) + +#define BFn_CS2(reg, blk, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +// +// macros for MULTI-BLOCK multiple instance registers +// + +#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) +#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) +#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) + +#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) +#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) +#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) + +#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field +#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) + +#define BFn_CS1n(reg, blk, n, f1, v1) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) + +#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +#endif // _REGS_H + +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsarmglobaltimer.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsarmglobaltimer.h new file mode 100644 index 0000000000000000000000000000000000000000..94837c46f3a154778aab642990b3d496b76204b1 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsarmglobaltimer.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_ARMGLOBALTIMER_REGISTERS_H__ +#define __HW_ARMGLOBALTIMER_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL ARMGLOBALTIMER + * + * ARM Cortex-A9 Global Timer + * + * Registers defined in this header file: + * - HW_ARMGLOBALTIMER_COUNTERn - Global Timer Counter Registers + * - HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register + * - HW_ARMGLOBALTIMER_IRQSTATUS - Global Timer Interrupt Status Register + * - HW_ARMGLOBALTIMER_COMPARATORn - Global Timer Comparator Value Registers + * - HW_ARMGLOBALTIMER_AUTOINCREMENT - Global Timer Auto-increment Register + * + * - hw_armglobaltimer_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_ARMGLOBALTIMER_BASE +#define HW_ARMGLOBALTIMER_INSTANCE_COUNT (1) //!< Number of instances of the ARMGLOBALTIMER module. +#define REGS_ARMGLOBALTIMER_BASE (0x021DC000) //!< Base address for ARMGLOBALTIMER. +#endif +//@} + + +//------------------------------------------------------------------------------------------- +// HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register (RW) + * + * Reset value: 0x00000000 + * + * Configuration and control of the Global Timer. + */ +typedef union _hw_armglobaltimer_control +{ + reg32_t U; + struct _hw_armglobaltimer_control_bitfields + { + unsigned TIMER_ENABLE : 1; //!< [0] Timer enable. + unsigned DBG_ENABLE : 1; //!< [1] This bit is banked per Cortex-A9 processor. + unsigned RESERVED0 : 6; //!< [2] This bit is banked per Cortex-A9 processor. + unsigned FCR0 : 1; //!< [3] This bit is banked per Cortex-A9 processor. + unsigned FCR1 : 1; //!< [7:4] Reserved + unsigned RESERVED1 : 22; //!< [31:16] Reserved. + } B; +} hw_armglobaltimer_control_t; +#endif + +/*! + * @name Constants and macros for entire ARMGLOBALTIMER_CONTROL register + */ +//@{ +#define HW_ARMGLOBALTIMER_CONTROL_ADDR (REGS_ARMGLOBALTIMER_BASE + 0x000) + +#ifndef __LANGUAGE_ASM__ +#define HW_ARMGLOBALTIMER_CONTROL (*(volatile hw_armglobaltimer_control_t *) HW_ARMGLOBALTIMER_CONTROL_ADDR) +#define HW_ARMGLOBALTIMER_CONTROL_RD() (HW_ARMGLOBALTIMER_CONTROL.U) +#define HW_ARMGLOBALTIMER_CONTROL_WR(v) (HW_ARMGLOBALTIMER_CONTROL.U = (v)) +#define HW_ARMGLOBALTIMER_CONTROL_SET(v) (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() | (v))) +#define HW_ARMGLOBALTIMER_CONTROL_CLR(v) (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() & ~(v))) +#define HW_ARMGLOBALTIMER_CONTROL_TOG(v) (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() ^ (v))) +#endif +//@} + + +#define HW_ARMGLOBALTIMER_COUNTER_LO_ADDR (REGS_ARMGLOBALTIMER_BASE + 0x008) + +#ifndef __LANGUAGE_ASM__ +#define HW_ARMGLOBALTIMER_COUNTER_LO (*(volatile unsigned *) HW_ARMGLOBALTIMER_COUNTER_LO_ADDR) +#define HW_ARMGLOBALTIMER_COUNTER_LO_RD() (HW_ARMGLOBALTIMER_COUNTER_LO) +#define HW_ARMGLOBALTIMER_COUNTER_LO_WR(v) (HW_ARMGLOBALTIMER_COUNTER_LO = (v)) +#endif + +#define HW_ARMGLOBALTIMER_COUNTER_HI_ADDR (REGS_ARMGLOBALTIMER_BASE + 0x00C) + +#ifndef __LANGUAGE_ASM__ +#define HW_ARMGLOBALTIMER_COUNTER_HI (*(volatile unsigned *) HW_ARMGLOBALTIMER_COUNTER_HI_ADDR) +#define HW_ARMGLOBALTIMER_COUNTER_HI_RD() (HW_ARMGLOBALTIMER_COUNTER_HI) +#define HW_ARMGLOBALTIMER_COUNTER_HI_WR(v) (HW_ARMGLOBALTIMER_COUNTER_HI = (v)) +#endif + +#endif // __HW_ARMGLOBALTIMER_REGISTERS_H__ + diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsccm.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsccm.h new file mode 100644 index 0000000000000000000000000000000000000000..f2f516644c91320f1486543cbfe5804b4b218348 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsccm.h @@ -0,0 +1,8596 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_CCM_REGISTERS_H__ +#define __HW_CCM_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL CCM + * + * CCM + * + * Registers defined in this header file: + * - HW_CCM_CCR - CCM Control Register + * - HW_CCM_CCDR - CCM Control Divider Register + * - HW_CCM_CSR - CCM Status Register + * - HW_CCM_CCSR - CCM Clock Swither Register + * - HW_CCM_CACRR - CCM Arm Clock Root Register + * - HW_CCM_CBCDR - CCM Bus Clock Divider Register + * - HW_CCM_CBCMR - CCM Bus Clock Multiplexer Register + * - HW_CCM_CSCMR1 - CCM Serial Clock Multiplexer Register 1 + * - HW_CCM_CSCMR2 - CCM Serial Clock Multiplexer Register 2 + * - HW_CCM_CSCDR1 - CCM Serial Clock Divider Register 1 + * - HW_CCM_CS1CDR - CCM SSI1 Clock Divider Register + * - HW_CCM_CS2CDR - CCM SSI2 Clock Divider Register + * - HW_CCM_CDCDR - CCM D1 Clock Divider Register + * - HW_CCM_CHSCCDR - CCM HSC Clock Divider Register + * - HW_CCM_CSCDR2 - CCM Serial Clock Divider Register 2 + * - HW_CCM_CSCDR3 - CCM Serial Clock Divider Register 3 + * - HW_CCM_CWDR - CCM Wakeup Detector Register + * - HW_CCM_CDHIPR - CCM Divider Handshake In-Process Register + * - HW_CCM_CTOR - CCM Testing Observability Register + * - HW_CCM_CLPCR - CCM Low Power Control Register + * - HW_CCM_CISR - CCM Interrupt Status Register + * - HW_CCM_CIMR - CCM Interrupt Mask Register + * - HW_CCM_CCOSR - CCM Clock Output Source Register + * - HW_CCM_CGPR - CCM General Purpose Register + * - HW_CCM_CCGR0 - CCM Clock Gating Register 0 + * - HW_CCM_CCGR1 - CCM Clock Gating Register 1 + * - HW_CCM_CCGR2 - CCM Clock Gating Register 2 + * - HW_CCM_CCGR3 - CCM Clock Gating Register 3 + * - HW_CCM_CCGR4 - CCM Clock Gating Register 4 + * - HW_CCM_CCGR5 - CCM Clock Gating Register 5 + * - HW_CCM_CCGR6 - CCM Clock Gating Register 6 + * - HW_CCM_CMEOR - CCM Module Enable Overide Register + * + * - hw_ccm_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_CCM_BASE +#define HW_CCM_INSTANCE_COUNT (1) //!< Number of instances of the CCM module. +#define REGS_CCM_BASE (0x020c4000) //!< Base address for CCM. +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCR - CCM Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCR - CCM Control Register (RW) + * + * Reset value: 0x040116ff + * + * The figure below represents the CCM Control Register (CCR), which contains bits to control + * general operation of CCM. The table below provides its field descriptions. + */ +typedef union _hw_ccm_ccr +{ + reg32_t U; + struct _hw_ccm_ccr_bitfields + { + unsigned OSCNT : 8; //!< [7:0] Oscillator ready counter value. + unsigned RESERVED0 : 4; //!< [11:8] Reserved + unsigned COSC_EN : 1; //!< [12] On chip oscillator enable bit - this bit value is reflected on the output cosc_en. + unsigned RESERVED1 : 3; //!< [15:13] Reserved + unsigned WB_COUNT : 3; //!< [18:16] Well Bias counter. + unsigned RESERVED2 : 2; //!< [20:19] Reserved + unsigned REG_BYPASS_COUNT : 6; //!< [26:21] Counter for analog_reg_bypass signal assertion after standby voltage request by pmic_vstby_req. + unsigned RBC_EN : 1; //!< [27] Enable for REG_BYPASS_COUNTER. + unsigned RESERVED3 : 4; //!< [31:28] Reserved + } B; +} hw_ccm_ccr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCR register + */ +//@{ +#define HW_CCM_CCR_ADDR (REGS_CCM_BASE + 0x0) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCR (*(volatile hw_ccm_ccr_t *) HW_CCM_CCR_ADDR) +#define HW_CCM_CCR_RD() (HW_CCM_CCR.U) +#define HW_CCM_CCR_WR(v) (HW_CCM_CCR.U = (v)) +#define HW_CCM_CCR_SET(v) (HW_CCM_CCR_WR(HW_CCM_CCR_RD() | (v))) +#define HW_CCM_CCR_CLR(v) (HW_CCM_CCR_WR(HW_CCM_CCR_RD() & ~(v))) +#define HW_CCM_CCR_TOG(v) (HW_CCM_CCR_WR(HW_CCM_CCR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCR bitfields + */ + +/*! @name Register CCM_CCR, field OSCNT[7:0] (RW) + * + * Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter + * for oscillator lock time. This is used for oscillator lock time. Current estimation is ~5ms. This + * counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was + * defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then + * the gate in dpll_ip can be opened. + * + * Values: + * - 00000000 - count 1 ckil + * - 11111111 - count 256 ckil's (default) + */ +//@{ +#define BP_CCM_CCR_OSCNT (0) //!< Bit position for CCM_CCR_OSCNT. +#define BM_CCM_CCR_OSCNT (0x0000007f) //!< Bit mask for CCM_CCR_OSCNT. + +//! @brief Get value of CCM_CCR_OSCNT from a register value. +#define BG_CCM_CCR_OSCNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCR_OSCNT) >> BP_CCM_CCR_OSCNT) + +//! @brief Format value for bitfield CCM_CCR_OSCNT. +#define BF_CCM_CCR_OSCNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCR_OSCNT) & BM_CCM_CCR_OSCNT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OSCNT field to a new value. +#define BW_CCM_CCR_OSCNT(v) (HW_CCM_CCR_WR((HW_CCM_CCR_RD() & ~BM_CCM_CCR_OSCNT) | BF_CCM_CCR_OSCNT(v))) +#endif +//@} + +/*! @name Register CCM_CCR, field COSC_EN[12] (RW) + * + * On chip oscillator enable bit - this bit value is reflected on the output cosc_en. The system + * will start with on chip oscillator enabled to supply source for the PLL's. Software can change + * this bit if a transition to the bypass PLL clocks was performed for all the PLLs. In cases that + * this bit is changed from '0' to '1' then CCM will enable the on chip oscillator and after + * counting oscnt ckil clock cycles it will notify that on chip oscillator is ready by a interrupt + * cosc_ready and by status bit cosc_ready. The cosc_en bit should be changed only when on chip + * oscillator is not chosen as the clock source. + * + * Values: + * - 0 - disable on chip oscillator + * - 1 - enable on chip oscillator + */ +//@{ +#define BP_CCM_CCR_COSC_EN (12) //!< Bit position for CCM_CCR_COSC_EN. +#define BM_CCM_CCR_COSC_EN (0x00001000) //!< Bit mask for CCM_CCR_COSC_EN. + +//! @brief Get value of CCM_CCR_COSC_EN from a register value. +#define BG_CCM_CCR_COSC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCR_COSC_EN) >> BP_CCM_CCR_COSC_EN) + +//! @brief Format value for bitfield CCM_CCR_COSC_EN. +#define BF_CCM_CCR_COSC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCR_COSC_EN) & BM_CCM_CCR_COSC_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the COSC_EN field to a new value. +#define BW_CCM_CCR_COSC_EN(v) (HW_CCM_CCR_WR((HW_CCM_CCR_RD() & ~BM_CCM_CCR_COSC_EN) | BF_CCM_CCR_COSC_EN(v))) +#endif +//@} + +/*! @name Register CCM_CCR, field WB_COUNT[18:16] (RW) + * + * Well Bias counter. Delay, defined by this value, counted by CKIL clock will be applied till well + * bias is enabled at exit from wait or stop low power mode. Counter will be used if wb_core_at_lpm + * or wb_per_at_lpm bits are set. Should be zeroed and reconfigured after exit from low power mode. + * + * Values: + * - 000 - no delay + * - 001 - 1 CKIL clock delay + * - 111 - 7 CKIL clocks delay + */ +//@{ +#define BP_CCM_CCR_WB_COUNT (16) //!< Bit position for CCM_CCR_WB_COUNT. +#define BM_CCM_CCR_WB_COUNT (0x00070000) //!< Bit mask for CCM_CCR_WB_COUNT. + +//! @brief Get value of CCM_CCR_WB_COUNT from a register value. +#define BG_CCM_CCR_WB_COUNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCR_WB_COUNT) >> BP_CCM_CCR_WB_COUNT) + +//! @brief Format value for bitfield CCM_CCR_WB_COUNT. +#define BF_CCM_CCR_WB_COUNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCR_WB_COUNT) & BM_CCM_CCR_WB_COUNT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WB_COUNT field to a new value. +#define BW_CCM_CCR_WB_COUNT(v) (HW_CCM_CCR_WR((HW_CCM_CCR_RD() & ~BM_CCM_CCR_WB_COUNT) | BF_CCM_CCR_WB_COUNT(v))) +#endif +//@} + +/*! @name Register CCM_CCR, field REG_BYPASS_COUNT[26:21] (RW) + * + * Counter for analog_reg_bypass signal assertion after standby voltage request by pmic_vstby_req. + * Should be zeroed and reconfigured after exit from low power mode. + * + * Values: + * - 000000 - no delay + * - 000001 - 1 CKIL clock period delay + * - 111111 - 63 CKIL clock periods delay + */ +//@{ +#define BP_CCM_CCR_REG_BYPASS_COUNT (21) //!< Bit position for CCM_CCR_REG_BYPASS_COUNT. +#define BM_CCM_CCR_REG_BYPASS_COUNT (0x07e00000) //!< Bit mask for CCM_CCR_REG_BYPASS_COUNT. + +//! @brief Get value of CCM_CCR_REG_BYPASS_COUNT from a register value. +#define BG_CCM_CCR_REG_BYPASS_COUNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCR_REG_BYPASS_COUNT) >> BP_CCM_CCR_REG_BYPASS_COUNT) + +//! @brief Format value for bitfield CCM_CCR_REG_BYPASS_COUNT. +#define BF_CCM_CCR_REG_BYPASS_COUNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCR_REG_BYPASS_COUNT) & BM_CCM_CCR_REG_BYPASS_COUNT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the REG_BYPASS_COUNT field to a new value. +#define BW_CCM_CCR_REG_BYPASS_COUNT(v) (HW_CCM_CCR_WR((HW_CCM_CCR_RD() & ~BM_CCM_CCR_REG_BYPASS_COUNT) | BF_CCM_CCR_REG_BYPASS_COUNT(v))) +#endif +//@} + +/*! @name Register CCM_CCR, field RBC_EN[27] (RW) + * + * Enable for REG_BYPASS_COUNTER. If enabled, analog_reg_bypass signal will be asserted after + * REG_BYPASS_COUNT clocks of CKIL, after standby voltage is requested. If standby voltage is not + * requested analog_reg_bypass won't be asserted, event if counter is enabled. + * + * Values: + * - 0 - REG_BYPASS_COUNTER disabled + * - 1 - REG_BYPASS_COUNTER enabled. + */ +//@{ +#define BP_CCM_CCR_RBC_EN (27) //!< Bit position for CCM_CCR_RBC_EN. +#define BM_CCM_CCR_RBC_EN (0x08000000) //!< Bit mask for CCM_CCR_RBC_EN. + +//! @brief Get value of CCM_CCR_RBC_EN from a register value. +#define BG_CCM_CCR_RBC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCR_RBC_EN) >> BP_CCM_CCR_RBC_EN) + +//! @brief Format value for bitfield CCM_CCR_RBC_EN. +#define BF_CCM_CCR_RBC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCR_RBC_EN) & BM_CCM_CCR_RBC_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RBC_EN field to a new value. +#define BW_CCM_CCR_RBC_EN(v) (HW_CCM_CCR_WR((HW_CCM_CCR_RD() & ~BM_CCM_CCR_RBC_EN) | BF_CCM_CCR_RBC_EN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCDR - CCM Control Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCDR - CCM Control Divider Register (RW) + * + * Reset value: 0x00000000 + * + * The figure below represents the CCM Control Divider Register (CCDR), which contains bits that + * control the loading of the dividers that need handshake with the modules they affect. The table + * below provides its field descriptions. + */ +typedef union _hw_ccm_ccdr +{ + reg32_t U; + struct _hw_ccm_ccdr_bitfields + { + unsigned RESERVED0 : 16; //!< [15:0] Reserved + unsigned MMDC_CH1_MASK : 1; //!< [16] During divider ratio mmdc_ch1_axi_podf change or sync mux periph2_clk_sel change (but not jtag) or SRC request during warm reset, mask handshake with mmdc_ch1 module. + unsigned MMDC_CH0_MASK : 1; //!< [17] During divider ratio mmdc_ch0_axi_podf change or sync mux periph_clk_sel change (but not jtag) or SRC request during warm reset, mask handshake with mmdc_ch0 module. + unsigned RESERVED1 : 14; //!< [31:18] Reserved + } B; +} hw_ccm_ccdr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCDR register + */ +//@{ +#define HW_CCM_CCDR_ADDR (REGS_CCM_BASE + 0x4) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCDR (*(volatile hw_ccm_ccdr_t *) HW_CCM_CCDR_ADDR) +#define HW_CCM_CCDR_RD() (HW_CCM_CCDR.U) +#define HW_CCM_CCDR_WR(v) (HW_CCM_CCDR.U = (v)) +#define HW_CCM_CCDR_SET(v) (HW_CCM_CCDR_WR(HW_CCM_CCDR_RD() | (v))) +#define HW_CCM_CCDR_CLR(v) (HW_CCM_CCDR_WR(HW_CCM_CCDR_RD() & ~(v))) +#define HW_CCM_CCDR_TOG(v) (HW_CCM_CCDR_WR(HW_CCM_CCDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCDR bitfields + */ + +/*! @name Register CCM_CCDR, field MMDC_CH1_MASK[16] (RW) + * + * During divider ratio mmdc_ch1_axi_podf change or sync mux periph2_clk_sel change (but not jtag) + * or SRC request during warm reset, mask handshake with mmdc_ch1 module. + * + * Values: + * - 0 - allow handshake with mmdc_ch1 module + * - 1 - mask handshake with mmdc_ch1. Request signal will not be generated. + */ +//@{ +#define BP_CCM_CCDR_MMDC_CH1_MASK (16) //!< Bit position for CCM_CCDR_MMDC_CH1_MASK. +#define BM_CCM_CCDR_MMDC_CH1_MASK (0x00010000) //!< Bit mask for CCM_CCDR_MMDC_CH1_MASK. + +//! @brief Get value of CCM_CCDR_MMDC_CH1_MASK from a register value. +#define BG_CCM_CCDR_MMDC_CH1_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCDR_MMDC_CH1_MASK) >> BP_CCM_CCDR_MMDC_CH1_MASK) + +//! @brief Format value for bitfield CCM_CCDR_MMDC_CH1_MASK. +#define BF_CCM_CCDR_MMDC_CH1_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCDR_MMDC_CH1_MASK) & BM_CCM_CCDR_MMDC_CH1_MASK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MMDC_CH1_MASK field to a new value. +#define BW_CCM_CCDR_MMDC_CH1_MASK(v) (HW_CCM_CCDR_WR((HW_CCM_CCDR_RD() & ~BM_CCM_CCDR_MMDC_CH1_MASK) | BF_CCM_CCDR_MMDC_CH1_MASK(v))) +#endif +//@} + +/*! @name Register CCM_CCDR, field MMDC_CH0_MASK[17] (RW) + * + * During divider ratio mmdc_ch0_axi_podf change or sync mux periph_clk_sel change (but not jtag) or + * SRC request during warm reset, mask handshake with mmdc_ch0 module. + * + * Values: + * - 0 - allow handshake with mmdc_ch0 module + * - 1 - mask handshake with mmdc_ch0. Request signal will not be generated. + */ +//@{ +#define BP_CCM_CCDR_MMDC_CH0_MASK (17) //!< Bit position for CCM_CCDR_MMDC_CH0_MASK. +#define BM_CCM_CCDR_MMDC_CH0_MASK (0x00020000) //!< Bit mask for CCM_CCDR_MMDC_CH0_MASK. + +//! @brief Get value of CCM_CCDR_MMDC_CH0_MASK from a register value. +#define BG_CCM_CCDR_MMDC_CH0_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCDR_MMDC_CH0_MASK) >> BP_CCM_CCDR_MMDC_CH0_MASK) + +//! @brief Format value for bitfield CCM_CCDR_MMDC_CH0_MASK. +#define BF_CCM_CCDR_MMDC_CH0_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCDR_MMDC_CH0_MASK) & BM_CCM_CCDR_MMDC_CH0_MASK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MMDC_CH0_MASK field to a new value. +#define BW_CCM_CCDR_MMDC_CH0_MASK(v) (HW_CCM_CCDR_WR((HW_CCM_CCDR_RD() & ~BM_CCM_CCDR_MMDC_CH0_MASK) | BF_CCM_CCDR_MMDC_CH0_MASK(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CSR - CCM Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CSR - CCM Status Register (RO) + * + * Reset value: 0x00000010 + * + * The figure below represents the CCM status Register (CSR). The status bits are read only bits. + * The table below provides its field descriptions. + */ +typedef union _hw_ccm_csr +{ + reg32_t U; + struct _hw_ccm_csr_bitfields + { + unsigned REF_EN_B : 1; //!< [0] Status of the value of CCM_REF_EN_B output of ccm + unsigned RESERVED0 : 4; //!< [4:1] Reserved. + unsigned COSC_READY : 1; //!< [5] Status indication of on board oscillator. + unsigned RESERVED1 : 26; //!< [31:6] Reserved + } B; +} hw_ccm_csr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CSR register + */ +//@{ +#define HW_CCM_CSR_ADDR (REGS_CCM_BASE + 0x8) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CSR (*(volatile hw_ccm_csr_t *) HW_CCM_CSR_ADDR) +#define HW_CCM_CSR_RD() (HW_CCM_CSR.U) +#endif +//@} + +/* + * constants & macros for individual CCM_CSR bitfields + */ + +/*! @name Register CCM_CSR, field REF_EN_B[0] (RO) + * + * Status of the value of CCM_REF_EN_B output of ccm + * + * Values: + * - 0 - value of CCM_REF_EN_B is '0' + * - 1 - value of CCM_REF_EN_B is '1' + */ +//@{ +#define BP_CCM_CSR_REF_EN_B (0) //!< Bit position for CCM_CSR_REF_EN_B. +#define BM_CCM_CSR_REF_EN_B (0x00000001) //!< Bit mask for CCM_CSR_REF_EN_B. + +//! @brief Get value of CCM_CSR_REF_EN_B from a register value. +#define BG_CCM_CSR_REF_EN_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSR_REF_EN_B) >> BP_CCM_CSR_REF_EN_B) +//@} + +/*! @name Register CCM_CSR, field COSC_READY[5] (RO) + * + * Status indication of on board oscillator. This bit will be asserted if on chip oscillator is + * enabled and on chip oscillator is not powered down, and if oscnt counter has finished counting. + * + * Values: + * - 0 - on board oscillator is not ready. + * - 1 - on board oscillator is ready. + */ +//@{ +#define BP_CCM_CSR_COSC_READY (5) //!< Bit position for CCM_CSR_COSC_READY. +#define BM_CCM_CSR_COSC_READY (0x00000020) //!< Bit mask for CCM_CSR_COSC_READY. + +//! @brief Get value of CCM_CSR_COSC_READY from a register value. +#define BG_CCM_CSR_COSC_READY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSR_COSC_READY) >> BP_CCM_CSR_COSC_READY) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCSR - CCM Clock Swither Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCSR - CCM Clock Swither Register (RW) + * + * Reset value: 0x00000100 + * + * The figure below represents the CCM Clock Switcher register (CCSR). The CCSR register contains + * bits to control the switcher sub module dividers and multiplexers. The table below provides its + * field descriptions. + */ +typedef union _hw_ccm_ccsr +{ + reg32_t U; + struct _hw_ccm_ccsr_bitfields + { + unsigned PLL3_SW_CLK_SEL : 1; //!< [0] Selects source to generate pll3_sw_clk. + unsigned PLL2_SW_CLK_SEL : 1; //!< [1] Selects source to generate pll2_sw_clk. + unsigned PLL1_SW_CLK_SEL : 1; //!< [2] Selects source to generate pll1_sw_clk. + unsigned RESERVED0 : 5; //!< [7:3] Reserved + unsigned STEP_SEL : 1; //!< [8] Selects the option to be chosen for the step frequency when shifting ARM frequency. + unsigned PDF_396M_DIS_MASK : 1; //!< [9] Mask of 396M PFD auto-disable. + unsigned PDF_307M_DIS_MASK : 1; //!< [10] Mask of 307M PFD auto-disable. + unsigned PDF_528M_DIS_MASK : 1; //!< [11] Mask of 528M PFD auto-disable. + unsigned PDF_508M_DIS_MASK : 1; //!< [12] Mask of 508M PFD auto-disable. + unsigned RESERVED1 : 2; //!< [14:13] Reserved. + unsigned PDF_540M_DIS_MASK : 1; //!< [15] Mask of 540M PFD auto-disable. + unsigned RESERVED2 : 16; //!< [31:16] Reserved + } B; +} hw_ccm_ccsr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCSR register + */ +//@{ +#define HW_CCM_CCSR_ADDR (REGS_CCM_BASE + 0xc) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCSR (*(volatile hw_ccm_ccsr_t *) HW_CCM_CCSR_ADDR) +#define HW_CCM_CCSR_RD() (HW_CCM_CCSR.U) +#define HW_CCM_CCSR_WR(v) (HW_CCM_CCSR.U = (v)) +#define HW_CCM_CCSR_SET(v) (HW_CCM_CCSR_WR(HW_CCM_CCSR_RD() | (v))) +#define HW_CCM_CCSR_CLR(v) (HW_CCM_CCSR_WR(HW_CCM_CCSR_RD() & ~(v))) +#define HW_CCM_CCSR_TOG(v) (HW_CCM_CCSR_WR(HW_CCM_CCSR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCSR bitfields + */ + +/*! @name Register CCM_CCSR, field PLL3_SW_CLK_SEL[0] (RW) + * + * Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes. Note: + * this bit will be ored with pll_bypass_en3 signal. If one of the sources requests to move to pll3 + * bypass clk (pll3_sw_clk=1 or pll_bypass_en3=1) then the pll3_sw_clk will be pll3 bypass clk. Only + * if both sources request pll3_main_clk (pll3_sw_clk=0 and pll_bypass_en3=0) then the pll3_sw_clk + * will be pll3_main_clk. + * + * Values: + * - 0 - pll3_main_clk(default) + * - 1 - pll3 bypass clock + */ +//@{ +#define BP_CCM_CCSR_PLL3_SW_CLK_SEL (0) //!< Bit position for CCM_CCSR_PLL3_SW_CLK_SEL. +#define BM_CCM_CCSR_PLL3_SW_CLK_SEL (0x00000001) //!< Bit mask for CCM_CCSR_PLL3_SW_CLK_SEL. + +//! @brief Get value of CCM_CCSR_PLL3_SW_CLK_SEL from a register value. +#define BG_CCM_CCSR_PLL3_SW_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_PLL3_SW_CLK_SEL) >> BP_CCM_CCSR_PLL3_SW_CLK_SEL) + +//! @brief Format value for bitfield CCM_CCSR_PLL3_SW_CLK_SEL. +#define BF_CCM_CCSR_PLL3_SW_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_PLL3_SW_CLK_SEL) & BM_CCM_CCSR_PLL3_SW_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PLL3_SW_CLK_SEL field to a new value. +#define BW_CCM_CCSR_PLL3_SW_CLK_SEL(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_PLL3_SW_CLK_SEL) | BF_CCM_CCSR_PLL3_SW_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CCSR, field PLL2_SW_CLK_SEL[1] (RW) + * + * Selects source to generate pll2_sw_clk. This bit should only be used for testing purposes. Note: + * this bit will be ored with pll_bypass_en2 signal. If one of the sources requests to move to pll2 + * bypass clk (pll2_sw_clk=1 or pll_bypass_en2=1) then the pll2_sw_clk will be pll2 bypass clk. Only + * if both sources request pll2_main_clk (pll2_sw_clk=0 and pll_bypass_en2=0) then the pll2_sw_clk + * will be pll2_main_clk. + * + * Values: + * - 0 - pll2_main_clk(default) + * - 1 - pll2 bypass clock + */ +//@{ +#define BP_CCM_CCSR_PLL2_SW_CLK_SEL (1) //!< Bit position for CCM_CCSR_PLL2_SW_CLK_SEL. +#define BM_CCM_CCSR_PLL2_SW_CLK_SEL (0x00000002) //!< Bit mask for CCM_CCSR_PLL2_SW_CLK_SEL. + +//! @brief Get value of CCM_CCSR_PLL2_SW_CLK_SEL from a register value. +#define BG_CCM_CCSR_PLL2_SW_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_PLL2_SW_CLK_SEL) >> BP_CCM_CCSR_PLL2_SW_CLK_SEL) + +//! @brief Format value for bitfield CCM_CCSR_PLL2_SW_CLK_SEL. +#define BF_CCM_CCSR_PLL2_SW_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_PLL2_SW_CLK_SEL) & BM_CCM_CCSR_PLL2_SW_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PLL2_SW_CLK_SEL field to a new value. +#define BW_CCM_CCSR_PLL2_SW_CLK_SEL(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_PLL2_SW_CLK_SEL) | BF_CCM_CCSR_PLL2_SW_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CCSR, field PLL1_SW_CLK_SEL[2] (RW) + * + * Selects source to generate pll1_sw_clk. Note: this bit will be ored with pll_bypass_en1 signal + * and dvfs_control signal. If one of the sources requests to move to step_clk (pll1_sw_clk=1 or + * pll_bypass_en1=1 or dvfs_control=1) then the pll1_sw_clk will be step_clk. Only if both sources + * request pll1_main_clk (pll1_sw_clk=0 and pll_bypass_en1=0 and dvfs_control=0) then the + * pll1_sw_clk will be pll1_main_clk. + * + * Values: + * - 0 - pll1_main_clk(default) + * - 1 - step_clk + */ +//@{ +#define BP_CCM_CCSR_PLL1_SW_CLK_SEL (2) //!< Bit position for CCM_CCSR_PLL1_SW_CLK_SEL. +#define BM_CCM_CCSR_PLL1_SW_CLK_SEL (0x00000004) //!< Bit mask for CCM_CCSR_PLL1_SW_CLK_SEL. + +//! @brief Get value of CCM_CCSR_PLL1_SW_CLK_SEL from a register value. +#define BG_CCM_CCSR_PLL1_SW_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_PLL1_SW_CLK_SEL) >> BP_CCM_CCSR_PLL1_SW_CLK_SEL) + +//! @brief Format value for bitfield CCM_CCSR_PLL1_SW_CLK_SEL. +#define BF_CCM_CCSR_PLL1_SW_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_PLL1_SW_CLK_SEL) & BM_CCM_CCSR_PLL1_SW_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PLL1_SW_CLK_SEL field to a new value. +#define BW_CCM_CCSR_PLL1_SW_CLK_SEL(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_PLL1_SW_CLK_SEL) | BF_CCM_CCSR_PLL1_SW_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CCSR, field STEP_SEL[8] (RW) + * + * Selects the option to be chosen for the step frequency when shifting ARM frequency. this will + * control the step_clk. Note: this mux is allowed to be changed only if its output is not used, + * i.e. ARM uses the output of pll1, and step_clk is not used. + * + * Values: + * - 0 - clock source 4 - source for lp_apm. (default) + * - 1 - pll2 PDF clock + */ +//@{ +#define BP_CCM_CCSR_STEP_SEL (8) //!< Bit position for CCM_CCSR_STEP_SEL. +#define BM_CCM_CCSR_STEP_SEL (0x00000100) //!< Bit mask for CCM_CCSR_STEP_SEL. + +//! @brief Get value of CCM_CCSR_STEP_SEL from a register value. +#define BG_CCM_CCSR_STEP_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_STEP_SEL) >> BP_CCM_CCSR_STEP_SEL) + +//! @brief Format value for bitfield CCM_CCSR_STEP_SEL. +#define BF_CCM_CCSR_STEP_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_STEP_SEL) & BM_CCM_CCSR_STEP_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STEP_SEL field to a new value. +#define BW_CCM_CCSR_STEP_SEL(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_STEP_SEL) | BF_CCM_CCSR_STEP_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CCSR, field PDF_396M_DIS_MASK[9] (RW) + * + * Mask of 396M PFD auto-disable. + * + * Values: + * - 0 - 396M PFD disable=0 (PFD always on) + * - 1 - 396M PFD disable is managed by associated dividers disable. If all 396M-driven dividers are closed, + * PDF is disabled. + */ +//@{ +#define BP_CCM_CCSR_PDF_396M_DIS_MASK (9) //!< Bit position for CCM_CCSR_PDF_396M_DIS_MASK. +#define BM_CCM_CCSR_PDF_396M_DIS_MASK (0x00000200) //!< Bit mask for CCM_CCSR_PDF_396M_DIS_MASK. + +//! @brief Get value of CCM_CCSR_PDF_396M_DIS_MASK from a register value. +#define BG_CCM_CCSR_PDF_396M_DIS_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_PDF_396M_DIS_MASK) >> BP_CCM_CCSR_PDF_396M_DIS_MASK) + +//! @brief Format value for bitfield CCM_CCSR_PDF_396M_DIS_MASK. +#define BF_CCM_CCSR_PDF_396M_DIS_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_PDF_396M_DIS_MASK) & BM_CCM_CCSR_PDF_396M_DIS_MASK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PDF_396M_DIS_MASK field to a new value. +#define BW_CCM_CCSR_PDF_396M_DIS_MASK(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_PDF_396M_DIS_MASK) | BF_CCM_CCSR_PDF_396M_DIS_MASK(v))) +#endif +//@} + +/*! @name Register CCM_CCSR, field PDF_307M_DIS_MASK[10] (RW) + * + * Mask of 307M PFD auto-disable. + * + * Values: + * - 0 - 307M PFD disable=0 (PFD always on) + * - 1 - 307M PFD disable is managed by associated dividers disable. If all 307M-driven dividers are closed, + * PDF is disabled. + */ +//@{ +#define BP_CCM_CCSR_PDF_307M_DIS_MASK (10) //!< Bit position for CCM_CCSR_PDF_307M_DIS_MASK. +#define BM_CCM_CCSR_PDF_307M_DIS_MASK (0x00000400) //!< Bit mask for CCM_CCSR_PDF_307M_DIS_MASK. + +//! @brief Get value of CCM_CCSR_PDF_307M_DIS_MASK from a register value. +#define BG_CCM_CCSR_PDF_307M_DIS_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_PDF_307M_DIS_MASK) >> BP_CCM_CCSR_PDF_307M_DIS_MASK) + +//! @brief Format value for bitfield CCM_CCSR_PDF_307M_DIS_MASK. +#define BF_CCM_CCSR_PDF_307M_DIS_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_PDF_307M_DIS_MASK) & BM_CCM_CCSR_PDF_307M_DIS_MASK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PDF_307M_DIS_MASK field to a new value. +#define BW_CCM_CCSR_PDF_307M_DIS_MASK(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_PDF_307M_DIS_MASK) | BF_CCM_CCSR_PDF_307M_DIS_MASK(v))) +#endif +//@} + +/*! @name Register CCM_CCSR, field PDF_528M_DIS_MASK[11] (RW) + * + * Mask of 528M PFD auto-disable. + * + * Values: + * - 0 - 528M PFD disable=0 (PFD always on) + * - 1 - 528M PFD disable is managed by associated dividers disable. If all 528M-driven dividers are closed, + * PDF is disabled. + */ +//@{ +#define BP_CCM_CCSR_PDF_528M_DIS_MASK (11) //!< Bit position for CCM_CCSR_PDF_528M_DIS_MASK. +#define BM_CCM_CCSR_PDF_528M_DIS_MASK (0x00000800) //!< Bit mask for CCM_CCSR_PDF_528M_DIS_MASK. + +//! @brief Get value of CCM_CCSR_PDF_528M_DIS_MASK from a register value. +#define BG_CCM_CCSR_PDF_528M_DIS_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_PDF_528M_DIS_MASK) >> BP_CCM_CCSR_PDF_528M_DIS_MASK) + +//! @brief Format value for bitfield CCM_CCSR_PDF_528M_DIS_MASK. +#define BF_CCM_CCSR_PDF_528M_DIS_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_PDF_528M_DIS_MASK) & BM_CCM_CCSR_PDF_528M_DIS_MASK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PDF_528M_DIS_MASK field to a new value. +#define BW_CCM_CCSR_PDF_528M_DIS_MASK(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_PDF_528M_DIS_MASK) | BF_CCM_CCSR_PDF_528M_DIS_MASK(v))) +#endif +//@} + +/*! @name Register CCM_CCSR, field PDF_508M_DIS_MASK[12] (RW) + * + * Mask of 508M PFD auto-disable. + * + * Values: + * - 0 - 508M PFD disable=0 (PFD always on) + * - 1 - 508M PFD disable is managed by associated dividers disable. If all 508M-driven dividers are closed, + * PDF is disabled. + */ +//@{ +#define BP_CCM_CCSR_PDF_508M_DIS_MASK (12) //!< Bit position for CCM_CCSR_PDF_508M_DIS_MASK. +#define BM_CCM_CCSR_PDF_508M_DIS_MASK (0x00001000) //!< Bit mask for CCM_CCSR_PDF_508M_DIS_MASK. + +//! @brief Get value of CCM_CCSR_PDF_508M_DIS_MASK from a register value. +#define BG_CCM_CCSR_PDF_508M_DIS_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_PDF_508M_DIS_MASK) >> BP_CCM_CCSR_PDF_508M_DIS_MASK) + +//! @brief Format value for bitfield CCM_CCSR_PDF_508M_DIS_MASK. +#define BF_CCM_CCSR_PDF_508M_DIS_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_PDF_508M_DIS_MASK) & BM_CCM_CCSR_PDF_508M_DIS_MASK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PDF_508M_DIS_MASK field to a new value. +#define BW_CCM_CCSR_PDF_508M_DIS_MASK(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_PDF_508M_DIS_MASK) | BF_CCM_CCSR_PDF_508M_DIS_MASK(v))) +#endif +//@} + +/*! @name Register CCM_CCSR, field PDF_540M_DIS_MASK[15] (RW) + * + * Mask of 540M PFD auto-disable. + * + * Values: + * - 0 - - 540M PFD disable=0 (PFD always on) + * - 1 - 540M PFD disable is managed by associated dividers disable. If all 540M-driven dividers are closed, + * PDF is disabled. + */ +//@{ +#define BP_CCM_CCSR_PDF_540M_DIS_MASK (15) //!< Bit position for CCM_CCSR_PDF_540M_DIS_MASK. +#define BM_CCM_CCSR_PDF_540M_DIS_MASK (0x00008000) //!< Bit mask for CCM_CCSR_PDF_540M_DIS_MASK. + +//! @brief Get value of CCM_CCSR_PDF_540M_DIS_MASK from a register value. +#define BG_CCM_CCSR_PDF_540M_DIS_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCSR_PDF_540M_DIS_MASK) >> BP_CCM_CCSR_PDF_540M_DIS_MASK) + +//! @brief Format value for bitfield CCM_CCSR_PDF_540M_DIS_MASK. +#define BF_CCM_CCSR_PDF_540M_DIS_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCSR_PDF_540M_DIS_MASK) & BM_CCM_CCSR_PDF_540M_DIS_MASK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PDF_540M_DIS_MASK field to a new value. +#define BW_CCM_CCSR_PDF_540M_DIS_MASK(v) (HW_CCM_CCSR_WR((HW_CCM_CCSR_RD() & ~BM_CCM_CCSR_PDF_540M_DIS_MASK) | BF_CCM_CCSR_PDF_540M_DIS_MASK(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CACRR - CCM Arm Clock Root Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CACRR - CCM Arm Clock Root Register (RW) + * + * Reset value: 0x00000000 + * + * The figure below represents the CCM Arm Clock Root register (CACRR). The CACRR register contains + * bits to control the ARM clock root generation. The table below provides its field descriptions. + */ +typedef union _hw_ccm_cacrr +{ + reg32_t U; + struct _hw_ccm_cacrr_bitfields + { + unsigned ARM_PODF : 3; //!< [2:0] Divider for ARM clock root. + unsigned RESERVED0 : 29; //!< [31:3] Reserved + } B; +} hw_ccm_cacrr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CACRR register + */ +//@{ +#define HW_CCM_CACRR_ADDR (REGS_CCM_BASE + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CACRR (*(volatile hw_ccm_cacrr_t *) HW_CCM_CACRR_ADDR) +#define HW_CCM_CACRR_RD() (HW_CCM_CACRR.U) +#define HW_CCM_CACRR_WR(v) (HW_CCM_CACRR.U = (v)) +#define HW_CCM_CACRR_SET(v) (HW_CCM_CACRR_WR(HW_CCM_CACRR_RD() | (v))) +#define HW_CCM_CACRR_CLR(v) (HW_CCM_CACRR_WR(HW_CCM_CACRR_RD() & ~(v))) +#define HW_CCM_CACRR_TOG(v) (HW_CCM_CACRR_WR(HW_CCM_CACRR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CACRR bitfields + */ + +/*! @name Register CCM_CACRR, field ARM_PODF[2:0] (RW) + * + * Divider for ARM clock root. Note: if arm_freq_shift_divider is set to '1' then any new write to + * arm_podf will be held until arm_clk_switch_req signal is asserted. + * + * Values: + * - 000 - divide by 1(default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CACRR_ARM_PODF (0) //!< Bit position for CCM_CACRR_ARM_PODF. +#define BM_CCM_CACRR_ARM_PODF (0x00000007) //!< Bit mask for CCM_CACRR_ARM_PODF. + +//! @brief Get value of CCM_CACRR_ARM_PODF from a register value. +#define BG_CCM_CACRR_ARM_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CACRR_ARM_PODF) >> BP_CCM_CACRR_ARM_PODF) + +//! @brief Format value for bitfield CCM_CACRR_ARM_PODF. +#define BF_CCM_CACRR_ARM_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CACRR_ARM_PODF) & BM_CCM_CACRR_ARM_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ARM_PODF field to a new value. +#define BW_CCM_CACRR_ARM_PODF(v) (HW_CCM_CACRR_WR((HW_CCM_CACRR_RD() & ~BM_CCM_CACRR_ARM_PODF) | BF_CCM_CACRR_ARM_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CBCDR - CCM Bus Clock Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CBCDR - CCM Bus Clock Divider Register (RW) + * + * Reset value: 0x00018d40 + * + * The figure below represents the CCM Bus Clock Divider Register (CBCDR). The CBCDR register + * contains bits to control the clock generation sub module dividers. The table below provides its + * field descriptions. + */ +typedef union _hw_ccm_cbcdr +{ + reg32_t U; + struct _hw_ccm_cbcdr_bitfields + { + unsigned PERIPH2_CLK2_PODF : 3; //!< [2:0] Divider for periph2_clk2 podf. + unsigned MMDC_CH1_AXI_PODF : 3; //!< [5:3] Divider for mmdc_ch1_axi podf. + unsigned AXI_SEL : 1; //!< [6] AXI clock source select + unsigned AXI_ALT_SEL : 1; //!< [7] AXI alternative clock select + unsigned IPG_PODF : 2; //!< [9:8] Divider for ipg podf. + unsigned AHB_PODF : 3; //!< [12:10] Divider for ahb podf. + unsigned RESERVED0 : 3; //!< [15:13] Reserved + unsigned AXI_PODF : 3; //!< [18:16] Divider for axi podf. + unsigned MMDC_CH0_AXI_PODF : 3; //!< [21:19] Divider for mmdc_ch0_axi podf. + unsigned RESERVED1 : 3; //!< [24:22] Reserved + unsigned PERIPH_CLK_SEL : 1; //!< [25] Selector for peripheral main clock (source of mmdc_ch0_axi_clk_root). + unsigned PERIPH2_CLK_SEL : 1; //!< [26] Selector for peripheral2 main clock (source of mmdc_ch1_axi_clk_root ). + unsigned PERIPH_CLK2_PODF : 3; //!< [29:27] Divider for periph2 clock podf. + unsigned RESERVED2 : 2; //!< [31:30] Reserved + } B; +} hw_ccm_cbcdr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CBCDR register + */ +//@{ +#define HW_CCM_CBCDR_ADDR (REGS_CCM_BASE + 0x14) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CBCDR (*(volatile hw_ccm_cbcdr_t *) HW_CCM_CBCDR_ADDR) +#define HW_CCM_CBCDR_RD() (HW_CCM_CBCDR.U) +#define HW_CCM_CBCDR_WR(v) (HW_CCM_CBCDR.U = (v)) +#define HW_CCM_CBCDR_SET(v) (HW_CCM_CBCDR_WR(HW_CCM_CBCDR_RD() | (v))) +#define HW_CCM_CBCDR_CLR(v) (HW_CCM_CBCDR_WR(HW_CCM_CBCDR_RD() & ~(v))) +#define HW_CCM_CBCDR_TOG(v) (HW_CCM_CBCDR_WR(HW_CCM_CBCDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CBCDR bitfields + */ + +/*! @name Register CCM_CBCDR, field PERIPH2_CLK2_PODF[2:0] (RW) + * + * Divider for periph2_clk2 podf. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 (default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCDR_PERIPH2_CLK2_PODF (0) //!< Bit position for CCM_CBCDR_PERIPH2_CLK2_PODF. +#define BM_CCM_CBCDR_PERIPH2_CLK2_PODF (0x00000007) //!< Bit mask for CCM_CBCDR_PERIPH2_CLK2_PODF. + +//! @brief Get value of CCM_CBCDR_PERIPH2_CLK2_PODF from a register value. +#define BG_CCM_CBCDR_PERIPH2_CLK2_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_PERIPH2_CLK2_PODF) >> BP_CCM_CBCDR_PERIPH2_CLK2_PODF) + +//! @brief Format value for bitfield CCM_CBCDR_PERIPH2_CLK2_PODF. +#define BF_CCM_CBCDR_PERIPH2_CLK2_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_PERIPH2_CLK2_PODF) & BM_CCM_CBCDR_PERIPH2_CLK2_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIPH2_CLK2_PODF field to a new value. +#define BW_CCM_CBCDR_PERIPH2_CLK2_PODF(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_PERIPH2_CLK2_PODF) | BF_CCM_CBCDR_PERIPH2_CLK2_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field MMDC_CH1_AXI_PODF[5:3] (RW) + * + * Divider for mmdc_ch1_axi podf. Note: This design implementation does not use + * MMDC_CH1_AXI_CLK_ROOT as a clock source to the MMDC. Only MMDC_CH0_AXI_CLK_ROOT is used. + * + * Values: + * - 000 - divide by 1 (default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCDR_MMDC_CH1_AXI_PODF (3) //!< Bit position for CCM_CBCDR_MMDC_CH1_AXI_PODF. +#define BM_CCM_CBCDR_MMDC_CH1_AXI_PODF (0x00000038) //!< Bit mask for CCM_CBCDR_MMDC_CH1_AXI_PODF. + +//! @brief Get value of CCM_CBCDR_MMDC_CH1_AXI_PODF from a register value. +#define BG_CCM_CBCDR_MMDC_CH1_AXI_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_MMDC_CH1_AXI_PODF) >> BP_CCM_CBCDR_MMDC_CH1_AXI_PODF) + +//! @brief Format value for bitfield CCM_CBCDR_MMDC_CH1_AXI_PODF. +#define BF_CCM_CBCDR_MMDC_CH1_AXI_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_MMDC_CH1_AXI_PODF) & BM_CCM_CBCDR_MMDC_CH1_AXI_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MMDC_CH1_AXI_PODF field to a new value. +#define BW_CCM_CBCDR_MMDC_CH1_AXI_PODF(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_MMDC_CH1_AXI_PODF) | BF_CCM_CBCDR_MMDC_CH1_AXI_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field AXI_SEL[6] (RW) + * + * AXI clock source select + * + * Values: + * - 0 - Periph_clk output will be used as AXI clock root + * - 1 - AXI alternative clock will be used as AXI clock root + */ +//@{ +#define BP_CCM_CBCDR_AXI_SEL (6) //!< Bit position for CCM_CBCDR_AXI_SEL. +#define BM_CCM_CBCDR_AXI_SEL (0x00000040) //!< Bit mask for CCM_CBCDR_AXI_SEL. + +//! @brief Get value of CCM_CBCDR_AXI_SEL from a register value. +#define BG_CCM_CBCDR_AXI_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_AXI_SEL) >> BP_CCM_CBCDR_AXI_SEL) + +//! @brief Format value for bitfield CCM_CBCDR_AXI_SEL. +#define BF_CCM_CBCDR_AXI_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_AXI_SEL) & BM_CCM_CBCDR_AXI_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AXI_SEL field to a new value. +#define BW_CCM_CBCDR_AXI_SEL(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_AXI_SEL) | BF_CCM_CBCDR_AXI_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field AXI_ALT_SEL[7] (RW) + * + * AXI alternative clock select + * + * Values: + * - 0 - pll2 396MHz PFD will be selected as alternative clock for AXI root clock + * - 1 - pll3 540MHz PFD will be selected as alternative clock for AXI root clock + */ +//@{ +#define BP_CCM_CBCDR_AXI_ALT_SEL (7) //!< Bit position for CCM_CBCDR_AXI_ALT_SEL. +#define BM_CCM_CBCDR_AXI_ALT_SEL (0x00000080) //!< Bit mask for CCM_CBCDR_AXI_ALT_SEL. + +//! @brief Get value of CCM_CBCDR_AXI_ALT_SEL from a register value. +#define BG_CCM_CBCDR_AXI_ALT_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_AXI_ALT_SEL) >> BP_CCM_CBCDR_AXI_ALT_SEL) + +//! @brief Format value for bitfield CCM_CBCDR_AXI_ALT_SEL. +#define BF_CCM_CBCDR_AXI_ALT_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_AXI_ALT_SEL) & BM_CCM_CBCDR_AXI_ALT_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AXI_ALT_SEL field to a new value. +#define BW_CCM_CBCDR_AXI_ALT_SEL(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_AXI_ALT_SEL) | BF_CCM_CBCDR_AXI_ALT_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field IPG_PODF[9:8] (RW) + * + * Divider for ipg podf. Note: IEEE_RTC module will not support ratio of 1:3 for ahb_clk:ipg_clk. In + * case IEEE_RTC is used, then those ratios should not be used. Note: SDMA module will not support + * ratio of 1:3 and 1:4 for ahb_clk:ipg_clk. In case SDMA is used, then those ratios should not be + * used. + * + * Values: + * - 00 - divide by 1 + * - 01 - divide by 2 (default) + * - 10 - divide by 3 + * - 11 - divide by 4 + */ +//@{ +#define BP_CCM_CBCDR_IPG_PODF (8) //!< Bit position for CCM_CBCDR_IPG_PODF. +#define BM_CCM_CBCDR_IPG_PODF (0x00000300) //!< Bit mask for CCM_CBCDR_IPG_PODF. + +//! @brief Get value of CCM_CBCDR_IPG_PODF from a register value. +#define BG_CCM_CBCDR_IPG_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_IPG_PODF) >> BP_CCM_CBCDR_IPG_PODF) + +//! @brief Format value for bitfield CCM_CBCDR_IPG_PODF. +#define BF_CCM_CBCDR_IPG_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_IPG_PODF) & BM_CCM_CBCDR_IPG_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPG_PODF field to a new value. +#define BW_CCM_CBCDR_IPG_PODF(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_IPG_PODF) | BF_CCM_CBCDR_IPG_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field AHB_PODF[12:10] (RW) + * + * Divider for ahb podf. Note: any change of this divider might involve handshake with EMI and IPU. + * See CDHIPR register for the handshake busy bits. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 (default) + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCDR_AHB_PODF (10) //!< Bit position for CCM_CBCDR_AHB_PODF. +#define BM_CCM_CBCDR_AHB_PODF (0x00001c00) //!< Bit mask for CCM_CBCDR_AHB_PODF. + +//! @brief Get value of CCM_CBCDR_AHB_PODF from a register value. +#define BG_CCM_CBCDR_AHB_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_AHB_PODF) >> BP_CCM_CBCDR_AHB_PODF) + +//! @brief Format value for bitfield CCM_CBCDR_AHB_PODF. +#define BF_CCM_CBCDR_AHB_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_AHB_PODF) & BM_CCM_CBCDR_AHB_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AHB_PODF field to a new value. +#define BW_CCM_CBCDR_AHB_PODF(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_AHB_PODF) | BF_CCM_CBCDR_AHB_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field AXI_PODF[18:16] (RW) + * + * Divider for axi podf. Note: any change of this divider might involve handshake with EMI and IPU. + * See CDHIPR register for the handshake busy bits. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCDR_AXI_PODF (16) //!< Bit position for CCM_CBCDR_AXI_PODF. +#define BM_CCM_CBCDR_AXI_PODF (0x00070000) //!< Bit mask for CCM_CBCDR_AXI_PODF. + +//! @brief Get value of CCM_CBCDR_AXI_PODF from a register value. +#define BG_CCM_CBCDR_AXI_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_AXI_PODF) >> BP_CCM_CBCDR_AXI_PODF) + +//! @brief Format value for bitfield CCM_CBCDR_AXI_PODF. +#define BF_CCM_CBCDR_AXI_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_AXI_PODF) & BM_CCM_CBCDR_AXI_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AXI_PODF field to a new value. +#define BW_CCM_CBCDR_AXI_PODF(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_AXI_PODF) | BF_CCM_CBCDR_AXI_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field MMDC_CH0_AXI_PODF[21:19] (RW) + * + * Divider for mmdc_ch0_axi podf. + * + * Values: + * - 000 - divide by 1 (default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCDR_MMDC_CH0_AXI_PODF (19) //!< Bit position for CCM_CBCDR_MMDC_CH0_AXI_PODF. +#define BM_CCM_CBCDR_MMDC_CH0_AXI_PODF (0x00380000) //!< Bit mask for CCM_CBCDR_MMDC_CH0_AXI_PODF. + +//! @brief Get value of CCM_CBCDR_MMDC_CH0_AXI_PODF from a register value. +#define BG_CCM_CBCDR_MMDC_CH0_AXI_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_MMDC_CH0_AXI_PODF) >> BP_CCM_CBCDR_MMDC_CH0_AXI_PODF) + +//! @brief Format value for bitfield CCM_CBCDR_MMDC_CH0_AXI_PODF. +#define BF_CCM_CBCDR_MMDC_CH0_AXI_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_MMDC_CH0_AXI_PODF) & BM_CCM_CBCDR_MMDC_CH0_AXI_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MMDC_CH0_AXI_PODF field to a new value. +#define BW_CCM_CBCDR_MMDC_CH0_AXI_PODF(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_MMDC_CH0_AXI_PODF) | BF_CCM_CBCDR_MMDC_CH0_AXI_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field PERIPH_CLK_SEL[25] (RW) + * + * Selector for peripheral main clock (source of mmdc_ch0_axi_clk_root). Note: alternative clock + * source should be used when PLL is relocked. For PLL relock procedure pls refer PLL chapter + * + * Values: + * - 0 - derive clock from pll2_sw_clk muxed clock source. + * - 1 - derive clock from periph_clk2_clk clock source. + */ +//@{ +#define BP_CCM_CBCDR_PERIPH_CLK_SEL (25) //!< Bit position for CCM_CBCDR_PERIPH_CLK_SEL. +#define BM_CCM_CBCDR_PERIPH_CLK_SEL (0x02000000) //!< Bit mask for CCM_CBCDR_PERIPH_CLK_SEL. + +//! @brief Get value of CCM_CBCDR_PERIPH_CLK_SEL from a register value. +#define BG_CCM_CBCDR_PERIPH_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_PERIPH_CLK_SEL) >> BP_CCM_CBCDR_PERIPH_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCDR_PERIPH_CLK_SEL. +#define BF_CCM_CBCDR_PERIPH_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_PERIPH_CLK_SEL) & BM_CCM_CBCDR_PERIPH_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIPH_CLK_SEL field to a new value. +#define BW_CCM_CBCDR_PERIPH_CLK_SEL(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_PERIPH_CLK_SEL) | BF_CCM_CBCDR_PERIPH_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field PERIPH2_CLK_SEL[26] (RW) + * + * Selector for peripheral2 main clock (source of mmdc_ch1_axi_clk_root ). + * + * Values: + * - 0 - derive clock from pll2_sw_clk muxed clock source. + * - 1 - derive clock from periph_clk2_clk clock source. + */ +//@{ +#define BP_CCM_CBCDR_PERIPH2_CLK_SEL (26) //!< Bit position for CCM_CBCDR_PERIPH2_CLK_SEL. +#define BM_CCM_CBCDR_PERIPH2_CLK_SEL (0x04000000) //!< Bit mask for CCM_CBCDR_PERIPH2_CLK_SEL. + +//! @brief Get value of CCM_CBCDR_PERIPH2_CLK_SEL from a register value. +#define BG_CCM_CBCDR_PERIPH2_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_PERIPH2_CLK_SEL) >> BP_CCM_CBCDR_PERIPH2_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCDR_PERIPH2_CLK_SEL. +#define BF_CCM_CBCDR_PERIPH2_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_PERIPH2_CLK_SEL) & BM_CCM_CBCDR_PERIPH2_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIPH2_CLK_SEL field to a new value. +#define BW_CCM_CBCDR_PERIPH2_CLK_SEL(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_PERIPH2_CLK_SEL) | BF_CCM_CBCDR_PERIPH2_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCDR, field PERIPH_CLK2_PODF[29:27] (RW) + * + * Divider for periph2 clock podf. + * + * Values: + * - 000 - divide by 1 (default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCDR_PERIPH_CLK2_PODF (27) //!< Bit position for CCM_CBCDR_PERIPH_CLK2_PODF. +#define BM_CCM_CBCDR_PERIPH_CLK2_PODF (0x38000000) //!< Bit mask for CCM_CBCDR_PERIPH_CLK2_PODF. + +//! @brief Get value of CCM_CBCDR_PERIPH_CLK2_PODF from a register value. +#define BG_CCM_CBCDR_PERIPH_CLK2_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCDR_PERIPH_CLK2_PODF) >> BP_CCM_CBCDR_PERIPH_CLK2_PODF) + +//! @brief Format value for bitfield CCM_CBCDR_PERIPH_CLK2_PODF. +#define BF_CCM_CBCDR_PERIPH_CLK2_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCDR_PERIPH_CLK2_PODF) & BM_CCM_CBCDR_PERIPH_CLK2_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIPH_CLK2_PODF field to a new value. +#define BW_CCM_CBCDR_PERIPH_CLK2_PODF(v) (HW_CCM_CBCDR_WR((HW_CCM_CBCDR_RD() & ~BM_CCM_CBCDR_PERIPH_CLK2_PODF) | BF_CCM_CBCDR_PERIPH_CLK2_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CBCMR - CCM Bus Clock Multiplexer Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CBCMR - CCM Bus Clock Multiplexer Register (RW) + * + * Reset value: 0x00820224 + * + * The figure below represents the CCM Bus Clock Multiplexer Register (CBCMR). The CBCMR register + * contains bits to control the multiplexers that generate the bus clocks. The table below provides + * its field descriptions. Note: Any change on the above multiplexer will have to be done while the + * module that its clock is affected is not functional and the respective clock is gated in LPCG. If + * the change will be done during operation of the module, then it is not guaranteed that the + * modules operation will not be harmed. The change for arm_axi_clk_sel should be done through sdma + * so that ARM will not use this clock during the change and the clock will be gated in LPCG. + */ +typedef union _hw_ccm_cbcmr +{ + reg32_t U; + struct _hw_ccm_cbcmr_bitfields + { + unsigned RESERVED1 : 4; //!< [3:0] Reserved. + unsigned GPU3D_CORE_CLK_SEL : 2; //!< [5:4] Selector for gpu3d_core clock multiplexer + unsigned RESERVED2 : 2; //!< [7:6] Reserved + unsigned GPU2D_CORE_SEL : 2; //!< [9:8] Selector for gpu2d_core clock multiplexer + unsigned PCIE_AXI_CLK_SEL : 1; //!< [10] Selector for pcie_axi clock multiplexer + unsigned VDOAXI_CLK_SEL : 1; //!< [11] Selector for vdoaxi clock multiplexer + unsigned PERIPH_CLK2_SEL : 2; //!< [13:12] Selector for peripheral clk2 clock multiplexer + unsigned VPU_AXI_CLK_SEL : 2; //!< [15:14] Selector for VPU axi clock multiplexer + unsigned GPU2D_CLK_SEL : 2; //!< [17:16] Selector for open vg clock multiplexer + unsigned PRE_PERIPH_CLK_SEL : 2; //!< [19:18] Selector for pre_periph clock multiplexer + unsigned PERIPH2_CLK2_SEL : 1; //!< [20] Selector for periph2_clk2 clock multiplexer + unsigned PRE_PERIPH2_CLK_SEL : 2; //!< [22:21] Selector for pre_periph2 clock multiplexer + unsigned MLB_SYS_CLK_PODF : 3; //!< [25:23] Divider for mlb_sys clock. + unsigned GPU3D_CORE_PODF : 3; //!< [28:26] Divider for gpu3d_core_podf. + unsigned GPU2D_CORE_PODF : 3; //!< [31:29] Divider for gpu2d_core clock. + } B; +} hw_ccm_cbcmr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CBCMR register + */ +//@{ +#define HW_CCM_CBCMR_ADDR (REGS_CCM_BASE + 0x18) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CBCMR (*(volatile hw_ccm_cbcmr_t *) HW_CCM_CBCMR_ADDR) +#define HW_CCM_CBCMR_RD() (HW_CCM_CBCMR.U) +#define HW_CCM_CBCMR_WR(v) (HW_CCM_CBCMR.U = (v)) +#define HW_CCM_CBCMR_SET(v) (HW_CCM_CBCMR_WR(HW_CCM_CBCMR_RD() | (v))) +#define HW_CCM_CBCMR_CLR(v) (HW_CCM_CBCMR_WR(HW_CCM_CBCMR_RD() & ~(v))) +#define HW_CCM_CBCMR_TOG(v) (HW_CCM_CBCMR_WR(HW_CCM_CBCMR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CBCMR bitfields + */ + +/*! @name Register CCM_CBCMR, field GPU3D_CORE_CLK_SEL[5:4] (RW) + * + * Selector for gpu3d_core clock multiplexer + * + * Values: + * - 00 - derive clock from mmdc_ch0 + * - 01 - derive clock from pll3 + * - 10 - derive clock from 528M PFD (default) + * - 11 - derive clock from 396M PFD + */ +//@{ +#define BP_CCM_CBCMR_GPU3D_CORE_CLK_SEL (4) //!< Bit position for CCM_CBCMR_GPU3D_CORE_CLK_SEL. +#define BM_CCM_CBCMR_GPU3D_CORE_CLK_SEL (0x00000030) //!< Bit mask for CCM_CBCMR_GPU3D_CORE_CLK_SEL. + +//! @brief Get value of CCM_CBCMR_GPU3D_CORE_CLK_SEL from a register value. +#define BG_CCM_CBCMR_GPU3D_CORE_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_GPU3D_CORE_CLK_SEL) >> BP_CCM_CBCMR_GPU3D_CORE_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_GPU3D_CORE_CLK_SEL. +#define BF_CCM_CBCMR_GPU3D_CORE_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_GPU3D_CORE_CLK_SEL) & BM_CCM_CBCMR_GPU3D_CORE_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GPU3D_CORE_CLK_SEL field to a new value. +#define BW_CCM_CBCMR_GPU3D_CORE_CLK_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_GPU3D_CORE_CLK_SEL) | BF_CCM_CBCMR_GPU3D_CORE_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field GPU2D_CORE_SEL[9:8] (RW) + * + * Selector for gpu2d_core clock multiplexer + * + * Values: + * - 00 - derive clock from mmdc_ch0 clk + * - 01 - derive clock from pll3 + * - 10 - derive clock from 528M PFD (default) + * - 11 - derive clock from Reserved PFD + */ +//@{ +#define BP_CCM_CBCMR_GPU2D_CORE_SEL (8) //!< Bit position for CCM_CBCMR_GPU2D_CORE_SEL. +#define BM_CCM_CBCMR_GPU2D_CORE_SEL (0x00000300) //!< Bit mask for CCM_CBCMR_GPU2D_CORE_SEL. + +//! @brief Get value of CCM_CBCMR_GPU2D_CORE_SEL from a register value. +#define BG_CCM_CBCMR_GPU2D_CORE_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_GPU2D_CORE_SEL) >> BP_CCM_CBCMR_GPU2D_CORE_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_GPU2D_CORE_SEL. +#define BF_CCM_CBCMR_GPU2D_CORE_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_GPU2D_CORE_SEL) & BM_CCM_CBCMR_GPU2D_CORE_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GPU2D_CORE_SEL field to a new value. +#define BW_CCM_CBCMR_GPU2D_CORE_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_GPU2D_CORE_SEL) | BF_CCM_CBCMR_GPU2D_CORE_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field PCIE_AXI_CLK_SEL[10] (RW) + * + * Selector for pcie_axi clock multiplexer + * + * Values: + * - 0 - derive clock from axi clk (default) + * - 1 - derive clock from system_133M clk + */ +//@{ +#define BP_CCM_CBCMR_PCIE_AXI_CLK_SEL (10) //!< Bit position for CCM_CBCMR_PCIE_AXI_CLK_SEL. +#define BM_CCM_CBCMR_PCIE_AXI_CLK_SEL (0x00000400) //!< Bit mask for CCM_CBCMR_PCIE_AXI_CLK_SEL. + +//! @brief Get value of CCM_CBCMR_PCIE_AXI_CLK_SEL from a register value. +#define BG_CCM_CBCMR_PCIE_AXI_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_PCIE_AXI_CLK_SEL) >> BP_CCM_CBCMR_PCIE_AXI_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_PCIE_AXI_CLK_SEL. +#define BF_CCM_CBCMR_PCIE_AXI_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_PCIE_AXI_CLK_SEL) & BM_CCM_CBCMR_PCIE_AXI_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PCIE_AXI_CLK_SEL field to a new value. +#define BW_CCM_CBCMR_PCIE_AXI_CLK_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_PCIE_AXI_CLK_SEL) | BF_CCM_CBCMR_PCIE_AXI_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field VDOAXI_CLK_SEL[11] (RW) + * + * Selector for vdoaxi clock multiplexer + * + * Values: + * - 0 - derive clock from axi clk (default) + * - 1 - derive clock from 132M clock + */ +//@{ +#define BP_CCM_CBCMR_VDOAXI_CLK_SEL (11) //!< Bit position for CCM_CBCMR_VDOAXI_CLK_SEL. +#define BM_CCM_CBCMR_VDOAXI_CLK_SEL (0x00000800) //!< Bit mask for CCM_CBCMR_VDOAXI_CLK_SEL. + +//! @brief Get value of CCM_CBCMR_VDOAXI_CLK_SEL from a register value. +#define BG_CCM_CBCMR_VDOAXI_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_VDOAXI_CLK_SEL) >> BP_CCM_CBCMR_VDOAXI_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_VDOAXI_CLK_SEL. +#define BF_CCM_CBCMR_VDOAXI_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_VDOAXI_CLK_SEL) & BM_CCM_CBCMR_VDOAXI_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VDOAXI_CLK_SEL field to a new value. +#define BW_CCM_CBCMR_VDOAXI_CLK_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_VDOAXI_CLK_SEL) | BF_CCM_CBCMR_VDOAXI_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field PERIPH_CLK2_SEL[13:12] (RW) + * + * Selector for peripheral clk2 clock multiplexer + * + * Values: + * - 00 - derive clock from pll3_sw_clk + * - 01 - derive clock from pll1_ref_clk + * - 10 - derive clock from pll2_burn_in_clk (default) + * - 11 - reserved + */ +//@{ +#define BP_CCM_CBCMR_PERIPH_CLK2_SEL (12) //!< Bit position for CCM_CBCMR_PERIPH_CLK2_SEL. +#define BM_CCM_CBCMR_PERIPH_CLK2_SEL (0x00003000) //!< Bit mask for CCM_CBCMR_PERIPH_CLK2_SEL. + +//! @brief Get value of CCM_CBCMR_PERIPH_CLK2_SEL from a register value. +#define BG_CCM_CBCMR_PERIPH_CLK2_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_PERIPH_CLK2_SEL) >> BP_CCM_CBCMR_PERIPH_CLK2_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_PERIPH_CLK2_SEL. +#define BF_CCM_CBCMR_PERIPH_CLK2_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_PERIPH_CLK2_SEL) & BM_CCM_CBCMR_PERIPH_CLK2_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIPH_CLK2_SEL field to a new value. +#define BW_CCM_CBCMR_PERIPH_CLK2_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_PERIPH_CLK2_SEL) | BF_CCM_CBCMR_PERIPH_CLK2_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field VPU_AXI_CLK_SEL[15:14] (RW) + * + * Selector for VPU axi clock multiplexer + * + * Values: + * - 00 - derive clock from AXI (default) + * - 01 - derive clock from 396M PFD + * - 10 - derive clock from 307M PFD (default) + * - 11 - Restricted + */ +//@{ +#define BP_CCM_CBCMR_VPU_AXI_CLK_SEL (14) //!< Bit position for CCM_CBCMR_VPU_AXI_CLK_SEL. +#define BM_CCM_CBCMR_VPU_AXI_CLK_SEL (0x0000c000) //!< Bit mask for CCM_CBCMR_VPU_AXI_CLK_SEL. + +//! @brief Get value of CCM_CBCMR_VPU_AXI_CLK_SEL from a register value. +#define BG_CCM_CBCMR_VPU_AXI_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_VPU_AXI_CLK_SEL) >> BP_CCM_CBCMR_VPU_AXI_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_VPU_AXI_CLK_SEL. +#define BF_CCM_CBCMR_VPU_AXI_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_VPU_AXI_CLK_SEL) & BM_CCM_CBCMR_VPU_AXI_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VPU_AXI_CLK_SEL field to a new value. +#define BW_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_VPU_AXI_CLK_SEL) | BF_CCM_CBCMR_VPU_AXI_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field GPU2D_CLK_SEL[17:16] (RW) + * + * Selector for open vg clock multiplexer + * + * Values: + * - 00 - derive clock from axi + * - 01 - derive clock from pll3 + * - 10 - 307M PFD + * - 11 - derive clock from 396M PFD + */ +//@{ +#define BP_CCM_CBCMR_GPU2D_CLK_SEL (16) //!< Bit position for CCM_CBCMR_GPU2D_CLK_SEL. +#define BM_CCM_CBCMR_GPU2D_CLK_SEL (0x00030000) //!< Bit mask for CCM_CBCMR_GPU2D_CLK_SEL. + +//! @brief Get value of CCM_CBCMR_GPU2D_CLK_SEL from a register value. +#define BG_CCM_CBCMR_GPU2D_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_GPU2D_CLK_SEL) >> BP_CCM_CBCMR_GPU2D_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_GPU2D_CLK_SEL. +#define BF_CCM_CBCMR_GPU2D_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_GPU2D_CLK_SEL) & BM_CCM_CBCMR_GPU2D_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GPU2D_CLK_SEL field to a new value. +#define BW_CCM_CBCMR_GPU2D_CLK_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_GPU2D_CLK_SEL) | BF_CCM_CBCMR_GPU2D_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field PRE_PERIPH_CLK_SEL[19:18] (RW) + * + * Selector for pre_periph clock multiplexer + * + * Values: + * - 00 - derive clock from PLL2 main 528MHz clock + * - 01 - derive clock from 396MHz PLL2 PFD (default) + * - 10 - derive clock from 307M PFD + * - 11 - derive clock from 198MHz clock (divided 396MHz PLL2 PFD) + */ +//@{ +#define BP_CCM_CBCMR_PRE_PERIPH_CLK_SEL (18) //!< Bit position for CCM_CBCMR_PRE_PERIPH_CLK_SEL. +#define BM_CCM_CBCMR_PRE_PERIPH_CLK_SEL (0x000c0000) //!< Bit mask for CCM_CBCMR_PRE_PERIPH_CLK_SEL. + +//! @brief Get value of CCM_CBCMR_PRE_PERIPH_CLK_SEL from a register value. +#define BG_CCM_CBCMR_PRE_PERIPH_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_PRE_PERIPH_CLK_SEL) >> BP_CCM_CBCMR_PRE_PERIPH_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_PRE_PERIPH_CLK_SEL. +#define BF_CCM_CBCMR_PRE_PERIPH_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_PRE_PERIPH_CLK_SEL) & BM_CCM_CBCMR_PRE_PERIPH_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PRE_PERIPH_CLK_SEL field to a new value. +#define BW_CCM_CBCMR_PRE_PERIPH_CLK_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_PRE_PERIPH_CLK_SEL) | BF_CCM_CBCMR_PRE_PERIPH_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field PERIPH2_CLK2_SEL[20] (RW) + * + * Selector for periph2_clk2 clock multiplexer + * + * Values: + * - 0 - derive clock from pll3_sw_clk + * - 1 - derive clock from PLL2 Main + */ +//@{ +#define BP_CCM_CBCMR_PERIPH2_CLK2_SEL (20) //!< Bit position for CCM_CBCMR_PERIPH2_CLK2_SEL. +#define BM_CCM_CBCMR_PERIPH2_CLK2_SEL (0x00100000) //!< Bit mask for CCM_CBCMR_PERIPH2_CLK2_SEL. + +//! @brief Get value of CCM_CBCMR_PERIPH2_CLK2_SEL from a register value. +#define BG_CCM_CBCMR_PERIPH2_CLK2_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_PERIPH2_CLK2_SEL) >> BP_CCM_CBCMR_PERIPH2_CLK2_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_PERIPH2_CLK2_SEL. +#define BF_CCM_CBCMR_PERIPH2_CLK2_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_PERIPH2_CLK2_SEL) & BM_CCM_CBCMR_PERIPH2_CLK2_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIPH2_CLK2_SEL field to a new value. +#define BW_CCM_CBCMR_PERIPH2_CLK2_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_PERIPH2_CLK2_SEL) | BF_CCM_CBCMR_PERIPH2_CLK2_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field PRE_PERIPH2_CLK_SEL[22:21] (RW) + * + * Selector for pre_periph2 clock multiplexer + * + * Values: + * - 00 - derive clock from PLL2 main 528MHz clock + * - 01 - derive clock from 396MHz PLL2 PFD (default) + * - 10 - derive clock from 307M PFD + * - 11 - derive clock from 198MHz clock (divided 396MHz PLL2 PFD) + */ +//@{ +#define BP_CCM_CBCMR_PRE_PERIPH2_CLK_SEL (21) //!< Bit position for CCM_CBCMR_PRE_PERIPH2_CLK_SEL. +#define BM_CCM_CBCMR_PRE_PERIPH2_CLK_SEL (0x00600000) //!< Bit mask for CCM_CBCMR_PRE_PERIPH2_CLK_SEL. + +//! @brief Get value of CCM_CBCMR_PRE_PERIPH2_CLK_SEL from a register value. +#define BG_CCM_CBCMR_PRE_PERIPH2_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_PRE_PERIPH2_CLK_SEL) >> BP_CCM_CBCMR_PRE_PERIPH2_CLK_SEL) + +//! @brief Format value for bitfield CCM_CBCMR_PRE_PERIPH2_CLK_SEL. +#define BF_CCM_CBCMR_PRE_PERIPH2_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_PRE_PERIPH2_CLK_SEL) & BM_CCM_CBCMR_PRE_PERIPH2_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PRE_PERIPH2_CLK_SEL field to a new value. +#define BW_CCM_CBCMR_PRE_PERIPH2_CLK_SEL(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_PRE_PERIPH2_CLK_SEL) | BF_CCM_CBCMR_PRE_PERIPH2_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field MLB_SYS_CLK_PODF[25:23] (RW) + * + * Divider for mlb_sys clock. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCMR_MLB_SYS_CLK_PODF (23) //!< Bit position for CCM_CBCMR_MLB_SYS_CLK_PODF. +#define BM_CCM_CBCMR_MLB_SYS_CLK_PODF (0x03800000) //!< Bit mask for CCM_CBCMR_MLB_SYS_CLK_PODF. + +//! @brief Get value of CCM_CBCMR_MLB_SYS_CLK_PODF from a register value. +#define BG_CCM_CBCMR_MLB_SYS_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_MLB_SYS_CLK_PODF) >> BP_CCM_CBCMR_MLB_SYS_CLK_PODF) + +//! @brief Format value for bitfield CCM_CBCMR_MLB_SYS_CLK_PODF. +#define BF_CCM_CBCMR_MLB_SYS_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_MLB_SYS_CLK_PODF) & BM_CCM_CBCMR_MLB_SYS_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MLB_SYS_CLK_PODF field to a new value. +#define BW_CCM_CBCMR_MLB_SYS_CLK_PODF(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_MLB_SYS_CLK_PODF) | BF_CCM_CBCMR_MLB_SYS_CLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field GPU3D_CORE_PODF[28:26] (RW) + * + * Divider for gpu3d_core_podf. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCMR_GPU3D_CORE_PODF (26) //!< Bit position for CCM_CBCMR_GPU3D_CORE_PODF. +#define BM_CCM_CBCMR_GPU3D_CORE_PODF (0x1c000000) //!< Bit mask for CCM_CBCMR_GPU3D_CORE_PODF. + +//! @brief Get value of CCM_CBCMR_GPU3D_CORE_PODF from a register value. +#define BG_CCM_CBCMR_GPU3D_CORE_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_GPU3D_CORE_PODF) >> BP_CCM_CBCMR_GPU3D_CORE_PODF) + +//! @brief Format value for bitfield CCM_CBCMR_GPU3D_CORE_PODF. +#define BF_CCM_CBCMR_GPU3D_CORE_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_GPU3D_CORE_PODF) & BM_CCM_CBCMR_GPU3D_CORE_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GPU3D_CORE_PODF field to a new value. +#define BW_CCM_CBCMR_GPU3D_CORE_PODF(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_GPU3D_CORE_PODF) | BF_CCM_CBCMR_GPU3D_CORE_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CBCMR, field GPU2D_CORE_PODF[31:29] (RW) + * + * Divider for gpu2d_core clock. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 (default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CBCMR_GPU2D_CORE_PODF (29) //!< Bit position for CCM_CBCMR_GPU2D_CORE_PODF. +#define BM_CCM_CBCMR_GPU2D_CORE_PODF (0xe0000000) //!< Bit mask for CCM_CBCMR_GPU2D_CORE_PODF. + +//! @brief Get value of CCM_CBCMR_GPU2D_CORE_PODF from a register value. +#define BG_CCM_CBCMR_GPU2D_CORE_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CBCMR_GPU2D_CORE_PODF) >> BP_CCM_CBCMR_GPU2D_CORE_PODF) + +//! @brief Format value for bitfield CCM_CBCMR_GPU2D_CORE_PODF. +#define BF_CCM_CBCMR_GPU2D_CORE_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CBCMR_GPU2D_CORE_PODF) & BM_CCM_CBCMR_GPU2D_CORE_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GPU2D_CORE_PODF field to a new value. +#define BW_CCM_CBCMR_GPU2D_CORE_PODF(v) (HW_CCM_CBCMR_WR((HW_CCM_CBCMR_RD() & ~BM_CCM_CBCMR_GPU2D_CORE_PODF) | BF_CCM_CBCMR_GPU2D_CORE_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CSCMR1 - CCM Serial Clock Multiplexer Register 1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CSCMR1 - CCM Serial Clock Multiplexer Register 1 (RW) + * + * Reset value: 0x00f00000 + * + * The figure below represents the CCM Serial Clock Multiplexer Register 1 (CSCMR1). The CSCMR1 + * register contains bits to control the multiplexers that generate the serial clocks. The table + * below provides its field descriptions. Note: Any change on the above multiplexer will have to be + * done while the module that its clock is affected is not functional and the clock is gated. If the + * change will be done during operation of the module, then it is not guaranteed that the modules + * operation will not be harmed. + */ +typedef union _hw_ccm_cscmr1 +{ + reg32_t U; + struct _hw_ccm_cscmr1_bitfields + { + unsigned PERCLK_PODF : 6; //!< [5:0] Divider for perclk podf. + unsigned RESERVED0 : 4; //!< [9:6] Reserved + unsigned SSI1_CLK_SEL : 2; //!< [11:10] Selector for ssi1 clock multiplexer + unsigned SSI2_CLK_SEL : 2; //!< [13:12] Selector for ssi2 clock multiplexer + unsigned SSI3_CLK_SEL : 2; //!< [15:14] Selector for ssi3 clock multiplexer + unsigned USDHC1_CLK_SEL : 1; //!< [16] Selector for usdhc1 clock multiplexer + unsigned USDHC2_CLK_SEL : 1; //!< [17] Selector for usdhc2 clock multiplexer + unsigned USDHC3_CLK_SEL : 1; //!< [18] Selector for usdhc3 clock multiplexer + unsigned USDHC4_CLK_SEL : 1; //!< [19] Selector for usdhc4 clock multiplexer + unsigned ACLK_PODF : 3; //!< [22:20] Divider for aclk clock root. + unsigned ACLK_EIM_SLOW_PODF : 3; //!< [25:23] Divider for aclk_eim_slow clock root. + unsigned RESERVED1 : 1; //!< [26] Reserved + unsigned ACLK_SEL : 2; //!< [28:27] Selector for aclk root clock multiplexer + unsigned ACLK_EIM_SLOW_SEL : 2; //!< [30:29] Selector for aclk_eim_slow root clock multiplexer + unsigned RESERVED2 : 1; //!< [31] Reserved. + } B; +} hw_ccm_cscmr1_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CSCMR1 register + */ +//@{ +#define HW_CCM_CSCMR1_ADDR (REGS_CCM_BASE + 0x1c) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CSCMR1 (*(volatile hw_ccm_cscmr1_t *) HW_CCM_CSCMR1_ADDR) +#define HW_CCM_CSCMR1_RD() (HW_CCM_CSCMR1.U) +#define HW_CCM_CSCMR1_WR(v) (HW_CCM_CSCMR1.U = (v)) +#define HW_CCM_CSCMR1_SET(v) (HW_CCM_CSCMR1_WR(HW_CCM_CSCMR1_RD() | (v))) +#define HW_CCM_CSCMR1_CLR(v) (HW_CCM_CSCMR1_WR(HW_CCM_CSCMR1_RD() & ~(v))) +#define HW_CCM_CSCMR1_TOG(v) (HW_CCM_CSCMR1_WR(HW_CCM_CSCMR1_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CSCMR1 bitfields + */ + +/*! @name Register CCM_CSCMR1, field PERCLK_PODF[5:0] (RW) + * + * Divider for perclk podf. + * + * Values: + * - 000 - divide by 1 (default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCMR1_PERCLK_PODF (0) //!< Bit position for CCM_CSCMR1_PERCLK_PODF. +#define BM_CCM_CSCMR1_PERCLK_PODF (0x0000003f) //!< Bit mask for CCM_CSCMR1_PERCLK_PODF. + +//! @brief Get value of CCM_CSCMR1_PERCLK_PODF from a register value. +#define BG_CCM_CSCMR1_PERCLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_PERCLK_PODF) >> BP_CCM_CSCMR1_PERCLK_PODF) + +//! @brief Format value for bitfield CCM_CSCMR1_PERCLK_PODF. +#define BF_CCM_CSCMR1_PERCLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_PERCLK_PODF) & BM_CCM_CSCMR1_PERCLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERCLK_PODF field to a new value. +#define BW_CCM_CSCMR1_PERCLK_PODF(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_PERCLK_PODF) | BF_CCM_CSCMR1_PERCLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field SSI1_CLK_SEL[11:10] (RW) + * + * Selector for ssi1 clock multiplexer + * + * Values: + * - 00 - derive clock from 508.2M PFD (default) + * - 10 - derive clock from pll4 + * - 11 - Restricted + */ +//@{ +#define BP_CCM_CSCMR1_SSI1_CLK_SEL (10) //!< Bit position for CCM_CSCMR1_SSI1_CLK_SEL. +#define BM_CCM_CSCMR1_SSI1_CLK_SEL (0x00000c00) //!< Bit mask for CCM_CSCMR1_SSI1_CLK_SEL. + +//! @brief Get value of CCM_CSCMR1_SSI1_CLK_SEL from a register value. +#define BG_CCM_CSCMR1_SSI1_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_SSI1_CLK_SEL) >> BP_CCM_CSCMR1_SSI1_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_SSI1_CLK_SEL. +#define BF_CCM_CSCMR1_SSI1_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_SSI1_CLK_SEL) & BM_CCM_CSCMR1_SSI1_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI1_CLK_SEL field to a new value. +#define BW_CCM_CSCMR1_SSI1_CLK_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_SSI1_CLK_SEL) | BF_CCM_CSCMR1_SSI1_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field SSI2_CLK_SEL[13:12] (RW) + * + * Selector for ssi2 clock multiplexer + * + * Values: + * - 00 - derive clock from 508.2M PFD (default) + * - 10 - derive clock from pll4 + * - 11 - Restricted + */ +//@{ +#define BP_CCM_CSCMR1_SSI2_CLK_SEL (12) //!< Bit position for CCM_CSCMR1_SSI2_CLK_SEL. +#define BM_CCM_CSCMR1_SSI2_CLK_SEL (0x00003000) //!< Bit mask for CCM_CSCMR1_SSI2_CLK_SEL. + +//! @brief Get value of CCM_CSCMR1_SSI2_CLK_SEL from a register value. +#define BG_CCM_CSCMR1_SSI2_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_SSI2_CLK_SEL) >> BP_CCM_CSCMR1_SSI2_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_SSI2_CLK_SEL. +#define BF_CCM_CSCMR1_SSI2_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_SSI2_CLK_SEL) & BM_CCM_CSCMR1_SSI2_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI2_CLK_SEL field to a new value. +#define BW_CCM_CSCMR1_SSI2_CLK_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_SSI2_CLK_SEL) | BF_CCM_CSCMR1_SSI2_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field SSI3_CLK_SEL[15:14] (RW) + * + * Selector for ssi3 clock multiplexer + * + * Values: + * - 00 - derive clock from 508.2M PFD (default) + * - 10 - derive clock from pll4 + * - 11 - Restricted + */ +//@{ +#define BP_CCM_CSCMR1_SSI3_CLK_SEL (14) //!< Bit position for CCM_CSCMR1_SSI3_CLK_SEL. +#define BM_CCM_CSCMR1_SSI3_CLK_SEL (0x0000c000) //!< Bit mask for CCM_CSCMR1_SSI3_CLK_SEL. + +//! @brief Get value of CCM_CSCMR1_SSI3_CLK_SEL from a register value. +#define BG_CCM_CSCMR1_SSI3_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_SSI3_CLK_SEL) >> BP_CCM_CSCMR1_SSI3_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_SSI3_CLK_SEL. +#define BF_CCM_CSCMR1_SSI3_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_SSI3_CLK_SEL) & BM_CCM_CSCMR1_SSI3_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI3_CLK_SEL field to a new value. +#define BW_CCM_CSCMR1_SSI3_CLK_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_SSI3_CLK_SEL) | BF_CCM_CSCMR1_SSI3_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field USDHC1_CLK_SEL[16] (RW) + * + * Selector for usdhc1 clock multiplexer + * + * Values: + * - 0 - derive clock from 396M PFD + * - 1 - derive clock from 307M PFD + */ +//@{ +#define BP_CCM_CSCMR1_USDHC1_CLK_SEL (16) //!< Bit position for CCM_CSCMR1_USDHC1_CLK_SEL. +#define BM_CCM_CSCMR1_USDHC1_CLK_SEL (0x00010000) //!< Bit mask for CCM_CSCMR1_USDHC1_CLK_SEL. + +//! @brief Get value of CCM_CSCMR1_USDHC1_CLK_SEL from a register value. +#define BG_CCM_CSCMR1_USDHC1_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_USDHC1_CLK_SEL) >> BP_CCM_CSCMR1_USDHC1_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_USDHC1_CLK_SEL. +#define BF_CCM_CSCMR1_USDHC1_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_USDHC1_CLK_SEL) & BM_CCM_CSCMR1_USDHC1_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the USDHC1_CLK_SEL field to a new value. +#define BW_CCM_CSCMR1_USDHC1_CLK_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_USDHC1_CLK_SEL) | BF_CCM_CSCMR1_USDHC1_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field USDHC2_CLK_SEL[17] (RW) + * + * Selector for usdhc2 clock multiplexer + * + * Values: + * - 0 - derive clock from 396M PFD + * - 1 - derive clock from 307M PFD + */ +//@{ +#define BP_CCM_CSCMR1_USDHC2_CLK_SEL (17) //!< Bit position for CCM_CSCMR1_USDHC2_CLK_SEL. +#define BM_CCM_CSCMR1_USDHC2_CLK_SEL (0x00020000) //!< Bit mask for CCM_CSCMR1_USDHC2_CLK_SEL. + +//! @brief Get value of CCM_CSCMR1_USDHC2_CLK_SEL from a register value. +#define BG_CCM_CSCMR1_USDHC2_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_USDHC2_CLK_SEL) >> BP_CCM_CSCMR1_USDHC2_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_USDHC2_CLK_SEL. +#define BF_CCM_CSCMR1_USDHC2_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_USDHC2_CLK_SEL) & BM_CCM_CSCMR1_USDHC2_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the USDHC2_CLK_SEL field to a new value. +#define BW_CCM_CSCMR1_USDHC2_CLK_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_USDHC2_CLK_SEL) | BF_CCM_CSCMR1_USDHC2_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field USDHC3_CLK_SEL[18] (RW) + * + * Selector for usdhc3 clock multiplexer + * + * Values: + * - 0 - derive clock from 396M PFD + * - 1 - derive clock from 307M PFD + */ +//@{ +#define BP_CCM_CSCMR1_USDHC3_CLK_SEL (18) //!< Bit position for CCM_CSCMR1_USDHC3_CLK_SEL. +#define BM_CCM_CSCMR1_USDHC3_CLK_SEL (0x00040000) //!< Bit mask for CCM_CSCMR1_USDHC3_CLK_SEL. + +//! @brief Get value of CCM_CSCMR1_USDHC3_CLK_SEL from a register value. +#define BG_CCM_CSCMR1_USDHC3_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_USDHC3_CLK_SEL) >> BP_CCM_CSCMR1_USDHC3_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_USDHC3_CLK_SEL. +#define BF_CCM_CSCMR1_USDHC3_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_USDHC3_CLK_SEL) & BM_CCM_CSCMR1_USDHC3_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the USDHC3_CLK_SEL field to a new value. +#define BW_CCM_CSCMR1_USDHC3_CLK_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_USDHC3_CLK_SEL) | BF_CCM_CSCMR1_USDHC3_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field USDHC4_CLK_SEL[19] (RW) + * + * Selector for usdhc4 clock multiplexer + * + * Values: + * - 0 - derive clock from 396M PFD + * - 1 - derive clock from 307M PFD + */ +//@{ +#define BP_CCM_CSCMR1_USDHC4_CLK_SEL (19) //!< Bit position for CCM_CSCMR1_USDHC4_CLK_SEL. +#define BM_CCM_CSCMR1_USDHC4_CLK_SEL (0x00080000) //!< Bit mask for CCM_CSCMR1_USDHC4_CLK_SEL. + +//! @brief Get value of CCM_CSCMR1_USDHC4_CLK_SEL from a register value. +#define BG_CCM_CSCMR1_USDHC4_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_USDHC4_CLK_SEL) >> BP_CCM_CSCMR1_USDHC4_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_USDHC4_CLK_SEL. +#define BF_CCM_CSCMR1_USDHC4_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_USDHC4_CLK_SEL) & BM_CCM_CSCMR1_USDHC4_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the USDHC4_CLK_SEL field to a new value. +#define BW_CCM_CSCMR1_USDHC4_CLK_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_USDHC4_CLK_SEL) | BF_CCM_CSCMR1_USDHC4_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field ACLK_PODF[22:20] (RW) + * + * Divider for aclk clock root. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 111 - divide by 8 (default) + */ +//@{ +#define BP_CCM_CSCMR1_ACLK_PODF (20) //!< Bit position for CCM_CSCMR1_ACLK_PODF. +#define BM_CCM_CSCMR1_ACLK_PODF (0x00700000) //!< Bit mask for CCM_CSCMR1_ACLK_PODF. + +//! @brief Get value of CCM_CSCMR1_ACLK_PODF from a register value. +#define BG_CCM_CSCMR1_ACLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_ACLK_PODF) >> BP_CCM_CSCMR1_ACLK_PODF) + +//! @brief Format value for bitfield CCM_CSCMR1_ACLK_PODF. +#define BF_CCM_CSCMR1_ACLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_ACLK_PODF) & BM_CCM_CSCMR1_ACLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ACLK_PODF field to a new value. +#define BW_CCM_CSCMR1_ACLK_PODF(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_ACLK_PODF) | BF_CCM_CSCMR1_ACLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field ACLK_EIM_SLOW_PODF[25:23] (RW) + * + * Divider for aclk_eim_slow clock root. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCMR1_ACLK_EIM_SLOW_PODF (23) //!< Bit position for CCM_CSCMR1_ACLK_EIM_SLOW_PODF. +#define BM_CCM_CSCMR1_ACLK_EIM_SLOW_PODF (0x03800000) //!< Bit mask for CCM_CSCMR1_ACLK_EIM_SLOW_PODF. + +//! @brief Get value of CCM_CSCMR1_ACLK_EIM_SLOW_PODF from a register value. +#define BG_CCM_CSCMR1_ACLK_EIM_SLOW_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_ACLK_EIM_SLOW_PODF) >> BP_CCM_CSCMR1_ACLK_EIM_SLOW_PODF) + +//! @brief Format value for bitfield CCM_CSCMR1_ACLK_EIM_SLOW_PODF. +#define BF_CCM_CSCMR1_ACLK_EIM_SLOW_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_ACLK_EIM_SLOW_PODF) & BM_CCM_CSCMR1_ACLK_EIM_SLOW_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ACLK_EIM_SLOW_PODF field to a new value. +#define BW_CCM_CSCMR1_ACLK_EIM_SLOW_PODF(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_ACLK_EIM_SLOW_PODF) | BF_CCM_CSCMR1_ACLK_EIM_SLOW_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field ACLK_SEL[28:27] (RW) + * + * Selector for aclk root clock multiplexer + * + * Values: + * - 00 - derive clock from 396M PFD (default) + * - 01 - derive clock from PLL3 + * - 10 - derive clock from AXI clk root + * - 11 - derive clock from 307M PFD + */ +//@{ +#define BP_CCM_CSCMR1_ACLK_SEL (27) //!< Bit position for CCM_CSCMR1_ACLK_SEL. +#define BM_CCM_CSCMR1_ACLK_SEL (0x18000000) //!< Bit mask for CCM_CSCMR1_ACLK_SEL. + +//! @brief Get value of CCM_CSCMR1_ACLK_SEL from a register value. +#define BG_CCM_CSCMR1_ACLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_ACLK_SEL) >> BP_CCM_CSCMR1_ACLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_ACLK_SEL. +#define BF_CCM_CSCMR1_ACLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_ACLK_SEL) & BM_CCM_CSCMR1_ACLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ACLK_SEL field to a new value. +#define BW_CCM_CSCMR1_ACLK_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_ACLK_SEL) | BF_CCM_CSCMR1_ACLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR1, field ACLK_EIM_SLOW_SEL[30:29] (RW) + * + * Selector for aclk_eim_slow root clock multiplexer + * + * Values: + * - 00 - derive clock from AXI clk root (default) + * - 01 - derive clock from PLL3 + * - 10 - derive clock from 396M PFD + * - 11 - derive clock from 307M PFD + */ +//@{ +#define BP_CCM_CSCMR1_ACLK_EIM_SLOW_SEL (29) //!< Bit position for CCM_CSCMR1_ACLK_EIM_SLOW_SEL. +#define BM_CCM_CSCMR1_ACLK_EIM_SLOW_SEL (0x60000000) //!< Bit mask for CCM_CSCMR1_ACLK_EIM_SLOW_SEL. + +//! @brief Get value of CCM_CSCMR1_ACLK_EIM_SLOW_SEL from a register value. +#define BG_CCM_CSCMR1_ACLK_EIM_SLOW_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR1_ACLK_EIM_SLOW_SEL) >> BP_CCM_CSCMR1_ACLK_EIM_SLOW_SEL) + +//! @brief Format value for bitfield CCM_CSCMR1_ACLK_EIM_SLOW_SEL. +#define BF_CCM_CSCMR1_ACLK_EIM_SLOW_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR1_ACLK_EIM_SLOW_SEL) & BM_CCM_CSCMR1_ACLK_EIM_SLOW_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ACLK_EIM_SLOW_SEL field to a new value. +#define BW_CCM_CSCMR1_ACLK_EIM_SLOW_SEL(v) (HW_CCM_CSCMR1_WR((HW_CCM_CSCMR1_RD() & ~BM_CCM_CSCMR1_ACLK_EIM_SLOW_SEL) | BF_CCM_CSCMR1_ACLK_EIM_SLOW_SEL(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CSCMR2 - CCM Serial Clock Multiplexer Register 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CSCMR2 - CCM Serial Clock Multiplexer Register 2 (RW) + * + * Reset value: 0x02b92f06 + * + * The figure below represents the CCM Serial Clock Multiplexer Register 2 (CSCMR2). The CSCMR2 + * register contains bits to control the multiplexers that generate the serial clocks. The table + * below provides its field descriptions. Note: Any change on the above multiplexer will have to be + * done while the module that its clock is affected is not functional and the clock is gated. If the + * change will be done during operation of the module, then it is not guaranteed that the modules + * operation will not be harmed. + */ +typedef union _hw_ccm_cscmr2 +{ + reg32_t U; + struct _hw_ccm_cscmr2_bitfields + { + unsigned RESERVED0 : 2; //!< [1:0] Reserved + unsigned CAN_CLK_PODF : 6; //!< [7:2] Divider for can clock podf. + unsigned RESERVED1 : 2; //!< [9:8] Reserved + unsigned LDB_DI0_IPU_DIV : 1; //!< [10] Control for divider of ldb clock for IPU di0 + unsigned LDB_DI1_IPU_DIV : 1; //!< [11] Control for divider of ldb clock for IPU di1 + unsigned RESERVED2 : 7; //!< [18:12] Reserved + unsigned ESAI_CLK_SEL : 2; //!< [20:19] Selector for esai clock multiplexer + unsigned RESERVED3 : 11; //!< [31:21] Reserved + } B; +} hw_ccm_cscmr2_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CSCMR2 register + */ +//@{ +#define HW_CCM_CSCMR2_ADDR (REGS_CCM_BASE + 0x20) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CSCMR2 (*(volatile hw_ccm_cscmr2_t *) HW_CCM_CSCMR2_ADDR) +#define HW_CCM_CSCMR2_RD() (HW_CCM_CSCMR2.U) +#define HW_CCM_CSCMR2_WR(v) (HW_CCM_CSCMR2.U = (v)) +#define HW_CCM_CSCMR2_SET(v) (HW_CCM_CSCMR2_WR(HW_CCM_CSCMR2_RD() | (v))) +#define HW_CCM_CSCMR2_CLR(v) (HW_CCM_CSCMR2_WR(HW_CCM_CSCMR2_RD() & ~(v))) +#define HW_CCM_CSCMR2_TOG(v) (HW_CCM_CSCMR2_WR(HW_CCM_CSCMR2_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CSCMR2 bitfields + */ + +/*! @name Register CCM_CSCMR2, field CAN_CLK_PODF[7:2] (RW) + * + * Divider for can clock podf. + * + * Values: + * - 000000 - divide by 1 + * - 000111 - divide by 8 + * - 111111 - divide by 2^6 + */ +//@{ +#define BP_CCM_CSCMR2_CAN_CLK_PODF (2) //!< Bit position for CCM_CSCMR2_CAN_CLK_PODF. +#define BM_CCM_CSCMR2_CAN_CLK_PODF (0x000000fc) //!< Bit mask for CCM_CSCMR2_CAN_CLK_PODF. + +//! @brief Get value of CCM_CSCMR2_CAN_CLK_PODF from a register value. +#define BG_CCM_CSCMR2_CAN_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR2_CAN_CLK_PODF) >> BP_CCM_CSCMR2_CAN_CLK_PODF) + +//! @brief Format value for bitfield CCM_CSCMR2_CAN_CLK_PODF. +#define BF_CCM_CSCMR2_CAN_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR2_CAN_CLK_PODF) & BM_CCM_CSCMR2_CAN_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CAN_CLK_PODF field to a new value. +#define BW_CCM_CSCMR2_CAN_CLK_PODF(v) (HW_CCM_CSCMR2_WR((HW_CCM_CSCMR2_RD() & ~BM_CCM_CSCMR2_CAN_CLK_PODF) | BF_CCM_CSCMR2_CAN_CLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR2, field LDB_DI0_IPU_DIV[10] (RW) + * + * Control for divider of ldb clock for IPU di0 + * + * Values: + * - 0 - divide by 3.5 + * - 1 - divide by 7(default) + */ +//@{ +#define BP_CCM_CSCMR2_LDB_DI0_IPU_DIV (10) //!< Bit position for CCM_CSCMR2_LDB_DI0_IPU_DIV. +#define BM_CCM_CSCMR2_LDB_DI0_IPU_DIV (0x00000400) //!< Bit mask for CCM_CSCMR2_LDB_DI0_IPU_DIV. + +//! @brief Get value of CCM_CSCMR2_LDB_DI0_IPU_DIV from a register value. +#define BG_CCM_CSCMR2_LDB_DI0_IPU_DIV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR2_LDB_DI0_IPU_DIV) >> BP_CCM_CSCMR2_LDB_DI0_IPU_DIV) + +//! @brief Format value for bitfield CCM_CSCMR2_LDB_DI0_IPU_DIV. +#define BF_CCM_CSCMR2_LDB_DI0_IPU_DIV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR2_LDB_DI0_IPU_DIV) & BM_CCM_CSCMR2_LDB_DI0_IPU_DIV) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LDB_DI0_IPU_DIV field to a new value. +#define BW_CCM_CSCMR2_LDB_DI0_IPU_DIV(v) (HW_CCM_CSCMR2_WR((HW_CCM_CSCMR2_RD() & ~BM_CCM_CSCMR2_LDB_DI0_IPU_DIV) | BF_CCM_CSCMR2_LDB_DI0_IPU_DIV(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR2, field LDB_DI1_IPU_DIV[11] (RW) + * + * Control for divider of ldb clock for IPU di1 + * + * Values: + * - 0 - divide by 3.5 + * - 1 - divide by 7(default) + */ +//@{ +#define BP_CCM_CSCMR2_LDB_DI1_IPU_DIV (11) //!< Bit position for CCM_CSCMR2_LDB_DI1_IPU_DIV. +#define BM_CCM_CSCMR2_LDB_DI1_IPU_DIV (0x00000800) //!< Bit mask for CCM_CSCMR2_LDB_DI1_IPU_DIV. + +//! @brief Get value of CCM_CSCMR2_LDB_DI1_IPU_DIV from a register value. +#define BG_CCM_CSCMR2_LDB_DI1_IPU_DIV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR2_LDB_DI1_IPU_DIV) >> BP_CCM_CSCMR2_LDB_DI1_IPU_DIV) + +//! @brief Format value for bitfield CCM_CSCMR2_LDB_DI1_IPU_DIV. +#define BF_CCM_CSCMR2_LDB_DI1_IPU_DIV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR2_LDB_DI1_IPU_DIV) & BM_CCM_CSCMR2_LDB_DI1_IPU_DIV) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LDB_DI1_IPU_DIV field to a new value. +#define BW_CCM_CSCMR2_LDB_DI1_IPU_DIV(v) (HW_CCM_CSCMR2_WR((HW_CCM_CSCMR2_RD() & ~BM_CCM_CSCMR2_LDB_DI1_IPU_DIV) | BF_CCM_CSCMR2_LDB_DI1_IPU_DIV(v))) +#endif +//@} + +/*! @name Register CCM_CSCMR2, field ESAI_CLK_SEL[20:19] (RW) + * + * Selector for esai clock multiplexer + * + * Values: + * - 00 - derive clock from pll4 divided clock + * - 01 - derive clock from 508M PFD clock + * - 11 - derive clock from pll3 clock + */ +//@{ +#define BP_CCM_CSCMR2_ESAI_CLK_SEL (19) //!< Bit position for CCM_CSCMR2_ESAI_CLK_SEL. +#define BM_CCM_CSCMR2_ESAI_CLK_SEL (0x00180000) //!< Bit mask for CCM_CSCMR2_ESAI_CLK_SEL. + +//! @brief Get value of CCM_CSCMR2_ESAI_CLK_SEL from a register value. +#define BG_CCM_CSCMR2_ESAI_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCMR2_ESAI_CLK_SEL) >> BP_CCM_CSCMR2_ESAI_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCMR2_ESAI_CLK_SEL. +#define BF_CCM_CSCMR2_ESAI_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCMR2_ESAI_CLK_SEL) & BM_CCM_CSCMR2_ESAI_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ESAI_CLK_SEL field to a new value. +#define BW_CCM_CSCMR2_ESAI_CLK_SEL(v) (HW_CCM_CSCMR2_WR((HW_CCM_CSCMR2_RD() & ~BM_CCM_CSCMR2_ESAI_CLK_SEL) | BF_CCM_CSCMR2_ESAI_CLK_SEL(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CSCDR1 - CCM Serial Clock Divider Register 1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CSCDR1 - CCM Serial Clock Divider Register 1 (RW) + * + * Reset value: 0x00490b00 + * + * The figure below represents the CCM Serial Clock Divider Register 1 (CSCDR1). The CSCDR1 register + * contains bits to control the clock generation sub module dividers. The table below provides its + * field descriptions. Note: Any change on the above dividers will have to be done while the module + * that its clock is affected is not functional and the affected clock is gated. If the change will + * be done during operation of the module, then it is not guaranteed that the modules operation will + * not be harmed. + */ +typedef union _hw_ccm_cscdr1 +{ + reg32_t U; + struct _hw_ccm_cscdr1_bitfields + { + unsigned UART_CLK_PODF : 6; //!< [5:0] Divider for uart clock podf. + unsigned RESERVED0 : 5; //!< [10:6] Reserved. + unsigned USDHC1_PODF : 3; //!< [13:11] Divider for usdhc1 clock podf. + unsigned RESERVED1 : 2; //!< [15:14] Reserved + unsigned USDHC2_PODF : 3; //!< [18:16] Divider for usdhc2 clock. + unsigned USDHC3_PODF : 3; //!< [21:19] Divider for usdhc3 clock podf. + unsigned USDHC4_PODF : 3; //!< [24:22] Divider for esdhc4 clock pred. + unsigned VPU_AXI_PODF : 3; //!< [27:25] Divider for vpu axi clock podf. + unsigned RESERVED2 : 4; //!< [31:28] Reserved + } B; +} hw_ccm_cscdr1_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CSCDR1 register + */ +//@{ +#define HW_CCM_CSCDR1_ADDR (REGS_CCM_BASE + 0x24) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CSCDR1 (*(volatile hw_ccm_cscdr1_t *) HW_CCM_CSCDR1_ADDR) +#define HW_CCM_CSCDR1_RD() (HW_CCM_CSCDR1.U) +#define HW_CCM_CSCDR1_WR(v) (HW_CCM_CSCDR1.U = (v)) +#define HW_CCM_CSCDR1_SET(v) (HW_CCM_CSCDR1_WR(HW_CCM_CSCDR1_RD() | (v))) +#define HW_CCM_CSCDR1_CLR(v) (HW_CCM_CSCDR1_WR(HW_CCM_CSCDR1_RD() & ~(v))) +#define HW_CCM_CSCDR1_TOG(v) (HW_CCM_CSCDR1_WR(HW_CCM_CSCDR1_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CSCDR1 bitfields + */ + +/*! @name Register CCM_CSCDR1, field UART_CLK_PODF[5:0] (RW) + * + * Divider for uart clock podf. + * + * Values: + * - 000000 - divide by 1 (default) + * - 111111 - divide by 2^6 + */ +//@{ +#define BP_CCM_CSCDR1_UART_CLK_PODF (0) //!< Bit position for CCM_CSCDR1_UART_CLK_PODF. +#define BM_CCM_CSCDR1_UART_CLK_PODF (0x0000003f) //!< Bit mask for CCM_CSCDR1_UART_CLK_PODF. + +//! @brief Get value of CCM_CSCDR1_UART_CLK_PODF from a register value. +#define BG_CCM_CSCDR1_UART_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR1_UART_CLK_PODF) >> BP_CCM_CSCDR1_UART_CLK_PODF) + +//! @brief Format value for bitfield CCM_CSCDR1_UART_CLK_PODF. +#define BF_CCM_CSCDR1_UART_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR1_UART_CLK_PODF) & BM_CCM_CSCDR1_UART_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the UART_CLK_PODF field to a new value. +#define BW_CCM_CSCDR1_UART_CLK_PODF(v) (HW_CCM_CSCDR1_WR((HW_CCM_CSCDR1_RD() & ~BM_CCM_CSCDR1_UART_CLK_PODF) | BF_CCM_CSCDR1_UART_CLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR1, field USDHC1_PODF[13:11] (RW) + * + * Divider for usdhc1 clock podf. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCDR1_USDHC1_PODF (11) //!< Bit position for CCM_CSCDR1_USDHC1_PODF. +#define BM_CCM_CSCDR1_USDHC1_PODF (0x00003800) //!< Bit mask for CCM_CSCDR1_USDHC1_PODF. + +//! @brief Get value of CCM_CSCDR1_USDHC1_PODF from a register value. +#define BG_CCM_CSCDR1_USDHC1_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR1_USDHC1_PODF) >> BP_CCM_CSCDR1_USDHC1_PODF) + +//! @brief Format value for bitfield CCM_CSCDR1_USDHC1_PODF. +#define BF_CCM_CSCDR1_USDHC1_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR1_USDHC1_PODF) & BM_CCM_CSCDR1_USDHC1_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the USDHC1_PODF field to a new value. +#define BW_CCM_CSCDR1_USDHC1_PODF(v) (HW_CCM_CSCDR1_WR((HW_CCM_CSCDR1_RD() & ~BM_CCM_CSCDR1_USDHC1_PODF) | BF_CCM_CSCDR1_USDHC1_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR1, field USDHC2_PODF[18:16] (RW) + * + * Divider for usdhc2 clock. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCDR1_USDHC2_PODF (16) //!< Bit position for CCM_CSCDR1_USDHC2_PODF. +#define BM_CCM_CSCDR1_USDHC2_PODF (0x00070000) //!< Bit mask for CCM_CSCDR1_USDHC2_PODF. + +//! @brief Get value of CCM_CSCDR1_USDHC2_PODF from a register value. +#define BG_CCM_CSCDR1_USDHC2_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR1_USDHC2_PODF) >> BP_CCM_CSCDR1_USDHC2_PODF) + +//! @brief Format value for bitfield CCM_CSCDR1_USDHC2_PODF. +#define BF_CCM_CSCDR1_USDHC2_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR1_USDHC2_PODF) & BM_CCM_CSCDR1_USDHC2_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the USDHC2_PODF field to a new value. +#define BW_CCM_CSCDR1_USDHC2_PODF(v) (HW_CCM_CSCDR1_WR((HW_CCM_CSCDR1_RD() & ~BM_CCM_CSCDR1_USDHC2_PODF) | BF_CCM_CSCDR1_USDHC2_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR1, field USDHC3_PODF[21:19] (RW) + * + * Divider for usdhc3 clock podf. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCDR1_USDHC3_PODF (19) //!< Bit position for CCM_CSCDR1_USDHC3_PODF. +#define BM_CCM_CSCDR1_USDHC3_PODF (0x00380000) //!< Bit mask for CCM_CSCDR1_USDHC3_PODF. + +//! @brief Get value of CCM_CSCDR1_USDHC3_PODF from a register value. +#define BG_CCM_CSCDR1_USDHC3_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR1_USDHC3_PODF) >> BP_CCM_CSCDR1_USDHC3_PODF) + +//! @brief Format value for bitfield CCM_CSCDR1_USDHC3_PODF. +#define BF_CCM_CSCDR1_USDHC3_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR1_USDHC3_PODF) & BM_CCM_CSCDR1_USDHC3_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the USDHC3_PODF field to a new value. +#define BW_CCM_CSCDR1_USDHC3_PODF(v) (HW_CCM_CSCDR1_WR((HW_CCM_CSCDR1_RD() & ~BM_CCM_CSCDR1_USDHC3_PODF) | BF_CCM_CSCDR1_USDHC3_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR1, field USDHC4_PODF[24:22] (RW) + * + * Divider for esdhc4 clock pred. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCDR1_USDHC4_PODF (22) //!< Bit position for CCM_CSCDR1_USDHC4_PODF. +#define BM_CCM_CSCDR1_USDHC4_PODF (0x01c00000) //!< Bit mask for CCM_CSCDR1_USDHC4_PODF. + +//! @brief Get value of CCM_CSCDR1_USDHC4_PODF from a register value. +#define BG_CCM_CSCDR1_USDHC4_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR1_USDHC4_PODF) >> BP_CCM_CSCDR1_USDHC4_PODF) + +//! @brief Format value for bitfield CCM_CSCDR1_USDHC4_PODF. +#define BF_CCM_CSCDR1_USDHC4_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR1_USDHC4_PODF) & BM_CCM_CSCDR1_USDHC4_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the USDHC4_PODF field to a new value. +#define BW_CCM_CSCDR1_USDHC4_PODF(v) (HW_CCM_CSCDR1_WR((HW_CCM_CSCDR1_RD() & ~BM_CCM_CSCDR1_USDHC4_PODF) | BF_CCM_CSCDR1_USDHC4_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR1, field VPU_AXI_PODF[27:25] (RW) + * + * Divider for vpu axi clock podf. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 (default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCDR1_VPU_AXI_PODF (25) //!< Bit position for CCM_CSCDR1_VPU_AXI_PODF. +#define BM_CCM_CSCDR1_VPU_AXI_PODF (0x0e000000) //!< Bit mask for CCM_CSCDR1_VPU_AXI_PODF. + +//! @brief Get value of CCM_CSCDR1_VPU_AXI_PODF from a register value. +#define BG_CCM_CSCDR1_VPU_AXI_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR1_VPU_AXI_PODF) >> BP_CCM_CSCDR1_VPU_AXI_PODF) + +//! @brief Format value for bitfield CCM_CSCDR1_VPU_AXI_PODF. +#define BF_CCM_CSCDR1_VPU_AXI_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR1_VPU_AXI_PODF) & BM_CCM_CSCDR1_VPU_AXI_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VPU_AXI_PODF field to a new value. +#define BW_CCM_CSCDR1_VPU_AXI_PODF(v) (HW_CCM_CSCDR1_WR((HW_CCM_CSCDR1_RD() & ~BM_CCM_CSCDR1_VPU_AXI_PODF) | BF_CCM_CSCDR1_VPU_AXI_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CS1CDR - CCM SSI1 Clock Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CS1CDR - CCM SSI1 Clock Divider Register (RW) + * + * Reset value: 0x0ec102c1 + * + * The figure below represents the CCM SSI1, SSI3, ESAI Clock Divider Register (CS1CDR). The CS1CDR + * register contains bits to control the ssi1 clock generation dividers. The table below provides + * its field descriptions. + */ +typedef union _hw_ccm_cs1cdr +{ + reg32_t U; + struct _hw_ccm_cs1cdr_bitfields + { + unsigned SSI1_CLK_PODF : 6; //!< [5:0] Divider for ssi1 clock podf. + unsigned SSI1_CLK_PRED : 3; //!< [8:6] Divider for ssi1 clock pred. + unsigned ESAI_CLK_PRED : 3; //!< [11:9] Divider for esai clock pred. + unsigned RESERVED0 : 4; //!< [15:12] Reserved + unsigned SSI3_CLK_PODF : 6; //!< [21:16] Divider for ssi3 clock podf. + unsigned SSI3_CLK_PRED : 3; //!< [24:22] Divider for ssi3 clock pred. + unsigned ESAI_CLK_PODF : 3; //!< [27:25] Divider for esai clock podf. + unsigned RESERVED1 : 4; //!< [31:28] Reserved + } B; +} hw_ccm_cs1cdr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CS1CDR register + */ +//@{ +#define HW_CCM_CS1CDR_ADDR (REGS_CCM_BASE + 0x28) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CS1CDR (*(volatile hw_ccm_cs1cdr_t *) HW_CCM_CS1CDR_ADDR) +#define HW_CCM_CS1CDR_RD() (HW_CCM_CS1CDR.U) +#define HW_CCM_CS1CDR_WR(v) (HW_CCM_CS1CDR.U = (v)) +#define HW_CCM_CS1CDR_SET(v) (HW_CCM_CS1CDR_WR(HW_CCM_CS1CDR_RD() | (v))) +#define HW_CCM_CS1CDR_CLR(v) (HW_CCM_CS1CDR_WR(HW_CCM_CS1CDR_RD() & ~(v))) +#define HW_CCM_CS1CDR_TOG(v) (HW_CCM_CS1CDR_WR(HW_CCM_CS1CDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CS1CDR bitfields + */ + +/*! @name Register CCM_CS1CDR, field SSI1_CLK_PODF[5:0] (RW) + * + * Divider for ssi1 clock podf. The input clock to this divider should be lower than 300Mhz, the + * predivider can be used to achieve this. + * + * Values: + * - 000000 - divide by 1 + * - 111111 - divide by 2^6 + */ +//@{ +#define BP_CCM_CS1CDR_SSI1_CLK_PODF (0) //!< Bit position for CCM_CS1CDR_SSI1_CLK_PODF. +#define BM_CCM_CS1CDR_SSI1_CLK_PODF (0x0000003f) //!< Bit mask for CCM_CS1CDR_SSI1_CLK_PODF. + +//! @brief Get value of CCM_CS1CDR_SSI1_CLK_PODF from a register value. +#define BG_CCM_CS1CDR_SSI1_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS1CDR_SSI1_CLK_PODF) >> BP_CCM_CS1CDR_SSI1_CLK_PODF) + +//! @brief Format value for bitfield CCM_CS1CDR_SSI1_CLK_PODF. +#define BF_CCM_CS1CDR_SSI1_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS1CDR_SSI1_CLK_PODF) & BM_CCM_CS1CDR_SSI1_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI1_CLK_PODF field to a new value. +#define BW_CCM_CS1CDR_SSI1_CLK_PODF(v) (HW_CCM_CS1CDR_WR((HW_CCM_CS1CDR_RD() & ~BM_CCM_CS1CDR_SSI1_CLK_PODF) | BF_CCM_CS1CDR_SSI1_CLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CS1CDR, field SSI1_CLK_PRED[8:6] (RW) + * + * Divider for ssi1 clock pred. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CS1CDR_SSI1_CLK_PRED (6) //!< Bit position for CCM_CS1CDR_SSI1_CLK_PRED. +#define BM_CCM_CS1CDR_SSI1_CLK_PRED (0x000001c0) //!< Bit mask for CCM_CS1CDR_SSI1_CLK_PRED. + +//! @brief Get value of CCM_CS1CDR_SSI1_CLK_PRED from a register value. +#define BG_CCM_CS1CDR_SSI1_CLK_PRED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS1CDR_SSI1_CLK_PRED) >> BP_CCM_CS1CDR_SSI1_CLK_PRED) + +//! @brief Format value for bitfield CCM_CS1CDR_SSI1_CLK_PRED. +#define BF_CCM_CS1CDR_SSI1_CLK_PRED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS1CDR_SSI1_CLK_PRED) & BM_CCM_CS1CDR_SSI1_CLK_PRED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI1_CLK_PRED field to a new value. +#define BW_CCM_CS1CDR_SSI1_CLK_PRED(v) (HW_CCM_CS1CDR_WR((HW_CCM_CS1CDR_RD() & ~BM_CCM_CS1CDR_SSI1_CLK_PRED) | BF_CCM_CS1CDR_SSI1_CLK_PRED(v))) +#endif +//@} + +/*! @name Register CCM_CS1CDR, field ESAI_CLK_PRED[11:9] (RW) + * + * Divider for esai clock pred. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CS1CDR_ESAI_CLK_PRED (9) //!< Bit position for CCM_CS1CDR_ESAI_CLK_PRED. +#define BM_CCM_CS1CDR_ESAI_CLK_PRED (0x00000e00) //!< Bit mask for CCM_CS1CDR_ESAI_CLK_PRED. + +//! @brief Get value of CCM_CS1CDR_ESAI_CLK_PRED from a register value. +#define BG_CCM_CS1CDR_ESAI_CLK_PRED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS1CDR_ESAI_CLK_PRED) >> BP_CCM_CS1CDR_ESAI_CLK_PRED) + +//! @brief Format value for bitfield CCM_CS1CDR_ESAI_CLK_PRED. +#define BF_CCM_CS1CDR_ESAI_CLK_PRED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS1CDR_ESAI_CLK_PRED) & BM_CCM_CS1CDR_ESAI_CLK_PRED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ESAI_CLK_PRED field to a new value. +#define BW_CCM_CS1CDR_ESAI_CLK_PRED(v) (HW_CCM_CS1CDR_WR((HW_CCM_CS1CDR_RD() & ~BM_CCM_CS1CDR_ESAI_CLK_PRED) | BF_CCM_CS1CDR_ESAI_CLK_PRED(v))) +#endif +//@} + +/*! @name Register CCM_CS1CDR, field SSI3_CLK_PODF[21:16] (RW) + * + * Divider for ssi3 clock podf. The input clock to this divider should be lower than 300Mhz, the + * predivider can be used to achieve this. + * + * Values: + * - 000000 - divide by 1 + * - 111111 - divide by 2^6 + */ +//@{ +#define BP_CCM_CS1CDR_SSI3_CLK_PODF (16) //!< Bit position for CCM_CS1CDR_SSI3_CLK_PODF. +#define BM_CCM_CS1CDR_SSI3_CLK_PODF (0x003f0000) //!< Bit mask for CCM_CS1CDR_SSI3_CLK_PODF. + +//! @brief Get value of CCM_CS1CDR_SSI3_CLK_PODF from a register value. +#define BG_CCM_CS1CDR_SSI3_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS1CDR_SSI3_CLK_PODF) >> BP_CCM_CS1CDR_SSI3_CLK_PODF) + +//! @brief Format value for bitfield CCM_CS1CDR_SSI3_CLK_PODF. +#define BF_CCM_CS1CDR_SSI3_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS1CDR_SSI3_CLK_PODF) & BM_CCM_CS1CDR_SSI3_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI3_CLK_PODF field to a new value. +#define BW_CCM_CS1CDR_SSI3_CLK_PODF(v) (HW_CCM_CS1CDR_WR((HW_CCM_CS1CDR_RD() & ~BM_CCM_CS1CDR_SSI3_CLK_PODF) | BF_CCM_CS1CDR_SSI3_CLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CS1CDR, field SSI3_CLK_PRED[24:22] (RW) + * + * Divider for ssi3 clock pred. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CS1CDR_SSI3_CLK_PRED (22) //!< Bit position for CCM_CS1CDR_SSI3_CLK_PRED. +#define BM_CCM_CS1CDR_SSI3_CLK_PRED (0x01c00000) //!< Bit mask for CCM_CS1CDR_SSI3_CLK_PRED. + +//! @brief Get value of CCM_CS1CDR_SSI3_CLK_PRED from a register value. +#define BG_CCM_CS1CDR_SSI3_CLK_PRED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS1CDR_SSI3_CLK_PRED) >> BP_CCM_CS1CDR_SSI3_CLK_PRED) + +//! @brief Format value for bitfield CCM_CS1CDR_SSI3_CLK_PRED. +#define BF_CCM_CS1CDR_SSI3_CLK_PRED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS1CDR_SSI3_CLK_PRED) & BM_CCM_CS1CDR_SSI3_CLK_PRED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI3_CLK_PRED field to a new value. +#define BW_CCM_CS1CDR_SSI3_CLK_PRED(v) (HW_CCM_CS1CDR_WR((HW_CCM_CS1CDR_RD() & ~BM_CCM_CS1CDR_SSI3_CLK_PRED) | BF_CCM_CS1CDR_SSI3_CLK_PRED(v))) +#endif +//@} + +/*! @name Register CCM_CS1CDR, field ESAI_CLK_PODF[27:25] (RW) + * + * Divider for esai clock podf. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CS1CDR_ESAI_CLK_PODF (25) //!< Bit position for CCM_CS1CDR_ESAI_CLK_PODF. +#define BM_CCM_CS1CDR_ESAI_CLK_PODF (0x0e000000) //!< Bit mask for CCM_CS1CDR_ESAI_CLK_PODF. + +//! @brief Get value of CCM_CS1CDR_ESAI_CLK_PODF from a register value. +#define BG_CCM_CS1CDR_ESAI_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS1CDR_ESAI_CLK_PODF) >> BP_CCM_CS1CDR_ESAI_CLK_PODF) + +//! @brief Format value for bitfield CCM_CS1CDR_ESAI_CLK_PODF. +#define BF_CCM_CS1CDR_ESAI_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS1CDR_ESAI_CLK_PODF) & BM_CCM_CS1CDR_ESAI_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ESAI_CLK_PODF field to a new value. +#define BW_CCM_CS1CDR_ESAI_CLK_PODF(v) (HW_CCM_CS1CDR_WR((HW_CCM_CS1CDR_RD() & ~BM_CCM_CS1CDR_ESAI_CLK_PODF) | BF_CCM_CS1CDR_ESAI_CLK_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CS2CDR - CCM SSI2 Clock Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CS2CDR - CCM SSI2 Clock Divider Register (RW) + * + * Reset value: 0x000736c1 + * + * The figure below represents the CCM SSI2, LDB Clock Divider Register (CS2CDR). The CS2CDR + * register contains bits to control the ssi2 clock generation dividers, and ldb serial clocks + * select. The table below provides its field descriptions. + */ +typedef union _hw_ccm_cs2cdr +{ + reg32_t U; + struct _hw_ccm_cs2cdr_bitfields + { + unsigned SSI2_CLK_PODF : 6; //!< [5:0] Divider for ssi2 clock podf. + unsigned SSI2_CLK_PRED : 3; //!< [8:6] Divider for ssi2 clock pred. + unsigned LDB_DI0_CLK_SEL : 3; //!< [11:9] Selector for ldb_di1 clock multiplexer + unsigned LDB_DI1_CLK_SEL : 3; //!< [14:12] Selector for ldb_di1 clock multiplexer + unsigned RESERVED0 : 1; //!< [15] Reserved + unsigned ENFC_CLK_SEL : 2; //!< [17:16] Selector for enfc clock multiplexer + unsigned ENFC_CLK_PRED : 3; //!< [20:18] Divider for enfc clock pred divider. + unsigned ENFC_CLK_PODF : 6; //!< [26:21] Divider for enfc clock divider. + unsigned RESERVED1 : 5; //!< [31:27] Reserved + } B; +} hw_ccm_cs2cdr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CS2CDR register + */ +//@{ +#define HW_CCM_CS2CDR_ADDR (REGS_CCM_BASE + 0x2c) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CS2CDR (*(volatile hw_ccm_cs2cdr_t *) HW_CCM_CS2CDR_ADDR) +#define HW_CCM_CS2CDR_RD() (HW_CCM_CS2CDR.U) +#define HW_CCM_CS2CDR_WR(v) (HW_CCM_CS2CDR.U = (v)) +#define HW_CCM_CS2CDR_SET(v) (HW_CCM_CS2CDR_WR(HW_CCM_CS2CDR_RD() | (v))) +#define HW_CCM_CS2CDR_CLR(v) (HW_CCM_CS2CDR_WR(HW_CCM_CS2CDR_RD() & ~(v))) +#define HW_CCM_CS2CDR_TOG(v) (HW_CCM_CS2CDR_WR(HW_CCM_CS2CDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CS2CDR bitfields + */ + +/*! @name Register CCM_CS2CDR, field SSI2_CLK_PODF[5:0] (RW) + * + * Divider for ssi2 clock podf. The input clock to this divider should be lower than 300Mhz, the + * predivider can be used to achieve this. + * + * Values: + * - 000000 - divide by 1 + * - 111111 - divide by 2^6 + */ +//@{ +#define BP_CCM_CS2CDR_SSI2_CLK_PODF (0) //!< Bit position for CCM_CS2CDR_SSI2_CLK_PODF. +#define BM_CCM_CS2CDR_SSI2_CLK_PODF (0x0000003f) //!< Bit mask for CCM_CS2CDR_SSI2_CLK_PODF. + +//! @brief Get value of CCM_CS2CDR_SSI2_CLK_PODF from a register value. +#define BG_CCM_CS2CDR_SSI2_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS2CDR_SSI2_CLK_PODF) >> BP_CCM_CS2CDR_SSI2_CLK_PODF) + +//! @brief Format value for bitfield CCM_CS2CDR_SSI2_CLK_PODF. +#define BF_CCM_CS2CDR_SSI2_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS2CDR_SSI2_CLK_PODF) & BM_CCM_CS2CDR_SSI2_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI2_CLK_PODF field to a new value. +#define BW_CCM_CS2CDR_SSI2_CLK_PODF(v) (HW_CCM_CS2CDR_WR((HW_CCM_CS2CDR_RD() & ~BM_CCM_CS2CDR_SSI2_CLK_PODF) | BF_CCM_CS2CDR_SSI2_CLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CS2CDR, field SSI2_CLK_PRED[8:6] (RW) + * + * Divider for ssi2 clock pred. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CS2CDR_SSI2_CLK_PRED (6) //!< Bit position for CCM_CS2CDR_SSI2_CLK_PRED. +#define BM_CCM_CS2CDR_SSI2_CLK_PRED (0x000001c0) //!< Bit mask for CCM_CS2CDR_SSI2_CLK_PRED. + +//! @brief Get value of CCM_CS2CDR_SSI2_CLK_PRED from a register value. +#define BG_CCM_CS2CDR_SSI2_CLK_PRED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS2CDR_SSI2_CLK_PRED) >> BP_CCM_CS2CDR_SSI2_CLK_PRED) + +//! @brief Format value for bitfield CCM_CS2CDR_SSI2_CLK_PRED. +#define BF_CCM_CS2CDR_SSI2_CLK_PRED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS2CDR_SSI2_CLK_PRED) & BM_CCM_CS2CDR_SSI2_CLK_PRED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSI2_CLK_PRED field to a new value. +#define BW_CCM_CS2CDR_SSI2_CLK_PRED(v) (HW_CCM_CS2CDR_WR((HW_CCM_CS2CDR_RD() & ~BM_CCM_CS2CDR_SSI2_CLK_PRED) | BF_CCM_CS2CDR_SSI2_CLK_PRED(v))) +#endif +//@} + +/*! @name Register CCM_CS2CDR, field LDB_DI0_CLK_SEL[11:9] (RW) + * + * Selector for ldb_di1 clock multiplexer + * + * Values: + * - 000 - pll5 clock + * - 001 - pll2 307M PFD (default) + * - 010 - pll2 396M PFD + * - 011 - MMDC_CH1 clock + * - 100 - pll3 clock + * - 101 - 111 Resrticted + */ +//@{ +#define BP_CCM_CS2CDR_LDB_DI0_CLK_SEL (9) //!< Bit position for CCM_CS2CDR_LDB_DI0_CLK_SEL. +#define BM_CCM_CS2CDR_LDB_DI0_CLK_SEL (0x00000e00) //!< Bit mask for CCM_CS2CDR_LDB_DI0_CLK_SEL. + +//! @brief Get value of CCM_CS2CDR_LDB_DI0_CLK_SEL from a register value. +#define BG_CCM_CS2CDR_LDB_DI0_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS2CDR_LDB_DI0_CLK_SEL) >> BP_CCM_CS2CDR_LDB_DI0_CLK_SEL) + +//! @brief Format value for bitfield CCM_CS2CDR_LDB_DI0_CLK_SEL. +#define BF_CCM_CS2CDR_LDB_DI0_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS2CDR_LDB_DI0_CLK_SEL) & BM_CCM_CS2CDR_LDB_DI0_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LDB_DI0_CLK_SEL field to a new value. +#define BW_CCM_CS2CDR_LDB_DI0_CLK_SEL(v) (HW_CCM_CS2CDR_WR((HW_CCM_CS2CDR_RD() & ~BM_CCM_CS2CDR_LDB_DI0_CLK_SEL) | BF_CCM_CS2CDR_LDB_DI0_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CS2CDR, field LDB_DI1_CLK_SEL[14:12] (RW) + * + * Selector for ldb_di1 clock multiplexer + * + * Values: + * - 000 - pll5 clock + * - 001 - pll2 307M PFD (default) + * - 010 - pll2 396M PFD + * - 011 - MMDC_CH1 clock + * - 100 - pll3 clock + * - 101 - 111 Resrticted + */ +//@{ +#define BP_CCM_CS2CDR_LDB_DI1_CLK_SEL (12) //!< Bit position for CCM_CS2CDR_LDB_DI1_CLK_SEL. +#define BM_CCM_CS2CDR_LDB_DI1_CLK_SEL (0x00007000) //!< Bit mask for CCM_CS2CDR_LDB_DI1_CLK_SEL. + +//! @brief Get value of CCM_CS2CDR_LDB_DI1_CLK_SEL from a register value. +#define BG_CCM_CS2CDR_LDB_DI1_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS2CDR_LDB_DI1_CLK_SEL) >> BP_CCM_CS2CDR_LDB_DI1_CLK_SEL) + +//! @brief Format value for bitfield CCM_CS2CDR_LDB_DI1_CLK_SEL. +#define BF_CCM_CS2CDR_LDB_DI1_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS2CDR_LDB_DI1_CLK_SEL) & BM_CCM_CS2CDR_LDB_DI1_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LDB_DI1_CLK_SEL field to a new value. +#define BW_CCM_CS2CDR_LDB_DI1_CLK_SEL(v) (HW_CCM_CS2CDR_WR((HW_CCM_CS2CDR_RD() & ~BM_CCM_CS2CDR_LDB_DI1_CLK_SEL) | BF_CCM_CS2CDR_LDB_DI1_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CS2CDR, field ENFC_CLK_SEL[17:16] (RW) + * + * Selector for enfc clock multiplexer + * + * Values: + * - 00 - pll2 307M PDF (default) + * - 01 - pll2 clock + * - 10 - pll3 clock + * - 11 - pll2 396M PFD + */ +//@{ +#define BP_CCM_CS2CDR_ENFC_CLK_SEL (16) //!< Bit position for CCM_CS2CDR_ENFC_CLK_SEL. +#define BM_CCM_CS2CDR_ENFC_CLK_SEL (0x00030000) //!< Bit mask for CCM_CS2CDR_ENFC_CLK_SEL. + +//! @brief Get value of CCM_CS2CDR_ENFC_CLK_SEL from a register value. +#define BG_CCM_CS2CDR_ENFC_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS2CDR_ENFC_CLK_SEL) >> BP_CCM_CS2CDR_ENFC_CLK_SEL) + +//! @brief Format value for bitfield CCM_CS2CDR_ENFC_CLK_SEL. +#define BF_CCM_CS2CDR_ENFC_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS2CDR_ENFC_CLK_SEL) & BM_CCM_CS2CDR_ENFC_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENFC_CLK_SEL field to a new value. +#define BW_CCM_CS2CDR_ENFC_CLK_SEL(v) (HW_CCM_CS2CDR_WR((HW_CCM_CS2CDR_RD() & ~BM_CCM_CS2CDR_ENFC_CLK_SEL) | BF_CCM_CS2CDR_ENFC_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CS2CDR, field ENFC_CLK_PRED[20:18] (RW) + * + * Divider for enfc clock pred divider. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CS2CDR_ENFC_CLK_PRED (18) //!< Bit position for CCM_CS2CDR_ENFC_CLK_PRED. +#define BM_CCM_CS2CDR_ENFC_CLK_PRED (0x001c0000) //!< Bit mask for CCM_CS2CDR_ENFC_CLK_PRED. + +//! @brief Get value of CCM_CS2CDR_ENFC_CLK_PRED from a register value. +#define BG_CCM_CS2CDR_ENFC_CLK_PRED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS2CDR_ENFC_CLK_PRED) >> BP_CCM_CS2CDR_ENFC_CLK_PRED) + +//! @brief Format value for bitfield CCM_CS2CDR_ENFC_CLK_PRED. +#define BF_CCM_CS2CDR_ENFC_CLK_PRED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS2CDR_ENFC_CLK_PRED) & BM_CCM_CS2CDR_ENFC_CLK_PRED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENFC_CLK_PRED field to a new value. +#define BW_CCM_CS2CDR_ENFC_CLK_PRED(v) (HW_CCM_CS2CDR_WR((HW_CCM_CS2CDR_RD() & ~BM_CCM_CS2CDR_ENFC_CLK_PRED) | BF_CCM_CS2CDR_ENFC_CLK_PRED(v))) +#endif +//@} + +/*! @name Register CCM_CS2CDR, field ENFC_CLK_PODF[26:21] (RW) + * + * Divider for enfc clock divider. + * + * Values: + * - 000000 - divide by 1 + * - 000001 - divide by 2 (default) + * - 111111 - divide by 2^6 + */ +//@{ +#define BP_CCM_CS2CDR_ENFC_CLK_PODF (21) //!< Bit position for CCM_CS2CDR_ENFC_CLK_PODF. +#define BM_CCM_CS2CDR_ENFC_CLK_PODF (0x07e00000) //!< Bit mask for CCM_CS2CDR_ENFC_CLK_PODF. + +//! @brief Get value of CCM_CS2CDR_ENFC_CLK_PODF from a register value. +#define BG_CCM_CS2CDR_ENFC_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CS2CDR_ENFC_CLK_PODF) >> BP_CCM_CS2CDR_ENFC_CLK_PODF) + +//! @brief Format value for bitfield CCM_CS2CDR_ENFC_CLK_PODF. +#define BF_CCM_CS2CDR_ENFC_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CS2CDR_ENFC_CLK_PODF) & BM_CCM_CS2CDR_ENFC_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENFC_CLK_PODF field to a new value. +#define BW_CCM_CS2CDR_ENFC_CLK_PODF(v) (HW_CCM_CS2CDR_WR((HW_CCM_CS2CDR_RD() & ~BM_CCM_CS2CDR_ENFC_CLK_PODF) | BF_CCM_CS2CDR_ENFC_CLK_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CDCDR - CCM D1 Clock Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CDCDR - CCM D1 Clock Divider Register (RW) + * + * Reset value: 0x33f71f92 + * + * The figure below represents the CCM DI Clock Divider Register (CDCDR). The table below provides + * its field descriptions. + */ +typedef union _hw_ccm_cdcdr +{ + reg32_t U; + struct _hw_ccm_cdcdr_bitfields + { + unsigned RESERVED0 : 7; //!< [6:0] Reserved + unsigned SPDIF1_CLK_SEL : 2; //!< [8:7] Selector for spdif1 clock multiplexer + unsigned SPDIF1_CLK_PODF : 3; //!< [11:9] Divider for spdif1 clock podf. + unsigned SPDIF1_CLK_PRED : 3; //!< [14:12] Divider for spdif1 clock pred. + unsigned RESERVED1 : 5; //!< [19:15] Reserved. + unsigned SPDIF0_CLK_SEL : 2; //!< [21:20] Selector for spdif0 clock multiplexer + unsigned SPDIF0_CLK_PODF : 3; //!< [24:22] Divider for spdif0 clock podf. + unsigned SPDIF0_CLK_PRED : 3; //!< [27:25] Divider for spdif0 clock pred. + unsigned HSI_TX_CLK_SEL : 1; //!< [28] Selector for hsi_tx clock multiplexer + unsigned HSI_TX_PODF : 3; //!< [31:29] Divider for hsi_tx clock podf. + } B; +} hw_ccm_cdcdr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CDCDR register + */ +//@{ +#define HW_CCM_CDCDR_ADDR (REGS_CCM_BASE + 0x30) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CDCDR (*(volatile hw_ccm_cdcdr_t *) HW_CCM_CDCDR_ADDR) +#define HW_CCM_CDCDR_RD() (HW_CCM_CDCDR.U) +#define HW_CCM_CDCDR_WR(v) (HW_CCM_CDCDR.U = (v)) +#define HW_CCM_CDCDR_SET(v) (HW_CCM_CDCDR_WR(HW_CCM_CDCDR_RD() | (v))) +#define HW_CCM_CDCDR_CLR(v) (HW_CCM_CDCDR_WR(HW_CCM_CDCDR_RD() & ~(v))) +#define HW_CCM_CDCDR_TOG(v) (HW_CCM_CDCDR_WR(HW_CCM_CDCDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CDCDR bitfields + */ + +/*! @name Register CCM_CDCDR, field SPDIF1_CLK_SEL[8:7] (RW) + * + * Selector for spdif1 clock multiplexer + * + * Values: + * - 00 - derive clock from pll4 divided clock + * - 01 - derive clock from 508M PFD clock + * - 11 - derive clock from pll3 clock + */ +//@{ +#define BP_CCM_CDCDR_SPDIF1_CLK_SEL (7) //!< Bit position for CCM_CDCDR_SPDIF1_CLK_SEL. +#define BM_CCM_CDCDR_SPDIF1_CLK_SEL (0x00000180) //!< Bit mask for CCM_CDCDR_SPDIF1_CLK_SEL. + +//! @brief Get value of CCM_CDCDR_SPDIF1_CLK_SEL from a register value. +#define BG_CCM_CDCDR_SPDIF1_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDCDR_SPDIF1_CLK_SEL) >> BP_CCM_CDCDR_SPDIF1_CLK_SEL) + +//! @brief Format value for bitfield CCM_CDCDR_SPDIF1_CLK_SEL. +#define BF_CCM_CDCDR_SPDIF1_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CDCDR_SPDIF1_CLK_SEL) & BM_CCM_CDCDR_SPDIF1_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SPDIF1_CLK_SEL field to a new value. +#define BW_CCM_CDCDR_SPDIF1_CLK_SEL(v) (HW_CCM_CDCDR_WR((HW_CCM_CDCDR_RD() & ~BM_CCM_CDCDR_SPDIF1_CLK_SEL) | BF_CCM_CDCDR_SPDIF1_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CDCDR, field SPDIF1_CLK_PODF[11:9] (RW) + * + * Divider for spdif1 clock podf. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CDCDR_SPDIF1_CLK_PODF (9) //!< Bit position for CCM_CDCDR_SPDIF1_CLK_PODF. +#define BM_CCM_CDCDR_SPDIF1_CLK_PODF (0x00000e00) //!< Bit mask for CCM_CDCDR_SPDIF1_CLK_PODF. + +//! @brief Get value of CCM_CDCDR_SPDIF1_CLK_PODF from a register value. +#define BG_CCM_CDCDR_SPDIF1_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDCDR_SPDIF1_CLK_PODF) >> BP_CCM_CDCDR_SPDIF1_CLK_PODF) + +//! @brief Format value for bitfield CCM_CDCDR_SPDIF1_CLK_PODF. +#define BF_CCM_CDCDR_SPDIF1_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CDCDR_SPDIF1_CLK_PODF) & BM_CCM_CDCDR_SPDIF1_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SPDIF1_CLK_PODF field to a new value. +#define BW_CCM_CDCDR_SPDIF1_CLK_PODF(v) (HW_CCM_CDCDR_WR((HW_CCM_CDCDR_RD() & ~BM_CCM_CDCDR_SPDIF1_CLK_PODF) | BF_CCM_CDCDR_SPDIF1_CLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CDCDR, field SPDIF1_CLK_PRED[14:12] (RW) + * + * Divider for spdif1 clock pred. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 (do not use with high input frequencies) + * - 001 - divide by 2 + * - 010 - divide by 3 (default) + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CDCDR_SPDIF1_CLK_PRED (12) //!< Bit position for CCM_CDCDR_SPDIF1_CLK_PRED. +#define BM_CCM_CDCDR_SPDIF1_CLK_PRED (0x00007000) //!< Bit mask for CCM_CDCDR_SPDIF1_CLK_PRED. + +//! @brief Get value of CCM_CDCDR_SPDIF1_CLK_PRED from a register value. +#define BG_CCM_CDCDR_SPDIF1_CLK_PRED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDCDR_SPDIF1_CLK_PRED) >> BP_CCM_CDCDR_SPDIF1_CLK_PRED) + +//! @brief Format value for bitfield CCM_CDCDR_SPDIF1_CLK_PRED. +#define BF_CCM_CDCDR_SPDIF1_CLK_PRED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CDCDR_SPDIF1_CLK_PRED) & BM_CCM_CDCDR_SPDIF1_CLK_PRED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SPDIF1_CLK_PRED field to a new value. +#define BW_CCM_CDCDR_SPDIF1_CLK_PRED(v) (HW_CCM_CDCDR_WR((HW_CCM_CDCDR_RD() & ~BM_CCM_CDCDR_SPDIF1_CLK_PRED) | BF_CCM_CDCDR_SPDIF1_CLK_PRED(v))) +#endif +//@} + +/*! @name Register CCM_CDCDR, field SPDIF0_CLK_SEL[21:20] (RW) + * + * Selector for spdif0 clock multiplexer + * + * Values: + * - 00 - derive clock from pll4 divided clock + * - 01 - derive clock from 508M PFD clock + * - 11 - derive clock from pll3 clock + */ +//@{ +#define BP_CCM_CDCDR_SPDIF0_CLK_SEL (20) //!< Bit position for CCM_CDCDR_SPDIF0_CLK_SEL. +#define BM_CCM_CDCDR_SPDIF0_CLK_SEL (0x00300000) //!< Bit mask for CCM_CDCDR_SPDIF0_CLK_SEL. + +//! @brief Get value of CCM_CDCDR_SPDIF0_CLK_SEL from a register value. +#define BG_CCM_CDCDR_SPDIF0_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDCDR_SPDIF0_CLK_SEL) >> BP_CCM_CDCDR_SPDIF0_CLK_SEL) + +//! @brief Format value for bitfield CCM_CDCDR_SPDIF0_CLK_SEL. +#define BF_CCM_CDCDR_SPDIF0_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CDCDR_SPDIF0_CLK_SEL) & BM_CCM_CDCDR_SPDIF0_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SPDIF0_CLK_SEL field to a new value. +#define BW_CCM_CDCDR_SPDIF0_CLK_SEL(v) (HW_CCM_CDCDR_WR((HW_CCM_CDCDR_RD() & ~BM_CCM_CDCDR_SPDIF0_CLK_SEL) | BF_CCM_CDCDR_SPDIF0_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CDCDR, field SPDIF0_CLK_PODF[24:22] (RW) + * + * Divider for spdif0 clock podf. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CDCDR_SPDIF0_CLK_PODF (22) //!< Bit position for CCM_CDCDR_SPDIF0_CLK_PODF. +#define BM_CCM_CDCDR_SPDIF0_CLK_PODF (0x01c00000) //!< Bit mask for CCM_CDCDR_SPDIF0_CLK_PODF. + +//! @brief Get value of CCM_CDCDR_SPDIF0_CLK_PODF from a register value. +#define BG_CCM_CDCDR_SPDIF0_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDCDR_SPDIF0_CLK_PODF) >> BP_CCM_CDCDR_SPDIF0_CLK_PODF) + +//! @brief Format value for bitfield CCM_CDCDR_SPDIF0_CLK_PODF. +#define BF_CCM_CDCDR_SPDIF0_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CDCDR_SPDIF0_CLK_PODF) & BM_CCM_CDCDR_SPDIF0_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SPDIF0_CLK_PODF field to a new value. +#define BW_CCM_CDCDR_SPDIF0_CLK_PODF(v) (HW_CCM_CDCDR_WR((HW_CCM_CDCDR_RD() & ~BM_CCM_CDCDR_SPDIF0_CLK_PODF) | BF_CCM_CDCDR_SPDIF0_CLK_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CDCDR, field SPDIF0_CLK_PRED[27:25] (RW) + * + * Divider for spdif0 clock pred. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 (do not use with high input frequencies) + * - 001 - divide by 2 + * - 010 - divide by 3 (default) + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CDCDR_SPDIF0_CLK_PRED (25) //!< Bit position for CCM_CDCDR_SPDIF0_CLK_PRED. +#define BM_CCM_CDCDR_SPDIF0_CLK_PRED (0x0e000000) //!< Bit mask for CCM_CDCDR_SPDIF0_CLK_PRED. + +//! @brief Get value of CCM_CDCDR_SPDIF0_CLK_PRED from a register value. +#define BG_CCM_CDCDR_SPDIF0_CLK_PRED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDCDR_SPDIF0_CLK_PRED) >> BP_CCM_CDCDR_SPDIF0_CLK_PRED) + +//! @brief Format value for bitfield CCM_CDCDR_SPDIF0_CLK_PRED. +#define BF_CCM_CDCDR_SPDIF0_CLK_PRED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CDCDR_SPDIF0_CLK_PRED) & BM_CCM_CDCDR_SPDIF0_CLK_PRED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SPDIF0_CLK_PRED field to a new value. +#define BW_CCM_CDCDR_SPDIF0_CLK_PRED(v) (HW_CCM_CDCDR_WR((HW_CCM_CDCDR_RD() & ~BM_CCM_CDCDR_SPDIF0_CLK_PRED) | BF_CCM_CDCDR_SPDIF0_CLK_PRED(v))) +#endif +//@} + +/*! @name Register CCM_CDCDR, field HSI_TX_CLK_SEL[28] (RW) + * + * Selector for hsi_tx clock multiplexer + * + * Values: + * - 0 - derive from pll3 120M clock (default) + * - 1 - derive from pll2 396M PDF + */ +//@{ +#define BP_CCM_CDCDR_HSI_TX_CLK_SEL (28) //!< Bit position for CCM_CDCDR_HSI_TX_CLK_SEL. +#define BM_CCM_CDCDR_HSI_TX_CLK_SEL (0x10000000) //!< Bit mask for CCM_CDCDR_HSI_TX_CLK_SEL. + +//! @brief Get value of CCM_CDCDR_HSI_TX_CLK_SEL from a register value. +#define BG_CCM_CDCDR_HSI_TX_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDCDR_HSI_TX_CLK_SEL) >> BP_CCM_CDCDR_HSI_TX_CLK_SEL) + +//! @brief Format value for bitfield CCM_CDCDR_HSI_TX_CLK_SEL. +#define BF_CCM_CDCDR_HSI_TX_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CDCDR_HSI_TX_CLK_SEL) & BM_CCM_CDCDR_HSI_TX_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HSI_TX_CLK_SEL field to a new value. +#define BW_CCM_CDCDR_HSI_TX_CLK_SEL(v) (HW_CCM_CDCDR_WR((HW_CCM_CDCDR_RD() & ~BM_CCM_CDCDR_HSI_TX_CLK_SEL) | BF_CCM_CDCDR_HSI_TX_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CDCDR, field HSI_TX_PODF[31:29] (RW) + * + * Divider for hsi_tx clock podf. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 (default) + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CDCDR_HSI_TX_PODF (29) //!< Bit position for CCM_CDCDR_HSI_TX_PODF. +#define BM_CCM_CDCDR_HSI_TX_PODF (0xe0000000) //!< Bit mask for CCM_CDCDR_HSI_TX_PODF. + +//! @brief Get value of CCM_CDCDR_HSI_TX_PODF from a register value. +#define BG_CCM_CDCDR_HSI_TX_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDCDR_HSI_TX_PODF) >> BP_CCM_CDCDR_HSI_TX_PODF) + +//! @brief Format value for bitfield CCM_CDCDR_HSI_TX_PODF. +#define BF_CCM_CDCDR_HSI_TX_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CDCDR_HSI_TX_PODF) & BM_CCM_CDCDR_HSI_TX_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HSI_TX_PODF field to a new value. +#define BW_CCM_CDCDR_HSI_TX_PODF(v) (HW_CCM_CDCDR_WR((HW_CCM_CDCDR_RD() & ~BM_CCM_CDCDR_HSI_TX_PODF) | BF_CCM_CDCDR_HSI_TX_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CHSCCDR - CCM HSC Clock Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CHSCCDR - CCM HSC Clock Divider Register (RW) + * + * Reset value: 0x0002a150 + * + * The figure below represents the CCM IPU1 DI Clock Divider Register (CHSCCDR). The CHSCCDR + * register contains bits to control the ipu di clock generation dividers. The table below provides + * its field descriptions. + */ +typedef union _hw_ccm_chsccdr +{ + reg32_t U; + struct _hw_ccm_chsccdr_bitfields + { + unsigned IPU1_DI0_CLK_SEL : 3; //!< [2:0] Selector for ipu1 di0 root clock multiplexer + unsigned IPU1_DI0_PODF : 3; //!< [5:3] Divider for ipu1_di0 clock divider. + unsigned IPU1_DI0_PRE_CLK_SEL : 3; //!< [8:6] Selector for ipu1 di0 root clock pre-multiplexer + unsigned IPU1_DI1_CLK_SEL : 3; //!< [11:9] Selector for ipu1 di1 root clock multiplexer + unsigned IPU1_DI1_PODF : 3; //!< [14:12] Divider for ipu1_di clock divider. + unsigned IPU1_DI1_PRE_CLK_SEL : 3; //!< [17:15] Selector for ipu1 di1 root clock pre-multiplexer + unsigned RESERVED0 : 14; //!< [31:18] Reserved + } B; +} hw_ccm_chsccdr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CHSCCDR register + */ +//@{ +#define HW_CCM_CHSCCDR_ADDR (REGS_CCM_BASE + 0x34) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CHSCCDR (*(volatile hw_ccm_chsccdr_t *) HW_CCM_CHSCCDR_ADDR) +#define HW_CCM_CHSCCDR_RD() (HW_CCM_CHSCCDR.U) +#define HW_CCM_CHSCCDR_WR(v) (HW_CCM_CHSCCDR.U = (v)) +#define HW_CCM_CHSCCDR_SET(v) (HW_CCM_CHSCCDR_WR(HW_CCM_CHSCCDR_RD() | (v))) +#define HW_CCM_CHSCCDR_CLR(v) (HW_CCM_CHSCCDR_WR(HW_CCM_CHSCCDR_RD() & ~(v))) +#define HW_CCM_CHSCCDR_TOG(v) (HW_CCM_CHSCCDR_WR(HW_CCM_CHSCCDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CHSCCDR bitfields + */ + +/*! @name Register CCM_CHSCCDR, field IPU1_DI0_CLK_SEL[2:0] (RW) + * + * Selector for ipu1 di0 root clock multiplexer + * + * Values: + * - 000 - derive clock from divided pre-muxed ipu1 di0 clock (default) + * - 001 - derive clock from ipp_di0_clk + * - 010 - derive clock from ipp_di1_clk + * - 011 - derive clock from ldb_di0_clk + * - 100 - derive clock from ldb_di1_clk + * - 101-111 - Restricted + */ +//@{ +#define BP_CCM_CHSCCDR_IPU1_DI0_CLK_SEL (0) //!< Bit position for CCM_CHSCCDR_IPU1_DI0_CLK_SEL. +#define BM_CCM_CHSCCDR_IPU1_DI0_CLK_SEL (0x00000007) //!< Bit mask for CCM_CHSCCDR_IPU1_DI0_CLK_SEL. + +//! @brief Get value of CCM_CHSCCDR_IPU1_DI0_CLK_SEL from a register value. +#define BG_CCM_CHSCCDR_IPU1_DI0_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CHSCCDR_IPU1_DI0_CLK_SEL) >> BP_CCM_CHSCCDR_IPU1_DI0_CLK_SEL) + +//! @brief Format value for bitfield CCM_CHSCCDR_IPU1_DI0_CLK_SEL. +#define BF_CCM_CHSCCDR_IPU1_DI0_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CHSCCDR_IPU1_DI0_CLK_SEL) & BM_CCM_CHSCCDR_IPU1_DI0_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPU1_DI0_CLK_SEL field to a new value. +#define BW_CCM_CHSCCDR_IPU1_DI0_CLK_SEL(v) (HW_CCM_CHSCCDR_WR((HW_CCM_CHSCCDR_RD() & ~BM_CCM_CHSCCDR_IPU1_DI0_CLK_SEL) | BF_CCM_CHSCCDR_IPU1_DI0_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CHSCCDR, field IPU1_DI0_PODF[5:3] (RW) + * + * Divider for ipu1_di0 clock divider. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 (default) + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CHSCCDR_IPU1_DI0_PODF (3) //!< Bit position for CCM_CHSCCDR_IPU1_DI0_PODF. +#define BM_CCM_CHSCCDR_IPU1_DI0_PODF (0x00000038) //!< Bit mask for CCM_CHSCCDR_IPU1_DI0_PODF. + +//! @brief Get value of CCM_CHSCCDR_IPU1_DI0_PODF from a register value. +#define BG_CCM_CHSCCDR_IPU1_DI0_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CHSCCDR_IPU1_DI0_PODF) >> BP_CCM_CHSCCDR_IPU1_DI0_PODF) + +//! @brief Format value for bitfield CCM_CHSCCDR_IPU1_DI0_PODF. +#define BF_CCM_CHSCCDR_IPU1_DI0_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CHSCCDR_IPU1_DI0_PODF) & BM_CCM_CHSCCDR_IPU1_DI0_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPU1_DI0_PODF field to a new value. +#define BW_CCM_CHSCCDR_IPU1_DI0_PODF(v) (HW_CCM_CHSCCDR_WR((HW_CCM_CHSCCDR_RD() & ~BM_CCM_CHSCCDR_IPU1_DI0_PODF) | BF_CCM_CHSCCDR_IPU1_DI0_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CHSCCDR, field IPU1_DI0_PRE_CLK_SEL[8:6] (RW) + * + * Selector for ipu1 di0 root clock pre-multiplexer + * + * Values: + * - 000 - derive clock from mmdc_ch0 clock + * - 001 - derive clock from pll3 + * - 010 - derive clock from pll5 + * - 011 - derive clock from 307M PFD + * - 100 - derive clock from 396M PFD + * - 101 - derive clock from 540M PFD + * - 110-111 - Restricted + */ +//@{ +#define BP_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL (6) //!< Bit position for CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL. +#define BM_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL (0x000001c0) //!< Bit mask for CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL. + +//! @brief Get value of CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL from a register value. +#define BG_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL) >> BP_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL) + +//! @brief Format value for bitfield CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL. +#define BF_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL) & BM_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPU1_DI0_PRE_CLK_SEL field to a new value. +#define BW_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL(v) (HW_CCM_CHSCCDR_WR((HW_CCM_CHSCCDR_RD() & ~BM_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL) | BF_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CHSCCDR, field IPU1_DI1_CLK_SEL[11:9] (RW) + * + * Selector for ipu1 di1 root clock multiplexer + * + * Values: + * - 000 - derive clock from divided pre-muxed ipu1 di1 clock (default) + * - 001 - derive clock from ipp_di0_clk + * - 010 - derive clock from ipp_di1_clk + * - 011 - derive clock from ldb_di0_clk + * - 100 - derive clock from ldb_di1_clk + * - 101-111 - Restricted + */ +//@{ +#define BP_CCM_CHSCCDR_IPU1_DI1_CLK_SEL (9) //!< Bit position for CCM_CHSCCDR_IPU1_DI1_CLK_SEL. +#define BM_CCM_CHSCCDR_IPU1_DI1_CLK_SEL (0x00000e00) //!< Bit mask for CCM_CHSCCDR_IPU1_DI1_CLK_SEL. + +//! @brief Get value of CCM_CHSCCDR_IPU1_DI1_CLK_SEL from a register value. +#define BG_CCM_CHSCCDR_IPU1_DI1_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CHSCCDR_IPU1_DI1_CLK_SEL) >> BP_CCM_CHSCCDR_IPU1_DI1_CLK_SEL) + +//! @brief Format value for bitfield CCM_CHSCCDR_IPU1_DI1_CLK_SEL. +#define BF_CCM_CHSCCDR_IPU1_DI1_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CHSCCDR_IPU1_DI1_CLK_SEL) & BM_CCM_CHSCCDR_IPU1_DI1_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPU1_DI1_CLK_SEL field to a new value. +#define BW_CCM_CHSCCDR_IPU1_DI1_CLK_SEL(v) (HW_CCM_CHSCCDR_WR((HW_CCM_CHSCCDR_RD() & ~BM_CCM_CHSCCDR_IPU1_DI1_CLK_SEL) | BF_CCM_CHSCCDR_IPU1_DI1_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CHSCCDR, field IPU1_DI1_PODF[14:12] (RW) + * + * Divider for ipu1_di clock divider. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 (default) + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CHSCCDR_IPU1_DI1_PODF (12) //!< Bit position for CCM_CHSCCDR_IPU1_DI1_PODF. +#define BM_CCM_CHSCCDR_IPU1_DI1_PODF (0x00007000) //!< Bit mask for CCM_CHSCCDR_IPU1_DI1_PODF. + +//! @brief Get value of CCM_CHSCCDR_IPU1_DI1_PODF from a register value. +#define BG_CCM_CHSCCDR_IPU1_DI1_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CHSCCDR_IPU1_DI1_PODF) >> BP_CCM_CHSCCDR_IPU1_DI1_PODF) + +//! @brief Format value for bitfield CCM_CHSCCDR_IPU1_DI1_PODF. +#define BF_CCM_CHSCCDR_IPU1_DI1_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CHSCCDR_IPU1_DI1_PODF) & BM_CCM_CHSCCDR_IPU1_DI1_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPU1_DI1_PODF field to a new value. +#define BW_CCM_CHSCCDR_IPU1_DI1_PODF(v) (HW_CCM_CHSCCDR_WR((HW_CCM_CHSCCDR_RD() & ~BM_CCM_CHSCCDR_IPU1_DI1_PODF) | BF_CCM_CHSCCDR_IPU1_DI1_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CHSCCDR, field IPU1_DI1_PRE_CLK_SEL[17:15] (RW) + * + * Selector for ipu1 di1 root clock pre-multiplexer + * + * Values: + * - 000 - derive clock from mmdc_ch0 clock + * - 001 - derive clock from pll3 + * - 010 - derive clock from pll5 + * - 011 - derive clock from 307M PFD + * - 100 - derive clock from 396M PFD + * - 101 - derive clock from 540M PFD + * - 110-111 - Restricted + */ +//@{ +#define BP_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL (15) //!< Bit position for CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL. +#define BM_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL (0x00038000) //!< Bit mask for CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL. + +//! @brief Get value of CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL from a register value. +#define BG_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL) >> BP_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL) + +//! @brief Format value for bitfield CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL. +#define BF_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL) & BM_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPU1_DI1_PRE_CLK_SEL field to a new value. +#define BW_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL(v) (HW_CCM_CHSCCDR_WR((HW_CCM_CHSCCDR_RD() & ~BM_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL) | BF_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CSCDR2 - CCM Serial Clock Divider Register 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CSCDR2 - CCM Serial Clock Divider Register 2 (RW) + * + * Reset value: 0x00029b48 + * + * The figure below represents the CCM Serial Clock Divider Register 2(CSCDR2). The CSCDR2 register + * contains bits to control the clock generation sub module dividers. The table below provides its + * field descriptions. + */ +typedef union _hw_ccm_cscdr2 +{ + reg32_t U; + struct _hw_ccm_cscdr2_bitfields + { + unsigned LCDIF_PIX_CLK_SEL : 3; //!< [2:0] Selector for lcdif_pix root clock multiplexer + unsigned LCDIF_PIX_PODF : 3; //!< [5:3] Divider for lcdif_pix clock divider. + unsigned LCDIF_PIX_PRE_CLK_SEL : 3; //!< [8:6] Selector for lcdif_pix root clock pre-multiplexer + unsigned EPDC_PIX_CLK_SEL : 3; //!< [11:9] Selector for epdc_pix root clock multiplexer + unsigned EPDC_PIX_PODF : 3; //!< [14:12] Divider for epdc_pix clock divider. + unsigned EPDC_PIX_PRE_CLK_SEL : 3; //!< [17:15] Selector for epdc_pix root clock pre-multiplexer + unsigned RESERVED0 : 1; //!< [18] Reserved + unsigned ECSPI_CLK_PODF : 6; //!< [24:19] Divider for ecspi clock podf. + unsigned RESERVED1 : 7; //!< [31:25] Reserved. + } B; +} hw_ccm_cscdr2_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CSCDR2 register + */ +//@{ +#define HW_CCM_CSCDR2_ADDR (REGS_CCM_BASE + 0x38) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CSCDR2 (*(volatile hw_ccm_cscdr2_t *) HW_CCM_CSCDR2_ADDR) +#define HW_CCM_CSCDR2_RD() (HW_CCM_CSCDR2.U) +#define HW_CCM_CSCDR2_WR(v) (HW_CCM_CSCDR2.U = (v)) +#define HW_CCM_CSCDR2_SET(v) (HW_CCM_CSCDR2_WR(HW_CCM_CSCDR2_RD() | (v))) +#define HW_CCM_CSCDR2_CLR(v) (HW_CCM_CSCDR2_WR(HW_CCM_CSCDR2_RD() & ~(v))) +#define HW_CCM_CSCDR2_TOG(v) (HW_CCM_CSCDR2_WR(HW_CCM_CSCDR2_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CSCDR2 bitfields + */ + +/*! @name Register CCM_CSCDR2, field LCDIF_PIX_CLK_SEL[2:0] (RW) + * + * Selector for lcdif_pix root clock multiplexer + * + * Values: + * - 000 - derive clock from divided pre-muxed lcdif_pix clock (default) + * - 001 - derive clock from ipp_di0_clk + * - 010 - derive clock from ipp_di1_clk + * - 011 - derive clock from ldb_di0_clk + * - 100 - derive clock from ldb_di1_clk + * - 101-111 - Restricted + */ +//@{ +#define BP_CCM_CSCDR2_LCDIF_PIX_CLK_SEL (0) //!< Bit position for CCM_CSCDR2_LCDIF_PIX_CLK_SEL. +#define BM_CCM_CSCDR2_LCDIF_PIX_CLK_SEL (0x00000007) //!< Bit mask for CCM_CSCDR2_LCDIF_PIX_CLK_SEL. + +//! @brief Get value of CCM_CSCDR2_LCDIF_PIX_CLK_SEL from a register value. +#define BG_CCM_CSCDR2_LCDIF_PIX_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR2_LCDIF_PIX_CLK_SEL) >> BP_CCM_CSCDR2_LCDIF_PIX_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCDR2_LCDIF_PIX_CLK_SEL. +#define BF_CCM_CSCDR2_LCDIF_PIX_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR2_LCDIF_PIX_CLK_SEL) & BM_CCM_CSCDR2_LCDIF_PIX_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LCDIF_PIX_CLK_SEL field to a new value. +#define BW_CCM_CSCDR2_LCDIF_PIX_CLK_SEL(v) (HW_CCM_CSCDR2_WR((HW_CCM_CSCDR2_RD() & ~BM_CCM_CSCDR2_LCDIF_PIX_CLK_SEL) | BF_CCM_CSCDR2_LCDIF_PIX_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR2, field LCDIF_PIX_PODF[5:3] (RW) + * + * Divider for lcdif_pix clock divider. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 (default) + */ +//@{ +#define BP_CCM_CSCDR2_LCDIF_PIX_PODF (3) //!< Bit position for CCM_CSCDR2_LCDIF_PIX_PODF. +#define BM_CCM_CSCDR2_LCDIF_PIX_PODF (0x00000038) //!< Bit mask for CCM_CSCDR2_LCDIF_PIX_PODF. + +//! @brief Get value of CCM_CSCDR2_LCDIF_PIX_PODF from a register value. +#define BG_CCM_CSCDR2_LCDIF_PIX_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR2_LCDIF_PIX_PODF) >> BP_CCM_CSCDR2_LCDIF_PIX_PODF) + +//! @brief Format value for bitfield CCM_CSCDR2_LCDIF_PIX_PODF. +#define BF_CCM_CSCDR2_LCDIF_PIX_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR2_LCDIF_PIX_PODF) & BM_CCM_CSCDR2_LCDIF_PIX_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LCDIF_PIX_PODF field to a new value. +#define BW_CCM_CSCDR2_LCDIF_PIX_PODF(v) (HW_CCM_CSCDR2_WR((HW_CCM_CSCDR2_RD() & ~BM_CCM_CSCDR2_LCDIF_PIX_PODF) | BF_CCM_CSCDR2_LCDIF_PIX_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR2, field LCDIF_PIX_PRE_CLK_SEL[8:6] (RW) + * + * Selector for lcdif_pix root clock pre-multiplexer + * + * Values: + * - 000 - derive clock from mmdc_ch0 clock + * - 001 - derive clock from pll3 (default) + * - 010 - derive clock from pll5 + * - 011 - derive clock from 307M PFD + * - 100 - derive clock from 396M PFD + * - 101 - derive clock from 540M PFD + * - 110-111 - Restricted + */ +//@{ +#define BP_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL (6) //!< Bit position for CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL. +#define BM_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL (0x000001c0) //!< Bit mask for CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL. + +//! @brief Get value of CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL from a register value. +#define BG_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL) >> BP_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL. +#define BF_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL) & BM_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LCDIF_PIX_PRE_CLK_SEL field to a new value. +#define BW_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL(v) (HW_CCM_CSCDR2_WR((HW_CCM_CSCDR2_RD() & ~BM_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL) | BF_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR2, field EPDC_PIX_CLK_SEL[11:9] (RW) + * + * Selector for epdc_pix root clock multiplexer + * + * Values: + * - 000 - derive clock from divided pre-muxed epdc_pix clock (default) + * - 001 - derive clock from ipp_di0_clk + * - 010 - derive clock from ipp_di1_clk + * - 011 - derive clock from ldb_di0_clk + * - 100 - derive clock from ldb_di1_clk + * - 101-111 - Restricted + */ +//@{ +#define BP_CCM_CSCDR2_EPDC_PIX_CLK_SEL (9) //!< Bit position for CCM_CSCDR2_EPDC_PIX_CLK_SEL. +#define BM_CCM_CSCDR2_EPDC_PIX_CLK_SEL (0x00000e00) //!< Bit mask for CCM_CSCDR2_EPDC_PIX_CLK_SEL. + +//! @brief Get value of CCM_CSCDR2_EPDC_PIX_CLK_SEL from a register value. +#define BG_CCM_CSCDR2_EPDC_PIX_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR2_EPDC_PIX_CLK_SEL) >> BP_CCM_CSCDR2_EPDC_PIX_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCDR2_EPDC_PIX_CLK_SEL. +#define BF_CCM_CSCDR2_EPDC_PIX_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR2_EPDC_PIX_CLK_SEL) & BM_CCM_CSCDR2_EPDC_PIX_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EPDC_PIX_CLK_SEL field to a new value. +#define BW_CCM_CSCDR2_EPDC_PIX_CLK_SEL(v) (HW_CCM_CSCDR2_WR((HW_CCM_CSCDR2_RD() & ~BM_CCM_CSCDR2_EPDC_PIX_CLK_SEL) | BF_CCM_CSCDR2_EPDC_PIX_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR2, field EPDC_PIX_PODF[14:12] (RW) + * + * Divider for epdc_pix clock divider. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 (default) + */ +//@{ +#define BP_CCM_CSCDR2_EPDC_PIX_PODF (12) //!< Bit position for CCM_CSCDR2_EPDC_PIX_PODF. +#define BM_CCM_CSCDR2_EPDC_PIX_PODF (0x00007000) //!< Bit mask for CCM_CSCDR2_EPDC_PIX_PODF. + +//! @brief Get value of CCM_CSCDR2_EPDC_PIX_PODF from a register value. +#define BG_CCM_CSCDR2_EPDC_PIX_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR2_EPDC_PIX_PODF) >> BP_CCM_CSCDR2_EPDC_PIX_PODF) + +//! @brief Format value for bitfield CCM_CSCDR2_EPDC_PIX_PODF. +#define BF_CCM_CSCDR2_EPDC_PIX_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR2_EPDC_PIX_PODF) & BM_CCM_CSCDR2_EPDC_PIX_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EPDC_PIX_PODF field to a new value. +#define BW_CCM_CSCDR2_EPDC_PIX_PODF(v) (HW_CCM_CSCDR2_WR((HW_CCM_CSCDR2_RD() & ~BM_CCM_CSCDR2_EPDC_PIX_PODF) | BF_CCM_CSCDR2_EPDC_PIX_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR2, field EPDC_PIX_PRE_CLK_SEL[17:15] (RW) + * + * Selector for epdc_pix root clock pre-multiplexer + * + * Values: + * - 000 - derive clock from mmdc_ch0 clock + * - 001 - derive clock from pll3 + * - 010 - derive clock from pll5 + * - 011 - derive clock from 307M PFD + * - 100 - derive clock from 396M PFD + * - 101 - derive clock from 540M PFD + * - 110-111 - Restricted + */ +//@{ +#define BP_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL (15) //!< Bit position for CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL. +#define BM_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL (0x00038000) //!< Bit mask for CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL. + +//! @brief Get value of CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL from a register value. +#define BG_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL) >> BP_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL. +#define BF_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL) & BM_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EPDC_PIX_PRE_CLK_SEL field to a new value. +#define BW_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL(v) (HW_CCM_CSCDR2_WR((HW_CCM_CSCDR2_RD() & ~BM_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL) | BF_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR2, field ECSPI_CLK_PODF[24:19] (RW) + * + * Divider for ecspi clock podf. Note: Divider should be updated when output clock is gated. Note: + * The input clock to this divider should be lower than 300Mhz, the predivider can be used to + * achieve this. + * + * Values: + * - 000000 - divide by 1 + * - 111111 - divide by 2^6 + */ +//@{ +#define BP_CCM_CSCDR2_ECSPI_CLK_PODF (19) //!< Bit position for CCM_CSCDR2_ECSPI_CLK_PODF. +#define BM_CCM_CSCDR2_ECSPI_CLK_PODF (0x01f80000) //!< Bit mask for CCM_CSCDR2_ECSPI_CLK_PODF. + +//! @brief Get value of CCM_CSCDR2_ECSPI_CLK_PODF from a register value. +#define BG_CCM_CSCDR2_ECSPI_CLK_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR2_ECSPI_CLK_PODF) >> BP_CCM_CSCDR2_ECSPI_CLK_PODF) + +//! @brief Format value for bitfield CCM_CSCDR2_ECSPI_CLK_PODF. +#define BF_CCM_CSCDR2_ECSPI_CLK_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR2_ECSPI_CLK_PODF) & BM_CCM_CSCDR2_ECSPI_CLK_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ECSPI_CLK_PODF field to a new value. +#define BW_CCM_CSCDR2_ECSPI_CLK_PODF(v) (HW_CCM_CSCDR2_WR((HW_CCM_CSCDR2_RD() & ~BM_CCM_CSCDR2_ECSPI_CLK_PODF) | BF_CCM_CSCDR2_ECSPI_CLK_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CSCDR3 - CCM Serial Clock Divider Register 3 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CSCDR3 - CCM Serial Clock Divider Register 3 (RW) + * + * Reset value: 0x00014841 + * + * The figure below represents the CCM Serial Clock Divider Register 3(CSCDR3). The CSCDR3 register + * contains bits to control the clock generation sub module dividers. The table below provides its + * field descriptions. + */ +typedef union _hw_ccm_cscdr3 +{ + reg32_t U; + struct _hw_ccm_cscdr3_bitfields + { + unsigned RESERVED0 : 9; //!< [8:0] Reserved + unsigned IPU1_HSP_CLK_SEL : 2; //!< [10:9] Selector for ipu1_hsp clock multiplexer + unsigned IPU1_HSP_PODF : 3; //!< [13:11] Divider for ipu1_hsp clock. + unsigned EPDC_CLK_SEL : 2; //!< [15:14] Selector for epdc_axi, lcdif_axi, and pxp_axi clock multiplexer + unsigned EPDC_PODF : 3; //!< [18:16] Divider for epdc_axi, lcdif_axi, and pxp_axi clock. + unsigned RESERVED1 : 13; //!< [31:19] Reserved + } B; +} hw_ccm_cscdr3_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CSCDR3 register + */ +//@{ +#define HW_CCM_CSCDR3_ADDR (REGS_CCM_BASE + 0x3c) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CSCDR3 (*(volatile hw_ccm_cscdr3_t *) HW_CCM_CSCDR3_ADDR) +#define HW_CCM_CSCDR3_RD() (HW_CCM_CSCDR3.U) +#define HW_CCM_CSCDR3_WR(v) (HW_CCM_CSCDR3.U = (v)) +#define HW_CCM_CSCDR3_SET(v) (HW_CCM_CSCDR3_WR(HW_CCM_CSCDR3_RD() | (v))) +#define HW_CCM_CSCDR3_CLR(v) (HW_CCM_CSCDR3_WR(HW_CCM_CSCDR3_RD() & ~(v))) +#define HW_CCM_CSCDR3_TOG(v) (HW_CCM_CSCDR3_WR(HW_CCM_CSCDR3_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CSCDR3 bitfields + */ + +/*! @name Register CCM_CSCDR3, field IPU1_HSP_CLK_SEL[10:9] (RW) + * + * Selector for ipu1_hsp clock multiplexer + * + * Values: + * - 00 - derive clock from mmdc_ch0 clock (default) + * - 01 - derive clock from 396M PFD + * - 10 - derive clock from 120M + * - 11 - derive clock from 540M PFD + */ +//@{ +#define BP_CCM_CSCDR3_IPU1_HSP_CLK_SEL (9) //!< Bit position for CCM_CSCDR3_IPU1_HSP_CLK_SEL. +#define BM_CCM_CSCDR3_IPU1_HSP_CLK_SEL (0x00000600) //!< Bit mask for CCM_CSCDR3_IPU1_HSP_CLK_SEL. + +//! @brief Get value of CCM_CSCDR3_IPU1_HSP_CLK_SEL from a register value. +#define BG_CCM_CSCDR3_IPU1_HSP_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR3_IPU1_HSP_CLK_SEL) >> BP_CCM_CSCDR3_IPU1_HSP_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCDR3_IPU1_HSP_CLK_SEL. +#define BF_CCM_CSCDR3_IPU1_HSP_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR3_IPU1_HSP_CLK_SEL) & BM_CCM_CSCDR3_IPU1_HSP_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPU1_HSP_CLK_SEL field to a new value. +#define BW_CCM_CSCDR3_IPU1_HSP_CLK_SEL(v) (HW_CCM_CSCDR3_WR((HW_CCM_CSCDR3_RD() & ~BM_CCM_CSCDR3_IPU1_HSP_CLK_SEL) | BF_CCM_CSCDR3_IPU1_HSP_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR3, field IPU1_HSP_PODF[13:11] (RW) + * + * Divider for ipu1_hsp clock. Note: Divider should be updated when output clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCDR3_IPU1_HSP_PODF (11) //!< Bit position for CCM_CSCDR3_IPU1_HSP_PODF. +#define BM_CCM_CSCDR3_IPU1_HSP_PODF (0x00003800) //!< Bit mask for CCM_CSCDR3_IPU1_HSP_PODF. + +//! @brief Get value of CCM_CSCDR3_IPU1_HSP_PODF from a register value. +#define BG_CCM_CSCDR3_IPU1_HSP_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR3_IPU1_HSP_PODF) >> BP_CCM_CSCDR3_IPU1_HSP_PODF) + +//! @brief Format value for bitfield CCM_CSCDR3_IPU1_HSP_PODF. +#define BF_CCM_CSCDR3_IPU1_HSP_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR3_IPU1_HSP_PODF) & BM_CCM_CSCDR3_IPU1_HSP_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPU1_HSP_PODF field to a new value. +#define BW_CCM_CSCDR3_IPU1_HSP_PODF(v) (HW_CCM_CSCDR3_WR((HW_CCM_CSCDR3_RD() & ~BM_CCM_CSCDR3_IPU1_HSP_PODF) | BF_CCM_CSCDR3_IPU1_HSP_PODF(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR3, field EPDC_CLK_SEL[15:14] (RW) + * + * Selector for epdc_axi, lcdif_axi, and pxp_axi clock multiplexer + * + * Values: + * - 00 - derive clock from mmdc_ch0 clock + * - 01 - derive clock from 396M PFD (default) + * - 10 - derive clock from 120M + * - 11 - derive clock from 540M PFD + */ +//@{ +#define BP_CCM_CSCDR3_EPDC_CLK_SEL (14) //!< Bit position for CCM_CSCDR3_EPDC_CLK_SEL. +#define BM_CCM_CSCDR3_EPDC_CLK_SEL (0x0000c000) //!< Bit mask for CCM_CSCDR3_EPDC_CLK_SEL. + +//! @brief Get value of CCM_CSCDR3_EPDC_CLK_SEL from a register value. +#define BG_CCM_CSCDR3_EPDC_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR3_EPDC_CLK_SEL) >> BP_CCM_CSCDR3_EPDC_CLK_SEL) + +//! @brief Format value for bitfield CCM_CSCDR3_EPDC_CLK_SEL. +#define BF_CCM_CSCDR3_EPDC_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR3_EPDC_CLK_SEL) & BM_CCM_CSCDR3_EPDC_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EPDC_CLK_SEL field to a new value. +#define BW_CCM_CSCDR3_EPDC_CLK_SEL(v) (HW_CCM_CSCDR3_WR((HW_CCM_CSCDR3_RD() & ~BM_CCM_CSCDR3_EPDC_CLK_SEL) | BF_CCM_CSCDR3_EPDC_CLK_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CSCDR3, field EPDC_PODF[18:16] (RW) + * + * Divider for epdc_axi, lcdif_axi, and pxp_axi clock. Note: Divider should be updated when output + * clock is gated. + * + * Values: + * - 000 - divide by 1 + * - 001 - divide by 2 (default) + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CSCDR3_EPDC_PODF (16) //!< Bit position for CCM_CSCDR3_EPDC_PODF. +#define BM_CCM_CSCDR3_EPDC_PODF (0x00070000) //!< Bit mask for CCM_CSCDR3_EPDC_PODF. + +//! @brief Get value of CCM_CSCDR3_EPDC_PODF from a register value. +#define BG_CCM_CSCDR3_EPDC_PODF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CSCDR3_EPDC_PODF) >> BP_CCM_CSCDR3_EPDC_PODF) + +//! @brief Format value for bitfield CCM_CSCDR3_EPDC_PODF. +#define BF_CCM_CSCDR3_EPDC_PODF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CSCDR3_EPDC_PODF) & BM_CCM_CSCDR3_EPDC_PODF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EPDC_PODF field to a new value. +#define BW_CCM_CSCDR3_EPDC_PODF(v) (HW_CCM_CSCDR3_WR((HW_CCM_CSCDR3_RD() & ~BM_CCM_CSCDR3_EPDC_PODF) | BF_CCM_CSCDR3_EPDC_PODF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CWDR - CCM Wakeup Detector Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CWDR - CCM Wakeup Detector Register (RW) + * + * Reset value: 0x00000000 + * + * The figure below represents the CCM Wakeup Detector Register (CWDR). The CWDR register contains + * reserved, read-only bits.The table below provides its field descriptions. + */ +typedef union _hw_ccm_cwdr +{ + reg32_t U; + struct _hw_ccm_cwdr_bitfields + { + unsigned RESERVED0 : 32; //!< [31:0] Reserved + } B; +} hw_ccm_cwdr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CWDR register + */ +//@{ +#define HW_CCM_CWDR_ADDR (REGS_CCM_BASE + 0x44) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CWDR (*(volatile hw_ccm_cwdr_t *) HW_CCM_CWDR_ADDR) +#define HW_CCM_CWDR_RD() (HW_CCM_CWDR.U) +#define HW_CCM_CWDR_WR(v) (HW_CCM_CWDR.U = (v)) +#define HW_CCM_CWDR_SET(v) (HW_CCM_CWDR_WR(HW_CCM_CWDR_RD() | (v))) +#define HW_CCM_CWDR_CLR(v) (HW_CCM_CWDR_WR(HW_CCM_CWDR_RD() & ~(v))) +#define HW_CCM_CWDR_TOG(v) (HW_CCM_CWDR_WR(HW_CCM_CWDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CWDR bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_CCM_CDHIPR - CCM Divider Handshake In-Process Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CDHIPR - CCM Divider Handshake In-Process Register (RO) + * + * Reset value: 0x00000000 + * + * The figure below represents the CCM Divider Handshake In-Process Register (CDHIPR). The CDHIPR + * register contains read only bits that indicate that CCM is in the process of updating dividers or + * muxes that might need handshake with modules. + */ +typedef union _hw_ccm_cdhipr +{ + reg32_t U; + struct _hw_ccm_cdhipr_bitfields + { + unsigned AXI_PODF_BUSY : 1; //!< [0] Busy indicator for axi_podf. + unsigned AHB_PODF_BUSY : 1; //!< [1] Busy indicator for ahb_podf. + unsigned MMDC_CH1_PODF_BUSY : 1; //!< [2] Busy indicator for mmdc_ch1_axi_podf. + unsigned PERIPH2_CLK_SEL_BUSY : 1; //!< [3] Busy indicator for periph2_clk_sel mux control. + unsigned MMDC_CH0_PODF_BUSY : 1; //!< [4] Busy indicator for mmdc_ch0_axi_podf. + unsigned PERIPH_CLK_SEL_BUSY : 1; //!< [5] Busy indicator for periph_clk_sel mux control. + unsigned RESERVED0 : 10; //!< [15:6] Reserved + unsigned ARM_PODF_BUSY : 1; //!< [16] Busy indicator for arm_podf. + unsigned RESERVED1 : 15; //!< [31:17] Reserved + } B; +} hw_ccm_cdhipr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CDHIPR register + */ +//@{ +#define HW_CCM_CDHIPR_ADDR (REGS_CCM_BASE + 0x48) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CDHIPR (*(volatile hw_ccm_cdhipr_t *) HW_CCM_CDHIPR_ADDR) +#define HW_CCM_CDHIPR_RD() (HW_CCM_CDHIPR.U) +#endif +//@} + +/* + * constants & macros for individual CCM_CDHIPR bitfields + */ + +/*! @name Register CCM_CDHIPR, field AXI_PODF_BUSY[0] (RO) + * + * Busy indicator for axi_podf. + * + * Values: + * - 0 - divider is not busy and its value represents the actual division. + * - 1 - divider is busy with handshake process with module. The value read in the divider represents the + * previous value odivision factor, and after the handshake the written value of the axi_podf + * will be applied. + */ +//@{ +#define BP_CCM_CDHIPR_AXI_PODF_BUSY (0) //!< Bit position for CCM_CDHIPR_AXI_PODF_BUSY. +#define BM_CCM_CDHIPR_AXI_PODF_BUSY (0x00000001) //!< Bit mask for CCM_CDHIPR_AXI_PODF_BUSY. + +//! @brief Get value of CCM_CDHIPR_AXI_PODF_BUSY from a register value. +#define BG_CCM_CDHIPR_AXI_PODF_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDHIPR_AXI_PODF_BUSY) >> BP_CCM_CDHIPR_AXI_PODF_BUSY) +//@} + +/*! @name Register CCM_CDHIPR, field AHB_PODF_BUSY[1] (RO) + * + * Busy indicator for ahb_podf. + * + * Values: + * - 0 - divider is not busy and its value represents the actual division. + * - 1 - divider is busy with handshake process with module. The value read in the divider represents the + * previous value odivision factor, and after the handshake the written value of the ahb_podf + * will be applied. + */ +//@{ +#define BP_CCM_CDHIPR_AHB_PODF_BUSY (1) //!< Bit position for CCM_CDHIPR_AHB_PODF_BUSY. +#define BM_CCM_CDHIPR_AHB_PODF_BUSY (0x00000002) //!< Bit mask for CCM_CDHIPR_AHB_PODF_BUSY. + +//! @brief Get value of CCM_CDHIPR_AHB_PODF_BUSY from a register value. +#define BG_CCM_CDHIPR_AHB_PODF_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDHIPR_AHB_PODF_BUSY) >> BP_CCM_CDHIPR_AHB_PODF_BUSY) +//@} + +/*! @name Register CCM_CDHIPR, field MMDC_CH1_PODF_BUSY[2] (RO) + * + * Busy indicator for mmdc_ch1_axi_podf. + * + * Values: + * - 0 - divider is not busy and its value represents the actual division. + * - 1 - divider is busy with handshake process with module. The value read in the divider represents the + * previous value odivision factor, and after the handshake the written value of the + * mmdc_ch1_axi_podf will be applied. + */ +//@{ +#define BP_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (2) //!< Bit position for CCM_CDHIPR_MMDC_CH1_PODF_BUSY. +#define BM_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (0x00000004) //!< Bit mask for CCM_CDHIPR_MMDC_CH1_PODF_BUSY. + +//! @brief Get value of CCM_CDHIPR_MMDC_CH1_PODF_BUSY from a register value. +#define BG_CCM_CDHIPR_MMDC_CH1_PODF_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDHIPR_MMDC_CH1_PODF_BUSY) >> BP_CCM_CDHIPR_MMDC_CH1_PODF_BUSY) +//@} + +/*! @name Register CCM_CDHIPR, field PERIPH2_CLK_SEL_BUSY[3] (RO) + * + * Busy indicator for periph2_clk_sel mux control. + * + * Values: + * - 0 - mux is not busy and its value represents the actual division. + * - 1 - mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the + * previous value of select, and after the handshake periph2_clk_sel value will be applied. + */ +//@{ +#define BP_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (3) //!< Bit position for CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY. +#define BM_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (0x00000008) //!< Bit mask for CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY. + +//! @brief Get value of CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY from a register value. +#define BG_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) >> BP_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) +//@} + +/*! @name Register CCM_CDHIPR, field MMDC_CH0_PODF_BUSY[4] (RO) + * + * Busy indicator for mmdc_ch0_axi_podf. + * + * Values: + * - 0 - divider is not busy and its value represents the actual division. + * - 1 - divider is busy with handshake process with module. The value read in the divider represents the + * previous value odivision factor, and after the handshake the written value of the + * mmdc_ch0_axi_podf will be applied. + */ +//@{ +#define BP_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (4) //!< Bit position for CCM_CDHIPR_MMDC_CH0_PODF_BUSY. +#define BM_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (0x00000010) //!< Bit mask for CCM_CDHIPR_MMDC_CH0_PODF_BUSY. + +//! @brief Get value of CCM_CDHIPR_MMDC_CH0_PODF_BUSY from a register value. +#define BG_CCM_CDHIPR_MMDC_CH0_PODF_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDHIPR_MMDC_CH0_PODF_BUSY) >> BP_CCM_CDHIPR_MMDC_CH0_PODF_BUSY) +//@} + +/*! @name Register CCM_CDHIPR, field PERIPH_CLK_SEL_BUSY[5] (RO) + * + * Busy indicator for periph_clk_sel mux control. + * + * Values: + * - 0 - mux is not busy and its value represents the actual division. + * - 1 - mux is busy with handshake process with module. The value read in the periph_clk_sel represents the + * previous value of select, and after the handshake periph_clk_sel value will be applied. + */ +//@{ +#define BP_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (5) //!< Bit position for CCM_CDHIPR_PERIPH_CLK_SEL_BUSY. +#define BM_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (0x00000020) //!< Bit mask for CCM_CDHIPR_PERIPH_CLK_SEL_BUSY. + +//! @brief Get value of CCM_CDHIPR_PERIPH_CLK_SEL_BUSY from a register value. +#define BG_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) >> BP_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) +//@} + +/*! @name Register CCM_CDHIPR, field ARM_PODF_BUSY[16] (RO) + * + * Busy indicator for arm_podf. + * + * Values: + * - 0 - divider is not busy and its value represents the actual division. + * - 1 - divider is busy with handshake process with module. The value read in the divider represents the + * previous value odivision factor, and after the handshake the written value of the arm_podf + * will be applied. + */ +//@{ +#define BP_CCM_CDHIPR_ARM_PODF_BUSY (16) //!< Bit position for CCM_CDHIPR_ARM_PODF_BUSY. +#define BM_CCM_CDHIPR_ARM_PODF_BUSY (0x00010000) //!< Bit mask for CCM_CDHIPR_ARM_PODF_BUSY. + +//! @brief Get value of CCM_CDHIPR_ARM_PODF_BUSY from a register value. +#define BG_CCM_CDHIPR_ARM_PODF_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CDHIPR_ARM_PODF_BUSY) >> BP_CCM_CDHIPR_ARM_PODF_BUSY) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CTOR - CCM Testing Observability Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CTOR - CCM Testing Observability Register (RW) + * + * Reset value: 0x00000000 + * + * The figure below represents the CCM Testing Observability Register (CTOR). CCM includes three + * muxes to mux between different critical signals for testing observability. The output of the + * three muxes is generated on the three output signals obs_output_0, obs_output_1 and obs_output_2. + * Those three output signals can be generated on the IC pads by configuring the IOMUXC. The CTOR + * register contains bits to control the data generated for observability on the three output + * signals above. The table below provides its field descriptions. + */ +typedef union _hw_ccm_ctor +{ + reg32_t U; + struct _hw_ccm_ctor_bitfields + { + unsigned OBS_SPARE_OUTPUT_2_SEL : 4; //!< [3:0] Selection of the signal to be generated on obs_output_2 (output of CCM) for observability on the pads. + unsigned OBS_SPARE_OUTPUT_1_SEL : 4; //!< [7:4] Selection of the signal to be generated on obs_output_1 (output of CCM) for observability on the pads. + unsigned OBS_SPARE_OUTPUT_0_SEL : 5; //!< [12:8] Selection of the signal to be generated on obs_output_0 (output of CCM) for observability on the pads. + unsigned OBS_EN : 1; //!< [13] observability enable bit. + unsigned RESERVED0 : 18; //!< [31:14] Reserved + } B; +} hw_ccm_ctor_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CTOR register + */ +//@{ +#define HW_CCM_CTOR_ADDR (REGS_CCM_BASE + 0x50) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CTOR (*(volatile hw_ccm_ctor_t *) HW_CCM_CTOR_ADDR) +#define HW_CCM_CTOR_RD() (HW_CCM_CTOR.U) +#define HW_CCM_CTOR_WR(v) (HW_CCM_CTOR.U = (v)) +#define HW_CCM_CTOR_SET(v) (HW_CCM_CTOR_WR(HW_CCM_CTOR_RD() | (v))) +#define HW_CCM_CTOR_CLR(v) (HW_CCM_CTOR_WR(HW_CCM_CTOR_RD() & ~(v))) +#define HW_CCM_CTOR_TOG(v) (HW_CCM_CTOR_WR(HW_CCM_CTOR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CTOR bitfields + */ + +/*! @name Register CCM_CTOR, field OBS_SPARE_OUTPUT_2_SEL[3:0] (RW) + * + * Selection of the signal to be generated on obs_output_2 (output of CCM) for observability on the + * pads. + * + * Values: + * - 0000 - ccm_int_mem_ipg_stop + * - 0001 - lpm_current_state[2] + * - 0010 - hndsk_current_state[2] + * - 0011 - shd_current_state[1] + * - 0100 - Reserved + * - 0101 - src_clock_ready + * - 0110 - ref_clk_en_dpllip + * - 0111 - ccm_pup_req + * - 1000 - mmdc_ch0_stop_ack (lpack) + * - 1001 - mmdc_ch1_stop_ack (lpack): + * - 1010 - Reserved + * - 1011 - Reserved + * - 1100 - src_power_gating_reset_done + * - 1101 - tzic_dsm_wakeup + * - 1110 - gpc_pdn_ack + * - 1111 - pll_lrf_sticky3 + */ +//@{ +#define BP_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL (0) //!< Bit position for CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL. +#define BM_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL (0x0000000f) //!< Bit mask for CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL. + +//! @brief Get value of CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL from a register value. +#define BG_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL) >> BP_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL) + +//! @brief Format value for bitfield CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL. +#define BF_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL) & BM_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OBS_SPARE_OUTPUT_2_SEL field to a new value. +#define BW_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL(v) (HW_CCM_CTOR_WR((HW_CCM_CTOR_RD() & ~BM_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL) | BF_CCM_CTOR_OBS_SPARE_OUTPUT_2_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CTOR, field OBS_SPARE_OUTPUT_1_SEL[7:4] (RW) + * + * Selection of the signal to be generated on obs_output_1 (output of CCM) for observability on the + * pads. + * + * Values: + * - 0000 - ccm_system_in_wait_mode + * - 0001 - lpm_current_state[1] + * - 0010 - hndsk_current_state[1] + * - 0011 - Reserved + * - 0100 - ccm_ipg_wait + * - 0101 - Reserved + * - 0110 - dpll_en_dpllip + * - 0111 - ccm_pdn_4all_req + * - 1000 - eim_freq_change_ack + * - 1001 - ipu_freq_change_ack + * - 1010 - pll_lrf_sticky4 + * - 1011 - Reserved + * - 1100 - arm_dsm_request + * - 1101 - Reserved + * - 1110 - gpc_pup_ack + * - 1111 - pll_lrf_sticky2 + */ +//@{ +#define BP_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL (4) //!< Bit position for CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL. +#define BM_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL (0x000000f0) //!< Bit mask for CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL. + +//! @brief Get value of CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL from a register value. +#define BG_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL) >> BP_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL) + +//! @brief Format value for bitfield CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL. +#define BF_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL) & BM_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OBS_SPARE_OUTPUT_1_SEL field to a new value. +#define BW_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL(v) (HW_CCM_CTOR_WR((HW_CCM_CTOR_RD() & ~BM_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL) | BF_CCM_CTOR_OBS_SPARE_OUTPUT_1_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CTOR, field OBS_SPARE_OUTPUT_0_SEL[12:8] (RW) + * + * Selection of the signal to be generated on obs_output_0 (output of CCM) for observability on the + * pads. + * + * Values: + * - 00000 - ccm_system_in_stop_mode + * - 00001 - lpm_current_state[0] + * - 00010 - hndsk_current_state[0] + * - 00011 - shd_current_state[0] + * - 00100 - ccm_ipg_stop + * - 00101 - ccm_pdn_4arm_req + * - 00110 - mmdc_ch0_clk_change_req + * - 00111 - mmdc_ch1_clk_change_req + * - 01000 - Reserved + * - 01001 - Reserved + * - 01010 - pll_lrf_sticky1 + * - 01011 - Reserved + * - 01100 - clk_src_on + * - 01101 - ipu_lpsr_wakeup_ack + * - 01110 - src_warm_dvfs_req + * - 01111 - Reserved + * - 10000 - Reserved + * - 10001 - Reserved + * - 10010 - Reserved + * - 10011 - mmdc_ch0/1_lpmd + * - 10100 - Reserved + * - 10101 - Reserved + * - 10110 - Reserved + * - 10111 - Reserved + * - 11000 - Reserved + * - 11001 - obs_input_6 + * - 11010 - obs_input_0 + * - 11011 - obs_input_1 + * - 11100 - obs_input_2 + * - 11101 - obs_input_3 + * - 11110 - obs_input_4 + * - 11111 - obs_input_5 + */ +//@{ +#define BP_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL (8) //!< Bit position for CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL. +#define BM_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL (0x00001f00) //!< Bit mask for CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL. + +//! @brief Get value of CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL from a register value. +#define BG_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL) >> BP_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL) + +//! @brief Format value for bitfield CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL. +#define BF_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL) & BM_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OBS_SPARE_OUTPUT_0_SEL field to a new value. +#define BW_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL(v) (HW_CCM_CTOR_WR((HW_CCM_CTOR_RD() & ~BM_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL) | BF_CCM_CTOR_OBS_SPARE_OUTPUT_0_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CTOR, field OBS_EN[13] (RW) + * + * observability enable bit. this bit enables the output of the three observability muxes. + * + * Values: + * - 0 - Observability mux disabled. + * - 1 - Observability mux enabled. + */ +//@{ +#define BP_CCM_CTOR_OBS_EN (13) //!< Bit position for CCM_CTOR_OBS_EN. +#define BM_CCM_CTOR_OBS_EN (0x00002000) //!< Bit mask for CCM_CTOR_OBS_EN. + +//! @brief Get value of CCM_CTOR_OBS_EN from a register value. +#define BG_CCM_CTOR_OBS_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CTOR_OBS_EN) >> BP_CCM_CTOR_OBS_EN) + +//! @brief Format value for bitfield CCM_CTOR_OBS_EN. +#define BF_CCM_CTOR_OBS_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CTOR_OBS_EN) & BM_CCM_CTOR_OBS_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OBS_EN field to a new value. +#define BW_CCM_CTOR_OBS_EN(v) (HW_CCM_CTOR_WR((HW_CCM_CTOR_RD() & ~BM_CCM_CTOR_OBS_EN) | BF_CCM_CTOR_OBS_EN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CLPCR - CCM Low Power Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CLPCR - CCM Low Power Control Register (RW) + * + * Reset value: 0x00000079 + * + * The figure below represents the CCM Low Power Control Register (CLPCR). The CLPCR register + * contains bits to control the low power modes operation.The table below provides its field + * descriptions. + */ +typedef union _hw_ccm_clpcr +{ + reg32_t U; + struct _hw_ccm_clpcr_bitfields + { + unsigned LPM : 2; //!< [1:0] Setting the low power mode that system will enter on next assertion of dsm_request signal. + unsigned BYPASS_PMIC_VFUNCTIONAL_READY : 1; //!< [2] By asserting this bit CCM will bypass waiting for pmic_vfunctional_ready signal when coming out of STOP mode. + unsigned RESERVED0 : 2; //!< [4:3] Reserved + unsigned ARM_CLK_DIS_ON_LPM : 1; //!< [5] Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode. + unsigned SBYOS : 1; //!< [6] Standby clock oscillator bit. + unsigned DIS_REF_OSC : 1; //!< [7] dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i.e. + unsigned VSTBY : 1; //!< [8] Voltage standby request bit. + unsigned STBY_COUNT : 2; //!< [10:9] Standby counter definition. + unsigned COSC_PWRDOWN : 1; //!< [11] In run mode, software can manually control powering down of on chip oscillator, i.e. + unsigned RESERVED1 : 4; //!< [15:12] Reserved + unsigned WB_PER_AT_LPM : 1; //!< [16] Enable periphery charge pump for well biasing at low power mode (stop or wait) + unsigned RESERVED2 : 2; //!< [18:17] Reserved. + unsigned BYPASS_MMDC_CH0_LPM_HS : 1; //!< [19] Bypass handshake with mmdc_ch0 on next entrance to low power mode (wait or stop mode). + unsigned RESERVED3 : 1; //!< [20] Reserved + unsigned BYPASS_MMDC_CH1_LPM_HS : 1; //!< [21] Bypass handshake with mmdc_ch1 on next entrance to low power mode (wait or stop mode). + unsigned MASK_CORE0_WFI : 1; //!< [22] Mask WFI of core0 for entering low power mode + unsigned MASK_CORE1_WFI : 1; //!< [23] Mask WFI of core1 for entering low power mode + unsigned RESERVED4 : 2; //!< [25:24] Reserved + unsigned MASK_SCU_IDLE : 1; //!< [26] Mask SCU IDLE for entering low power mode + unsigned MASK_L2CC_IDLE : 1; //!< [27] Mask L2CC IDLE for entering low power mode. + unsigned RESERVED5 : 4; //!< [31:28] Reserved + } B; +} hw_ccm_clpcr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CLPCR register + */ +//@{ +#define HW_CCM_CLPCR_ADDR (REGS_CCM_BASE + 0x54) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CLPCR (*(volatile hw_ccm_clpcr_t *) HW_CCM_CLPCR_ADDR) +#define HW_CCM_CLPCR_RD() (HW_CCM_CLPCR.U) +#define HW_CCM_CLPCR_WR(v) (HW_CCM_CLPCR.U = (v)) +#define HW_CCM_CLPCR_SET(v) (HW_CCM_CLPCR_WR(HW_CCM_CLPCR_RD() | (v))) +#define HW_CCM_CLPCR_CLR(v) (HW_CCM_CLPCR_WR(HW_CCM_CLPCR_RD() & ~(v))) +#define HW_CCM_CLPCR_TOG(v) (HW_CCM_CLPCR_WR(HW_CCM_CLPCR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CLPCR bitfields + */ + +/*! @name Register CCM_CLPCR, field LPM[1:0] (RW) + * + * Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * Values: + * - 00 - Remain in run mode + * - 01 - Transfer to wait mode + * - 10 - Transfer to stop mode + * - 11 - Reserved + */ +//@{ +#define BP_CCM_CLPCR_LPM (0) //!< Bit position for CCM_CLPCR_LPM. +#define BM_CCM_CLPCR_LPM (0x00000003) //!< Bit mask for CCM_CLPCR_LPM. + +//! @brief Get value of CCM_CLPCR_LPM from a register value. +#define BG_CCM_CLPCR_LPM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_LPM) >> BP_CCM_CLPCR_LPM) + +//! @brief Format value for bitfield CCM_CLPCR_LPM. +#define BF_CCM_CLPCR_LPM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_LPM) & BM_CCM_CLPCR_LPM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LPM field to a new value. +#define BW_CCM_CLPCR_LPM(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_LPM) | BF_CCM_CLPCR_LPM(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field BYPASS_PMIC_VFUNCTIONAL_READY[2] (RW) + * + * By asserting this bit CCM will bypass waiting for pmic_vfunctional_ready signal when coming out + * of STOP mode. This should be used for PMIC's that don't support the pmic_vfunctional_ready + * signal. + * + * Values: + * - 0 - Don't bypass the pmic_vfunctional_ready signal - CCM will wait for it's assertion during exit of low + * power mode if standby voltage was enabled. + * - 1 - bypass the pmic_vfunctional_ready signal - CCM will not wait for it's assertion during exit of low + * power mode if standby voltage was enabled. + */ +//@{ +#define BP_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY (2) //!< Bit position for CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY. +#define BM_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY (0x00000004) //!< Bit mask for CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY. + +//! @brief Get value of CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY from a register value. +#define BG_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY) >> BP_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY) + +//! @brief Format value for bitfield CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY. +#define BF_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY) & BM_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_PMIC_VFUNCTIONAL_READY field to a new value. +#define BW_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY) | BF_CCM_CLPCR_BYPASS_PMIC_VFUNCTIONAL_READY(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field ARM_CLK_DIS_ON_LPM[5] (RW) + * + * Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on + * wait mode. This is useful for debug mode, when the user still wants to simulate entering wait + * mode and still keep ARM clock functioning. Note: software should not enable ARM power gating in + * wait mode if this bit is cleared. + * + * Values: + * - 0 - ARM clock enabled on wait mode. + * - 1 - ARM clock disabled on wait mode. (default). + */ +//@{ +#define BP_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (5) //!< Bit position for CCM_CLPCR_ARM_CLK_DIS_ON_LPM. +#define BM_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x00000020) //!< Bit mask for CCM_CLPCR_ARM_CLK_DIS_ON_LPM. + +//! @brief Get value of CCM_CLPCR_ARM_CLK_DIS_ON_LPM from a register value. +#define BG_CCM_CLPCR_ARM_CLK_DIS_ON_LPM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_ARM_CLK_DIS_ON_LPM) >> BP_CCM_CLPCR_ARM_CLK_DIS_ON_LPM) + +//! @brief Format value for bitfield CCM_CLPCR_ARM_CLK_DIS_ON_LPM. +#define BF_CCM_CLPCR_ARM_CLK_DIS_ON_LPM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_ARM_CLK_DIS_ON_LPM) & BM_CCM_CLPCR_ARM_CLK_DIS_ON_LPM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ARM_CLK_DIS_ON_LPM field to a new value. +#define BW_CCM_CLPCR_ARM_CLK_DIS_ON_LPM(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_ARM_CLK_DIS_ON_LPM) | BF_CCM_CLPCR_ARM_CLK_DIS_ON_LPM(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field SBYOS[6] (RW) + * + * Standby clock oscillator bit. This bit defines if cosc_pwrdown, which power down the on chip + * oscillator, will be asserted in stop mode. This bit is discarded if cosc_pwrdown='1' for the on + * chip oscillator. + * + * Values: + * - 0 - on chip oscillator will not be powered down, after next entrance to stop mode. (CCM_REF_EN_B will + * remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + * - 1 - on chip oscillator will be powered down, after next entrance to stop mode. (CCM_REF_EN_B will be + * deasserted - '1' and cosc_pwrdown will be asserted - '1'). (default). When returning from + * stop mode, external oscillator will be enabled again, on chip oscillator will return to + * oscillator mode , and after oscnt count ccm will continue with the exit from stop mode + * process. + */ +//@{ +#define BP_CCM_CLPCR_SBYOS (6) //!< Bit position for CCM_CLPCR_SBYOS. +#define BM_CCM_CLPCR_SBYOS (0x00000040) //!< Bit mask for CCM_CLPCR_SBYOS. + +//! @brief Get value of CCM_CLPCR_SBYOS from a register value. +#define BG_CCM_CLPCR_SBYOS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_SBYOS) >> BP_CCM_CLPCR_SBYOS) + +//! @brief Format value for bitfield CCM_CLPCR_SBYOS. +#define BF_CCM_CLPCR_SBYOS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_SBYOS) & BM_CCM_CLPCR_SBYOS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SBYOS field to a new value. +#define BW_CCM_CLPCR_SBYOS(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_SBYOS) | BF_CCM_CLPCR_SBYOS(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field DIS_REF_OSC[7] (RW) + * + * dis_ref_osc - in run mode, software can manually control closing of external reference oscillator + * clock, i.e. generating '1' on CCM_REF_EN_B signal. If software closed manually the external + * reference clock, then sbyos functionality will be bypassed. The manual closing of external + * reference oscilator should be performed only in case the reference oscilator is not the source of + * any clock generation. Note: When returning from stop mode, the PMIC_VSTBY_REQ will be deasserted + * (if it was asserted when entering stop mode), and CCM will wait for indication that functional + * voltage is ready (by sampling the assertion of pmic_vfuncional_ready) before continuing the + * process of exiting from stop mode. Please refer to stby_count bits. + * + * Values: + * - 0 - external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.(default) + * - 1 - external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + */ +//@{ +#define BP_CCM_CLPCR_DIS_REF_OSC (7) //!< Bit position for CCM_CLPCR_DIS_REF_OSC. +#define BM_CCM_CLPCR_DIS_REF_OSC (0x00000080) //!< Bit mask for CCM_CLPCR_DIS_REF_OSC. + +//! @brief Get value of CCM_CLPCR_DIS_REF_OSC from a register value. +#define BG_CCM_CLPCR_DIS_REF_OSC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_DIS_REF_OSC) >> BP_CCM_CLPCR_DIS_REF_OSC) + +//! @brief Format value for bitfield CCM_CLPCR_DIS_REF_OSC. +#define BF_CCM_CLPCR_DIS_REF_OSC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_DIS_REF_OSC) & BM_CCM_CLPCR_DIS_REF_OSC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIS_REF_OSC field to a new value. +#define BW_CCM_CLPCR_DIS_REF_OSC(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_DIS_REF_OSC) | BF_CCM_CLPCR_DIS_REF_OSC(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field VSTBY[8] (RW) + * + * Voltage standby request bit. This bit defines if PMIC_VSTBY_REQ pin, which notifies external + * power management IC to move from functional voltage to standby voltage, will be asserted in stop + * mode. + * + * Values: + * - 0 - voltage will not be changed to standby voltage after next entrance to stop mode. ( PMIC_VSTBY_REQ + * will remain negated - '0') + * - 1 - voltage will be requested to change to standby voltage after next entrance to stop mode. ( + * PMIC_VSTBY_REQ will be asserted - '1'). + */ +//@{ +#define BP_CCM_CLPCR_VSTBY (8) //!< Bit position for CCM_CLPCR_VSTBY. +#define BM_CCM_CLPCR_VSTBY (0x00000100) //!< Bit mask for CCM_CLPCR_VSTBY. + +//! @brief Get value of CCM_CLPCR_VSTBY from a register value. +#define BG_CCM_CLPCR_VSTBY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_VSTBY) >> BP_CCM_CLPCR_VSTBY) + +//! @brief Format value for bitfield CCM_CLPCR_VSTBY. +#define BF_CCM_CLPCR_VSTBY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_VSTBY) & BM_CCM_CLPCR_VSTBY) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VSTBY field to a new value. +#define BW_CCM_CLPCR_VSTBY(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_VSTBY) | BF_CCM_CLPCR_VSTBY(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field STBY_COUNT[10:9] (RW) + * + * Standby counter definition. These two bits define, in the case of stop exit (if vstby bit was + * set), the amount of time CCM will wait between PMIC_VSTBY_REQ negation and the check of assertion + * of PMIC_VFUNCTIONAL_READY . *NOTE: clock cycles ratio depends on pmic_delay_scaler, defined by + * CGPR[0] bit. + * + * Values: + * - 00 - CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + * - 01 - CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + * - 10 - CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + * - 11 - CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + */ +//@{ +#define BP_CCM_CLPCR_STBY_COUNT (9) //!< Bit position for CCM_CLPCR_STBY_COUNT. +#define BM_CCM_CLPCR_STBY_COUNT (0x00000600) //!< Bit mask for CCM_CLPCR_STBY_COUNT. + +//! @brief Get value of CCM_CLPCR_STBY_COUNT from a register value. +#define BG_CCM_CLPCR_STBY_COUNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_STBY_COUNT) >> BP_CCM_CLPCR_STBY_COUNT) + +//! @brief Format value for bitfield CCM_CLPCR_STBY_COUNT. +#define BF_CCM_CLPCR_STBY_COUNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_STBY_COUNT) & BM_CCM_CLPCR_STBY_COUNT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STBY_COUNT field to a new value. +#define BW_CCM_CLPCR_STBY_COUNT(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_STBY_COUNT) | BF_CCM_CLPCR_STBY_COUNT(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field COSC_PWRDOWN[11] (RW) + * + * In run mode, software can manually control powering down of on chip oscillator, i.e. generating + * '1' on cosc_pwrdown signal. If software manually powered down the on chip oscillator, then sbyos + * functionality for on chip oscillator will be bypassed. The manual closing of onchip oscillator + * should be performed only in case the reference oscilator is not the source of all the clocks + * generation. + * + * Values: + * - 0 - On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.(default) + * - 1 - On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + */ +//@{ +#define BP_CCM_CLPCR_COSC_PWRDOWN (11) //!< Bit position for CCM_CLPCR_COSC_PWRDOWN. +#define BM_CCM_CLPCR_COSC_PWRDOWN (0x00000800) //!< Bit mask for CCM_CLPCR_COSC_PWRDOWN. + +//! @brief Get value of CCM_CLPCR_COSC_PWRDOWN from a register value. +#define BG_CCM_CLPCR_COSC_PWRDOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_COSC_PWRDOWN) >> BP_CCM_CLPCR_COSC_PWRDOWN) + +//! @brief Format value for bitfield CCM_CLPCR_COSC_PWRDOWN. +#define BF_CCM_CLPCR_COSC_PWRDOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_COSC_PWRDOWN) & BM_CCM_CLPCR_COSC_PWRDOWN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the COSC_PWRDOWN field to a new value. +#define BW_CCM_CLPCR_COSC_PWRDOWN(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_COSC_PWRDOWN) | BF_CCM_CLPCR_COSC_PWRDOWN(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field WB_PER_AT_LPM[16] (RW) + * + * Enable periphery charge pump for well biasing at low power mode (stop or wait) + * + * Values: + * - 0 - Periphery charge pump won't be enabled at stop or wait low power mode + * - 1 - Periphery charge pump will be enabled at stop or wait low power mode + */ +//@{ +#define BP_CCM_CLPCR_WB_PER_AT_LPM (16) //!< Bit position for CCM_CLPCR_WB_PER_AT_LPM. +#define BM_CCM_CLPCR_WB_PER_AT_LPM (0x00010000) //!< Bit mask for CCM_CLPCR_WB_PER_AT_LPM. + +//! @brief Get value of CCM_CLPCR_WB_PER_AT_LPM from a register value. +#define BG_CCM_CLPCR_WB_PER_AT_LPM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_WB_PER_AT_LPM) >> BP_CCM_CLPCR_WB_PER_AT_LPM) + +//! @brief Format value for bitfield CCM_CLPCR_WB_PER_AT_LPM. +#define BF_CCM_CLPCR_WB_PER_AT_LPM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_WB_PER_AT_LPM) & BM_CCM_CLPCR_WB_PER_AT_LPM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WB_PER_AT_LPM field to a new value. +#define BW_CCM_CLPCR_WB_PER_AT_LPM(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_WB_PER_AT_LPM) | BF_CCM_CLPCR_WB_PER_AT_LPM(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field BYPASS_MMDC_CH0_LPM_HS[19] (RW) + * + * Bypass handshake with mmdc_ch0 on next entrance to low power mode (wait or stop mode). CCM does + * not wait for the module's acknowledge. Handshake also will be bypassed, if CGR3 CG10 is set to + * gate fast mmdc_ch0 clock. + * + * Values: + * - 0 - handshake with mmdc_ch0 on next entrance to low power mode will be performed. (default). + * - 1 - handshake with mmdc_ch0 on next entrance to low power mode will be bypassed. + */ +//@{ +#define BP_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS (19) //!< Bit position for CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS. +#define BM_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS (0x00080000) //!< Bit mask for CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS. + +//! @brief Get value of CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS from a register value. +#define BG_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS) >> BP_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS) + +//! @brief Format value for bitfield CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS. +#define BF_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS) & BM_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_MMDC_CH0_LPM_HS field to a new value. +#define BW_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS) | BF_CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field BYPASS_MMDC_CH1_LPM_HS[21] (RW) + * + * Bypass handshake with mmdc_ch1 on next entrance to low power mode (wait or stop mode). CCM does + * not wait for the module's acknowledge. Handshake also will be bypassed, if CGR3 CG10 is set to + * gate fast mmdc_ch1 clock. + * + * Values: + * - 0 - handshake with mmdc_ch1 on next entrance to low power mode will be performed. (default). + * - 1 - handshake with mmdc_ch1 on next entrance to low power mode will be bypassed. + */ +//@{ +#define BP_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS (21) //!< Bit position for CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS. +#define BM_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS (0x00200000) //!< Bit mask for CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS. + +//! @brief Get value of CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS from a register value. +#define BG_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS) >> BP_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS) + +//! @brief Format value for bitfield CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS. +#define BF_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS) & BM_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_MMDC_CH1_LPM_HS field to a new value. +#define BW_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS) | BF_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field MASK_CORE0_WFI[22] (RW) + * + * Mask WFI of core0 for entering low power mode Note: assertion of all bits[27:22] will generate + * low power mode request + * + * Values: + * - 0 - WFI of core0 is not masked + * - 1 - WFI of core0 is masked + */ +//@{ +#define BP_CCM_CLPCR_MASK_CORE0_WFI (22) //!< Bit position for CCM_CLPCR_MASK_CORE0_WFI. +#define BM_CCM_CLPCR_MASK_CORE0_WFI (0x00400000) //!< Bit mask for CCM_CLPCR_MASK_CORE0_WFI. + +//! @brief Get value of CCM_CLPCR_MASK_CORE0_WFI from a register value. +#define BG_CCM_CLPCR_MASK_CORE0_WFI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_MASK_CORE0_WFI) >> BP_CCM_CLPCR_MASK_CORE0_WFI) + +//! @brief Format value for bitfield CCM_CLPCR_MASK_CORE0_WFI. +#define BF_CCM_CLPCR_MASK_CORE0_WFI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_MASK_CORE0_WFI) & BM_CCM_CLPCR_MASK_CORE0_WFI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_CORE0_WFI field to a new value. +#define BW_CCM_CLPCR_MASK_CORE0_WFI(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_MASK_CORE0_WFI) | BF_CCM_CLPCR_MASK_CORE0_WFI(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field MASK_CORE1_WFI[23] (RW) + * + * Mask WFI of core1 for entering low power mode Note: assertion of all bits[27:22] will generate + * low power mode request + * + * Values: + * - 0 - WFI of core1 is not masked + * - 1 - WFI of core1 is masked + */ +//@{ +#define BP_CCM_CLPCR_MASK_CORE1_WFI (23) //!< Bit position for CCM_CLPCR_MASK_CORE1_WFI. +#define BM_CCM_CLPCR_MASK_CORE1_WFI (0x00800000) //!< Bit mask for CCM_CLPCR_MASK_CORE1_WFI. + +//! @brief Get value of CCM_CLPCR_MASK_CORE1_WFI from a register value. +#define BG_CCM_CLPCR_MASK_CORE1_WFI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_MASK_CORE1_WFI) >> BP_CCM_CLPCR_MASK_CORE1_WFI) + +//! @brief Format value for bitfield CCM_CLPCR_MASK_CORE1_WFI. +#define BF_CCM_CLPCR_MASK_CORE1_WFI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_MASK_CORE1_WFI) & BM_CCM_CLPCR_MASK_CORE1_WFI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_CORE1_WFI field to a new value. +#define BW_CCM_CLPCR_MASK_CORE1_WFI(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_MASK_CORE1_WFI) | BF_CCM_CLPCR_MASK_CORE1_WFI(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field MASK_SCU_IDLE[26] (RW) + * + * Mask SCU IDLE for entering low power mode Note: assertion of all bits[27:22] will generate low + * power mode request + * + * Values: + * - 0 - SCU IDLE is not masked + * - 1 - SCU IDLE is masked + */ +//@{ +#define BP_CCM_CLPCR_MASK_SCU_IDLE (26) //!< Bit position for CCM_CLPCR_MASK_SCU_IDLE. +#define BM_CCM_CLPCR_MASK_SCU_IDLE (0x04000000) //!< Bit mask for CCM_CLPCR_MASK_SCU_IDLE. + +//! @brief Get value of CCM_CLPCR_MASK_SCU_IDLE from a register value. +#define BG_CCM_CLPCR_MASK_SCU_IDLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_MASK_SCU_IDLE) >> BP_CCM_CLPCR_MASK_SCU_IDLE) + +//! @brief Format value for bitfield CCM_CLPCR_MASK_SCU_IDLE. +#define BF_CCM_CLPCR_MASK_SCU_IDLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_MASK_SCU_IDLE) & BM_CCM_CLPCR_MASK_SCU_IDLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_SCU_IDLE field to a new value. +#define BW_CCM_CLPCR_MASK_SCU_IDLE(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_MASK_SCU_IDLE) | BF_CCM_CLPCR_MASK_SCU_IDLE(v))) +#endif +//@} + +/*! @name Register CCM_CLPCR, field MASK_L2CC_IDLE[27] (RW) + * + * Mask L2CC IDLE for entering low power mode. Note: assertion of all bits[27:22] will generate low + * power mode request + * + * Values: + * - 0 - L2CC IDLE is not masked + * - 1 - L2CC IDLE is masked + */ +//@{ +#define BP_CCM_CLPCR_MASK_L2CC_IDLE (27) //!< Bit position for CCM_CLPCR_MASK_L2CC_IDLE. +#define BM_CCM_CLPCR_MASK_L2CC_IDLE (0x08000000) //!< Bit mask for CCM_CLPCR_MASK_L2CC_IDLE. + +//! @brief Get value of CCM_CLPCR_MASK_L2CC_IDLE from a register value. +#define BG_CCM_CLPCR_MASK_L2CC_IDLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CLPCR_MASK_L2CC_IDLE) >> BP_CCM_CLPCR_MASK_L2CC_IDLE) + +//! @brief Format value for bitfield CCM_CLPCR_MASK_L2CC_IDLE. +#define BF_CCM_CLPCR_MASK_L2CC_IDLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CLPCR_MASK_L2CC_IDLE) & BM_CCM_CLPCR_MASK_L2CC_IDLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_L2CC_IDLE field to a new value. +#define BW_CCM_CLPCR_MASK_L2CC_IDLE(v) (HW_CCM_CLPCR_WR((HW_CCM_CLPCR_RD() & ~BM_CCM_CLPCR_MASK_L2CC_IDLE) | BF_CCM_CLPCR_MASK_L2CC_IDLE(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CISR - CCM Interrupt Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CISR - CCM Interrupt Status Register (W1C) + * + * Reset value: 0x00000000 + * + * The figure below represents the CCM Interrupt Status Register (CISR). This is a write one to + * clear register. Once a interrupt is generated, software should write one to clear it. The table + * below provides its field descriptions. * Note: ipi_int_1 can be masked by ipi_int_1_mask bit. + * ipi_int_2 can be masked by ipi_int_2_mask bit. + */ +typedef union _hw_ccm_cisr +{ + reg32_t U; + struct _hw_ccm_cisr_bitfields + { + unsigned LRF_PLL : 1; //!< [0] Interrupt ipi_int_2 generated due to lock of all enabled and not bypaseed pll's + unsigned RESERVED0 : 5; //!< [5:1] Reserved + unsigned COSC_READY : 1; //!< [6] Interrupt ipi_int_2 generated due to on board oscillator ready, i.e. + unsigned RESERVED1 : 10; //!< [16:7] Reserved + unsigned AXI_PODF_LOADED : 1; //!< [17] Interrupt ipi_int_1 generated due to frequency change of axi_a_podf + unsigned AXI_B_PODF_LOADED : 1; //!< [18] Interrupt ipi_int_1 generated due to frequency change of axi_b_podf + unsigned PERIPH2_CLK_SEL_LOADED : 1; //!< [19] Interrupt ipi_int_1 generated due to frequency change of periph2_clk_sel + unsigned AHB_PODF_LOADED : 1; //!< [20] Interrupt ipi_int_1 generated due to frequency change of ahb_podf + unsigned MMDC_CH1_PODF_LOADED : 1; //!< [21] Interrupt ipi_int_1 generated due to frequency change of mmdc_ch0_podf_ loaded + unsigned PERIPH_CLK_SEL_LOADED : 1; //!< [22] Interrupt ipi_int_1 generated due to update of periph_clk_sel. + unsigned MMDC_CH0_PODF_LOADED : 1; //!< [23] Interrupt ipi_int_1 generated due to update of mmdc_ch0_axi_podf. + unsigned RESERVED2 : 2; //!< [25:24] Reserved + unsigned ARM_PODF_LOADED : 1; //!< [26] Interrupt ipi_int_1 generated due to frequency change of arm_podf. + unsigned RESERVED3 : 5; //!< [31:27] Reserved + } B; +} hw_ccm_cisr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CISR register + */ +//@{ +#define HW_CCM_CISR_ADDR (REGS_CCM_BASE + 0x58) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CISR (*(volatile hw_ccm_cisr_t *) HW_CCM_CISR_ADDR) +#define HW_CCM_CISR_RD() (HW_CCM_CISR.U) +#define HW_CCM_CISR_WR(v) (HW_CCM_CISR.U = (v)) +#define HW_CCM_CISR_SET(v) (HW_CCM_CISR_WR(HW_CCM_CISR_RD() | (v))) +#define HW_CCM_CISR_CLR(v) (HW_CCM_CISR_WR(HW_CCM_CISR_RD() & ~(v))) +#define HW_CCM_CISR_TOG(v) (HW_CCM_CISR_WR(HW_CCM_CISR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CISR bitfields + */ + +/*! @name Register CCM_CISR, field LRF_PLL[0] (W1C) + * + * Interrupt ipi_int_2 generated due to lock of all enabled and not bypaseed pll's + * + * Values: + * - 0 - interrupt is not genrerated due to lock ready of all enabled and not bypaseed pll's + * - 1 - interrupt genrerated due to lock ready of all enabled and not bypaseed pll's + */ +//@{ +#define BP_CCM_CISR_LRF_PLL (0) //!< Bit position for CCM_CISR_LRF_PLL. +#define BM_CCM_CISR_LRF_PLL (0x00000001) //!< Bit mask for CCM_CISR_LRF_PLL. + +//! @brief Get value of CCM_CISR_LRF_PLL from a register value. +#define BG_CCM_CISR_LRF_PLL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_LRF_PLL) >> BP_CCM_CISR_LRF_PLL) + +//! @brief Format value for bitfield CCM_CISR_LRF_PLL. +#define BF_CCM_CISR_LRF_PLL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_LRF_PLL) & BM_CCM_CISR_LRF_PLL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LRF_PLL field to a new value. +#define BW_CCM_CISR_LRF_PLL(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_LRF_PLL) | BF_CCM_CISR_LRF_PLL(v))) +#endif +//@} + +/*! @name Register CCM_CISR, field COSC_READY[6] (W1C) + * + * Interrupt ipi_int_2 generated due to on board oscillator ready, i.e. oscnt has finished counting. + * + * Values: + * - 0 - interrupt is not genrerated due to on board oscillator ready + * - 1 - interrupt genrerated due to on board oscillator ready + */ +//@{ +#define BP_CCM_CISR_COSC_READY (6) //!< Bit position for CCM_CISR_COSC_READY. +#define BM_CCM_CISR_COSC_READY (0x00000040) //!< Bit mask for CCM_CISR_COSC_READY. + +//! @brief Get value of CCM_CISR_COSC_READY from a register value. +#define BG_CCM_CISR_COSC_READY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_COSC_READY) >> BP_CCM_CISR_COSC_READY) + +//! @brief Format value for bitfield CCM_CISR_COSC_READY. +#define BF_CCM_CISR_COSC_READY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_COSC_READY) & BM_CCM_CISR_COSC_READY) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the COSC_READY field to a new value. +#define BW_CCM_CISR_COSC_READY(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_COSC_READY) | BF_CCM_CISR_COSC_READY(v))) +#endif +//@} + +/*! @name Register CCM_CISR, field AXI_PODF_LOADED[17] (W1C) + * + * Interrupt ipi_int_1 generated due to frequency change of axi_a_podf + * + * Values: + * - 0 - interrupt is not genrerated due to frequency change of axi_a_podf + * - 1 - interrupt genrerated due to frequency change of axi_a_podf + */ +//@{ +#define BP_CCM_CISR_AXI_PODF_LOADED (17) //!< Bit position for CCM_CISR_AXI_PODF_LOADED. +#define BM_CCM_CISR_AXI_PODF_LOADED (0x00020000) //!< Bit mask for CCM_CISR_AXI_PODF_LOADED. + +//! @brief Get value of CCM_CISR_AXI_PODF_LOADED from a register value. +#define BG_CCM_CISR_AXI_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_AXI_PODF_LOADED) >> BP_CCM_CISR_AXI_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CISR_AXI_PODF_LOADED. +#define BF_CCM_CISR_AXI_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_AXI_PODF_LOADED) & BM_CCM_CISR_AXI_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AXI_PODF_LOADED field to a new value. +#define BW_CCM_CISR_AXI_PODF_LOADED(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_AXI_PODF_LOADED) | BF_CCM_CISR_AXI_PODF_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CISR, field AXI_B_PODF_LOADED[18] (ROZ) + * + * Interrupt ipi_int_1 generated due to frequency change of axi_b_podf + * + * Values: + * - 0 - interrupt is not genrerated due to frequency change of axi_b_podf + * - 1 - interrupt genrerated due to frequency change of axi_b_podf + */ +//@{ +#define BP_CCM_CISR_AXI_B_PODF_LOADED (18) //!< Bit position for CCM_CISR_AXI_B_PODF_LOADED. +#define BM_CCM_CISR_AXI_B_PODF_LOADED (0x00040000) //!< Bit mask for CCM_CISR_AXI_B_PODF_LOADED. + +//! @brief Get value of CCM_CISR_AXI_B_PODF_LOADED from a register value. +#define BG_CCM_CISR_AXI_B_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_AXI_B_PODF_LOADED) >> BP_CCM_CISR_AXI_B_PODF_LOADED) +//@} + +/*! @name Register CCM_CISR, field PERIPH2_CLK_SEL_LOADED[19] (W1C) + * + * Interrupt ipi_int_1 generated due to frequency change of periph2_clk_sel + * + * Values: + * - 0 - interrupt is not genrerated due to frequency change of periph2_clk_sel + * - 1 - interrupt genrerated due to frequency change of periph2_clk_sel + */ +//@{ +#define BP_CCM_CISR_PERIPH2_CLK_SEL_LOADED (19) //!< Bit position for CCM_CISR_PERIPH2_CLK_SEL_LOADED. +#define BM_CCM_CISR_PERIPH2_CLK_SEL_LOADED (0x00080000) //!< Bit mask for CCM_CISR_PERIPH2_CLK_SEL_LOADED. + +//! @brief Get value of CCM_CISR_PERIPH2_CLK_SEL_LOADED from a register value. +#define BG_CCM_CISR_PERIPH2_CLK_SEL_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_PERIPH2_CLK_SEL_LOADED) >> BP_CCM_CISR_PERIPH2_CLK_SEL_LOADED) + +//! @brief Format value for bitfield CCM_CISR_PERIPH2_CLK_SEL_LOADED. +#define BF_CCM_CISR_PERIPH2_CLK_SEL_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_PERIPH2_CLK_SEL_LOADED) & BM_CCM_CISR_PERIPH2_CLK_SEL_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIPH2_CLK_SEL_LOADED field to a new value. +#define BW_CCM_CISR_PERIPH2_CLK_SEL_LOADED(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_PERIPH2_CLK_SEL_LOADED) | BF_CCM_CISR_PERIPH2_CLK_SEL_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CISR, field AHB_PODF_LOADED[20] (W1C) + * + * Interrupt ipi_int_1 generated due to frequency change of ahb_podf + * + * Values: + * - 0 - interrupt is not genrerated due to frequency change of ahb_podf + * - 1 - interrupt genrerated due to frequency change of ahb_podf + */ +//@{ +#define BP_CCM_CISR_AHB_PODF_LOADED (20) //!< Bit position for CCM_CISR_AHB_PODF_LOADED. +#define BM_CCM_CISR_AHB_PODF_LOADED (0x00100000) //!< Bit mask for CCM_CISR_AHB_PODF_LOADED. + +//! @brief Get value of CCM_CISR_AHB_PODF_LOADED from a register value. +#define BG_CCM_CISR_AHB_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_AHB_PODF_LOADED) >> BP_CCM_CISR_AHB_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CISR_AHB_PODF_LOADED. +#define BF_CCM_CISR_AHB_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_AHB_PODF_LOADED) & BM_CCM_CISR_AHB_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AHB_PODF_LOADED field to a new value. +#define BW_CCM_CISR_AHB_PODF_LOADED(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_AHB_PODF_LOADED) | BF_CCM_CISR_AHB_PODF_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CISR, field MMDC_CH1_PODF_LOADED[21] (W1C) + * + * Interrupt ipi_int_1 generated due to frequency change of mmdc_ch0_podf_ loaded + * + * Values: + * - 0 - interrupt is not genrerated due to frequency change of mmdc_ch0_podf_ loaded + * - 1 - interrupt genrerated due to frequency change of mmdc_ch0_podf_ loaded + */ +//@{ +#define BP_CCM_CISR_MMDC_CH1_PODF_LOADED (21) //!< Bit position for CCM_CISR_MMDC_CH1_PODF_LOADED. +#define BM_CCM_CISR_MMDC_CH1_PODF_LOADED (0x00200000) //!< Bit mask for CCM_CISR_MMDC_CH1_PODF_LOADED. + +//! @brief Get value of CCM_CISR_MMDC_CH1_PODF_LOADED from a register value. +#define BG_CCM_CISR_MMDC_CH1_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_MMDC_CH1_PODF_LOADED) >> BP_CCM_CISR_MMDC_CH1_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CISR_MMDC_CH1_PODF_LOADED. +#define BF_CCM_CISR_MMDC_CH1_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_MMDC_CH1_PODF_LOADED) & BM_CCM_CISR_MMDC_CH1_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MMDC_CH1_PODF_LOADED field to a new value. +#define BW_CCM_CISR_MMDC_CH1_PODF_LOADED(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_MMDC_CH1_PODF_LOADED) | BF_CCM_CISR_MMDC_CH1_PODF_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CISR, field PERIPH_CLK_SEL_LOADED[22] (W1C) + * + * Interrupt ipi_int_1 generated due to update of periph_clk_sel. + * + * Values: + * - 0 - interrupt is not genrerated due to update of periph_clk_sel. + * - 1 - interrupt genrerated due to update of periph_clk_sel. + */ +//@{ +#define BP_CCM_CISR_PERIPH_CLK_SEL_LOADED (22) //!< Bit position for CCM_CISR_PERIPH_CLK_SEL_LOADED. +#define BM_CCM_CISR_PERIPH_CLK_SEL_LOADED (0x00400000) //!< Bit mask for CCM_CISR_PERIPH_CLK_SEL_LOADED. + +//! @brief Get value of CCM_CISR_PERIPH_CLK_SEL_LOADED from a register value. +#define BG_CCM_CISR_PERIPH_CLK_SEL_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_PERIPH_CLK_SEL_LOADED) >> BP_CCM_CISR_PERIPH_CLK_SEL_LOADED) + +//! @brief Format value for bitfield CCM_CISR_PERIPH_CLK_SEL_LOADED. +#define BF_CCM_CISR_PERIPH_CLK_SEL_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_PERIPH_CLK_SEL_LOADED) & BM_CCM_CISR_PERIPH_CLK_SEL_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIPH_CLK_SEL_LOADED field to a new value. +#define BW_CCM_CISR_PERIPH_CLK_SEL_LOADED(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_PERIPH_CLK_SEL_LOADED) | BF_CCM_CISR_PERIPH_CLK_SEL_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CISR, field MMDC_CH0_PODF_LOADED[23] (W1C) + * + * Interrupt ipi_int_1 generated due to update of mmdc_ch0_axi_podf. + * + * Values: + * - 0 - interrupt is not genrerated due to update of mmdc_ch0_axi_podf. + * - 1 - interrupt genrerated due to update of mmdc_ch0_axi_podf* + */ +//@{ +#define BP_CCM_CISR_MMDC_CH0_PODF_LOADED (23) //!< Bit position for CCM_CISR_MMDC_CH0_PODF_LOADED. +#define BM_CCM_CISR_MMDC_CH0_PODF_LOADED (0x00800000) //!< Bit mask for CCM_CISR_MMDC_CH0_PODF_LOADED. + +//! @brief Get value of CCM_CISR_MMDC_CH0_PODF_LOADED from a register value. +#define BG_CCM_CISR_MMDC_CH0_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_MMDC_CH0_PODF_LOADED) >> BP_CCM_CISR_MMDC_CH0_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CISR_MMDC_CH0_PODF_LOADED. +#define BF_CCM_CISR_MMDC_CH0_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_MMDC_CH0_PODF_LOADED) & BM_CCM_CISR_MMDC_CH0_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MMDC_CH0_PODF_LOADED field to a new value. +#define BW_CCM_CISR_MMDC_CH0_PODF_LOADED(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_MMDC_CH0_PODF_LOADED) | BF_CCM_CISR_MMDC_CH0_PODF_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CISR, field ARM_PODF_LOADED[26] (W1C) + * + * Interrupt ipi_int_1 generated due to frequency change of arm_podf. The interrupt will commence + * only if arm_podf is loaded during a arm dvfs operation. + * + * Values: + * - 0 - interrupt is not genrerated due to frequency change of arm_podf + * - 1 - interrupt genrerated due to frequency change of arm_podf + */ +//@{ +#define BP_CCM_CISR_ARM_PODF_LOADED (26) //!< Bit position for CCM_CISR_ARM_PODF_LOADED. +#define BM_CCM_CISR_ARM_PODF_LOADED (0x04000000) //!< Bit mask for CCM_CISR_ARM_PODF_LOADED. + +//! @brief Get value of CCM_CISR_ARM_PODF_LOADED from a register value. +#define BG_CCM_CISR_ARM_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CISR_ARM_PODF_LOADED) >> BP_CCM_CISR_ARM_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CISR_ARM_PODF_LOADED. +#define BF_CCM_CISR_ARM_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CISR_ARM_PODF_LOADED) & BM_CCM_CISR_ARM_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ARM_PODF_LOADED field to a new value. +#define BW_CCM_CISR_ARM_PODF_LOADED(v) (HW_CCM_CISR_WR((HW_CCM_CISR_RD() & ~BM_CCM_CISR_ARM_PODF_LOADED) | BF_CCM_CISR_ARM_PODF_LOADED(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CIMR - CCM Interrupt Mask Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CIMR - CCM Interrupt Mask Register (RW) + * + * Reset value: 0xffffffff + * + * The figure below represents the CCM Interrupt Mask Register (CIMR). The table below provides its + * field descriptions. + */ +typedef union _hw_ccm_cimr +{ + reg32_t U; + struct _hw_ccm_cimr_bitfields + { + unsigned MASK_LRF_PLL : 1; //!< [0] mask interrupt generation due to lrf of pll's + unsigned RESERVED0 : 5; //!< [5:1] Reserved + unsigned MASK_COSC_READY : 1; //!< [6] mask interrupt generation due to on board oscillator ready + unsigned RESERVED1 : 10; //!< [16:7] Reserved + unsigned MASK_AXI_PODF_LOADED : 1; //!< [17] mask interrupt generation due to frequency change of axi_podf + unsigned MASK_AXI_B_PODF_LOADED : 1; //!< [18] mask interrupt generation due to frequency change of axi_b_podf + unsigned MASK_PERIPH2_CLK_SEL_LOADED : 1; //!< [19] mask interrupt generation due to update of periph2_clk_sel. + unsigned MASK_AHB_PODF_LOADED : 1; //!< [20] mask interrupt generation due to frequency change of ahb_podf + unsigned MASK_MMDC_CH1_PODF_LOADED : 1; //!< [21] mask interrupt generation due to update of mask_mmdc_ch1_podf + unsigned MASK_PERIPH_CLK_SEL_LOADED : 1; //!< [22] mask interrupt generation due to update of periph_clk_sel. + unsigned MASK_MMDC_CH0_PODF_LOADED : 1; //!< [23] mask interrupt generation due to update of mask_mmdc_ch0_podf + unsigned RESERVED2 : 2; //!< [25:24] Reserved + unsigned ARM_PODF_LOADED : 1; //!< [26] mask interrupt generation due to frequency change of arm_podf + unsigned RESERVED3 : 5; //!< [31:27] Reserved + } B; +} hw_ccm_cimr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CIMR register + */ +//@{ +#define HW_CCM_CIMR_ADDR (REGS_CCM_BASE + 0x5c) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CIMR (*(volatile hw_ccm_cimr_t *) HW_CCM_CIMR_ADDR) +#define HW_CCM_CIMR_RD() (HW_CCM_CIMR.U) +#define HW_CCM_CIMR_WR(v) (HW_CCM_CIMR.U = (v)) +#define HW_CCM_CIMR_SET(v) (HW_CCM_CIMR_WR(HW_CCM_CIMR_RD() | (v))) +#define HW_CCM_CIMR_CLR(v) (HW_CCM_CIMR_WR(HW_CCM_CIMR_RD() & ~(v))) +#define HW_CCM_CIMR_TOG(v) (HW_CCM_CIMR_WR(HW_CCM_CIMR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CIMR bitfields + */ + +/*! @name Register CCM_CIMR, field MASK_LRF_PLL[0] (RW) + * + * mask interrupt generation due to lrf of pll's + * + * Values: + * - 0 - don't mask interrupt due to lrf of pll's - interrupt will be created + * - 1 - mask interrupt due to lrf of pll's + */ +//@{ +#define BP_CCM_CIMR_MASK_LRF_PLL (0) //!< Bit position for CCM_CIMR_MASK_LRF_PLL. +#define BM_CCM_CIMR_MASK_LRF_PLL (0x00000001) //!< Bit mask for CCM_CIMR_MASK_LRF_PLL. + +//! @brief Get value of CCM_CIMR_MASK_LRF_PLL from a register value. +#define BG_CCM_CIMR_MASK_LRF_PLL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_LRF_PLL) >> BP_CCM_CIMR_MASK_LRF_PLL) + +//! @brief Format value for bitfield CCM_CIMR_MASK_LRF_PLL. +#define BF_CCM_CIMR_MASK_LRF_PLL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_MASK_LRF_PLL) & BM_CCM_CIMR_MASK_LRF_PLL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_LRF_PLL field to a new value. +#define BW_CCM_CIMR_MASK_LRF_PLL(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_MASK_LRF_PLL) | BF_CCM_CIMR_MASK_LRF_PLL(v))) +#endif +//@} + +/*! @name Register CCM_CIMR, field MASK_COSC_READY[6] (RW) + * + * mask interrupt generation due to on board oscillator ready + * + * Values: + * - 0 - don't mask interrupt due to on board oscillator ready - interrupt will be created + * - 1 - mask interrupt due to on board oscillator ready + */ +//@{ +#define BP_CCM_CIMR_MASK_COSC_READY (6) //!< Bit position for CCM_CIMR_MASK_COSC_READY. +#define BM_CCM_CIMR_MASK_COSC_READY (0x00000040) //!< Bit mask for CCM_CIMR_MASK_COSC_READY. + +//! @brief Get value of CCM_CIMR_MASK_COSC_READY from a register value. +#define BG_CCM_CIMR_MASK_COSC_READY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_COSC_READY) >> BP_CCM_CIMR_MASK_COSC_READY) + +//! @brief Format value for bitfield CCM_CIMR_MASK_COSC_READY. +#define BF_CCM_CIMR_MASK_COSC_READY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_MASK_COSC_READY) & BM_CCM_CIMR_MASK_COSC_READY) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_COSC_READY field to a new value. +#define BW_CCM_CIMR_MASK_COSC_READY(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_MASK_COSC_READY) | BF_CCM_CIMR_MASK_COSC_READY(v))) +#endif +//@} + +/*! @name Register CCM_CIMR, field MASK_AXI_PODF_LOADED[17] (RW) + * + * mask interrupt generation due to frequency change of axi_podf + * + * Values: + * - 0 - don't mask interrupt due to frequency change of axi_podf - interrupt will be created + * - 1 - mask interrupt due to frequency change of axi_podf + */ +//@{ +#define BP_CCM_CIMR_MASK_AXI_PODF_LOADED (17) //!< Bit position for CCM_CIMR_MASK_AXI_PODF_LOADED. +#define BM_CCM_CIMR_MASK_AXI_PODF_LOADED (0x00020000) //!< Bit mask for CCM_CIMR_MASK_AXI_PODF_LOADED. + +//! @brief Get value of CCM_CIMR_MASK_AXI_PODF_LOADED from a register value. +#define BG_CCM_CIMR_MASK_AXI_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_AXI_PODF_LOADED) >> BP_CCM_CIMR_MASK_AXI_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CIMR_MASK_AXI_PODF_LOADED. +#define BF_CCM_CIMR_MASK_AXI_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_MASK_AXI_PODF_LOADED) & BM_CCM_CIMR_MASK_AXI_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_AXI_PODF_LOADED field to a new value. +#define BW_CCM_CIMR_MASK_AXI_PODF_LOADED(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_MASK_AXI_PODF_LOADED) | BF_CCM_CIMR_MASK_AXI_PODF_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CIMR, field MASK_AXI_B_PODF_LOADED[18] (RO) + * + * mask interrupt generation due to frequency change of axi_b_podf + * + * Values: + * - 0 - don't mask interrupt due to frequency change of axi_b_podf - interrupt will be created + * - 1 - mask interrupt due to frequency change of axi_b_podf + */ +//@{ +#define BP_CCM_CIMR_MASK_AXI_B_PODF_LOADED (18) //!< Bit position for CCM_CIMR_MASK_AXI_B_PODF_LOADED. +#define BM_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x00040000) //!< Bit mask for CCM_CIMR_MASK_AXI_B_PODF_LOADED. + +//! @brief Get value of CCM_CIMR_MASK_AXI_B_PODF_LOADED from a register value. +#define BG_CCM_CIMR_MASK_AXI_B_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_AXI_B_PODF_LOADED) >> BP_CCM_CIMR_MASK_AXI_B_PODF_LOADED) +//@} + +/*! @name Register CCM_CIMR, field MASK_PERIPH2_CLK_SEL_LOADED[19] (RW) + * + * mask interrupt generation due to update of periph2_clk_sel. + * + * Values: + * - 0 - don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + * - 1 - mask interrupt due to update of periph2_clk_sel + */ +//@{ +#define BP_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (19) //!< Bit position for CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED. +#define BM_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (0x00080000) //!< Bit mask for CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED. + +//! @brief Get value of CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED from a register value. +#define BG_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED) >> BP_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED) + +//! @brief Format value for bitfield CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED. +#define BF_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED) & BM_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_PERIPH2_CLK_SEL_LOADED field to a new value. +#define BW_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED) | BF_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CIMR, field MASK_AHB_PODF_LOADED[20] (RW) + * + * mask interrupt generation due to frequency change of ahb_podf + * + * Values: + * - 0 - don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + * - 1 - mask interrupt due to frequency change of ahb_podf + */ +//@{ +#define BP_CCM_CIMR_MASK_AHB_PODF_LOADED (20) //!< Bit position for CCM_CIMR_MASK_AHB_PODF_LOADED. +#define BM_CCM_CIMR_MASK_AHB_PODF_LOADED (0x00100000) //!< Bit mask for CCM_CIMR_MASK_AHB_PODF_LOADED. + +//! @brief Get value of CCM_CIMR_MASK_AHB_PODF_LOADED from a register value. +#define BG_CCM_CIMR_MASK_AHB_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_AHB_PODF_LOADED) >> BP_CCM_CIMR_MASK_AHB_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CIMR_MASK_AHB_PODF_LOADED. +#define BF_CCM_CIMR_MASK_AHB_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_MASK_AHB_PODF_LOADED) & BM_CCM_CIMR_MASK_AHB_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_AHB_PODF_LOADED field to a new value. +#define BW_CCM_CIMR_MASK_AHB_PODF_LOADED(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_MASK_AHB_PODF_LOADED) | BF_CCM_CIMR_MASK_AHB_PODF_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CIMR, field MASK_MMDC_CH1_PODF_LOADED[21] (RW) + * + * mask interrupt generation due to update of mask_mmdc_ch1_podf + * + * Values: + * - 0 - don't mask interrupt due to update of mask_mmdc_ch1_podf - interrupt will be created + * - 1 - mask interrupt due to update of mask_mmdc_ch1_podf + */ +//@{ +#define BP_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (21) //!< Bit position for CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED. +#define BM_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (0x00200000) //!< Bit mask for CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED. + +//! @brief Get value of CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED from a register value. +#define BG_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED) >> BP_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED. +#define BF_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED) & BM_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_MMDC_CH1_PODF_LOADED field to a new value. +#define BW_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED) | BF_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CIMR, field MASK_PERIPH_CLK_SEL_LOADED[22] (RW) + * + * mask interrupt generation due to update of periph_clk_sel. + * + * Values: + * - 0 - don't mask interrupt due to update of periph_clk_sel - interrupt will be created + * - 1 - mask interrupt due to update of periph_clk_sel + */ +//@{ +#define BP_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (22) //!< Bit position for CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED. +#define BM_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (0x00400000) //!< Bit mask for CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED. + +//! @brief Get value of CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED from a register value. +#define BG_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED) >> BP_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED) + +//! @brief Format value for bitfield CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED. +#define BF_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED) & BM_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_PERIPH_CLK_SEL_LOADED field to a new value. +#define BW_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED) | BF_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CIMR, field MASK_MMDC_CH0_PODF_LOADED[23] (RW) + * + * mask interrupt generation due to update of mask_mmdc_ch0_podf + * + * Values: + * - 0 - don't mask interrupt due to update of mask_mmdc_ch0_podf - interrupt will be created + * - 1 - mask interrupt due to update of mask_mmdc_ch0_podf + */ +//@{ +#define BP_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (23) //!< Bit position for CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED. +#define BM_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (0x00800000) //!< Bit mask for CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED. + +//! @brief Get value of CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED from a register value. +#define BG_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED) >> BP_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED. +#define BF_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED) & BM_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MASK_MMDC_CH0_PODF_LOADED field to a new value. +#define BW_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED) | BF_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED(v))) +#endif +//@} + +/*! @name Register CCM_CIMR, field ARM_PODF_LOADED[26] (RW) + * + * mask interrupt generation due to frequency change of arm_podf + * + * Values: + * - 0 - don't mask interrupt due to frequency change of arm_podf - interrupt will be created + * - 1 - mask interrupt due to frequency change of arm_podf + */ +//@{ +#define BP_CCM_CIMR_ARM_PODF_LOADED (26) //!< Bit position for CCM_CIMR_ARM_PODF_LOADED. +#define BM_CCM_CIMR_ARM_PODF_LOADED (0x04000000) //!< Bit mask for CCM_CIMR_ARM_PODF_LOADED. + +//! @brief Get value of CCM_CIMR_ARM_PODF_LOADED from a register value. +#define BG_CCM_CIMR_ARM_PODF_LOADED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CIMR_ARM_PODF_LOADED) >> BP_CCM_CIMR_ARM_PODF_LOADED) + +//! @brief Format value for bitfield CCM_CIMR_ARM_PODF_LOADED. +#define BF_CCM_CIMR_ARM_PODF_LOADED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CIMR_ARM_PODF_LOADED) & BM_CCM_CIMR_ARM_PODF_LOADED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ARM_PODF_LOADED field to a new value. +#define BW_CCM_CIMR_ARM_PODF_LOADED(v) (HW_CCM_CIMR_WR((HW_CCM_CIMR_RD() & ~BM_CCM_CIMR_ARM_PODF_LOADED) | BF_CCM_CIMR_ARM_PODF_LOADED(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCOSR - CCM Clock Output Source Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCOSR - CCM Clock Output Source Register (RW) + * + * Reset value: 0x000a0001 + * + * The figure below represents the CCM Clock Output Source Register (CCOSR). The CCOSR register + * contains bits to control the clock s that will be generated on the output ipp_do_clko1 + * (CCM_CLKO1) and ipp_do_clko2 (CCM_CLKO2) .The table below provides its field descriptions. + */ +typedef union _hw_ccm_ccosr +{ + reg32_t U; + struct _hw_ccm_ccosr_bitfields + { + unsigned CLKO1_SEL : 4; //!< [3:0] Selection of the clock to be generated on CCM_CLKO1 + unsigned CLKO1_DIV : 3; //!< [6:4] Setting the divider of CCM_CLKO1 + unsigned CLKO1_EN : 1; //!< [7] Enable of CCM_CLKO1 clock + unsigned CLKO_SEL : 1; //!< [8] CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks + unsigned RESERVED0 : 7; //!< [15:9] Reserved + unsigned CLKO2_SEL : 5; //!< [20:16] Selection of the clock to be generated on CCM_CLKO2 + unsigned CLKO2_DIV : 3; //!< [23:21] Setting the divider of CCM_CLKO2 + unsigned CLKO2_EN : 1; //!< [24] Enable of CCM_CLKO2 clock + unsigned RESERVED1 : 7; //!< [31:25] Reserved + } B; +} hw_ccm_ccosr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCOSR register + */ +//@{ +#define HW_CCM_CCOSR_ADDR (REGS_CCM_BASE + 0x60) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCOSR (*(volatile hw_ccm_ccosr_t *) HW_CCM_CCOSR_ADDR) +#define HW_CCM_CCOSR_RD() (HW_CCM_CCOSR.U) +#define HW_CCM_CCOSR_WR(v) (HW_CCM_CCOSR.U = (v)) +#define HW_CCM_CCOSR_SET(v) (HW_CCM_CCOSR_WR(HW_CCM_CCOSR_RD() | (v))) +#define HW_CCM_CCOSR_CLR(v) (HW_CCM_CCOSR_WR(HW_CCM_CCOSR_RD() & ~(v))) +#define HW_CCM_CCOSR_TOG(v) (HW_CCM_CCOSR_WR(HW_CCM_CCOSR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCOSR bitfields + */ + +/*! @name Register CCM_CCOSR, field CLKO1_SEL[3:0] (RW) + * + * Selection of the clock to be generated on CCM_CLKO1 + * + * Values: + * - 0000 - pll3_sw_clk (this inputs has additional constant division /2) + * - 0001 - pll2_main_clk (default) (this inputs has additional constant division /2) + * - 0010 - pll1_main_clk (this inputs has additional constant division /2) + * - 0011 - pll5_main_clk (this inputs has additional constant division /2) + * - 0100 - video_27M_clk_root + * - 0101 - dtcp_clk_root + * - 0110 - enfc_clk_root + * - 0111 - ipu1_di0_clk_root + * - 1000 - ipu1_di1_clk_root + * - 1001 - lcdif_pix_clk_root + * - 1010 - epdc_pix_clk_root + * - 1011 - ahb_clk_root + * - 1100 - ipg_clk_root + * - 1101 - perclk_root + * - 1110 - ckil_sync_clk_root + * - 1111 - pll4_main_clk + */ +//@{ +#define BP_CCM_CCOSR_CLKO1_SEL (0) //!< Bit position for CCM_CCOSR_CLKO1_SEL. +#define BM_CCM_CCOSR_CLKO1_SEL (0x0000000f) //!< Bit mask for CCM_CCOSR_CLKO1_SEL. + +//! @brief Get value of CCM_CCOSR_CLKO1_SEL from a register value. +#define BG_CCM_CCOSR_CLKO1_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCOSR_CLKO1_SEL) >> BP_CCM_CCOSR_CLKO1_SEL) + +//! @brief Format value for bitfield CCM_CCOSR_CLKO1_SEL. +#define BF_CCM_CCOSR_CLKO1_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCOSR_CLKO1_SEL) & BM_CCM_CCOSR_CLKO1_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKO1_SEL field to a new value. +#define BW_CCM_CCOSR_CLKO1_SEL(v) (HW_CCM_CCOSR_WR((HW_CCM_CCOSR_RD() & ~BM_CCM_CCOSR_CLKO1_SEL) | BF_CCM_CCOSR_CLKO1_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CCOSR, field CLKO1_DIV[6:4] (RW) + * + * Setting the divider of CCM_CLKO1 + * + * Values: + * - 000 - divide by 1(default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CCOSR_CLKO1_DIV (4) //!< Bit position for CCM_CCOSR_CLKO1_DIV. +#define BM_CCM_CCOSR_CLKO1_DIV (0x00000070) //!< Bit mask for CCM_CCOSR_CLKO1_DIV. + +//! @brief Get value of CCM_CCOSR_CLKO1_DIV from a register value. +#define BG_CCM_CCOSR_CLKO1_DIV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCOSR_CLKO1_DIV) >> BP_CCM_CCOSR_CLKO1_DIV) + +//! @brief Format value for bitfield CCM_CCOSR_CLKO1_DIV. +#define BF_CCM_CCOSR_CLKO1_DIV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCOSR_CLKO1_DIV) & BM_CCM_CCOSR_CLKO1_DIV) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKO1_DIV field to a new value. +#define BW_CCM_CCOSR_CLKO1_DIV(v) (HW_CCM_CCOSR_WR((HW_CCM_CCOSR_RD() & ~BM_CCM_CCOSR_CLKO1_DIV) | BF_CCM_CCOSR_CLKO1_DIV(v))) +#endif +//@} + +/*! @name Register CCM_CCOSR, field CLKO1_EN[7] (RW) + * + * Enable of CCM_CLKO1 clock + * + * Values: + * - 0 - CCM_CLKO1 disabled. + * - 1 - CCM_CLKO1 enabled. + */ +//@{ +#define BP_CCM_CCOSR_CLKO1_EN (7) //!< Bit position for CCM_CCOSR_CLKO1_EN. +#define BM_CCM_CCOSR_CLKO1_EN (0x00000080) //!< Bit mask for CCM_CCOSR_CLKO1_EN. + +//! @brief Get value of CCM_CCOSR_CLKO1_EN from a register value. +#define BG_CCM_CCOSR_CLKO1_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCOSR_CLKO1_EN) >> BP_CCM_CCOSR_CLKO1_EN) + +//! @brief Format value for bitfield CCM_CCOSR_CLKO1_EN. +#define BF_CCM_CCOSR_CLKO1_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCOSR_CLKO1_EN) & BM_CCM_CCOSR_CLKO1_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKO1_EN field to a new value. +#define BW_CCM_CCOSR_CLKO1_EN(v) (HW_CCM_CCOSR_WR((HW_CCM_CCOSR_RD() & ~BM_CCM_CCOSR_CLKO1_EN) | BF_CCM_CCOSR_CLKO1_EN(v))) +#endif +//@} + +/*! @name Register CCM_CCOSR, field CLKO_SEL[8] (RW) + * + * CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks + * + * Values: + * - 0 - CCM_CLKO1 output drives CCM_CLKO1 clock + * - 1 - CCM_CLKO1 output drives CCM_CLKO2 clock + */ +//@{ +#define BP_CCM_CCOSR_CLKO_SEL (8) //!< Bit position for CCM_CCOSR_CLKO_SEL. +#define BM_CCM_CCOSR_CLKO_SEL (0x00000100) //!< Bit mask for CCM_CCOSR_CLKO_SEL. + +//! @brief Get value of CCM_CCOSR_CLKO_SEL from a register value. +#define BG_CCM_CCOSR_CLKO_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCOSR_CLKO_SEL) >> BP_CCM_CCOSR_CLKO_SEL) + +//! @brief Format value for bitfield CCM_CCOSR_CLKO_SEL. +#define BF_CCM_CCOSR_CLKO_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCOSR_CLKO_SEL) & BM_CCM_CCOSR_CLKO_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKO_SEL field to a new value. +#define BW_CCM_CCOSR_CLKO_SEL(v) (HW_CCM_CCOSR_WR((HW_CCM_CCOSR_RD() & ~BM_CCM_CCOSR_CLKO_SEL) | BF_CCM_CCOSR_CLKO_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CCOSR, field CLKO2_SEL[20:16] (RW) + * + * Selection of the clock to be generated on CCM_CLKO2 + * + * Values: + * - 00000 - mmdc_ch0_axi_clk_root + * - 00001 - mmdc_ch1_axi_clk_root + * - 00010 - usdhc4_clk_root + * - 00011 - usdhc1_clk_root + * - 00101 - wrck_clk_root + * - 00110 - ecspi_clk_root + * - 01000 - usdhc3_clk_root + * - 01001 - pcie_clk_root + * - 01010 - arm_axi_clk_root (default) + * - 01011 - ipu1_hsp_clk_root + * - 01100 - epdc_axi_clk_root, lcdif_axi_clk_root, pxp_axi_clk_root + * - 01101 - vdo_axi_clk_root + * - 01110 - osc_clk + * - 01111 - mlb_sys_clk_root + * - 10000 - gpu3d_core_clk_root + * - 10001 - usdhc2_clk_root + * - 10010 - ssi1_clk_root + * - 10011 - ssi2_clk_root + * - 10100 - ssi3_clk_root + * - 10101 - gpu2d_core_clk_root + * - 10110 - vpu_axi_clk_root + * - 10111 - can_clk_root + * - 11000 - ldb_di0_serial_clk_root + * - 11001 - ldb_di1_serial_clk_root + * - 11010 - esai_clk_root + * - 11011 - aclk_eim_slow_clk_root + * - 11100 - uart_clk_root + * - 11101 - spdif0_clk_root + * - 11110 - spdif1_clk_root + * - 11111 - hsi_tx_clk_root + */ +//@{ +#define BP_CCM_CCOSR_CLKO2_SEL (16) //!< Bit position for CCM_CCOSR_CLKO2_SEL. +#define BM_CCM_CCOSR_CLKO2_SEL (0x001f0000) //!< Bit mask for CCM_CCOSR_CLKO2_SEL. + +//! @brief Get value of CCM_CCOSR_CLKO2_SEL from a register value. +#define BG_CCM_CCOSR_CLKO2_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCOSR_CLKO2_SEL) >> BP_CCM_CCOSR_CLKO2_SEL) + +//! @brief Format value for bitfield CCM_CCOSR_CLKO2_SEL. +#define BF_CCM_CCOSR_CLKO2_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCOSR_CLKO2_SEL) & BM_CCM_CCOSR_CLKO2_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKO2_SEL field to a new value. +#define BW_CCM_CCOSR_CLKO2_SEL(v) (HW_CCM_CCOSR_WR((HW_CCM_CCOSR_RD() & ~BM_CCM_CCOSR_CLKO2_SEL) | BF_CCM_CCOSR_CLKO2_SEL(v))) +#endif +//@} + +/*! @name Register CCM_CCOSR, field CLKO2_DIV[23:21] (RW) + * + * Setting the divider of CCM_CLKO2 + * + * Values: + * - 000 - divide by 1 (default) + * - 001 - divide by 2 + * - 010 - divide by 3 + * - 011 - divide by 4 + * - 100 - divide by 5 + * - 101 - divide by 6 + * - 110 - divide by 7 + * - 111 - divide by 8 + */ +//@{ +#define BP_CCM_CCOSR_CLKO2_DIV (21) //!< Bit position for CCM_CCOSR_CLKO2_DIV. +#define BM_CCM_CCOSR_CLKO2_DIV (0x00e00000) //!< Bit mask for CCM_CCOSR_CLKO2_DIV. + +//! @brief Get value of CCM_CCOSR_CLKO2_DIV from a register value. +#define BG_CCM_CCOSR_CLKO2_DIV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCOSR_CLKO2_DIV) >> BP_CCM_CCOSR_CLKO2_DIV) + +//! @brief Format value for bitfield CCM_CCOSR_CLKO2_DIV. +#define BF_CCM_CCOSR_CLKO2_DIV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCOSR_CLKO2_DIV) & BM_CCM_CCOSR_CLKO2_DIV) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKO2_DIV field to a new value. +#define BW_CCM_CCOSR_CLKO2_DIV(v) (HW_CCM_CCOSR_WR((HW_CCM_CCOSR_RD() & ~BM_CCM_CCOSR_CLKO2_DIV) | BF_CCM_CCOSR_CLKO2_DIV(v))) +#endif +//@} + +/*! @name Register CCM_CCOSR, field CLKO2_EN[24] (RW) + * + * Enable of CCM_CLKO2 clock + * + * Values: + * - 0 - CCM_CLKO2 disabled. + * - 1 - CCM_CLKO2 enabled. + */ +//@{ +#define BP_CCM_CCOSR_CLKO2_EN (24) //!< Bit position for CCM_CCOSR_CLKO2_EN. +#define BM_CCM_CCOSR_CLKO2_EN (0x01000000) //!< Bit mask for CCM_CCOSR_CLKO2_EN. + +//! @brief Get value of CCM_CCOSR_CLKO2_EN from a register value. +#define BG_CCM_CCOSR_CLKO2_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCOSR_CLKO2_EN) >> BP_CCM_CCOSR_CLKO2_EN) + +//! @brief Format value for bitfield CCM_CCOSR_CLKO2_EN. +#define BF_CCM_CCOSR_CLKO2_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCOSR_CLKO2_EN) & BM_CCM_CCOSR_CLKO2_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKO2_EN field to a new value. +#define BW_CCM_CCOSR_CLKO2_EN(v) (HW_CCM_CCOSR_WR((HW_CCM_CCOSR_RD() & ~BM_CCM_CCOSR_CLKO2_EN) | BF_CCM_CCOSR_CLKO2_EN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CGPR - CCM General Purpose Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CGPR - CCM General Purpose Register (RW) + * + * Reset value: 0x0000fe62 + * + * Fast PLL enable. Can be used to engage PLL faster after STOP mode, if 24MHz OSC was active + */ +typedef union _hw_ccm_cgpr +{ + reg32_t U; + struct _hw_ccm_cgpr_bitfields + { + unsigned PMIC_DELAY_SCALER : 1; //!< [0] Defines clock dividion of clock for stby_count (pmic delay counter) + unsigned RESERVED0 : 1; //!< [1] Reserved + unsigned MMDC_EXT_CLK_DIS : 1; //!< [2] Disable external clock driver of MMDC during STOP mode + unsigned RESERVED1 : 1; //!< [3] Reserved + unsigned EFUSE_PROG_SUPPLY_GATE : 1; //!< [4] Defines the value of the output signal cgpr_dout[4]. + unsigned RESERVED3 : 11; //!< [15:5] Reserved. + unsigned FPL : 1; //!< [16] Fast PLL enable. + unsigned RESERVED4 : 15; //!< [31:17] Reserved + } B; +} hw_ccm_cgpr_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CGPR register + */ +//@{ +#define HW_CCM_CGPR_ADDR (REGS_CCM_BASE + 0x64) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CGPR (*(volatile hw_ccm_cgpr_t *) HW_CCM_CGPR_ADDR) +#define HW_CCM_CGPR_RD() (HW_CCM_CGPR.U) +#define HW_CCM_CGPR_WR(v) (HW_CCM_CGPR.U = (v)) +#define HW_CCM_CGPR_SET(v) (HW_CCM_CGPR_WR(HW_CCM_CGPR_RD() | (v))) +#define HW_CCM_CGPR_CLR(v) (HW_CCM_CGPR_WR(HW_CCM_CGPR_RD() & ~(v))) +#define HW_CCM_CGPR_TOG(v) (HW_CCM_CGPR_WR(HW_CCM_CGPR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CGPR bitfields + */ + +/*! @name Register CCM_CGPR, field PMIC_DELAY_SCALER[0] (RW) + * + * Defines clock dividion of clock for stby_count (pmic delay counter) + * + * Values: + * - 0 - clock is not divided + * - 1 - clock is divided /8 + */ +//@{ +#define BP_CCM_CGPR_PMIC_DELAY_SCALER (0) //!< Bit position for CCM_CGPR_PMIC_DELAY_SCALER. +#define BM_CCM_CGPR_PMIC_DELAY_SCALER (0x00000001) //!< Bit mask for CCM_CGPR_PMIC_DELAY_SCALER. + +//! @brief Get value of CCM_CGPR_PMIC_DELAY_SCALER from a register value. +#define BG_CCM_CGPR_PMIC_DELAY_SCALER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CGPR_PMIC_DELAY_SCALER) >> BP_CCM_CGPR_PMIC_DELAY_SCALER) + +//! @brief Format value for bitfield CCM_CGPR_PMIC_DELAY_SCALER. +#define BF_CCM_CGPR_PMIC_DELAY_SCALER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CGPR_PMIC_DELAY_SCALER) & BM_CCM_CGPR_PMIC_DELAY_SCALER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PMIC_DELAY_SCALER field to a new value. +#define BW_CCM_CGPR_PMIC_DELAY_SCALER(v) (HW_CCM_CGPR_WR((HW_CCM_CGPR_RD() & ~BM_CCM_CGPR_PMIC_DELAY_SCALER) | BF_CCM_CGPR_PMIC_DELAY_SCALER(v))) +#endif +//@} + +/*! @name Register CCM_CGPR, field MMDC_EXT_CLK_DIS[2] (RW) + * + * Disable external clock driver of MMDC during STOP mode + * + * Values: + * - 0 - don't disable during stop mode. + * - 1 - disable during stop mode + */ +//@{ +#define BP_CCM_CGPR_MMDC_EXT_CLK_DIS (2) //!< Bit position for CCM_CGPR_MMDC_EXT_CLK_DIS. +#define BM_CCM_CGPR_MMDC_EXT_CLK_DIS (0x00000004) //!< Bit mask for CCM_CGPR_MMDC_EXT_CLK_DIS. + +//! @brief Get value of CCM_CGPR_MMDC_EXT_CLK_DIS from a register value. +#define BG_CCM_CGPR_MMDC_EXT_CLK_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CGPR_MMDC_EXT_CLK_DIS) >> BP_CCM_CGPR_MMDC_EXT_CLK_DIS) + +//! @brief Format value for bitfield CCM_CGPR_MMDC_EXT_CLK_DIS. +#define BF_CCM_CGPR_MMDC_EXT_CLK_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CGPR_MMDC_EXT_CLK_DIS) & BM_CCM_CGPR_MMDC_EXT_CLK_DIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MMDC_EXT_CLK_DIS field to a new value. +#define BW_CCM_CGPR_MMDC_EXT_CLK_DIS(v) (HW_CCM_CGPR_WR((HW_CCM_CGPR_RD() & ~BM_CCM_CGPR_MMDC_EXT_CLK_DIS) | BF_CCM_CGPR_MMDC_EXT_CLK_DIS(v))) +#endif +//@} + +/*! @name Register CCM_CGPR, field EFUSE_PROG_SUPPLY_GATE[4] (RW) + * + * Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing + * + * Values: + * - 0 - fuse programing supply voltage is gated off to the efuse module + * - 1 - allow fuse programing. + */ +//@{ +#define BP_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (4) //!< Bit position for CCM_CGPR_EFUSE_PROG_SUPPLY_GATE. +#define BM_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x00000010) //!< Bit mask for CCM_CGPR_EFUSE_PROG_SUPPLY_GATE. + +//! @brief Get value of CCM_CGPR_EFUSE_PROG_SUPPLY_GATE from a register value. +#define BG_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE) >> BP_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE) + +//! @brief Format value for bitfield CCM_CGPR_EFUSE_PROG_SUPPLY_GATE. +#define BF_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE) & BM_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EFUSE_PROG_SUPPLY_GATE field to a new value. +#define BW_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(v) (HW_CCM_CGPR_WR((HW_CCM_CGPR_RD() & ~BM_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE) | BF_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(v))) +#endif +//@} + +/*! @name Register CCM_CGPR, field FPL[16] (RW) + * + * Values: + * - 0 - Engage PLL enable default way. + * - 1 - Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if + * 24MHz OSC was active in low power mode. + */ +//@{ +#define BP_CCM_CGPR_FPL (16) //!< Bit position for CCM_CGPR_FPL. +#define BM_CCM_CGPR_FPL (0x00010000) //!< Bit mask for CCM_CGPR_FPL. + +//! @brief Get value of CCM_CGPR_FPL from a register value. +#define BG_CCM_CGPR_FPL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CGPR_FPL) >> BP_CCM_CGPR_FPL) + +//! @brief Format value for bitfield CCM_CGPR_FPL. +#define BF_CCM_CGPR_FPL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CGPR_FPL) & BM_CCM_CGPR_FPL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FPL field to a new value. +#define BW_CCM_CGPR_FPL(v) (HW_CCM_CGPR_WR((HW_CCM_CGPR_RD() & ~BM_CCM_CGPR_FPL) | BF_CCM_CGPR_FPL(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCGR0 - CCM Clock Gating Register 0 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCGR0 - CCM Clock Gating Register 0 (RW) + * + * Reset value: 0xffffffff + * + * CG(i) bits CCGR 0- 6 These bits are used to turn on/off the clock to each module + * independently.The following table details the possible clock activity conditions for each module + * CGR value Clock Activity Description 00 clock is off during all modes. stop enter hardware + * handshake is disabled. 01 clock is on in run mode, but off in wait and stop modes 10 Not + * applicable (Reserved). 11 clock is on during all modes, except stop mode. Module should be + * stopped, before set it's bits to "0", since clocks to the module will be stopped immediately. The + * tables above show the register mapings for the different CGR's. The clock connectivity table + * should be used to match the "CCM output affected" to the actual clocks going into the modules. + * The figure below represents the CCM Clock Gating Register 0 (CCM_CCGR0). The clock gating + * Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 7 CGR + * registers. The number of registers required is according to the number of peripherals in the + * system. + */ +typedef union _hw_ccm_ccgr0 +{ + reg32_t U; + struct _hw_ccm_ccgr0_bitfields + { + unsigned CG0 : 2; //!< [1:0] aips_tz1 clocks (aips_tz1_clk_enable) + unsigned CG1 : 2; //!< [3:2] aips_tz2 clocks (aips_tz2_clk_enable) + unsigned CG2 : 2; //!< [5:4] apbhdma hclk clock (apbhdma_hclk_enable) + unsigned CG3 : 2; //!< [7:6] asrc clock (asrc_clk_enable) + unsigned CG4 : 2; //!< [9:8] caam_secure_mem clock (caam_secure_mem_clk_enable) + unsigned CG5 : 2; //!< [11:10] caam_wrapper_aclk clock (caam_wrapper_aclk_enable) + unsigned CG6 : 2; //!< [13:12] caam_wrapper_ipg clock (caam_wrapper_ipg_enable) + unsigned CG7 : 2; //!< [15:14] can1 clock (can1_clk_enable) + unsigned CG8 : 2; //!< [17:16] can1_serial clock (can1_serial_clk_enable) + unsigned CG9 : 2; //!< [19:18] can2 clock (can2_clk_enable) + unsigned CG10 : 2; //!< [21:20] can2_serial clock (can2_serial_clk_enable) + unsigned CG11 : 2; //!< [23:22] CPU debug clocks (arm_dbg_clk_enable) + unsigned CG12 : 2; //!< [25:24] dcic 1 clocks (dcic1_clk_enable) + unsigned CG13 : 2; //!< [27:26] dcic2 clocks (dcic2_clk_enable) + unsigned CG14 : 2; //!< [29:28] dtcp clocks (dtcp_dtcp_clk_enable) + unsigned CG15 : 2; //!< [31:30] Reserved + } B; +} hw_ccm_ccgr0_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCGR0 register + */ +//@{ +#define HW_CCM_CCGR0_ADDR (REGS_CCM_BASE + 0x68) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCGR0 (*(volatile hw_ccm_ccgr0_t *) HW_CCM_CCGR0_ADDR) +#define HW_CCM_CCGR0_RD() (HW_CCM_CCGR0.U) +#define HW_CCM_CCGR0_WR(v) (HW_CCM_CCGR0.U = (v)) +#define HW_CCM_CCGR0_SET(v) (HW_CCM_CCGR0_WR(HW_CCM_CCGR0_RD() | (v))) +#define HW_CCM_CCGR0_CLR(v) (HW_CCM_CCGR0_WR(HW_CCM_CCGR0_RD() & ~(v))) +#define HW_CCM_CCGR0_TOG(v) (HW_CCM_CCGR0_WR(HW_CCM_CCGR0_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCGR0 bitfields + */ + +/*! @name Register CCM_CCGR0, field CG0[1:0] (RW) + * + * aips_tz1 clocks (aips_tz1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG0 (0) //!< Bit position for CCM_CCGR0_CG0. +#define BM_CCM_CCGR0_CG0 (0x00000003) //!< Bit mask for CCM_CCGR0_CG0. + +//! @brief Get value of CCM_CCGR0_CG0 from a register value. +#define BG_CCM_CCGR0_CG0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG0) >> BP_CCM_CCGR0_CG0) + +//! @brief Format value for bitfield CCM_CCGR0_CG0. +#define BF_CCM_CCGR0_CG0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG0) & BM_CCM_CCGR0_CG0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG0 field to a new value. +#define BW_CCM_CCGR0_CG0(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG0) | BF_CCM_CCGR0_CG0(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG1[3:2] (RW) + * + * aips_tz2 clocks (aips_tz2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG1 (2) //!< Bit position for CCM_CCGR0_CG1. +#define BM_CCM_CCGR0_CG1 (0x0000000c) //!< Bit mask for CCM_CCGR0_CG1. + +//! @brief Get value of CCM_CCGR0_CG1 from a register value. +#define BG_CCM_CCGR0_CG1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG1) >> BP_CCM_CCGR0_CG1) + +//! @brief Format value for bitfield CCM_CCGR0_CG1. +#define BF_CCM_CCGR0_CG1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG1) & BM_CCM_CCGR0_CG1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG1 field to a new value. +#define BW_CCM_CCGR0_CG1(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG1) | BF_CCM_CCGR0_CG1(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG2[5:4] (RW) + * + * apbhdma hclk clock (apbhdma_hclk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG2 (4) //!< Bit position for CCM_CCGR0_CG2. +#define BM_CCM_CCGR0_CG2 (0x00000030) //!< Bit mask for CCM_CCGR0_CG2. + +//! @brief Get value of CCM_CCGR0_CG2 from a register value. +#define BG_CCM_CCGR0_CG2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG2) >> BP_CCM_CCGR0_CG2) + +//! @brief Format value for bitfield CCM_CCGR0_CG2. +#define BF_CCM_CCGR0_CG2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG2) & BM_CCM_CCGR0_CG2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG2 field to a new value. +#define BW_CCM_CCGR0_CG2(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG2) | BF_CCM_CCGR0_CG2(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG3[7:6] (RW) + * + * asrc clock (asrc_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG3 (6) //!< Bit position for CCM_CCGR0_CG3. +#define BM_CCM_CCGR0_CG3 (0x000000c0) //!< Bit mask for CCM_CCGR0_CG3. + +//! @brief Get value of CCM_CCGR0_CG3 from a register value. +#define BG_CCM_CCGR0_CG3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG3) >> BP_CCM_CCGR0_CG3) + +//! @brief Format value for bitfield CCM_CCGR0_CG3. +#define BF_CCM_CCGR0_CG3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG3) & BM_CCM_CCGR0_CG3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG3 field to a new value. +#define BW_CCM_CCGR0_CG3(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG3) | BF_CCM_CCGR0_CG3(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG4[9:8] (RW) + * + * caam_secure_mem clock (caam_secure_mem_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG4 (8) //!< Bit position for CCM_CCGR0_CG4. +#define BM_CCM_CCGR0_CG4 (0x00000300) //!< Bit mask for CCM_CCGR0_CG4. + +//! @brief Get value of CCM_CCGR0_CG4 from a register value. +#define BG_CCM_CCGR0_CG4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG4) >> BP_CCM_CCGR0_CG4) + +//! @brief Format value for bitfield CCM_CCGR0_CG4. +#define BF_CCM_CCGR0_CG4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG4) & BM_CCM_CCGR0_CG4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG4 field to a new value. +#define BW_CCM_CCGR0_CG4(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG4) | BF_CCM_CCGR0_CG4(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG5[11:10] (RW) + * + * caam_wrapper_aclk clock (caam_wrapper_aclk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG5 (10) //!< Bit position for CCM_CCGR0_CG5. +#define BM_CCM_CCGR0_CG5 (0x00000c00) //!< Bit mask for CCM_CCGR0_CG5. + +//! @brief Get value of CCM_CCGR0_CG5 from a register value. +#define BG_CCM_CCGR0_CG5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG5) >> BP_CCM_CCGR0_CG5) + +//! @brief Format value for bitfield CCM_CCGR0_CG5. +#define BF_CCM_CCGR0_CG5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG5) & BM_CCM_CCGR0_CG5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG5 field to a new value. +#define BW_CCM_CCGR0_CG5(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG5) | BF_CCM_CCGR0_CG5(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG6[13:12] (RW) + * + * caam_wrapper_ipg clock (caam_wrapper_ipg_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG6 (12) //!< Bit position for CCM_CCGR0_CG6. +#define BM_CCM_CCGR0_CG6 (0x00003000) //!< Bit mask for CCM_CCGR0_CG6. + +//! @brief Get value of CCM_CCGR0_CG6 from a register value. +#define BG_CCM_CCGR0_CG6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG6) >> BP_CCM_CCGR0_CG6) + +//! @brief Format value for bitfield CCM_CCGR0_CG6. +#define BF_CCM_CCGR0_CG6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG6) & BM_CCM_CCGR0_CG6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG6 field to a new value. +#define BW_CCM_CCGR0_CG6(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG6) | BF_CCM_CCGR0_CG6(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG7[15:14] (RW) + * + * can1 clock (can1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG7 (14) //!< Bit position for CCM_CCGR0_CG7. +#define BM_CCM_CCGR0_CG7 (0x0000c000) //!< Bit mask for CCM_CCGR0_CG7. + +//! @brief Get value of CCM_CCGR0_CG7 from a register value. +#define BG_CCM_CCGR0_CG7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG7) >> BP_CCM_CCGR0_CG7) + +//! @brief Format value for bitfield CCM_CCGR0_CG7. +#define BF_CCM_CCGR0_CG7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG7) & BM_CCM_CCGR0_CG7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG7 field to a new value. +#define BW_CCM_CCGR0_CG7(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG7) | BF_CCM_CCGR0_CG7(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG8[17:16] (RW) + * + * can1_serial clock (can1_serial_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG8 (16) //!< Bit position for CCM_CCGR0_CG8. +#define BM_CCM_CCGR0_CG8 (0x00030000) //!< Bit mask for CCM_CCGR0_CG8. + +//! @brief Get value of CCM_CCGR0_CG8 from a register value. +#define BG_CCM_CCGR0_CG8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG8) >> BP_CCM_CCGR0_CG8) + +//! @brief Format value for bitfield CCM_CCGR0_CG8. +#define BF_CCM_CCGR0_CG8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG8) & BM_CCM_CCGR0_CG8) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG8 field to a new value. +#define BW_CCM_CCGR0_CG8(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG8) | BF_CCM_CCGR0_CG8(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG9[19:18] (RW) + * + * can2 clock (can2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG9 (18) //!< Bit position for CCM_CCGR0_CG9. +#define BM_CCM_CCGR0_CG9 (0x000c0000) //!< Bit mask for CCM_CCGR0_CG9. + +//! @brief Get value of CCM_CCGR0_CG9 from a register value. +#define BG_CCM_CCGR0_CG9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG9) >> BP_CCM_CCGR0_CG9) + +//! @brief Format value for bitfield CCM_CCGR0_CG9. +#define BF_CCM_CCGR0_CG9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG9) & BM_CCM_CCGR0_CG9) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG9 field to a new value. +#define BW_CCM_CCGR0_CG9(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG9) | BF_CCM_CCGR0_CG9(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG10[21:20] (RW) + * + * can2_serial clock (can2_serial_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG10 (20) //!< Bit position for CCM_CCGR0_CG10. +#define BM_CCM_CCGR0_CG10 (0x00300000) //!< Bit mask for CCM_CCGR0_CG10. + +//! @brief Get value of CCM_CCGR0_CG10 from a register value. +#define BG_CCM_CCGR0_CG10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG10) >> BP_CCM_CCGR0_CG10) + +//! @brief Format value for bitfield CCM_CCGR0_CG10. +#define BF_CCM_CCGR0_CG10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG10) & BM_CCM_CCGR0_CG10) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG10 field to a new value. +#define BW_CCM_CCGR0_CG10(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG10) | BF_CCM_CCGR0_CG10(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG11[23:22] (RW) + * + * CPU debug clocks (arm_dbg_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG11 (22) //!< Bit position for CCM_CCGR0_CG11. +#define BM_CCM_CCGR0_CG11 (0x00c00000) //!< Bit mask for CCM_CCGR0_CG11. + +//! @brief Get value of CCM_CCGR0_CG11 from a register value. +#define BG_CCM_CCGR0_CG11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG11) >> BP_CCM_CCGR0_CG11) + +//! @brief Format value for bitfield CCM_CCGR0_CG11. +#define BF_CCM_CCGR0_CG11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG11) & BM_CCM_CCGR0_CG11) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG11 field to a new value. +#define BW_CCM_CCGR0_CG11(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG11) | BF_CCM_CCGR0_CG11(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG12[25:24] (RW) + * + * dcic 1 clocks (dcic1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG12 (24) //!< Bit position for CCM_CCGR0_CG12. +#define BM_CCM_CCGR0_CG12 (0x03000000) //!< Bit mask for CCM_CCGR0_CG12. + +//! @brief Get value of CCM_CCGR0_CG12 from a register value. +#define BG_CCM_CCGR0_CG12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG12) >> BP_CCM_CCGR0_CG12) + +//! @brief Format value for bitfield CCM_CCGR0_CG12. +#define BF_CCM_CCGR0_CG12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG12) & BM_CCM_CCGR0_CG12) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG12 field to a new value. +#define BW_CCM_CCGR0_CG12(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG12) | BF_CCM_CCGR0_CG12(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG13[27:26] (RW) + * + * dcic2 clocks (dcic2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG13 (26) //!< Bit position for CCM_CCGR0_CG13. +#define BM_CCM_CCGR0_CG13 (0x0c000000) //!< Bit mask for CCM_CCGR0_CG13. + +//! @brief Get value of CCM_CCGR0_CG13 from a register value. +#define BG_CCM_CCGR0_CG13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG13) >> BP_CCM_CCGR0_CG13) + +//! @brief Format value for bitfield CCM_CCGR0_CG13. +#define BF_CCM_CCGR0_CG13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG13) & BM_CCM_CCGR0_CG13) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG13 field to a new value. +#define BW_CCM_CCGR0_CG13(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG13) | BF_CCM_CCGR0_CG13(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG14[29:28] (RW) + * + * dtcp clocks (dtcp_dtcp_clk_enable) + */ +//@{ +#define BP_CCM_CCGR0_CG14 (28) //!< Bit position for CCM_CCGR0_CG14. +#define BM_CCM_CCGR0_CG14 (0x30000000) //!< Bit mask for CCM_CCGR0_CG14. + +//! @brief Get value of CCM_CCGR0_CG14 from a register value. +#define BG_CCM_CCGR0_CG14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG14) >> BP_CCM_CCGR0_CG14) + +//! @brief Format value for bitfield CCM_CCGR0_CG14. +#define BF_CCM_CCGR0_CG14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG14) & BM_CCM_CCGR0_CG14) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG14 field to a new value. +#define BW_CCM_CCGR0_CG14(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG14) | BF_CCM_CCGR0_CG14(v))) +#endif +//@} + +/*! @name Register CCM_CCGR0, field CG15[31:30] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR0_CG15 (30) //!< Bit position for CCM_CCGR0_CG15. +#define BM_CCM_CCGR0_CG15 (0xc0000000) //!< Bit mask for CCM_CCGR0_CG15. + +//! @brief Get value of CCM_CCGR0_CG15 from a register value. +#define BG_CCM_CCGR0_CG15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR0_CG15) >> BP_CCM_CCGR0_CG15) + +//! @brief Format value for bitfield CCM_CCGR0_CG15. +#define BF_CCM_CCGR0_CG15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR0_CG15) & BM_CCM_CCGR0_CG15) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG15 field to a new value. +#define BW_CCM_CCGR0_CG15(v) (HW_CCM_CCGR0_WR((HW_CCM_CCGR0_RD() & ~BM_CCM_CCGR0_CG15) | BF_CCM_CCGR0_CG15(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCGR1 - CCM Clock Gating Register 1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCGR1 - CCM Clock Gating Register 1 (RW) + * + * Reset value: 0xffffffff + * + * The figure below represents the CCM Clock Gating Register 1(CCM_CCGR1). The clock gating + * Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR + * registers. The number of registers required is according to the number of peripherals in the + * system. + */ +typedef union _hw_ccm_ccgr1 +{ + reg32_t U; + struct _hw_ccm_ccgr1_bitfields + { + unsigned CG0 : 2; //!< [1:0] ecspi1 clocks (ecspi1_clk_enable) + unsigned CG1 : 2; //!< [3:2] ecspi2 clocks (ecspi2_clk_enable) + unsigned CG2 : 2; //!< [5:4] ecspi3 clocks (ecspi3_clk_enable) + unsigned CG3 : 2; //!< [7:6] ecspi4 clocks (ecspi4_clk_enable) + unsigned CG4 : 2; //!< [9:8] ecspi5 clocks (ecspi5_clk_enable) + unsigned CG5 : 2; //!< [11:10] clock (enet_clk_enable) + unsigned CG6 : 2; //!< [13:12] epit1 clocks (epit1_clk_enable) + unsigned CG7 : 2; //!< [15:14] epit2 clocks (epit2_clk_enable) + unsigned CG8 : 2; //!< [17:16] esai clocks (esai_clk_enable) + unsigned CG9 : 2; //!< [19:18] Reserved + unsigned CG10 : 2; //!< [21:20] gpt bus clock (gpt_clk_enable) + unsigned CG11 : 2; //!< [23:22] gpt serial clock (gpt_serial_clk_enable) + unsigned CG12 : 2; //!< [25:24] gpu2d clock (gpu2d_clk_enable) + unsigned CG13 : 2; //!< [27:26] gpu3d clock (gpu3d_clk_enable) + unsigned CG14 : 2; //!< [29:28] Reserved + unsigned CG15 : 2; //!< [31:30] Reserved + } B; +} hw_ccm_ccgr1_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCGR1 register + */ +//@{ +#define HW_CCM_CCGR1_ADDR (REGS_CCM_BASE + 0x6c) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCGR1 (*(volatile hw_ccm_ccgr1_t *) HW_CCM_CCGR1_ADDR) +#define HW_CCM_CCGR1_RD() (HW_CCM_CCGR1.U) +#define HW_CCM_CCGR1_WR(v) (HW_CCM_CCGR1.U = (v)) +#define HW_CCM_CCGR1_SET(v) (HW_CCM_CCGR1_WR(HW_CCM_CCGR1_RD() | (v))) +#define HW_CCM_CCGR1_CLR(v) (HW_CCM_CCGR1_WR(HW_CCM_CCGR1_RD() & ~(v))) +#define HW_CCM_CCGR1_TOG(v) (HW_CCM_CCGR1_WR(HW_CCM_CCGR1_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCGR1 bitfields + */ + +/*! @name Register CCM_CCGR1, field CG0[1:0] (RW) + * + * ecspi1 clocks (ecspi1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG0 (0) //!< Bit position for CCM_CCGR1_CG0. +#define BM_CCM_CCGR1_CG0 (0x00000003) //!< Bit mask for CCM_CCGR1_CG0. + +//! @brief Get value of CCM_CCGR1_CG0 from a register value. +#define BG_CCM_CCGR1_CG0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG0) >> BP_CCM_CCGR1_CG0) + +//! @brief Format value for bitfield CCM_CCGR1_CG0. +#define BF_CCM_CCGR1_CG0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG0) & BM_CCM_CCGR1_CG0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG0 field to a new value. +#define BW_CCM_CCGR1_CG0(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG0) | BF_CCM_CCGR1_CG0(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG1[3:2] (RW) + * + * ecspi2 clocks (ecspi2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG1 (2) //!< Bit position for CCM_CCGR1_CG1. +#define BM_CCM_CCGR1_CG1 (0x0000000c) //!< Bit mask for CCM_CCGR1_CG1. + +//! @brief Get value of CCM_CCGR1_CG1 from a register value. +#define BG_CCM_CCGR1_CG1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG1) >> BP_CCM_CCGR1_CG1) + +//! @brief Format value for bitfield CCM_CCGR1_CG1. +#define BF_CCM_CCGR1_CG1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG1) & BM_CCM_CCGR1_CG1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG1 field to a new value. +#define BW_CCM_CCGR1_CG1(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG1) | BF_CCM_CCGR1_CG1(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG2[5:4] (RW) + * + * ecspi3 clocks (ecspi3_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG2 (4) //!< Bit position for CCM_CCGR1_CG2. +#define BM_CCM_CCGR1_CG2 (0x00000030) //!< Bit mask for CCM_CCGR1_CG2. + +//! @brief Get value of CCM_CCGR1_CG2 from a register value. +#define BG_CCM_CCGR1_CG2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG2) >> BP_CCM_CCGR1_CG2) + +//! @brief Format value for bitfield CCM_CCGR1_CG2. +#define BF_CCM_CCGR1_CG2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG2) & BM_CCM_CCGR1_CG2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG2 field to a new value. +#define BW_CCM_CCGR1_CG2(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG2) | BF_CCM_CCGR1_CG2(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG3[7:6] (RW) + * + * ecspi4 clocks (ecspi4_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG3 (6) //!< Bit position for CCM_CCGR1_CG3. +#define BM_CCM_CCGR1_CG3 (0x000000c0) //!< Bit mask for CCM_CCGR1_CG3. + +//! @brief Get value of CCM_CCGR1_CG3 from a register value. +#define BG_CCM_CCGR1_CG3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG3) >> BP_CCM_CCGR1_CG3) + +//! @brief Format value for bitfield CCM_CCGR1_CG3. +#define BF_CCM_CCGR1_CG3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG3) & BM_CCM_CCGR1_CG3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG3 field to a new value. +#define BW_CCM_CCGR1_CG3(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG3) | BF_CCM_CCGR1_CG3(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG4[9:8] (RW) + * + * ecspi5 clocks (ecspi5_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG4 (8) //!< Bit position for CCM_CCGR1_CG4. +#define BM_CCM_CCGR1_CG4 (0x00000300) //!< Bit mask for CCM_CCGR1_CG4. + +//! @brief Get value of CCM_CCGR1_CG4 from a register value. +#define BG_CCM_CCGR1_CG4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG4) >> BP_CCM_CCGR1_CG4) + +//! @brief Format value for bitfield CCM_CCGR1_CG4. +#define BF_CCM_CCGR1_CG4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG4) & BM_CCM_CCGR1_CG4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG4 field to a new value. +#define BW_CCM_CCGR1_CG4(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG4) | BF_CCM_CCGR1_CG4(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG5[11:10] (RW) + * + * clock (enet_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG5 (10) //!< Bit position for CCM_CCGR1_CG5. +#define BM_CCM_CCGR1_CG5 (0x00000c00) //!< Bit mask for CCM_CCGR1_CG5. + +//! @brief Get value of CCM_CCGR1_CG5 from a register value. +#define BG_CCM_CCGR1_CG5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG5) >> BP_CCM_CCGR1_CG5) + +//! @brief Format value for bitfield CCM_CCGR1_CG5. +#define BF_CCM_CCGR1_CG5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG5) & BM_CCM_CCGR1_CG5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG5 field to a new value. +#define BW_CCM_CCGR1_CG5(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG5) | BF_CCM_CCGR1_CG5(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG6[13:12] (RW) + * + * epit1 clocks (epit1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG6 (12) //!< Bit position for CCM_CCGR1_CG6. +#define BM_CCM_CCGR1_CG6 (0x00003000) //!< Bit mask for CCM_CCGR1_CG6. + +//! @brief Get value of CCM_CCGR1_CG6 from a register value. +#define BG_CCM_CCGR1_CG6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG6) >> BP_CCM_CCGR1_CG6) + +//! @brief Format value for bitfield CCM_CCGR1_CG6. +#define BF_CCM_CCGR1_CG6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG6) & BM_CCM_CCGR1_CG6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG6 field to a new value. +#define BW_CCM_CCGR1_CG6(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG6) | BF_CCM_CCGR1_CG6(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG7[15:14] (RW) + * + * epit2 clocks (epit2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG7 (14) //!< Bit position for CCM_CCGR1_CG7. +#define BM_CCM_CCGR1_CG7 (0x0000c000) //!< Bit mask for CCM_CCGR1_CG7. + +//! @brief Get value of CCM_CCGR1_CG7 from a register value. +#define BG_CCM_CCGR1_CG7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG7) >> BP_CCM_CCGR1_CG7) + +//! @brief Format value for bitfield CCM_CCGR1_CG7. +#define BF_CCM_CCGR1_CG7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG7) & BM_CCM_CCGR1_CG7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG7 field to a new value. +#define BW_CCM_CCGR1_CG7(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG7) | BF_CCM_CCGR1_CG7(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG8[17:16] (RW) + * + * esai clocks (esai_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG8 (16) //!< Bit position for CCM_CCGR1_CG8. +#define BM_CCM_CCGR1_CG8 (0x00030000) //!< Bit mask for CCM_CCGR1_CG8. + +//! @brief Get value of CCM_CCGR1_CG8 from a register value. +#define BG_CCM_CCGR1_CG8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG8) >> BP_CCM_CCGR1_CG8) + +//! @brief Format value for bitfield CCM_CCGR1_CG8. +#define BF_CCM_CCGR1_CG8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG8) & BM_CCM_CCGR1_CG8) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG8 field to a new value. +#define BW_CCM_CCGR1_CG8(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG8) | BF_CCM_CCGR1_CG8(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG9[19:18] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR1_CG9 (18) //!< Bit position for CCM_CCGR1_CG9. +#define BM_CCM_CCGR1_CG9 (0x000c0000) //!< Bit mask for CCM_CCGR1_CG9. + +//! @brief Get value of CCM_CCGR1_CG9 from a register value. +#define BG_CCM_CCGR1_CG9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG9) >> BP_CCM_CCGR1_CG9) + +//! @brief Format value for bitfield CCM_CCGR1_CG9. +#define BF_CCM_CCGR1_CG9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG9) & BM_CCM_CCGR1_CG9) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG9 field to a new value. +#define BW_CCM_CCGR1_CG9(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG9) | BF_CCM_CCGR1_CG9(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG10[21:20] (RW) + * + * gpt bus clock (gpt_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG10 (20) //!< Bit position for CCM_CCGR1_CG10. +#define BM_CCM_CCGR1_CG10 (0x00300000) //!< Bit mask for CCM_CCGR1_CG10. + +//! @brief Get value of CCM_CCGR1_CG10 from a register value. +#define BG_CCM_CCGR1_CG10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG10) >> BP_CCM_CCGR1_CG10) + +//! @brief Format value for bitfield CCM_CCGR1_CG10. +#define BF_CCM_CCGR1_CG10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG10) & BM_CCM_CCGR1_CG10) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG10 field to a new value. +#define BW_CCM_CCGR1_CG10(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG10) | BF_CCM_CCGR1_CG10(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG11[23:22] (RW) + * + * gpt serial clock (gpt_serial_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG11 (22) //!< Bit position for CCM_CCGR1_CG11. +#define BM_CCM_CCGR1_CG11 (0x00c00000) //!< Bit mask for CCM_CCGR1_CG11. + +//! @brief Get value of CCM_CCGR1_CG11 from a register value. +#define BG_CCM_CCGR1_CG11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG11) >> BP_CCM_CCGR1_CG11) + +//! @brief Format value for bitfield CCM_CCGR1_CG11. +#define BF_CCM_CCGR1_CG11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG11) & BM_CCM_CCGR1_CG11) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG11 field to a new value. +#define BW_CCM_CCGR1_CG11(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG11) | BF_CCM_CCGR1_CG11(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG12[25:24] (RW) + * + * gpu2d clock (gpu2d_clk_enable) GPU2D clock cannot be gated without gating OPENVG clock as well. + * Please configure both CG bits (CCM_ANALOG_CCGR1[CG12] and CCM_ANALOG_CCGR3[CG15]), to gate GPU2D. + */ +//@{ +#define BP_CCM_CCGR1_CG12 (24) //!< Bit position for CCM_CCGR1_CG12. +#define BM_CCM_CCGR1_CG12 (0x03000000) //!< Bit mask for CCM_CCGR1_CG12. + +//! @brief Get value of CCM_CCGR1_CG12 from a register value. +#define BG_CCM_CCGR1_CG12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG12) >> BP_CCM_CCGR1_CG12) + +//! @brief Format value for bitfield CCM_CCGR1_CG12. +#define BF_CCM_CCGR1_CG12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG12) & BM_CCM_CCGR1_CG12) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG12 field to a new value. +#define BW_CCM_CCGR1_CG12(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG12) | BF_CCM_CCGR1_CG12(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG13[27:26] (RW) + * + * gpu3d clock (gpu3d_clk_enable) + */ +//@{ +#define BP_CCM_CCGR1_CG13 (26) //!< Bit position for CCM_CCGR1_CG13. +#define BM_CCM_CCGR1_CG13 (0x0c000000) //!< Bit mask for CCM_CCGR1_CG13. + +//! @brief Get value of CCM_CCGR1_CG13 from a register value. +#define BG_CCM_CCGR1_CG13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG13) >> BP_CCM_CCGR1_CG13) + +//! @brief Format value for bitfield CCM_CCGR1_CG13. +#define BF_CCM_CCGR1_CG13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG13) & BM_CCM_CCGR1_CG13) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG13 field to a new value. +#define BW_CCM_CCGR1_CG13(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG13) | BF_CCM_CCGR1_CG13(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG14[29:28] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR1_CG14 (28) //!< Bit position for CCM_CCGR1_CG14. +#define BM_CCM_CCGR1_CG14 (0x30000000) //!< Bit mask for CCM_CCGR1_CG14. + +//! @brief Get value of CCM_CCGR1_CG14 from a register value. +#define BG_CCM_CCGR1_CG14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG14) >> BP_CCM_CCGR1_CG14) + +//! @brief Format value for bitfield CCM_CCGR1_CG14. +#define BF_CCM_CCGR1_CG14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG14) & BM_CCM_CCGR1_CG14) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG14 field to a new value. +#define BW_CCM_CCGR1_CG14(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG14) | BF_CCM_CCGR1_CG14(v))) +#endif +//@} + +/*! @name Register CCM_CCGR1, field CG15[31:30] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR1_CG15 (30) //!< Bit position for CCM_CCGR1_CG15. +#define BM_CCM_CCGR1_CG15 (0xc0000000) //!< Bit mask for CCM_CCGR1_CG15. + +//! @brief Get value of CCM_CCGR1_CG15 from a register value. +#define BG_CCM_CCGR1_CG15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR1_CG15) >> BP_CCM_CCGR1_CG15) + +//! @brief Format value for bitfield CCM_CCGR1_CG15. +#define BF_CCM_CCGR1_CG15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR1_CG15) & BM_CCM_CCGR1_CG15) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG15 field to a new value. +#define BW_CCM_CCGR1_CG15(v) (HW_CCM_CCGR1_WR((HW_CCM_CCGR1_RD() & ~BM_CCM_CCGR1_CG15) | BF_CCM_CCGR1_CG15(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCGR2 - CCM Clock Gating Register 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCGR2 - CCM Clock Gating Register 2 (RW) + * + * Reset value: 0xfc3fffff + * + * The figure below represents the CCM Clock Gating Register 2 (CCM_CCGR2). The clock gating + * Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR + * registers. The number of registers required is according to the number of peripherals in the + * system. + */ +typedef union _hw_ccm_ccgr2 +{ + reg32_t U; + struct _hw_ccm_ccgr2_bitfields + { + unsigned CG0 : 2; //!< [1:0] hdmi_tx_iahbclk, hdmi_tx_ihclk clock (hdmi_tx_iahbclk_enable) + unsigned CG1 : 2; //!< [3:2] Reserved + unsigned CG2 : 2; //!< [5:4] hdmi_tx_isfrclk clock (hdmi_tx_isfrclk_enable) + unsigned CG3 : 2; //!< [7:6] i2c1_serial clock (i2c1_serial_clk_enable) + unsigned CG4 : 2; //!< [9:8] i2c2_serial clock (i2c2_serial_clk_enable) + unsigned CG5 : 2; //!< [11:10] i2c3_serial clock (i2c3_serial_clk_enable) + unsigned CG6 : 2; //!< [13:12] OCOTP_CTRL clock (iim_clk_enable) + unsigned CG7 : 2; //!< [15:14] iomux_ipt_clk_io clock (iomux_ipt_clk_io_enable) + unsigned CG8 : 2; //!< [17:16] ipmux1 clock (ipmux1_clk_enable) + unsigned CG9 : 2; //!< [19:18] ipmux2 clock (ipmux2_clk_enable) + unsigned CG10 : 2; //!< [21:20] ipmux3 clock (ipmux3_clk_enable) + unsigned CG11 : 2; //!< [23:22] ipsync_ip2apb_tzasc1_ipg clocks (ipsync_ip2apb_tzasc1_ipg_master_clk_enable) + unsigned CG12 : 2; //!< [25:24] ipsync_vdoa_ipg clocks (ipsync_ip2apb_tzasc2_ipg clocks) + unsigned CG13 : 2; //!< [27:26] ipsync_vdoa_ipg clocks (ipsync_vdoa_ipg_master_clk_enable) + unsigned CG14 : 2; //!< [29:28] Reserved + unsigned CG15 : 2; //!< [31:30] Reserved + } B; +} hw_ccm_ccgr2_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCGR2 register + */ +//@{ +#define HW_CCM_CCGR2_ADDR (REGS_CCM_BASE + 0x70) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCGR2 (*(volatile hw_ccm_ccgr2_t *) HW_CCM_CCGR2_ADDR) +#define HW_CCM_CCGR2_RD() (HW_CCM_CCGR2.U) +#define HW_CCM_CCGR2_WR(v) (HW_CCM_CCGR2.U = (v)) +#define HW_CCM_CCGR2_SET(v) (HW_CCM_CCGR2_WR(HW_CCM_CCGR2_RD() | (v))) +#define HW_CCM_CCGR2_CLR(v) (HW_CCM_CCGR2_WR(HW_CCM_CCGR2_RD() & ~(v))) +#define HW_CCM_CCGR2_TOG(v) (HW_CCM_CCGR2_WR(HW_CCM_CCGR2_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCGR2 bitfields + */ + +/*! @name Register CCM_CCGR2, field CG0[1:0] (RW) + * + * hdmi_tx_iahbclk, hdmi_tx_ihclk clock (hdmi_tx_iahbclk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG0 (0) //!< Bit position for CCM_CCGR2_CG0. +#define BM_CCM_CCGR2_CG0 (0x00000003) //!< Bit mask for CCM_CCGR2_CG0. + +//! @brief Get value of CCM_CCGR2_CG0 from a register value. +#define BG_CCM_CCGR2_CG0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG0) >> BP_CCM_CCGR2_CG0) + +//! @brief Format value for bitfield CCM_CCGR2_CG0. +#define BF_CCM_CCGR2_CG0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG0) & BM_CCM_CCGR2_CG0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG0 field to a new value. +#define BW_CCM_CCGR2_CG0(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG0) | BF_CCM_CCGR2_CG0(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG1[3:2] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR2_CG1 (2) //!< Bit position for CCM_CCGR2_CG1. +#define BM_CCM_CCGR2_CG1 (0x0000000c) //!< Bit mask for CCM_CCGR2_CG1. + +//! @brief Get value of CCM_CCGR2_CG1 from a register value. +#define BG_CCM_CCGR2_CG1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG1) >> BP_CCM_CCGR2_CG1) + +//! @brief Format value for bitfield CCM_CCGR2_CG1. +#define BF_CCM_CCGR2_CG1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG1) & BM_CCM_CCGR2_CG1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG1 field to a new value. +#define BW_CCM_CCGR2_CG1(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG1) | BF_CCM_CCGR2_CG1(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG2[5:4] (RW) + * + * hdmi_tx_isfrclk clock (hdmi_tx_isfrclk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG2 (4) //!< Bit position for CCM_CCGR2_CG2. +#define BM_CCM_CCGR2_CG2 (0x00000030) //!< Bit mask for CCM_CCGR2_CG2. + +//! @brief Get value of CCM_CCGR2_CG2 from a register value. +#define BG_CCM_CCGR2_CG2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG2) >> BP_CCM_CCGR2_CG2) + +//! @brief Format value for bitfield CCM_CCGR2_CG2. +#define BF_CCM_CCGR2_CG2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG2) & BM_CCM_CCGR2_CG2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG2 field to a new value. +#define BW_CCM_CCGR2_CG2(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG2) | BF_CCM_CCGR2_CG2(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG3[7:6] (RW) + * + * i2c1_serial clock (i2c1_serial_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG3 (6) //!< Bit position for CCM_CCGR2_CG3. +#define BM_CCM_CCGR2_CG3 (0x000000c0) //!< Bit mask for CCM_CCGR2_CG3. + +//! @brief Get value of CCM_CCGR2_CG3 from a register value. +#define BG_CCM_CCGR2_CG3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG3) >> BP_CCM_CCGR2_CG3) + +//! @brief Format value for bitfield CCM_CCGR2_CG3. +#define BF_CCM_CCGR2_CG3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG3) & BM_CCM_CCGR2_CG3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG3 field to a new value. +#define BW_CCM_CCGR2_CG3(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG3) | BF_CCM_CCGR2_CG3(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG4[9:8] (RW) + * + * i2c2_serial clock (i2c2_serial_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG4 (8) //!< Bit position for CCM_CCGR2_CG4. +#define BM_CCM_CCGR2_CG4 (0x00000300) //!< Bit mask for CCM_CCGR2_CG4. + +//! @brief Get value of CCM_CCGR2_CG4 from a register value. +#define BG_CCM_CCGR2_CG4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG4) >> BP_CCM_CCGR2_CG4) + +//! @brief Format value for bitfield CCM_CCGR2_CG4. +#define BF_CCM_CCGR2_CG4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG4) & BM_CCM_CCGR2_CG4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG4 field to a new value. +#define BW_CCM_CCGR2_CG4(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG4) | BF_CCM_CCGR2_CG4(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG5[11:10] (RW) + * + * i2c3_serial clock (i2c3_serial_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG5 (10) //!< Bit position for CCM_CCGR2_CG5. +#define BM_CCM_CCGR2_CG5 (0x00000c00) //!< Bit mask for CCM_CCGR2_CG5. + +//! @brief Get value of CCM_CCGR2_CG5 from a register value. +#define BG_CCM_CCGR2_CG5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG5) >> BP_CCM_CCGR2_CG5) + +//! @brief Format value for bitfield CCM_CCGR2_CG5. +#define BF_CCM_CCGR2_CG5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG5) & BM_CCM_CCGR2_CG5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG5 field to a new value. +#define BW_CCM_CCGR2_CG5(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG5) | BF_CCM_CCGR2_CG5(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG6[13:12] (RW) + * + * OCOTP_CTRL clock (iim_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG6 (12) //!< Bit position for CCM_CCGR2_CG6. +#define BM_CCM_CCGR2_CG6 (0x00003000) //!< Bit mask for CCM_CCGR2_CG6. + +//! @brief Get value of CCM_CCGR2_CG6 from a register value. +#define BG_CCM_CCGR2_CG6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG6) >> BP_CCM_CCGR2_CG6) + +//! @brief Format value for bitfield CCM_CCGR2_CG6. +#define BF_CCM_CCGR2_CG6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG6) & BM_CCM_CCGR2_CG6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG6 field to a new value. +#define BW_CCM_CCGR2_CG6(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG6) | BF_CCM_CCGR2_CG6(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG7[15:14] (RW) + * + * iomux_ipt_clk_io clock (iomux_ipt_clk_io_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG7 (14) //!< Bit position for CCM_CCGR2_CG7. +#define BM_CCM_CCGR2_CG7 (0x0000c000) //!< Bit mask for CCM_CCGR2_CG7. + +//! @brief Get value of CCM_CCGR2_CG7 from a register value. +#define BG_CCM_CCGR2_CG7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG7) >> BP_CCM_CCGR2_CG7) + +//! @brief Format value for bitfield CCM_CCGR2_CG7. +#define BF_CCM_CCGR2_CG7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG7) & BM_CCM_CCGR2_CG7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG7 field to a new value. +#define BW_CCM_CCGR2_CG7(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG7) | BF_CCM_CCGR2_CG7(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG8[17:16] (RW) + * + * ipmux1 clock (ipmux1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG8 (16) //!< Bit position for CCM_CCGR2_CG8. +#define BM_CCM_CCGR2_CG8 (0x00030000) //!< Bit mask for CCM_CCGR2_CG8. + +//! @brief Get value of CCM_CCGR2_CG8 from a register value. +#define BG_CCM_CCGR2_CG8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG8) >> BP_CCM_CCGR2_CG8) + +//! @brief Format value for bitfield CCM_CCGR2_CG8. +#define BF_CCM_CCGR2_CG8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG8) & BM_CCM_CCGR2_CG8) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG8 field to a new value. +#define BW_CCM_CCGR2_CG8(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG8) | BF_CCM_CCGR2_CG8(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG9[19:18] (RW) + * + * ipmux2 clock (ipmux2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG9 (18) //!< Bit position for CCM_CCGR2_CG9. +#define BM_CCM_CCGR2_CG9 (0x000c0000) //!< Bit mask for CCM_CCGR2_CG9. + +//! @brief Get value of CCM_CCGR2_CG9 from a register value. +#define BG_CCM_CCGR2_CG9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG9) >> BP_CCM_CCGR2_CG9) + +//! @brief Format value for bitfield CCM_CCGR2_CG9. +#define BF_CCM_CCGR2_CG9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG9) & BM_CCM_CCGR2_CG9) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG9 field to a new value. +#define BW_CCM_CCGR2_CG9(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG9) | BF_CCM_CCGR2_CG9(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG10[21:20] (RW) + * + * ipmux3 clock (ipmux3_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG10 (20) //!< Bit position for CCM_CCGR2_CG10. +#define BM_CCM_CCGR2_CG10 (0x00300000) //!< Bit mask for CCM_CCGR2_CG10. + +//! @brief Get value of CCM_CCGR2_CG10 from a register value. +#define BG_CCM_CCGR2_CG10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG10) >> BP_CCM_CCGR2_CG10) + +//! @brief Format value for bitfield CCM_CCGR2_CG10. +#define BF_CCM_CCGR2_CG10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG10) & BM_CCM_CCGR2_CG10) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG10 field to a new value. +#define BW_CCM_CCGR2_CG10(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG10) | BF_CCM_CCGR2_CG10(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG11[23:22] (RW) + * + * ipsync_ip2apb_tzasc1_ipg clocks (ipsync_ip2apb_tzasc1_ipg_master_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG11 (22) //!< Bit position for CCM_CCGR2_CG11. +#define BM_CCM_CCGR2_CG11 (0x00c00000) //!< Bit mask for CCM_CCGR2_CG11. + +//! @brief Get value of CCM_CCGR2_CG11 from a register value. +#define BG_CCM_CCGR2_CG11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG11) >> BP_CCM_CCGR2_CG11) + +//! @brief Format value for bitfield CCM_CCGR2_CG11. +#define BF_CCM_CCGR2_CG11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG11) & BM_CCM_CCGR2_CG11) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG11 field to a new value. +#define BW_CCM_CCGR2_CG11(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG11) | BF_CCM_CCGR2_CG11(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG12[25:24] (RW) + * + * ipsync_vdoa_ipg clocks (ipsync_ip2apb_tzasc2_ipg clocks) + */ +//@{ +#define BP_CCM_CCGR2_CG12 (24) //!< Bit position for CCM_CCGR2_CG12. +#define BM_CCM_CCGR2_CG12 (0x03000000) //!< Bit mask for CCM_CCGR2_CG12. + +//! @brief Get value of CCM_CCGR2_CG12 from a register value. +#define BG_CCM_CCGR2_CG12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG12) >> BP_CCM_CCGR2_CG12) + +//! @brief Format value for bitfield CCM_CCGR2_CG12. +#define BF_CCM_CCGR2_CG12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG12) & BM_CCM_CCGR2_CG12) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG12 field to a new value. +#define BW_CCM_CCGR2_CG12(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG12) | BF_CCM_CCGR2_CG12(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG13[27:26] (RW) + * + * ipsync_vdoa_ipg clocks (ipsync_vdoa_ipg_master_clk_enable) + */ +//@{ +#define BP_CCM_CCGR2_CG13 (26) //!< Bit position for CCM_CCGR2_CG13. +#define BM_CCM_CCGR2_CG13 (0x0c000000) //!< Bit mask for CCM_CCGR2_CG13. + +//! @brief Get value of CCM_CCGR2_CG13 from a register value. +#define BG_CCM_CCGR2_CG13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG13) >> BP_CCM_CCGR2_CG13) + +//! @brief Format value for bitfield CCM_CCGR2_CG13. +#define BF_CCM_CCGR2_CG13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG13) & BM_CCM_CCGR2_CG13) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG13 field to a new value. +#define BW_CCM_CCGR2_CG13(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG13) | BF_CCM_CCGR2_CG13(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG14[29:28] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR2_CG14 (28) //!< Bit position for CCM_CCGR2_CG14. +#define BM_CCM_CCGR2_CG14 (0x30000000) //!< Bit mask for CCM_CCGR2_CG14. + +//! @brief Get value of CCM_CCGR2_CG14 from a register value. +#define BG_CCM_CCGR2_CG14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG14) >> BP_CCM_CCGR2_CG14) + +//! @brief Format value for bitfield CCM_CCGR2_CG14. +#define BF_CCM_CCGR2_CG14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG14) & BM_CCM_CCGR2_CG14) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG14 field to a new value. +#define BW_CCM_CCGR2_CG14(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG14) | BF_CCM_CCGR2_CG14(v))) +#endif +//@} + +/*! @name Register CCM_CCGR2, field CG15[31:30] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR2_CG15 (30) //!< Bit position for CCM_CCGR2_CG15. +#define BM_CCM_CCGR2_CG15 (0xc0000000) //!< Bit mask for CCM_CCGR2_CG15. + +//! @brief Get value of CCM_CCGR2_CG15 from a register value. +#define BG_CCM_CCGR2_CG15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR2_CG15) >> BP_CCM_CCGR2_CG15) + +//! @brief Format value for bitfield CCM_CCGR2_CG15. +#define BF_CCM_CCGR2_CG15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR2_CG15) & BM_CCM_CCGR2_CG15) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG15 field to a new value. +#define BW_CCM_CCGR2_CG15(v) (HW_CCM_CCGR2_WR((HW_CCM_CCGR2_RD() & ~BM_CCM_CCGR2_CG15) | BF_CCM_CCGR2_CG15(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCGR3 - CCM Clock Gating Register 3 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCGR3 - CCM Clock Gating Register 3 (RW) + * + * Reset value: 0xffffffff + * + * The figure below represents the CCM Clock Gating Register 3 (CCM_CCGR3). The clock gating + * Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR + * registers. The number of registers required is according to the number of peripherals in the + * system. + */ +typedef union _hw_ccm_ccgr3 +{ + reg32_t U; + struct _hw_ccm_ccgr3_bitfields + { + unsigned CG0 : 2; //!< [1:0] ipu1_ipu clock (ipu1_ipu_clk_enable) + unsigned CG1 : 2; //!< [3:2] ipu1_ipu_di0 clock (ipu1_ipu_di0_clk_enable) + unsigned CG2 : 2; //!< [5:4] ipu1_ipu_di1 clock (ipu1_ipu_di1_clk_enable) + unsigned CG3 : 2; //!< [7:6] epdc/lcdif/pxp clock (epdc_axi_clk_enable) + unsigned CG4 : 2; //!< [9:8] lcdif_pix clock (lcdif_pix_clk_enable) + unsigned CG5 : 2; //!< [11:10] epdc_pix clock (epdc_pix_clk_enable) + unsigned CG6 : 2; //!< [13:12] ldb_di0 clock (ldb_di0_clk_enable) + unsigned CG7 : 2; //!< [15:14] ldb_di1 clock (ldb_di1_clk_enable) + unsigned CG8 : 2; //!< [17:16] mipi_core_cfg clock (mipi_core_cfg_clk_enable) + unsigned CG9 : 2; //!< [19:18] mlb clock (mlb_clk_enable) + unsigned CG10 : 2; //!< [21:20] mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable) + unsigned CG11 : 2; //!< [23:22] mmdc_core_aclk_fast_core_p1 clock (mmdc_core_aclk_fast_core_p1_enable) + unsigned CG12 : 2; //!< [25:24] mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable) + unsigned CG13 : 2; //!< [27:26] mmdc_core_ipg_clk_p1 clock (mmdc_core_ipg_clk_p1_enable) + unsigned CG14 : 2; //!< [29:28] ocram clock (ocram_clk_enable) + unsigned CG15 : 2; //!< [31:30] openvgaxiclk clock (openvgaxiclk_clk_root_enable) + } B; +} hw_ccm_ccgr3_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCGR3 register + */ +//@{ +#define HW_CCM_CCGR3_ADDR (REGS_CCM_BASE + 0x74) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCGR3 (*(volatile hw_ccm_ccgr3_t *) HW_CCM_CCGR3_ADDR) +#define HW_CCM_CCGR3_RD() (HW_CCM_CCGR3.U) +#define HW_CCM_CCGR3_WR(v) (HW_CCM_CCGR3.U = (v)) +#define HW_CCM_CCGR3_SET(v) (HW_CCM_CCGR3_WR(HW_CCM_CCGR3_RD() | (v))) +#define HW_CCM_CCGR3_CLR(v) (HW_CCM_CCGR3_WR(HW_CCM_CCGR3_RD() & ~(v))) +#define HW_CCM_CCGR3_TOG(v) (HW_CCM_CCGR3_WR(HW_CCM_CCGR3_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCGR3 bitfields + */ + +/*! @name Register CCM_CCGR3, field CG0[1:0] (RW) + * + * ipu1_ipu clock (ipu1_ipu_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG0 (0) //!< Bit position for CCM_CCGR3_CG0. +#define BM_CCM_CCGR3_CG0 (0x00000003) //!< Bit mask for CCM_CCGR3_CG0. + +//! @brief Get value of CCM_CCGR3_CG0 from a register value. +#define BG_CCM_CCGR3_CG0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG0) >> BP_CCM_CCGR3_CG0) + +//! @brief Format value for bitfield CCM_CCGR3_CG0. +#define BF_CCM_CCGR3_CG0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG0) & BM_CCM_CCGR3_CG0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG0 field to a new value. +#define BW_CCM_CCGR3_CG0(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG0) | BF_CCM_CCGR3_CG0(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG1[3:2] (RW) + * + * ipu1_ipu_di0 clock (ipu1_ipu_di0_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG1 (2) //!< Bit position for CCM_CCGR3_CG1. +#define BM_CCM_CCGR3_CG1 (0x0000000c) //!< Bit mask for CCM_CCGR3_CG1. + +//! @brief Get value of CCM_CCGR3_CG1 from a register value. +#define BG_CCM_CCGR3_CG1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG1) >> BP_CCM_CCGR3_CG1) + +//! @brief Format value for bitfield CCM_CCGR3_CG1. +#define BF_CCM_CCGR3_CG1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG1) & BM_CCM_CCGR3_CG1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG1 field to a new value. +#define BW_CCM_CCGR3_CG1(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG1) | BF_CCM_CCGR3_CG1(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG2[5:4] (RW) + * + * ipu1_ipu_di1 clock (ipu1_ipu_di1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG2 (4) //!< Bit position for CCM_CCGR3_CG2. +#define BM_CCM_CCGR3_CG2 (0x00000030) //!< Bit mask for CCM_CCGR3_CG2. + +//! @brief Get value of CCM_CCGR3_CG2 from a register value. +#define BG_CCM_CCGR3_CG2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG2) >> BP_CCM_CCGR3_CG2) + +//! @brief Format value for bitfield CCM_CCGR3_CG2. +#define BF_CCM_CCGR3_CG2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG2) & BM_CCM_CCGR3_CG2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG2 field to a new value. +#define BW_CCM_CCGR3_CG2(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG2) | BF_CCM_CCGR3_CG2(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG3[7:6] (RW) + * + * epdc/lcdif/pxp clock (epdc_axi_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG3 (6) //!< Bit position for CCM_CCGR3_CG3. +#define BM_CCM_CCGR3_CG3 (0x000000c0) //!< Bit mask for CCM_CCGR3_CG3. + +//! @brief Get value of CCM_CCGR3_CG3 from a register value. +#define BG_CCM_CCGR3_CG3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG3) >> BP_CCM_CCGR3_CG3) + +//! @brief Format value for bitfield CCM_CCGR3_CG3. +#define BF_CCM_CCGR3_CG3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG3) & BM_CCM_CCGR3_CG3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG3 field to a new value. +#define BW_CCM_CCGR3_CG3(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG3) | BF_CCM_CCGR3_CG3(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG4[9:8] (RW) + * + * lcdif_pix clock (lcdif_pix_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG4 (8) //!< Bit position for CCM_CCGR3_CG4. +#define BM_CCM_CCGR3_CG4 (0x00000300) //!< Bit mask for CCM_CCGR3_CG4. + +//! @brief Get value of CCM_CCGR3_CG4 from a register value. +#define BG_CCM_CCGR3_CG4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG4) >> BP_CCM_CCGR3_CG4) + +//! @brief Format value for bitfield CCM_CCGR3_CG4. +#define BF_CCM_CCGR3_CG4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG4) & BM_CCM_CCGR3_CG4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG4 field to a new value. +#define BW_CCM_CCGR3_CG4(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG4) | BF_CCM_CCGR3_CG4(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG5[11:10] (RW) + * + * epdc_pix clock (epdc_pix_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG5 (10) //!< Bit position for CCM_CCGR3_CG5. +#define BM_CCM_CCGR3_CG5 (0x00000c00) //!< Bit mask for CCM_CCGR3_CG5. + +//! @brief Get value of CCM_CCGR3_CG5 from a register value. +#define BG_CCM_CCGR3_CG5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG5) >> BP_CCM_CCGR3_CG5) + +//! @brief Format value for bitfield CCM_CCGR3_CG5. +#define BF_CCM_CCGR3_CG5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG5) & BM_CCM_CCGR3_CG5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG5 field to a new value. +#define BW_CCM_CCGR3_CG5(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG5) | BF_CCM_CCGR3_CG5(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG6[13:12] (RW) + * + * ldb_di0 clock (ldb_di0_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG6 (12) //!< Bit position for CCM_CCGR3_CG6. +#define BM_CCM_CCGR3_CG6 (0x00003000) //!< Bit mask for CCM_CCGR3_CG6. + +//! @brief Get value of CCM_CCGR3_CG6 from a register value. +#define BG_CCM_CCGR3_CG6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG6) >> BP_CCM_CCGR3_CG6) + +//! @brief Format value for bitfield CCM_CCGR3_CG6. +#define BF_CCM_CCGR3_CG6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG6) & BM_CCM_CCGR3_CG6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG6 field to a new value. +#define BW_CCM_CCGR3_CG6(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG6) | BF_CCM_CCGR3_CG6(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG7[15:14] (RW) + * + * ldb_di1 clock (ldb_di1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG7 (14) //!< Bit position for CCM_CCGR3_CG7. +#define BM_CCM_CCGR3_CG7 (0x0000c000) //!< Bit mask for CCM_CCGR3_CG7. + +//! @brief Get value of CCM_CCGR3_CG7 from a register value. +#define BG_CCM_CCGR3_CG7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG7) >> BP_CCM_CCGR3_CG7) + +//! @brief Format value for bitfield CCM_CCGR3_CG7. +#define BF_CCM_CCGR3_CG7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG7) & BM_CCM_CCGR3_CG7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG7 field to a new value. +#define BW_CCM_CCGR3_CG7(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG7) | BF_CCM_CCGR3_CG7(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG8[17:16] (RW) + * + * mipi_core_cfg clock (mipi_core_cfg_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG8 (16) //!< Bit position for CCM_CCGR3_CG8. +#define BM_CCM_CCGR3_CG8 (0x00030000) //!< Bit mask for CCM_CCGR3_CG8. + +//! @brief Get value of CCM_CCGR3_CG8 from a register value. +#define BG_CCM_CCGR3_CG8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG8) >> BP_CCM_CCGR3_CG8) + +//! @brief Format value for bitfield CCM_CCGR3_CG8. +#define BF_CCM_CCGR3_CG8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG8) & BM_CCM_CCGR3_CG8) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG8 field to a new value. +#define BW_CCM_CCGR3_CG8(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG8) | BF_CCM_CCGR3_CG8(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG9[19:18] (RW) + * + * mlb clock (mlb_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG9 (18) //!< Bit position for CCM_CCGR3_CG9. +#define BM_CCM_CCGR3_CG9 (0x000c0000) //!< Bit mask for CCM_CCGR3_CG9. + +//! @brief Get value of CCM_CCGR3_CG9 from a register value. +#define BG_CCM_CCGR3_CG9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG9) >> BP_CCM_CCGR3_CG9) + +//! @brief Format value for bitfield CCM_CCGR3_CG9. +#define BF_CCM_CCGR3_CG9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG9) & BM_CCM_CCGR3_CG9) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG9 field to a new value. +#define BW_CCM_CCGR3_CG9(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG9) | BF_CCM_CCGR3_CG9(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG10[21:20] (RW) + * + * mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG10 (20) //!< Bit position for CCM_CCGR3_CG10. +#define BM_CCM_CCGR3_CG10 (0x00300000) //!< Bit mask for CCM_CCGR3_CG10. + +//! @brief Get value of CCM_CCGR3_CG10 from a register value. +#define BG_CCM_CCGR3_CG10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG10) >> BP_CCM_CCGR3_CG10) + +//! @brief Format value for bitfield CCM_CCGR3_CG10. +#define BF_CCM_CCGR3_CG10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG10) & BM_CCM_CCGR3_CG10) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG10 field to a new value. +#define BW_CCM_CCGR3_CG10(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG10) | BF_CCM_CCGR3_CG10(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG11[23:22] (RW) + * + * mmdc_core_aclk_fast_core_p1 clock (mmdc_core_aclk_fast_core_p1_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG11 (22) //!< Bit position for CCM_CCGR3_CG11. +#define BM_CCM_CCGR3_CG11 (0x00c00000) //!< Bit mask for CCM_CCGR3_CG11. + +//! @brief Get value of CCM_CCGR3_CG11 from a register value. +#define BG_CCM_CCGR3_CG11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG11) >> BP_CCM_CCGR3_CG11) + +//! @brief Format value for bitfield CCM_CCGR3_CG11. +#define BF_CCM_CCGR3_CG11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG11) & BM_CCM_CCGR3_CG11) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG11 field to a new value. +#define BW_CCM_CCGR3_CG11(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG11) | BF_CCM_CCGR3_CG11(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG12[25:24] (RW) + * + * mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG12 (24) //!< Bit position for CCM_CCGR3_CG12. +#define BM_CCM_CCGR3_CG12 (0x03000000) //!< Bit mask for CCM_CCGR3_CG12. + +//! @brief Get value of CCM_CCGR3_CG12 from a register value. +#define BG_CCM_CCGR3_CG12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG12) >> BP_CCM_CCGR3_CG12) + +//! @brief Format value for bitfield CCM_CCGR3_CG12. +#define BF_CCM_CCGR3_CG12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG12) & BM_CCM_CCGR3_CG12) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG12 field to a new value. +#define BW_CCM_CCGR3_CG12(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG12) | BF_CCM_CCGR3_CG12(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG13[27:26] (RW) + * + * mmdc_core_ipg_clk_p1 clock (mmdc_core_ipg_clk_p1_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG13 (26) //!< Bit position for CCM_CCGR3_CG13. +#define BM_CCM_CCGR3_CG13 (0x0c000000) //!< Bit mask for CCM_CCGR3_CG13. + +//! @brief Get value of CCM_CCGR3_CG13 from a register value. +#define BG_CCM_CCGR3_CG13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG13) >> BP_CCM_CCGR3_CG13) + +//! @brief Format value for bitfield CCM_CCGR3_CG13. +#define BF_CCM_CCGR3_CG13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG13) & BM_CCM_CCGR3_CG13) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG13 field to a new value. +#define BW_CCM_CCGR3_CG13(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG13) | BF_CCM_CCGR3_CG13(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG14[29:28] (RW) + * + * ocram clock (ocram_clk_enable) + */ +//@{ +#define BP_CCM_CCGR3_CG14 (28) //!< Bit position for CCM_CCGR3_CG14. +#define BM_CCM_CCGR3_CG14 (0x30000000) //!< Bit mask for CCM_CCGR3_CG14. + +//! @brief Get value of CCM_CCGR3_CG14 from a register value. +#define BG_CCM_CCGR3_CG14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG14) >> BP_CCM_CCGR3_CG14) + +//! @brief Format value for bitfield CCM_CCGR3_CG14. +#define BF_CCM_CCGR3_CG14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG14) & BM_CCM_CCGR3_CG14) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG14 field to a new value. +#define BW_CCM_CCGR3_CG14(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG14) | BF_CCM_CCGR3_CG14(v))) +#endif +//@} + +/*! @name Register CCM_CCGR3, field CG15[31:30] (RW) + * + * openvgaxiclk clock (openvgaxiclk_clk_root_enable) OPENVG clock cannot be gated without gating + * GPU2D clock as well. Please configure both CG bits (CCM_ANALOG_CCGR1[CG12] and + * CCM_ANALOG_CCGR3[CG15]) to gate OPENVG. + */ +//@{ +#define BP_CCM_CCGR3_CG15 (30) //!< Bit position for CCM_CCGR3_CG15. +#define BM_CCM_CCGR3_CG15 (0xc0000000) //!< Bit mask for CCM_CCGR3_CG15. + +//! @brief Get value of CCM_CCGR3_CG15 from a register value. +#define BG_CCM_CCGR3_CG15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR3_CG15) >> BP_CCM_CCGR3_CG15) + +//! @brief Format value for bitfield CCM_CCGR3_CG15. +#define BF_CCM_CCGR3_CG15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR3_CG15) & BM_CCM_CCGR3_CG15) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG15 field to a new value. +#define BW_CCM_CCGR3_CG15(v) (HW_CCM_CCGR3_WR((HW_CCM_CCGR3_RD() & ~BM_CCM_CCGR3_CG15) | BF_CCM_CCGR3_CG15(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCGR4 - CCM Clock Gating Register 4 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCGR4 - CCM Clock Gating Register 4 (RW) + * + * Reset value: 0xffffffff + * + * The figure below represents the CCM Clock Gating Register 4 (CCM_CCGR4). The clock gating + * Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR + * registers. The number of registers required is according to the number of peripherals in the + * system. + */ +typedef union _hw_ccm_ccgr4 +{ + reg32_t U; + struct _hw_ccm_ccgr4_bitfields + { + unsigned CG0 : 2; //!< [1:0] 125M clocks (125M_root_enable) + unsigned CG1 : 2; //!< [3:2] Reserved. + unsigned CG2 : 2; //!< [5:4] Reserved. + unsigned CG3 : 2; //!< [7:6] Reserved. + unsigned CG4 : 2; //!< [9:8] pl301_mx6qfast1_s133 clock (pl301_mx6qfast1_s133clk_enable) + unsigned CG5 : 2; //!< [11:10] Reserved + unsigned CG6 : 2; //!< [13:12] pl301_mx6qper1_bch clocks (pl301_mx6qper1_bchclk_enable) + unsigned CG7 : 2; //!< [15:14] pl301_mx6qper2_mainclk_enable (pl301_mx6qper2_mainclk_enable) + unsigned CG8 : 2; //!< [17:16] pwm1 clocks (pwm1_clk_enable) + unsigned CG9 : 2; //!< [19:18] pwm2 clocks (pwm2_clk_enable) + unsigned CG10 : 2; //!< [21:20] pwm3 clocks (pwm3_clk_enable) + unsigned CG11 : 2; //!< [23:22] pwm4 clocks (pwm4_clk_enable) + unsigned CG12 : 2; //!< [25:24] rawnand_u_bch_input_apb clock (rawnand_u_bch_input_apb_clk_enable) + unsigned CG13 : 2; //!< [27:26] rawnand_u_gpmi_bch_input_bch clock (rawnand_u_gpmi_bch_input_bch_clk_enable) + unsigned CG14 : 2; //!< [29:28] rawnand_u_gpmi_bch_input_gpmi_io clock (rawnand_u_gpmi_bch_input_gpmi_io_clk_enable) + unsigned CG15 : 2; //!< [31:30] rawnand_u_gpmi_input_apb clock rawnand_u_gpmi_input_apb_clk_enable) + } B; +} hw_ccm_ccgr4_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCGR4 register + */ +//@{ +#define HW_CCM_CCGR4_ADDR (REGS_CCM_BASE + 0x78) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCGR4 (*(volatile hw_ccm_ccgr4_t *) HW_CCM_CCGR4_ADDR) +#define HW_CCM_CCGR4_RD() (HW_CCM_CCGR4.U) +#define HW_CCM_CCGR4_WR(v) (HW_CCM_CCGR4.U = (v)) +#define HW_CCM_CCGR4_SET(v) (HW_CCM_CCGR4_WR(HW_CCM_CCGR4_RD() | (v))) +#define HW_CCM_CCGR4_CLR(v) (HW_CCM_CCGR4_WR(HW_CCM_CCGR4_RD() & ~(v))) +#define HW_CCM_CCGR4_TOG(v) (HW_CCM_CCGR4_WR(HW_CCM_CCGR4_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCGR4 bitfields + */ + +/*! @name Register CCM_CCGR4, field CG0[1:0] (RW) + * + * 125M clocks (125M_root_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG0 (0) //!< Bit position for CCM_CCGR4_CG0. +#define BM_CCM_CCGR4_CG0 (0x00000003) //!< Bit mask for CCM_CCGR4_CG0. + +//! @brief Get value of CCM_CCGR4_CG0 from a register value. +#define BG_CCM_CCGR4_CG0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG0) >> BP_CCM_CCGR4_CG0) + +//! @brief Format value for bitfield CCM_CCGR4_CG0. +#define BF_CCM_CCGR4_CG0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG0) & BM_CCM_CCGR4_CG0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG0 field to a new value. +#define BW_CCM_CCGR4_CG0(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG0) | BF_CCM_CCGR4_CG0(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG1[3:2] (RW) + * + * Reserved. + */ +//@{ +#define BP_CCM_CCGR4_CG1 (2) //!< Bit position for CCM_CCGR4_CG1. +#define BM_CCM_CCGR4_CG1 (0x0000000c) //!< Bit mask for CCM_CCGR4_CG1. + +//! @brief Get value of CCM_CCGR4_CG1 from a register value. +#define BG_CCM_CCGR4_CG1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG1) >> BP_CCM_CCGR4_CG1) + +//! @brief Format value for bitfield CCM_CCGR4_CG1. +#define BF_CCM_CCGR4_CG1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG1) & BM_CCM_CCGR4_CG1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG1 field to a new value. +#define BW_CCM_CCGR4_CG1(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG1) | BF_CCM_CCGR4_CG1(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG2[5:4] (RW) + * + * Reserved. + */ +//@{ +#define BP_CCM_CCGR4_CG2 (4) //!< Bit position for CCM_CCGR4_CG2. +#define BM_CCM_CCGR4_CG2 (0x00000030) //!< Bit mask for CCM_CCGR4_CG2. + +//! @brief Get value of CCM_CCGR4_CG2 from a register value. +#define BG_CCM_CCGR4_CG2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG2) >> BP_CCM_CCGR4_CG2) + +//! @brief Format value for bitfield CCM_CCGR4_CG2. +#define BF_CCM_CCGR4_CG2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG2) & BM_CCM_CCGR4_CG2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG2 field to a new value. +#define BW_CCM_CCGR4_CG2(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG2) | BF_CCM_CCGR4_CG2(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG3[7:6] (RW) + * + * Reserved. + */ +//@{ +#define BP_CCM_CCGR4_CG3 (6) //!< Bit position for CCM_CCGR4_CG3. +#define BM_CCM_CCGR4_CG3 (0x000000c0) //!< Bit mask for CCM_CCGR4_CG3. + +//! @brief Get value of CCM_CCGR4_CG3 from a register value. +#define BG_CCM_CCGR4_CG3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG3) >> BP_CCM_CCGR4_CG3) + +//! @brief Format value for bitfield CCM_CCGR4_CG3. +#define BF_CCM_CCGR4_CG3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG3) & BM_CCM_CCGR4_CG3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG3 field to a new value. +#define BW_CCM_CCGR4_CG3(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG3) | BF_CCM_CCGR4_CG3(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG4[9:8] (RW) + * + * pl301_mx6qfast1_s133 clock (pl301_mx6qfast1_s133clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG4 (8) //!< Bit position for CCM_CCGR4_CG4. +#define BM_CCM_CCGR4_CG4 (0x00000300) //!< Bit mask for CCM_CCGR4_CG4. + +//! @brief Get value of CCM_CCGR4_CG4 from a register value. +#define BG_CCM_CCGR4_CG4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG4) >> BP_CCM_CCGR4_CG4) + +//! @brief Format value for bitfield CCM_CCGR4_CG4. +#define BF_CCM_CCGR4_CG4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG4) & BM_CCM_CCGR4_CG4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG4 field to a new value. +#define BW_CCM_CCGR4_CG4(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG4) | BF_CCM_CCGR4_CG4(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG5[11:10] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR4_CG5 (10) //!< Bit position for CCM_CCGR4_CG5. +#define BM_CCM_CCGR4_CG5 (0x00000c00) //!< Bit mask for CCM_CCGR4_CG5. + +//! @brief Get value of CCM_CCGR4_CG5 from a register value. +#define BG_CCM_CCGR4_CG5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG5) >> BP_CCM_CCGR4_CG5) + +//! @brief Format value for bitfield CCM_CCGR4_CG5. +#define BF_CCM_CCGR4_CG5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG5) & BM_CCM_CCGR4_CG5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG5 field to a new value. +#define BW_CCM_CCGR4_CG5(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG5) | BF_CCM_CCGR4_CG5(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG6[13:12] (RW) + * + * pl301_mx6qper1_bch clocks (pl301_mx6qper1_bchclk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG6 (12) //!< Bit position for CCM_CCGR4_CG6. +#define BM_CCM_CCGR4_CG6 (0x00003000) //!< Bit mask for CCM_CCGR4_CG6. + +//! @brief Get value of CCM_CCGR4_CG6 from a register value. +#define BG_CCM_CCGR4_CG6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG6) >> BP_CCM_CCGR4_CG6) + +//! @brief Format value for bitfield CCM_CCGR4_CG6. +#define BF_CCM_CCGR4_CG6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG6) & BM_CCM_CCGR4_CG6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG6 field to a new value. +#define BW_CCM_CCGR4_CG6(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG6) | BF_CCM_CCGR4_CG6(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG7[15:14] (RW) + * + * pl301_mx6qper2_mainclk_enable (pl301_mx6qper2_mainclk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG7 (14) //!< Bit position for CCM_CCGR4_CG7. +#define BM_CCM_CCGR4_CG7 (0x0000c000) //!< Bit mask for CCM_CCGR4_CG7. + +//! @brief Get value of CCM_CCGR4_CG7 from a register value. +#define BG_CCM_CCGR4_CG7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG7) >> BP_CCM_CCGR4_CG7) + +//! @brief Format value for bitfield CCM_CCGR4_CG7. +#define BF_CCM_CCGR4_CG7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG7) & BM_CCM_CCGR4_CG7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG7 field to a new value. +#define BW_CCM_CCGR4_CG7(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG7) | BF_CCM_CCGR4_CG7(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG8[17:16] (RW) + * + * pwm1 clocks (pwm1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG8 (16) //!< Bit position for CCM_CCGR4_CG8. +#define BM_CCM_CCGR4_CG8 (0x00030000) //!< Bit mask for CCM_CCGR4_CG8. + +//! @brief Get value of CCM_CCGR4_CG8 from a register value. +#define BG_CCM_CCGR4_CG8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG8) >> BP_CCM_CCGR4_CG8) + +//! @brief Format value for bitfield CCM_CCGR4_CG8. +#define BF_CCM_CCGR4_CG8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG8) & BM_CCM_CCGR4_CG8) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG8 field to a new value. +#define BW_CCM_CCGR4_CG8(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG8) | BF_CCM_CCGR4_CG8(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG9[19:18] (RW) + * + * pwm2 clocks (pwm2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG9 (18) //!< Bit position for CCM_CCGR4_CG9. +#define BM_CCM_CCGR4_CG9 (0x000c0000) //!< Bit mask for CCM_CCGR4_CG9. + +//! @brief Get value of CCM_CCGR4_CG9 from a register value. +#define BG_CCM_CCGR4_CG9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG9) >> BP_CCM_CCGR4_CG9) + +//! @brief Format value for bitfield CCM_CCGR4_CG9. +#define BF_CCM_CCGR4_CG9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG9) & BM_CCM_CCGR4_CG9) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG9 field to a new value. +#define BW_CCM_CCGR4_CG9(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG9) | BF_CCM_CCGR4_CG9(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG10[21:20] (RW) + * + * pwm3 clocks (pwm3_clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG10 (20) //!< Bit position for CCM_CCGR4_CG10. +#define BM_CCM_CCGR4_CG10 (0x00300000) //!< Bit mask for CCM_CCGR4_CG10. + +//! @brief Get value of CCM_CCGR4_CG10 from a register value. +#define BG_CCM_CCGR4_CG10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG10) >> BP_CCM_CCGR4_CG10) + +//! @brief Format value for bitfield CCM_CCGR4_CG10. +#define BF_CCM_CCGR4_CG10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG10) & BM_CCM_CCGR4_CG10) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG10 field to a new value. +#define BW_CCM_CCGR4_CG10(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG10) | BF_CCM_CCGR4_CG10(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG11[23:22] (RW) + * + * pwm4 clocks (pwm4_clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG11 (22) //!< Bit position for CCM_CCGR4_CG11. +#define BM_CCM_CCGR4_CG11 (0x00c00000) //!< Bit mask for CCM_CCGR4_CG11. + +//! @brief Get value of CCM_CCGR4_CG11 from a register value. +#define BG_CCM_CCGR4_CG11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG11) >> BP_CCM_CCGR4_CG11) + +//! @brief Format value for bitfield CCM_CCGR4_CG11. +#define BF_CCM_CCGR4_CG11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG11) & BM_CCM_CCGR4_CG11) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG11 field to a new value. +#define BW_CCM_CCGR4_CG11(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG11) | BF_CCM_CCGR4_CG11(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG12[25:24] (RW) + * + * rawnand_u_bch_input_apb clock (rawnand_u_bch_input_apb_clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG12 (24) //!< Bit position for CCM_CCGR4_CG12. +#define BM_CCM_CCGR4_CG12 (0x03000000) //!< Bit mask for CCM_CCGR4_CG12. + +//! @brief Get value of CCM_CCGR4_CG12 from a register value. +#define BG_CCM_CCGR4_CG12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG12) >> BP_CCM_CCGR4_CG12) + +//! @brief Format value for bitfield CCM_CCGR4_CG12. +#define BF_CCM_CCGR4_CG12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG12) & BM_CCM_CCGR4_CG12) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG12 field to a new value. +#define BW_CCM_CCGR4_CG12(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG12) | BF_CCM_CCGR4_CG12(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG13[27:26] (RW) + * + * rawnand_u_gpmi_bch_input_bch clock (rawnand_u_gpmi_bch_input_bch_clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG13 (26) //!< Bit position for CCM_CCGR4_CG13. +#define BM_CCM_CCGR4_CG13 (0x0c000000) //!< Bit mask for CCM_CCGR4_CG13. + +//! @brief Get value of CCM_CCGR4_CG13 from a register value. +#define BG_CCM_CCGR4_CG13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG13) >> BP_CCM_CCGR4_CG13) + +//! @brief Format value for bitfield CCM_CCGR4_CG13. +#define BF_CCM_CCGR4_CG13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG13) & BM_CCM_CCGR4_CG13) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG13 field to a new value. +#define BW_CCM_CCGR4_CG13(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG13) | BF_CCM_CCGR4_CG13(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG14[29:28] (RW) + * + * rawnand_u_gpmi_bch_input_gpmi_io clock (rawnand_u_gpmi_bch_input_gpmi_io_clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG14 (28) //!< Bit position for CCM_CCGR4_CG14. +#define BM_CCM_CCGR4_CG14 (0x30000000) //!< Bit mask for CCM_CCGR4_CG14. + +//! @brief Get value of CCM_CCGR4_CG14 from a register value. +#define BG_CCM_CCGR4_CG14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG14) >> BP_CCM_CCGR4_CG14) + +//! @brief Format value for bitfield CCM_CCGR4_CG14. +#define BF_CCM_CCGR4_CG14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG14) & BM_CCM_CCGR4_CG14) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG14 field to a new value. +#define BW_CCM_CCGR4_CG14(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG14) | BF_CCM_CCGR4_CG14(v))) +#endif +//@} + +/*! @name Register CCM_CCGR4, field CG15[31:30] (RW) + * + * rawnand_u_gpmi_input_apb clock rawnand_u_gpmi_input_apb_clk_enable) + */ +//@{ +#define BP_CCM_CCGR4_CG15 (30) //!< Bit position for CCM_CCGR4_CG15. +#define BM_CCM_CCGR4_CG15 (0xc0000000) //!< Bit mask for CCM_CCGR4_CG15. + +//! @brief Get value of CCM_CCGR4_CG15 from a register value. +#define BG_CCM_CCGR4_CG15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR4_CG15) >> BP_CCM_CCGR4_CG15) + +//! @brief Format value for bitfield CCM_CCGR4_CG15. +#define BF_CCM_CCGR4_CG15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR4_CG15) & BM_CCM_CCGR4_CG15) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG15 field to a new value. +#define BW_CCM_CCGR4_CG15(v) (HW_CCM_CCGR4_WR((HW_CCM_CCGR4_RD() & ~BM_CCM_CCGR4_CG15) | BF_CCM_CCGR4_CG15(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCGR5 - CCM Clock Gating Register 5 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCGR5 - CCM Clock Gating Register 5 (RW) + * + * Reset value: 0xffffffff + * + * The figure below represents the CCM Clock Gating Register 5 (CCM_CCGR5). The clock gating + * Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR + * registers. The number of registers required is according to the number of peripherals in the + * system. + */ +typedef union _hw_ccm_ccgr5 +{ + reg32_t U; + struct _hw_ccm_ccgr5_bitfields + { + unsigned CG0 : 2; //!< [1:0] rom clock (rom_clk_enable) + unsigned CG1 : 2; //!< [3:2] Reserved + unsigned CG2 : 2; //!< [5:4] 100M clock (100M_clk_enable) + unsigned CG3 : 2; //!< [7:6] sdma clock (sdma_clk_enable) + unsigned CG4 : 2; //!< [9:8] Reserved + unsigned CG5 : 2; //!< [11:10] Reserved + unsigned CG6 : 2; //!< [13:12] spba clock (spba_clk_enable) + unsigned CG7 : 2; //!< [15:14] spdif clock (spdif_clk_enable) + unsigned CG8 : 2; //!< [17:16] Reserved + unsigned CG9 : 2; //!< [19:18] ssi1 clocks (ssi1_clk_enable) + unsigned CG10 : 2; //!< [21:20] ssi2 clocks (ssi2_clk_enable) + unsigned CG11 : 2; //!< [23:22] ssi3 clocks (ssi3_clk_enable) + unsigned CG12 : 2; //!< [25:24] uart clock (uart_clk_enable) + unsigned CG13 : 2; //!< [27:26] uart_serial clock (uart_serial_clk_enable) + unsigned CG14 : 2; //!< [29:28] Reserved + unsigned CG15 : 2; //!< [31:30] Reserved + } B; +} hw_ccm_ccgr5_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCGR5 register + */ +//@{ +#define HW_CCM_CCGR5_ADDR (REGS_CCM_BASE + 0x7c) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCGR5 (*(volatile hw_ccm_ccgr5_t *) HW_CCM_CCGR5_ADDR) +#define HW_CCM_CCGR5_RD() (HW_CCM_CCGR5.U) +#define HW_CCM_CCGR5_WR(v) (HW_CCM_CCGR5.U = (v)) +#define HW_CCM_CCGR5_SET(v) (HW_CCM_CCGR5_WR(HW_CCM_CCGR5_RD() | (v))) +#define HW_CCM_CCGR5_CLR(v) (HW_CCM_CCGR5_WR(HW_CCM_CCGR5_RD() & ~(v))) +#define HW_CCM_CCGR5_TOG(v) (HW_CCM_CCGR5_WR(HW_CCM_CCGR5_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCGR5 bitfields + */ + +/*! @name Register CCM_CCGR5, field CG0[1:0] (RW) + * + * rom clock (rom_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG0 (0) //!< Bit position for CCM_CCGR5_CG0. +#define BM_CCM_CCGR5_CG0 (0x00000003) //!< Bit mask for CCM_CCGR5_CG0. + +//! @brief Get value of CCM_CCGR5_CG0 from a register value. +#define BG_CCM_CCGR5_CG0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG0) >> BP_CCM_CCGR5_CG0) + +//! @brief Format value for bitfield CCM_CCGR5_CG0. +#define BF_CCM_CCGR5_CG0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG0) & BM_CCM_CCGR5_CG0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG0 field to a new value. +#define BW_CCM_CCGR5_CG0(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG0) | BF_CCM_CCGR5_CG0(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG1[3:2] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR5_CG1 (2) //!< Bit position for CCM_CCGR5_CG1. +#define BM_CCM_CCGR5_CG1 (0x0000000c) //!< Bit mask for CCM_CCGR5_CG1. + +//! @brief Get value of CCM_CCGR5_CG1 from a register value. +#define BG_CCM_CCGR5_CG1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG1) >> BP_CCM_CCGR5_CG1) + +//! @brief Format value for bitfield CCM_CCGR5_CG1. +#define BF_CCM_CCGR5_CG1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG1) & BM_CCM_CCGR5_CG1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG1 field to a new value. +#define BW_CCM_CCGR5_CG1(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG1) | BF_CCM_CCGR5_CG1(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG2[5:4] (RW) + * + * 100M clock (100M_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG2 (4) //!< Bit position for CCM_CCGR5_CG2. +#define BM_CCM_CCGR5_CG2 (0x00000030) //!< Bit mask for CCM_CCGR5_CG2. + +//! @brief Get value of CCM_CCGR5_CG2 from a register value. +#define BG_CCM_CCGR5_CG2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG2) >> BP_CCM_CCGR5_CG2) + +//! @brief Format value for bitfield CCM_CCGR5_CG2. +#define BF_CCM_CCGR5_CG2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG2) & BM_CCM_CCGR5_CG2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG2 field to a new value. +#define BW_CCM_CCGR5_CG2(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG2) | BF_CCM_CCGR5_CG2(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG3[7:6] (RW) + * + * sdma clock (sdma_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG3 (6) //!< Bit position for CCM_CCGR5_CG3. +#define BM_CCM_CCGR5_CG3 (0x000000c0) //!< Bit mask for CCM_CCGR5_CG3. + +//! @brief Get value of CCM_CCGR5_CG3 from a register value. +#define BG_CCM_CCGR5_CG3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG3) >> BP_CCM_CCGR5_CG3) + +//! @brief Format value for bitfield CCM_CCGR5_CG3. +#define BF_CCM_CCGR5_CG3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG3) & BM_CCM_CCGR5_CG3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG3 field to a new value. +#define BW_CCM_CCGR5_CG3(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG3) | BF_CCM_CCGR5_CG3(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG4[9:8] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR5_CG4 (8) //!< Bit position for CCM_CCGR5_CG4. +#define BM_CCM_CCGR5_CG4 (0x00000300) //!< Bit mask for CCM_CCGR5_CG4. + +//! @brief Get value of CCM_CCGR5_CG4 from a register value. +#define BG_CCM_CCGR5_CG4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG4) >> BP_CCM_CCGR5_CG4) + +//! @brief Format value for bitfield CCM_CCGR5_CG4. +#define BF_CCM_CCGR5_CG4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG4) & BM_CCM_CCGR5_CG4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG4 field to a new value. +#define BW_CCM_CCGR5_CG4(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG4) | BF_CCM_CCGR5_CG4(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG5[11:10] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR5_CG5 (10) //!< Bit position for CCM_CCGR5_CG5. +#define BM_CCM_CCGR5_CG5 (0x00000c00) //!< Bit mask for CCM_CCGR5_CG5. + +//! @brief Get value of CCM_CCGR5_CG5 from a register value. +#define BG_CCM_CCGR5_CG5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG5) >> BP_CCM_CCGR5_CG5) + +//! @brief Format value for bitfield CCM_CCGR5_CG5. +#define BF_CCM_CCGR5_CG5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG5) & BM_CCM_CCGR5_CG5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG5 field to a new value. +#define BW_CCM_CCGR5_CG5(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG5) | BF_CCM_CCGR5_CG5(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG6[13:12] (RW) + * + * spba clock (spba_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG6 (12) //!< Bit position for CCM_CCGR5_CG6. +#define BM_CCM_CCGR5_CG6 (0x00003000) //!< Bit mask for CCM_CCGR5_CG6. + +//! @brief Get value of CCM_CCGR5_CG6 from a register value. +#define BG_CCM_CCGR5_CG6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG6) >> BP_CCM_CCGR5_CG6) + +//! @brief Format value for bitfield CCM_CCGR5_CG6. +#define BF_CCM_CCGR5_CG6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG6) & BM_CCM_CCGR5_CG6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG6 field to a new value. +#define BW_CCM_CCGR5_CG6(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG6) | BF_CCM_CCGR5_CG6(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG7[15:14] (RW) + * + * spdif clock (spdif_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG7 (14) //!< Bit position for CCM_CCGR5_CG7. +#define BM_CCM_CCGR5_CG7 (0x0000c000) //!< Bit mask for CCM_CCGR5_CG7. + +//! @brief Get value of CCM_CCGR5_CG7 from a register value. +#define BG_CCM_CCGR5_CG7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG7) >> BP_CCM_CCGR5_CG7) + +//! @brief Format value for bitfield CCM_CCGR5_CG7. +#define BF_CCM_CCGR5_CG7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG7) & BM_CCM_CCGR5_CG7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG7 field to a new value. +#define BW_CCM_CCGR5_CG7(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG7) | BF_CCM_CCGR5_CG7(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG8[17:16] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR5_CG8 (16) //!< Bit position for CCM_CCGR5_CG8. +#define BM_CCM_CCGR5_CG8 (0x00030000) //!< Bit mask for CCM_CCGR5_CG8. + +//! @brief Get value of CCM_CCGR5_CG8 from a register value. +#define BG_CCM_CCGR5_CG8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG8) >> BP_CCM_CCGR5_CG8) + +//! @brief Format value for bitfield CCM_CCGR5_CG8. +#define BF_CCM_CCGR5_CG8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG8) & BM_CCM_CCGR5_CG8) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG8 field to a new value. +#define BW_CCM_CCGR5_CG8(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG8) | BF_CCM_CCGR5_CG8(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG9[19:18] (RW) + * + * ssi1 clocks (ssi1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG9 (18) //!< Bit position for CCM_CCGR5_CG9. +#define BM_CCM_CCGR5_CG9 (0x000c0000) //!< Bit mask for CCM_CCGR5_CG9. + +//! @brief Get value of CCM_CCGR5_CG9 from a register value. +#define BG_CCM_CCGR5_CG9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG9) >> BP_CCM_CCGR5_CG9) + +//! @brief Format value for bitfield CCM_CCGR5_CG9. +#define BF_CCM_CCGR5_CG9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG9) & BM_CCM_CCGR5_CG9) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG9 field to a new value. +#define BW_CCM_CCGR5_CG9(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG9) | BF_CCM_CCGR5_CG9(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG10[21:20] (RW) + * + * ssi2 clocks (ssi2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG10 (20) //!< Bit position for CCM_CCGR5_CG10. +#define BM_CCM_CCGR5_CG10 (0x00300000) //!< Bit mask for CCM_CCGR5_CG10. + +//! @brief Get value of CCM_CCGR5_CG10 from a register value. +#define BG_CCM_CCGR5_CG10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG10) >> BP_CCM_CCGR5_CG10) + +//! @brief Format value for bitfield CCM_CCGR5_CG10. +#define BF_CCM_CCGR5_CG10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG10) & BM_CCM_CCGR5_CG10) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG10 field to a new value. +#define BW_CCM_CCGR5_CG10(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG10) | BF_CCM_CCGR5_CG10(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG11[23:22] (RW) + * + * ssi3 clocks (ssi3_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG11 (22) //!< Bit position for CCM_CCGR5_CG11. +#define BM_CCM_CCGR5_CG11 (0x00c00000) //!< Bit mask for CCM_CCGR5_CG11. + +//! @brief Get value of CCM_CCGR5_CG11 from a register value. +#define BG_CCM_CCGR5_CG11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG11) >> BP_CCM_CCGR5_CG11) + +//! @brief Format value for bitfield CCM_CCGR5_CG11. +#define BF_CCM_CCGR5_CG11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG11) & BM_CCM_CCGR5_CG11) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG11 field to a new value. +#define BW_CCM_CCGR5_CG11(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG11) | BF_CCM_CCGR5_CG11(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG12[25:24] (RW) + * + * uart clock (uart_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG12 (24) //!< Bit position for CCM_CCGR5_CG12. +#define BM_CCM_CCGR5_CG12 (0x03000000) //!< Bit mask for CCM_CCGR5_CG12. + +//! @brief Get value of CCM_CCGR5_CG12 from a register value. +#define BG_CCM_CCGR5_CG12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG12) >> BP_CCM_CCGR5_CG12) + +//! @brief Format value for bitfield CCM_CCGR5_CG12. +#define BF_CCM_CCGR5_CG12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG12) & BM_CCM_CCGR5_CG12) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG12 field to a new value. +#define BW_CCM_CCGR5_CG12(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG12) | BF_CCM_CCGR5_CG12(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG13[27:26] (RW) + * + * uart_serial clock (uart_serial_clk_enable) + */ +//@{ +#define BP_CCM_CCGR5_CG13 (26) //!< Bit position for CCM_CCGR5_CG13. +#define BM_CCM_CCGR5_CG13 (0x0c000000) //!< Bit mask for CCM_CCGR5_CG13. + +//! @brief Get value of CCM_CCGR5_CG13 from a register value. +#define BG_CCM_CCGR5_CG13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG13) >> BP_CCM_CCGR5_CG13) + +//! @brief Format value for bitfield CCM_CCGR5_CG13. +#define BF_CCM_CCGR5_CG13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG13) & BM_CCM_CCGR5_CG13) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG13 field to a new value. +#define BW_CCM_CCGR5_CG13(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG13) | BF_CCM_CCGR5_CG13(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG14[29:28] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR5_CG14 (28) //!< Bit position for CCM_CCGR5_CG14. +#define BM_CCM_CCGR5_CG14 (0x30000000) //!< Bit mask for CCM_CCGR5_CG14. + +//! @brief Get value of CCM_CCGR5_CG14 from a register value. +#define BG_CCM_CCGR5_CG14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG14) >> BP_CCM_CCGR5_CG14) + +//! @brief Format value for bitfield CCM_CCGR5_CG14. +#define BF_CCM_CCGR5_CG14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG14) & BM_CCM_CCGR5_CG14) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG14 field to a new value. +#define BW_CCM_CCGR5_CG14(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG14) | BF_CCM_CCGR5_CG14(v))) +#endif +//@} + +/*! @name Register CCM_CCGR5, field CG15[31:30] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR5_CG15 (30) //!< Bit position for CCM_CCGR5_CG15. +#define BM_CCM_CCGR5_CG15 (0xc0000000) //!< Bit mask for CCM_CCGR5_CG15. + +//! @brief Get value of CCM_CCGR5_CG15 from a register value. +#define BG_CCM_CCGR5_CG15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR5_CG15) >> BP_CCM_CCGR5_CG15) + +//! @brief Format value for bitfield CCM_CCGR5_CG15. +#define BF_CCM_CCGR5_CG15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR5_CG15) & BM_CCM_CCGR5_CG15) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG15 field to a new value. +#define BW_CCM_CCGR5_CG15(v) (HW_CCM_CCGR5_WR((HW_CCM_CCGR5_RD() & ~BM_CCM_CCGR5_CG15) | BF_CCM_CCGR5_CG15(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CCGR6 - CCM Clock Gating Register 6 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CCGR6 - CCM Clock Gating Register 6 (RW) + * + * Reset value: 0xffffffff + * + * The figure below represents the CCM Clock Gating Register 6 (CCM_CCGR6). The clock gating + * Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR + * registers. The number of registers required is according to the number of peripherals in the + * system. + */ +typedef union _hw_ccm_ccgr6 +{ + reg32_t U; + struct _hw_ccm_ccgr6_bitfields + { + unsigned CG0 : 2; //!< [1:0] usboh3 clock (usboh3_clk_enable) + unsigned CG1 : 2; //!< [3:2] usdhc1 clocks (usdhc1_clk_enable) + unsigned CG2 : 2; //!< [5:4] usdhc2 clocks (usdhc2_clk_enable) + unsigned CG3 : 2; //!< [7:6] usdhc3 clocks (usdhc3_clk_enable) + unsigned CG4 : 2; //!< [9:8] usdhc4 clocks (usdhc4_clk_enable) + unsigned CG5 : 2; //!< [11:10] eim_slow clocks (eim_slow_clk_enable) + unsigned CG6 : 2; //!< [13:12] vdoaxiclk root clock (vdoaxiclk_clk_enable) + unsigned CG7 : 2; //!< [15:14] vpu clocks (vpu_clk_enable) + unsigned CG8 : 2; //!< [17:16] Reserved + unsigned CG9 : 2; //!< [19:18] Reserved + unsigned CG10 : 2; //!< [21:20] Reserved + unsigned CG11 : 2; //!< [23:22] Reserved + unsigned CG12 : 2; //!< [25:24] Reserved + unsigned CG13 : 2; //!< [27:26] Reserved + unsigned CG14 : 2; //!< [29:28] Reserved + unsigned CG15 : 2; //!< [31:30] Reserved + } B; +} hw_ccm_ccgr6_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CCGR6 register + */ +//@{ +#define HW_CCM_CCGR6_ADDR (REGS_CCM_BASE + 0x80) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CCGR6 (*(volatile hw_ccm_ccgr6_t *) HW_CCM_CCGR6_ADDR) +#define HW_CCM_CCGR6_RD() (HW_CCM_CCGR6.U) +#define HW_CCM_CCGR6_WR(v) (HW_CCM_CCGR6.U = (v)) +#define HW_CCM_CCGR6_SET(v) (HW_CCM_CCGR6_WR(HW_CCM_CCGR6_RD() | (v))) +#define HW_CCM_CCGR6_CLR(v) (HW_CCM_CCGR6_WR(HW_CCM_CCGR6_RD() & ~(v))) +#define HW_CCM_CCGR6_TOG(v) (HW_CCM_CCGR6_WR(HW_CCM_CCGR6_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CCGR6 bitfields + */ + +/*! @name Register CCM_CCGR6, field CG0[1:0] (RW) + * + * usboh3 clock (usboh3_clk_enable) + */ +//@{ +#define BP_CCM_CCGR6_CG0 (0) //!< Bit position for CCM_CCGR6_CG0. +#define BM_CCM_CCGR6_CG0 (0x00000003) //!< Bit mask for CCM_CCGR6_CG0. + +//! @brief Get value of CCM_CCGR6_CG0 from a register value. +#define BG_CCM_CCGR6_CG0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG0) >> BP_CCM_CCGR6_CG0) + +//! @brief Format value for bitfield CCM_CCGR6_CG0. +#define BF_CCM_CCGR6_CG0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG0) & BM_CCM_CCGR6_CG0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG0 field to a new value. +#define BW_CCM_CCGR6_CG0(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG0) | BF_CCM_CCGR6_CG0(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG1[3:2] (RW) + * + * usdhc1 clocks (usdhc1_clk_enable) + */ +//@{ +#define BP_CCM_CCGR6_CG1 (2) //!< Bit position for CCM_CCGR6_CG1. +#define BM_CCM_CCGR6_CG1 (0x0000000c) //!< Bit mask for CCM_CCGR6_CG1. + +//! @brief Get value of CCM_CCGR6_CG1 from a register value. +#define BG_CCM_CCGR6_CG1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG1) >> BP_CCM_CCGR6_CG1) + +//! @brief Format value for bitfield CCM_CCGR6_CG1. +#define BF_CCM_CCGR6_CG1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG1) & BM_CCM_CCGR6_CG1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG1 field to a new value. +#define BW_CCM_CCGR6_CG1(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG1) | BF_CCM_CCGR6_CG1(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG2[5:4] (RW) + * + * usdhc2 clocks (usdhc2_clk_enable) + */ +//@{ +#define BP_CCM_CCGR6_CG2 (4) //!< Bit position for CCM_CCGR6_CG2. +#define BM_CCM_CCGR6_CG2 (0x00000030) //!< Bit mask for CCM_CCGR6_CG2. + +//! @brief Get value of CCM_CCGR6_CG2 from a register value. +#define BG_CCM_CCGR6_CG2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG2) >> BP_CCM_CCGR6_CG2) + +//! @brief Format value for bitfield CCM_CCGR6_CG2. +#define BF_CCM_CCGR6_CG2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG2) & BM_CCM_CCGR6_CG2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG2 field to a new value. +#define BW_CCM_CCGR6_CG2(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG2) | BF_CCM_CCGR6_CG2(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG3[7:6] (RW) + * + * usdhc3 clocks (usdhc3_clk_enable) + */ +//@{ +#define BP_CCM_CCGR6_CG3 (6) //!< Bit position for CCM_CCGR6_CG3. +#define BM_CCM_CCGR6_CG3 (0x000000c0) //!< Bit mask for CCM_CCGR6_CG3. + +//! @brief Get value of CCM_CCGR6_CG3 from a register value. +#define BG_CCM_CCGR6_CG3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG3) >> BP_CCM_CCGR6_CG3) + +//! @brief Format value for bitfield CCM_CCGR6_CG3. +#define BF_CCM_CCGR6_CG3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG3) & BM_CCM_CCGR6_CG3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG3 field to a new value. +#define BW_CCM_CCGR6_CG3(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG3) | BF_CCM_CCGR6_CG3(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG4[9:8] (RW) + * + * usdhc4 clocks (usdhc4_clk_enable) + */ +//@{ +#define BP_CCM_CCGR6_CG4 (8) //!< Bit position for CCM_CCGR6_CG4. +#define BM_CCM_CCGR6_CG4 (0x00000300) //!< Bit mask for CCM_CCGR6_CG4. + +//! @brief Get value of CCM_CCGR6_CG4 from a register value. +#define BG_CCM_CCGR6_CG4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG4) >> BP_CCM_CCGR6_CG4) + +//! @brief Format value for bitfield CCM_CCGR6_CG4. +#define BF_CCM_CCGR6_CG4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG4) & BM_CCM_CCGR6_CG4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG4 field to a new value. +#define BW_CCM_CCGR6_CG4(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG4) | BF_CCM_CCGR6_CG4(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG5[11:10] (RW) + * + * eim_slow clocks (eim_slow_clk_enable) + */ +//@{ +#define BP_CCM_CCGR6_CG5 (10) //!< Bit position for CCM_CCGR6_CG5. +#define BM_CCM_CCGR6_CG5 (0x00000c00) //!< Bit mask for CCM_CCGR6_CG5. + +//! @brief Get value of CCM_CCGR6_CG5 from a register value. +#define BG_CCM_CCGR6_CG5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG5) >> BP_CCM_CCGR6_CG5) + +//! @brief Format value for bitfield CCM_CCGR6_CG5. +#define BF_CCM_CCGR6_CG5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG5) & BM_CCM_CCGR6_CG5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG5 field to a new value. +#define BW_CCM_CCGR6_CG5(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG5) | BF_CCM_CCGR6_CG5(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG6[13:12] (RW) + * + * vdoaxiclk root clock (vdoaxiclk_clk_enable) + */ +//@{ +#define BP_CCM_CCGR6_CG6 (12) //!< Bit position for CCM_CCGR6_CG6. +#define BM_CCM_CCGR6_CG6 (0x00003000) //!< Bit mask for CCM_CCGR6_CG6. + +//! @brief Get value of CCM_CCGR6_CG6 from a register value. +#define BG_CCM_CCGR6_CG6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG6) >> BP_CCM_CCGR6_CG6) + +//! @brief Format value for bitfield CCM_CCGR6_CG6. +#define BF_CCM_CCGR6_CG6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG6) & BM_CCM_CCGR6_CG6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG6 field to a new value. +#define BW_CCM_CCGR6_CG6(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG6) | BF_CCM_CCGR6_CG6(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG7[15:14] (RW) + * + * vpu clocks (vpu_clk_enable) + */ +//@{ +#define BP_CCM_CCGR6_CG7 (14) //!< Bit position for CCM_CCGR6_CG7. +#define BM_CCM_CCGR6_CG7 (0x0000c000) //!< Bit mask for CCM_CCGR6_CG7. + +//! @brief Get value of CCM_CCGR6_CG7 from a register value. +#define BG_CCM_CCGR6_CG7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG7) >> BP_CCM_CCGR6_CG7) + +//! @brief Format value for bitfield CCM_CCGR6_CG7. +#define BF_CCM_CCGR6_CG7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG7) & BM_CCM_CCGR6_CG7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG7 field to a new value. +#define BW_CCM_CCGR6_CG7(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG7) | BF_CCM_CCGR6_CG7(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG8[17:16] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR6_CG8 (16) //!< Bit position for CCM_CCGR6_CG8. +#define BM_CCM_CCGR6_CG8 (0x00030000) //!< Bit mask for CCM_CCGR6_CG8. + +//! @brief Get value of CCM_CCGR6_CG8 from a register value. +#define BG_CCM_CCGR6_CG8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG8) >> BP_CCM_CCGR6_CG8) + +//! @brief Format value for bitfield CCM_CCGR6_CG8. +#define BF_CCM_CCGR6_CG8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG8) & BM_CCM_CCGR6_CG8) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG8 field to a new value. +#define BW_CCM_CCGR6_CG8(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG8) | BF_CCM_CCGR6_CG8(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG9[19:18] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR6_CG9 (18) //!< Bit position for CCM_CCGR6_CG9. +#define BM_CCM_CCGR6_CG9 (0x000c0000) //!< Bit mask for CCM_CCGR6_CG9. + +//! @brief Get value of CCM_CCGR6_CG9 from a register value. +#define BG_CCM_CCGR6_CG9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG9) >> BP_CCM_CCGR6_CG9) + +//! @brief Format value for bitfield CCM_CCGR6_CG9. +#define BF_CCM_CCGR6_CG9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG9) & BM_CCM_CCGR6_CG9) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG9 field to a new value. +#define BW_CCM_CCGR6_CG9(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG9) | BF_CCM_CCGR6_CG9(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG10[21:20] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR6_CG10 (20) //!< Bit position for CCM_CCGR6_CG10. +#define BM_CCM_CCGR6_CG10 (0x00300000) //!< Bit mask for CCM_CCGR6_CG10. + +//! @brief Get value of CCM_CCGR6_CG10 from a register value. +#define BG_CCM_CCGR6_CG10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG10) >> BP_CCM_CCGR6_CG10) + +//! @brief Format value for bitfield CCM_CCGR6_CG10. +#define BF_CCM_CCGR6_CG10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG10) & BM_CCM_CCGR6_CG10) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG10 field to a new value. +#define BW_CCM_CCGR6_CG10(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG10) | BF_CCM_CCGR6_CG10(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG11[23:22] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR6_CG11 (22) //!< Bit position for CCM_CCGR6_CG11. +#define BM_CCM_CCGR6_CG11 (0x00c00000) //!< Bit mask for CCM_CCGR6_CG11. + +//! @brief Get value of CCM_CCGR6_CG11 from a register value. +#define BG_CCM_CCGR6_CG11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG11) >> BP_CCM_CCGR6_CG11) + +//! @brief Format value for bitfield CCM_CCGR6_CG11. +#define BF_CCM_CCGR6_CG11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG11) & BM_CCM_CCGR6_CG11) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG11 field to a new value. +#define BW_CCM_CCGR6_CG11(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG11) | BF_CCM_CCGR6_CG11(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG12[25:24] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR6_CG12 (24) //!< Bit position for CCM_CCGR6_CG12. +#define BM_CCM_CCGR6_CG12 (0x03000000) //!< Bit mask for CCM_CCGR6_CG12. + +//! @brief Get value of CCM_CCGR6_CG12 from a register value. +#define BG_CCM_CCGR6_CG12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG12) >> BP_CCM_CCGR6_CG12) + +//! @brief Format value for bitfield CCM_CCGR6_CG12. +#define BF_CCM_CCGR6_CG12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG12) & BM_CCM_CCGR6_CG12) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG12 field to a new value. +#define BW_CCM_CCGR6_CG12(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG12) | BF_CCM_CCGR6_CG12(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG13[27:26] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR6_CG13 (26) //!< Bit position for CCM_CCGR6_CG13. +#define BM_CCM_CCGR6_CG13 (0x0c000000) //!< Bit mask for CCM_CCGR6_CG13. + +//! @brief Get value of CCM_CCGR6_CG13 from a register value. +#define BG_CCM_CCGR6_CG13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG13) >> BP_CCM_CCGR6_CG13) + +//! @brief Format value for bitfield CCM_CCGR6_CG13. +#define BF_CCM_CCGR6_CG13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG13) & BM_CCM_CCGR6_CG13) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG13 field to a new value. +#define BW_CCM_CCGR6_CG13(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG13) | BF_CCM_CCGR6_CG13(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG14[29:28] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR6_CG14 (28) //!< Bit position for CCM_CCGR6_CG14. +#define BM_CCM_CCGR6_CG14 (0x30000000) //!< Bit mask for CCM_CCGR6_CG14. + +//! @brief Get value of CCM_CCGR6_CG14 from a register value. +#define BG_CCM_CCGR6_CG14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG14) >> BP_CCM_CCGR6_CG14) + +//! @brief Format value for bitfield CCM_CCGR6_CG14. +#define BF_CCM_CCGR6_CG14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG14) & BM_CCM_CCGR6_CG14) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG14 field to a new value. +#define BW_CCM_CCGR6_CG14(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG14) | BF_CCM_CCGR6_CG14(v))) +#endif +//@} + +/*! @name Register CCM_CCGR6, field CG15[31:30] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_CCGR6_CG15 (30) //!< Bit position for CCM_CCGR6_CG15. +#define BM_CCM_CCGR6_CG15 (0xc0000000) //!< Bit mask for CCM_CCGR6_CG15. + +//! @brief Get value of CCM_CCGR6_CG15 from a register value. +#define BG_CCM_CCGR6_CG15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CCGR6_CG15) >> BP_CCM_CCGR6_CG15) + +//! @brief Format value for bitfield CCM_CCGR6_CG15. +#define BF_CCM_CCGR6_CG15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CCGR6_CG15) & BM_CCM_CCGR6_CG15) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CG15 field to a new value. +#define BW_CCM_CCGR6_CG15(v) (HW_CCM_CCGR6_WR((HW_CCM_CCGR6_RD() & ~BM_CCM_CCGR6_CG15) | BF_CCM_CCGR6_CG15(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_CMEOR - CCM Module Enable Overide Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_CMEOR - CCM Module Enable Overide Register (RW) + * + * Reset value: 0xffffffff + * + * The follow figure represents the CCM Module Enable Override Register (CMEOR). The CMEOR register + * contains bits to override the clock enable signal from the module. This should be used in case + * that it is decided to bypass the clock enable signals from the modules. This bit will be + * applicable only for module that their clock enable signal is used. The following table provides + * its field descriptions. + */ +typedef union _hw_ccm_cmeor +{ + reg32_t U; + struct _hw_ccm_cmeor_bitfields + { + unsigned RESERVED0 : 4; //!< [3:0] Reserved + unsigned MOD_EN_OV_VDOA : 1; //!< [4] overide clock enable signal from vdoa - clock will not be gated based on vdoa signal. + unsigned MOD_EN_OV_GPT : 1; //!< [5] overide clock enable signal from gpt - clock will not be gated based on gpt's signal 'ipg_enable_clk' . + unsigned MOD_EN_OV_EPIT : 1; //!< [6] overide clock enable signal from epit - clock will not be gated based on epit's signal 'ipg_enable_clk' . + unsigned MOD_EN_USDHC : 1; //!< [7] overide clock enable signal from usdhc. + unsigned MOD_EN_OV_DAP : 1; //!< [8] overide clock enable signal from dap- clock will not be gated based on dap's signal 'dap_dbgen' . + unsigned MOD_EN_OV_VPU : 1; //!< [9] overide clock enable signal from vpu- clock will not be gated based on vpu's signal 'vpu_idle' . + unsigned MOD_EN_OV_GPU2D : 1; //!< [10] overide clock enable signal from gpu2d - clock will not be gated based on gpu2d's signal 'gpu2d_busy' . + unsigned MOD_EN_OV_GPU3D : 1; //!< [11] overide clock enable signal from gpu3d - clock will not be gated based on gpu3d's signal. + unsigned RESERVED1 : 16; //!< [27:12] Reserved + unsigned MOD_EN_OV_CAN2_CPI : 1; //!< [28] overide clock enable signal from can2 - clock will not be gated based on can's signal 'enable_clk_cpi'. + unsigned RESERVED2 : 1; //!< [29] Reserved + unsigned MOD_EN_OV_CAN1_CPI : 1; //!< [30] overide clock enable signal from can1 - clock will not be gated based on can's signal 'enable_clk_cpi'. + unsigned RESERVED3 : 1; //!< [31] Reserved + } B; +} hw_ccm_cmeor_t; +#endif + +/*! + * @name Constants and macros for entire CCM_CMEOR register + */ +//@{ +#define HW_CCM_CMEOR_ADDR (REGS_CCM_BASE + 0x88) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_CMEOR (*(volatile hw_ccm_cmeor_t *) HW_CCM_CMEOR_ADDR) +#define HW_CCM_CMEOR_RD() (HW_CCM_CMEOR.U) +#define HW_CCM_CMEOR_WR(v) (HW_CCM_CMEOR.U = (v)) +#define HW_CCM_CMEOR_SET(v) (HW_CCM_CMEOR_WR(HW_CCM_CMEOR_RD() | (v))) +#define HW_CCM_CMEOR_CLR(v) (HW_CCM_CMEOR_WR(HW_CCM_CMEOR_RD() & ~(v))) +#define HW_CCM_CMEOR_TOG(v) (HW_CCM_CMEOR_WR(HW_CCM_CMEOR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_CMEOR bitfields + */ + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_VDOA[4] (RW) + * + * overide clock enable signal from vdoa - clock will not be gated based on vdoa signal. + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_VDOA (4) //!< Bit position for CCM_CMEOR_MOD_EN_OV_VDOA. +#define BM_CCM_CMEOR_MOD_EN_OV_VDOA (0x00000010) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_VDOA. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_VDOA from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_VDOA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_VDOA) >> BP_CCM_CMEOR_MOD_EN_OV_VDOA) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_VDOA. +#define BF_CCM_CMEOR_MOD_EN_OV_VDOA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_VDOA) & BM_CCM_CMEOR_MOD_EN_OV_VDOA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_VDOA field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_VDOA(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_VDOA) | BF_CCM_CMEOR_MOD_EN_OV_VDOA(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_GPT[5] (RW) + * + * overide clock enable signal from gpt - clock will not be gated based on gpt's signal + * 'ipg_enable_clk' . + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_GPT (5) //!< Bit position for CCM_CMEOR_MOD_EN_OV_GPT. +#define BM_CCM_CMEOR_MOD_EN_OV_GPT (0x00000020) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_GPT. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_GPT from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_GPT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_GPT) >> BP_CCM_CMEOR_MOD_EN_OV_GPT) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_GPT. +#define BF_CCM_CMEOR_MOD_EN_OV_GPT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_GPT) & BM_CCM_CMEOR_MOD_EN_OV_GPT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_GPT field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_GPT(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_GPT) | BF_CCM_CMEOR_MOD_EN_OV_GPT(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_EPIT[6] (RW) + * + * overide clock enable signal from epit - clock will not be gated based on epit's signal + * 'ipg_enable_clk' . + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_EPIT (6) //!< Bit position for CCM_CMEOR_MOD_EN_OV_EPIT. +#define BM_CCM_CMEOR_MOD_EN_OV_EPIT (0x00000040) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_EPIT. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_EPIT from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_EPIT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_EPIT) >> BP_CCM_CMEOR_MOD_EN_OV_EPIT) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_EPIT. +#define BF_CCM_CMEOR_MOD_EN_OV_EPIT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_EPIT) & BM_CCM_CMEOR_MOD_EN_OV_EPIT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_EPIT field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_EPIT(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_EPIT) | BF_CCM_CMEOR_MOD_EN_OV_EPIT(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_USDHC[7] (RW) + * + * overide clock enable signal from usdhc. + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_USDHC (7) //!< Bit position for CCM_CMEOR_MOD_EN_USDHC. +#define BM_CCM_CMEOR_MOD_EN_USDHC (0x00000080) //!< Bit mask for CCM_CMEOR_MOD_EN_USDHC. + +//! @brief Get value of CCM_CMEOR_MOD_EN_USDHC from a register value. +#define BG_CCM_CMEOR_MOD_EN_USDHC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_USDHC) >> BP_CCM_CMEOR_MOD_EN_USDHC) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_USDHC. +#define BF_CCM_CMEOR_MOD_EN_USDHC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_USDHC) & BM_CCM_CMEOR_MOD_EN_USDHC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_USDHC field to a new value. +#define BW_CCM_CMEOR_MOD_EN_USDHC(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_USDHC) | BF_CCM_CMEOR_MOD_EN_USDHC(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_DAP[8] (RW) + * + * overide clock enable signal from dap- clock will not be gated based on dap's signal 'dap_dbgen' . + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_DAP (8) //!< Bit position for CCM_CMEOR_MOD_EN_OV_DAP. +#define BM_CCM_CMEOR_MOD_EN_OV_DAP (0x00000100) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_DAP. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_DAP from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_DAP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_DAP) >> BP_CCM_CMEOR_MOD_EN_OV_DAP) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_DAP. +#define BF_CCM_CMEOR_MOD_EN_OV_DAP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_DAP) & BM_CCM_CMEOR_MOD_EN_OV_DAP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_DAP field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_DAP(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_DAP) | BF_CCM_CMEOR_MOD_EN_OV_DAP(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_VPU[9] (RW) + * + * overide clock enable signal from vpu- clock will not be gated based on vpu's signal 'vpu_idle' . + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_VPU (9) //!< Bit position for CCM_CMEOR_MOD_EN_OV_VPU. +#define BM_CCM_CMEOR_MOD_EN_OV_VPU (0x00000200) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_VPU. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_VPU from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_VPU(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_VPU) >> BP_CCM_CMEOR_MOD_EN_OV_VPU) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_VPU. +#define BF_CCM_CMEOR_MOD_EN_OV_VPU(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_VPU) & BM_CCM_CMEOR_MOD_EN_OV_VPU) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_VPU field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_VPU(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_VPU) | BF_CCM_CMEOR_MOD_EN_OV_VPU(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_GPU2D[10] (RW) + * + * overide clock enable signal from gpu2d - clock will not be gated based on gpu2d's signal + * 'gpu2d_busy' . + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_GPU2D (10) //!< Bit position for CCM_CMEOR_MOD_EN_OV_GPU2D. +#define BM_CCM_CMEOR_MOD_EN_OV_GPU2D (0x00000400) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_GPU2D. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_GPU2D from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_GPU2D(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_GPU2D) >> BP_CCM_CMEOR_MOD_EN_OV_GPU2D) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_GPU2D. +#define BF_CCM_CMEOR_MOD_EN_OV_GPU2D(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_GPU2D) & BM_CCM_CMEOR_MOD_EN_OV_GPU2D) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_GPU2D field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_GPU2D(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_GPU2D) | BF_CCM_CMEOR_MOD_EN_OV_GPU2D(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_GPU3D[11] (RW) + * + * overide clock enable signal from gpu3d - clock will not be gated based on gpu3d's signal. + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_GPU3D (11) //!< Bit position for CCM_CMEOR_MOD_EN_OV_GPU3D. +#define BM_CCM_CMEOR_MOD_EN_OV_GPU3D (0x00000800) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_GPU3D. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_GPU3D from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_GPU3D(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_GPU3D) >> BP_CCM_CMEOR_MOD_EN_OV_GPU3D) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_GPU3D. +#define BF_CCM_CMEOR_MOD_EN_OV_GPU3D(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_GPU3D) & BM_CCM_CMEOR_MOD_EN_OV_GPU3D) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_GPU3D field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_GPU3D(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_GPU3D) | BF_CCM_CMEOR_MOD_EN_OV_GPU3D(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_CAN2_CPI[28] (RW) + * + * overide clock enable signal from can2 - clock will not be gated based on can's signal + * 'enable_clk_cpi'. + * + * Values: + * - 0 - dont override module enable signal + * - 1 - override module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_CAN2_CPI (28) //!< Bit position for CCM_CMEOR_MOD_EN_OV_CAN2_CPI. +#define BM_CCM_CMEOR_MOD_EN_OV_CAN2_CPI (0x10000000) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_CAN2_CPI. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_CAN2_CPI from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_CAN2_CPI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_CAN2_CPI) >> BP_CCM_CMEOR_MOD_EN_OV_CAN2_CPI) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_CAN2_CPI. +#define BF_CCM_CMEOR_MOD_EN_OV_CAN2_CPI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_CAN2_CPI) & BM_CCM_CMEOR_MOD_EN_OV_CAN2_CPI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_CAN2_CPI field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_CAN2_CPI(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_CAN2_CPI) | BF_CCM_CMEOR_MOD_EN_OV_CAN2_CPI(v))) +#endif +//@} + +/*! @name Register CCM_CMEOR, field MOD_EN_OV_CAN1_CPI[30] (RW) + * + * overide clock enable signal from can1 - clock will not be gated based on can's signal + * 'enable_clk_cpi'. + * + * Values: + * - 0 - dont overide module enable signal + * - 1 - overide module enable signal + */ +//@{ +#define BP_CCM_CMEOR_MOD_EN_OV_CAN1_CPI (30) //!< Bit position for CCM_CMEOR_MOD_EN_OV_CAN1_CPI. +#define BM_CCM_CMEOR_MOD_EN_OV_CAN1_CPI (0x40000000) //!< Bit mask for CCM_CMEOR_MOD_EN_OV_CAN1_CPI. + +//! @brief Get value of CCM_CMEOR_MOD_EN_OV_CAN1_CPI from a register value. +#define BG_CCM_CMEOR_MOD_EN_OV_CAN1_CPI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_CMEOR_MOD_EN_OV_CAN1_CPI) >> BP_CCM_CMEOR_MOD_EN_OV_CAN1_CPI) + +//! @brief Format value for bitfield CCM_CMEOR_MOD_EN_OV_CAN1_CPI. +#define BF_CCM_CMEOR_MOD_EN_OV_CAN1_CPI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_CMEOR_MOD_EN_OV_CAN1_CPI) & BM_CCM_CMEOR_MOD_EN_OV_CAN1_CPI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD_EN_OV_CAN1_CPI field to a new value. +#define BW_CCM_CMEOR_MOD_EN_OV_CAN1_CPI(v) (HW_CCM_CMEOR_WR((HW_CCM_CMEOR_RD() & ~BM_CCM_CMEOR_MOD_EN_OV_CAN1_CPI) | BF_CCM_CMEOR_MOD_EN_OV_CAN1_CPI(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// hw_ccm_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All CCM module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_ccm +{ + volatile hw_ccm_ccr_t CCR; //!< CCM Control Register + volatile hw_ccm_ccdr_t CCDR; //!< CCM Control Divider Register + volatile hw_ccm_csr_t CSR; //!< CCM Status Register + volatile hw_ccm_ccsr_t CCSR; //!< CCM Clock Swither Register + volatile hw_ccm_cacrr_t CACRR; //!< CCM Arm Clock Root Register + volatile hw_ccm_cbcdr_t CBCDR; //!< CCM Bus Clock Divider Register + volatile hw_ccm_cbcmr_t CBCMR; //!< CCM Bus Clock Multiplexer Register + volatile hw_ccm_cscmr1_t CSCMR1; //!< CCM Serial Clock Multiplexer Register 1 + volatile hw_ccm_cscmr2_t CSCMR2; //!< CCM Serial Clock Multiplexer Register 2 + volatile hw_ccm_cscdr1_t CSCDR1; //!< CCM Serial Clock Divider Register 1 + volatile hw_ccm_cs1cdr_t CS1CDR; //!< CCM SSI1 Clock Divider Register + volatile hw_ccm_cs2cdr_t CS2CDR; //!< CCM SSI2 Clock Divider Register + volatile hw_ccm_cdcdr_t CDCDR; //!< CCM D1 Clock Divider Register + volatile hw_ccm_chsccdr_t CHSCCDR; //!< CCM HSC Clock Divider Register + volatile hw_ccm_cscdr2_t CSCDR2; //!< CCM Serial Clock Divider Register 2 + volatile hw_ccm_cscdr3_t CSCDR3; //!< CCM Serial Clock Divider Register 3 + reg32_t _reserved0; + volatile hw_ccm_cwdr_t CWDR; //!< CCM Wakeup Detector Register + volatile hw_ccm_cdhipr_t CDHIPR; //!< CCM Divider Handshake In-Process Register + reg32_t _reserved1; + volatile hw_ccm_ctor_t CTOR; //!< CCM Testing Observability Register + volatile hw_ccm_clpcr_t CLPCR; //!< CCM Low Power Control Register + volatile hw_ccm_cisr_t CISR; //!< CCM Interrupt Status Register + volatile hw_ccm_cimr_t CIMR; //!< CCM Interrupt Mask Register + volatile hw_ccm_ccosr_t CCOSR; //!< CCM Clock Output Source Register + volatile hw_ccm_cgpr_t CGPR; //!< CCM General Purpose Register + volatile hw_ccm_ccgr0_t CCGR0; //!< CCM Clock Gating Register 0 + volatile hw_ccm_ccgr1_t CCGR1; //!< CCM Clock Gating Register 1 + volatile hw_ccm_ccgr2_t CCGR2; //!< CCM Clock Gating Register 2 + volatile hw_ccm_ccgr3_t CCGR3; //!< CCM Clock Gating Register 3 + volatile hw_ccm_ccgr4_t CCGR4; //!< CCM Clock Gating Register 4 + volatile hw_ccm_ccgr5_t CCGR5; //!< CCM Clock Gating Register 5 + volatile hw_ccm_ccgr6_t CCGR6; //!< CCM Clock Gating Register 6 + reg32_t _reserved2; + volatile hw_ccm_cmeor_t CMEOR; //!< CCM Module Enable Overide Register +} hw_ccm_t; +#pragma pack() + +//! @brief Macro to access all CCM registers. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_CCM. +#define HW_CCM (*(hw_ccm_t *) REGS_CCM_BASE) +#endif + +#endif // __HW_CCM_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsccmanalog.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsccmanalog.h new file mode 100644 index 0000000000000000000000000000000000000000..8ae2222a715c210256de3faa76014babe5d3eae8 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsccmanalog.h @@ -0,0 +1,3254 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_CCM_ANALOG_REGISTERS_H__ +#define __HW_CCM_ANALOG_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL CCM_ANALOG + * + * CCM + * + * Registers defined in this header file: + * - HW_CCM_ANALOG_PLL_ARM - Analog ARM PLL control Register + * - HW_CCM_ANALOG_PLL_USB1 - Analog USB1 480MHz PLL Control Register + * - HW_CCM_ANALOG_PLL_USB2 - Analog USB2 480MHz PLL Control Register + * - HW_CCM_ANALOG_PLL_SYS - Analog System PLL Control Register + * - HW_CCM_ANALOG_PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register. + * - HW_CCM_ANALOG_PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register + * - HW_CCM_ANALOG_PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register + * - HW_CCM_ANALOG_PLL_AUDIO - Analog Audio PLL control Register + * - HW_CCM_ANALOG_PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register + * - HW_CCM_ANALOG_PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register + * - HW_CCM_ANALOG_PLL_VIDEO - Analog Video PLL control Register + * - HW_CCM_ANALOG_PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register + * - HW_CCM_ANALOG_PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register + * - HW_CCM_ANALOG_PLL_MLB - MLB PLL Control Register + * - HW_CCM_ANALOG_PLL_ENET - Analog ENET PLL Control Register + * - HW_CCM_ANALOG_PFD_480 - 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register + * - HW_CCM_ANALOG_PFD_528 - 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register + * - HW_CCM_ANALOG_MISC0 - Miscellaneous Control Register + * - HW_CCM_ANALOG_MISC2 - Miscellaneous Control Register + * + * - hw_ccm_analog_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_CCM_ANALOG_BASE +#define HW_CCM_ANALOG_INSTANCE_COUNT (1) //!< Number of instances of the CCM_ANALOG module. +#define REGS_CCM_ANALOG_BASE (0x020c8000) //!< Base address for CCM_ANALOG. +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_ARM - Analog ARM PLL control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_ARM - Analog ARM PLL control Register (RW) + * + * Reset value: 0x00013042 + * + * The control register provides control for the system PLL. + */ +typedef union _hw_ccm_analog_pll_arm +{ + reg32_t U; + struct _hw_ccm_analog_pll_arm_bitfields + { + unsigned DIV_SELECT : 7; //!< [6:0] This field controls the pll loop divider. + unsigned RESERVED0 : 5; //!< [11:7] Reserved. + unsigned POWERDOWN : 1; //!< [12] Powers down the PLL. + unsigned ENABLE : 1; //!< [13] Enable the clock output. + unsigned BYPASS_CLK_SRC : 2; //!< [15:14] Determines the bypass source. + unsigned BYPASS : 1; //!< [16] Bypass the pll. + unsigned LVDS_SEL : 1; //!< [17] Analog Debug Bit + unsigned LVDS_24MHZ_SEL : 1; //!< [18] Analog Debug Bit + unsigned PLL_SEL : 1; //!< [19] Reserved + unsigned RESERVED1 : 11; //!< [30:20] Always set to zero (0). + unsigned LOCK : 1; //!< [31] 1 - PLL is currently locked. + } B; +} hw_ccm_analog_pll_arm_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_ARM register + */ +//@{ +#define HW_CCM_ANALOG_PLL_ARM_ADDR (REGS_CCM_ANALOG_BASE + 0x0) +#define HW_CCM_ANALOG_PLL_ARM_SET_ADDR (HW_CCM_ANALOG_PLL_ARM_ADDR + 0x4) +#define HW_CCM_ANALOG_PLL_ARM_CLR_ADDR (HW_CCM_ANALOG_PLL_ARM_ADDR + 0x8) +#define HW_CCM_ANALOG_PLL_ARM_TOG_ADDR (HW_CCM_ANALOG_PLL_ARM_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_ARM (*(volatile hw_ccm_analog_pll_arm_t *) HW_CCM_ANALOG_PLL_ARM_ADDR) +#define HW_CCM_ANALOG_PLL_ARM_RD() (HW_CCM_ANALOG_PLL_ARM.U) +#define HW_CCM_ANALOG_PLL_ARM_WR(v) (HW_CCM_ANALOG_PLL_ARM.U = (v)) +#define HW_CCM_ANALOG_PLL_ARM_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_ARM_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_ARM_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_ARM_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_ARM_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_ARM_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_ARM bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_ARM, field DIV_SELECT[6:0] (RW) + * + * This field controls the pll loop divider. Valid range for divider value: 54-108. Fout = Fin * + * div_select/2.0. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_DIV_SELECT (0) //!< Bit position for CCM_ANALOG_PLL_ARM_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_ARM_DIV_SELECT (0x0000007f) //!< Bit mask for CCM_ANALOG_PLL_ARM_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_ARM_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_DIV_SELECT) >> BP_CCM_ANALOG_PLL_ARM_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ARM_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_ARM_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ARM_DIV_SELECT) & BM_CCM_ANALOG_PLL_ARM_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_ARM_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_ARM, DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ARM, field POWERDOWN[12] (RW) + * + * Powers down the PLL. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_POWERDOWN (12) //!< Bit position for CCM_ANALOG_PLL_ARM_POWERDOWN. +#define BM_CCM_ANALOG_PLL_ARM_POWERDOWN (0x00001000) //!< Bit mask for CCM_ANALOG_PLL_ARM_POWERDOWN. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_POWERDOWN from a register value. +#define BG_CCM_ANALOG_PLL_ARM_POWERDOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_POWERDOWN) >> BP_CCM_ANALOG_PLL_ARM_POWERDOWN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ARM_POWERDOWN. +#define BF_CCM_ANALOG_PLL_ARM_POWERDOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ARM_POWERDOWN) & BM_CCM_ANALOG_PLL_ARM_POWERDOWN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POWERDOWN field to a new value. +#define BW_CCM_ANALOG_PLL_ARM_POWERDOWN(v) BF_CS1(CCM_ANALOG_PLL_ARM, POWERDOWN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ARM, field ENABLE[13] (RW) + * + * Enable the clock output. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_ENABLE (13) //!< Bit position for CCM_ANALOG_PLL_ARM_ENABLE. +#define BM_CCM_ANALOG_PLL_ARM_ENABLE (0x00002000) //!< Bit mask for CCM_ANALOG_PLL_ARM_ENABLE. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_ENABLE from a register value. +#define BG_CCM_ANALOG_PLL_ARM_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_ENABLE) >> BP_CCM_ANALOG_PLL_ARM_ENABLE) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ARM_ENABLE. +#define BF_CCM_ANALOG_PLL_ARM_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ARM_ENABLE) & BM_CCM_ANALOG_PLL_ARM_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE field to a new value. +#define BW_CCM_ANALOG_PLL_ARM_ENABLE(v) BF_CS1(CCM_ANALOG_PLL_ARM, ENABLE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ARM, field BYPASS_CLK_SRC[15:14] (RW) + * + * Determines the bypass source. + * + * Values: + * - REF_CLK_24M = 0x0 - Select the 24MHz oscillator as source. + * - CLK1 = 0x1 - Select the CLK1_N / CLK1_P as source. + * - CLK2 = 0x2 - Select the CLK2_N / CLK2_P as source. + * - XOR = 0x3 - Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC (14) //!< Bit position for CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC. +#define BM_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC (0x0000c000) //!< Bit mask for CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC from a register value. +#define BG_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC) >> BP_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC. +#define BF_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC) & BM_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_CLK_SRC field to a new value. +#define BW_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(v) BF_CS1(CCM_ANALOG_PLL_ARM, BYPASS_CLK_SRC, v) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_V(v) BF_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(BV_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC__##v) + +#define BV_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC__REF_CLK_24M (0x0) //!< Select the 24MHz oscillator as source. +#define BV_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC__CLK1 (0x1) //!< Select the CLK1_N / CLK1_P as source. +#define BV_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC__CLK2 (0x2) //!< Select the CLK2_N / CLK2_P as source. +#define BV_CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC__XOR (0x3) //!< Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. +//@} + +/*! @name Register CCM_ANALOG_PLL_ARM, field BYPASS[16] (RW) + * + * Bypass the pll. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_BYPASS (16) //!< Bit position for CCM_ANALOG_PLL_ARM_BYPASS. +#define BM_CCM_ANALOG_PLL_ARM_BYPASS (0x00010000) //!< Bit mask for CCM_ANALOG_PLL_ARM_BYPASS. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_BYPASS from a register value. +#define BG_CCM_ANALOG_PLL_ARM_BYPASS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_BYPASS) >> BP_CCM_ANALOG_PLL_ARM_BYPASS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ARM_BYPASS. +#define BF_CCM_ANALOG_PLL_ARM_BYPASS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ARM_BYPASS) & BM_CCM_ANALOG_PLL_ARM_BYPASS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS field to a new value. +#define BW_CCM_ANALOG_PLL_ARM_BYPASS(v) BF_CS1(CCM_ANALOG_PLL_ARM, BYPASS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ARM, field LVDS_SEL[17] (RW) + * + * Analog Debug Bit + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_LVDS_SEL (17) //!< Bit position for CCM_ANALOG_PLL_ARM_LVDS_SEL. +#define BM_CCM_ANALOG_PLL_ARM_LVDS_SEL (0x00020000) //!< Bit mask for CCM_ANALOG_PLL_ARM_LVDS_SEL. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_LVDS_SEL from a register value. +#define BG_CCM_ANALOG_PLL_ARM_LVDS_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_LVDS_SEL) >> BP_CCM_ANALOG_PLL_ARM_LVDS_SEL) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ARM_LVDS_SEL. +#define BF_CCM_ANALOG_PLL_ARM_LVDS_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ARM_LVDS_SEL) & BM_CCM_ANALOG_PLL_ARM_LVDS_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LVDS_SEL field to a new value. +#define BW_CCM_ANALOG_PLL_ARM_LVDS_SEL(v) BF_CS1(CCM_ANALOG_PLL_ARM, LVDS_SEL, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ARM, field LVDS_24MHZ_SEL[18] (RW) + * + * Analog Debug Bit + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL (18) //!< Bit position for CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL. +#define BM_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL (0x00040000) //!< Bit mask for CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL from a register value. +#define BG_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL) >> BP_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL. +#define BF_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL) & BM_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LVDS_24MHZ_SEL field to a new value. +#define BW_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL(v) BF_CS1(CCM_ANALOG_PLL_ARM, LVDS_24MHZ_SEL, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ARM, field PLL_SEL[19] (RW) + * + * Reserved + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_PLL_SEL (19) //!< Bit position for CCM_ANALOG_PLL_ARM_PLL_SEL. +#define BM_CCM_ANALOG_PLL_ARM_PLL_SEL (0x00080000) //!< Bit mask for CCM_ANALOG_PLL_ARM_PLL_SEL. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_PLL_SEL from a register value. +#define BG_CCM_ANALOG_PLL_ARM_PLL_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_PLL_SEL) >> BP_CCM_ANALOG_PLL_ARM_PLL_SEL) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ARM_PLL_SEL. +#define BF_CCM_ANALOG_PLL_ARM_PLL_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ARM_PLL_SEL) & BM_CCM_ANALOG_PLL_ARM_PLL_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PLL_SEL field to a new value. +#define BW_CCM_ANALOG_PLL_ARM_PLL_SEL(v) BF_CS1(CCM_ANALOG_PLL_ARM, PLL_SEL, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ARM, field LOCK[31] (RO) + * + * 1 - PLL is currently locked. 0 - PLL is not currently locked. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ARM_LOCK (31) //!< Bit position for CCM_ANALOG_PLL_ARM_LOCK. +#define BM_CCM_ANALOG_PLL_ARM_LOCK (0x80000000) //!< Bit mask for CCM_ANALOG_PLL_ARM_LOCK. + +//! @brief Get value of CCM_ANALOG_PLL_ARM_LOCK from a register value. +#define BG_CCM_ANALOG_PLL_ARM_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ARM_LOCK) >> BP_CCM_ANALOG_PLL_ARM_LOCK) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_USB1 - Analog USB1 480MHz PLL Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_USB1 - Analog USB1 480MHz PLL Control Register (RW) + * + * Reset value: 0x00012000 + * + * The control register provides control for USBPHY0 480MHz PLL. + */ +typedef union _hw_ccm_analog_pll_usb1 +{ + reg32_t U; + struct _hw_ccm_analog_pll_usb1_bitfields + { + unsigned DIV_SELECT : 2; //!< [1:0] This field controls the pll loop divider. + unsigned RESERVED0 : 4; //!< [5:2] Always set to zero (0). + unsigned EN_USB_CLKS : 1; //!< [6] Powers the 9-phase PLL outputs for USBPHYn. + unsigned RESERVED1 : 5; //!< [11:7] Always set to zero (0). + unsigned POWER : 1; //!< [12] Powers up the PLL. + unsigned ENABLE : 1; //!< [13] Enable the PLL clock output. + unsigned BYPASS_CLK_SRC : 2; //!< [15:14] Determines the bypass source. + unsigned BYPASS : 1; //!< [16] Bypass the pll. + unsigned RESERVED2 : 14; //!< [30:17] Always set to zero (0). + unsigned LOCK : 1; //!< [31] 1 - PLL is currently locked. + } B; +} hw_ccm_analog_pll_usb1_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_USB1 register + */ +//@{ +#define HW_CCM_ANALOG_PLL_USB1_ADDR (REGS_CCM_ANALOG_BASE + 0x10) +#define HW_CCM_ANALOG_PLL_USB1_SET_ADDR (HW_CCM_ANALOG_PLL_USB1_ADDR + 0x4) +#define HW_CCM_ANALOG_PLL_USB1_CLR_ADDR (HW_CCM_ANALOG_PLL_USB1_ADDR + 0x8) +#define HW_CCM_ANALOG_PLL_USB1_TOG_ADDR (HW_CCM_ANALOG_PLL_USB1_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_USB1 (*(volatile hw_ccm_analog_pll_usb1_t *) HW_CCM_ANALOG_PLL_USB1_ADDR) +#define HW_CCM_ANALOG_PLL_USB1_RD() (HW_CCM_ANALOG_PLL_USB1.U) +#define HW_CCM_ANALOG_PLL_USB1_WR(v) (HW_CCM_ANALOG_PLL_USB1.U = (v)) +#define HW_CCM_ANALOG_PLL_USB1_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_USB1_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_USB1_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_USB1_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_USB1_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_USB1_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_USB1 bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_USB1, field DIV_SELECT[1:0] (RW) + * + * This field controls the pll loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB1_DIV_SELECT (0) //!< Bit position for CCM_ANALOG_PLL_USB1_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_USB1_DIV_SELECT (0x00000003) //!< Bit mask for CCM_ANALOG_PLL_USB1_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_USB1_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_USB1_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB1_DIV_SELECT) >> BP_CCM_ANALOG_PLL_USB1_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB1_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_USB1_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB1_DIV_SELECT) & BM_CCM_ANALOG_PLL_USB1_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_USB1_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_USB1, DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB1, field EN_USB_CLKS[6] (RW) + * + * Powers the 9-phase PLL outputs for USBPHYn. Additionally, the UTMI clock gate must be deasserted + * in the USBPHYn to enable USBn operation (clear CLKGATE bit in USBPHYn_CTRL). This bit will be set + * automatically when USBPHYn remote wakeup event occurs. + * + * Values: + * - 0 - PLL outputs for USBPHYn off. + * - 1 - PLL outputs for USBPHYn on. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB1_EN_USB_CLKS (6) //!< Bit position for CCM_ANALOG_PLL_USB1_EN_USB_CLKS. +#define BM_CCM_ANALOG_PLL_USB1_EN_USB_CLKS (0x00000040) //!< Bit mask for CCM_ANALOG_PLL_USB1_EN_USB_CLKS. + +//! @brief Get value of CCM_ANALOG_PLL_USB1_EN_USB_CLKS from a register value. +#define BG_CCM_ANALOG_PLL_USB1_EN_USB_CLKS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB1_EN_USB_CLKS) >> BP_CCM_ANALOG_PLL_USB1_EN_USB_CLKS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB1_EN_USB_CLKS. +#define BF_CCM_ANALOG_PLL_USB1_EN_USB_CLKS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB1_EN_USB_CLKS) & BM_CCM_ANALOG_PLL_USB1_EN_USB_CLKS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_USB_CLKS field to a new value. +#define BW_CCM_ANALOG_PLL_USB1_EN_USB_CLKS(v) BF_CS1(CCM_ANALOG_PLL_USB1, EN_USB_CLKS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB1, field POWER[12] (RW) + * + * Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB1_POWER (12) //!< Bit position for CCM_ANALOG_PLL_USB1_POWER. +#define BM_CCM_ANALOG_PLL_USB1_POWER (0x00001000) //!< Bit mask for CCM_ANALOG_PLL_USB1_POWER. + +//! @brief Get value of CCM_ANALOG_PLL_USB1_POWER from a register value. +#define BG_CCM_ANALOG_PLL_USB1_POWER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB1_POWER) >> BP_CCM_ANALOG_PLL_USB1_POWER) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB1_POWER. +#define BF_CCM_ANALOG_PLL_USB1_POWER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB1_POWER) & BM_CCM_ANALOG_PLL_USB1_POWER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POWER field to a new value. +#define BW_CCM_ANALOG_PLL_USB1_POWER(v) BF_CS1(CCM_ANALOG_PLL_USB1, POWER, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB1, field ENABLE[13] (RW) + * + * Enable the PLL clock output. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB1_ENABLE (13) //!< Bit position for CCM_ANALOG_PLL_USB1_ENABLE. +#define BM_CCM_ANALOG_PLL_USB1_ENABLE (0x00002000) //!< Bit mask for CCM_ANALOG_PLL_USB1_ENABLE. + +//! @brief Get value of CCM_ANALOG_PLL_USB1_ENABLE from a register value. +#define BG_CCM_ANALOG_PLL_USB1_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB1_ENABLE) >> BP_CCM_ANALOG_PLL_USB1_ENABLE) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB1_ENABLE. +#define BF_CCM_ANALOG_PLL_USB1_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB1_ENABLE) & BM_CCM_ANALOG_PLL_USB1_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE field to a new value. +#define BW_CCM_ANALOG_PLL_USB1_ENABLE(v) BF_CS1(CCM_ANALOG_PLL_USB1, ENABLE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB1, field BYPASS_CLK_SRC[15:14] (RW) + * + * Determines the bypass source. + * + * Values: + * - REF_CLK_24M = 0x0 - Select the 24MHz oscillator as source. + * - CLK1 = 0x1 - Select the CLK1_N / CLK1_P as source. + * - CLK2 = 0x2 - Select the CLK2_N / CLK2_P as source. + * - XOR = 0x3 - Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC (14) //!< Bit position for CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC. +#define BM_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC (0x0000c000) //!< Bit mask for CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC. + +//! @brief Get value of CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC from a register value. +#define BG_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC) >> BP_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC. +#define BF_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC) & BM_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_CLK_SRC field to a new value. +#define BW_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(v) BF_CS1(CCM_ANALOG_PLL_USB1, BYPASS_CLK_SRC, v) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_V(v) BF_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(BV_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC__##v) + +#define BV_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC__REF_CLK_24M (0x0) //!< Select the 24MHz oscillator as source. +#define BV_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC__CLK1 (0x1) //!< Select the CLK1_N / CLK1_P as source. +#define BV_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC__CLK2 (0x2) //!< Select the CLK2_N / CLK2_P as source. +#define BV_CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC__XOR (0x3) //!< Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. +//@} + +/*! @name Register CCM_ANALOG_PLL_USB1, field BYPASS[16] (RW) + * + * Bypass the pll. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB1_BYPASS (16) //!< Bit position for CCM_ANALOG_PLL_USB1_BYPASS. +#define BM_CCM_ANALOG_PLL_USB1_BYPASS (0x00010000) //!< Bit mask for CCM_ANALOG_PLL_USB1_BYPASS. + +//! @brief Get value of CCM_ANALOG_PLL_USB1_BYPASS from a register value. +#define BG_CCM_ANALOG_PLL_USB1_BYPASS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB1_BYPASS) >> BP_CCM_ANALOG_PLL_USB1_BYPASS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB1_BYPASS. +#define BF_CCM_ANALOG_PLL_USB1_BYPASS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB1_BYPASS) & BM_CCM_ANALOG_PLL_USB1_BYPASS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS field to a new value. +#define BW_CCM_ANALOG_PLL_USB1_BYPASS(v) BF_CS1(CCM_ANALOG_PLL_USB1, BYPASS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB1, field LOCK[31] (RO) + * + * 1 - PLL is currently locked. 0 - PLL is not currently locked. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB1_LOCK (31) //!< Bit position for CCM_ANALOG_PLL_USB1_LOCK. +#define BM_CCM_ANALOG_PLL_USB1_LOCK (0x80000000) //!< Bit mask for CCM_ANALOG_PLL_USB1_LOCK. + +//! @brief Get value of CCM_ANALOG_PLL_USB1_LOCK from a register value. +#define BG_CCM_ANALOG_PLL_USB1_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB1_LOCK) >> BP_CCM_ANALOG_PLL_USB1_LOCK) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_USB2 - Analog USB2 480MHz PLL Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_USB2 - Analog USB2 480MHz PLL Control Register (RW) + * + * Reset value: 0x00012000 + * + * The control register provides control for USBPHY1 480MHz PLL. + */ +typedef union _hw_ccm_analog_pll_usb2 +{ + reg32_t U; + struct _hw_ccm_analog_pll_usb2_bitfields + { + unsigned DIV_SELECT : 2; //!< [1:0] This field controls the pll loop divider. + unsigned RESERVED0 : 4; //!< [5:2] Always set to zero (0). + unsigned EN_USB_CLKS : 1; //!< [6] 0: 8-phase PLL outputs for USBPHY1 are powered down. + unsigned RESERVED1 : 5; //!< [11:7] Always set to zero (0). + unsigned POWER : 1; //!< [12] Powers up the PLL. + unsigned ENABLE : 1; //!< [13] Enable the PLL clock output. + unsigned BYPASS_CLK_SRC : 2; //!< [15:14] Determines the bypass source. + unsigned BYPASS : 1; //!< [16] Bypass the pll. + unsigned RESERVED2 : 14; //!< [30:17] Always set to zero (0). + unsigned LOCK : 1; //!< [31] 1 - PLL is currently locked. + } B; +} hw_ccm_analog_pll_usb2_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_USB2 register + */ +//@{ +#define HW_CCM_ANALOG_PLL_USB2_ADDR (REGS_CCM_ANALOG_BASE + 0x20) +#define HW_CCM_ANALOG_PLL_USB2_SET_ADDR (HW_CCM_ANALOG_PLL_USB2_ADDR + 0x4) +#define HW_CCM_ANALOG_PLL_USB2_CLR_ADDR (HW_CCM_ANALOG_PLL_USB2_ADDR + 0x8) +#define HW_CCM_ANALOG_PLL_USB2_TOG_ADDR (HW_CCM_ANALOG_PLL_USB2_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_USB2 (*(volatile hw_ccm_analog_pll_usb2_t *) HW_CCM_ANALOG_PLL_USB2_ADDR) +#define HW_CCM_ANALOG_PLL_USB2_RD() (HW_CCM_ANALOG_PLL_USB2.U) +#define HW_CCM_ANALOG_PLL_USB2_WR(v) (HW_CCM_ANALOG_PLL_USB2.U = (v)) +#define HW_CCM_ANALOG_PLL_USB2_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_USB2_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_USB2_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_USB2_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_USB2_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_USB2_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_USB2 bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_USB2, field DIV_SELECT[1:0] (RW) + * + * This field controls the pll loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB2_DIV_SELECT (0) //!< Bit position for CCM_ANALOG_PLL_USB2_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_USB2_DIV_SELECT (0x00000003) //!< Bit mask for CCM_ANALOG_PLL_USB2_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_USB2_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_USB2_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB2_DIV_SELECT) >> BP_CCM_ANALOG_PLL_USB2_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB2_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_USB2_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB2_DIV_SELECT) & BM_CCM_ANALOG_PLL_USB2_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_USB2_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_USB2, DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB2, field EN_USB_CLKS[6] (RW) + * + * 0: 8-phase PLL outputs for USBPHY1 are powered down. If set to 1, 8-phase PLL outputs for USBPHY1 + * are powered up. Additionally, the utmi clock gate must be deasserted in the USBPHY1 to enable + * USB0 operation (clear CLKGATE bit in USBPHY1_CTRL).This bit will be set automatically when + * USBPHY1 remote wakeup event happens. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB2_EN_USB_CLKS (6) //!< Bit position for CCM_ANALOG_PLL_USB2_EN_USB_CLKS. +#define BM_CCM_ANALOG_PLL_USB2_EN_USB_CLKS (0x00000040) //!< Bit mask for CCM_ANALOG_PLL_USB2_EN_USB_CLKS. + +//! @brief Get value of CCM_ANALOG_PLL_USB2_EN_USB_CLKS from a register value. +#define BG_CCM_ANALOG_PLL_USB2_EN_USB_CLKS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB2_EN_USB_CLKS) >> BP_CCM_ANALOG_PLL_USB2_EN_USB_CLKS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB2_EN_USB_CLKS. +#define BF_CCM_ANALOG_PLL_USB2_EN_USB_CLKS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB2_EN_USB_CLKS) & BM_CCM_ANALOG_PLL_USB2_EN_USB_CLKS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_USB_CLKS field to a new value. +#define BW_CCM_ANALOG_PLL_USB2_EN_USB_CLKS(v) BF_CS1(CCM_ANALOG_PLL_USB2, EN_USB_CLKS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB2, field POWER[12] (RW) + * + * Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB2_POWER (12) //!< Bit position for CCM_ANALOG_PLL_USB2_POWER. +#define BM_CCM_ANALOG_PLL_USB2_POWER (0x00001000) //!< Bit mask for CCM_ANALOG_PLL_USB2_POWER. + +//! @brief Get value of CCM_ANALOG_PLL_USB2_POWER from a register value. +#define BG_CCM_ANALOG_PLL_USB2_POWER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB2_POWER) >> BP_CCM_ANALOG_PLL_USB2_POWER) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB2_POWER. +#define BF_CCM_ANALOG_PLL_USB2_POWER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB2_POWER) & BM_CCM_ANALOG_PLL_USB2_POWER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POWER field to a new value. +#define BW_CCM_ANALOG_PLL_USB2_POWER(v) BF_CS1(CCM_ANALOG_PLL_USB2, POWER, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB2, field ENABLE[13] (RW) + * + * Enable the PLL clock output. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB2_ENABLE (13) //!< Bit position for CCM_ANALOG_PLL_USB2_ENABLE. +#define BM_CCM_ANALOG_PLL_USB2_ENABLE (0x00002000) //!< Bit mask for CCM_ANALOG_PLL_USB2_ENABLE. + +//! @brief Get value of CCM_ANALOG_PLL_USB2_ENABLE from a register value. +#define BG_CCM_ANALOG_PLL_USB2_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB2_ENABLE) >> BP_CCM_ANALOG_PLL_USB2_ENABLE) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB2_ENABLE. +#define BF_CCM_ANALOG_PLL_USB2_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB2_ENABLE) & BM_CCM_ANALOG_PLL_USB2_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE field to a new value. +#define BW_CCM_ANALOG_PLL_USB2_ENABLE(v) BF_CS1(CCM_ANALOG_PLL_USB2, ENABLE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB2, field BYPASS_CLK_SRC[15:14] (RW) + * + * Determines the bypass source. + * + * Values: + * - REF_CLK_24M = 0x0 - Select the 24MHz oscillator as source. + * - CLK1 = 0x1 - Select the CLK1_N / CLK1_P as source. + * - CLK2 = 0x2 - Select the CLK2_N / CLK2_P as source. + * - XOR = 0x3 - Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC (14) //!< Bit position for CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC. +#define BM_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC (0x0000c000) //!< Bit mask for CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC. + +//! @brief Get value of CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC from a register value. +#define BG_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC) >> BP_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC. +#define BF_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC) & BM_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_CLK_SRC field to a new value. +#define BW_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(v) BF_CS1(CCM_ANALOG_PLL_USB2, BYPASS_CLK_SRC, v) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_V(v) BF_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(BV_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC__##v) + +#define BV_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC__REF_CLK_24M (0x0) //!< Select the 24MHz oscillator as source. +#define BV_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC__CLK1 (0x1) //!< Select the CLK1_N / CLK1_P as source. +#define BV_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC__CLK2 (0x2) //!< Select the CLK2_N / CLK2_P as source. +#define BV_CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC__XOR (0x3) //!< Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. +//@} + +/*! @name Register CCM_ANALOG_PLL_USB2, field BYPASS[16] (RW) + * + * Bypass the pll. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB2_BYPASS (16) //!< Bit position for CCM_ANALOG_PLL_USB2_BYPASS. +#define BM_CCM_ANALOG_PLL_USB2_BYPASS (0x00010000) //!< Bit mask for CCM_ANALOG_PLL_USB2_BYPASS. + +//! @brief Get value of CCM_ANALOG_PLL_USB2_BYPASS from a register value. +#define BG_CCM_ANALOG_PLL_USB2_BYPASS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB2_BYPASS) >> BP_CCM_ANALOG_PLL_USB2_BYPASS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_USB2_BYPASS. +#define BF_CCM_ANALOG_PLL_USB2_BYPASS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_USB2_BYPASS) & BM_CCM_ANALOG_PLL_USB2_BYPASS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS field to a new value. +#define BW_CCM_ANALOG_PLL_USB2_BYPASS(v) BF_CS1(CCM_ANALOG_PLL_USB2, BYPASS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_USB2, field LOCK[31] (RO) + * + * 1 - PLL is currently locked. 0 - PLL is not currently locked. + */ +//@{ +#define BP_CCM_ANALOG_PLL_USB2_LOCK (31) //!< Bit position for CCM_ANALOG_PLL_USB2_LOCK. +#define BM_CCM_ANALOG_PLL_USB2_LOCK (0x80000000) //!< Bit mask for CCM_ANALOG_PLL_USB2_LOCK. + +//! @brief Get value of CCM_ANALOG_PLL_USB2_LOCK from a register value. +#define BG_CCM_ANALOG_PLL_USB2_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_USB2_LOCK) >> BP_CCM_ANALOG_PLL_USB2_LOCK) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_SYS - Analog System PLL Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_SYS - Analog System PLL Control Register (RW) + * + * Reset value: 0x00013001 + * + * The control register provides control for the 528MHz PLL. + */ +typedef union _hw_ccm_analog_pll_sys +{ + reg32_t U; + struct _hw_ccm_analog_pll_sys_bitfields + { + unsigned DIV_SELECT : 1; //!< [0] This field controls the pll loop divider. + unsigned RESERVED0 : 11; //!< [11:1] Reserved. + unsigned POWERDOWN : 1; //!< [12] Powers down the PLL. + unsigned ENABLE : 1; //!< [13] Enable PLL output + unsigned BYPASS_CLK_SRC : 2; //!< [15:14] Determines the bypass source. + unsigned BYPASS : 1; //!< [16] Bypass the pll. + unsigned RESERVED1 : 1; //!< [17] Reserved + unsigned PFD_OFFSET_EN : 1; //!< [18] Enables an offset in the phase frequency detector. + unsigned RESERVED2 : 12; //!< [30:19] Always set to zero (0). + unsigned LOCK : 1; //!< [31] 1 - PLL is currently locked; 0 - PLL is not currently locked. + } B; +} hw_ccm_analog_pll_sys_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_SYS register + */ +//@{ +#define HW_CCM_ANALOG_PLL_SYS_ADDR (REGS_CCM_ANALOG_BASE + 0x30) +#define HW_CCM_ANALOG_PLL_SYS_SET_ADDR (HW_CCM_ANALOG_PLL_SYS_ADDR + 0x4) +#define HW_CCM_ANALOG_PLL_SYS_CLR_ADDR (HW_CCM_ANALOG_PLL_SYS_ADDR + 0x8) +#define HW_CCM_ANALOG_PLL_SYS_TOG_ADDR (HW_CCM_ANALOG_PLL_SYS_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_SYS (*(volatile hw_ccm_analog_pll_sys_t *) HW_CCM_ANALOG_PLL_SYS_ADDR) +#define HW_CCM_ANALOG_PLL_SYS_RD() (HW_CCM_ANALOG_PLL_SYS.U) +#define HW_CCM_ANALOG_PLL_SYS_WR(v) (HW_CCM_ANALOG_PLL_SYS.U = (v)) +#define HW_CCM_ANALOG_PLL_SYS_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_SYS_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_SYS_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_SYS_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_SYS_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_SYS_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_SYS bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_SYS, field DIV_SELECT[0] (RW) + * + * This field controls the pll loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_DIV_SELECT (0) //!< Bit position for CCM_ANALOG_PLL_SYS_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_SYS_DIV_SELECT (0x00000001) //!< Bit mask for CCM_ANALOG_PLL_SYS_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_SYS_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_DIV_SELECT) >> BP_CCM_ANALOG_PLL_SYS_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_SYS_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_DIV_SELECT) & BM_CCM_ANALOG_PLL_SYS_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_SYS, DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_SYS, field POWERDOWN[12] (RW) + * + * Powers down the PLL. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_POWERDOWN (12) //!< Bit position for CCM_ANALOG_PLL_SYS_POWERDOWN. +#define BM_CCM_ANALOG_PLL_SYS_POWERDOWN (0x00001000) //!< Bit mask for CCM_ANALOG_PLL_SYS_POWERDOWN. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_POWERDOWN from a register value. +#define BG_CCM_ANALOG_PLL_SYS_POWERDOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_POWERDOWN) >> BP_CCM_ANALOG_PLL_SYS_POWERDOWN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_POWERDOWN. +#define BF_CCM_ANALOG_PLL_SYS_POWERDOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_POWERDOWN) & BM_CCM_ANALOG_PLL_SYS_POWERDOWN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POWERDOWN field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_POWERDOWN(v) BF_CS1(CCM_ANALOG_PLL_SYS, POWERDOWN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_SYS, field ENABLE[13] (RW) + * + * Enable PLL output + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_ENABLE (13) //!< Bit position for CCM_ANALOG_PLL_SYS_ENABLE. +#define BM_CCM_ANALOG_PLL_SYS_ENABLE (0x00002000) //!< Bit mask for CCM_ANALOG_PLL_SYS_ENABLE. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_ENABLE from a register value. +#define BG_CCM_ANALOG_PLL_SYS_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_ENABLE) >> BP_CCM_ANALOG_PLL_SYS_ENABLE) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_ENABLE. +#define BF_CCM_ANALOG_PLL_SYS_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_ENABLE) & BM_CCM_ANALOG_PLL_SYS_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_ENABLE(v) BF_CS1(CCM_ANALOG_PLL_SYS, ENABLE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_SYS, field BYPASS_CLK_SRC[15:14] (RW) + * + * Determines the bypass source. + * + * Values: + * - REF_CLK_24M = 0x0 - Select the 24MHz oscillator as source. + * - CLK1 = 0x1 - Select the CLK1_N / CLK1_P as source. + * - CLK2 = 0x2 - Select the CLK2_N / CLK2_P as source. + * - XOR = 0x3 - Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC (14) //!< Bit position for CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC. +#define BM_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC (0x0000c000) //!< Bit mask for CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC from a register value. +#define BG_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC) >> BP_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC. +#define BF_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC) & BM_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_CLK_SRC field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(v) BF_CS1(CCM_ANALOG_PLL_SYS, BYPASS_CLK_SRC, v) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_V(v) BF_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(BV_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC__##v) + +#define BV_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC__REF_CLK_24M (0x0) //!< Select the 24MHz oscillator as source. +#define BV_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC__CLK1 (0x1) //!< Select the CLK1_N / CLK1_P as source. +#define BV_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC__CLK2 (0x2) //!< Select the CLK2_N / CLK2_P as source. +#define BV_CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC__XOR (0x3) //!< Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. +//@} + +/*! @name Register CCM_ANALOG_PLL_SYS, field BYPASS[16] (RW) + * + * Bypass the pll. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_BYPASS (16) //!< Bit position for CCM_ANALOG_PLL_SYS_BYPASS. +#define BM_CCM_ANALOG_PLL_SYS_BYPASS (0x00010000) //!< Bit mask for CCM_ANALOG_PLL_SYS_BYPASS. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_BYPASS from a register value. +#define BG_CCM_ANALOG_PLL_SYS_BYPASS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_BYPASS) >> BP_CCM_ANALOG_PLL_SYS_BYPASS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_BYPASS. +#define BF_CCM_ANALOG_PLL_SYS_BYPASS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_BYPASS) & BM_CCM_ANALOG_PLL_SYS_BYPASS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_BYPASS(v) BF_CS1(CCM_ANALOG_PLL_SYS, BYPASS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_SYS, field PFD_OFFSET_EN[18] (RW) + * + * Enables an offset in the phase frequency detector. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (18) //!< Bit position for CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN. +#define BM_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (0x00040000) //!< Bit mask for CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN from a register value. +#define BG_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN) >> BP_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN. +#define BF_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN) & BM_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD_OFFSET_EN field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(v) BF_CS1(CCM_ANALOG_PLL_SYS, PFD_OFFSET_EN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_SYS, field LOCK[31] (RO) + * + * 1 - PLL is currently locked; 0 - PLL is not currently locked. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_LOCK (31) //!< Bit position for CCM_ANALOG_PLL_SYS_LOCK. +#define BM_CCM_ANALOG_PLL_SYS_LOCK (0x80000000) //!< Bit mask for CCM_ANALOG_PLL_SYS_LOCK. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_LOCK from a register value. +#define BG_CCM_ANALOG_PLL_SYS_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_LOCK) >> BP_CCM_ANALOG_PLL_SYS_LOCK) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register. +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register. (RW) + * + * Reset value: 0x00000000 + * + * This register contains the 528 PLL spread spectrum controls. + */ +typedef union _hw_ccm_analog_pll_sys_ss +{ + reg32_t U; + struct _hw_ccm_analog_pll_sys_ss_bitfields + { + unsigned STEP : 15; //!< [14:0] frequency change step = step/B*24MHz. + unsigned ENABLE : 1; //!< [15] This bit enables the spread spectrum modulation. + unsigned STOP : 16; //!< [31:16] Frequency change = stop/B*24MHz. + } B; +} hw_ccm_analog_pll_sys_ss_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_SYS_SS register + */ +//@{ +#define HW_CCM_ANALOG_PLL_SYS_SS_ADDR (REGS_CCM_ANALOG_BASE + 0x40) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_SYS_SS (*(volatile hw_ccm_analog_pll_sys_ss_t *) HW_CCM_ANALOG_PLL_SYS_SS_ADDR) +#define HW_CCM_ANALOG_PLL_SYS_SS_RD() (HW_CCM_ANALOG_PLL_SYS_SS.U) +#define HW_CCM_ANALOG_PLL_SYS_SS_WR(v) (HW_CCM_ANALOG_PLL_SYS_SS.U = (v)) +#define HW_CCM_ANALOG_PLL_SYS_SS_SET(v) (HW_CCM_ANALOG_PLL_SYS_SS_WR(HW_CCM_ANALOG_PLL_SYS_SS_RD() | (v))) +#define HW_CCM_ANALOG_PLL_SYS_SS_CLR(v) (HW_CCM_ANALOG_PLL_SYS_SS_WR(HW_CCM_ANALOG_PLL_SYS_SS_RD() & ~(v))) +#define HW_CCM_ANALOG_PLL_SYS_SS_TOG(v) (HW_CCM_ANALOG_PLL_SYS_SS_WR(HW_CCM_ANALOG_PLL_SYS_SS_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_SYS_SS bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_SYS_SS, field STEP[14:0] (RW) + * + * frequency change step = step/B*24MHz. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_SS_STEP (0) //!< Bit position for CCM_ANALOG_PLL_SYS_SS_STEP. +#define BM_CCM_ANALOG_PLL_SYS_SS_STEP (0x00007fff) //!< Bit mask for CCM_ANALOG_PLL_SYS_SS_STEP. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_SS_STEP from a register value. +#define BG_CCM_ANALOG_PLL_SYS_SS_STEP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_SS_STEP) >> BP_CCM_ANALOG_PLL_SYS_SS_STEP) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_SS_STEP. +#define BF_CCM_ANALOG_PLL_SYS_SS_STEP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_SS_STEP) & BM_CCM_ANALOG_PLL_SYS_SS_STEP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STEP field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_SS_STEP(v) (HW_CCM_ANALOG_PLL_SYS_SS_WR((HW_CCM_ANALOG_PLL_SYS_SS_RD() & ~BM_CCM_ANALOG_PLL_SYS_SS_STEP) | BF_CCM_ANALOG_PLL_SYS_SS_STEP(v))) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_SYS_SS, field ENABLE[15] (RW) + * + * This bit enables the spread spectrum modulation. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_SS_ENABLE (15) //!< Bit position for CCM_ANALOG_PLL_SYS_SS_ENABLE. +#define BM_CCM_ANALOG_PLL_SYS_SS_ENABLE (0x00008000) //!< Bit mask for CCM_ANALOG_PLL_SYS_SS_ENABLE. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_SS_ENABLE from a register value. +#define BG_CCM_ANALOG_PLL_SYS_SS_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_SS_ENABLE) >> BP_CCM_ANALOG_PLL_SYS_SS_ENABLE) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_SS_ENABLE. +#define BF_CCM_ANALOG_PLL_SYS_SS_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_SS_ENABLE) & BM_CCM_ANALOG_PLL_SYS_SS_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_SS_ENABLE(v) (HW_CCM_ANALOG_PLL_SYS_SS_WR((HW_CCM_ANALOG_PLL_SYS_SS_RD() & ~BM_CCM_ANALOG_PLL_SYS_SS_ENABLE) | BF_CCM_ANALOG_PLL_SYS_SS_ENABLE(v))) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_SYS_SS, field STOP[31:16] (RW) + * + * Frequency change = stop/B*24MHz. + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_SS_STOP (16) //!< Bit position for CCM_ANALOG_PLL_SYS_SS_STOP. +#define BM_CCM_ANALOG_PLL_SYS_SS_STOP (0xffff0000) //!< Bit mask for CCM_ANALOG_PLL_SYS_SS_STOP. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_SS_STOP from a register value. +#define BG_CCM_ANALOG_PLL_SYS_SS_STOP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_SS_STOP) >> BP_CCM_ANALOG_PLL_SYS_SS_STOP) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_SS_STOP. +#define BF_CCM_ANALOG_PLL_SYS_SS_STOP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_SS_STOP) & BM_CCM_ANALOG_PLL_SYS_SS_STOP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STOP field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_SS_STOP(v) (HW_CCM_ANALOG_PLL_SYS_SS_WR((HW_CCM_ANALOG_PLL_SYS_SS_RD() & ~BM_CCM_ANALOG_PLL_SYS_SS_STOP) | BF_CCM_ANALOG_PLL_SYS_SS_STOP(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register (RW) + * + * Reset value: 0x00000000 + * + * This register contains the numerator of 528MHz PLL fractional loop divider (signed number). + * Absoulte value should be less than denominator + */ +typedef union _hw_ccm_analog_pll_sys_num +{ + reg32_t U; + struct _hw_ccm_analog_pll_sys_num_bitfields + { + unsigned A : 30; //!< [29:0] 30 bit numerator (A) of fractional loop divider (signed integer). + unsigned RESERVED0 : 2; //!< [31:30] Always set to zero (0). + } B; +} hw_ccm_analog_pll_sys_num_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_SYS_NUM register + */ +//@{ +#define HW_CCM_ANALOG_PLL_SYS_NUM_ADDR (REGS_CCM_ANALOG_BASE + 0x50) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_SYS_NUM (*(volatile hw_ccm_analog_pll_sys_num_t *) HW_CCM_ANALOG_PLL_SYS_NUM_ADDR) +#define HW_CCM_ANALOG_PLL_SYS_NUM_RD() (HW_CCM_ANALOG_PLL_SYS_NUM.U) +#define HW_CCM_ANALOG_PLL_SYS_NUM_WR(v) (HW_CCM_ANALOG_PLL_SYS_NUM.U = (v)) +#define HW_CCM_ANALOG_PLL_SYS_NUM_SET(v) (HW_CCM_ANALOG_PLL_SYS_NUM_WR(HW_CCM_ANALOG_PLL_SYS_NUM_RD() | (v))) +#define HW_CCM_ANALOG_PLL_SYS_NUM_CLR(v) (HW_CCM_ANALOG_PLL_SYS_NUM_WR(HW_CCM_ANALOG_PLL_SYS_NUM_RD() & ~(v))) +#define HW_CCM_ANALOG_PLL_SYS_NUM_TOG(v) (HW_CCM_ANALOG_PLL_SYS_NUM_WR(HW_CCM_ANALOG_PLL_SYS_NUM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_SYS_NUM bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_SYS_NUM, field A[29:0] (RW) + * + * 30 bit numerator (A) of fractional loop divider (signed integer). + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_NUM_A (0) //!< Bit position for CCM_ANALOG_PLL_SYS_NUM_A. +#define BM_CCM_ANALOG_PLL_SYS_NUM_A (0x3fffffff) //!< Bit mask for CCM_ANALOG_PLL_SYS_NUM_A. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_NUM_A from a register value. +#define BG_CCM_ANALOG_PLL_SYS_NUM_A(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_NUM_A) >> BP_CCM_ANALOG_PLL_SYS_NUM_A) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_NUM_A. +#define BF_CCM_ANALOG_PLL_SYS_NUM_A(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_NUM_A) & BM_CCM_ANALOG_PLL_SYS_NUM_A) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the A field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_NUM_A(v) (HW_CCM_ANALOG_PLL_SYS_NUM_WR((HW_CCM_ANALOG_PLL_SYS_NUM_RD() & ~BM_CCM_ANALOG_PLL_SYS_NUM_A) | BF_CCM_ANALOG_PLL_SYS_NUM_A(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register (RW) + * + * Reset value: 0x00000012 + * + * This register contains the Denominator of 528MHz PLL fractional loop divider. + */ +typedef union _hw_ccm_analog_pll_sys_denom +{ + reg32_t U; + struct _hw_ccm_analog_pll_sys_denom_bitfields + { + unsigned B : 30; //!< [29:0] 30 bit Denominator (B) of fractional loop divider (unsigned integer). + unsigned RESERVED0 : 2; //!< [31:30] Always set to zero (0). + } B; +} hw_ccm_analog_pll_sys_denom_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_SYS_DENOM register + */ +//@{ +#define HW_CCM_ANALOG_PLL_SYS_DENOM_ADDR (REGS_CCM_ANALOG_BASE + 0x60) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_SYS_DENOM (*(volatile hw_ccm_analog_pll_sys_denom_t *) HW_CCM_ANALOG_PLL_SYS_DENOM_ADDR) +#define HW_CCM_ANALOG_PLL_SYS_DENOM_RD() (HW_CCM_ANALOG_PLL_SYS_DENOM.U) +#define HW_CCM_ANALOG_PLL_SYS_DENOM_WR(v) (HW_CCM_ANALOG_PLL_SYS_DENOM.U = (v)) +#define HW_CCM_ANALOG_PLL_SYS_DENOM_SET(v) (HW_CCM_ANALOG_PLL_SYS_DENOM_WR(HW_CCM_ANALOG_PLL_SYS_DENOM_RD() | (v))) +#define HW_CCM_ANALOG_PLL_SYS_DENOM_CLR(v) (HW_CCM_ANALOG_PLL_SYS_DENOM_WR(HW_CCM_ANALOG_PLL_SYS_DENOM_RD() & ~(v))) +#define HW_CCM_ANALOG_PLL_SYS_DENOM_TOG(v) (HW_CCM_ANALOG_PLL_SYS_DENOM_WR(HW_CCM_ANALOG_PLL_SYS_DENOM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_SYS_DENOM bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_SYS_DENOM, field B[29:0] (RW) + * + * 30 bit Denominator (B) of fractional loop divider (unsigned integer). + */ +//@{ +#define BP_CCM_ANALOG_PLL_SYS_DENOM_B (0) //!< Bit position for CCM_ANALOG_PLL_SYS_DENOM_B. +#define BM_CCM_ANALOG_PLL_SYS_DENOM_B (0x3fffffff) //!< Bit mask for CCM_ANALOG_PLL_SYS_DENOM_B. + +//! @brief Get value of CCM_ANALOG_PLL_SYS_DENOM_B from a register value. +#define BG_CCM_ANALOG_PLL_SYS_DENOM_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_SYS_DENOM_B) >> BP_CCM_ANALOG_PLL_SYS_DENOM_B) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_SYS_DENOM_B. +#define BF_CCM_ANALOG_PLL_SYS_DENOM_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_SYS_DENOM_B) & BM_CCM_ANALOG_PLL_SYS_DENOM_B) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the B field to a new value. +#define BW_CCM_ANALOG_PLL_SYS_DENOM_B(v) (HW_CCM_ANALOG_PLL_SYS_DENOM_WR((HW_CCM_ANALOG_PLL_SYS_DENOM_RD() & ~BM_CCM_ANALOG_PLL_SYS_DENOM_B) | BF_CCM_ANALOG_PLL_SYS_DENOM_B(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_AUDIO - Analog Audio PLL control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_AUDIO - Analog Audio PLL control Register (RW) + * + * Reset value: 0x00011006 + * + * The control register provides control for the audio PLL. + */ +typedef union _hw_ccm_analog_pll_audio +{ + reg32_t U; + struct _hw_ccm_analog_pll_audio_bitfields + { + unsigned DIV_SELECT : 7; //!< [6:0] This field controls the pll loop divider. + unsigned RESERVED0 : 5; //!< [11:7] Reserved. + unsigned POWERDOWN : 1; //!< [12] Powers down the PLL. + unsigned ENABLE : 1; //!< [13] Enable PLL output + unsigned BYPASS_CLK_SRC : 2; //!< [15:14] Determines the bypass source. + unsigned BYPASS : 1; //!< [16] Bypass the pll. + unsigned RESERVED1 : 1; //!< [17] Revsered + unsigned PFD_OFFSET_EN : 1; //!< [18] Enables an offset in the phase frequency detector. + unsigned POST_DIV_SELECT : 2; //!< [20:19] These bits implement a divider after the PLL, but before the enable and bypass mux. + unsigned SSC_EN : 1; //!< [21] Reserved Bit + unsigned RESERVED2 : 9; //!< [30:22] Always set to zero (0). + unsigned LOCK : 1; //!< [31] 1 - PLL is currently locked. + } B; +} hw_ccm_analog_pll_audio_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_AUDIO register + */ +//@{ +#define HW_CCM_ANALOG_PLL_AUDIO_ADDR (REGS_CCM_ANALOG_BASE + 0x70) +#define HW_CCM_ANALOG_PLL_AUDIO_SET_ADDR (HW_CCM_ANALOG_PLL_AUDIO_ADDR + 0x4) +#define HW_CCM_ANALOG_PLL_AUDIO_CLR_ADDR (HW_CCM_ANALOG_PLL_AUDIO_ADDR + 0x8) +#define HW_CCM_ANALOG_PLL_AUDIO_TOG_ADDR (HW_CCM_ANALOG_PLL_AUDIO_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_AUDIO (*(volatile hw_ccm_analog_pll_audio_t *) HW_CCM_ANALOG_PLL_AUDIO_ADDR) +#define HW_CCM_ANALOG_PLL_AUDIO_RD() (HW_CCM_ANALOG_PLL_AUDIO.U) +#define HW_CCM_ANALOG_PLL_AUDIO_WR(v) (HW_CCM_ANALOG_PLL_AUDIO.U = (v)) +#define HW_CCM_ANALOG_PLL_AUDIO_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_AUDIO_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_AUDIO_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_AUDIO_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_AUDIO_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_AUDIO_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_AUDIO bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field DIV_SELECT[6:0] (RW) + * + * This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27~54. + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_DIV_SELECT (0) //!< Bit position for CCM_ANALOG_PLL_AUDIO_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_AUDIO_DIV_SELECT (0x0000007f) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_DIV_SELECT) >> BP_CCM_ANALOG_PLL_AUDIO_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_AUDIO_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_DIV_SELECT) & BM_CCM_ANALOG_PLL_AUDIO_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_AUDIO, DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field POWERDOWN[12] (RW) + * + * Powers down the PLL. + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_POWERDOWN (12) //!< Bit position for CCM_ANALOG_PLL_AUDIO_POWERDOWN. +#define BM_CCM_ANALOG_PLL_AUDIO_POWERDOWN (0x00001000) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_POWERDOWN. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_POWERDOWN from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_POWERDOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_POWERDOWN) >> BP_CCM_ANALOG_PLL_AUDIO_POWERDOWN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_POWERDOWN. +#define BF_CCM_ANALOG_PLL_AUDIO_POWERDOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_POWERDOWN) & BM_CCM_ANALOG_PLL_AUDIO_POWERDOWN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POWERDOWN field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_POWERDOWN(v) BF_CS1(CCM_ANALOG_PLL_AUDIO, POWERDOWN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field ENABLE[13] (RW) + * + * Enable PLL output + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_ENABLE (13) //!< Bit position for CCM_ANALOG_PLL_AUDIO_ENABLE. +#define BM_CCM_ANALOG_PLL_AUDIO_ENABLE (0x00002000) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_ENABLE. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_ENABLE from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_ENABLE) >> BP_CCM_ANALOG_PLL_AUDIO_ENABLE) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_ENABLE. +#define BF_CCM_ANALOG_PLL_AUDIO_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_ENABLE) & BM_CCM_ANALOG_PLL_AUDIO_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_ENABLE(v) BF_CS1(CCM_ANALOG_PLL_AUDIO, ENABLE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field BYPASS_CLK_SRC[15:14] (RW) + * + * Determines the bypass source. + * + * Values: + * - REF_CLK_24M = 0x0 - Select the 24MHz oscillator as source. + * - CLK1 = 0x1 - Select the CLK1_N / CLK1_P as source. + * - CLK2 = 0x2 - Select the CLK2_N / CLK2_P as source. + * - XOR = 0x3 - Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC (14) //!< Bit position for CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC. +#define BM_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC (0x0000c000) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC) >> BP_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC. +#define BF_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_CLK_SRC field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(v) BF_CS1(CCM_ANALOG_PLL_AUDIO, BYPASS_CLK_SRC, v) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_V(v) BF_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(BV_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC__##v) + +#define BV_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC__REF_CLK_24M (0x0) //!< Select the 24MHz oscillator as source. +#define BV_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC__CLK1 (0x1) //!< Select the CLK1_N / CLK1_P as source. +#define BV_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC__CLK2 (0x2) //!< Select the CLK2_N / CLK2_P as source. +#define BV_CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC__XOR (0x3) //!< Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. +//@} + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field BYPASS[16] (RW) + * + * Bypass the pll. + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_BYPASS (16) //!< Bit position for CCM_ANALOG_PLL_AUDIO_BYPASS. +#define BM_CCM_ANALOG_PLL_AUDIO_BYPASS (0x00010000) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_BYPASS. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_BYPASS from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_BYPASS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_BYPASS) >> BP_CCM_ANALOG_PLL_AUDIO_BYPASS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_BYPASS. +#define BF_CCM_ANALOG_PLL_AUDIO_BYPASS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_BYPASS) & BM_CCM_ANALOG_PLL_AUDIO_BYPASS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_BYPASS(v) BF_CS1(CCM_ANALOG_PLL_AUDIO, BYPASS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field PFD_OFFSET_EN[18] (RW) + * + * Enables an offset in the phase frequency detector. + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (18) //!< Bit position for CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN. +#define BM_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (0x00040000) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN) >> BP_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN. +#define BF_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN) & BM_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD_OFFSET_EN field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(v) BF_CS1(CCM_ANALOG_PLL_AUDIO, PFD_OFFSET_EN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field POST_DIV_SELECT[20:19] (RW) + * + * These bits implement a divider after the PLL, but before the enable and bypass mux. + * + * Values: + * - 00 - Divide by 4. + * - 01 - Divide by 2. + * - 10 - Divide by 1. + * - 11 - Reserved + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT (19) //!< Bit position for CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT (0x00180000) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT) >> BP_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT) & BM_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POST_DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_AUDIO, POST_DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field SSC_EN[21] (RW) + * + * Reserved Bit + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_SSC_EN (21) //!< Bit position for CCM_ANALOG_PLL_AUDIO_SSC_EN. +#define BM_CCM_ANALOG_PLL_AUDIO_SSC_EN (0x00200000) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_SSC_EN. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_SSC_EN from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_SSC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_SSC_EN) >> BP_CCM_ANALOG_PLL_AUDIO_SSC_EN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_SSC_EN. +#define BF_CCM_ANALOG_PLL_AUDIO_SSC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_SSC_EN) & BM_CCM_ANALOG_PLL_AUDIO_SSC_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSC_EN field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_SSC_EN(v) BF_CS1(CCM_ANALOG_PLL_AUDIO, SSC_EN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_AUDIO, field LOCK[31] (RO) + * + * 1 - PLL is currently locked. 0 - PLL is not currently locked. + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_LOCK (31) //!< Bit position for CCM_ANALOG_PLL_AUDIO_LOCK. +#define BM_CCM_ANALOG_PLL_AUDIO_LOCK (0x80000000) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_LOCK. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_LOCK from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_LOCK) >> BP_CCM_ANALOG_PLL_AUDIO_LOCK) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register (RW) + * + * Reset value: 0x05f5e100 + * + * This register contains the numerator (A) of Audio PLL fractional loop divider.(Signed number), + * absolute value should be less than denominator Absolute value should be less than denominator + */ +typedef union _hw_ccm_analog_pll_audio_num +{ + reg32_t U; + struct _hw_ccm_analog_pll_audio_num_bitfields + { + unsigned A : 30; //!< [29:0] 30 bit numerator of fractional loop divider. + unsigned RESERVED0 : 2; //!< [31:30] Always set to zero (0). + } B; +} hw_ccm_analog_pll_audio_num_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_AUDIO_NUM register + */ +//@{ +#define HW_CCM_ANALOG_PLL_AUDIO_NUM_ADDR (REGS_CCM_ANALOG_BASE + 0x80) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_AUDIO_NUM (*(volatile hw_ccm_analog_pll_audio_num_t *) HW_CCM_ANALOG_PLL_AUDIO_NUM_ADDR) +#define HW_CCM_ANALOG_PLL_AUDIO_NUM_RD() (HW_CCM_ANALOG_PLL_AUDIO_NUM.U) +#define HW_CCM_ANALOG_PLL_AUDIO_NUM_WR(v) (HW_CCM_ANALOG_PLL_AUDIO_NUM.U = (v)) +#define HW_CCM_ANALOG_PLL_AUDIO_NUM_SET(v) (HW_CCM_ANALOG_PLL_AUDIO_NUM_WR(HW_CCM_ANALOG_PLL_AUDIO_NUM_RD() | (v))) +#define HW_CCM_ANALOG_PLL_AUDIO_NUM_CLR(v) (HW_CCM_ANALOG_PLL_AUDIO_NUM_WR(HW_CCM_ANALOG_PLL_AUDIO_NUM_RD() & ~(v))) +#define HW_CCM_ANALOG_PLL_AUDIO_NUM_TOG(v) (HW_CCM_ANALOG_PLL_AUDIO_NUM_WR(HW_CCM_ANALOG_PLL_AUDIO_NUM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_AUDIO_NUM bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_AUDIO_NUM, field A[29:0] (RW) + * + * 30 bit numerator of fractional loop divider. + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_NUM_A (0) //!< Bit position for CCM_ANALOG_PLL_AUDIO_NUM_A. +#define BM_CCM_ANALOG_PLL_AUDIO_NUM_A (0x3fffffff) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_NUM_A. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_NUM_A from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_NUM_A(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_NUM_A) >> BP_CCM_ANALOG_PLL_AUDIO_NUM_A) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_NUM_A. +#define BF_CCM_ANALOG_PLL_AUDIO_NUM_A(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_NUM_A) & BM_CCM_ANALOG_PLL_AUDIO_NUM_A) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the A field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_NUM_A(v) (HW_CCM_ANALOG_PLL_AUDIO_NUM_WR((HW_CCM_ANALOG_PLL_AUDIO_NUM_RD() & ~BM_CCM_ANALOG_PLL_AUDIO_NUM_A) | BF_CCM_ANALOG_PLL_AUDIO_NUM_A(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register (RW) + * + * Reset value: 0x2964619c + * + * This register contains the Denominator (B) of Audio PLL fractional loop divider.(unsigned number) + */ +typedef union _hw_ccm_analog_pll_audio_denom +{ + reg32_t U; + struct _hw_ccm_analog_pll_audio_denom_bitfields + { + unsigned B : 30; //!< [29:0] 30 bit Denominator of fractional loop divider. + unsigned RESERVED0 : 2; //!< [31:30] Always set to zero (0). + } B; +} hw_ccm_analog_pll_audio_denom_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_AUDIO_DENOM register + */ +//@{ +#define HW_CCM_ANALOG_PLL_AUDIO_DENOM_ADDR (REGS_CCM_ANALOG_BASE + 0x90) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_AUDIO_DENOM (*(volatile hw_ccm_analog_pll_audio_denom_t *) HW_CCM_ANALOG_PLL_AUDIO_DENOM_ADDR) +#define HW_CCM_ANALOG_PLL_AUDIO_DENOM_RD() (HW_CCM_ANALOG_PLL_AUDIO_DENOM.U) +#define HW_CCM_ANALOG_PLL_AUDIO_DENOM_WR(v) (HW_CCM_ANALOG_PLL_AUDIO_DENOM.U = (v)) +#define HW_CCM_ANALOG_PLL_AUDIO_DENOM_SET(v) (HW_CCM_ANALOG_PLL_AUDIO_DENOM_WR(HW_CCM_ANALOG_PLL_AUDIO_DENOM_RD() | (v))) +#define HW_CCM_ANALOG_PLL_AUDIO_DENOM_CLR(v) (HW_CCM_ANALOG_PLL_AUDIO_DENOM_WR(HW_CCM_ANALOG_PLL_AUDIO_DENOM_RD() & ~(v))) +#define HW_CCM_ANALOG_PLL_AUDIO_DENOM_TOG(v) (HW_CCM_ANALOG_PLL_AUDIO_DENOM_WR(HW_CCM_ANALOG_PLL_AUDIO_DENOM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_AUDIO_DENOM bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_AUDIO_DENOM, field B[29:0] (RW) + * + * 30 bit Denominator of fractional loop divider. + */ +//@{ +#define BP_CCM_ANALOG_PLL_AUDIO_DENOM_B (0) //!< Bit position for CCM_ANALOG_PLL_AUDIO_DENOM_B. +#define BM_CCM_ANALOG_PLL_AUDIO_DENOM_B (0x3fffffff) //!< Bit mask for CCM_ANALOG_PLL_AUDIO_DENOM_B. + +//! @brief Get value of CCM_ANALOG_PLL_AUDIO_DENOM_B from a register value. +#define BG_CCM_ANALOG_PLL_AUDIO_DENOM_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_AUDIO_DENOM_B) >> BP_CCM_ANALOG_PLL_AUDIO_DENOM_B) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_AUDIO_DENOM_B. +#define BF_CCM_ANALOG_PLL_AUDIO_DENOM_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_AUDIO_DENOM_B) & BM_CCM_ANALOG_PLL_AUDIO_DENOM_B) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the B field to a new value. +#define BW_CCM_ANALOG_PLL_AUDIO_DENOM_B(v) (HW_CCM_ANALOG_PLL_AUDIO_DENOM_WR((HW_CCM_ANALOG_PLL_AUDIO_DENOM_RD() & ~BM_CCM_ANALOG_PLL_AUDIO_DENOM_B) | BF_CCM_ANALOG_PLL_AUDIO_DENOM_B(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_VIDEO - Analog Video PLL control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_VIDEO - Analog Video PLL control Register (RW) + * + * Reset value: 0x0001100c + * + * The control register provides control for the Video PLL. + */ +typedef union _hw_ccm_analog_pll_video +{ + reg32_t U; + struct _hw_ccm_analog_pll_video_bitfields + { + unsigned DIV_SELECT : 7; //!< [6:0] This field controls the pll loop divider. + unsigned RESERVED0 : 5; //!< [11:7] Reserved. + unsigned POWERDOWN : 1; //!< [12] Powers down the PLL. + unsigned ENABLE : 1; //!< [13] Enalbe PLL output + unsigned BYPASS_CLK_SRC : 2; //!< [15:14] Determines the bypass source. + unsigned BYPASS : 1; //!< [16] Bypass the pll. + unsigned RESERVED1 : 1; //!< [17] Reserved + unsigned PFD_OFFSET_EN : 1; //!< [18] Enables an offset in the phase frequency detector. + unsigned POST_DIV_SELECT : 2; //!< [20:19] These bits implement a divider after the PLL, but before the enable and bypass mux. + unsigned SSC_EN : 1; //!< [21] Revserved BIt + unsigned RESERVED2 : 9; //!< [30:22] Always set to zero (0). + unsigned LOCK : 1; //!< [31] 1 - PLL is currently locked; + } B; +} hw_ccm_analog_pll_video_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_VIDEO register + */ +//@{ +#define HW_CCM_ANALOG_PLL_VIDEO_ADDR (REGS_CCM_ANALOG_BASE + 0xa0) +#define HW_CCM_ANALOG_PLL_VIDEO_SET_ADDR (HW_CCM_ANALOG_PLL_VIDEO_ADDR + 0x4) +#define HW_CCM_ANALOG_PLL_VIDEO_CLR_ADDR (HW_CCM_ANALOG_PLL_VIDEO_ADDR + 0x8) +#define HW_CCM_ANALOG_PLL_VIDEO_TOG_ADDR (HW_CCM_ANALOG_PLL_VIDEO_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_VIDEO (*(volatile hw_ccm_analog_pll_video_t *) HW_CCM_ANALOG_PLL_VIDEO_ADDR) +#define HW_CCM_ANALOG_PLL_VIDEO_RD() (HW_CCM_ANALOG_PLL_VIDEO.U) +#define HW_CCM_ANALOG_PLL_VIDEO_WR(v) (HW_CCM_ANALOG_PLL_VIDEO.U = (v)) +#define HW_CCM_ANALOG_PLL_VIDEO_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_VIDEO_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_VIDEO_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_VIDEO_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_VIDEO_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_VIDEO_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_VIDEO bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field DIV_SELECT[6:0] (RW) + * + * This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27~54. + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_DIV_SELECT (0) //!< Bit position for CCM_ANALOG_PLL_VIDEO_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_VIDEO_DIV_SELECT (0x0000007f) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_DIV_SELECT) >> BP_CCM_ANALOG_PLL_VIDEO_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_VIDEO_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_DIV_SELECT) & BM_CCM_ANALOG_PLL_VIDEO_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_VIDEO, DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field POWERDOWN[12] (RW) + * + * Powers down the PLL. + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_POWERDOWN (12) //!< Bit position for CCM_ANALOG_PLL_VIDEO_POWERDOWN. +#define BM_CCM_ANALOG_PLL_VIDEO_POWERDOWN (0x00001000) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_POWERDOWN. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_POWERDOWN from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_POWERDOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_POWERDOWN) >> BP_CCM_ANALOG_PLL_VIDEO_POWERDOWN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_POWERDOWN. +#define BF_CCM_ANALOG_PLL_VIDEO_POWERDOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_POWERDOWN) & BM_CCM_ANALOG_PLL_VIDEO_POWERDOWN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POWERDOWN field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_POWERDOWN(v) BF_CS1(CCM_ANALOG_PLL_VIDEO, POWERDOWN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field ENABLE[13] (RW) + * + * Enalbe PLL output + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_ENABLE (13) //!< Bit position for CCM_ANALOG_PLL_VIDEO_ENABLE. +#define BM_CCM_ANALOG_PLL_VIDEO_ENABLE (0x00002000) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_ENABLE. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_ENABLE from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_ENABLE) >> BP_CCM_ANALOG_PLL_VIDEO_ENABLE) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_ENABLE. +#define BF_CCM_ANALOG_PLL_VIDEO_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_ENABLE) & BM_CCM_ANALOG_PLL_VIDEO_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_ENABLE(v) BF_CS1(CCM_ANALOG_PLL_VIDEO, ENABLE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field BYPASS_CLK_SRC[15:14] (RW) + * + * Determines the bypass source. + * + * Values: + * - REF_CLK_24M = 0x0 - Select the 24MHz oscillator as source. + * - CLK1 = 0x1 - Select the CLK1_N / CLK1_P as source. + * - CLK2 = 0x2 - Select the CLK2_N / CLK2_P as source. + * - XOR = 0x3 - Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC (14) //!< Bit position for CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC. +#define BM_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC (0x0000c000) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC) >> BP_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC. +#define BF_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_CLK_SRC field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(v) BF_CS1(CCM_ANALOG_PLL_VIDEO, BYPASS_CLK_SRC, v) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_V(v) BF_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(BV_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC__##v) + +#define BV_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC__REF_CLK_24M (0x0) //!< Select the 24MHz oscillator as source. +#define BV_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC__CLK1 (0x1) //!< Select the CLK1_N / CLK1_P as source. +#define BV_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC__CLK2 (0x2) //!< Select the CLK2_N / CLK2_P as source. +#define BV_CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC__XOR (0x3) //!< Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. +//@} + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field BYPASS[16] (RW) + * + * Bypass the pll. + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_BYPASS (16) //!< Bit position for CCM_ANALOG_PLL_VIDEO_BYPASS. +#define BM_CCM_ANALOG_PLL_VIDEO_BYPASS (0x00010000) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_BYPASS. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_BYPASS from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_BYPASS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_BYPASS) >> BP_CCM_ANALOG_PLL_VIDEO_BYPASS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_BYPASS. +#define BF_CCM_ANALOG_PLL_VIDEO_BYPASS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_BYPASS) & BM_CCM_ANALOG_PLL_VIDEO_BYPASS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_BYPASS(v) BF_CS1(CCM_ANALOG_PLL_VIDEO, BYPASS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field PFD_OFFSET_EN[18] (RW) + * + * Enables an offset in the phase frequency detector. + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (18) //!< Bit position for CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN. +#define BM_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (0x00040000) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN) >> BP_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN. +#define BF_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN) & BM_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD_OFFSET_EN field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(v) BF_CS1(CCM_ANALOG_PLL_VIDEO, PFD_OFFSET_EN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field POST_DIV_SELECT[20:19] (RW) + * + * These bits implement a divider after the PLL, but before the enable and bypass mux. + * + * Values: + * - 00 - Divide by 4. + * - 01 - Divide by 2. + * - 10 - Divide by 1. + * - 11 - Reserved + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT (19) //!< Bit position for CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT (0x00180000) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT) >> BP_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT) & BM_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POST_DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_VIDEO, POST_DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field SSC_EN[21] (RW) + * + * Revserved BIt + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_SSC_EN (21) //!< Bit position for CCM_ANALOG_PLL_VIDEO_SSC_EN. +#define BM_CCM_ANALOG_PLL_VIDEO_SSC_EN (0x00200000) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_SSC_EN. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_SSC_EN from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_SSC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_SSC_EN) >> BP_CCM_ANALOG_PLL_VIDEO_SSC_EN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_SSC_EN. +#define BF_CCM_ANALOG_PLL_VIDEO_SSC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_SSC_EN) & BM_CCM_ANALOG_PLL_VIDEO_SSC_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SSC_EN field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_SSC_EN(v) BF_CS1(CCM_ANALOG_PLL_VIDEO, SSC_EN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_VIDEO, field LOCK[31] (RO) + * + * 1 - PLL is currently locked; 0 - PLL is not currently locked. + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_LOCK (31) //!< Bit position for CCM_ANALOG_PLL_VIDEO_LOCK. +#define BM_CCM_ANALOG_PLL_VIDEO_LOCK (0x80000000) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_LOCK. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_LOCK from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_LOCK) >> BP_CCM_ANALOG_PLL_VIDEO_LOCK) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register (RW) + * + * Reset value: 0x05f5e100 + * + * This register contains the numerator (A) of Video PLL fractional loop divider.(Signed number) + * Absolute value should be less than denominator + */ +typedef union _hw_ccm_analog_pll_video_num +{ + reg32_t U; + struct _hw_ccm_analog_pll_video_num_bitfields + { + unsigned A : 30; //!< [29:0] 30 bit numerator of fractional loop divider(Signed number), absolute value should be less than denominator + unsigned RESERVED0 : 2; //!< [31:30] Always set to zero (0). + } B; +} hw_ccm_analog_pll_video_num_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_VIDEO_NUM register + */ +//@{ +#define HW_CCM_ANALOG_PLL_VIDEO_NUM_ADDR (REGS_CCM_ANALOG_BASE + 0xb0) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_VIDEO_NUM (*(volatile hw_ccm_analog_pll_video_num_t *) HW_CCM_ANALOG_PLL_VIDEO_NUM_ADDR) +#define HW_CCM_ANALOG_PLL_VIDEO_NUM_RD() (HW_CCM_ANALOG_PLL_VIDEO_NUM.U) +#define HW_CCM_ANALOG_PLL_VIDEO_NUM_WR(v) (HW_CCM_ANALOG_PLL_VIDEO_NUM.U = (v)) +#define HW_CCM_ANALOG_PLL_VIDEO_NUM_SET(v) (HW_CCM_ANALOG_PLL_VIDEO_NUM_WR(HW_CCM_ANALOG_PLL_VIDEO_NUM_RD() | (v))) +#define HW_CCM_ANALOG_PLL_VIDEO_NUM_CLR(v) (HW_CCM_ANALOG_PLL_VIDEO_NUM_WR(HW_CCM_ANALOG_PLL_VIDEO_NUM_RD() & ~(v))) +#define HW_CCM_ANALOG_PLL_VIDEO_NUM_TOG(v) (HW_CCM_ANALOG_PLL_VIDEO_NUM_WR(HW_CCM_ANALOG_PLL_VIDEO_NUM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_VIDEO_NUM bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_VIDEO_NUM, field A[29:0] (RW) + * + * 30 bit numerator of fractional loop divider(Signed number), absolute value should be less than + * denominator + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_NUM_A (0) //!< Bit position for CCM_ANALOG_PLL_VIDEO_NUM_A. +#define BM_CCM_ANALOG_PLL_VIDEO_NUM_A (0x3fffffff) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_NUM_A. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_NUM_A from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_NUM_A(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_NUM_A) >> BP_CCM_ANALOG_PLL_VIDEO_NUM_A) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_NUM_A. +#define BF_CCM_ANALOG_PLL_VIDEO_NUM_A(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_NUM_A) & BM_CCM_ANALOG_PLL_VIDEO_NUM_A) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the A field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_NUM_A(v) (HW_CCM_ANALOG_PLL_VIDEO_NUM_WR((HW_CCM_ANALOG_PLL_VIDEO_NUM_RD() & ~BM_CCM_ANALOG_PLL_VIDEO_NUM_A) | BF_CCM_ANALOG_PLL_VIDEO_NUM_A(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register (RW) + * + * Reset value: 0x10a24447 + * + * This register contains the Denominator (B) of Video PLL fractional loop divider.(Unsigned number) + */ +typedef union _hw_ccm_analog_pll_video_denom +{ + reg32_t U; + struct _hw_ccm_analog_pll_video_denom_bitfields + { + unsigned B : 30; //!< [29:0] 30 bit Denominator of fractional loop divider. + unsigned RESERVED0 : 2; //!< [31:30] Always set to zero (0). + } B; +} hw_ccm_analog_pll_video_denom_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_VIDEO_DENOM register + */ +//@{ +#define HW_CCM_ANALOG_PLL_VIDEO_DENOM_ADDR (REGS_CCM_ANALOG_BASE + 0xc0) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_VIDEO_DENOM (*(volatile hw_ccm_analog_pll_video_denom_t *) HW_CCM_ANALOG_PLL_VIDEO_DENOM_ADDR) +#define HW_CCM_ANALOG_PLL_VIDEO_DENOM_RD() (HW_CCM_ANALOG_PLL_VIDEO_DENOM.U) +#define HW_CCM_ANALOG_PLL_VIDEO_DENOM_WR(v) (HW_CCM_ANALOG_PLL_VIDEO_DENOM.U = (v)) +#define HW_CCM_ANALOG_PLL_VIDEO_DENOM_SET(v) (HW_CCM_ANALOG_PLL_VIDEO_DENOM_WR(HW_CCM_ANALOG_PLL_VIDEO_DENOM_RD() | (v))) +#define HW_CCM_ANALOG_PLL_VIDEO_DENOM_CLR(v) (HW_CCM_ANALOG_PLL_VIDEO_DENOM_WR(HW_CCM_ANALOG_PLL_VIDEO_DENOM_RD() & ~(v))) +#define HW_CCM_ANALOG_PLL_VIDEO_DENOM_TOG(v) (HW_CCM_ANALOG_PLL_VIDEO_DENOM_WR(HW_CCM_ANALOG_PLL_VIDEO_DENOM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_VIDEO_DENOM bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_VIDEO_DENOM, field B[29:0] (RW) + * + * 30 bit Denominator of fractional loop divider. + */ +//@{ +#define BP_CCM_ANALOG_PLL_VIDEO_DENOM_B (0) //!< Bit position for CCM_ANALOG_PLL_VIDEO_DENOM_B. +#define BM_CCM_ANALOG_PLL_VIDEO_DENOM_B (0x3fffffff) //!< Bit mask for CCM_ANALOG_PLL_VIDEO_DENOM_B. + +//! @brief Get value of CCM_ANALOG_PLL_VIDEO_DENOM_B from a register value. +#define BG_CCM_ANALOG_PLL_VIDEO_DENOM_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_VIDEO_DENOM_B) >> BP_CCM_ANALOG_PLL_VIDEO_DENOM_B) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_VIDEO_DENOM_B. +#define BF_CCM_ANALOG_PLL_VIDEO_DENOM_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_VIDEO_DENOM_B) & BM_CCM_ANALOG_PLL_VIDEO_DENOM_B) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the B field to a new value. +#define BW_CCM_ANALOG_PLL_VIDEO_DENOM_B(v) (HW_CCM_ANALOG_PLL_VIDEO_DENOM_WR((HW_CCM_ANALOG_PLL_VIDEO_DENOM_RD() & ~BM_CCM_ANALOG_PLL_VIDEO_DENOM_B) | BF_CCM_ANALOG_PLL_VIDEO_DENOM_B(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_MLB - MLB PLL Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_MLB - MLB PLL Control Register (RW) + * + * Reset value: 0x00010000 + * + * This register defines the control bits for the MLB PLL. + */ +typedef union _hw_ccm_analog_pll_mlb +{ + reg32_t U; + struct _hw_ccm_analog_pll_mlb_bitfields + { + unsigned RESERVED0 : 11; //!< [10:0] Reserved. + unsigned HOLD_RING_OFF : 1; //!< [11] Analog debug bit. + unsigned PHASE_SEL : 2; //!< [13:12] Analog debut bit. + unsigned RESERVED1 : 2; //!< [15:14] Reserved. + unsigned BYPASS : 1; //!< [16] Bypass the PLL. + unsigned VDDA_DELAY_CFG : 3; //!< [19:17] Configure the phase delay of the MLB PLL by adjusting the delay line in Vddio power domain. + unsigned VDDD_DELAY_CFG : 3; //!< [22:20] Configure the phase delay of the MLB PLL by adjusting the delay line in core Vdd poser domain. + unsigned RX_CLK_DELAY_CFG : 3; //!< [25:23] Configure the phase delay of the MLB PLL RX Clock. + unsigned MLB_FLT_RES_CFG : 3; //!< [28:26] Configure the filter resistor for different divider ratio of MLB PLL. + unsigned RESERVED2 : 2; //!< [30:29] Reserved. + unsigned LOCK : 1; //!< [31] Lock bit + } B; +} hw_ccm_analog_pll_mlb_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_MLB register + */ +//@{ +#define HW_CCM_ANALOG_PLL_MLB_ADDR (REGS_CCM_ANALOG_BASE + 0xd0) +#define HW_CCM_ANALOG_PLL_MLB_SET_ADDR (HW_CCM_ANALOG_PLL_MLB_ADDR + 0x4) +#define HW_CCM_ANALOG_PLL_MLB_CLR_ADDR (HW_CCM_ANALOG_PLL_MLB_ADDR + 0x8) +#define HW_CCM_ANALOG_PLL_MLB_TOG_ADDR (HW_CCM_ANALOG_PLL_MLB_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_MLB (*(volatile hw_ccm_analog_pll_mlb_t *) HW_CCM_ANALOG_PLL_MLB_ADDR) +#define HW_CCM_ANALOG_PLL_MLB_RD() (HW_CCM_ANALOG_PLL_MLB.U) +#define HW_CCM_ANALOG_PLL_MLB_WR(v) (HW_CCM_ANALOG_PLL_MLB.U = (v)) +#define HW_CCM_ANALOG_PLL_MLB_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_MLB_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_MLB_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_MLB_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_MLB_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_MLB_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_MLB bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_MLB, field HOLD_RING_OFF[11] (RW) + * + * Analog debug bit. + */ +//@{ +#define BP_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF (11) //!< Bit position for CCM_ANALOG_PLL_MLB_HOLD_RING_OFF. +#define BM_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF (0x00000800) //!< Bit mask for CCM_ANALOG_PLL_MLB_HOLD_RING_OFF. + +//! @brief Get value of CCM_ANALOG_PLL_MLB_HOLD_RING_OFF from a register value. +#define BG_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF) >> BP_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_MLB_HOLD_RING_OFF. +#define BF_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF) & BM_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HOLD_RING_OFF field to a new value. +#define BW_CCM_ANALOG_PLL_MLB_HOLD_RING_OFF(v) BF_CS1(CCM_ANALOG_PLL_MLB, HOLD_RING_OFF, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_MLB, field PHASE_SEL[13:12] (RW) + * + * Analog debut bit. + */ +//@{ +#define BP_CCM_ANALOG_PLL_MLB_PHASE_SEL (12) //!< Bit position for CCM_ANALOG_PLL_MLB_PHASE_SEL. +#define BM_CCM_ANALOG_PLL_MLB_PHASE_SEL (0x00003000) //!< Bit mask for CCM_ANALOG_PLL_MLB_PHASE_SEL. + +//! @brief Get value of CCM_ANALOG_PLL_MLB_PHASE_SEL from a register value. +#define BG_CCM_ANALOG_PLL_MLB_PHASE_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_MLB_PHASE_SEL) >> BP_CCM_ANALOG_PLL_MLB_PHASE_SEL) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_MLB_PHASE_SEL. +#define BF_CCM_ANALOG_PLL_MLB_PHASE_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_MLB_PHASE_SEL) & BM_CCM_ANALOG_PLL_MLB_PHASE_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PHASE_SEL field to a new value. +#define BW_CCM_ANALOG_PLL_MLB_PHASE_SEL(v) BF_CS1(CCM_ANALOG_PLL_MLB, PHASE_SEL, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_MLB, field BYPASS[16] (RW) + * + * Bypass the PLL. + */ +//@{ +#define BP_CCM_ANALOG_PLL_MLB_BYPASS (16) //!< Bit position for CCM_ANALOG_PLL_MLB_BYPASS. +#define BM_CCM_ANALOG_PLL_MLB_BYPASS (0x00010000) //!< Bit mask for CCM_ANALOG_PLL_MLB_BYPASS. + +//! @brief Get value of CCM_ANALOG_PLL_MLB_BYPASS from a register value. +#define BG_CCM_ANALOG_PLL_MLB_BYPASS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_MLB_BYPASS) >> BP_CCM_ANALOG_PLL_MLB_BYPASS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_MLB_BYPASS. +#define BF_CCM_ANALOG_PLL_MLB_BYPASS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_MLB_BYPASS) & BM_CCM_ANALOG_PLL_MLB_BYPASS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS field to a new value. +#define BW_CCM_ANALOG_PLL_MLB_BYPASS(v) BF_CS1(CCM_ANALOG_PLL_MLB, BYPASS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_MLB, field VDDA_DELAY_CFG[19:17] (RW) + * + * Configure the phase delay of the MLB PLL by adjusting the delay line in Vddio power domain. + */ +//@{ +#define BP_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG (17) //!< Bit position for CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG. +#define BM_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG (0x000e0000) //!< Bit mask for CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG. + +//! @brief Get value of CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG from a register value. +#define BG_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG) >> BP_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG. +#define BF_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG) & BM_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VDDA_DELAY_CFG field to a new value. +#define BW_CCM_ANALOG_PLL_MLB_VDDA_DELAY_CFG(v) BF_CS1(CCM_ANALOG_PLL_MLB, VDDA_DELAY_CFG, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_MLB, field VDDD_DELAY_CFG[22:20] (RW) + * + * Configure the phase delay of the MLB PLL by adjusting the delay line in core Vdd poser domain. + */ +//@{ +#define BP_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG (20) //!< Bit position for CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG. +#define BM_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG (0x00700000) //!< Bit mask for CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG. + +//! @brief Get value of CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG from a register value. +#define BG_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG) >> BP_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG. +#define BF_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG) & BM_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VDDD_DELAY_CFG field to a new value. +#define BW_CCM_ANALOG_PLL_MLB_VDDD_DELAY_CFG(v) BF_CS1(CCM_ANALOG_PLL_MLB, VDDD_DELAY_CFG, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_MLB, field RX_CLK_DELAY_CFG[25:23] (RW) + * + * Configure the phase delay of the MLB PLL RX Clock. + */ +//@{ +#define BP_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG (23) //!< Bit position for CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG. +#define BM_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG (0x03800000) //!< Bit mask for CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG. + +//! @brief Get value of CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG from a register value. +#define BG_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG) >> BP_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG. +#define BF_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG) & BM_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RX_CLK_DELAY_CFG field to a new value. +#define BW_CCM_ANALOG_PLL_MLB_RX_CLK_DELAY_CFG(v) BF_CS1(CCM_ANALOG_PLL_MLB, RX_CLK_DELAY_CFG, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_MLB, field MLB_FLT_RES_CFG[28:26] (RW) + * + * Configure the filter resistor for different divider ratio of MLB PLL. + */ +//@{ +#define BP_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG (26) //!< Bit position for CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG. +#define BM_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG (0x1c000000) //!< Bit mask for CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG. + +//! @brief Get value of CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG from a register value. +#define BG_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG) >> BP_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG. +#define BF_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG) & BM_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MLB_FLT_RES_CFG field to a new value. +#define BW_CCM_ANALOG_PLL_MLB_MLB_FLT_RES_CFG(v) BF_CS1(CCM_ANALOG_PLL_MLB, MLB_FLT_RES_CFG, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_MLB, field LOCK[31] (RO) + * + * Lock bit + * + * Values: + * - 0 - PLL is not currently locked + * - 1 - PLL is currently locked. + */ +//@{ +#define BP_CCM_ANALOG_PLL_MLB_LOCK (31) //!< Bit position for CCM_ANALOG_PLL_MLB_LOCK. +#define BM_CCM_ANALOG_PLL_MLB_LOCK (0x80000000) //!< Bit mask for CCM_ANALOG_PLL_MLB_LOCK. + +//! @brief Get value of CCM_ANALOG_PLL_MLB_LOCK from a register value. +#define BG_CCM_ANALOG_PLL_MLB_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_MLB_LOCK) >> BP_CCM_ANALOG_PLL_MLB_LOCK) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PLL_ENET - Analog ENET PLL Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PLL_ENET - Analog ENET PLL Control Register (RW) + * + * Reset value: 0x00011001 + * + * The control register provides control for the ENET PLL. + */ +typedef union _hw_ccm_analog_pll_enet +{ + reg32_t U; + struct _hw_ccm_analog_pll_enet_bitfields + { + unsigned DIV_SELECT : 2; //!< [1:0] Controls the frequency of the ethernet reference clock.00 - 25MHz; 01 - 50MHz; 10 - 100MHz (not 50% duty cycle); 11 - 125MHz; + unsigned RESERVED0 : 10; //!< [11:2] Reserved. + unsigned POWERDOWN : 1; //!< [12] Powers down the PLL. + unsigned ENABLE : 1; //!< [13] Enable the ethernet clock output. + unsigned BYPASS_CLK_SRC : 2; //!< [15:14] Determines the bypass source. + unsigned BYPASS : 1; //!< [16] Bypass the pll. + unsigned RESERVED1 : 1; //!< [17] Reserved + unsigned PFD_OFFSET_EN : 1; //!< [18] Enables an offset in the phase frequency detector. + unsigned ENABLE_125M : 1; //!< [19] Enables an offset in the phase frequency detector. + unsigned ENABLE_100M : 1; //!< [20] Enables an offset in the phase frequency detector. + unsigned RESERVED2 : 10; //!< [30:21] Always set to zero (0). + unsigned LOCK : 1; //!< [31] 1 - PLL is currently locked; 0 - PLL is not currently locked. + } B; +} hw_ccm_analog_pll_enet_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PLL_ENET register + */ +//@{ +#define HW_CCM_ANALOG_PLL_ENET_ADDR (REGS_CCM_ANALOG_BASE + 0xe0) +#define HW_CCM_ANALOG_PLL_ENET_SET_ADDR (HW_CCM_ANALOG_PLL_ENET_ADDR + 0x4) +#define HW_CCM_ANALOG_PLL_ENET_CLR_ADDR (HW_CCM_ANALOG_PLL_ENET_ADDR + 0x8) +#define HW_CCM_ANALOG_PLL_ENET_TOG_ADDR (HW_CCM_ANALOG_PLL_ENET_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PLL_ENET (*(volatile hw_ccm_analog_pll_enet_t *) HW_CCM_ANALOG_PLL_ENET_ADDR) +#define HW_CCM_ANALOG_PLL_ENET_RD() (HW_CCM_ANALOG_PLL_ENET.U) +#define HW_CCM_ANALOG_PLL_ENET_WR(v) (HW_CCM_ANALOG_PLL_ENET.U = (v)) +#define HW_CCM_ANALOG_PLL_ENET_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_ENET_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_ENET_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_ENET_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PLL_ENET_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PLL_ENET_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PLL_ENET bitfields + */ + +/*! @name Register CCM_ANALOG_PLL_ENET, field DIV_SELECT[1:0] (RW) + * + * Controls the frequency of the ethernet reference clock.00 - 25MHz; 01 - 50MHz; 10 - 100MHz (not + * 50% duty cycle); 11 - 125MHz; + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_DIV_SELECT (0) //!< Bit position for CCM_ANALOG_PLL_ENET_DIV_SELECT. +#define BM_CCM_ANALOG_PLL_ENET_DIV_SELECT (0x00000003) //!< Bit mask for CCM_ANALOG_PLL_ENET_DIV_SELECT. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_DIV_SELECT from a register value. +#define BG_CCM_ANALOG_PLL_ENET_DIV_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_DIV_SELECT) >> BP_CCM_ANALOG_PLL_ENET_DIV_SELECT) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ENET_DIV_SELECT. +#define BF_CCM_ANALOG_PLL_ENET_DIV_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ENET_DIV_SELECT) & BM_CCM_ANALOG_PLL_ENET_DIV_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIV_SELECT field to a new value. +#define BW_CCM_ANALOG_PLL_ENET_DIV_SELECT(v) BF_CS1(CCM_ANALOG_PLL_ENET, DIV_SELECT, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ENET, field POWERDOWN[12] (RW) + * + * Powers down the PLL. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_POWERDOWN (12) //!< Bit position for CCM_ANALOG_PLL_ENET_POWERDOWN. +#define BM_CCM_ANALOG_PLL_ENET_POWERDOWN (0x00001000) //!< Bit mask for CCM_ANALOG_PLL_ENET_POWERDOWN. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_POWERDOWN from a register value. +#define BG_CCM_ANALOG_PLL_ENET_POWERDOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_POWERDOWN) >> BP_CCM_ANALOG_PLL_ENET_POWERDOWN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ENET_POWERDOWN. +#define BF_CCM_ANALOG_PLL_ENET_POWERDOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ENET_POWERDOWN) & BM_CCM_ANALOG_PLL_ENET_POWERDOWN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POWERDOWN field to a new value. +#define BW_CCM_ANALOG_PLL_ENET_POWERDOWN(v) BF_CS1(CCM_ANALOG_PLL_ENET, POWERDOWN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ENET, field ENABLE[13] (RW) + * + * Enable the ethernet clock output. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_ENABLE (13) //!< Bit position for CCM_ANALOG_PLL_ENET_ENABLE. +#define BM_CCM_ANALOG_PLL_ENET_ENABLE (0x00002000) //!< Bit mask for CCM_ANALOG_PLL_ENET_ENABLE. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_ENABLE from a register value. +#define BG_CCM_ANALOG_PLL_ENET_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_ENABLE) >> BP_CCM_ANALOG_PLL_ENET_ENABLE) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ENET_ENABLE. +#define BF_CCM_ANALOG_PLL_ENET_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ENET_ENABLE) & BM_CCM_ANALOG_PLL_ENET_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE field to a new value. +#define BW_CCM_ANALOG_PLL_ENET_ENABLE(v) BF_CS1(CCM_ANALOG_PLL_ENET, ENABLE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ENET, field BYPASS_CLK_SRC[15:14] (RW) + * + * Determines the bypass source. + * + * Values: + * - REF_CLK_24M = 0x0 - Select the 24MHz oscillator as source. + * - CLK1 = 0x1 - Select the CLK1_N / CLK1_P as source. + * - CLK2 = 0x2 - Select the CLK2_N / CLK2_P as source. + * - XOR = 0x3 - Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC (14) //!< Bit position for CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC. +#define BM_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC (0x0000c000) //!< Bit mask for CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC from a register value. +#define BG_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC) >> BP_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC. +#define BF_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC) & BM_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS_CLK_SRC field to a new value. +#define BW_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(v) BF_CS1(CCM_ANALOG_PLL_ENET, BYPASS_CLK_SRC, v) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_V(v) BF_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(BV_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC__##v) + +#define BV_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC__REF_CLK_24M (0x0) //!< Select the 24MHz oscillator as source. +#define BV_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC__CLK1 (0x1) //!< Select the CLK1_N / CLK1_P as source. +#define BV_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC__CLK2 (0x2) //!< Select the CLK2_N / CLK2_P as source. +#define BV_CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC__XOR (0x3) //!< Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source. +//@} + +/*! @name Register CCM_ANALOG_PLL_ENET, field BYPASS[16] (RW) + * + * Bypass the pll. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_BYPASS (16) //!< Bit position for CCM_ANALOG_PLL_ENET_BYPASS. +#define BM_CCM_ANALOG_PLL_ENET_BYPASS (0x00010000) //!< Bit mask for CCM_ANALOG_PLL_ENET_BYPASS. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_BYPASS from a register value. +#define BG_CCM_ANALOG_PLL_ENET_BYPASS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_BYPASS) >> BP_CCM_ANALOG_PLL_ENET_BYPASS) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ENET_BYPASS. +#define BF_CCM_ANALOG_PLL_ENET_BYPASS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ENET_BYPASS) & BM_CCM_ANALOG_PLL_ENET_BYPASS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BYPASS field to a new value. +#define BW_CCM_ANALOG_PLL_ENET_BYPASS(v) BF_CS1(CCM_ANALOG_PLL_ENET, BYPASS, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ENET, field PFD_OFFSET_EN[18] (RW) + * + * Enables an offset in the phase frequency detector. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (18) //!< Bit position for CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN. +#define BM_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (0x00040000) //!< Bit mask for CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN from a register value. +#define BG_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN) >> BP_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN. +#define BF_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN) & BM_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD_OFFSET_EN field to a new value. +#define BW_CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(v) BF_CS1(CCM_ANALOG_PLL_ENET, PFD_OFFSET_EN, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ENET, field ENABLE_125M[19] (RW) + * + * Enables an offset in the phase frequency detector. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_ENABLE_125M (19) //!< Bit position for CCM_ANALOG_PLL_ENET_ENABLE_125M. +#define BM_CCM_ANALOG_PLL_ENET_ENABLE_125M (0x00080000) //!< Bit mask for CCM_ANALOG_PLL_ENET_ENABLE_125M. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_ENABLE_125M from a register value. +#define BG_CCM_ANALOG_PLL_ENET_ENABLE_125M(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_ENABLE_125M) >> BP_CCM_ANALOG_PLL_ENET_ENABLE_125M) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ENET_ENABLE_125M. +#define BF_CCM_ANALOG_PLL_ENET_ENABLE_125M(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ENET_ENABLE_125M) & BM_CCM_ANALOG_PLL_ENET_ENABLE_125M) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE_125M field to a new value. +#define BW_CCM_ANALOG_PLL_ENET_ENABLE_125M(v) BF_CS1(CCM_ANALOG_PLL_ENET, ENABLE_125M, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ENET, field ENABLE_100M[20] (RW) + * + * Enables an offset in the phase frequency detector. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_ENABLE_100M (20) //!< Bit position for CCM_ANALOG_PLL_ENET_ENABLE_100M. +#define BM_CCM_ANALOG_PLL_ENET_ENABLE_100M (0x00100000) //!< Bit mask for CCM_ANALOG_PLL_ENET_ENABLE_100M. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_ENABLE_100M from a register value. +#define BG_CCM_ANALOG_PLL_ENET_ENABLE_100M(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_ENABLE_100M) >> BP_CCM_ANALOG_PLL_ENET_ENABLE_100M) + +//! @brief Format value for bitfield CCM_ANALOG_PLL_ENET_ENABLE_100M. +#define BF_CCM_ANALOG_PLL_ENET_ENABLE_100M(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PLL_ENET_ENABLE_100M) & BM_CCM_ANALOG_PLL_ENET_ENABLE_100M) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENABLE_100M field to a new value. +#define BW_CCM_ANALOG_PLL_ENET_ENABLE_100M(v) BF_CS1(CCM_ANALOG_PLL_ENET, ENABLE_100M, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PLL_ENET, field LOCK[31] (RO) + * + * 1 - PLL is currently locked; 0 - PLL is not currently locked. + */ +//@{ +#define BP_CCM_ANALOG_PLL_ENET_LOCK (31) //!< Bit position for CCM_ANALOG_PLL_ENET_LOCK. +#define BM_CCM_ANALOG_PLL_ENET_LOCK (0x80000000) //!< Bit mask for CCM_ANALOG_PLL_ENET_LOCK. + +//! @brief Get value of CCM_ANALOG_PLL_ENET_LOCK from a register value. +#define BG_CCM_ANALOG_PLL_ENET_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PLL_ENET_LOCK) >> BP_CCM_ANALOG_PLL_ENET_LOCK) +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PFD_480 - 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PFD_480 - 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register (RW) + * + * Reset value: 0x1311100c + * + * The PFD_480 control register provides control for PFD clock generation. This register controls + * the 4-phase fractional clock dividers. The fractional clock frequencies are a product of the + * values in these registers. + */ +typedef union _hw_ccm_analog_pfd_480 +{ + reg32_t U; + struct _hw_ccm_analog_pfd_480_bitfields + { + unsigned PFD0_FRAC : 6; //!< [5:0] This field controls the fractional divide value. + unsigned PFD0_STABLE : 1; //!< [6] This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. + unsigned PFD0_CLKGATE : 1; //!< [7] If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings). + unsigned PFD1_FRAC : 6; //!< [13:8] This field controls the fractional divide value. + unsigned PFD1_STABLE : 1; //!< [14] This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. + unsigned PFD1_CLKGATE : 1; //!< [15] IO Clock Gate. + unsigned PFD2_FRAC : 6; //!< [21:16] This field controls the fractional divide value. + unsigned PFD2_STABLE : 1; //!< [22] This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. + unsigned PFD2_CLKGATE : 1; //!< [23] IO Clock Gate. + unsigned PFD3_FRAC : 6; //!< [29:24] This field controls the fractional divide value. + unsigned PFD3_STABLE : 1; //!< [30] This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. + unsigned PFD3_CLKGATE : 1; //!< [31] IO Clock Gate. + } B; +} hw_ccm_analog_pfd_480_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PFD_480 register + */ +//@{ +#define HW_CCM_ANALOG_PFD_480_ADDR (REGS_CCM_ANALOG_BASE + 0xf0) +#define HW_CCM_ANALOG_PFD_480_SET_ADDR (HW_CCM_ANALOG_PFD_480_ADDR + 0x4) +#define HW_CCM_ANALOG_PFD_480_CLR_ADDR (HW_CCM_ANALOG_PFD_480_ADDR + 0x8) +#define HW_CCM_ANALOG_PFD_480_TOG_ADDR (HW_CCM_ANALOG_PFD_480_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PFD_480 (*(volatile hw_ccm_analog_pfd_480_t *) HW_CCM_ANALOG_PFD_480_ADDR) +#define HW_CCM_ANALOG_PFD_480_RD() (HW_CCM_ANALOG_PFD_480.U) +#define HW_CCM_ANALOG_PFD_480_WR(v) (HW_CCM_ANALOG_PFD_480.U = (v)) +#define HW_CCM_ANALOG_PFD_480_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PFD_480_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PFD_480_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PFD_480_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PFD_480_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PFD_480_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PFD_480 bitfields + */ + +/*! @name Register CCM_ANALOG_PFD_480, field PFD0_FRAC[5:0] (RW) + * + * This field controls the fractional divide value. The resulting frequency shall be + * 480*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35. + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD0_FRAC (0) //!< Bit position for CCM_ANALOG_PFD_480_PFD0_FRAC. +#define BM_CCM_ANALOG_PFD_480_PFD0_FRAC (0x0000003f) //!< Bit mask for CCM_ANALOG_PFD_480_PFD0_FRAC. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD0_FRAC from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD0_FRAC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD0_FRAC) >> BP_CCM_ANALOG_PFD_480_PFD0_FRAC) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_480_PFD0_FRAC. +#define BF_CCM_ANALOG_PFD_480_PFD0_FRAC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_480_PFD0_FRAC) & BM_CCM_ANALOG_PFD_480_PFD0_FRAC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD0_FRAC field to a new value. +#define BW_CCM_ANALOG_PFD_480_PFD0_FRAC(v) BF_CS1(CCM_ANALOG_PFD_480, PFD0_FRAC, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD0_STABLE[6] (RO) + * + * This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should + * become stable quickly enough that this field will never need to be used by either device driver + * or application code. The value inverts when the new programmed fractional divide value has taken + * effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock + * output is stable. Note that the value will not invert when the fractional divider is taken out of + * or placed into clock-gated state. + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD0_STABLE (6) //!< Bit position for CCM_ANALOG_PFD_480_PFD0_STABLE. +#define BM_CCM_ANALOG_PFD_480_PFD0_STABLE (0x00000040) //!< Bit mask for CCM_ANALOG_PFD_480_PFD0_STABLE. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD0_STABLE from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD0_STABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD0_STABLE) >> BP_CCM_ANALOG_PFD_480_PFD0_STABLE) +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD0_CLKGATE[7] (RW) + * + * If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings). 0: + * ref_pfd0 fractional divider clock is enabled. Need to assert this bit before PLL is powered down + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD0_CLKGATE (7) //!< Bit position for CCM_ANALOG_PFD_480_PFD0_CLKGATE. +#define BM_CCM_ANALOG_PFD_480_PFD0_CLKGATE (0x00000080) //!< Bit mask for CCM_ANALOG_PFD_480_PFD0_CLKGATE. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD0_CLKGATE from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD0_CLKGATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD0_CLKGATE) >> BP_CCM_ANALOG_PFD_480_PFD0_CLKGATE) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_480_PFD0_CLKGATE. +#define BF_CCM_ANALOG_PFD_480_PFD0_CLKGATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_480_PFD0_CLKGATE) & BM_CCM_ANALOG_PFD_480_PFD0_CLKGATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD0_CLKGATE field to a new value. +#define BW_CCM_ANALOG_PFD_480_PFD0_CLKGATE(v) BF_CS1(CCM_ANALOG_PFD_480, PFD0_CLKGATE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD1_FRAC[13:8] (RW) + * + * This field controls the fractional divide value. The resulting frequency shall be + * 480*18/PFD1_FRAC where PFD1_FRAC is in the range 12-35. + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD1_FRAC (8) //!< Bit position for CCM_ANALOG_PFD_480_PFD1_FRAC. +#define BM_CCM_ANALOG_PFD_480_PFD1_FRAC (0x00003f00) //!< Bit mask for CCM_ANALOG_PFD_480_PFD1_FRAC. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD1_FRAC from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD1_FRAC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD1_FRAC) >> BP_CCM_ANALOG_PFD_480_PFD1_FRAC) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_480_PFD1_FRAC. +#define BF_CCM_ANALOG_PFD_480_PFD1_FRAC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_480_PFD1_FRAC) & BM_CCM_ANALOG_PFD_480_PFD1_FRAC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD1_FRAC field to a new value. +#define BW_CCM_ANALOG_PFD_480_PFD1_FRAC(v) BF_CS1(CCM_ANALOG_PFD_480, PFD1_FRAC, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD1_STABLE[14] (RO) + * + * This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should + * become stable quickly enough that this field will never need to be used by either device driver + * or application code. The value inverts when the new programmed fractional divide value has taken + * effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock + * output is stable. Note that the value will not invert when the fractional divider is taken out of + * or placed into clock-gated state. + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD1_STABLE (14) //!< Bit position for CCM_ANALOG_PFD_480_PFD1_STABLE. +#define BM_CCM_ANALOG_PFD_480_PFD1_STABLE (0x00004000) //!< Bit mask for CCM_ANALOG_PFD_480_PFD1_STABLE. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD1_STABLE from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD1_STABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD1_STABLE) >> BP_CCM_ANALOG_PFD_480_PFD1_STABLE) +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD1_CLKGATE[15] (RW) + * + * IO Clock Gate. If set to 1, the IO fractional divider clock (reference ref_pfd1) is off (power + * savings). 0: ref_pfd1 fractional divider clock is enabled. Need to assert this bit before PLL is + * powered down + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD1_CLKGATE (15) //!< Bit position for CCM_ANALOG_PFD_480_PFD1_CLKGATE. +#define BM_CCM_ANALOG_PFD_480_PFD1_CLKGATE (0x00008000) //!< Bit mask for CCM_ANALOG_PFD_480_PFD1_CLKGATE. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD1_CLKGATE from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD1_CLKGATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD1_CLKGATE) >> BP_CCM_ANALOG_PFD_480_PFD1_CLKGATE) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_480_PFD1_CLKGATE. +#define BF_CCM_ANALOG_PFD_480_PFD1_CLKGATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_480_PFD1_CLKGATE) & BM_CCM_ANALOG_PFD_480_PFD1_CLKGATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD1_CLKGATE field to a new value. +#define BW_CCM_ANALOG_PFD_480_PFD1_CLKGATE(v) BF_CS1(CCM_ANALOG_PFD_480, PFD1_CLKGATE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD2_FRAC[21:16] (RW) + * + * This field controls the fractional divide value. The resulting frequency shall be + * 480*18/PFD2_FRAC where PFD2_FRAC is in the range 12-35. + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD2_FRAC (16) //!< Bit position for CCM_ANALOG_PFD_480_PFD2_FRAC. +#define BM_CCM_ANALOG_PFD_480_PFD2_FRAC (0x003f0000) //!< Bit mask for CCM_ANALOG_PFD_480_PFD2_FRAC. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD2_FRAC from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD2_FRAC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD2_FRAC) >> BP_CCM_ANALOG_PFD_480_PFD2_FRAC) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_480_PFD2_FRAC. +#define BF_CCM_ANALOG_PFD_480_PFD2_FRAC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_480_PFD2_FRAC) & BM_CCM_ANALOG_PFD_480_PFD2_FRAC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD2_FRAC field to a new value. +#define BW_CCM_ANALOG_PFD_480_PFD2_FRAC(v) BF_CS1(CCM_ANALOG_PFD_480, PFD2_FRAC, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD2_STABLE[22] (RO) + * + * This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should + * become stable quickly enough that this field will never need to be used by either device driver + * or application code. The value inverts when the new programmed fractional divide value has taken + * effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock + * output is stable. Note that the value will not invert when the fractional divider is taken out of + * or placed into clock-gated state. + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD2_STABLE (22) //!< Bit position for CCM_ANALOG_PFD_480_PFD2_STABLE. +#define BM_CCM_ANALOG_PFD_480_PFD2_STABLE (0x00400000) //!< Bit mask for CCM_ANALOG_PFD_480_PFD2_STABLE. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD2_STABLE from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD2_STABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD2_STABLE) >> BP_CCM_ANALOG_PFD_480_PFD2_STABLE) +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD2_CLKGATE[23] (RW) + * + * IO Clock Gate. If set to 1, the IO fractional divider clock (reference ref_pfd2) is off (power + * savings). 0: ref_pfd2 fractional divider clock is enabled. Need to assert this bit before PLL is + * powered down + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD2_CLKGATE (23) //!< Bit position for CCM_ANALOG_PFD_480_PFD2_CLKGATE. +#define BM_CCM_ANALOG_PFD_480_PFD2_CLKGATE (0x00800000) //!< Bit mask for CCM_ANALOG_PFD_480_PFD2_CLKGATE. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD2_CLKGATE from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD2_CLKGATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD2_CLKGATE) >> BP_CCM_ANALOG_PFD_480_PFD2_CLKGATE) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_480_PFD2_CLKGATE. +#define BF_CCM_ANALOG_PFD_480_PFD2_CLKGATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_480_PFD2_CLKGATE) & BM_CCM_ANALOG_PFD_480_PFD2_CLKGATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD2_CLKGATE field to a new value. +#define BW_CCM_ANALOG_PFD_480_PFD2_CLKGATE(v) BF_CS1(CCM_ANALOG_PFD_480, PFD2_CLKGATE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD3_FRAC[29:24] (RW) + * + * This field controls the fractional divide value. The resulting frequency shall be + * 480*18/PFD3_FRAC where PFD3_FRAC is in the range 12-35. + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD3_FRAC (24) //!< Bit position for CCM_ANALOG_PFD_480_PFD3_FRAC. +#define BM_CCM_ANALOG_PFD_480_PFD3_FRAC (0x3f000000) //!< Bit mask for CCM_ANALOG_PFD_480_PFD3_FRAC. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD3_FRAC from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD3_FRAC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD3_FRAC) >> BP_CCM_ANALOG_PFD_480_PFD3_FRAC) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_480_PFD3_FRAC. +#define BF_CCM_ANALOG_PFD_480_PFD3_FRAC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_480_PFD3_FRAC) & BM_CCM_ANALOG_PFD_480_PFD3_FRAC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD3_FRAC field to a new value. +#define BW_CCM_ANALOG_PFD_480_PFD3_FRAC(v) BF_CS1(CCM_ANALOG_PFD_480, PFD3_FRAC, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD3_STABLE[30] (RO) + * + * This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should + * become stable quickly enough that this field will never need to be used by either device driver + * or application code. The value inverts when the new programmed fractional divide value has taken + * effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock + * output is stable. Note that the value will not invert when the fractional divider is taken out of + * or placed into clock-gated state. + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD3_STABLE (30) //!< Bit position for CCM_ANALOG_PFD_480_PFD3_STABLE. +#define BM_CCM_ANALOG_PFD_480_PFD3_STABLE (0x40000000) //!< Bit mask for CCM_ANALOG_PFD_480_PFD3_STABLE. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD3_STABLE from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD3_STABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD3_STABLE) >> BP_CCM_ANALOG_PFD_480_PFD3_STABLE) +//@} + +/*! @name Register CCM_ANALOG_PFD_480, field PFD3_CLKGATE[31] (RW) + * + * IO Clock Gate. If set to 1, the 3rd fractional divider clock (reference ref_pfd3) is off (power + * savings). 0: ref_pfd3 fractional divider clock is enabled. Need to assert this bit before PLL is + * powered down + */ +//@{ +#define BP_CCM_ANALOG_PFD_480_PFD3_CLKGATE (31) //!< Bit position for CCM_ANALOG_PFD_480_PFD3_CLKGATE. +#define BM_CCM_ANALOG_PFD_480_PFD3_CLKGATE (0x80000000) //!< Bit mask for CCM_ANALOG_PFD_480_PFD3_CLKGATE. + +//! @brief Get value of CCM_ANALOG_PFD_480_PFD3_CLKGATE from a register value. +#define BG_CCM_ANALOG_PFD_480_PFD3_CLKGATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_480_PFD3_CLKGATE) >> BP_CCM_ANALOG_PFD_480_PFD3_CLKGATE) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_480_PFD3_CLKGATE. +#define BF_CCM_ANALOG_PFD_480_PFD3_CLKGATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_480_PFD3_CLKGATE) & BM_CCM_ANALOG_PFD_480_PFD3_CLKGATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD3_CLKGATE field to a new value. +#define BW_CCM_ANALOG_PFD_480_PFD3_CLKGATE(v) BF_CS1(CCM_ANALOG_PFD_480, PFD3_CLKGATE, v) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_PFD_528 - 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_PFD_528 - 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register (RW) + * + * Reset value: 0x1018101b + * + * The PFD_528 control register provides control for PFD clock generation. This register controls + * the 4-phase fractional clock dividers. The fractional clock frequencies are a product of the + * values in these registers. + */ +typedef union _hw_ccm_analog_pfd_528 +{ + reg32_t U; + struct _hw_ccm_analog_pfd_528_bitfields + { + unsigned PFD0_FRAC : 6; //!< [5:0] This field controls the fractional divide value. + unsigned PFD0_STABLE : 1; //!< [6] This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. + unsigned PFD0_CLKGATE : 1; //!< [7] If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings). + unsigned PFD1_FRAC : 6; //!< [13:8] This field controls the fractional divide value. + unsigned PFD1_STABLE : 1; //!< [14] This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. + unsigned PFD1_CLKGATE : 1; //!< [15] IO Clock Gate. + unsigned PFD2_FRAC : 6; //!< [21:16] This field controls the fractional divide value. + unsigned PFD2_STABLE : 1; //!< [22] This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. + unsigned PFD2_CLKGATE : 1; //!< [23] IO Clock Gate. + unsigned PFD3_FRAC : 6; //!< [29:24] This field controls the fractional divide value. + unsigned PFD3_STABLE : 1; //!< [30] This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. + unsigned PFD3_CLKGATE : 1; //!< [31] IO Clock Gate. + } B; +} hw_ccm_analog_pfd_528_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_PFD_528 register + */ +//@{ +#define HW_CCM_ANALOG_PFD_528_ADDR (REGS_CCM_ANALOG_BASE + 0x100) +#define HW_CCM_ANALOG_PFD_528_SET_ADDR (HW_CCM_ANALOG_PFD_528_ADDR + 0x4) +#define HW_CCM_ANALOG_PFD_528_CLR_ADDR (HW_CCM_ANALOG_PFD_528_ADDR + 0x8) +#define HW_CCM_ANALOG_PFD_528_TOG_ADDR (HW_CCM_ANALOG_PFD_528_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_PFD_528 (*(volatile hw_ccm_analog_pfd_528_t *) HW_CCM_ANALOG_PFD_528_ADDR) +#define HW_CCM_ANALOG_PFD_528_RD() (HW_CCM_ANALOG_PFD_528.U) +#define HW_CCM_ANALOG_PFD_528_WR(v) (HW_CCM_ANALOG_PFD_528.U = (v)) +#define HW_CCM_ANALOG_PFD_528_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PFD_528_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_PFD_528_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PFD_528_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_PFD_528_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_PFD_528_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_PFD_528 bitfields + */ + +/*! @name Register CCM_ANALOG_PFD_528, field PFD0_FRAC[5:0] (RW) + * + * This field controls the fractional divide value. The resulting frequency shall be + * 528*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35. + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD0_FRAC (0) //!< Bit position for CCM_ANALOG_PFD_528_PFD0_FRAC. +#define BM_CCM_ANALOG_PFD_528_PFD0_FRAC (0x0000003f) //!< Bit mask for CCM_ANALOG_PFD_528_PFD0_FRAC. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD0_FRAC from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD0_FRAC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD0_FRAC) >> BP_CCM_ANALOG_PFD_528_PFD0_FRAC) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_528_PFD0_FRAC. +#define BF_CCM_ANALOG_PFD_528_PFD0_FRAC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_528_PFD0_FRAC) & BM_CCM_ANALOG_PFD_528_PFD0_FRAC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD0_FRAC field to a new value. +#define BW_CCM_ANALOG_PFD_528_PFD0_FRAC(v) BF_CS1(CCM_ANALOG_PFD_528, PFD0_FRAC, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD0_STABLE[6] (RO) + * + * This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should + * become stable quickly enough that this field will never need to be used by either device driver + * or application code. The value inverts when the new programmed fractional divide value has taken + * effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock + * output is stable. Note that the value will not invert when the fractional divider is taken out of + * or placed into clock-gated state. + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD0_STABLE (6) //!< Bit position for CCM_ANALOG_PFD_528_PFD0_STABLE. +#define BM_CCM_ANALOG_PFD_528_PFD0_STABLE (0x00000040) //!< Bit mask for CCM_ANALOG_PFD_528_PFD0_STABLE. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD0_STABLE from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD0_STABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD0_STABLE) >> BP_CCM_ANALOG_PFD_528_PFD0_STABLE) +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD0_CLKGATE[7] (RW) + * + * If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings). 0: + * ref_pfd0 fractional divider clock is enabled. Need to assert this bit before PLL powered down + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD0_CLKGATE (7) //!< Bit position for CCM_ANALOG_PFD_528_PFD0_CLKGATE. +#define BM_CCM_ANALOG_PFD_528_PFD0_CLKGATE (0x00000080) //!< Bit mask for CCM_ANALOG_PFD_528_PFD0_CLKGATE. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD0_CLKGATE from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD0_CLKGATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD0_CLKGATE) >> BP_CCM_ANALOG_PFD_528_PFD0_CLKGATE) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_528_PFD0_CLKGATE. +#define BF_CCM_ANALOG_PFD_528_PFD0_CLKGATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_528_PFD0_CLKGATE) & BM_CCM_ANALOG_PFD_528_PFD0_CLKGATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD0_CLKGATE field to a new value. +#define BW_CCM_ANALOG_PFD_528_PFD0_CLKGATE(v) BF_CS1(CCM_ANALOG_PFD_528, PFD0_CLKGATE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD1_FRAC[13:8] (RW) + * + * This field controls the fractional divide value. The resulting frequency shall be + * 528*18/PFD1_FRAC where PFD1_FRAC is in the range 12-35. + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD1_FRAC (8) //!< Bit position for CCM_ANALOG_PFD_528_PFD1_FRAC. +#define BM_CCM_ANALOG_PFD_528_PFD1_FRAC (0x00003f00) //!< Bit mask for CCM_ANALOG_PFD_528_PFD1_FRAC. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD1_FRAC from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD1_FRAC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD1_FRAC) >> BP_CCM_ANALOG_PFD_528_PFD1_FRAC) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_528_PFD1_FRAC. +#define BF_CCM_ANALOG_PFD_528_PFD1_FRAC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_528_PFD1_FRAC) & BM_CCM_ANALOG_PFD_528_PFD1_FRAC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD1_FRAC field to a new value. +#define BW_CCM_ANALOG_PFD_528_PFD1_FRAC(v) BF_CS1(CCM_ANALOG_PFD_528, PFD1_FRAC, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD1_STABLE[14] (RO) + * + * This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should + * become stable quickly enough that this field will never need to be used by either device driver + * or application code. The value inverts when the new programmed fractional divide value has taken + * effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock + * output is stable. Note that the value will not invert when the fractional divider is taken out of + * or placed into clock-gated state. + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD1_STABLE (14) //!< Bit position for CCM_ANALOG_PFD_528_PFD1_STABLE. +#define BM_CCM_ANALOG_PFD_528_PFD1_STABLE (0x00004000) //!< Bit mask for CCM_ANALOG_PFD_528_PFD1_STABLE. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD1_STABLE from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD1_STABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD1_STABLE) >> BP_CCM_ANALOG_PFD_528_PFD1_STABLE) +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD1_CLKGATE[15] (RW) + * + * IO Clock Gate. If set to 1, the IO fractional divider clock (reference ref_pfd1) is off (power + * savings). 0: ref_pfd1 fractional divider clock is enabled. Need to assert this bit before PLL + * powered down + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD1_CLKGATE (15) //!< Bit position for CCM_ANALOG_PFD_528_PFD1_CLKGATE. +#define BM_CCM_ANALOG_PFD_528_PFD1_CLKGATE (0x00008000) //!< Bit mask for CCM_ANALOG_PFD_528_PFD1_CLKGATE. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD1_CLKGATE from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD1_CLKGATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD1_CLKGATE) >> BP_CCM_ANALOG_PFD_528_PFD1_CLKGATE) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_528_PFD1_CLKGATE. +#define BF_CCM_ANALOG_PFD_528_PFD1_CLKGATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_528_PFD1_CLKGATE) & BM_CCM_ANALOG_PFD_528_PFD1_CLKGATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD1_CLKGATE field to a new value. +#define BW_CCM_ANALOG_PFD_528_PFD1_CLKGATE(v) BF_CS1(CCM_ANALOG_PFD_528, PFD1_CLKGATE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD2_FRAC[21:16] (RW) + * + * This field controls the fractional divide value. The resulting frequency shall be + * 528*18/PFD2_FRAC where PFD2_FRAC is in the range 12-35. + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD2_FRAC (16) //!< Bit position for CCM_ANALOG_PFD_528_PFD2_FRAC. +#define BM_CCM_ANALOG_PFD_528_PFD2_FRAC (0x003f0000) //!< Bit mask for CCM_ANALOG_PFD_528_PFD2_FRAC. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD2_FRAC from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD2_FRAC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD2_FRAC) >> BP_CCM_ANALOG_PFD_528_PFD2_FRAC) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_528_PFD2_FRAC. +#define BF_CCM_ANALOG_PFD_528_PFD2_FRAC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_528_PFD2_FRAC) & BM_CCM_ANALOG_PFD_528_PFD2_FRAC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD2_FRAC field to a new value. +#define BW_CCM_ANALOG_PFD_528_PFD2_FRAC(v) BF_CS1(CCM_ANALOG_PFD_528, PFD2_FRAC, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD2_STABLE[22] (RO) + * + * This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should + * become stable quickly enough that this field will never need to be used by either device driver + * or application code. The value inverts when the new programmed fractional divide value has taken + * effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock + * output is stable. Note that the value will not invert when the fractional divider is taken out of + * or placed into clock-gated state. + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD2_STABLE (22) //!< Bit position for CCM_ANALOG_PFD_528_PFD2_STABLE. +#define BM_CCM_ANALOG_PFD_528_PFD2_STABLE (0x00400000) //!< Bit mask for CCM_ANALOG_PFD_528_PFD2_STABLE. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD2_STABLE from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD2_STABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD2_STABLE) >> BP_CCM_ANALOG_PFD_528_PFD2_STABLE) +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD2_CLKGATE[23] (RW) + * + * IO Clock Gate. If set to 1, the IO fractional divider clock (reference ref_pfd2) is off (power + * savings). 0: ref_pfd2 fractional divider clock is enabled. Need to assert this bit before PLL + * powered down + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD2_CLKGATE (23) //!< Bit position for CCM_ANALOG_PFD_528_PFD2_CLKGATE. +#define BM_CCM_ANALOG_PFD_528_PFD2_CLKGATE (0x00800000) //!< Bit mask for CCM_ANALOG_PFD_528_PFD2_CLKGATE. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD2_CLKGATE from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD2_CLKGATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD2_CLKGATE) >> BP_CCM_ANALOG_PFD_528_PFD2_CLKGATE) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_528_PFD2_CLKGATE. +#define BF_CCM_ANALOG_PFD_528_PFD2_CLKGATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_528_PFD2_CLKGATE) & BM_CCM_ANALOG_PFD_528_PFD2_CLKGATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD2_CLKGATE field to a new value. +#define BW_CCM_ANALOG_PFD_528_PFD2_CLKGATE(v) BF_CS1(CCM_ANALOG_PFD_528, PFD2_CLKGATE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD3_FRAC[29:24] (RW) + * + * This field controls the fractional divide value. The resulting frequency shall be + * 528*18/PFD3_FRAC where PFD3_FRAC is in the range 12-35. + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD3_FRAC (24) //!< Bit position for CCM_ANALOG_PFD_528_PFD3_FRAC. +#define BM_CCM_ANALOG_PFD_528_PFD3_FRAC (0x3f000000) //!< Bit mask for CCM_ANALOG_PFD_528_PFD3_FRAC. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD3_FRAC from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD3_FRAC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD3_FRAC) >> BP_CCM_ANALOG_PFD_528_PFD3_FRAC) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_528_PFD3_FRAC. +#define BF_CCM_ANALOG_PFD_528_PFD3_FRAC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_528_PFD3_FRAC) & BM_CCM_ANALOG_PFD_528_PFD3_FRAC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD3_FRAC field to a new value. +#define BW_CCM_ANALOG_PFD_528_PFD3_FRAC(v) BF_CS1(CCM_ANALOG_PFD_528, PFD3_FRAC, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD3_STABLE[30] (RO) + * + * This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should + * become stable quickly enough that this field will never need to be used by either device driver + * or application code. The value inverts when the new programmed fractional divide value has taken + * effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock + * output is stable. Note that the value will not invert when the fractional divider is taken out of + * or placed into clock-gated state. + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD3_STABLE (30) //!< Bit position for CCM_ANALOG_PFD_528_PFD3_STABLE. +#define BM_CCM_ANALOG_PFD_528_PFD3_STABLE (0x40000000) //!< Bit mask for CCM_ANALOG_PFD_528_PFD3_STABLE. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD3_STABLE from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD3_STABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD3_STABLE) >> BP_CCM_ANALOG_PFD_528_PFD3_STABLE) +//@} + +/*! @name Register CCM_ANALOG_PFD_528, field PFD3_CLKGATE[31] (RW) + * + * IO Clock Gate. If set to 1, the 3rd fractional divider clock (reference ref_pfd3) is off (power + * savings). 0: ref_pfd3 fractional divider clock is enabled. Need to assert this bit before PLL + * powered down + */ +//@{ +#define BP_CCM_ANALOG_PFD_528_PFD3_CLKGATE (31) //!< Bit position for CCM_ANALOG_PFD_528_PFD3_CLKGATE. +#define BM_CCM_ANALOG_PFD_528_PFD3_CLKGATE (0x80000000) //!< Bit mask for CCM_ANALOG_PFD_528_PFD3_CLKGATE. + +//! @brief Get value of CCM_ANALOG_PFD_528_PFD3_CLKGATE from a register value. +#define BG_CCM_ANALOG_PFD_528_PFD3_CLKGATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_PFD_528_PFD3_CLKGATE) >> BP_CCM_ANALOG_PFD_528_PFD3_CLKGATE) + +//! @brief Format value for bitfield CCM_ANALOG_PFD_528_PFD3_CLKGATE. +#define BF_CCM_ANALOG_PFD_528_PFD3_CLKGATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_PFD_528_PFD3_CLKGATE) & BM_CCM_ANALOG_PFD_528_PFD3_CLKGATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PFD3_CLKGATE field to a new value. +#define BW_CCM_ANALOG_PFD_528_PFD3_CLKGATE(v) BF_CS1(CCM_ANALOG_PFD_528, PFD3_CLKGATE, v) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_MISC0 - Miscellaneous Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_MISC0 - Miscellaneous Control Register (RW) + * + * Reset value: 0x02000000 + * + * This register defines the control for miscellaneous CCM Analog blocks. + */ +typedef union _hw_ccm_analog_misc0 +{ + reg32_t U; + struct _hw_ccm_analog_misc0_bitfields + { + unsigned RESERVED0 : 12; //!< [11:0] + unsigned STOP_MODE_CONFIG : 1; //!< [12] Configure the analog behavior in stop mode. + unsigned RESERVED1 : 19; //!< [31:13] + } B; +} hw_ccm_analog_misc0_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_MISC0 register + */ +//@{ +#define HW_CCM_ANALOG_MISC0_ADDR (REGS_CCM_ANALOG_BASE + 0x150) +#define HW_CCM_ANALOG_MISC0_SET_ADDR (HW_CCM_ANALOG_MISC0_ADDR + 0x4) +#define HW_CCM_ANALOG_MISC0_CLR_ADDR (HW_CCM_ANALOG_MISC0_ADDR + 0x8) +#define HW_CCM_ANALOG_MISC0_TOG_ADDR (HW_CCM_ANALOG_MISC0_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_MISC0 (*(volatile hw_ccm_analog_misc0_t *) HW_CCM_ANALOG_MISC0_ADDR) +#define HW_CCM_ANALOG_MISC0_RD() (HW_CCM_ANALOG_MISC0.U) +#define HW_CCM_ANALOG_MISC0_WR(v) (HW_CCM_ANALOG_MISC0.U = (v)) +#define HW_CCM_ANALOG_MISC0_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_MISC0_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_MISC0_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_MISC0_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_MISC0_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_MISC0_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_MISC0 bitfields + */ + +/*! @name Register CCM_ANALOG_MISC0, field STOP_MODE_CONFIG[12] (RW) + * + * Configure the analog behavior in stop mode. + * + * Values: + * - 0 - All the analog domain except the RTC is powered down on STOP mode assertion + * - 1 - All the analog domain except the LDO_1P1 and LDO_2P5 regulators are powered down on STOP mode + * assertion. If required the CCM can be configured to not power down the oscillator (XTALOSC). + */ +//@{ +#define BP_CCM_ANALOG_MISC0_STOP_MODE_CONFIG (12) //!< Bit position for CCM_ANALOG_MISC0_STOP_MODE_CONFIG. +#define BM_CCM_ANALOG_MISC0_STOP_MODE_CONFIG (0x00001000) //!< Bit mask for CCM_ANALOG_MISC0_STOP_MODE_CONFIG. + +//! @brief Get value of CCM_ANALOG_MISC0_STOP_MODE_CONFIG from a register value. +#define BG_CCM_ANALOG_MISC0_STOP_MODE_CONFIG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_MISC0_STOP_MODE_CONFIG) >> BP_CCM_ANALOG_MISC0_STOP_MODE_CONFIG) + +//! @brief Format value for bitfield CCM_ANALOG_MISC0_STOP_MODE_CONFIG. +#define BF_CCM_ANALOG_MISC0_STOP_MODE_CONFIG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_MISC0_STOP_MODE_CONFIG) & BM_CCM_ANALOG_MISC0_STOP_MODE_CONFIG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STOP_MODE_CONFIG field to a new value. +#define BW_CCM_ANALOG_MISC0_STOP_MODE_CONFIG(v) BF_CS1(CCM_ANALOG_MISC0, STOP_MODE_CONFIG, v) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_CCM_ANALOG_MISC2 - Miscellaneous Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_CCM_ANALOG_MISC2 - Miscellaneous Control Register (RW) + * + * Reset value: 0x00272727 + * + * This register defines the control for miscellaneous CCM Analog blocks. + */ +typedef union _hw_ccm_analog_misc2 +{ + reg32_t U; + struct _hw_ccm_analog_misc2_bitfields + { + unsigned RESERVED0 : 7; //!< [6:0] + unsigned PLL3_DISABLE : 1; //!< [7] Default value of "0". + unsigned RESERVED1 : 7; //!< [14:8] + unsigned AUDIO_DIV_LSB : 1; //!< [15] LSB of Post-divider for Audio PLL. + unsigned RESERVED2 : 7; //!< [22:16] + unsigned AUDIO_DIV_MSB : 1; //!< [23] MSB of Post-divider for Audio PLL. + unsigned RESERVED3 : 6; //!< [29:24] + unsigned VIDEO_DIV : 2; //!< [31:30] Post-divider for video. + } B; +} hw_ccm_analog_misc2_t; +#endif + +/*! + * @name Constants and macros for entire CCM_ANALOG_MISC2 register + */ +//@{ +#define HW_CCM_ANALOG_MISC2_ADDR (REGS_CCM_ANALOG_BASE + 0x170) +#define HW_CCM_ANALOG_MISC2_SET_ADDR (HW_CCM_ANALOG_MISC2_ADDR + 0x4) +#define HW_CCM_ANALOG_MISC2_CLR_ADDR (HW_CCM_ANALOG_MISC2_ADDR + 0x8) +#define HW_CCM_ANALOG_MISC2_TOG_ADDR (HW_CCM_ANALOG_MISC2_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_CCM_ANALOG_MISC2 (*(volatile hw_ccm_analog_misc2_t *) HW_CCM_ANALOG_MISC2_ADDR) +#define HW_CCM_ANALOG_MISC2_RD() (HW_CCM_ANALOG_MISC2.U) +#define HW_CCM_ANALOG_MISC2_WR(v) (HW_CCM_ANALOG_MISC2.U = (v)) +#define HW_CCM_ANALOG_MISC2_SET(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_MISC2_SET_ADDR) = (v)) +#define HW_CCM_ANALOG_MISC2_CLR(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_MISC2_CLR_ADDR) = (v)) +#define HW_CCM_ANALOG_MISC2_TOG(v) ((*(volatile reg32_t *) HW_CCM_ANALOG_MISC2_TOG_ADDR) = (v)) +#endif +//@} + +/* + * constants & macros for individual CCM_ANALOG_MISC2 bitfields + */ + +/*! @name Register CCM_ANALOG_MISC2, field PLL3_DISABLE[7] (RW) + * + * Default value of "0". Should be set to "1" to turn off the USB-PLL(PLL3) in run mode + */ +//@{ +#define BP_CCM_ANALOG_MISC2_PLL3_DISABLE (7) //!< Bit position for CCM_ANALOG_MISC2_PLL3_DISABLE. +#define BM_CCM_ANALOG_MISC2_PLL3_DISABLE (0x00000080) //!< Bit mask for CCM_ANALOG_MISC2_PLL3_DISABLE. + +//! @brief Get value of CCM_ANALOG_MISC2_PLL3_DISABLE from a register value. +#define BG_CCM_ANALOG_MISC2_PLL3_DISABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_MISC2_PLL3_DISABLE) >> BP_CCM_ANALOG_MISC2_PLL3_DISABLE) + +//! @brief Format value for bitfield CCM_ANALOG_MISC2_PLL3_DISABLE. +#define BF_CCM_ANALOG_MISC2_PLL3_DISABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_MISC2_PLL3_DISABLE) & BM_CCM_ANALOG_MISC2_PLL3_DISABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PLL3_DISABLE field to a new value. +#define BW_CCM_ANALOG_MISC2_PLL3_DISABLE(v) BF_CS1(CCM_ANALOG_MISC2, PLL3_DISABLE, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_MISC2, field AUDIO_DIV_LSB[15] (RW) + * + * LSB of Post-divider for Audio PLL. The output clock of the video PLL should be gated prior to + * changing this divider to prevent glitches. + * + * Values: + * - 00 - divide by 1 (Default) + * - 01 - divide by 2 + * - 10 - divide by 1 + * - 11 - divide by 4 + */ +//@{ +#define BP_CCM_ANALOG_MISC2_AUDIO_DIV_LSB (15) //!< Bit position for CCM_ANALOG_MISC2_AUDIO_DIV_LSB. +#define BM_CCM_ANALOG_MISC2_AUDIO_DIV_LSB (0x00008000) //!< Bit mask for CCM_ANALOG_MISC2_AUDIO_DIV_LSB. + +//! @brief Get value of CCM_ANALOG_MISC2_AUDIO_DIV_LSB from a register value. +#define BG_CCM_ANALOG_MISC2_AUDIO_DIV_LSB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_MISC2_AUDIO_DIV_LSB) >> BP_CCM_ANALOG_MISC2_AUDIO_DIV_LSB) + +//! @brief Format value for bitfield CCM_ANALOG_MISC2_AUDIO_DIV_LSB. +#define BF_CCM_ANALOG_MISC2_AUDIO_DIV_LSB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_MISC2_AUDIO_DIV_LSB) & BM_CCM_ANALOG_MISC2_AUDIO_DIV_LSB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AUDIO_DIV_LSB field to a new value. +#define BW_CCM_ANALOG_MISC2_AUDIO_DIV_LSB(v) BF_CS1(CCM_ANALOG_MISC2, AUDIO_DIV_LSB, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_MISC2, field AUDIO_DIV_MSB[23] (RW) + * + * MSB of Post-divider for Audio PLL. The output clock of the video PLL should be gated prior to + * changing this divider to prevent glitches. + * + * Values: + * - 00 - divide by 1 (Default) + * - 01 - divide by 2 + * - 10 - divide by 1 + * - 11 - divide by 4 + */ +//@{ +#define BP_CCM_ANALOG_MISC2_AUDIO_DIV_MSB (23) //!< Bit position for CCM_ANALOG_MISC2_AUDIO_DIV_MSB. +#define BM_CCM_ANALOG_MISC2_AUDIO_DIV_MSB (0x00800000) //!< Bit mask for CCM_ANALOG_MISC2_AUDIO_DIV_MSB. + +//! @brief Get value of CCM_ANALOG_MISC2_AUDIO_DIV_MSB from a register value. +#define BG_CCM_ANALOG_MISC2_AUDIO_DIV_MSB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_MISC2_AUDIO_DIV_MSB) >> BP_CCM_ANALOG_MISC2_AUDIO_DIV_MSB) + +//! @brief Format value for bitfield CCM_ANALOG_MISC2_AUDIO_DIV_MSB. +#define BF_CCM_ANALOG_MISC2_AUDIO_DIV_MSB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_MISC2_AUDIO_DIV_MSB) & BM_CCM_ANALOG_MISC2_AUDIO_DIV_MSB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AUDIO_DIV_MSB field to a new value. +#define BW_CCM_ANALOG_MISC2_AUDIO_DIV_MSB(v) BF_CS1(CCM_ANALOG_MISC2, AUDIO_DIV_MSB, v) +#endif +//@} + +/*! @name Register CCM_ANALOG_MISC2, field VIDEO_DIV[31:30] (RW) + * + * Post-divider for video. The output clock of the video PLL should be gated prior to changing this + * divider to prevent glitches. + * + * Values: + * - 00 - divide by 1 (Default) + * - 01 - divide by 2 + * - 10 - divide by 1 + * - 11 - divide by 4 + */ +//@{ +#define BP_CCM_ANALOG_MISC2_VIDEO_DIV (30) //!< Bit position for CCM_ANALOG_MISC2_VIDEO_DIV. +#define BM_CCM_ANALOG_MISC2_VIDEO_DIV (0xc0000000) //!< Bit mask for CCM_ANALOG_MISC2_VIDEO_DIV. + +//! @brief Get value of CCM_ANALOG_MISC2_VIDEO_DIV from a register value. +#define BG_CCM_ANALOG_MISC2_VIDEO_DIV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_CCM_ANALOG_MISC2_VIDEO_DIV) >> BP_CCM_ANALOG_MISC2_VIDEO_DIV) + +//! @brief Format value for bitfield CCM_ANALOG_MISC2_VIDEO_DIV. +#define BF_CCM_ANALOG_MISC2_VIDEO_DIV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_CCM_ANALOG_MISC2_VIDEO_DIV) & BM_CCM_ANALOG_MISC2_VIDEO_DIV) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VIDEO_DIV field to a new value. +#define BW_CCM_ANALOG_MISC2_VIDEO_DIV(v) BF_CS1(CCM_ANALOG_MISC2, VIDEO_DIV, v) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// hw_ccm_analog_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All CCM_ANALOG module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_ccm_analog +{ + volatile hw_ccm_analog_pll_arm_t PLL_ARM; //!< Analog ARM PLL control Register + volatile reg32_t PLL_ARM_SET; //!< Analog ARM PLL control Register Set + volatile reg32_t PLL_ARM_CLR; //!< Analog ARM PLL control Register Clear + volatile reg32_t PLL_ARM_TOG; //!< Analog ARM PLL control Register Toggle + volatile hw_ccm_analog_pll_usb1_t PLL_USB1; //!< Analog USB1 480MHz PLL Control Register + volatile reg32_t PLL_USB1_SET; //!< Analog USB1 480MHz PLL Control Register Set + volatile reg32_t PLL_USB1_CLR; //!< Analog USB1 480MHz PLL Control Register Clear + volatile reg32_t PLL_USB1_TOG; //!< Analog USB1 480MHz PLL Control Register Toggle + volatile hw_ccm_analog_pll_usb2_t PLL_USB2; //!< Analog USB2 480MHz PLL Control Register + volatile reg32_t PLL_USB2_SET; //!< Analog USB2 480MHz PLL Control Register Set + volatile reg32_t PLL_USB2_CLR; //!< Analog USB2 480MHz PLL Control Register Clear + volatile reg32_t PLL_USB2_TOG; //!< Analog USB2 480MHz PLL Control Register Toggle + volatile hw_ccm_analog_pll_sys_t PLL_SYS; //!< Analog System PLL Control Register + volatile reg32_t PLL_SYS_SET; //!< Analog System PLL Control Register Set + volatile reg32_t PLL_SYS_CLR; //!< Analog System PLL Control Register Clear + volatile reg32_t PLL_SYS_TOG; //!< Analog System PLL Control Register Toggle + volatile hw_ccm_analog_pll_sys_ss_t PLL_SYS_SS; //!< 528MHz System PLL Spread Spectrum Register. + reg32_t _reserved0[3]; + volatile hw_ccm_analog_pll_sys_num_t PLL_SYS_NUM; //!< Numerator of 528MHz System PLL Fractional Loop Divider Register + reg32_t _reserved1[3]; + volatile hw_ccm_analog_pll_sys_denom_t PLL_SYS_DENOM; //!< Denominator of 528MHz System PLL Fractional Loop Divider Register + reg32_t _reserved2[3]; + volatile hw_ccm_analog_pll_audio_t PLL_AUDIO; //!< Analog Audio PLL control Register + volatile reg32_t PLL_AUDIO_SET; //!< Analog Audio PLL control Register Set + volatile reg32_t PLL_AUDIO_CLR; //!< Analog Audio PLL control Register Clear + volatile reg32_t PLL_AUDIO_TOG; //!< Analog Audio PLL control Register Toggle + volatile hw_ccm_analog_pll_audio_num_t PLL_AUDIO_NUM; //!< Numerator of Audio PLL Fractional Loop Divider Register + reg32_t _reserved3[3]; + volatile hw_ccm_analog_pll_audio_denom_t PLL_AUDIO_DENOM; //!< Denominator of Audio PLL Fractional Loop Divider Register + reg32_t _reserved4[3]; + volatile hw_ccm_analog_pll_video_t PLL_VIDEO; //!< Analog Video PLL control Register + volatile reg32_t PLL_VIDEO_SET; //!< Analog Video PLL control Register Set + volatile reg32_t PLL_VIDEO_CLR; //!< Analog Video PLL control Register Clear + volatile reg32_t PLL_VIDEO_TOG; //!< Analog Video PLL control Register Toggle + volatile hw_ccm_analog_pll_video_num_t PLL_VIDEO_NUM; //!< Numerator of Video PLL Fractional Loop Divider Register + reg32_t _reserved5[3]; + volatile hw_ccm_analog_pll_video_denom_t PLL_VIDEO_DENOM; //!< Denominator of Video PLL Fractional Loop Divider Register + reg32_t _reserved6[3]; + volatile hw_ccm_analog_pll_mlb_t PLL_MLB; //!< MLB PLL Control Register + volatile reg32_t PLL_MLB_SET; //!< MLB PLL Control Register Set + volatile reg32_t PLL_MLB_CLR; //!< MLB PLL Control Register Clear + volatile reg32_t PLL_MLB_TOG; //!< MLB PLL Control Register Toggle + volatile hw_ccm_analog_pll_enet_t PLL_ENET; //!< Analog ENET PLL Control Register + volatile reg32_t PLL_ENET_SET; //!< Analog ENET PLL Control Register Set + volatile reg32_t PLL_ENET_CLR; //!< Analog ENET PLL Control Register Clear + volatile reg32_t PLL_ENET_TOG; //!< Analog ENET PLL Control Register Toggle + volatile hw_ccm_analog_pfd_480_t PFD_480; //!< 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register + volatile reg32_t PFD_480_SET; //!< 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register Set + volatile reg32_t PFD_480_CLR; //!< 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register Clear + volatile reg32_t PFD_480_TOG; //!< 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register Toggle + volatile hw_ccm_analog_pfd_528_t PFD_528; //!< 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register + volatile reg32_t PFD_528_SET; //!< 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register Set + volatile reg32_t PFD_528_CLR; //!< 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register Clear + volatile reg32_t PFD_528_TOG; //!< 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register Toggle + reg32_t _reserved7[16]; + volatile hw_ccm_analog_misc0_t MISC0; //!< Miscellaneous Control Register + volatile reg32_t MISC0_SET; //!< Miscellaneous Control Register Set + volatile reg32_t MISC0_CLR; //!< Miscellaneous Control Register Clear + volatile reg32_t MISC0_TOG; //!< Miscellaneous Control Register Toggle + reg32_t _reserved8[4]; + volatile hw_ccm_analog_misc2_t MISC2; //!< Miscellaneous Control Register + volatile reg32_t MISC2_SET; //!< Miscellaneous Control Register Set + volatile reg32_t MISC2_CLR; //!< Miscellaneous Control Register Clear + volatile reg32_t MISC2_TOG; //!< Miscellaneous Control Register Toggle +} hw_ccm_analog_t; +#pragma pack() + +//! @brief Macro to access all CCM_ANALOG registers. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_CCM_ANALOG. +#define HW_CCM_ANALOG (*(hw_ccm_analog_t *) REGS_CCM_ANALOG_BASE) +#endif + +#endif // __HW_CCM_ANALOG_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsecspi.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsecspi.h new file mode 100644 index 0000000000000000000000000000000000000000..24172aa575a9fae9750e837e939777ef3b518fcf --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsecspi.h @@ -0,0 +1,1735 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_ECSPI_REGISTERS_H__ +#define __HW_ECSPI_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL ECSPI + * + * ECSPI + * + * Registers defined in this header file: + * - HW_ECSPI_RXDATA - Receive Data Register + * - HW_ECSPI_TXDATA - Transmit Data Register + * - HW_ECSPI_CONREG - Control Register + * - HW_ECSPI_CONFIGREG - Config Register + * - HW_ECSPI_INTREG - Interrupt Control Register + * - HW_ECSPI_DMAREG - DMA Control Register + * - HW_ECSPI_STATREG - Status Register + * - HW_ECSPI_PERIODREG - Sample Period Control Register + * - HW_ECSPI_TESTREG - Test Control Register + * - HW_ECSPI_MSGDATA - Message Data Register + * + * - hw_ecspi_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_ECSPI_BASE +#define HW_ECSPI_INSTANCE_COUNT (4) //!< Number of instances of the ECSPI module. +#define HW_ECSPI1 (1) //!< Instance number for ECSPI1. +#define HW_ECSPI2 (2) //!< Instance number for ECSPI2. +#define HW_ECSPI3 (3) //!< Instance number for ECSPI3. +#define HW_ECSPI4 (4) //!< Instance number for ECSPI4. +#define REGS_ECSPI1_BASE (0x02008000) //!< Base address for ECSPI instance number 1. +#define REGS_ECSPI2_BASE (0x0200c000) //!< Base address for ECSPI instance number 2. +#define REGS_ECSPI3_BASE (0x02010000) //!< Base address for ECSPI instance number 3. +#define REGS_ECSPI4_BASE (0x02014000) //!< Base address for ECSPI instance number 4. + +//! @brief Get the base address of ECSPI by instance number. +//! @param x ECSPI instance number, from 1 through 4. +#define REGS_ECSPI_BASE(x) ( (x) == HW_ECSPI1 ? REGS_ECSPI1_BASE : (x) == HW_ECSPI2 ? REGS_ECSPI2_BASE : (x) == HW_ECSPI3 ? REGS_ECSPI3_BASE : (x) == HW_ECSPI4 ? REGS_ECSPI4_BASE : 0x00d00000) + +//! @brief Get the instance number given a base address. +//! @param b Base address for an instance of ECSPI. +#define REGS_ECSPI_INSTANCE(b) ( (b) == REGS_ECSPI1_BASE ? HW_ECSPI1 : (b) == REGS_ECSPI2_BASE ? HW_ECSPI2 : (b) == REGS_ECSPI3_BASE ? HW_ECSPI3 : (b) == REGS_ECSPI4_BASE ? HW_ECSPI4 : 0) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_RXDATA - Receive Data Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_RXDATA - Receive Data Register (RO) + * + * Reset value: 0x00000000 + * + * The Receive Data register (ECSPI_RXDATA) is a read-only register that forms the top word of the + * 64 x 32 receive FIFO. This register holds the data received from an external SPI device during a + * data transaction. Only word-sized read operations are allowed. + */ +typedef union _hw_ecspi_rxdata +{ + reg32_t U; + struct _hw_ecspi_rxdata_bitfields + { + unsigned ECSPI_RXDATA : 32; //!< [31:0] Receive Data. + } B; +} hw_ecspi_rxdata_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_RXDATA register + */ +//@{ +#define HW_ECSPI_RXDATA_ADDR(x) (REGS_ECSPI_BASE(x) + 0x0) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_RXDATA(x) (*(volatile hw_ecspi_rxdata_t *) HW_ECSPI_RXDATA_ADDR(x)) +#define HW_ECSPI_RXDATA_RD(x) (HW_ECSPI_RXDATA(x).U) +#endif +//@} + +/* + * constants & macros for individual ECSPI_RXDATA bitfields + */ + +/*! @name Register ECSPI_RXDATA, field ECSPI_RXDATA[31:0] (RO) + * + * Receive Data. This register holds the top word of the receive data FIFO. The FIFO is advanced for + * each read of this register. The data read is undefined when the Receive Data Ready (RR) bit in + * the Interrupt Control/Status register is cleared. Zeros are read when ECSPI is disabled. + */ +//@{ +#define BP_ECSPI_RXDATA_ECSPI_RXDATA (0) //!< Bit position for ECSPI_RXDATA_ECSPI_RXDATA. +#define BM_ECSPI_RXDATA_ECSPI_RXDATA (0xffffffff) //!< Bit mask for ECSPI_RXDATA_ECSPI_RXDATA. + +//! @brief Get value of ECSPI_RXDATA_ECSPI_RXDATA from a register value. +#define BG_ECSPI_RXDATA_ECSPI_RXDATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_RXDATA_ECSPI_RXDATA) >> BP_ECSPI_RXDATA_ECSPI_RXDATA) +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_TXDATA - Transmit Data Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_TXDATA - Transmit Data Register (WO) + * + * Reset value: 0x00000000 + * + * The Transmit Data (ECSPI_TXDATA) register is a write-only data register that forms the bottom + * word of the 64 x 32 TXFIFO. The TXFIFO can be written to as long as it is not full, even when the + * SPI Exchange bit (XCH) in ECSPI_CONREG is set. This allows software to write to the TXFIFO during + * a SPI data exchange process. Writes to this register are ignored when the ECSPI is disabled + * (ECSPI_CONREG[EN] bit is cleared). + */ +typedef union _hw_ecspi_txdata +{ + reg32_t U; + struct _hw_ecspi_txdata_bitfields + { + unsigned ECSPI_TXDATA : 32; //!< [31:0] Transmit Data. + } B; +} hw_ecspi_txdata_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_TXDATA register + */ +//@{ +#define HW_ECSPI_TXDATA_ADDR(x) (REGS_ECSPI_BASE(x) + 0x4) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_TXDATA(x) (*(volatile hw_ecspi_txdata_t *) HW_ECSPI_TXDATA_ADDR(x)) +#define HW_ECSPI_TXDATA_WR(x, v) (HW_ECSPI_TXDATA(x).U = (v)) +#endif +//@} + +/* + * constants & macros for individual ECSPI_TXDATA bitfields + */ + +/*! @name Register ECSPI_TXDATA, field ECSPI_TXDATA[31:0] (WO) + * + * Transmit Data. This register holds the top word of data loaded into the FIFO. Data written to + * this register must be a word operation. The number of bits actually transmitted is determined by + * the BIT_COUNT field of the corresponding SPI Control register. If this field contains more bits + * than the number specified by BIT_COUNT, the extra bits are ignored. For example, to transfer 10 + * bits of data, a 32-bit word must be written to this register. Bits 9-0 are shifted out and bits + * 31-10 are ignored. When the ECSPI is operating in Slave mode, zeros are shifted out when the FIFO + * is empty. Zeros are read when ECSPI is disabled. + */ +//@{ +#define BP_ECSPI_TXDATA_ECSPI_TXDATA (0) //!< Bit position for ECSPI_TXDATA_ECSPI_TXDATA. +#define BM_ECSPI_TXDATA_ECSPI_TXDATA (0xffffffff) //!< Bit mask for ECSPI_TXDATA_ECSPI_TXDATA. + +//! @brief Get value of ECSPI_TXDATA_ECSPI_TXDATA from a register value. +#define BG_ECSPI_TXDATA_ECSPI_TXDATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_TXDATA_ECSPI_TXDATA) >> BP_ECSPI_TXDATA_ECSPI_TXDATA) + +//! @brief Format value for bitfield ECSPI_TXDATA_ECSPI_TXDATA. +#define BF_ECSPI_TXDATA_ECSPI_TXDATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_TXDATA_ECSPI_TXDATA) & BM_ECSPI_TXDATA_ECSPI_TXDATA) +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_CONREG - Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_CONREG - Control Register (RW) + * + * Reset value: 0x00000000 + * + * The Control Register (ECSPI_CONREG) allows software to enable the ECSPI , configure its operating + * modes, specify the divider value, and SPI_RDY control signal, and define the transfer length. + */ +typedef union _hw_ecspi_conreg +{ + reg32_t U; + struct _hw_ecspi_conreg_bitfields + { + unsigned EN : 1; //!< [0] SPI Block Enable Control. + unsigned HT : 1; //!< [1] Hardware Trigger Enable. + unsigned XCH : 1; //!< [2] SPI Exchange Bit. + unsigned SMC : 1; //!< [3] Start Mode Control. + unsigned CHANNEL_MODE : 4; //!< [7:4] SPI CHANNEL MODE selects the mode for each SPI channel. + unsigned POST_DIVIDER : 4; //!< [11:8] SPI Post Divider. + unsigned PRE_DIVIDER : 4; //!< [15:12] SPI Pre Divider. + unsigned DRCTL : 2; //!< [17:16] SPI Data Ready Control. + unsigned CHANNEL_SELECT : 2; //!< [19:18] SPI CHANNEL SELECT bits. + unsigned BURST_LENGTH : 12; //!< [31:20] Burst Length. + } B; +} hw_ecspi_conreg_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_CONREG register + */ +//@{ +#define HW_ECSPI_CONREG_ADDR(x) (REGS_ECSPI_BASE(x) + 0x8) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_CONREG(x) (*(volatile hw_ecspi_conreg_t *) HW_ECSPI_CONREG_ADDR(x)) +#define HW_ECSPI_CONREG_RD(x) (HW_ECSPI_CONREG(x).U) +#define HW_ECSPI_CONREG_WR(x, v) (HW_ECSPI_CONREG(x).U = (v)) +#define HW_ECSPI_CONREG_SET(x, v) (HW_ECSPI_CONREG_WR(x, HW_ECSPI_CONREG_RD(x) | (v))) +#define HW_ECSPI_CONREG_CLR(x, v) (HW_ECSPI_CONREG_WR(x, HW_ECSPI_CONREG_RD(x) & ~(v))) +#define HW_ECSPI_CONREG_TOG(x, v) (HW_ECSPI_CONREG_WR(x, HW_ECSPI_CONREG_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ECSPI_CONREG bitfields + */ + +/*! @name Register ECSPI_CONREG, field EN[0] (RW) + * + * SPI Block Enable Control. This bit enables the ECSPI. This bit must be set before writing to + * other registers or initiating an exchange. Writing zero to this bit disables the block and resets + * the internal logic with the exception of the ECSPI_CONREG. The block's internal clocks are gated + * off whenever the block is disabled. + * + * Values: + * - 0 - Disable the block. + * - 1 - Enable the block. + */ +//@{ +#define BP_ECSPI_CONREG_EN (0) //!< Bit position for ECSPI_CONREG_EN. +#define BM_ECSPI_CONREG_EN (0x00000001) //!< Bit mask for ECSPI_CONREG_EN. + +//! @brief Get value of ECSPI_CONREG_EN from a register value. +#define BG_ECSPI_CONREG_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_EN) >> BP_ECSPI_CONREG_EN) + +//! @brief Format value for bitfield ECSPI_CONREG_EN. +#define BF_ECSPI_CONREG_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_EN) & BM_ECSPI_CONREG_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN field to a new value. +#define BW_ECSPI_CONREG_EN(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_EN) | BF_ECSPI_CONREG_EN(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field HT[1] (RW) + * + * Hardware Trigger Enable. This bit is used in master mode only. It enables hardware trigger (HT) + * mode. Note, HT mode is not supported by this product. + * + * Values: + * - 0 - Disable HT mode. + * - 1 - Enable HT mode. + */ +//@{ +#define BP_ECSPI_CONREG_HT (1) //!< Bit position for ECSPI_CONREG_HT. +#define BM_ECSPI_CONREG_HT (0x00000002) //!< Bit mask for ECSPI_CONREG_HT. + +//! @brief Get value of ECSPI_CONREG_HT from a register value. +#define BG_ECSPI_CONREG_HT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_HT) >> BP_ECSPI_CONREG_HT) + +//! @brief Format value for bitfield ECSPI_CONREG_HT. +#define BF_ECSPI_CONREG_HT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_HT) & BM_ECSPI_CONREG_HT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HT field to a new value. +#define BW_ECSPI_CONREG_HT(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_HT) | BF_ECSPI_CONREG_HT(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field XCH[2] (RW) + * + * SPI Exchange Bit. This bit applies only to channels configured in Master mode (CHANNEL MODE = 1). + * If the Start Mode Control (SMC) bit is cleared, writing a 1 to this bit starts one SPI burst or + * multiple SPI bursts according to the SPI SS Wave Form Select (SS_CTL). The XCH bit remains set + * while either the data exchange is in progress, or when the ECSPI is waiting for an active input + * if SPIRDY is enabled through DRCTL. This bit is cleared automatically when all data in the TXFIFO + * and the shift register has been shifted out. + * + * Values: + * - 0 - Idle. + * - 1 - Initiates exchange (write) or busy (read). + */ +//@{ +#define BP_ECSPI_CONREG_XCH (2) //!< Bit position for ECSPI_CONREG_XCH. +#define BM_ECSPI_CONREG_XCH (0x00000004) //!< Bit mask for ECSPI_CONREG_XCH. + +//! @brief Get value of ECSPI_CONREG_XCH from a register value. +#define BG_ECSPI_CONREG_XCH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_XCH) >> BP_ECSPI_CONREG_XCH) + +//! @brief Format value for bitfield ECSPI_CONREG_XCH. +#define BF_ECSPI_CONREG_XCH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_XCH) & BM_ECSPI_CONREG_XCH) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the XCH field to a new value. +#define BW_ECSPI_CONREG_XCH(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_XCH) | BF_ECSPI_CONREG_XCH(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field SMC[3] (RW) + * + * Start Mode Control. This bit applies only to channels configured in Master mode (CHANNEL MODE = + * 1). It controls how the ECSPI starts a SPI burst, either through the SPI exchange bit, or + * immediately when the TXFIFO is written to. + * + * Values: + * - 0 - SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI + * burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer + * to XCH and SS_CTL descriptions. + * - 1 - Immediately starts a SPI burst when data is written in TXFIFO. + */ +//@{ +#define BP_ECSPI_CONREG_SMC (3) //!< Bit position for ECSPI_CONREG_SMC. +#define BM_ECSPI_CONREG_SMC (0x00000008) //!< Bit mask for ECSPI_CONREG_SMC. + +//! @brief Get value of ECSPI_CONREG_SMC from a register value. +#define BG_ECSPI_CONREG_SMC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_SMC) >> BP_ECSPI_CONREG_SMC) + +//! @brief Format value for bitfield ECSPI_CONREG_SMC. +#define BF_ECSPI_CONREG_SMC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_SMC) & BM_ECSPI_CONREG_SMC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SMC field to a new value. +#define BW_ECSPI_CONREG_SMC(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_SMC) | BF_ECSPI_CONREG_SMC(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field CHANNEL_MODE[7:4] (RW) + * + * SPI CHANNEL MODE selects the mode for each SPI channel. CHANNEL MODE[3] is for SPI channel 3. + * CHANNEL MODE[2] is for SPI channel 2. CHANNEL MODE[1] is for SPI channel 1. CHANNEL MODE[0] is + * for SPI channel 0. + * + * Values: + * - 0 - Slave mode. + * - 1 - Master mode. + */ +//@{ +#define BP_ECSPI_CONREG_CHANNEL_MODE (4) //!< Bit position for ECSPI_CONREG_CHANNEL_MODE. +#define BM_ECSPI_CONREG_CHANNEL_MODE (0x000000f0) //!< Bit mask for ECSPI_CONREG_CHANNEL_MODE. + +//! @brief Get value of ECSPI_CONREG_CHANNEL_MODE from a register value. +#define BG_ECSPI_CONREG_CHANNEL_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_CHANNEL_MODE) >> BP_ECSPI_CONREG_CHANNEL_MODE) + +//! @brief Format value for bitfield ECSPI_CONREG_CHANNEL_MODE. +#define BF_ECSPI_CONREG_CHANNEL_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_CHANNEL_MODE) & BM_ECSPI_CONREG_CHANNEL_MODE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHANNEL_MODE field to a new value. +#define BW_ECSPI_CONREG_CHANNEL_MODE(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_CHANNEL_MODE) | BF_ECSPI_CONREG_CHANNEL_MODE(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field POST_DIVIDER[11:8] (RW) + * + * SPI Post Divider. ECSPI uses a two-stage divider to generate the SPI clock. This field defines + * the post-divider of the reference clock using the equation: 2 n . + * + * Values: + * - 0000 - Divide by 1. + * - ... - + * - 0001 - Divide by 2. + * - 0010 - Divide by 4. + * - 1110 - Divide by 2 14 . + * - 1111 - Divide by 2 15 . + */ +//@{ +#define BP_ECSPI_CONREG_POST_DIVIDER (8) //!< Bit position for ECSPI_CONREG_POST_DIVIDER. +#define BM_ECSPI_CONREG_POST_DIVIDER (0x00000f00) //!< Bit mask for ECSPI_CONREG_POST_DIVIDER. + +//! @brief Get value of ECSPI_CONREG_POST_DIVIDER from a register value. +#define BG_ECSPI_CONREG_POST_DIVIDER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_POST_DIVIDER) >> BP_ECSPI_CONREG_POST_DIVIDER) + +//! @brief Format value for bitfield ECSPI_CONREG_POST_DIVIDER. +#define BF_ECSPI_CONREG_POST_DIVIDER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_POST_DIVIDER) & BM_ECSPI_CONREG_POST_DIVIDER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the POST_DIVIDER field to a new value. +#define BW_ECSPI_CONREG_POST_DIVIDER(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_POST_DIVIDER) | BF_ECSPI_CONREG_POST_DIVIDER(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field PRE_DIVIDER[15:12] (RW) + * + * SPI Pre Divider. ECSPI uses a two-stage divider to generate the SPI clock. This field defines the + * pre-divider of the reference clock. + * + * Values: + * - 0000 - Divide by 1. + * - ... - + * - 0001 - Divide by 2. + * - 0010 - Divide by 3. + * - 1101 - Divide by 14. + * - 1110 - Divide by 15. + * - 1111 - Divide by 16. + */ +//@{ +#define BP_ECSPI_CONREG_PRE_DIVIDER (12) //!< Bit position for ECSPI_CONREG_PRE_DIVIDER. +#define BM_ECSPI_CONREG_PRE_DIVIDER (0x0000f000) //!< Bit mask for ECSPI_CONREG_PRE_DIVIDER. + +//! @brief Get value of ECSPI_CONREG_PRE_DIVIDER from a register value. +#define BG_ECSPI_CONREG_PRE_DIVIDER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_PRE_DIVIDER) >> BP_ECSPI_CONREG_PRE_DIVIDER) + +//! @brief Format value for bitfield ECSPI_CONREG_PRE_DIVIDER. +#define BF_ECSPI_CONREG_PRE_DIVIDER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_PRE_DIVIDER) & BM_ECSPI_CONREG_PRE_DIVIDER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PRE_DIVIDER field to a new value. +#define BW_ECSPI_CONREG_PRE_DIVIDER(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_PRE_DIVIDER) | BF_ECSPI_CONREG_PRE_DIVIDER(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field DRCTL[17:16] (RW) + * + * SPI Data Ready Control. This field selects the utilization of the SPI_RDY signal in master mode. + * ECSPI checks this field before it starts an SPI burst. + * + * Values: + * - 00 - The SPI_RDY signal is a don't care. + * - 01 - Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + * - 10 - Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + * - 11 - Reserved. + */ +//@{ +#define BP_ECSPI_CONREG_DRCTL (16) //!< Bit position for ECSPI_CONREG_DRCTL. +#define BM_ECSPI_CONREG_DRCTL (0x00030000) //!< Bit mask for ECSPI_CONREG_DRCTL. + +//! @brief Get value of ECSPI_CONREG_DRCTL from a register value. +#define BG_ECSPI_CONREG_DRCTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_DRCTL) >> BP_ECSPI_CONREG_DRCTL) + +//! @brief Format value for bitfield ECSPI_CONREG_DRCTL. +#define BF_ECSPI_CONREG_DRCTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_DRCTL) & BM_ECSPI_CONREG_DRCTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DRCTL field to a new value. +#define BW_ECSPI_CONREG_DRCTL(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_DRCTL) | BF_ECSPI_CONREG_DRCTL(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field CHANNEL_SELECT[19:18] (RW) + * + * SPI CHANNEL SELECT bits. Select one of four external SPI Master/Slave Devices. In master mode, + * these two bits select the external slave devices by asserting the Chip Select (SSn) outputs. Only + * the selected Chip Select (SSn) signal can be active at a given time; the remaining three signals + * will be negated. + * + * Values: + * - 00 - Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + * - 01 - Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + * - 10 - Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + * - 11 - Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + */ +//@{ +#define BP_ECSPI_CONREG_CHANNEL_SELECT (18) //!< Bit position for ECSPI_CONREG_CHANNEL_SELECT. +#define BM_ECSPI_CONREG_CHANNEL_SELECT (0x000c0000) //!< Bit mask for ECSPI_CONREG_CHANNEL_SELECT. + +//! @brief Get value of ECSPI_CONREG_CHANNEL_SELECT from a register value. +#define BG_ECSPI_CONREG_CHANNEL_SELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_CHANNEL_SELECT) >> BP_ECSPI_CONREG_CHANNEL_SELECT) + +//! @brief Format value for bitfield ECSPI_CONREG_CHANNEL_SELECT. +#define BF_ECSPI_CONREG_CHANNEL_SELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_CHANNEL_SELECT) & BM_ECSPI_CONREG_CHANNEL_SELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHANNEL_SELECT field to a new value. +#define BW_ECSPI_CONREG_CHANNEL_SELECT(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_CHANNEL_SELECT) | BF_ECSPI_CONREG_CHANNEL_SELECT(v))) +#endif +//@} + +/*! @name Register ECSPI_CONREG, field BURST_LENGTH[31:20] (RW) + * + * Burst Length. This field defines the length of a SPI burst to be transferred. The Chip Select + * (SS) will remain asserted until all bits in a SPI burst are shifted out. A maximum of 2^12 bits + * can be transferred in a single SPI burst. In master mode, it controls the number of bits per SPI + * burst. Since the shift register always loads 32-bit data from transmit FIFO, only the n least- + * significant (n = BURST LENGTH + 1) will be shifted out. The remaining bits will be ignored. In + * slave mode, only when SS_CTL is cleared, this field will take effect in the transfer. Number of + * Valid Bits in a SPI burst. + * + * Values: + * - 0x000 - A SPI burst contains the 1 LSB in a word. + * - ... - + * - ... - + * - 0x001 - A SPI burst contains the 2 LSB in a word. + * - 0x002 - A SPI burst contains the 3 LSB in a word. + * - 0x01F - A SPI burst contains all 32 bits in a word. + * - 0x020 - A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + * - 0x021 - A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + * - 0xFFE - A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + * - 0xFFF - A SPI burst contains 2^7 words. + */ +//@{ +#define BP_ECSPI_CONREG_BURST_LENGTH (20) //!< Bit position for ECSPI_CONREG_BURST_LENGTH. +#define BM_ECSPI_CONREG_BURST_LENGTH (0xfff00000) //!< Bit mask for ECSPI_CONREG_BURST_LENGTH. + +//! @brief Get value of ECSPI_CONREG_BURST_LENGTH from a register value. +#define BG_ECSPI_CONREG_BURST_LENGTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONREG_BURST_LENGTH) >> BP_ECSPI_CONREG_BURST_LENGTH) + +//! @brief Format value for bitfield ECSPI_CONREG_BURST_LENGTH. +#define BF_ECSPI_CONREG_BURST_LENGTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONREG_BURST_LENGTH) & BM_ECSPI_CONREG_BURST_LENGTH) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BURST_LENGTH field to a new value. +#define BW_ECSPI_CONREG_BURST_LENGTH(x, v) (HW_ECSPI_CONREG_WR(x, (HW_ECSPI_CONREG_RD(x) & ~BM_ECSPI_CONREG_BURST_LENGTH) | BF_ECSPI_CONREG_BURST_LENGTH(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_CONFIGREG - Config Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_CONFIGREG - Config Register (RW) + * + * Reset value: 0x00000000 + * + * The Config Register (ECSPI_CONFIGREG) allows software to configure each SPI channel, configure + * its operating modes, specify the phase and polarity of the clock, configure the Chip Select (SS), + * and define the HT transfer length. Note, HT mode is not supported by this product. + */ +typedef union _hw_ecspi_configreg +{ + reg32_t U; + struct _hw_ecspi_configreg_bitfields + { + unsigned SCLK_PHA : 4; //!< [3:0] SPI Clock/Data Phase Control. + unsigned SCLK_POL : 4; //!< [7:4] SPI Clock Polarity Control. + unsigned SS_CTL : 4; //!< [11:8] SPI SS Wave Form Select. + unsigned SS_POL : 4; //!< [15:12] SPI SS Polarity Select. + unsigned DATA_CTL : 4; //!< [19:16] DATA CTL. + unsigned SCLK_CTL : 4; //!< [23:20] SCLK CTL. + unsigned HT_LENGTH : 5; //!< [28:24] HT LENGTH. + unsigned RESERVED0 : 3; //!< [31:29] Reserved + } B; +} hw_ecspi_configreg_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_CONFIGREG register + */ +//@{ +#define HW_ECSPI_CONFIGREG_ADDR(x) (REGS_ECSPI_BASE(x) + 0xc) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_CONFIGREG(x) (*(volatile hw_ecspi_configreg_t *) HW_ECSPI_CONFIGREG_ADDR(x)) +#define HW_ECSPI_CONFIGREG_RD(x) (HW_ECSPI_CONFIGREG(x).U) +#define HW_ECSPI_CONFIGREG_WR(x, v) (HW_ECSPI_CONFIGREG(x).U = (v)) +#define HW_ECSPI_CONFIGREG_SET(x, v) (HW_ECSPI_CONFIGREG_WR(x, HW_ECSPI_CONFIGREG_RD(x) | (v))) +#define HW_ECSPI_CONFIGREG_CLR(x, v) (HW_ECSPI_CONFIGREG_WR(x, HW_ECSPI_CONFIGREG_RD(x) & ~(v))) +#define HW_ECSPI_CONFIGREG_TOG(x, v) (HW_ECSPI_CONFIGREG_WR(x, HW_ECSPI_CONFIGREG_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ECSPI_CONFIGREG bitfields + */ + +/*! @name Register ECSPI_CONFIGREG, field SCLK_PHA[3:0] (RW) + * + * SPI Clock/Data Phase Control. This field controls the clock/data phase relationship. See for more + * information. SCLK PHA[3] is for SPI channel 3. SCLK PHA[2] is for SPI channel 2. SCLK PHA[1] is + * for SPI channel 1. SCLK PHA[0] is for SPI channel 0. + * + * Values: + * - 0 - Phase 0 operation. + * - 1 - Phase 1 operation. + */ +//@{ +#define BP_ECSPI_CONFIGREG_SCLK_PHA (0) //!< Bit position for ECSPI_CONFIGREG_SCLK_PHA. +#define BM_ECSPI_CONFIGREG_SCLK_PHA (0x0000000f) //!< Bit mask for ECSPI_CONFIGREG_SCLK_PHA. + +//! @brief Get value of ECSPI_CONFIGREG_SCLK_PHA from a register value. +#define BG_ECSPI_CONFIGREG_SCLK_PHA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONFIGREG_SCLK_PHA) >> BP_ECSPI_CONFIGREG_SCLK_PHA) + +//! @brief Format value for bitfield ECSPI_CONFIGREG_SCLK_PHA. +#define BF_ECSPI_CONFIGREG_SCLK_PHA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONFIGREG_SCLK_PHA) & BM_ECSPI_CONFIGREG_SCLK_PHA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SCLK_PHA field to a new value. +#define BW_ECSPI_CONFIGREG_SCLK_PHA(x, v) (HW_ECSPI_CONFIGREG_WR(x, (HW_ECSPI_CONFIGREG_RD(x) & ~BM_ECSPI_CONFIGREG_SCLK_PHA) | BF_ECSPI_CONFIGREG_SCLK_PHA(v))) +#endif +//@} + +/*! @name Register ECSPI_CONFIGREG, field SCLK_POL[7:4] (RW) + * + * SPI Clock Polarity Control. This field controls the polarity of the SCLK signal. See for more + * information. SCLK_POL[3] is for SPI channel 3. SCLK_POL[2] is for SPI channel 2. SCLK_POL[1] is + * for SPI channel 1. SCLK_POL[0] is for SPI channel 0. + * + * Values: + * - 0 - Active high polarity (0 = Idle). + * - 1 - Active low polarity (1 = Idle). + */ +//@{ +#define BP_ECSPI_CONFIGREG_SCLK_POL (4) //!< Bit position for ECSPI_CONFIGREG_SCLK_POL. +#define BM_ECSPI_CONFIGREG_SCLK_POL (0x000000f0) //!< Bit mask for ECSPI_CONFIGREG_SCLK_POL. + +//! @brief Get value of ECSPI_CONFIGREG_SCLK_POL from a register value. +#define BG_ECSPI_CONFIGREG_SCLK_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONFIGREG_SCLK_POL) >> BP_ECSPI_CONFIGREG_SCLK_POL) + +//! @brief Format value for bitfield ECSPI_CONFIGREG_SCLK_POL. +#define BF_ECSPI_CONFIGREG_SCLK_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONFIGREG_SCLK_POL) & BM_ECSPI_CONFIGREG_SCLK_POL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SCLK_POL field to a new value. +#define BW_ECSPI_CONFIGREG_SCLK_POL(x, v) (HW_ECSPI_CONFIGREG_WR(x, (HW_ECSPI_CONFIGREG_RD(x) & ~BM_ECSPI_CONFIGREG_SCLK_POL) | BF_ECSPI_CONFIGREG_SCLK_POL(v))) +#endif +//@} + +/*! @name Register ECSPI_CONFIGREG, field SS_CTL[11:8] (RW) + * + * SPI SS Wave Form Select. In master mode, this field controls the output wave form of the Chip + * Select (SS) signal when the SMC (Start Mode Control) bit is cleared. The SS_CTL are ignored if + * the SMC bit is set. SS CTL[3] is for SPI channel 3. SS CTL[2] is for SPI channel 2. SS CTL[1] is + * for SPI channel 1. SS CTL[0] is for SPI channel 0. In slave mode, this bit controls when the SPI + * burst is completed. An SPI burst is completed by the Chip Select (SS) signal edges. (SSPOL = 0: + * rising edge; SSPOL = 1: falling edge) The RXFIFO is advanced whenever a Chip Select (SS) signal + * edge is detected or the shift register contains 32-bits of valid data. + * + * Values: + * - 0 - In master mode - only one SPI burst will be transmitted. + * - 0 - In slave mode - an SPI burst is completed when the number of bits received in the shift register is + * equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of + * the first received word are valid. All bits subsequent to the first received word in RXFIFO + * are valid. + * - 1 - In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be + * transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + * - 1 - In slave mode - an SPI burst is completed by the Chip Select (SS) signal edges. (SSPOL = 0: rising + * edge; SSPOL = 1: falling edge) The RXFIFO is advanced whenever a Chip Select (SS) signal edge + * is detected or the shift register contains 32-bits of valid data. + */ +//@{ +#define BP_ECSPI_CONFIGREG_SS_CTL (8) //!< Bit position for ECSPI_CONFIGREG_SS_CTL. +#define BM_ECSPI_CONFIGREG_SS_CTL (0x00000f00) //!< Bit mask for ECSPI_CONFIGREG_SS_CTL. + +//! @brief Get value of ECSPI_CONFIGREG_SS_CTL from a register value. +#define BG_ECSPI_CONFIGREG_SS_CTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONFIGREG_SS_CTL) >> BP_ECSPI_CONFIGREG_SS_CTL) + +//! @brief Format value for bitfield ECSPI_CONFIGREG_SS_CTL. +#define BF_ECSPI_CONFIGREG_SS_CTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONFIGREG_SS_CTL) & BM_ECSPI_CONFIGREG_SS_CTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SS_CTL field to a new value. +#define BW_ECSPI_CONFIGREG_SS_CTL(x, v) (HW_ECSPI_CONFIGREG_WR(x, (HW_ECSPI_CONFIGREG_RD(x) & ~BM_ECSPI_CONFIGREG_SS_CTL) | BF_ECSPI_CONFIGREG_SS_CTL(v))) +#endif +//@} + +/*! @name Register ECSPI_CONFIGREG, field SS_POL[15:12] (RW) + * + * SPI SS Polarity Select. In both Master and Slave modes, this field selects the polarity of the + * Chip Select (SS) signal. SS POL[3] is for SPI channel 3. SS POL[2] is for SPI channel 2. SS + * POL[1] is for SPI channel 1. SS POL[0] is for SPI channel 0. + * + * Values: + * - 0 - Active low. + * - 1 - Active high. + */ +//@{ +#define BP_ECSPI_CONFIGREG_SS_POL (12) //!< Bit position for ECSPI_CONFIGREG_SS_POL. +#define BM_ECSPI_CONFIGREG_SS_POL (0x0000f000) //!< Bit mask for ECSPI_CONFIGREG_SS_POL. + +//! @brief Get value of ECSPI_CONFIGREG_SS_POL from a register value. +#define BG_ECSPI_CONFIGREG_SS_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONFIGREG_SS_POL) >> BP_ECSPI_CONFIGREG_SS_POL) + +//! @brief Format value for bitfield ECSPI_CONFIGREG_SS_POL. +#define BF_ECSPI_CONFIGREG_SS_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONFIGREG_SS_POL) & BM_ECSPI_CONFIGREG_SS_POL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SS_POL field to a new value. +#define BW_ECSPI_CONFIGREG_SS_POL(x, v) (HW_ECSPI_CONFIGREG_WR(x, (HW_ECSPI_CONFIGREG_RD(x) & ~BM_ECSPI_CONFIGREG_SS_POL) | BF_ECSPI_CONFIGREG_SS_POL(v))) +#endif +//@} + +/*! @name Register ECSPI_CONFIGREG, field DATA_CTL[19:16] (RW) + * + * DATA CTL. This field controls inactive state of the data line for each SPI channel. DATA CTL[3] + * is for SPI channel 3. DATA CTL[2] is for SPI channel 2. DATA CTL[1] is for SPI channel 1. DATA + * CTL[0] is for SPI channel 0. + * + * Values: + * - 0 - Stay high. + * - 1 - Stay low. + */ +//@{ +#define BP_ECSPI_CONFIGREG_DATA_CTL (16) //!< Bit position for ECSPI_CONFIGREG_DATA_CTL. +#define BM_ECSPI_CONFIGREG_DATA_CTL (0x000f0000) //!< Bit mask for ECSPI_CONFIGREG_DATA_CTL. + +//! @brief Get value of ECSPI_CONFIGREG_DATA_CTL from a register value. +#define BG_ECSPI_CONFIGREG_DATA_CTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONFIGREG_DATA_CTL) >> BP_ECSPI_CONFIGREG_DATA_CTL) + +//! @brief Format value for bitfield ECSPI_CONFIGREG_DATA_CTL. +#define BF_ECSPI_CONFIGREG_DATA_CTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONFIGREG_DATA_CTL) & BM_ECSPI_CONFIGREG_DATA_CTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA_CTL field to a new value. +#define BW_ECSPI_CONFIGREG_DATA_CTL(x, v) (HW_ECSPI_CONFIGREG_WR(x, (HW_ECSPI_CONFIGREG_RD(x) & ~BM_ECSPI_CONFIGREG_DATA_CTL) | BF_ECSPI_CONFIGREG_DATA_CTL(v))) +#endif +//@} + +/*! @name Register ECSPI_CONFIGREG, field SCLK_CTL[23:20] (RW) + * + * SCLK CTL. This field controls the inactive state of SCLK for each SPI channel. SCLK CTL[3] is for + * SPI channel 3. SCLK CTL[2] is for SPI channel 2. SCLK CTL[1] is for SPI channel 1. SCLK CTL[0] is + * for SPI channel 0. + * + * Values: + * - 0 - Stay low. + * - 1 - Stay high. + */ +//@{ +#define BP_ECSPI_CONFIGREG_SCLK_CTL (20) //!< Bit position for ECSPI_CONFIGREG_SCLK_CTL. +#define BM_ECSPI_CONFIGREG_SCLK_CTL (0x00f00000) //!< Bit mask for ECSPI_CONFIGREG_SCLK_CTL. + +//! @brief Get value of ECSPI_CONFIGREG_SCLK_CTL from a register value. +#define BG_ECSPI_CONFIGREG_SCLK_CTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONFIGREG_SCLK_CTL) >> BP_ECSPI_CONFIGREG_SCLK_CTL) + +//! @brief Format value for bitfield ECSPI_CONFIGREG_SCLK_CTL. +#define BF_ECSPI_CONFIGREG_SCLK_CTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONFIGREG_SCLK_CTL) & BM_ECSPI_CONFIGREG_SCLK_CTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SCLK_CTL field to a new value. +#define BW_ECSPI_CONFIGREG_SCLK_CTL(x, v) (HW_ECSPI_CONFIGREG_WR(x, (HW_ECSPI_CONFIGREG_RD(x) & ~BM_ECSPI_CONFIGREG_SCLK_CTL) | BF_ECSPI_CONFIGREG_SCLK_CTL(v))) +#endif +//@} + +/*! @name Register ECSPI_CONFIGREG, field HT_LENGTH[28:24] (RW) + * + * HT LENGTH. This field defines the message length in HT Mode. Note, HT mode is not supported by + * this product. The length in bits of one message is (HT LENGTH + 1). + */ +//@{ +#define BP_ECSPI_CONFIGREG_HT_LENGTH (24) //!< Bit position for ECSPI_CONFIGREG_HT_LENGTH. +#define BM_ECSPI_CONFIGREG_HT_LENGTH (0x1f000000) //!< Bit mask for ECSPI_CONFIGREG_HT_LENGTH. + +//! @brief Get value of ECSPI_CONFIGREG_HT_LENGTH from a register value. +#define BG_ECSPI_CONFIGREG_HT_LENGTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_CONFIGREG_HT_LENGTH) >> BP_ECSPI_CONFIGREG_HT_LENGTH) + +//! @brief Format value for bitfield ECSPI_CONFIGREG_HT_LENGTH. +#define BF_ECSPI_CONFIGREG_HT_LENGTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_CONFIGREG_HT_LENGTH) & BM_ECSPI_CONFIGREG_HT_LENGTH) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HT_LENGTH field to a new value. +#define BW_ECSPI_CONFIGREG_HT_LENGTH(x, v) (HW_ECSPI_CONFIGREG_WR(x, (HW_ECSPI_CONFIGREG_RD(x) & ~BM_ECSPI_CONFIGREG_HT_LENGTH) | BF_ECSPI_CONFIGREG_HT_LENGTH(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_INTREG - Interrupt Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_INTREG - Interrupt Control Register (RW) + * + * Reset value: 0x00000000 + * + * The Interrupt Control Register (ECSPI_INTREG) enables the generation of interrupts to the host + * processor. If the ECSPI is disabled, this register reads zero. + */ +typedef union _hw_ecspi_intreg +{ + reg32_t U; + struct _hw_ecspi_intreg_bitfields + { + unsigned TEEN : 1; //!< [0] TXFIFO Empty Interrupt enable. + unsigned TDREN : 1; //!< [1] TXFIFO Data Request Interrupt enable. + unsigned TFEN : 1; //!< [2] TXFIFO Full Interrupt enable. + unsigned RREN : 1; //!< [3] RXFIFO Ready Interrupt enable. + unsigned RDREN : 1; //!< [4] RXFIFO Data Request Interrupt enable. + unsigned RFEN : 1; //!< [5] RXFIFO Full Interrupt enable. + unsigned ROEN : 1; //!< [6] RXFIFO Overflow Interrupt enable. + unsigned TCEN : 1; //!< [7] Transfer Completed Interrupt enable. + unsigned RESERVED0 : 24; //!< [31:8] Reserved + } B; +} hw_ecspi_intreg_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_INTREG register + */ +//@{ +#define HW_ECSPI_INTREG_ADDR(x) (REGS_ECSPI_BASE(x) + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_INTREG(x) (*(volatile hw_ecspi_intreg_t *) HW_ECSPI_INTREG_ADDR(x)) +#define HW_ECSPI_INTREG_RD(x) (HW_ECSPI_INTREG(x).U) +#define HW_ECSPI_INTREG_WR(x, v) (HW_ECSPI_INTREG(x).U = (v)) +#define HW_ECSPI_INTREG_SET(x, v) (HW_ECSPI_INTREG_WR(x, HW_ECSPI_INTREG_RD(x) | (v))) +#define HW_ECSPI_INTREG_CLR(x, v) (HW_ECSPI_INTREG_WR(x, HW_ECSPI_INTREG_RD(x) & ~(v))) +#define HW_ECSPI_INTREG_TOG(x, v) (HW_ECSPI_INTREG_WR(x, HW_ECSPI_INTREG_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ECSPI_INTREG bitfields + */ + +/*! @name Register ECSPI_INTREG, field TEEN[0] (RW) + * + * TXFIFO Empty Interrupt enable. This bit enables the TXFIFO Empty Interrupt. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_INTREG_TEEN (0) //!< Bit position for ECSPI_INTREG_TEEN. +#define BM_ECSPI_INTREG_TEEN (0x00000001) //!< Bit mask for ECSPI_INTREG_TEEN. + +//! @brief Get value of ECSPI_INTREG_TEEN from a register value. +#define BG_ECSPI_INTREG_TEEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_INTREG_TEEN) >> BP_ECSPI_INTREG_TEEN) + +//! @brief Format value for bitfield ECSPI_INTREG_TEEN. +#define BF_ECSPI_INTREG_TEEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_INTREG_TEEN) & BM_ECSPI_INTREG_TEEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TEEN field to a new value. +#define BW_ECSPI_INTREG_TEEN(x, v) (HW_ECSPI_INTREG_WR(x, (HW_ECSPI_INTREG_RD(x) & ~BM_ECSPI_INTREG_TEEN) | BF_ECSPI_INTREG_TEEN(v))) +#endif +//@} + +/*! @name Register ECSPI_INTREG, field TDREN[1] (RW) + * + * TXFIFO Data Request Interrupt enable. This bit enables the TXFIFO Data Request Interrupt when the + * number of data entries in the TXFIFO is less than or equal to TX_THRESHOLD. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_INTREG_TDREN (1) //!< Bit position for ECSPI_INTREG_TDREN. +#define BM_ECSPI_INTREG_TDREN (0x00000002) //!< Bit mask for ECSPI_INTREG_TDREN. + +//! @brief Get value of ECSPI_INTREG_TDREN from a register value. +#define BG_ECSPI_INTREG_TDREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_INTREG_TDREN) >> BP_ECSPI_INTREG_TDREN) + +//! @brief Format value for bitfield ECSPI_INTREG_TDREN. +#define BF_ECSPI_INTREG_TDREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_INTREG_TDREN) & BM_ECSPI_INTREG_TDREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TDREN field to a new value. +#define BW_ECSPI_INTREG_TDREN(x, v) (HW_ECSPI_INTREG_WR(x, (HW_ECSPI_INTREG_RD(x) & ~BM_ECSPI_INTREG_TDREN) | BF_ECSPI_INTREG_TDREN(v))) +#endif +//@} + +/*! @name Register ECSPI_INTREG, field TFEN[2] (RW) + * + * TXFIFO Full Interrupt enable. This bit enables the TXFIFO Full Interrupt. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_INTREG_TFEN (2) //!< Bit position for ECSPI_INTREG_TFEN. +#define BM_ECSPI_INTREG_TFEN (0x00000004) //!< Bit mask for ECSPI_INTREG_TFEN. + +//! @brief Get value of ECSPI_INTREG_TFEN from a register value. +#define BG_ECSPI_INTREG_TFEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_INTREG_TFEN) >> BP_ECSPI_INTREG_TFEN) + +//! @brief Format value for bitfield ECSPI_INTREG_TFEN. +#define BF_ECSPI_INTREG_TFEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_INTREG_TFEN) & BM_ECSPI_INTREG_TFEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TFEN field to a new value. +#define BW_ECSPI_INTREG_TFEN(x, v) (HW_ECSPI_INTREG_WR(x, (HW_ECSPI_INTREG_RD(x) & ~BM_ECSPI_INTREG_TFEN) | BF_ECSPI_INTREG_TFEN(v))) +#endif +//@} + +/*! @name Register ECSPI_INTREG, field RREN[3] (RW) + * + * RXFIFO Ready Interrupt enable. This bit enables the RXFIFO Ready Interrupt. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_INTREG_RREN (3) //!< Bit position for ECSPI_INTREG_RREN. +#define BM_ECSPI_INTREG_RREN (0x00000008) //!< Bit mask for ECSPI_INTREG_RREN. + +//! @brief Get value of ECSPI_INTREG_RREN from a register value. +#define BG_ECSPI_INTREG_RREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_INTREG_RREN) >> BP_ECSPI_INTREG_RREN) + +//! @brief Format value for bitfield ECSPI_INTREG_RREN. +#define BF_ECSPI_INTREG_RREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_INTREG_RREN) & BM_ECSPI_INTREG_RREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RREN field to a new value. +#define BW_ECSPI_INTREG_RREN(x, v) (HW_ECSPI_INTREG_WR(x, (HW_ECSPI_INTREG_RD(x) & ~BM_ECSPI_INTREG_RREN) | BF_ECSPI_INTREG_RREN(v))) +#endif +//@} + +/*! @name Register ECSPI_INTREG, field RDREN[4] (RW) + * + * RXFIFO Data Request Interrupt enable. This bit enables the RXFIFO Data Request Interrupt when the + * number of data entries in the RXFIFO is greater than RX_THRESHOLD. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_INTREG_RDREN (4) //!< Bit position for ECSPI_INTREG_RDREN. +#define BM_ECSPI_INTREG_RDREN (0x00000010) //!< Bit mask for ECSPI_INTREG_RDREN. + +//! @brief Get value of ECSPI_INTREG_RDREN from a register value. +#define BG_ECSPI_INTREG_RDREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_INTREG_RDREN) >> BP_ECSPI_INTREG_RDREN) + +//! @brief Format value for bitfield ECSPI_INTREG_RDREN. +#define BF_ECSPI_INTREG_RDREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_INTREG_RDREN) & BM_ECSPI_INTREG_RDREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RDREN field to a new value. +#define BW_ECSPI_INTREG_RDREN(x, v) (HW_ECSPI_INTREG_WR(x, (HW_ECSPI_INTREG_RD(x) & ~BM_ECSPI_INTREG_RDREN) | BF_ECSPI_INTREG_RDREN(v))) +#endif +//@} + +/*! @name Register ECSPI_INTREG, field RFEN[5] (RW) + * + * RXFIFO Full Interrupt enable. This bit enables the RXFIFO Full Interrupt. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_INTREG_RFEN (5) //!< Bit position for ECSPI_INTREG_RFEN. +#define BM_ECSPI_INTREG_RFEN (0x00000020) //!< Bit mask for ECSPI_INTREG_RFEN. + +//! @brief Get value of ECSPI_INTREG_RFEN from a register value. +#define BG_ECSPI_INTREG_RFEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_INTREG_RFEN) >> BP_ECSPI_INTREG_RFEN) + +//! @brief Format value for bitfield ECSPI_INTREG_RFEN. +#define BF_ECSPI_INTREG_RFEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_INTREG_RFEN) & BM_ECSPI_INTREG_RFEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RFEN field to a new value. +#define BW_ECSPI_INTREG_RFEN(x, v) (HW_ECSPI_INTREG_WR(x, (HW_ECSPI_INTREG_RD(x) & ~BM_ECSPI_INTREG_RFEN) | BF_ECSPI_INTREG_RFEN(v))) +#endif +//@} + +/*! @name Register ECSPI_INTREG, field ROEN[6] (RW) + * + * RXFIFO Overflow Interrupt enable. This bit enables the RXFIFO Overflow Interrupt. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_INTREG_ROEN (6) //!< Bit position for ECSPI_INTREG_ROEN. +#define BM_ECSPI_INTREG_ROEN (0x00000040) //!< Bit mask for ECSPI_INTREG_ROEN. + +//! @brief Get value of ECSPI_INTREG_ROEN from a register value. +#define BG_ECSPI_INTREG_ROEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_INTREG_ROEN) >> BP_ECSPI_INTREG_ROEN) + +//! @brief Format value for bitfield ECSPI_INTREG_ROEN. +#define BF_ECSPI_INTREG_ROEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_INTREG_ROEN) & BM_ECSPI_INTREG_ROEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ROEN field to a new value. +#define BW_ECSPI_INTREG_ROEN(x, v) (HW_ECSPI_INTREG_WR(x, (HW_ECSPI_INTREG_RD(x) & ~BM_ECSPI_INTREG_ROEN) | BF_ECSPI_INTREG_ROEN(v))) +#endif +//@} + +/*! @name Register ECSPI_INTREG, field TCEN[7] (RW) + * + * Transfer Completed Interrupt enable. This bit enables the Transfer Completed Interrupt. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_INTREG_TCEN (7) //!< Bit position for ECSPI_INTREG_TCEN. +#define BM_ECSPI_INTREG_TCEN (0x00000080) //!< Bit mask for ECSPI_INTREG_TCEN. + +//! @brief Get value of ECSPI_INTREG_TCEN from a register value. +#define BG_ECSPI_INTREG_TCEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_INTREG_TCEN) >> BP_ECSPI_INTREG_TCEN) + +//! @brief Format value for bitfield ECSPI_INTREG_TCEN. +#define BF_ECSPI_INTREG_TCEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_INTREG_TCEN) & BM_ECSPI_INTREG_TCEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TCEN field to a new value. +#define BW_ECSPI_INTREG_TCEN(x, v) (HW_ECSPI_INTREG_WR(x, (HW_ECSPI_INTREG_RD(x) & ~BM_ECSPI_INTREG_TCEN) | BF_ECSPI_INTREG_TCEN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_DMAREG - DMA Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_DMAREG - DMA Control Register (RW) + * + * Reset value: 0x00000000 + * + * The Direct Memory Access Control Register (ECSPI_DMAREG) provides software a way to use an on- + * chip DMA controller for ECSPI data. Internal DMA request signals enable direct data transfers + * between the ECSPI FIFOs and system memory. The ECSPI sends out DMA requests when the appropriate + * FIFO conditions are matched. If the ECSPI is disabled, this register is read as 0. + */ +typedef union _hw_ecspi_dmareg +{ + reg32_t U; + struct _hw_ecspi_dmareg_bitfields + { + unsigned TX_THRESHOLD : 6; //!< [5:0] TX THRESHOLD. + unsigned RESERVED0 : 1; //!< [6] Reserved + unsigned TEDEN : 1; //!< [7] TXFIFO Empty DMA Request Enable. + unsigned RESERVED1 : 8; //!< [15:8] Reserved + unsigned RX_THRESHOLD : 6; //!< [21:16] RX THRESHOLD. + unsigned RESERVED2 : 1; //!< [22] Reserved + unsigned RXDEN : 1; //!< [23] RXFIFO DMA Request Enable. + unsigned RX_DMA_LENGTH : 6; //!< [29:24] RX DMA LENGTH. + unsigned RESERVED3 : 1; //!< [30] Reserved + unsigned RXTDEN : 1; //!< [31] RXFIFO TAIL DMA Request Enable. + } B; +} hw_ecspi_dmareg_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_DMAREG register + */ +//@{ +#define HW_ECSPI_DMAREG_ADDR(x) (REGS_ECSPI_BASE(x) + 0x14) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_DMAREG(x) (*(volatile hw_ecspi_dmareg_t *) HW_ECSPI_DMAREG_ADDR(x)) +#define HW_ECSPI_DMAREG_RD(x) (HW_ECSPI_DMAREG(x).U) +#define HW_ECSPI_DMAREG_WR(x, v) (HW_ECSPI_DMAREG(x).U = (v)) +#define HW_ECSPI_DMAREG_SET(x, v) (HW_ECSPI_DMAREG_WR(x, HW_ECSPI_DMAREG_RD(x) | (v))) +#define HW_ECSPI_DMAREG_CLR(x, v) (HW_ECSPI_DMAREG_WR(x, HW_ECSPI_DMAREG_RD(x) & ~(v))) +#define HW_ECSPI_DMAREG_TOG(x, v) (HW_ECSPI_DMAREG_WR(x, HW_ECSPI_DMAREG_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ECSPI_DMAREG bitfields + */ + +/*! @name Register ECSPI_DMAREG, field TX_THRESHOLD[5:0] (RW) + * + * TX THRESHOLD. This field defines the FIFO threshold that triggers a TX DMA/INT request. A TX + * DMA/INT request is issued when the number of data entries in the TXFIFO is greater than + * TX_THRESHOLD. + */ +//@{ +#define BP_ECSPI_DMAREG_TX_THRESHOLD (0) //!< Bit position for ECSPI_DMAREG_TX_THRESHOLD. +#define BM_ECSPI_DMAREG_TX_THRESHOLD (0x0000003f) //!< Bit mask for ECSPI_DMAREG_TX_THRESHOLD. + +//! @brief Get value of ECSPI_DMAREG_TX_THRESHOLD from a register value. +#define BG_ECSPI_DMAREG_TX_THRESHOLD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_DMAREG_TX_THRESHOLD) >> BP_ECSPI_DMAREG_TX_THRESHOLD) + +//! @brief Format value for bitfield ECSPI_DMAREG_TX_THRESHOLD. +#define BF_ECSPI_DMAREG_TX_THRESHOLD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_DMAREG_TX_THRESHOLD) & BM_ECSPI_DMAREG_TX_THRESHOLD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TX_THRESHOLD field to a new value. +#define BW_ECSPI_DMAREG_TX_THRESHOLD(x, v) (HW_ECSPI_DMAREG_WR(x, (HW_ECSPI_DMAREG_RD(x) & ~BM_ECSPI_DMAREG_TX_THRESHOLD) | BF_ECSPI_DMAREG_TX_THRESHOLD(v))) +#endif +//@} + +/*! @name Register ECSPI_DMAREG, field TEDEN[7] (RW) + * + * TXFIFO Empty DMA Request Enable. This bit enables/disables the TXFIFO Empty DMA Request. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_DMAREG_TEDEN (7) //!< Bit position for ECSPI_DMAREG_TEDEN. +#define BM_ECSPI_DMAREG_TEDEN (0x00000080) //!< Bit mask for ECSPI_DMAREG_TEDEN. + +//! @brief Get value of ECSPI_DMAREG_TEDEN from a register value. +#define BG_ECSPI_DMAREG_TEDEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_DMAREG_TEDEN) >> BP_ECSPI_DMAREG_TEDEN) + +//! @brief Format value for bitfield ECSPI_DMAREG_TEDEN. +#define BF_ECSPI_DMAREG_TEDEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_DMAREG_TEDEN) & BM_ECSPI_DMAREG_TEDEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TEDEN field to a new value. +#define BW_ECSPI_DMAREG_TEDEN(x, v) (HW_ECSPI_DMAREG_WR(x, (HW_ECSPI_DMAREG_RD(x) & ~BM_ECSPI_DMAREG_TEDEN) | BF_ECSPI_DMAREG_TEDEN(v))) +#endif +//@} + +/*! @name Register ECSPI_DMAREG, field RX_THRESHOLD[21:16] (RW) + * + * RX THRESHOLD. This field defines the FIFO threshold that triggers a RX DMA/INT request. A RX + * DMA/INT request is issued when the number of data entries in the RXFIFO is greater than + * RX_THRESHOLD. + */ +//@{ +#define BP_ECSPI_DMAREG_RX_THRESHOLD (16) //!< Bit position for ECSPI_DMAREG_RX_THRESHOLD. +#define BM_ECSPI_DMAREG_RX_THRESHOLD (0x003f0000) //!< Bit mask for ECSPI_DMAREG_RX_THRESHOLD. + +//! @brief Get value of ECSPI_DMAREG_RX_THRESHOLD from a register value. +#define BG_ECSPI_DMAREG_RX_THRESHOLD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_DMAREG_RX_THRESHOLD) >> BP_ECSPI_DMAREG_RX_THRESHOLD) + +//! @brief Format value for bitfield ECSPI_DMAREG_RX_THRESHOLD. +#define BF_ECSPI_DMAREG_RX_THRESHOLD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_DMAREG_RX_THRESHOLD) & BM_ECSPI_DMAREG_RX_THRESHOLD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RX_THRESHOLD field to a new value. +#define BW_ECSPI_DMAREG_RX_THRESHOLD(x, v) (HW_ECSPI_DMAREG_WR(x, (HW_ECSPI_DMAREG_RD(x) & ~BM_ECSPI_DMAREG_RX_THRESHOLD) | BF_ECSPI_DMAREG_RX_THRESHOLD(v))) +#endif +//@} + +/*! @name Register ECSPI_DMAREG, field RXDEN[23] (RW) + * + * RXFIFO DMA Request Enable. This bit enables/disables the RXFIFO DMA Request. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_DMAREG_RXDEN (23) //!< Bit position for ECSPI_DMAREG_RXDEN. +#define BM_ECSPI_DMAREG_RXDEN (0x00800000) //!< Bit mask for ECSPI_DMAREG_RXDEN. + +//! @brief Get value of ECSPI_DMAREG_RXDEN from a register value. +#define BG_ECSPI_DMAREG_RXDEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_DMAREG_RXDEN) >> BP_ECSPI_DMAREG_RXDEN) + +//! @brief Format value for bitfield ECSPI_DMAREG_RXDEN. +#define BF_ECSPI_DMAREG_RXDEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_DMAREG_RXDEN) & BM_ECSPI_DMAREG_RXDEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXDEN field to a new value. +#define BW_ECSPI_DMAREG_RXDEN(x, v) (HW_ECSPI_DMAREG_WR(x, (HW_ECSPI_DMAREG_RD(x) & ~BM_ECSPI_DMAREG_RXDEN) | BF_ECSPI_DMAREG_RXDEN(v))) +#endif +//@} + +/*! @name Register ECSPI_DMAREG, field RX_DMA_LENGTH[29:24] (RW) + * + * RX DMA LENGTH. This field defines the burst length of a DMA operation. Applies only when RXTDEN + * is set. + */ +//@{ +#define BP_ECSPI_DMAREG_RX_DMA_LENGTH (24) //!< Bit position for ECSPI_DMAREG_RX_DMA_LENGTH. +#define BM_ECSPI_DMAREG_RX_DMA_LENGTH (0x3f000000) //!< Bit mask for ECSPI_DMAREG_RX_DMA_LENGTH. + +//! @brief Get value of ECSPI_DMAREG_RX_DMA_LENGTH from a register value. +#define BG_ECSPI_DMAREG_RX_DMA_LENGTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_DMAREG_RX_DMA_LENGTH) >> BP_ECSPI_DMAREG_RX_DMA_LENGTH) + +//! @brief Format value for bitfield ECSPI_DMAREG_RX_DMA_LENGTH. +#define BF_ECSPI_DMAREG_RX_DMA_LENGTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_DMAREG_RX_DMA_LENGTH) & BM_ECSPI_DMAREG_RX_DMA_LENGTH) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RX_DMA_LENGTH field to a new value. +#define BW_ECSPI_DMAREG_RX_DMA_LENGTH(x, v) (HW_ECSPI_DMAREG_WR(x, (HW_ECSPI_DMAREG_RD(x) & ~BM_ECSPI_DMAREG_RX_DMA_LENGTH) | BF_ECSPI_DMAREG_RX_DMA_LENGTH(v))) +#endif +//@} + +/*! @name Register ECSPI_DMAREG, field RXTDEN[31] (RW) + * + * RXFIFO TAIL DMA Request Enable. This bit enables an internal counter that is increased at each + * read of the RXFIFO. This counter is cleared automatically when it reaches RX DMA LENGTH. If the + * number of words remaining in the RXFIFO is greater than or equal to RX DMA LENGTH, a DMA request + * is generated even if it is less than or equal to RX_THRESHOLD. + * + * Values: + * - 0 - Disable + * - 1 - Enable + */ +//@{ +#define BP_ECSPI_DMAREG_RXTDEN (31) //!< Bit position for ECSPI_DMAREG_RXTDEN. +#define BM_ECSPI_DMAREG_RXTDEN (0x80000000) //!< Bit mask for ECSPI_DMAREG_RXTDEN. + +//! @brief Get value of ECSPI_DMAREG_RXTDEN from a register value. +#define BG_ECSPI_DMAREG_RXTDEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_DMAREG_RXTDEN) >> BP_ECSPI_DMAREG_RXTDEN) + +//! @brief Format value for bitfield ECSPI_DMAREG_RXTDEN. +#define BF_ECSPI_DMAREG_RXTDEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_DMAREG_RXTDEN) & BM_ECSPI_DMAREG_RXTDEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXTDEN field to a new value. +#define BW_ECSPI_DMAREG_RXTDEN(x, v) (HW_ECSPI_DMAREG_WR(x, (HW_ECSPI_DMAREG_RD(x) & ~BM_ECSPI_DMAREG_RXTDEN) | BF_ECSPI_DMAREG_RXTDEN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_STATREG - Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_STATREG - Status Register (RW) + * + * Reset value: 0x00000003 + * + * The ECSPI Status Register (ECSPI_STATREG) reflects the status of the ECSPI's operating condition. + * If the ECSPI is disabled, this register reads 0x0000_0003. + */ +typedef union _hw_ecspi_statreg +{ + reg32_t U; + struct _hw_ecspi_statreg_bitfields + { + unsigned TE : 1; //!< [0] TXFIFO Empty. + unsigned TDR : 1; //!< [1] TXFIFO Data Request. + unsigned TF : 1; //!< [2] TXFIFO Full. + unsigned RR : 1; //!< [3] RXFIFO Ready. + unsigned RDR : 1; //!< [4] RXFIFO Data Request. + unsigned RF : 1; //!< [5] RXFIFO Full. + unsigned RO : 1; //!< [6] RXFIFO Overflow. + unsigned TC : 1; //!< [7] Transfer Completed Status bit. + unsigned RESERVED0 : 24; //!< [31:8] Reserved + } B; +} hw_ecspi_statreg_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_STATREG register + */ +//@{ +#define HW_ECSPI_STATREG_ADDR(x) (REGS_ECSPI_BASE(x) + 0x18) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_STATREG(x) (*(volatile hw_ecspi_statreg_t *) HW_ECSPI_STATREG_ADDR(x)) +#define HW_ECSPI_STATREG_RD(x) (HW_ECSPI_STATREG(x).U) +#define HW_ECSPI_STATREG_WR(x, v) (HW_ECSPI_STATREG(x).U = (v)) +#define HW_ECSPI_STATREG_SET(x, v) (HW_ECSPI_STATREG_WR(x, HW_ECSPI_STATREG_RD(x) | (v))) +#define HW_ECSPI_STATREG_CLR(x, v) (HW_ECSPI_STATREG_WR(x, HW_ECSPI_STATREG_RD(x) & ~(v))) +#define HW_ECSPI_STATREG_TOG(x, v) (HW_ECSPI_STATREG_WR(x, HW_ECSPI_STATREG_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ECSPI_STATREG bitfields + */ + +/*! @name Register ECSPI_STATREG, field TE[0] (RO) + * + * TXFIFO Empty. This bit is set if the TXFIFO is empty. + * + * Values: + * - 0 - TXFIFO contains one or more words. + * - 1 - TXFIFO is empty. + */ +//@{ +#define BP_ECSPI_STATREG_TE (0) //!< Bit position for ECSPI_STATREG_TE. +#define BM_ECSPI_STATREG_TE (0x00000001) //!< Bit mask for ECSPI_STATREG_TE. + +//! @brief Get value of ECSPI_STATREG_TE from a register value. +#define BG_ECSPI_STATREG_TE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_STATREG_TE) >> BP_ECSPI_STATREG_TE) +//@} + +/*! @name Register ECSPI_STATREG, field TDR[1] (RO) + * + * TXFIFO Data Request. + * + * Values: + * - 0 - Number of empty slots in TXFIFO is greater than TX_THRESHOLD. + * - 1 - Number of empty slots in TXFIFO is not greater than TX_THRESHOLD. + */ +//@{ +#define BP_ECSPI_STATREG_TDR (1) //!< Bit position for ECSPI_STATREG_TDR. +#define BM_ECSPI_STATREG_TDR (0x00000002) //!< Bit mask for ECSPI_STATREG_TDR. + +//! @brief Get value of ECSPI_STATREG_TDR from a register value. +#define BG_ECSPI_STATREG_TDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_STATREG_TDR) >> BP_ECSPI_STATREG_TDR) +//@} + +/*! @name Register ECSPI_STATREG, field TF[2] (RO) + * + * TXFIFO Full. This bit is set when if the TXFIFO is full. + * + * Values: + * - 0 - TXFIFO is not Full. + * - 1 - TXFIFO is Full. + */ +//@{ +#define BP_ECSPI_STATREG_TF (2) //!< Bit position for ECSPI_STATREG_TF. +#define BM_ECSPI_STATREG_TF (0x00000004) //!< Bit mask for ECSPI_STATREG_TF. + +//! @brief Get value of ECSPI_STATREG_TF from a register value. +#define BG_ECSPI_STATREG_TF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_STATREG_TF) >> BP_ECSPI_STATREG_TF) +//@} + +/*! @name Register ECSPI_STATREG, field RR[3] (RO) + * + * RXFIFO Ready. This bit is set when one or more words are stored in the RXFIFO. + * + * Values: + * - 0 - No valid data in RXFIFO. + * - 1 - More than 1 word in RXFIFO. + */ +//@{ +#define BP_ECSPI_STATREG_RR (3) //!< Bit position for ECSPI_STATREG_RR. +#define BM_ECSPI_STATREG_RR (0x00000008) //!< Bit mask for ECSPI_STATREG_RR. + +//! @brief Get value of ECSPI_STATREG_RR from a register value. +#define BG_ECSPI_STATREG_RR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_STATREG_RR) >> BP_ECSPI_STATREG_RR) +//@} + +/*! @name Register ECSPI_STATREG, field RDR[4] (RO) + * + * RXFIFO Data Request. + * + * Values: + * - 0 - When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + * - 0 - When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + * - 1 - When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL + * DMA condition exists. + * - 1 - When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD. + */ +//@{ +#define BP_ECSPI_STATREG_RDR (4) //!< Bit position for ECSPI_STATREG_RDR. +#define BM_ECSPI_STATREG_RDR (0x00000010) //!< Bit mask for ECSPI_STATREG_RDR. + +//! @brief Get value of ECSPI_STATREG_RDR from a register value. +#define BG_ECSPI_STATREG_RDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_STATREG_RDR) >> BP_ECSPI_STATREG_RDR) +//@} + +/*! @name Register ECSPI_STATREG, field RF[5] (RO) + * + * RXFIFO Full. This bit is set when the RXFIFO is full. + * + * Values: + * - 0 - Not Full. + * - 1 - Full. + */ +//@{ +#define BP_ECSPI_STATREG_RF (5) //!< Bit position for ECSPI_STATREG_RF. +#define BM_ECSPI_STATREG_RF (0x00000020) //!< Bit mask for ECSPI_STATREG_RF. + +//! @brief Get value of ECSPI_STATREG_RF from a register value. +#define BG_ECSPI_STATREG_RF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_STATREG_RF) >> BP_ECSPI_STATREG_RF) +//@} + +/*! @name Register ECSPI_STATREG, field RO[6] (W1C) + * + * RXFIFO Overflow. When set, this bit indicates that RXFIFO has overflowed. Writing 1 to this bit + * clears it. + * + * Values: + * - 0 - RXFIFO has no overflow. + * - 1 - RXFIFO has overflowed. + */ +//@{ +#define BP_ECSPI_STATREG_RO (6) //!< Bit position for ECSPI_STATREG_RO. +#define BM_ECSPI_STATREG_RO (0x00000040) //!< Bit mask for ECSPI_STATREG_RO. + +//! @brief Get value of ECSPI_STATREG_RO from a register value. +#define BG_ECSPI_STATREG_RO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_STATREG_RO) >> BP_ECSPI_STATREG_RO) + +//! @brief Format value for bitfield ECSPI_STATREG_RO. +#define BF_ECSPI_STATREG_RO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_STATREG_RO) & BM_ECSPI_STATREG_RO) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RO field to a new value. +#define BW_ECSPI_STATREG_RO(x, v) (HW_ECSPI_STATREG_WR(x, (HW_ECSPI_STATREG_RD(x) & ~BM_ECSPI_STATREG_RO) | BF_ECSPI_STATREG_RO(v))) +#endif +//@} + +/*! @name Register ECSPI_STATREG, field TC[7] (W1C) + * + * Transfer Completed Status bit. Writing 1 to this bit clears it. + * + * Values: + * - 0 - Transfer in progress. + * - 1 - Transfer completed. + */ +//@{ +#define BP_ECSPI_STATREG_TC (7) //!< Bit position for ECSPI_STATREG_TC. +#define BM_ECSPI_STATREG_TC (0x00000080) //!< Bit mask for ECSPI_STATREG_TC. + +//! @brief Get value of ECSPI_STATREG_TC from a register value. +#define BG_ECSPI_STATREG_TC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_STATREG_TC) >> BP_ECSPI_STATREG_TC) + +//! @brief Format value for bitfield ECSPI_STATREG_TC. +#define BF_ECSPI_STATREG_TC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_STATREG_TC) & BM_ECSPI_STATREG_TC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TC field to a new value. +#define BW_ECSPI_STATREG_TC(x, v) (HW_ECSPI_STATREG_WR(x, (HW_ECSPI_STATREG_RD(x) & ~BM_ECSPI_STATREG_TC) | BF_ECSPI_STATREG_TC(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_PERIODREG - Sample Period Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_PERIODREG - Sample Period Control Register (RW) + * + * Reset value: 0x00000000 + * + * The Sample Period Control Register (ECSPI_PERIODREG) provides software a way to insert delays + * (wait states) between consecutive SPI transfers. Control bits in this register select the clock + * source for the sample period counter and the delay count indicating the number of wait states to + * be inserted between data transfers. The delay counts apply only when the current channel is + * operating in Master mode (ECSPI_CONREG[CHANNEL MODE] = 1).ECSPI_PERIODREG also contains the CSD + * CTRL field used to insert a delay between the Chip Select's active edge and the first SPI Clock + * edge. + */ +typedef union _hw_ecspi_periodreg +{ + reg32_t U; + struct _hw_ecspi_periodreg_bitfields + { + unsigned SAMPLE_PERIOD : 15; //!< [14:0] Sample Period Control. + unsigned CSRC : 1; //!< [15] Clock Source Control. + unsigned CSD_CTL : 6; //!< [21:16] Chip Select Delay Control bits. + unsigned RESERVED0 : 10; //!< [31:22] Reserved + } B; +} hw_ecspi_periodreg_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_PERIODREG register + */ +//@{ +#define HW_ECSPI_PERIODREG_ADDR(x) (REGS_ECSPI_BASE(x) + 0x1c) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_PERIODREG(x) (*(volatile hw_ecspi_periodreg_t *) HW_ECSPI_PERIODREG_ADDR(x)) +#define HW_ECSPI_PERIODREG_RD(x) (HW_ECSPI_PERIODREG(x).U) +#define HW_ECSPI_PERIODREG_WR(x, v) (HW_ECSPI_PERIODREG(x).U = (v)) +#define HW_ECSPI_PERIODREG_SET(x, v) (HW_ECSPI_PERIODREG_WR(x, HW_ECSPI_PERIODREG_RD(x) | (v))) +#define HW_ECSPI_PERIODREG_CLR(x, v) (HW_ECSPI_PERIODREG_WR(x, HW_ECSPI_PERIODREG_RD(x) & ~(v))) +#define HW_ECSPI_PERIODREG_TOG(x, v) (HW_ECSPI_PERIODREG_WR(x, HW_ECSPI_PERIODREG_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ECSPI_PERIODREG bitfields + */ + +/*! @name Register ECSPI_PERIODREG, field SAMPLE_PERIOD[14:0] (RW) + * + * Sample Period Control. These bits control the number of wait states to be inserted in data + * transfers. During the idle clocks, the state of the SS output will operate according to the + * SS_CTL control field in the ECSPI_CONREG register. + * + * Values: + * - 0x0000 - 0 wait states inserted + * - ... - ... + * - 0x0001 - 1 wait state inserted + * - 0x7FFE - 32766 wait states inserted + * - 0x7FFF - 32767 wait states inserted + */ +//@{ +#define BP_ECSPI_PERIODREG_SAMPLE_PERIOD (0) //!< Bit position for ECSPI_PERIODREG_SAMPLE_PERIOD. +#define BM_ECSPI_PERIODREG_SAMPLE_PERIOD (0x00007fff) //!< Bit mask for ECSPI_PERIODREG_SAMPLE_PERIOD. + +//! @brief Get value of ECSPI_PERIODREG_SAMPLE_PERIOD from a register value. +#define BG_ECSPI_PERIODREG_SAMPLE_PERIOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_PERIODREG_SAMPLE_PERIOD) >> BP_ECSPI_PERIODREG_SAMPLE_PERIOD) + +//! @brief Format value for bitfield ECSPI_PERIODREG_SAMPLE_PERIOD. +#define BF_ECSPI_PERIODREG_SAMPLE_PERIOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_PERIODREG_SAMPLE_PERIOD) & BM_ECSPI_PERIODREG_SAMPLE_PERIOD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SAMPLE_PERIOD field to a new value. +#define BW_ECSPI_PERIODREG_SAMPLE_PERIOD(x, v) (HW_ECSPI_PERIODREG_WR(x, (HW_ECSPI_PERIODREG_RD(x) & ~BM_ECSPI_PERIODREG_SAMPLE_PERIOD) | BF_ECSPI_PERIODREG_SAMPLE_PERIOD(v))) +#endif +//@} + +/*! @name Register ECSPI_PERIODREG, field CSRC[15] (RW) + * + * Clock Source Control. This bit selects the clock source for the sample period counter. + * + * Values: + * - 0 - SPI Clock (SCLK) + * - 1 - Low-Frequency Reference Clock (32.768 KHz) + */ +//@{ +#define BP_ECSPI_PERIODREG_CSRC (15) //!< Bit position for ECSPI_PERIODREG_CSRC. +#define BM_ECSPI_PERIODREG_CSRC (0x00008000) //!< Bit mask for ECSPI_PERIODREG_CSRC. + +//! @brief Get value of ECSPI_PERIODREG_CSRC from a register value. +#define BG_ECSPI_PERIODREG_CSRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_PERIODREG_CSRC) >> BP_ECSPI_PERIODREG_CSRC) + +//! @brief Format value for bitfield ECSPI_PERIODREG_CSRC. +#define BF_ECSPI_PERIODREG_CSRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_PERIODREG_CSRC) & BM_ECSPI_PERIODREG_CSRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CSRC field to a new value. +#define BW_ECSPI_PERIODREG_CSRC(x, v) (HW_ECSPI_PERIODREG_WR(x, (HW_ECSPI_PERIODREG_RD(x) & ~BM_ECSPI_PERIODREG_CSRC) | BF_ECSPI_PERIODREG_CSRC(v))) +#endif +//@} + +/*! @name Register ECSPI_PERIODREG, field CSD_CTL[21:16] (RW) + * + * Chip Select Delay Control bits. This field defines how many SPI clocks will be inserted between + * the chip select's active edge and the first SPI clock edge. The range is from 0 to 63. + */ +//@{ +#define BP_ECSPI_PERIODREG_CSD_CTL (16) //!< Bit position for ECSPI_PERIODREG_CSD_CTL. +#define BM_ECSPI_PERIODREG_CSD_CTL (0x003f0000) //!< Bit mask for ECSPI_PERIODREG_CSD_CTL. + +//! @brief Get value of ECSPI_PERIODREG_CSD_CTL from a register value. +#define BG_ECSPI_PERIODREG_CSD_CTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_PERIODREG_CSD_CTL) >> BP_ECSPI_PERIODREG_CSD_CTL) + +//! @brief Format value for bitfield ECSPI_PERIODREG_CSD_CTL. +#define BF_ECSPI_PERIODREG_CSD_CTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_PERIODREG_CSD_CTL) & BM_ECSPI_PERIODREG_CSD_CTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CSD_CTL field to a new value. +#define BW_ECSPI_PERIODREG_CSD_CTL(x, v) (HW_ECSPI_PERIODREG_WR(x, (HW_ECSPI_PERIODREG_RD(x) & ~BM_ECSPI_PERIODREG_CSD_CTL) | BF_ECSPI_PERIODREG_CSD_CTL(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_TESTREG - Test Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_TESTREG - Test Control Register (RW) + * + * Reset value: 0x00000000 + * + * The Test Control Register (ECSPI_TESTREG) provides software a mechanism to internally connect the + * receive and transmit devices of the ECSPI , and monitor the contents of the receive and transmit + * FIFOs. + */ +typedef union _hw_ecspi_testreg +{ + reg32_t U; + struct _hw_ecspi_testreg_bitfields + { + unsigned TXCNT : 7; //!< [6:0] TXFIFO Counter. + unsigned RESERVED0 : 1; //!< [7] Reserved + unsigned RXCNT : 7; //!< [14:8] RXFIFO Counter. + unsigned RESERVED1 : 16; //!< [30:15] Reserved. + unsigned LBC : 1; //!< [31] Loop Back Control. + } B; +} hw_ecspi_testreg_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_TESTREG register + */ +//@{ +#define HW_ECSPI_TESTREG_ADDR(x) (REGS_ECSPI_BASE(x) + 0x20) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_TESTREG(x) (*(volatile hw_ecspi_testreg_t *) HW_ECSPI_TESTREG_ADDR(x)) +#define HW_ECSPI_TESTREG_RD(x) (HW_ECSPI_TESTREG(x).U) +#define HW_ECSPI_TESTREG_WR(x, v) (HW_ECSPI_TESTREG(x).U = (v)) +#define HW_ECSPI_TESTREG_SET(x, v) (HW_ECSPI_TESTREG_WR(x, HW_ECSPI_TESTREG_RD(x) | (v))) +#define HW_ECSPI_TESTREG_CLR(x, v) (HW_ECSPI_TESTREG_WR(x, HW_ECSPI_TESTREG_RD(x) & ~(v))) +#define HW_ECSPI_TESTREG_TOG(x, v) (HW_ECSPI_TESTREG_WR(x, HW_ECSPI_TESTREG_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ECSPI_TESTREG bitfields + */ + +/*! @name Register ECSPI_TESTREG, field TXCNT[6:0] (RW) + * + * TXFIFO Counter. This field indicates the number of words in the TXFIFO. + */ +//@{ +#define BP_ECSPI_TESTREG_TXCNT (0) //!< Bit position for ECSPI_TESTREG_TXCNT. +#define BM_ECSPI_TESTREG_TXCNT (0x0000007f) //!< Bit mask for ECSPI_TESTREG_TXCNT. + +//! @brief Get value of ECSPI_TESTREG_TXCNT from a register value. +#define BG_ECSPI_TESTREG_TXCNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_TESTREG_TXCNT) >> BP_ECSPI_TESTREG_TXCNT) + +//! @brief Format value for bitfield ECSPI_TESTREG_TXCNT. +#define BF_ECSPI_TESTREG_TXCNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_TESTREG_TXCNT) & BM_ECSPI_TESTREG_TXCNT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXCNT field to a new value. +#define BW_ECSPI_TESTREG_TXCNT(x, v) (HW_ECSPI_TESTREG_WR(x, (HW_ECSPI_TESTREG_RD(x) & ~BM_ECSPI_TESTREG_TXCNT) | BF_ECSPI_TESTREG_TXCNT(v))) +#endif +//@} + +/*! @name Register ECSPI_TESTREG, field RXCNT[14:8] (RW) + * + * RXFIFO Counter. This field indicates the number of words in the RXFIFO. + */ +//@{ +#define BP_ECSPI_TESTREG_RXCNT (8) //!< Bit position for ECSPI_TESTREG_RXCNT. +#define BM_ECSPI_TESTREG_RXCNT (0x00007f00) //!< Bit mask for ECSPI_TESTREG_RXCNT. + +//! @brief Get value of ECSPI_TESTREG_RXCNT from a register value. +#define BG_ECSPI_TESTREG_RXCNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_TESTREG_RXCNT) >> BP_ECSPI_TESTREG_RXCNT) + +//! @brief Format value for bitfield ECSPI_TESTREG_RXCNT. +#define BF_ECSPI_TESTREG_RXCNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_TESTREG_RXCNT) & BM_ECSPI_TESTREG_RXCNT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXCNT field to a new value. +#define BW_ECSPI_TESTREG_RXCNT(x, v) (HW_ECSPI_TESTREG_WR(x, (HW_ECSPI_TESTREG_RD(x) & ~BM_ECSPI_TESTREG_RXCNT) | BF_ECSPI_TESTREG_RXCNT(v))) +#endif +//@} + +/*! @name Register ECSPI_TESTREG, field LBC[31] (RW) + * + * Loop Back Control. This bit is used in Master mode only. When this bit is set, the ECSPI connects + * the transmitter and receiver sections internally, and the data shifted out from the most- + * significant bit of the shift register is looped back into the least-significant bit of the Shift + * register. In this way, a self-test of the complete transmit/receive path can be made. The output + * pins are not affected, and the input pins are ignored. + * + * Values: + * - 0 - Not connected. + * - 1 - Transmitter and receiver sections internally connected for Loopback. + */ +//@{ +#define BP_ECSPI_TESTREG_LBC (31) //!< Bit position for ECSPI_TESTREG_LBC. +#define BM_ECSPI_TESTREG_LBC (0x80000000) //!< Bit mask for ECSPI_TESTREG_LBC. + +//! @brief Get value of ECSPI_TESTREG_LBC from a register value. +#define BG_ECSPI_TESTREG_LBC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_TESTREG_LBC) >> BP_ECSPI_TESTREG_LBC) + +//! @brief Format value for bitfield ECSPI_TESTREG_LBC. +#define BF_ECSPI_TESTREG_LBC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_TESTREG_LBC) & BM_ECSPI_TESTREG_LBC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LBC field to a new value. +#define BW_ECSPI_TESTREG_LBC(x, v) (HW_ECSPI_TESTREG_WR(x, (HW_ECSPI_TESTREG_RD(x) & ~BM_ECSPI_TESTREG_LBC) | BF_ECSPI_TESTREG_LBC(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ECSPI_MSGDATA - Message Data Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ECSPI_MSGDATA - Message Data Register (WO) + * + * Reset value: 0x00000000 + * + * The Message Data Register (ECSPI_MSGDATA) forms the top word of the 16 x 32 MSG Data FIFO. Only + * word-size accesses are allowed for this register. Reads to this register return zero, and writes + * to this register store data in the MSG Data FIFO. + */ +typedef union _hw_ecspi_msgdata +{ + reg32_t U; + struct _hw_ecspi_msgdata_bitfields + { + unsigned ECSPI_MSGDATA : 32; //!< [31:0] ECSPI_MSGDATA holds the top word of MSG Data FIFO. + } B; +} hw_ecspi_msgdata_t; +#endif + +/*! + * @name Constants and macros for entire ECSPI_MSGDATA register + */ +//@{ +#define HW_ECSPI_MSGDATA_ADDR(x) (REGS_ECSPI_BASE(x) + 0x40) + +#ifndef __LANGUAGE_ASM__ +#define HW_ECSPI_MSGDATA(x) (*(volatile hw_ecspi_msgdata_t *) HW_ECSPI_MSGDATA_ADDR(x)) +#define HW_ECSPI_MSGDATA_WR(x, v) (HW_ECSPI_MSGDATA(x).U = (v)) +#endif +//@} + +/* + * constants & macros for individual ECSPI_MSGDATA bitfields + */ + +/*! @name Register ECSPI_MSGDATA, field ECSPI_MSGDATA[31:0] (WO) + * + * ECSPI_MSGDATA holds the top word of MSG Data FIFO. The MSG Data FIFO is advanced for each write + * of this register. The data read is zero. The data written to this register is stored in the MSG + * Data FIFO. + */ +//@{ +#define BP_ECSPI_MSGDATA_ECSPI_MSGDATA (0) //!< Bit position for ECSPI_MSGDATA_ECSPI_MSGDATA. +#define BM_ECSPI_MSGDATA_ECSPI_MSGDATA (0xffffffff) //!< Bit mask for ECSPI_MSGDATA_ECSPI_MSGDATA. + +//! @brief Get value of ECSPI_MSGDATA_ECSPI_MSGDATA from a register value. +#define BG_ECSPI_MSGDATA_ECSPI_MSGDATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ECSPI_MSGDATA_ECSPI_MSGDATA) >> BP_ECSPI_MSGDATA_ECSPI_MSGDATA) + +//! @brief Format value for bitfield ECSPI_MSGDATA_ECSPI_MSGDATA. +#define BF_ECSPI_MSGDATA_ECSPI_MSGDATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ECSPI_MSGDATA_ECSPI_MSGDATA) & BM_ECSPI_MSGDATA_ECSPI_MSGDATA) +//@} + +//------------------------------------------------------------------------------------------- +// hw_ecspi_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All ECSPI module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_ecspi +{ + volatile hw_ecspi_rxdata_t RXDATA; //!< Receive Data Register + volatile hw_ecspi_txdata_t TXDATA; //!< Transmit Data Register + volatile hw_ecspi_conreg_t CONREG; //!< Control Register + volatile hw_ecspi_configreg_t CONFIGREG; //!< Config Register + volatile hw_ecspi_intreg_t INTREG; //!< Interrupt Control Register + volatile hw_ecspi_dmareg_t DMAREG; //!< DMA Control Register + volatile hw_ecspi_statreg_t STATREG; //!< Status Register + volatile hw_ecspi_periodreg_t PERIODREG; //!< Sample Period Control Register + volatile hw_ecspi_testreg_t TESTREG; //!< Test Control Register + reg32_t _reserved0[7]; + volatile hw_ecspi_msgdata_t MSGDATA; //!< Message Data Register +} hw_ecspi_t; +#pragma pack() + +//! @brief Macro to access all ECSPI registers. +//! @param x ECSPI instance number. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_ECSPI(0). +#define HW_ECSPI(x) (*(hw_ecspi_t *) REGS_ECSPI_BASE(x)) +#endif + +#endif // __HW_ECSPI_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsenet.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsenet.h new file mode 100644 index 0000000000000000000000000000000000000000..5ea22e18a0078ede6712a2bc7ec31a2035208760 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsenet.h @@ -0,0 +1,4508 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_ENET_REGISTERS_H__ +#define __HW_ENET_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL ENET + * + * Ethernet MAC-NET Core + * + * Registers defined in this header file: + * - HW_ENET_EIR - Interrupt Event Register + * - HW_ENET_EIMR - Interrupt Mask Register + * - HW_ENET_RDAR - Receive Descriptor Active Register + * - HW_ENET_TDAR - Transmit Descriptor Active Register + * - HW_ENET_ECR - Ethernet Control Register + * - HW_ENET_MMFR - MII Management Frame Register + * - HW_ENET_MSCR - MII Speed Control Register + * - HW_ENET_MIBC - MIB Control Register + * - HW_ENET_RCR - Receive Control Register + * - HW_ENET_TCR - Transmit Control Register + * - HW_ENET_PALR - Physical Address Lower Register + * - HW_ENET_PAUR - Physical Address Upper Register + * - HW_ENET_OPD - Opcode/Pause Duration Register + * - HW_ENET_IAUR - Descriptor Individual Upper Address Register + * - HW_ENET_IALR - Descriptor Individual Lower Address Register + * - HW_ENET_GAUR - Descriptor Group Upper Address Register + * - HW_ENET_GALR - Descriptor Group Lower Address Register + * - HW_ENET_TFWR - Transmit FIFO Watermark Register + * - HW_ENET_RDSR - Receive Descriptor Ring Start Register + * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register + * - HW_ENET_MRBR - Maximum Receive Buffer Size Register + * - HW_ENET_RSFL - Receive FIFO Section Full Threshold + * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold + * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold + * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold + * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold + * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold + * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold + * - HW_ENET_TIPG - Transmit Inter-Packet Gap + * - HW_ENET_FTRL - Frame Truncation Length + * - HW_ENET_TACC - Transmit Accelerator Function Configuration + * - HW_ENET_RACC - Receive Accelerator Function Configuration + * - HW_ENET_ATCR - Timer Control Register + * - HW_ENET_ATVR - Timer Value Register + * - HW_ENET_ATOFF - Timer Offset Register + * - HW_ENET_ATPER - Timer Period Register + * - HW_ENET_ATCOR - Timer Correction Register + * - HW_ENET_ATINC - Time-Stamping Clock Period Register + * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame + * + * - hw_enet_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_ENET_BASE +#define HW_ENET_INSTANCE_COUNT (1) //!< Number of instances of the ENET module. +#define REGS_ENET_BASE (0x02188000) //!< Base address for ENET. +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_EIR - Interrupt Event Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_EIR - Interrupt Event Register (W1C) + * + * Reset value: 0x00000000 + * + * When an event occurs that sets a bit in EIR, an interrupt occurs if the corresponding bit in the + * interrupt mask register (EIMR) is also set. Writing a 1 to an EIR bit clears it; writing 0 has no + * effect. This register is cleared upon hardware reset. + */ +typedef union _hw_enet_eir +{ + reg32_t U; + struct _hw_enet_eir_bitfields + { + unsigned RESERVED0 : 15; //!< [14:0] Reserved. + unsigned TS_TIMER : 1; //!< [15] Timestamp Timer + unsigned TS_AVAIL : 1; //!< [16] Transmit Timestamp Available + unsigned WAKEUP : 1; //!< [17] Node Wakeup Request Indication + unsigned PLR : 1; //!< [18] Payload Receive Error + unsigned UN : 1; //!< [19] Transmit FIFO Underrun + unsigned RL : 1; //!< [20] Collision Retry Limit + unsigned LC : 1; //!< [21] Late Collision + unsigned EBERR : 1; //!< [22] Ethernet Bus Error + unsigned MII : 1; //!< [23] MII Interrupt. + unsigned RXB : 1; //!< [24] Receive Buffer Interrupt + unsigned RXF : 1; //!< [25] Receive Frame Interrupt + unsigned TXB : 1; //!< [26] Transmit Buffer Interrupt + unsigned TXF : 1; //!< [27] Transmit Frame Interrupt + unsigned GRA : 1; //!< [28] Graceful Stop Complete + unsigned BABT : 1; //!< [29] Babbling Transmit Error + unsigned BABR : 1; //!< [30] Babbling Receive Error + unsigned RESERVED1 : 1; //!< [31] + } B; +} hw_enet_eir_t; +#endif + +/*! + * @name Constants and macros for entire ENET_EIR register + */ +//@{ +#define HW_ENET_EIR_ADDR (REGS_ENET_BASE + 0x4) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_EIR (*(volatile hw_enet_eir_t *) HW_ENET_EIR_ADDR) +#define HW_ENET_EIR_RD() (HW_ENET_EIR.U) +#define HW_ENET_EIR_WR(v) (HW_ENET_EIR.U = (v)) +#define HW_ENET_EIR_SET(v) (HW_ENET_EIR_WR(HW_ENET_EIR_RD() | (v))) +#define HW_ENET_EIR_CLR(v) (HW_ENET_EIR_WR(HW_ENET_EIR_RD() & ~(v))) +#define HW_ENET_EIR_TOG(v) (HW_ENET_EIR_WR(HW_ENET_EIR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_EIR bitfields + */ + +/*! @name Register ENET_EIR, field TS_TIMER[15] (W1C) + * + * The adjustable timer reached the period event. A period event interrupt can be generated if + * ATCR[PEREN] is set and the timer wraps according to the periodic setting in the ATPER register. + * Set the timer period value before setting ATCR[PEREN]. + */ +//@{ +#define BP_ENET_EIR_TS_TIMER (15) //!< Bit position for ENET_EIR_TS_TIMER. +#define BM_ENET_EIR_TS_TIMER (0x00008000) //!< Bit mask for ENET_EIR_TS_TIMER. + +//! @brief Get value of ENET_EIR_TS_TIMER from a register value. +#define BG_ENET_EIR_TS_TIMER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_TS_TIMER) >> BP_ENET_EIR_TS_TIMER) + +//! @brief Format value for bitfield ENET_EIR_TS_TIMER. +#define BF_ENET_EIR_TS_TIMER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_TS_TIMER) & BM_ENET_EIR_TS_TIMER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TS_TIMER field to a new value. +#define BW_ENET_EIR_TS_TIMER(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_TS_TIMER) | BF_ENET_EIR_TS_TIMER(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field TS_AVAIL[16] (W1C) + * + * Indicates that the timestamp of the last transmitted timing frame is available in the ATSTMP + * register. + */ +//@{ +#define BP_ENET_EIR_TS_AVAIL (16) //!< Bit position for ENET_EIR_TS_AVAIL. +#define BM_ENET_EIR_TS_AVAIL (0x00010000) //!< Bit mask for ENET_EIR_TS_AVAIL. + +//! @brief Get value of ENET_EIR_TS_AVAIL from a register value. +#define BG_ENET_EIR_TS_AVAIL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_TS_AVAIL) >> BP_ENET_EIR_TS_AVAIL) + +//! @brief Format value for bitfield ENET_EIR_TS_AVAIL. +#define BF_ENET_EIR_TS_AVAIL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_TS_AVAIL) & BM_ENET_EIR_TS_AVAIL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TS_AVAIL field to a new value. +#define BW_ENET_EIR_TS_AVAIL(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_TS_AVAIL) | BF_ENET_EIR_TS_AVAIL(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field WAKEUP[17] (W1C) + * + * Read-only status bit to indicate that a magic packet has been detected. Will act only if + * ECR[MAGICEN] is set. + */ +//@{ +#define BP_ENET_EIR_WAKEUP (17) //!< Bit position for ENET_EIR_WAKEUP. +#define BM_ENET_EIR_WAKEUP (0x00020000) //!< Bit mask for ENET_EIR_WAKEUP. + +//! @brief Get value of ENET_EIR_WAKEUP from a register value. +#define BG_ENET_EIR_WAKEUP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_WAKEUP) >> BP_ENET_EIR_WAKEUP) + +//! @brief Format value for bitfield ENET_EIR_WAKEUP. +#define BF_ENET_EIR_WAKEUP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_WAKEUP) & BM_ENET_EIR_WAKEUP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WAKEUP field to a new value. +#define BW_ENET_EIR_WAKEUP(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_WAKEUP) | BF_ENET_EIR_WAKEUP(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field PLR[18] (W1C) + * + * Indicates a frame was received with a payload length error. See Frame Length/Type Verification: + * Payload Length Check for more information. + */ +//@{ +#define BP_ENET_EIR_PLR (18) //!< Bit position for ENET_EIR_PLR. +#define BM_ENET_EIR_PLR (0x00040000) //!< Bit mask for ENET_EIR_PLR. + +//! @brief Get value of ENET_EIR_PLR from a register value. +#define BG_ENET_EIR_PLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_PLR) >> BP_ENET_EIR_PLR) + +//! @brief Format value for bitfield ENET_EIR_PLR. +#define BF_ENET_EIR_PLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_PLR) & BM_ENET_EIR_PLR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PLR field to a new value. +#define BW_ENET_EIR_PLR(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_PLR) | BF_ENET_EIR_PLR(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field UN[19] (W1C) + * + * Indicates the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is + * appended to the frame fragment and the remainder of the frame is discarded. + */ +//@{ +#define BP_ENET_EIR_UN (19) //!< Bit position for ENET_EIR_UN. +#define BM_ENET_EIR_UN (0x00080000) //!< Bit mask for ENET_EIR_UN. + +//! @brief Get value of ENET_EIR_UN from a register value. +#define BG_ENET_EIR_UN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_UN) >> BP_ENET_EIR_UN) + +//! @brief Format value for bitfield ENET_EIR_UN. +#define BF_ENET_EIR_UN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_UN) & BM_ENET_EIR_UN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the UN field to a new value. +#define BW_ENET_EIR_UN(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_UN) | BF_ENET_EIR_UN(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field RL[20] (W1C) + * + * Indicates a collision occurred on each of 16 successive attempts to transmit the frame. The frame + * is discarded without being transmitted and transmission of the next frame commences. This error + * can only occur in half-duplex mode. + */ +//@{ +#define BP_ENET_EIR_RL (20) //!< Bit position for ENET_EIR_RL. +#define BM_ENET_EIR_RL (0x00100000) //!< Bit mask for ENET_EIR_RL. + +//! @brief Get value of ENET_EIR_RL from a register value. +#define BG_ENET_EIR_RL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_RL) >> BP_ENET_EIR_RL) + +//! @brief Format value for bitfield ENET_EIR_RL. +#define BF_ENET_EIR_RL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_RL) & BM_ENET_EIR_RL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RL field to a new value. +#define BW_ENET_EIR_RL(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_RL) | BF_ENET_EIR_RL(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field LC[21] (W1C) + * + * Indicates a collision occurred beyond the collision window (slot time) in half-duplex mode. The + * frame truncates with a bad CRC and the remainder of the frame is discarded. + */ +//@{ +#define BP_ENET_EIR_LC (21) //!< Bit position for ENET_EIR_LC. +#define BM_ENET_EIR_LC (0x00200000) //!< Bit mask for ENET_EIR_LC. + +//! @brief Get value of ENET_EIR_LC from a register value. +#define BG_ENET_EIR_LC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_LC) >> BP_ENET_EIR_LC) + +//! @brief Format value for bitfield ENET_EIR_LC. +#define BF_ENET_EIR_LC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_LC) & BM_ENET_EIR_LC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LC field to a new value. +#define BW_ENET_EIR_LC(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_LC) | BF_ENET_EIR_LC(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field EBERR[22] (W1C) + * + * Indicates a system bus error occurred when a uDMA transaction is underway. When this bit is set, + * ECR[ETHEREN] is cleared, halting frame processing by the MAC. When this occurs, software must + * ensure proper actions, possibly resetting the system, to resume normal operation. + */ +//@{ +#define BP_ENET_EIR_EBERR (22) //!< Bit position for ENET_EIR_EBERR. +#define BM_ENET_EIR_EBERR (0x00400000) //!< Bit mask for ENET_EIR_EBERR. + +//! @brief Get value of ENET_EIR_EBERR from a register value. +#define BG_ENET_EIR_EBERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_EBERR) >> BP_ENET_EIR_EBERR) + +//! @brief Format value for bitfield ENET_EIR_EBERR. +#define BF_ENET_EIR_EBERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_EBERR) & BM_ENET_EIR_EBERR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EBERR field to a new value. +#define BW_ENET_EIR_EBERR(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_EBERR) | BF_ENET_EIR_EBERR(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field MII[23] (W1C) + * + * Indicates that the MII has completed the data transfer requested. + */ +//@{ +#define BP_ENET_EIR_MII (23) //!< Bit position for ENET_EIR_MII. +#define BM_ENET_EIR_MII (0x00800000) //!< Bit mask for ENET_EIR_MII. + +//! @brief Get value of ENET_EIR_MII from a register value. +#define BG_ENET_EIR_MII(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_MII) >> BP_ENET_EIR_MII) + +//! @brief Format value for bitfield ENET_EIR_MII. +#define BF_ENET_EIR_MII(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_MII) & BM_ENET_EIR_MII) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MII field to a new value. +#define BW_ENET_EIR_MII(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_MII) | BF_ENET_EIR_MII(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field RXB[24] (W1C) + * + * Indicates a receive buffer descriptor is not the last in the frame has been updated. + */ +//@{ +#define BP_ENET_EIR_RXB (24) //!< Bit position for ENET_EIR_RXB. +#define BM_ENET_EIR_RXB (0x01000000) //!< Bit mask for ENET_EIR_RXB. + +//! @brief Get value of ENET_EIR_RXB from a register value. +#define BG_ENET_EIR_RXB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_RXB) >> BP_ENET_EIR_RXB) + +//! @brief Format value for bitfield ENET_EIR_RXB. +#define BF_ENET_EIR_RXB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_RXB) & BM_ENET_EIR_RXB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXB field to a new value. +#define BW_ENET_EIR_RXB(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_RXB) | BF_ENET_EIR_RXB(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field RXF[25] (W1C) + * + * Indicates a frame has been received and the last corresponding buffer descriptor has been + * updated. + */ +//@{ +#define BP_ENET_EIR_RXF (25) //!< Bit position for ENET_EIR_RXF. +#define BM_ENET_EIR_RXF (0x02000000) //!< Bit mask for ENET_EIR_RXF. + +//! @brief Get value of ENET_EIR_RXF from a register value. +#define BG_ENET_EIR_RXF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_RXF) >> BP_ENET_EIR_RXF) + +//! @brief Format value for bitfield ENET_EIR_RXF. +#define BF_ENET_EIR_RXF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_RXF) & BM_ENET_EIR_RXF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXF field to a new value. +#define BW_ENET_EIR_RXF(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_RXF) | BF_ENET_EIR_RXF(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field TXB[26] (W1C) + * + * Indicates a transmit buffer descriptor has been updated. + */ +//@{ +#define BP_ENET_EIR_TXB (26) //!< Bit position for ENET_EIR_TXB. +#define BM_ENET_EIR_TXB (0x04000000) //!< Bit mask for ENET_EIR_TXB. + +//! @brief Get value of ENET_EIR_TXB from a register value. +#define BG_ENET_EIR_TXB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_TXB) >> BP_ENET_EIR_TXB) + +//! @brief Format value for bitfield ENET_EIR_TXB. +#define BF_ENET_EIR_TXB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_TXB) & BM_ENET_EIR_TXB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXB field to a new value. +#define BW_ENET_EIR_TXB(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_TXB) | BF_ENET_EIR_TXB(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field TXF[27] (W1C) + * + * Indicates a frame has been transmitted and the last corresponding buffer descriptor has been + * updated. + */ +//@{ +#define BP_ENET_EIR_TXF (27) //!< Bit position for ENET_EIR_TXF. +#define BM_ENET_EIR_TXF (0x08000000) //!< Bit mask for ENET_EIR_TXF. + +//! @brief Get value of ENET_EIR_TXF from a register value. +#define BG_ENET_EIR_TXF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_TXF) >> BP_ENET_EIR_TXF) + +//! @brief Format value for bitfield ENET_EIR_TXF. +#define BF_ENET_EIR_TXF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_TXF) & BM_ENET_EIR_TXF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXF field to a new value. +#define BW_ENET_EIR_TXF(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_TXF) | BF_ENET_EIR_TXF(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field GRA[28] (W1C) + * + * This interrupt is asserted after the transmitter is put into a pause state after completion of + * the frame currently being transmitted. See Graceful Transmit Stop (GTS) for conditions that lead + * to graceful stop. The GRA interrupt is asserted only when the TX transitions into the stopped + * state. If this bit is cleared by writing 1 and the TX is still stopped, the bit is not set again. + */ +//@{ +#define BP_ENET_EIR_GRA (28) //!< Bit position for ENET_EIR_GRA. +#define BM_ENET_EIR_GRA (0x10000000) //!< Bit mask for ENET_EIR_GRA. + +//! @brief Get value of ENET_EIR_GRA from a register value. +#define BG_ENET_EIR_GRA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_GRA) >> BP_ENET_EIR_GRA) + +//! @brief Format value for bitfield ENET_EIR_GRA. +#define BF_ENET_EIR_GRA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_GRA) & BM_ENET_EIR_GRA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GRA field to a new value. +#define BW_ENET_EIR_GRA(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_GRA) | BF_ENET_EIR_GRA(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field BABT[29] (W1C) + * + * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually this condition is + * caused when a frame that is too long is placed into the transmit data buffer(s). Truncation does + * not occur. + */ +//@{ +#define BP_ENET_EIR_BABT (29) //!< Bit position for ENET_EIR_BABT. +#define BM_ENET_EIR_BABT (0x20000000) //!< Bit mask for ENET_EIR_BABT. + +//! @brief Get value of ENET_EIR_BABT from a register value. +#define BG_ENET_EIR_BABT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_BABT) >> BP_ENET_EIR_BABT) + +//! @brief Format value for bitfield ENET_EIR_BABT. +#define BF_ENET_EIR_BABT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_BABT) & BM_ENET_EIR_BABT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BABT field to a new value. +#define BW_ENET_EIR_BABT(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_BABT) | BF_ENET_EIR_BABT(v))) +#endif +//@} + +/*! @name Register ENET_EIR, field BABR[30] (W1C) + * + * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes. + */ +//@{ +#define BP_ENET_EIR_BABR (30) //!< Bit position for ENET_EIR_BABR. +#define BM_ENET_EIR_BABR (0x40000000) //!< Bit mask for ENET_EIR_BABR. + +//! @brief Get value of ENET_EIR_BABR from a register value. +#define BG_ENET_EIR_BABR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIR_BABR) >> BP_ENET_EIR_BABR) + +//! @brief Format value for bitfield ENET_EIR_BABR. +#define BF_ENET_EIR_BABR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIR_BABR) & BM_ENET_EIR_BABR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BABR field to a new value. +#define BW_ENET_EIR_BABR(v) (HW_ENET_EIR_WR((HW_ENET_EIR_RD() & ~BM_ENET_EIR_BABR) | BF_ENET_EIR_BABR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_EIMR - Interrupt Mask Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_EIMR - Interrupt Mask Register (RW) + * + * Reset value: 0x00000000 + * + * EIMR controls which interrupt events are allowed to generate actual interrupts. A hardware reset + * clears this register. If the corresponding bits in the EIR and EIMR registers are set, an + * interrupt is generated. The interrupt signal remains asserted until a 1 is written to the EIR + * field (write 1 to clear) or a 0 is written to the EIMR field. + */ +typedef union _hw_enet_eimr +{ + reg32_t U; + struct _hw_enet_eimr_bitfields + { + unsigned RESERVED0 : 15; //!< [14:0] + unsigned TS_TIMER : 1; //!< [15] TS_TIMER Interrupt Mask + unsigned TS_AVAIL : 1; //!< [16] TS_AVAIL Interrupt Mask + unsigned WAKEUP : 1; //!< [17] WAKEUP Interrupt Mask + unsigned PLR : 1; //!< [18] PLR Interrupt Mask + unsigned UN : 1; //!< [19] UN Interrupt Mask + unsigned RL : 1; //!< [20] RL Interrupt Mask + unsigned LC : 1; //!< [21] LC Interrupt Mask + unsigned EBERR : 1; //!< [22] EBERR Interrupt Mask + unsigned MII : 1; //!< [23] MII Interrupt Mask + unsigned RXB : 1; //!< [24] RXB Interrupt Mask + unsigned RXF : 1; //!< [25] RXF Interrupt Mask + unsigned TXB : 1; //!< [26] TXB Interrupt Mask + unsigned TXF : 1; //!< [27] TXF Interrupt Mask + unsigned GRA : 1; //!< [28] GRA Interrupt Mask + unsigned BABT : 1; //!< [29] BABT Interrupt Mask + unsigned BABR : 1; //!< [30] BABR Interrupt Mask + unsigned RESERVED1 : 1; //!< [31] + } B; +} hw_enet_eimr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_EIMR register + */ +//@{ +#define HW_ENET_EIMR_ADDR (REGS_ENET_BASE + 0x8) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_EIMR (*(volatile hw_enet_eimr_t *) HW_ENET_EIMR_ADDR) +#define HW_ENET_EIMR_RD() (HW_ENET_EIMR.U) +#define HW_ENET_EIMR_WR(v) (HW_ENET_EIMR.U = (v)) +#define HW_ENET_EIMR_SET(v) (HW_ENET_EIMR_WR(HW_ENET_EIMR_RD() | (v))) +#define HW_ENET_EIMR_CLR(v) (HW_ENET_EIMR_WR(HW_ENET_EIMR_RD() & ~(v))) +#define HW_ENET_EIMR_TOG(v) (HW_ENET_EIMR_WR(HW_ENET_EIMR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_EIMR bitfields + */ + +/*! @name Register ENET_EIMR, field TS_TIMER[15] (RW) + * + * Corresponds to interrupt source TS_TIMER defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR TS_TIMER field reflects the state of + * the interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_TS_TIMER (15) //!< Bit position for ENET_EIMR_TS_TIMER. +#define BM_ENET_EIMR_TS_TIMER (0x00008000) //!< Bit mask for ENET_EIMR_TS_TIMER. + +//! @brief Get value of ENET_EIMR_TS_TIMER from a register value. +#define BG_ENET_EIMR_TS_TIMER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_TS_TIMER) >> BP_ENET_EIMR_TS_TIMER) + +//! @brief Format value for bitfield ENET_EIMR_TS_TIMER. +#define BF_ENET_EIMR_TS_TIMER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_TS_TIMER) & BM_ENET_EIMR_TS_TIMER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TS_TIMER field to a new value. +#define BW_ENET_EIMR_TS_TIMER(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_TS_TIMER) | BF_ENET_EIMR_TS_TIMER(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field TS_AVAIL[16] (RW) + * + * Corresponds to interrupt source TS_AVAIL defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR TS_AVAIL field reflects the state of + * the interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_TS_AVAIL (16) //!< Bit position for ENET_EIMR_TS_AVAIL. +#define BM_ENET_EIMR_TS_AVAIL (0x00010000) //!< Bit mask for ENET_EIMR_TS_AVAIL. + +//! @brief Get value of ENET_EIMR_TS_AVAIL from a register value. +#define BG_ENET_EIMR_TS_AVAIL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_TS_AVAIL) >> BP_ENET_EIMR_TS_AVAIL) + +//! @brief Format value for bitfield ENET_EIMR_TS_AVAIL. +#define BF_ENET_EIMR_TS_AVAIL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_TS_AVAIL) & BM_ENET_EIMR_TS_AVAIL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TS_AVAIL field to a new value. +#define BW_ENET_EIMR_TS_AVAIL(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_TS_AVAIL) | BF_ENET_EIMR_TS_AVAIL(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field WAKEUP[17] (RW) + * + * Corresponds to interrupt source WAKEUP defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR WAKEUP field reflects the state of + * the interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_WAKEUP (17) //!< Bit position for ENET_EIMR_WAKEUP. +#define BM_ENET_EIMR_WAKEUP (0x00020000) //!< Bit mask for ENET_EIMR_WAKEUP. + +//! @brief Get value of ENET_EIMR_WAKEUP from a register value. +#define BG_ENET_EIMR_WAKEUP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_WAKEUP) >> BP_ENET_EIMR_WAKEUP) + +//! @brief Format value for bitfield ENET_EIMR_WAKEUP. +#define BF_ENET_EIMR_WAKEUP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_WAKEUP) & BM_ENET_EIMR_WAKEUP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WAKEUP field to a new value. +#define BW_ENET_EIMR_WAKEUP(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_WAKEUP) | BF_ENET_EIMR_WAKEUP(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field PLR[18] (RW) + * + * Corresponds to interrupt source PLR defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR PLR field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_PLR (18) //!< Bit position for ENET_EIMR_PLR. +#define BM_ENET_EIMR_PLR (0x00040000) //!< Bit mask for ENET_EIMR_PLR. + +//! @brief Get value of ENET_EIMR_PLR from a register value. +#define BG_ENET_EIMR_PLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_PLR) >> BP_ENET_EIMR_PLR) + +//! @brief Format value for bitfield ENET_EIMR_PLR. +#define BF_ENET_EIMR_PLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_PLR) & BM_ENET_EIMR_PLR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PLR field to a new value. +#define BW_ENET_EIMR_PLR(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_PLR) | BF_ENET_EIMR_PLR(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field UN[19] (RW) + * + * Corresponds to interrupt source UN defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR UN field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_UN (19) //!< Bit position for ENET_EIMR_UN. +#define BM_ENET_EIMR_UN (0x00080000) //!< Bit mask for ENET_EIMR_UN. + +//! @brief Get value of ENET_EIMR_UN from a register value. +#define BG_ENET_EIMR_UN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_UN) >> BP_ENET_EIMR_UN) + +//! @brief Format value for bitfield ENET_EIMR_UN. +#define BF_ENET_EIMR_UN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_UN) & BM_ENET_EIMR_UN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the UN field to a new value. +#define BW_ENET_EIMR_UN(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_UN) | BF_ENET_EIMR_UN(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field RL[20] (RW) + * + * Corresponds to interrupt source RL defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR RL field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_RL (20) //!< Bit position for ENET_EIMR_RL. +#define BM_ENET_EIMR_RL (0x00100000) //!< Bit mask for ENET_EIMR_RL. + +//! @brief Get value of ENET_EIMR_RL from a register value. +#define BG_ENET_EIMR_RL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_RL) >> BP_ENET_EIMR_RL) + +//! @brief Format value for bitfield ENET_EIMR_RL. +#define BF_ENET_EIMR_RL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_RL) & BM_ENET_EIMR_RL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RL field to a new value. +#define BW_ENET_EIMR_RL(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_RL) | BF_ENET_EIMR_RL(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field LC[21] (RW) + * + * Corresponds to interrupt source LC defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR LC field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_LC (21) //!< Bit position for ENET_EIMR_LC. +#define BM_ENET_EIMR_LC (0x00200000) //!< Bit mask for ENET_EIMR_LC. + +//! @brief Get value of ENET_EIMR_LC from a register value. +#define BG_ENET_EIMR_LC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_LC) >> BP_ENET_EIMR_LC) + +//! @brief Format value for bitfield ENET_EIMR_LC. +#define BF_ENET_EIMR_LC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_LC) & BM_ENET_EIMR_LC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LC field to a new value. +#define BW_ENET_EIMR_LC(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_LC) | BF_ENET_EIMR_LC(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field EBERR[22] (RW) + * + * Corresponds to interrupt source EBERR defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR EBERR field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_EBERR (22) //!< Bit position for ENET_EIMR_EBERR. +#define BM_ENET_EIMR_EBERR (0x00400000) //!< Bit mask for ENET_EIMR_EBERR. + +//! @brief Get value of ENET_EIMR_EBERR from a register value. +#define BG_ENET_EIMR_EBERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_EBERR) >> BP_ENET_EIMR_EBERR) + +//! @brief Format value for bitfield ENET_EIMR_EBERR. +#define BF_ENET_EIMR_EBERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_EBERR) & BM_ENET_EIMR_EBERR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EBERR field to a new value. +#define BW_ENET_EIMR_EBERR(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_EBERR) | BF_ENET_EIMR_EBERR(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field MII[23] (RW) + * + * Corresponds to interrupt source MII defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR MII field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_MII (23) //!< Bit position for ENET_EIMR_MII. +#define BM_ENET_EIMR_MII (0x00800000) //!< Bit mask for ENET_EIMR_MII. + +//! @brief Get value of ENET_EIMR_MII from a register value. +#define BG_ENET_EIMR_MII(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_MII) >> BP_ENET_EIMR_MII) + +//! @brief Format value for bitfield ENET_EIMR_MII. +#define BF_ENET_EIMR_MII(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_MII) & BM_ENET_EIMR_MII) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MII field to a new value. +#define BW_ENET_EIMR_MII(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_MII) | BF_ENET_EIMR_MII(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field RXB[24] (RW) + * + * Corresponds to interrupt source RXB defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR RXB field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_RXB (24) //!< Bit position for ENET_EIMR_RXB. +#define BM_ENET_EIMR_RXB (0x01000000) //!< Bit mask for ENET_EIMR_RXB. + +//! @brief Get value of ENET_EIMR_RXB from a register value. +#define BG_ENET_EIMR_RXB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_RXB) >> BP_ENET_EIMR_RXB) + +//! @brief Format value for bitfield ENET_EIMR_RXB. +#define BF_ENET_EIMR_RXB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_RXB) & BM_ENET_EIMR_RXB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXB field to a new value. +#define BW_ENET_EIMR_RXB(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_RXB) | BF_ENET_EIMR_RXB(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field RXF[25] (RW) + * + * Corresponds to interrupt source RXF defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR RXF field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + */ +//@{ +#define BP_ENET_EIMR_RXF (25) //!< Bit position for ENET_EIMR_RXF. +#define BM_ENET_EIMR_RXF (0x02000000) //!< Bit mask for ENET_EIMR_RXF. + +//! @brief Get value of ENET_EIMR_RXF from a register value. +#define BG_ENET_EIMR_RXF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_RXF) >> BP_ENET_EIMR_RXF) + +//! @brief Format value for bitfield ENET_EIMR_RXF. +#define BF_ENET_EIMR_RXF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_RXF) & BM_ENET_EIMR_RXF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXF field to a new value. +#define BW_ENET_EIMR_RXF(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_RXF) | BF_ENET_EIMR_RXF(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field TXB[26] (RW) + * + * Corresponds to interrupt source TXB defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR TXF field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + * + * Values: + * - 0 - The corresponding interrupt source is masked. + * - 1 - The corresponding interrupt source is not masked. + */ +//@{ +#define BP_ENET_EIMR_TXB (26) //!< Bit position for ENET_EIMR_TXB. +#define BM_ENET_EIMR_TXB (0x04000000) //!< Bit mask for ENET_EIMR_TXB. + +//! @brief Get value of ENET_EIMR_TXB from a register value. +#define BG_ENET_EIMR_TXB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_TXB) >> BP_ENET_EIMR_TXB) + +//! @brief Format value for bitfield ENET_EIMR_TXB. +#define BF_ENET_EIMR_TXB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_TXB) & BM_ENET_EIMR_TXB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXB field to a new value. +#define BW_ENET_EIMR_TXB(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_TXB) | BF_ENET_EIMR_TXB(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field TXF[27] (RW) + * + * Corresponds to interrupt source TXF defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR TXF field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + * + * Values: + * - 0 - The corresponding interrupt source is masked. + * - 1 - The corresponding interrupt source is not masked. + */ +//@{ +#define BP_ENET_EIMR_TXF (27) //!< Bit position for ENET_EIMR_TXF. +#define BM_ENET_EIMR_TXF (0x08000000) //!< Bit mask for ENET_EIMR_TXF. + +//! @brief Get value of ENET_EIMR_TXF from a register value. +#define BG_ENET_EIMR_TXF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_TXF) >> BP_ENET_EIMR_TXF) + +//! @brief Format value for bitfield ENET_EIMR_TXF. +#define BF_ENET_EIMR_TXF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_TXF) & BM_ENET_EIMR_TXF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXF field to a new value. +#define BW_ENET_EIMR_TXF(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_TXF) | BF_ENET_EIMR_TXF(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field GRA[28] (RW) + * + * Corresponds to interrupt source GRA defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR GRA field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + * + * Values: + * - 0 - The corresponding interrupt source is masked. + * - 1 - The corresponding interrupt source is not masked. + */ +//@{ +#define BP_ENET_EIMR_GRA (28) //!< Bit position for ENET_EIMR_GRA. +#define BM_ENET_EIMR_GRA (0x10000000) //!< Bit mask for ENET_EIMR_GRA. + +//! @brief Get value of ENET_EIMR_GRA from a register value. +#define BG_ENET_EIMR_GRA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_GRA) >> BP_ENET_EIMR_GRA) + +//! @brief Format value for bitfield ENET_EIMR_GRA. +#define BF_ENET_EIMR_GRA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_GRA) & BM_ENET_EIMR_GRA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GRA field to a new value. +#define BW_ENET_EIMR_GRA(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_GRA) | BF_ENET_EIMR_GRA(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field BABT[29] (RW) + * + * Corresponds to interrupt source BABT defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR BABT field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + * + * Values: + * - 0 - The corresponding interrupt source is masked. + * - 1 - The corresponding interrupt source is not masked. + */ +//@{ +#define BP_ENET_EIMR_BABT (29) //!< Bit position for ENET_EIMR_BABT. +#define BM_ENET_EIMR_BABT (0x20000000) //!< Bit mask for ENET_EIMR_BABT. + +//! @brief Get value of ENET_EIMR_BABT from a register value. +#define BG_ENET_EIMR_BABT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_BABT) >> BP_ENET_EIMR_BABT) + +//! @brief Format value for bitfield ENET_EIMR_BABT. +#define BF_ENET_EIMR_BABT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_BABT) & BM_ENET_EIMR_BABT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BABT field to a new value. +#define BW_ENET_EIMR_BABT(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_BABT) | BF_ENET_EIMR_BABT(v))) +#endif +//@} + +/*! @name Register ENET_EIMR, field BABR[30] (RW) + * + * Corresponds to interrupt source BABR defined by the EIR register and determines whether an + * interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal + * generated by the interrupting source. The corresponding EIR BABR field reflects the state of the + * interrupt signal even if the corresponding EIMR field is cleared. + * + * Values: + * - 0 - The corresponding interrupt source is masked. + * - 1 - The corresponding interrupt source is not masked. + */ +//@{ +#define BP_ENET_EIMR_BABR (30) //!< Bit position for ENET_EIMR_BABR. +#define BM_ENET_EIMR_BABR (0x40000000) //!< Bit mask for ENET_EIMR_BABR. + +//! @brief Get value of ENET_EIMR_BABR from a register value. +#define BG_ENET_EIMR_BABR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_EIMR_BABR) >> BP_ENET_EIMR_BABR) + +//! @brief Format value for bitfield ENET_EIMR_BABR. +#define BF_ENET_EIMR_BABR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_EIMR_BABR) & BM_ENET_EIMR_BABR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BABR field to a new value. +#define BW_ENET_EIMR_BABR(v) (HW_ENET_EIMR_WR((HW_ENET_EIMR_RD() & ~BM_ENET_EIMR_BABR) | BF_ENET_EIMR_BABR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_RDAR - Receive Descriptor Active Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW) + * + * Reset value: 0x00000000 + * + * RDAR is a command register, written by the user, to indicate that the receive descriptor ring has + * been updated, that is, that the driver produced empty receive buffers with the empty bit set. + */ +typedef union _hw_enet_rdar +{ + reg32_t U; + struct _hw_enet_rdar_bitfields + { + unsigned RESERVED0 : 24; //!< [23:0] + unsigned RDAR : 1; //!< [24] Receive Descriptor Active + unsigned RESERVED1 : 7; //!< [31:25] + } B; +} hw_enet_rdar_t; +#endif + +/*! + * @name Constants and macros for entire ENET_RDAR register + */ +//@{ +#define HW_ENET_RDAR_ADDR (REGS_ENET_BASE + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_RDAR (*(volatile hw_enet_rdar_t *) HW_ENET_RDAR_ADDR) +#define HW_ENET_RDAR_RD() (HW_ENET_RDAR.U) +#define HW_ENET_RDAR_WR(v) (HW_ENET_RDAR.U = (v)) +#define HW_ENET_RDAR_SET(v) (HW_ENET_RDAR_WR(HW_ENET_RDAR_RD() | (v))) +#define HW_ENET_RDAR_CLR(v) (HW_ENET_RDAR_WR(HW_ENET_RDAR_RD() & ~(v))) +#define HW_ENET_RDAR_TOG(v) (HW_ENET_RDAR_WR(HW_ENET_RDAR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_RDAR bitfields + */ + +/*! @name Register ENET_RDAR, field RDAR[24] (RW) + * + * Always set to 1 when this register is written, regardless of the value written. This field is + * cleared by the MAC device when no additional empty descriptors remain in the receive ring. It is + * also cleared when ECR[ETHEREN] transitions from set to cleared or when ECR[RESET] is set. + */ +//@{ +#define BP_ENET_RDAR_RDAR (24) //!< Bit position for ENET_RDAR_RDAR. +#define BM_ENET_RDAR_RDAR (0x01000000) //!< Bit mask for ENET_RDAR_RDAR. + +//! @brief Get value of ENET_RDAR_RDAR from a register value. +#define BG_ENET_RDAR_RDAR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RDAR_RDAR) >> BP_ENET_RDAR_RDAR) + +//! @brief Format value for bitfield ENET_RDAR_RDAR. +#define BF_ENET_RDAR_RDAR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RDAR_RDAR) & BM_ENET_RDAR_RDAR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RDAR field to a new value. +#define BW_ENET_RDAR_RDAR(v) (HW_ENET_RDAR_WR((HW_ENET_RDAR_RD() & ~BM_ENET_RDAR_RDAR) | BF_ENET_RDAR_RDAR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_TDAR - Transmit Descriptor Active Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW) + * + * Reset value: 0x00000000 + * + * The TDAR is a command register that the user writes to indicate that the transmit descriptor ring + * has been updated, that is, that transmit buffers have been produced by the driver with the ready + * bit set in the buffer descriptor. The TDAR register is cleared at reset, when ECR[ETHEREN] + * transitions from set to cleared, or when ECR[RESET] is set. + */ +typedef union _hw_enet_tdar +{ + reg32_t U; + struct _hw_enet_tdar_bitfields + { + unsigned RESERVED0 : 24; //!< [23:0] + unsigned TDAR : 1; //!< [24] Transmit Descriptor Active + unsigned RESERVED1 : 7; //!< [31:25] + } B; +} hw_enet_tdar_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TDAR register + */ +//@{ +#define HW_ENET_TDAR_ADDR (REGS_ENET_BASE + 0x14) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TDAR (*(volatile hw_enet_tdar_t *) HW_ENET_TDAR_ADDR) +#define HW_ENET_TDAR_RD() (HW_ENET_TDAR.U) +#define HW_ENET_TDAR_WR(v) (HW_ENET_TDAR.U = (v)) +#define HW_ENET_TDAR_SET(v) (HW_ENET_TDAR_WR(HW_ENET_TDAR_RD() | (v))) +#define HW_ENET_TDAR_CLR(v) (HW_ENET_TDAR_WR(HW_ENET_TDAR_RD() & ~(v))) +#define HW_ENET_TDAR_TOG(v) (HW_ENET_TDAR_WR(HW_ENET_TDAR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TDAR bitfields + */ + +/*! @name Register ENET_TDAR, field TDAR[24] (RW) + * + * Always set to 1 when this register is written, regardless of the value written. This bit is + * cleared by the MAC device when no additional ready descriptors remain in the transmit ring. Also + * cleared when ECR[ETHEREN] transitions from set to cleared or when ECR[RESET] is set. + */ +//@{ +#define BP_ENET_TDAR_TDAR (24) //!< Bit position for ENET_TDAR_TDAR. +#define BM_ENET_TDAR_TDAR (0x01000000) //!< Bit mask for ENET_TDAR_TDAR. + +//! @brief Get value of ENET_TDAR_TDAR from a register value. +#define BG_ENET_TDAR_TDAR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TDAR_TDAR) >> BP_ENET_TDAR_TDAR) + +//! @brief Format value for bitfield ENET_TDAR_TDAR. +#define BF_ENET_TDAR_TDAR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TDAR_TDAR) & BM_ENET_TDAR_TDAR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TDAR field to a new value. +#define BW_ENET_TDAR_TDAR(v) (HW_ENET_TDAR_WR((HW_ENET_TDAR_RD() & ~BM_ENET_TDAR_TDAR) | BF_ENET_TDAR_TDAR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_ECR - Ethernet Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_ECR - Ethernet Control Register (RW) + * + * Reset value: 0xf0000000 + * + * ECR is a read/write user register, though hardware may also alter fields in this register. It + * controls many of the high level features of the Ethernet MAC, including legacy FEC support + * through the EN1588 field. + */ +typedef union _hw_enet_ecr +{ + reg32_t U; + struct _hw_enet_ecr_bitfields + { + unsigned RESET : 1; //!< [0] Ethernet MAC Reset + unsigned ETHEREN : 1; //!< [1] Ethernet Enable + unsigned MAGICEN : 1; //!< [2] Magic Packet Detection Enable + unsigned SLEEP : 1; //!< [3] Sleep Mode Enable + unsigned EN1588 : 1; //!< [4] EN1588 Enable + unsigned RESERVED0 : 1; //!< [5] Reserved. + unsigned DBGEN : 1; //!< [6] Debug Enable + unsigned STOPEN : 1; //!< [7] STOPEN Signal Control + unsigned RESERVED1 : 24; //!< [31:8] Reserved. + } B; +} hw_enet_ecr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_ECR register + */ +//@{ +#define HW_ENET_ECR_ADDR (REGS_ENET_BASE + 0x24) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_ECR (*(volatile hw_enet_ecr_t *) HW_ENET_ECR_ADDR) +#define HW_ENET_ECR_RD() (HW_ENET_ECR.U) +#define HW_ENET_ECR_WR(v) (HW_ENET_ECR.U = (v)) +#define HW_ENET_ECR_SET(v) (HW_ENET_ECR_WR(HW_ENET_ECR_RD() | (v))) +#define HW_ENET_ECR_CLR(v) (HW_ENET_ECR_WR(HW_ENET_ECR_RD() & ~(v))) +#define HW_ENET_ECR_TOG(v) (HW_ENET_ECR_WR(HW_ENET_ECR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_ECR bitfields + */ + +/*! @name Register ENET_ECR, field RESET[0] (RW) + * + * When this field is set, it clears the ETHEREN field. + */ +//@{ +#define BP_ENET_ECR_RESET (0) //!< Bit position for ENET_ECR_RESET. +#define BM_ENET_ECR_RESET (0x00000001) //!< Bit mask for ENET_ECR_RESET. + +//! @brief Get value of ENET_ECR_RESET from a register value. +#define BG_ENET_ECR_RESET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ECR_RESET) >> BP_ENET_ECR_RESET) + +//! @brief Format value for bitfield ENET_ECR_RESET. +#define BF_ENET_ECR_RESET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ECR_RESET) & BM_ENET_ECR_RESET) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RESET field to a new value. +#define BW_ENET_ECR_RESET(v) (HW_ENET_ECR_WR((HW_ENET_ECR_RD() & ~BM_ENET_ECR_RESET) | BF_ENET_ECR_RESET(v))) +#endif +//@} + +/*! @name Register ENET_ECR, field ETHEREN[1] (RW) + * + * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer descriptors for an + * aborted transmit frame are not updated. The uDMA, buffer descriptor, and FIFO control logic are + * reset, including the buffer descriptor and FIFO pointers. Hardware clears this field under the + * following conditions: RESET is set by software An error condition causes the EBERR field to set. + * ETHEREN must be set at the very last step during ENET configuration/setup/initialization, only + * after all other ENET-related registers have been configured. + * + * Values: + * - 0 - Reception immediately stops and transmission stops after a bad CRC is appended to any currently + * transmitted frame. + * - 1 - MAC is enabled, and reception and transmission are possible. + */ +//@{ +#define BP_ENET_ECR_ETHEREN (1) //!< Bit position for ENET_ECR_ETHEREN. +#define BM_ENET_ECR_ETHEREN (0x00000002) //!< Bit mask for ENET_ECR_ETHEREN. + +//! @brief Get value of ENET_ECR_ETHEREN from a register value. +#define BG_ENET_ECR_ETHEREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ECR_ETHEREN) >> BP_ENET_ECR_ETHEREN) + +//! @brief Format value for bitfield ENET_ECR_ETHEREN. +#define BF_ENET_ECR_ETHEREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ECR_ETHEREN) & BM_ENET_ECR_ETHEREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ETHEREN field to a new value. +#define BW_ENET_ECR_ETHEREN(v) (HW_ENET_ECR_WR((HW_ENET_ECR_RD() & ~BM_ENET_ECR_ETHEREN) | BF_ENET_ECR_ETHEREN(v))) +#endif +//@} + +/*! @name Register ENET_ECR, field MAGICEN[2] (RW) + * + * Enables/disables magic packet detection. MAGICEN is relevant only if the SLEEP field is set. If + * MAGICEN is set, changing the SLEEP field enables/disables sleep mode and magic packet detection. + * + * Values: + * - 0 - Magic detection logic disabled. + * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ +//@{ +#define BP_ENET_ECR_MAGICEN (2) //!< Bit position for ENET_ECR_MAGICEN. +#define BM_ENET_ECR_MAGICEN (0x00000004) //!< Bit mask for ENET_ECR_MAGICEN. + +//! @brief Get value of ENET_ECR_MAGICEN from a register value. +#define BG_ENET_ECR_MAGICEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ECR_MAGICEN) >> BP_ENET_ECR_MAGICEN) + +//! @brief Format value for bitfield ENET_ECR_MAGICEN. +#define BF_ENET_ECR_MAGICEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ECR_MAGICEN) & BM_ENET_ECR_MAGICEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MAGICEN field to a new value. +#define BW_ENET_ECR_MAGICEN(v) (HW_ENET_ECR_WR((HW_ENET_ECR_RD() & ~BM_ENET_ECR_MAGICEN) | BF_ENET_ECR_MAGICEN(v))) +#endif +//@} + +/*! @name Register ENET_ECR, field SLEEP[3] (RW) + * + * Values: + * - 0 - Normal operating mode. + * - 1 - Sleep mode. + */ +//@{ +#define BP_ENET_ECR_SLEEP (3) //!< Bit position for ENET_ECR_SLEEP. +#define BM_ENET_ECR_SLEEP (0x00000008) //!< Bit mask for ENET_ECR_SLEEP. + +//! @brief Get value of ENET_ECR_SLEEP from a register value. +#define BG_ENET_ECR_SLEEP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ECR_SLEEP) >> BP_ENET_ECR_SLEEP) + +//! @brief Format value for bitfield ENET_ECR_SLEEP. +#define BF_ENET_ECR_SLEEP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ECR_SLEEP) & BM_ENET_ECR_SLEEP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SLEEP field to a new value. +#define BW_ENET_ECR_SLEEP(v) (HW_ENET_ECR_WR((HW_ENET_ECR_RD() & ~BM_ENET_ECR_SLEEP) | BF_ENET_ECR_SLEEP(v))) +#endif +//@} + +/*! @name Register ENET_ECR, field EN1588[4] (RW) + * + * Enables enhanced functionality of the MAC. + * + * Values: + * - 0 - Legacy FEC buffer descriptors and functions enabled. + * - 1 - Enhanced frame time-stamping functions enabled. + */ +//@{ +#define BP_ENET_ECR_EN1588 (4) //!< Bit position for ENET_ECR_EN1588. +#define BM_ENET_ECR_EN1588 (0x00000010) //!< Bit mask for ENET_ECR_EN1588. + +//! @brief Get value of ENET_ECR_EN1588 from a register value. +#define BG_ENET_ECR_EN1588(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ECR_EN1588) >> BP_ENET_ECR_EN1588) + +//! @brief Format value for bitfield ENET_ECR_EN1588. +#define BF_ENET_ECR_EN1588(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ECR_EN1588) & BM_ENET_ECR_EN1588) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN1588 field to a new value. +#define BW_ENET_ECR_EN1588(v) (HW_ENET_ECR_WR((HW_ENET_ECR_RD() & ~BM_ENET_ECR_EN1588) | BF_ENET_ECR_EN1588(v))) +#endif +//@} + +/*! @name Register ENET_ECR, field DBGEN[6] (RW) + * + * Enables the MAC to enter hardware freeze mode when the device enters debug mode. + * + * Values: + * - 0 - MAC continues operation in debug mode. + * - 1 - MAC enters hardware freeze mode when the processor is in debug mode. + */ +//@{ +#define BP_ENET_ECR_DBGEN (6) //!< Bit position for ENET_ECR_DBGEN. +#define BM_ENET_ECR_DBGEN (0x00000040) //!< Bit mask for ENET_ECR_DBGEN. + +//! @brief Get value of ENET_ECR_DBGEN from a register value. +#define BG_ENET_ECR_DBGEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ECR_DBGEN) >> BP_ENET_ECR_DBGEN) + +//! @brief Format value for bitfield ENET_ECR_DBGEN. +#define BF_ENET_ECR_DBGEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ECR_DBGEN) & BM_ENET_ECR_DBGEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DBGEN field to a new value. +#define BW_ENET_ECR_DBGEN(v) (HW_ENET_ECR_WR((HW_ENET_ECR_RD() & ~BM_ENET_ECR_DBGEN) | BF_ENET_ECR_DBGEN(v))) +#endif +//@} + +/*! @name Register ENET_ECR, field STOPEN[7] (RW) + * + * Controls device behavior in doze mode. In doze mode, if this field is set then all the clocks of + * the ENET assembly are disabled, except the RMII clock. Doze mode is similar to a conditional stop + * mode entry for the ENET assembly depending on ECR[STOPEN]. If module clocks are gated in this + * mode, the module can still wake the system after receiving a magic packet in stop mode. MAGICEN + * must be set prior to entering sleep/stop mode. + */ +//@{ +#define BP_ENET_ECR_STOPEN (7) //!< Bit position for ENET_ECR_STOPEN. +#define BM_ENET_ECR_STOPEN (0x00000080) //!< Bit mask for ENET_ECR_STOPEN. + +//! @brief Get value of ENET_ECR_STOPEN from a register value. +#define BG_ENET_ECR_STOPEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ECR_STOPEN) >> BP_ENET_ECR_STOPEN) + +//! @brief Format value for bitfield ENET_ECR_STOPEN. +#define BF_ENET_ECR_STOPEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ECR_STOPEN) & BM_ENET_ECR_STOPEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STOPEN field to a new value. +#define BW_ENET_ECR_STOPEN(v) (HW_ENET_ECR_WR((HW_ENET_ECR_RD() & ~BM_ENET_ECR_STOPEN) | BF_ENET_ECR_STOPEN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_MMFR - MII Management Frame Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_MMFR - MII Management Frame Register (RW) + * + * Reset value: 0x00000000 + * + * Writing to MMFR triggers a management frame transaction to the PHY device unless MSCR is + * programmed to zero. If MSCR is changed from zero to non-zero during a write to MMFR, an MII frame + * is generated with the data previously written to the MMFR. This allows MMFR and MSCR to be + * programmed in either order if MSCR is currently zero. If the MMFR register is written while frame + * generation is in progress, the frame contents are altered. Software must use the EIR[MII] + * interrupt indication to avoid writing to the MMFR register while frame generation is in progress. + */ +typedef union _hw_enet_mmfr +{ + reg32_t U; + struct _hw_enet_mmfr_bitfields + { + unsigned DATA : 16; //!< [15:0] Management Frame Data + unsigned TA : 2; //!< [17:16] Turn Around + unsigned RA : 5; //!< [22:18] Register Address + unsigned PA : 5; //!< [27:23] PHY Address + unsigned OP : 2; //!< [29:28] Operation Code + unsigned ST : 2; //!< [31:30] Start Of Frame Delimiter + } B; +} hw_enet_mmfr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_MMFR register + */ +//@{ +#define HW_ENET_MMFR_ADDR (REGS_ENET_BASE + 0x40) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_MMFR (*(volatile hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR) +#define HW_ENET_MMFR_RD() (HW_ENET_MMFR.U) +#define HW_ENET_MMFR_WR(v) (HW_ENET_MMFR.U = (v)) +#define HW_ENET_MMFR_SET(v) (HW_ENET_MMFR_WR(HW_ENET_MMFR_RD() | (v))) +#define HW_ENET_MMFR_CLR(v) (HW_ENET_MMFR_WR(HW_ENET_MMFR_RD() & ~(v))) +#define HW_ENET_MMFR_TOG(v) (HW_ENET_MMFR_WR(HW_ENET_MMFR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_MMFR bitfields + */ + +/*! @name Register ENET_MMFR, field DATA[15:0] (RW) + * + * This is the field for data to be written to or read from the PHY register. + */ +//@{ +#define BP_ENET_MMFR_DATA (0) //!< Bit position for ENET_MMFR_DATA. +#define BM_ENET_MMFR_DATA (0x0000ffff) //!< Bit mask for ENET_MMFR_DATA. + +//! @brief Get value of ENET_MMFR_DATA from a register value. +#define BG_ENET_MMFR_DATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MMFR_DATA) >> BP_ENET_MMFR_DATA) + +//! @brief Format value for bitfield ENET_MMFR_DATA. +#define BF_ENET_MMFR_DATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MMFR_DATA) & BM_ENET_MMFR_DATA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA field to a new value. +#define BW_ENET_MMFR_DATA(v) (HW_ENET_MMFR_WR((HW_ENET_MMFR_RD() & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v))) +#endif +//@} + +/*! @name Register ENET_MMFR, field TA[17:16] (RW) + * + * This field must be programmed to 10 to generate a valid MII management frame. + */ +//@{ +#define BP_ENET_MMFR_TA (16) //!< Bit position for ENET_MMFR_TA. +#define BM_ENET_MMFR_TA (0x00030000) //!< Bit mask for ENET_MMFR_TA. + +//! @brief Get value of ENET_MMFR_TA from a register value. +#define BG_ENET_MMFR_TA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MMFR_TA) >> BP_ENET_MMFR_TA) + +//! @brief Format value for bitfield ENET_MMFR_TA. +#define BF_ENET_MMFR_TA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MMFR_TA) & BM_ENET_MMFR_TA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TA field to a new value. +#define BW_ENET_MMFR_TA(v) (HW_ENET_MMFR_WR((HW_ENET_MMFR_RD() & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v))) +#endif +//@} + +/*! @name Register ENET_MMFR, field RA[22:18] (RW) + * + * Specifies one of up to 32 registers within the specified PHY device. + */ +//@{ +#define BP_ENET_MMFR_RA (18) //!< Bit position for ENET_MMFR_RA. +#define BM_ENET_MMFR_RA (0x007c0000) //!< Bit mask for ENET_MMFR_RA. + +//! @brief Get value of ENET_MMFR_RA from a register value. +#define BG_ENET_MMFR_RA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MMFR_RA) >> BP_ENET_MMFR_RA) + +//! @brief Format value for bitfield ENET_MMFR_RA. +#define BF_ENET_MMFR_RA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MMFR_RA) & BM_ENET_MMFR_RA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RA field to a new value. +#define BW_ENET_MMFR_RA(v) (HW_ENET_MMFR_WR((HW_ENET_MMFR_RD() & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v))) +#endif +//@} + +/*! @name Register ENET_MMFR, field PA[27:23] (RW) + * + * Specifies one of up to 32 attached PHY devices. + */ +//@{ +#define BP_ENET_MMFR_PA (23) //!< Bit position for ENET_MMFR_PA. +#define BM_ENET_MMFR_PA (0x0f800000) //!< Bit mask for ENET_MMFR_PA. + +//! @brief Get value of ENET_MMFR_PA from a register value. +#define BG_ENET_MMFR_PA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MMFR_PA) >> BP_ENET_MMFR_PA) + +//! @brief Format value for bitfield ENET_MMFR_PA. +#define BF_ENET_MMFR_PA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MMFR_PA) & BM_ENET_MMFR_PA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PA field to a new value. +#define BW_ENET_MMFR_PA(v) (HW_ENET_MMFR_WR((HW_ENET_MMFR_RD() & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v))) +#endif +//@} + +/*! @name Register ENET_MMFR, field OP[29:28] (RW) + * + * Determines the frame operation. + * + * Values: + * - 00 - Write frame operation, but not MII compliant. + * - 01 - Write frame operation for a valid MII management frame. + * - 10 - Read frame operation for a valid MII management frame. + * - 11 - Read frame operation, but not MII compliant. + */ +//@{ +#define BP_ENET_MMFR_OP (28) //!< Bit position for ENET_MMFR_OP. +#define BM_ENET_MMFR_OP (0x30000000) //!< Bit mask for ENET_MMFR_OP. + +//! @brief Get value of ENET_MMFR_OP from a register value. +#define BG_ENET_MMFR_OP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MMFR_OP) >> BP_ENET_MMFR_OP) + +//! @brief Format value for bitfield ENET_MMFR_OP. +#define BF_ENET_MMFR_OP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MMFR_OP) & BM_ENET_MMFR_OP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OP field to a new value. +#define BW_ENET_MMFR_OP(v) (HW_ENET_MMFR_WR((HW_ENET_MMFR_RD() & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v))) +#endif +//@} + +/*! @name Register ENET_MMFR, field ST[31:30] (RW) + * + * These fields must be programmed to 01 for a valid MII management frame. + */ +//@{ +#define BP_ENET_MMFR_ST (30) //!< Bit position for ENET_MMFR_ST. +#define BM_ENET_MMFR_ST (0xc0000000) //!< Bit mask for ENET_MMFR_ST. + +//! @brief Get value of ENET_MMFR_ST from a register value. +#define BG_ENET_MMFR_ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MMFR_ST) >> BP_ENET_MMFR_ST) + +//! @brief Format value for bitfield ENET_MMFR_ST. +#define BF_ENET_MMFR_ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MMFR_ST) & BM_ENET_MMFR_ST) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ST field to a new value. +#define BW_ENET_MMFR_ST(v) (HW_ENET_MMFR_WR((HW_ENET_MMFR_RD() & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_MSCR - MII Speed Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_MSCR - MII Speed Control Register (RW) + * + * Reset value: 0x00000000 + * + * MSCR provides control of the MII clock (MDC pin) frequency and allows a preamble drop on the MII + * management frame. The MII_SPEED field must be programmed with a value to provide an MDC frequency + * of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The + * MII_SPEED must be set to a non-zero value to source a read or write management frame. After the + * management frame is complete, the MSCR register may optionally be cleared to turn off MDC. The + * MDC signal generated has a 50% duty cycle except when MII_SPEED changes during operation. This + * change takes effect following a rising or falling edge of MDC. If the internal module clock is 25 + * MHz, programming this register to 0x0000_0004 results in an MDC as stated in the following + * equation: 25 MHz / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for + * MII_SPEED as a function of internal module clock frequency. Programming Examples for MSCR + * Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz 0x4 2.50 MHz 33 MHz 0x6 2.36 + * MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz 0xD 2.36 MHz + */ +typedef union _hw_enet_mscr +{ + reg32_t U; + struct _hw_enet_mscr_bitfields + { + unsigned RESERVED0 : 1; //!< [0] + unsigned MII_SPEED : 6; //!< [6:1] MII Speed + unsigned DIS_PRE : 1; //!< [7] Disable Preamble + unsigned HOLDTIME : 3; //!< [10:8] Holdtime On MDIO Output + unsigned RESERVED1 : 21; //!< [31:11] + } B; +} hw_enet_mscr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_MSCR register + */ +//@{ +#define HW_ENET_MSCR_ADDR (REGS_ENET_BASE + 0x44) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_MSCR (*(volatile hw_enet_mscr_t *) HW_ENET_MSCR_ADDR) +#define HW_ENET_MSCR_RD() (HW_ENET_MSCR.U) +#define HW_ENET_MSCR_WR(v) (HW_ENET_MSCR.U = (v)) +#define HW_ENET_MSCR_SET(v) (HW_ENET_MSCR_WR(HW_ENET_MSCR_RD() | (v))) +#define HW_ENET_MSCR_CLR(v) (HW_ENET_MSCR_WR(HW_ENET_MSCR_RD() & ~(v))) +#define HW_ENET_MSCR_TOG(v) (HW_ENET_MSCR_WR(HW_ENET_MSCR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_MSCR bitfields + */ + +/*! @name Register ENET_MSCR, field MII_SPEED[6:1] (RW) + * + * Controls the frequency of the MII management interface clock (MDC) relative to the internal + * module clock. A value of 0 in this field turns off MDC and leaves it in low voltage state. Any + * non-zero value results in the MDC frequency of: 1/((MII_SPEED + 1) x 2) of the internal module + * clock frequency + */ +//@{ +#define BP_ENET_MSCR_MII_SPEED (1) //!< Bit position for ENET_MSCR_MII_SPEED. +#define BM_ENET_MSCR_MII_SPEED (0x0000007e) //!< Bit mask for ENET_MSCR_MII_SPEED. + +//! @brief Get value of ENET_MSCR_MII_SPEED from a register value. +#define BG_ENET_MSCR_MII_SPEED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MSCR_MII_SPEED) >> BP_ENET_MSCR_MII_SPEED) + +//! @brief Format value for bitfield ENET_MSCR_MII_SPEED. +#define BF_ENET_MSCR_MII_SPEED(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MSCR_MII_SPEED) & BM_ENET_MSCR_MII_SPEED) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MII_SPEED field to a new value. +#define BW_ENET_MSCR_MII_SPEED(v) (HW_ENET_MSCR_WR((HW_ENET_MSCR_RD() & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v))) +#endif +//@} + +/*! @name Register ENET_MSCR, field DIS_PRE[7] (RW) + * + * Enables/disables prepending a preamble to the MII management frame. The MII standard allows the + * preamble to be dropped if the attached PHY devices do not require it. + * + * Values: + * - 0 - Preamble enabled. + * - 1 - Preamble (32 ones) is not prepended to the MII management frame. + */ +//@{ +#define BP_ENET_MSCR_DIS_PRE (7) //!< Bit position for ENET_MSCR_DIS_PRE. +#define BM_ENET_MSCR_DIS_PRE (0x00000080) //!< Bit mask for ENET_MSCR_DIS_PRE. + +//! @brief Get value of ENET_MSCR_DIS_PRE from a register value. +#define BG_ENET_MSCR_DIS_PRE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MSCR_DIS_PRE) >> BP_ENET_MSCR_DIS_PRE) + +//! @brief Format value for bitfield ENET_MSCR_DIS_PRE. +#define BF_ENET_MSCR_DIS_PRE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MSCR_DIS_PRE) & BM_ENET_MSCR_DIS_PRE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DIS_PRE field to a new value. +#define BW_ENET_MSCR_DIS_PRE(v) (HW_ENET_MSCR_WR((HW_ENET_MSCR_RD() & ~BM_ENET_MSCR_DIS_PRE) | BF_ENET_MSCR_DIS_PRE(v))) +#endif +//@} + +/*! @name Register ENET_MSCR, field HOLDTIME[10:8] (RW) + * + * IEEE802.3 clause 22 defines a minimum of 10 ns for the holdtime on the MDIO output. Depending on + * the host bus frequency, the setting may need to be increased. + * + * Values: + * - 000 - 1 internal module clock cycle + * - 001 - 2 internal module clock cycles + * - 010 - 3 internal module clock cycles + * - 111 - 8 internal module clock cycles + */ +//@{ +#define BP_ENET_MSCR_HOLDTIME (8) //!< Bit position for ENET_MSCR_HOLDTIME. +#define BM_ENET_MSCR_HOLDTIME (0x00000700) //!< Bit mask for ENET_MSCR_HOLDTIME. + +//! @brief Get value of ENET_MSCR_HOLDTIME from a register value. +#define BG_ENET_MSCR_HOLDTIME(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MSCR_HOLDTIME) >> BP_ENET_MSCR_HOLDTIME) + +//! @brief Format value for bitfield ENET_MSCR_HOLDTIME. +#define BF_ENET_MSCR_HOLDTIME(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MSCR_HOLDTIME) & BM_ENET_MSCR_HOLDTIME) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HOLDTIME field to a new value. +#define BW_ENET_MSCR_HOLDTIME(v) (HW_ENET_MSCR_WR((HW_ENET_MSCR_RD() & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_MIBC - MIB Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_MIBC - MIB Control Register (RW) + * + * Reset value: 0xc0000000 + * + * MIBC is a read/write register controlling and observing the state of the MIB block. Access this + * register to disable the MIB block operation or clear the MIB counters. The MIB_DIS field resets + * to 1. + */ +typedef union _hw_enet_mibc +{ + reg32_t U; + struct _hw_enet_mibc_bitfields + { + unsigned RESERVED0 : 29; //!< [28:0] + unsigned MIB_CLEAR : 1; //!< [29] MIB Clear + unsigned MIB_IDLE : 1; //!< [30] MIB Idle + unsigned MIB_DIS : 1; //!< [31] Disable MIB Logic + } B; +} hw_enet_mibc_t; +#endif + +/*! + * @name Constants and macros for entire ENET_MIBC register + */ +//@{ +#define HW_ENET_MIBC_ADDR (REGS_ENET_BASE + 0x64) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_MIBC (*(volatile hw_enet_mibc_t *) HW_ENET_MIBC_ADDR) +#define HW_ENET_MIBC_RD() (HW_ENET_MIBC.U) +#define HW_ENET_MIBC_WR(v) (HW_ENET_MIBC.U = (v)) +#define HW_ENET_MIBC_SET(v) (HW_ENET_MIBC_WR(HW_ENET_MIBC_RD() | (v))) +#define HW_ENET_MIBC_CLR(v) (HW_ENET_MIBC_WR(HW_ENET_MIBC_RD() & ~(v))) +#define HW_ENET_MIBC_TOG(v) (HW_ENET_MIBC_WR(HW_ENET_MIBC_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_MIBC bitfields + */ + +/*! @name Register ENET_MIBC, field MIB_CLEAR[29] (RW) + * + * If set, all statistics counters are reset to 0. This field is not self-clearing. To clear the MIB + * counters set and then clear the field. + */ +//@{ +#define BP_ENET_MIBC_MIB_CLEAR (29) //!< Bit position for ENET_MIBC_MIB_CLEAR. +#define BM_ENET_MIBC_MIB_CLEAR (0x20000000) //!< Bit mask for ENET_MIBC_MIB_CLEAR. + +//! @brief Get value of ENET_MIBC_MIB_CLEAR from a register value. +#define BG_ENET_MIBC_MIB_CLEAR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MIBC_MIB_CLEAR) >> BP_ENET_MIBC_MIB_CLEAR) + +//! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR. +#define BF_ENET_MIBC_MIB_CLEAR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MIBC_MIB_CLEAR) & BM_ENET_MIBC_MIB_CLEAR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MIB_CLEAR field to a new value. +#define BW_ENET_MIBC_MIB_CLEAR(v) (HW_ENET_MIBC_WR((HW_ENET_MIBC_RD() & ~BM_ENET_MIBC_MIB_CLEAR) | BF_ENET_MIBC_MIB_CLEAR(v))) +#endif +//@} + +/*! @name Register ENET_MIBC, field MIB_IDLE[30] (RO) + * + * If this status field is set, the MIB block is not currently updating any MIB counters. + */ +//@{ +#define BP_ENET_MIBC_MIB_IDLE (30) //!< Bit position for ENET_MIBC_MIB_IDLE. +#define BM_ENET_MIBC_MIB_IDLE (0x40000000) //!< Bit mask for ENET_MIBC_MIB_IDLE. + +//! @brief Get value of ENET_MIBC_MIB_IDLE from a register value. +#define BG_ENET_MIBC_MIB_IDLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MIBC_MIB_IDLE) >> BP_ENET_MIBC_MIB_IDLE) +//@} + +/*! @name Register ENET_MIBC, field MIB_DIS[31] (RW) + * + * If this control field is set, the MIB logic halts and does not update any MIB counters. + */ +//@{ +#define BP_ENET_MIBC_MIB_DIS (31) //!< Bit position for ENET_MIBC_MIB_DIS. +#define BM_ENET_MIBC_MIB_DIS (0x80000000) //!< Bit mask for ENET_MIBC_MIB_DIS. + +//! @brief Get value of ENET_MIBC_MIB_DIS from a register value. +#define BG_ENET_MIBC_MIB_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MIBC_MIB_DIS) >> BP_ENET_MIBC_MIB_DIS) + +//! @brief Format value for bitfield ENET_MIBC_MIB_DIS. +#define BF_ENET_MIBC_MIB_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MIBC_MIB_DIS) & BM_ENET_MIBC_MIB_DIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MIB_DIS field to a new value. +#define BW_ENET_MIBC_MIB_DIS(v) (HW_ENET_MIBC_WR((HW_ENET_MIBC_RD() & ~BM_ENET_MIBC_MIB_DIS) | BF_ENET_MIBC_MIB_DIS(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_RCR - Receive Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_RCR - Receive Control Register (RW) + * + * Reset value: 0x05ee0001 + */ +typedef union _hw_enet_rcr +{ + reg32_t U; + struct _hw_enet_rcr_bitfields + { + unsigned LOOP : 1; //!< [0] Internal Loopback + unsigned DRT : 1; //!< [1] Disable Receive On Transmit + unsigned MII_MODE : 1; //!< [2] Media Independent Interface Mode + unsigned PROM : 1; //!< [3] Promiscuous Mode + unsigned BC_REJ : 1; //!< [4] Broadcast Frame Reject + unsigned FCE : 1; //!< [5] Flow Control Enable + unsigned RESERVED0 : 2; //!< [7:6] Reserved. + unsigned RMII_MODE : 1; //!< [8] RMII Mode Enable + unsigned RMII_10T : 1; //!< [9] Enables 10-Mbps mode of the RMII . + unsigned RESERVED1 : 2; //!< [11:10] + unsigned PADEN : 1; //!< [12] Enable Frame Padding Remove On Receive + unsigned PAUFWD : 1; //!< [13] Terminate/Forward Pause Frames + unsigned CRCFWD : 1; //!< [14] Terminate/Forward Received CRC + unsigned CFEN : 1; //!< [15] MAC Control Frame Enable + unsigned MAX_FL : 14; //!< [29:16] Maximum Frame Length + unsigned NLC : 1; //!< [30] Payload Length Check Disable + unsigned GRS : 1; //!< [31] Graceful Receive Stopped + } B; +} hw_enet_rcr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_RCR register + */ +//@{ +#define HW_ENET_RCR_ADDR (REGS_ENET_BASE + 0x84) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_RCR (*(volatile hw_enet_rcr_t *) HW_ENET_RCR_ADDR) +#define HW_ENET_RCR_RD() (HW_ENET_RCR.U) +#define HW_ENET_RCR_WR(v) (HW_ENET_RCR.U = (v)) +#define HW_ENET_RCR_SET(v) (HW_ENET_RCR_WR(HW_ENET_RCR_RD() | (v))) +#define HW_ENET_RCR_CLR(v) (HW_ENET_RCR_WR(HW_ENET_RCR_RD() & ~(v))) +#define HW_ENET_RCR_TOG(v) (HW_ENET_RCR_WR(HW_ENET_RCR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_RCR bitfields + */ + +/*! @name Register ENET_RCR, field LOOP[0] (RW) + * + * This is an MII internal loopback, therefore MII_MODE must be written to 1 and RMII_MODE must be + * written to 0. + * + * Values: + * - 0 - Loopback disabled. + * - 1 - Transmitted frames are looped back internal to the device and transmit MII output signals are not + * asserted. DRT must be cleared. + */ +//@{ +#define BP_ENET_RCR_LOOP (0) //!< Bit position for ENET_RCR_LOOP. +#define BM_ENET_RCR_LOOP (0x00000001) //!< Bit mask for ENET_RCR_LOOP. + +//! @brief Get value of ENET_RCR_LOOP from a register value. +#define BG_ENET_RCR_LOOP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_LOOP) >> BP_ENET_RCR_LOOP) + +//! @brief Format value for bitfield ENET_RCR_LOOP. +#define BF_ENET_RCR_LOOP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_LOOP) & BM_ENET_RCR_LOOP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LOOP field to a new value. +#define BW_ENET_RCR_LOOP(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_LOOP) | BF_ENET_RCR_LOOP(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field DRT[1] (RW) + * + * Values: + * - 0 - Receive path operates independently of transmit. Used for full-duplex or to monitor transmit + * activity in half-duplex mode. + * - 1 - Disable reception of frames while transmitting. Normally used for half-duplex mode. + */ +//@{ +#define BP_ENET_RCR_DRT (1) //!< Bit position for ENET_RCR_DRT. +#define BM_ENET_RCR_DRT (0x00000002) //!< Bit mask for ENET_RCR_DRT. + +//! @brief Get value of ENET_RCR_DRT from a register value. +#define BG_ENET_RCR_DRT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_DRT) >> BP_ENET_RCR_DRT) + +//! @brief Format value for bitfield ENET_RCR_DRT. +#define BF_ENET_RCR_DRT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_DRT) & BM_ENET_RCR_DRT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DRT field to a new value. +#define BW_ENET_RCR_DRT(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_DRT) | BF_ENET_RCR_DRT(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field MII_MODE[2] (RW) + * + * This field must always be set. + * + * Values: + * - 0 - Reserved. + * - 1 - MII or RMII mode, as indicated by the RMII_MODE field. + */ +//@{ +#define BP_ENET_RCR_MII_MODE (2) //!< Bit position for ENET_RCR_MII_MODE. +#define BM_ENET_RCR_MII_MODE (0x00000004) //!< Bit mask for ENET_RCR_MII_MODE. + +//! @brief Get value of ENET_RCR_MII_MODE from a register value. +#define BG_ENET_RCR_MII_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_MII_MODE) >> BP_ENET_RCR_MII_MODE) + +//! @brief Format value for bitfield ENET_RCR_MII_MODE. +#define BF_ENET_RCR_MII_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_MII_MODE) & BM_ENET_RCR_MII_MODE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MII_MODE field to a new value. +#define BW_ENET_RCR_MII_MODE(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_MII_MODE) | BF_ENET_RCR_MII_MODE(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field PROM[3] (RW) + * + * All frames are accepted regardless of address matching. + * + * Values: + * - 0 - Disabled. + * - 1 - Enabled. + */ +//@{ +#define BP_ENET_RCR_PROM (3) //!< Bit position for ENET_RCR_PROM. +#define BM_ENET_RCR_PROM (0x00000008) //!< Bit mask for ENET_RCR_PROM. + +//! @brief Get value of ENET_RCR_PROM from a register value. +#define BG_ENET_RCR_PROM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_PROM) >> BP_ENET_RCR_PROM) + +//! @brief Format value for bitfield ENET_RCR_PROM. +#define BF_ENET_RCR_PROM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_PROM) & BM_ENET_RCR_PROM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PROM field to a new value. +#define BW_ENET_RCR_PROM(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_PROM) | BF_ENET_RCR_PROM(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field BC_REJ[4] (RW) + * + * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are rejected unless the + * PROM field is set. If BC_REJ and PROM are set, frames with broadcast DA are accepted and the MISS + * (M) is set in the receive buffer descriptor. + */ +//@{ +#define BP_ENET_RCR_BC_REJ (4) //!< Bit position for ENET_RCR_BC_REJ. +#define BM_ENET_RCR_BC_REJ (0x00000010) //!< Bit mask for ENET_RCR_BC_REJ. + +//! @brief Get value of ENET_RCR_BC_REJ from a register value. +#define BG_ENET_RCR_BC_REJ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_BC_REJ) >> BP_ENET_RCR_BC_REJ) + +//! @brief Format value for bitfield ENET_RCR_BC_REJ. +#define BF_ENET_RCR_BC_REJ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_BC_REJ) & BM_ENET_RCR_BC_REJ) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BC_REJ field to a new value. +#define BW_ENET_RCR_BC_REJ(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_BC_REJ) | BF_ENET_RCR_BC_REJ(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field FCE[5] (RW) + * + * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter stops + * transmitting data frames for a given duration. + */ +//@{ +#define BP_ENET_RCR_FCE (5) //!< Bit position for ENET_RCR_FCE. +#define BM_ENET_RCR_FCE (0x00000020) //!< Bit mask for ENET_RCR_FCE. + +//! @brief Get value of ENET_RCR_FCE from a register value. +#define BG_ENET_RCR_FCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_FCE) >> BP_ENET_RCR_FCE) + +//! @brief Format value for bitfield ENET_RCR_FCE. +#define BF_ENET_RCR_FCE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_FCE) & BM_ENET_RCR_FCE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FCE field to a new value. +#define BW_ENET_RCR_FCE(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_FCE) | BF_ENET_RCR_FCE(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field RMII_MODE[8] (RW) + * + * Specifies whether the MAC is configured for MII mode or RMII operation . + * + * Values: + * - 0 - MAC configured for MII mode. + * - 1 - MAC configured for RMII operation. + */ +//@{ +#define BP_ENET_RCR_RMII_MODE (8) //!< Bit position for ENET_RCR_RMII_MODE. +#define BM_ENET_RCR_RMII_MODE (0x00000100) //!< Bit mask for ENET_RCR_RMII_MODE. + +//! @brief Get value of ENET_RCR_RMII_MODE from a register value. +#define BG_ENET_RCR_RMII_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_RMII_MODE) >> BP_ENET_RCR_RMII_MODE) + +//! @brief Format value for bitfield ENET_RCR_RMII_MODE. +#define BF_ENET_RCR_RMII_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_RMII_MODE) & BM_ENET_RCR_RMII_MODE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RMII_MODE field to a new value. +#define BW_ENET_RCR_RMII_MODE(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_RMII_MODE) | BF_ENET_RCR_RMII_MODE(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field RMII_10T[9] (RW) + * + * Enables 10-Mbps mode of the RMII . + * + * Values: + * - 0 - 100 Mbps operation. + * - 1 - 10 Mbps operation. + */ +//@{ +#define BP_ENET_RCR_RMII_10T (9) //!< Bit position for ENET_RCR_RMII_10T. +#define BM_ENET_RCR_RMII_10T (0x00000200) //!< Bit mask for ENET_RCR_RMII_10T. + +//! @brief Get value of ENET_RCR_RMII_10T from a register value. +#define BG_ENET_RCR_RMII_10T(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_RMII_10T) >> BP_ENET_RCR_RMII_10T) + +//! @brief Format value for bitfield ENET_RCR_RMII_10T. +#define BF_ENET_RCR_RMII_10T(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_RMII_10T) & BM_ENET_RCR_RMII_10T) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RMII_10T field to a new value. +#define BW_ENET_RCR_RMII_10T(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_RMII_10T) | BF_ENET_RCR_RMII_10T(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field PADEN[12] (RW) + * + * Specifies whether the MAC removes padding from received frames. + * + * Values: + * - 0 - No padding is removed on receive by the MAC. + * - 1 - Padding is removed from received frames. + */ +//@{ +#define BP_ENET_RCR_PADEN (12) //!< Bit position for ENET_RCR_PADEN. +#define BM_ENET_RCR_PADEN (0x00001000) //!< Bit mask for ENET_RCR_PADEN. + +//! @brief Get value of ENET_RCR_PADEN from a register value. +#define BG_ENET_RCR_PADEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_PADEN) >> BP_ENET_RCR_PADEN) + +//! @brief Format value for bitfield ENET_RCR_PADEN. +#define BF_ENET_RCR_PADEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_PADEN) & BM_ENET_RCR_PADEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PADEN field to a new value. +#define BW_ENET_RCR_PADEN(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_PADEN) | BF_ENET_RCR_PADEN(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field PAUFWD[13] (RW) + * + * Specifies whether pause frames are terminated or forwarded. + * + * Values: + * - 0 - Pause frames are terminated and discarded in the MAC. + * - 1 - Pause frames are forwarded to the user application. + */ +//@{ +#define BP_ENET_RCR_PAUFWD (13) //!< Bit position for ENET_RCR_PAUFWD. +#define BM_ENET_RCR_PAUFWD (0x00002000) //!< Bit mask for ENET_RCR_PAUFWD. + +//! @brief Get value of ENET_RCR_PAUFWD from a register value. +#define BG_ENET_RCR_PAUFWD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_PAUFWD) >> BP_ENET_RCR_PAUFWD) + +//! @brief Format value for bitfield ENET_RCR_PAUFWD. +#define BF_ENET_RCR_PAUFWD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_PAUFWD) & BM_ENET_RCR_PAUFWD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PAUFWD field to a new value. +#define BW_ENET_RCR_PAUFWD(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_PAUFWD) | BF_ENET_RCR_PAUFWD(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field CRCFWD[14] (RW) + * + * Specifies whether the CRC field of received frames is transmitted or stripped. If padding + * function is enabled (PADEN = 1), CRCFWD is ignored and the CRC field is checked and always + * terminated and removed. + * + * Values: + * - 0 - The CRC field of received frames is transmitted to the user application. + * - 1 - The CRC field is stripped from the frame. + */ +//@{ +#define BP_ENET_RCR_CRCFWD (14) //!< Bit position for ENET_RCR_CRCFWD. +#define BM_ENET_RCR_CRCFWD (0x00004000) //!< Bit mask for ENET_RCR_CRCFWD. + +//! @brief Get value of ENET_RCR_CRCFWD from a register value. +#define BG_ENET_RCR_CRCFWD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_CRCFWD) >> BP_ENET_RCR_CRCFWD) + +//! @brief Format value for bitfield ENET_RCR_CRCFWD. +#define BF_ENET_RCR_CRCFWD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_CRCFWD) & BM_ENET_RCR_CRCFWD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRCFWD field to a new value. +#define BW_ENET_RCR_CRCFWD(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_CRCFWD) | BF_ENET_RCR_CRCFWD(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field CFEN[15] (RW) + * + * Enables/disables the MAC control frame. + * + * Values: + * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the + * client interface. + * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ +//@{ +#define BP_ENET_RCR_CFEN (15) //!< Bit position for ENET_RCR_CFEN. +#define BM_ENET_RCR_CFEN (0x00008000) //!< Bit mask for ENET_RCR_CFEN. + +//! @brief Get value of ENET_RCR_CFEN from a register value. +#define BG_ENET_RCR_CFEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_CFEN) >> BP_ENET_RCR_CFEN) + +//! @brief Format value for bitfield ENET_RCR_CFEN. +#define BF_ENET_RCR_CFEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_CFEN) & BM_ENET_RCR_CFEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CFEN field to a new value. +#define BW_ENET_RCR_CFEN(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_CFEN) | BF_ENET_RCR_CFEN(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field MAX_FL[29:16] (RW) + * + * Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the + * frame. Transmit frames longer than MAX_FL cause the BABT interrupt to occur. Receive frames + * longer than MAX_FL cause the BABR interrupt to occur and set the LG field in the end of frame + * receive buffer descriptor. The recommended default value to be programmed is 1518 or 1522 if VLAN + * tags are supported. + */ +//@{ +#define BP_ENET_RCR_MAX_FL (16) //!< Bit position for ENET_RCR_MAX_FL. +#define BM_ENET_RCR_MAX_FL (0x3fff0000) //!< Bit mask for ENET_RCR_MAX_FL. + +//! @brief Get value of ENET_RCR_MAX_FL from a register value. +#define BG_ENET_RCR_MAX_FL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_MAX_FL) >> BP_ENET_RCR_MAX_FL) + +//! @brief Format value for bitfield ENET_RCR_MAX_FL. +#define BF_ENET_RCR_MAX_FL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_MAX_FL) & BM_ENET_RCR_MAX_FL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MAX_FL field to a new value. +#define BW_ENET_RCR_MAX_FL(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field NLC[30] (RW) + * + * Enables/disables a payload length check. + * + * Values: + * - 0 - The payload length check is disabled. + * - 1 - The core checks the frame's payload length with the frame length/type field. Errors are indicated in + * the EIR[PLC] field. + */ +//@{ +#define BP_ENET_RCR_NLC (30) //!< Bit position for ENET_RCR_NLC. +#define BM_ENET_RCR_NLC (0x40000000) //!< Bit mask for ENET_RCR_NLC. + +//! @brief Get value of ENET_RCR_NLC from a register value. +#define BG_ENET_RCR_NLC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_NLC) >> BP_ENET_RCR_NLC) + +//! @brief Format value for bitfield ENET_RCR_NLC. +#define BF_ENET_RCR_NLC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RCR_NLC) & BM_ENET_RCR_NLC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NLC field to a new value. +#define BW_ENET_RCR_NLC(v) (HW_ENET_RCR_WR((HW_ENET_RCR_RD() & ~BM_ENET_RCR_NLC) | BF_ENET_RCR_NLC(v))) +#endif +//@} + +/*! @name Register ENET_RCR, field GRS[31] (RO) + * + * Read-only status indicating that the MAC receive datapath is stopped. + */ +//@{ +#define BP_ENET_RCR_GRS (31) //!< Bit position for ENET_RCR_GRS. +#define BM_ENET_RCR_GRS (0x80000000) //!< Bit mask for ENET_RCR_GRS. + +//! @brief Get value of ENET_RCR_GRS from a register value. +#define BG_ENET_RCR_GRS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RCR_GRS) >> BP_ENET_RCR_GRS) +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_TCR - Transmit Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TCR - Transmit Control Register (RW) + * + * Reset value: 0x00000000 + * + * TCR is read/write and configures the transmit block. This register is cleared at system reset. + * FDEN can only be modified when ECR[ETHEREN] is cleared. + */ +typedef union _hw_enet_tcr +{ + reg32_t U; + struct _hw_enet_tcr_bitfields + { + unsigned GTS : 1; //!< [0] Graceful Transmit Stop + unsigned RESERVED0 : 1; //!< [1] + unsigned FDEN : 1; //!< [2] Full-Duplex Enable + unsigned TFC_PAUSE : 1; //!< [3] Transmit Frame Control Pause + unsigned RFC_PAUSE : 1; //!< [4] Receive Frame Control Pause + unsigned ADDSEL : 3; //!< [7:5] Source MAC Address Select On Transmit + unsigned ADDINS : 1; //!< [8] Set MAC Address On Transmit + unsigned CRCFWD : 1; //!< [9] Forward Frame From Application With CRC + unsigned RESERVED1 : 22; //!< [31:10] + } B; +} hw_enet_tcr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TCR register + */ +//@{ +#define HW_ENET_TCR_ADDR (REGS_ENET_BASE + 0xc4) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TCR (*(volatile hw_enet_tcr_t *) HW_ENET_TCR_ADDR) +#define HW_ENET_TCR_RD() (HW_ENET_TCR.U) +#define HW_ENET_TCR_WR(v) (HW_ENET_TCR.U = (v)) +#define HW_ENET_TCR_SET(v) (HW_ENET_TCR_WR(HW_ENET_TCR_RD() | (v))) +#define HW_ENET_TCR_CLR(v) (HW_ENET_TCR_WR(HW_ENET_TCR_RD() & ~(v))) +#define HW_ENET_TCR_TOG(v) (HW_ENET_TCR_WR(HW_ENET_TCR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TCR bitfields + */ + +/*! @name Register ENET_TCR, field GTS[0] (RW) + * + * When this field is set, MAC stops transmission after any frame currently transmitted is complete + * and EIR[GRA] is set. If frame transmission is not currently underway, the GRA interrupt is + * asserted immediately. After transmission finishes, clear GTS to restart. The next frame in the + * transmit FIFO is then transmitted. If an early collision occurs during transmission when GTS is + * set, transmission stops after the collision. The frame is transmitted again after GTS is cleared. + * There may be old frames in the transmit FIFO that transmit when GTS is reasserted. To avoid this, + * clear ECR[ETHEREN] following the GRA interrupt. + */ +//@{ +#define BP_ENET_TCR_GTS (0) //!< Bit position for ENET_TCR_GTS. +#define BM_ENET_TCR_GTS (0x00000001) //!< Bit mask for ENET_TCR_GTS. + +//! @brief Get value of ENET_TCR_GTS from a register value. +#define BG_ENET_TCR_GTS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TCR_GTS) >> BP_ENET_TCR_GTS) + +//! @brief Format value for bitfield ENET_TCR_GTS. +#define BF_ENET_TCR_GTS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TCR_GTS) & BM_ENET_TCR_GTS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GTS field to a new value. +#define BW_ENET_TCR_GTS(v) (HW_ENET_TCR_WR((HW_ENET_TCR_RD() & ~BM_ENET_TCR_GTS) | BF_ENET_TCR_GTS(v))) +#endif +//@} + +/*! @name Register ENET_TCR, field FDEN[2] (RW) + * + * If this field is set, frames transmit independent of carrier sense and collision inputs. Only + * modify this bit when ECR[ETHEREN] is cleared. + */ +//@{ +#define BP_ENET_TCR_FDEN (2) //!< Bit position for ENET_TCR_FDEN. +#define BM_ENET_TCR_FDEN (0x00000004) //!< Bit mask for ENET_TCR_FDEN. + +//! @brief Get value of ENET_TCR_FDEN from a register value. +#define BG_ENET_TCR_FDEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TCR_FDEN) >> BP_ENET_TCR_FDEN) + +//! @brief Format value for bitfield ENET_TCR_FDEN. +#define BF_ENET_TCR_FDEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TCR_FDEN) & BM_ENET_TCR_FDEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FDEN field to a new value. +#define BW_ENET_TCR_FDEN(v) (HW_ENET_TCR_WR((HW_ENET_TCR_RD() & ~BM_ENET_TCR_FDEN) | BF_ENET_TCR_FDEN(v))) +#endif +//@} + +/*! @name Register ENET_TCR, field TFC_PAUSE[3] (RW) + * + * Pauses frame transmission. When this field is set, EIR[GRA] is set. With transmission of data + * frames stopped, the MAC transmits a MAC control PAUSE frame. Next, the MAC clears TFC_PAUSE and + * resumes transmitting data frames. If the transmitter pauses due to user assertion of GTS or + * reception of a PAUSE frame, the MAC may continue transmitting a MAC control PAUSE frame. + * + * Values: + * - 0 - No PAUSE frame transmitted. + * - 1 - The MAC stops transmission of data frames after the current transmission is complete. + */ +//@{ +#define BP_ENET_TCR_TFC_PAUSE (3) //!< Bit position for ENET_TCR_TFC_PAUSE. +#define BM_ENET_TCR_TFC_PAUSE (0x00000008) //!< Bit mask for ENET_TCR_TFC_PAUSE. + +//! @brief Get value of ENET_TCR_TFC_PAUSE from a register value. +#define BG_ENET_TCR_TFC_PAUSE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TCR_TFC_PAUSE) >> BP_ENET_TCR_TFC_PAUSE) + +//! @brief Format value for bitfield ENET_TCR_TFC_PAUSE. +#define BF_ENET_TCR_TFC_PAUSE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TCR_TFC_PAUSE) & BM_ENET_TCR_TFC_PAUSE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TFC_PAUSE field to a new value. +#define BW_ENET_TCR_TFC_PAUSE(v) (HW_ENET_TCR_WR((HW_ENET_TCR_RD() & ~BM_ENET_TCR_TFC_PAUSE) | BF_ENET_TCR_TFC_PAUSE(v))) +#endif +//@} + +/*! @name Register ENET_TCR, field RFC_PAUSE[4] (RO) + * + * This status field is set when a full-duplex flow control pause frame is received and the + * transmitter pauses for the duration defined in this pause frame. This field automatically clears + * when the pause duration is complete. + */ +//@{ +#define BP_ENET_TCR_RFC_PAUSE (4) //!< Bit position for ENET_TCR_RFC_PAUSE. +#define BM_ENET_TCR_RFC_PAUSE (0x00000010) //!< Bit mask for ENET_TCR_RFC_PAUSE. + +//! @brief Get value of ENET_TCR_RFC_PAUSE from a register value. +#define BG_ENET_TCR_RFC_PAUSE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TCR_RFC_PAUSE) >> BP_ENET_TCR_RFC_PAUSE) +//@} + +/*! @name Register ENET_TCR, field ADDSEL[7:5] (RW) + * + * If ADDINS is set, indicates the MAC address that overwrites the source MAC address. + * + * Values: + * - 000 - Node MAC address programmed on PADDR1/2 registers. + * - 100 - + * - 101 - + * - 110 - + */ +//@{ +#define BP_ENET_TCR_ADDSEL (5) //!< Bit position for ENET_TCR_ADDSEL. +#define BM_ENET_TCR_ADDSEL (0x000000e0) //!< Bit mask for ENET_TCR_ADDSEL. + +//! @brief Get value of ENET_TCR_ADDSEL from a register value. +#define BG_ENET_TCR_ADDSEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TCR_ADDSEL) >> BP_ENET_TCR_ADDSEL) + +//! @brief Format value for bitfield ENET_TCR_ADDSEL. +#define BF_ENET_TCR_ADDSEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TCR_ADDSEL) & BM_ENET_TCR_ADDSEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADDSEL field to a new value. +#define BW_ENET_TCR_ADDSEL(v) (HW_ENET_TCR_WR((HW_ENET_TCR_RD() & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v))) +#endif +//@} + +/*! @name Register ENET_TCR, field ADDINS[8] (RW) + * + * Values: + * - 0 - The source MAC address is not modified by the MAC. + * - 1 - The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ +//@{ +#define BP_ENET_TCR_ADDINS (8) //!< Bit position for ENET_TCR_ADDINS. +#define BM_ENET_TCR_ADDINS (0x00000100) //!< Bit mask for ENET_TCR_ADDINS. + +//! @brief Get value of ENET_TCR_ADDINS from a register value. +#define BG_ENET_TCR_ADDINS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TCR_ADDINS) >> BP_ENET_TCR_ADDINS) + +//! @brief Format value for bitfield ENET_TCR_ADDINS. +#define BF_ENET_TCR_ADDINS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TCR_ADDINS) & BM_ENET_TCR_ADDINS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADDINS field to a new value. +#define BW_ENET_TCR_ADDINS(v) (HW_ENET_TCR_WR((HW_ENET_TCR_RD() & ~BM_ENET_TCR_ADDINS) | BF_ENET_TCR_ADDINS(v))) +#endif +//@} + +/*! @name Register ENET_TCR, field CRCFWD[9] (RW) + * + * Values: + * - 0 - TxBD[TC] controls whether the frame has a CRC from the application. + * - 1 - The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC + * from the application. + */ +//@{ +#define BP_ENET_TCR_CRCFWD (9) //!< Bit position for ENET_TCR_CRCFWD. +#define BM_ENET_TCR_CRCFWD (0x00000200) //!< Bit mask for ENET_TCR_CRCFWD. + +//! @brief Get value of ENET_TCR_CRCFWD from a register value. +#define BG_ENET_TCR_CRCFWD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TCR_CRCFWD) >> BP_ENET_TCR_CRCFWD) + +//! @brief Format value for bitfield ENET_TCR_CRCFWD. +#define BF_ENET_TCR_CRCFWD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TCR_CRCFWD) & BM_ENET_TCR_CRCFWD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRCFWD field to a new value. +#define BW_ENET_TCR_CRCFWD(v) (HW_ENET_TCR_WR((HW_ENET_TCR_RD() & ~BM_ENET_TCR_CRCFWD) | BF_ENET_TCR_CRCFWD(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_PALR - Physical Address Lower Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_PALR - Physical Address Lower Register (RW) + * + * Reset value: 0x00000000 + * + * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used in the address + * recognition process to compare with the destination address (DA) field of receive frames with an + * individual DA. In addition, this register is used in bytes 0 through 3 of the six-byte source + * address field when transmitting PAUSE frames. This register is not reset and you must initialize + * it. + */ +typedef union _hw_enet_palr +{ + reg32_t U; + struct _hw_enet_palr_bitfields + { + unsigned PADDR1 : 32; //!< [31:0] Pause Address + } B; +} hw_enet_palr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_PALR register + */ +//@{ +#define HW_ENET_PALR_ADDR (REGS_ENET_BASE + 0xe4) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_PALR (*(volatile hw_enet_palr_t *) HW_ENET_PALR_ADDR) +#define HW_ENET_PALR_RD() (HW_ENET_PALR.U) +#define HW_ENET_PALR_WR(v) (HW_ENET_PALR.U = (v)) +#define HW_ENET_PALR_SET(v) (HW_ENET_PALR_WR(HW_ENET_PALR_RD() | (v))) +#define HW_ENET_PALR_CLR(v) (HW_ENET_PALR_WR(HW_ENET_PALR_RD() & ~(v))) +#define HW_ENET_PALR_TOG(v) (HW_ENET_PALR_WR(HW_ENET_PALR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_PALR bitfields + */ + +/*! @name Register ENET_PALR, field PADDR1[31:0] (RW) + * + * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual + * address are used for exact match and the source address field in PAUSE frames. + */ +//@{ +#define BP_ENET_PALR_PADDR1 (0) //!< Bit position for ENET_PALR_PADDR1. +#define BM_ENET_PALR_PADDR1 (0xffffffff) //!< Bit mask for ENET_PALR_PADDR1. + +//! @brief Get value of ENET_PALR_PADDR1 from a register value. +#define BG_ENET_PALR_PADDR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_PALR_PADDR1) >> BP_ENET_PALR_PADDR1) + +//! @brief Format value for bitfield ENET_PALR_PADDR1. +#define BF_ENET_PALR_PADDR1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_PALR_PADDR1) & BM_ENET_PALR_PADDR1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PADDR1 field to a new value. +#define BW_ENET_PALR_PADDR1(v) (HW_ENET_PALR_WR((HW_ENET_PALR_RD() & ~BM_ENET_PALR_PADDR1) | BF_ENET_PALR_PADDR1(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_PAUR - Physical Address Upper Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_PAUR - Physical Address Upper Register (RW) + * + * Reset value: 0x00008808 + * + * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address + * recognition process to compare with the destination address (DA) field of receive frames with an + * individual DA. In addition, this register is used in bytes 4 and 5 of the six-byte source address + * field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) + * for transmission of PAUSE frames. The upper 16 bits of this register are not reset and you must + * initialize it. + */ +typedef union _hw_enet_paur +{ + reg32_t U; + struct _hw_enet_paur_bitfields + { + unsigned TYPE : 16; //!< [15:0] Type Field In PAUSE Frames + unsigned PADDR2 : 16; //!< [31:16] Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames. + } B; +} hw_enet_paur_t; +#endif + +/*! + * @name Constants and macros for entire ENET_PAUR register + */ +//@{ +#define HW_ENET_PAUR_ADDR (REGS_ENET_BASE + 0xe8) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_PAUR (*(volatile hw_enet_paur_t *) HW_ENET_PAUR_ADDR) +#define HW_ENET_PAUR_RD() (HW_ENET_PAUR.U) +#define HW_ENET_PAUR_WR(v) (HW_ENET_PAUR.U = (v)) +#define HW_ENET_PAUR_SET(v) (HW_ENET_PAUR_WR(HW_ENET_PAUR_RD() | (v))) +#define HW_ENET_PAUR_CLR(v) (HW_ENET_PAUR_WR(HW_ENET_PAUR_RD() & ~(v))) +#define HW_ENET_PAUR_TOG(v) (HW_ENET_PAUR_WR(HW_ENET_PAUR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_PAUR bitfields + */ + +/*! @name Register ENET_PAUR, field TYPE[15:0] (RO) + * + * These fields have a constant value of 0x8808. + */ +//@{ +#define BP_ENET_PAUR_TYPE (0) //!< Bit position for ENET_PAUR_TYPE. +#define BM_ENET_PAUR_TYPE (0x0000ffff) //!< Bit mask for ENET_PAUR_TYPE. + +//! @brief Get value of ENET_PAUR_TYPE from a register value. +#define BG_ENET_PAUR_TYPE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_PAUR_TYPE) >> BP_ENET_PAUR_TYPE) +//@} + +/*! @name Register ENET_PAUR, field PADDR2[31:16] (RW) + * + * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, + * and the source address field in PAUSE frames. + */ +//@{ +#define BP_ENET_PAUR_PADDR2 (16) //!< Bit position for ENET_PAUR_PADDR2. +#define BM_ENET_PAUR_PADDR2 (0xffff0000) //!< Bit mask for ENET_PAUR_PADDR2. + +//! @brief Get value of ENET_PAUR_PADDR2 from a register value. +#define BG_ENET_PAUR_PADDR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_PAUR_PADDR2) >> BP_ENET_PAUR_PADDR2) + +//! @brief Format value for bitfield ENET_PAUR_PADDR2. +#define BF_ENET_PAUR_PADDR2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_PAUR_PADDR2) & BM_ENET_PAUR_PADDR2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PADDR2 field to a new value. +#define BW_ENET_PAUR_PADDR2(v) (HW_ENET_PAUR_WR((HW_ENET_PAUR_RD() & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_OPD - Opcode/Pause Duration Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW) + * + * Reset value: 0x00010000 + * + * OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration + * fields used in transmission of a PAUSE frame. The opcode field is a constant value, 0x0001. When + * another node detects a PAUSE frame, that node pauses transmission for the duration specified in + * the pause duration field. The lower 16 bits of this register are not reset and you must + * initialize it. + */ +typedef union _hw_enet_opd +{ + reg32_t U; + struct _hw_enet_opd_bitfields + { + unsigned PAUSE_DUR : 16; //!< [15:0] Pause Duration + unsigned OPCODE : 16; //!< [31:16] Opcode Field In PAUSE Frames + } B; +} hw_enet_opd_t; +#endif + +/*! + * @name Constants and macros for entire ENET_OPD register + */ +//@{ +#define HW_ENET_OPD_ADDR (REGS_ENET_BASE + 0xec) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_OPD (*(volatile hw_enet_opd_t *) HW_ENET_OPD_ADDR) +#define HW_ENET_OPD_RD() (HW_ENET_OPD.U) +#define HW_ENET_OPD_WR(v) (HW_ENET_OPD.U = (v)) +#define HW_ENET_OPD_SET(v) (HW_ENET_OPD_WR(HW_ENET_OPD_RD() | (v))) +#define HW_ENET_OPD_CLR(v) (HW_ENET_OPD_WR(HW_ENET_OPD_RD() & ~(v))) +#define HW_ENET_OPD_TOG(v) (HW_ENET_OPD_WR(HW_ENET_OPD_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_OPD bitfields + */ + +/*! @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW) + * + * Pause duration field used in PAUSE frames. + */ +//@{ +#define BP_ENET_OPD_PAUSE_DUR (0) //!< Bit position for ENET_OPD_PAUSE_DUR. +#define BM_ENET_OPD_PAUSE_DUR (0x0000ffff) //!< Bit mask for ENET_OPD_PAUSE_DUR. + +//! @brief Get value of ENET_OPD_PAUSE_DUR from a register value. +#define BG_ENET_OPD_PAUSE_DUR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_OPD_PAUSE_DUR) >> BP_ENET_OPD_PAUSE_DUR) + +//! @brief Format value for bitfield ENET_OPD_PAUSE_DUR. +#define BF_ENET_OPD_PAUSE_DUR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_OPD_PAUSE_DUR) & BM_ENET_OPD_PAUSE_DUR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PAUSE_DUR field to a new value. +#define BW_ENET_OPD_PAUSE_DUR(v) (HW_ENET_OPD_WR((HW_ENET_OPD_RD() & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v))) +#endif +//@} + +/*! @name Register ENET_OPD, field OPCODE[31:16] (RO) + * + * These fields have a constant value of 0x0001. + */ +//@{ +#define BP_ENET_OPD_OPCODE (16) //!< Bit position for ENET_OPD_OPCODE. +#define BM_ENET_OPD_OPCODE (0xffff0000) //!< Bit mask for ENET_OPD_OPCODE. + +//! @brief Get value of ENET_OPD_OPCODE from a register value. +#define BG_ENET_OPD_OPCODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_OPD_OPCODE) >> BP_ENET_OPD_OPCODE) +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_IAUR - Descriptor Individual Upper Address Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW) + * + * Reset value: 0x00000000 + * + * IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address + * recognition process uses this table to check for a possible match with the destination address + * (DA) field of receive frames with an individual DA. This register is not reset and you must + * initialize it. + */ +typedef union _hw_enet_iaur +{ + reg32_t U; + struct _hw_enet_iaur_bitfields + { + unsigned IADDR1 : 32; //!< [31:0] Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. + } B; +} hw_enet_iaur_t; +#endif + +/*! + * @name Constants and macros for entire ENET_IAUR register + */ +//@{ +#define HW_ENET_IAUR_ADDR (REGS_ENET_BASE + 0x118) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_IAUR (*(volatile hw_enet_iaur_t *) HW_ENET_IAUR_ADDR) +#define HW_ENET_IAUR_RD() (HW_ENET_IAUR.U) +#define HW_ENET_IAUR_WR(v) (HW_ENET_IAUR.U = (v)) +#define HW_ENET_IAUR_SET(v) (HW_ENET_IAUR_WR(HW_ENET_IAUR_RD() | (v))) +#define HW_ENET_IAUR_CLR(v) (HW_ENET_IAUR_WR(HW_ENET_IAUR_RD() & ~(v))) +#define HW_ENET_IAUR_TOG(v) (HW_ENET_IAUR_WR(HW_ENET_IAUR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_IAUR bitfields + */ + +/*! @name Register ENET_IAUR, field IADDR1[31:0] (RW) + * + * Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for + * receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of + * IADDR1 contains hash index bit 32. + */ +//@{ +#define BP_ENET_IAUR_IADDR1 (0) //!< Bit position for ENET_IAUR_IADDR1. +#define BM_ENET_IAUR_IADDR1 (0xffffffff) //!< Bit mask for ENET_IAUR_IADDR1. + +//! @brief Get value of ENET_IAUR_IADDR1 from a register value. +#define BG_ENET_IAUR_IADDR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_IAUR_IADDR1) >> BP_ENET_IAUR_IADDR1) + +//! @brief Format value for bitfield ENET_IAUR_IADDR1. +#define BF_ENET_IAUR_IADDR1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_IAUR_IADDR1) & BM_ENET_IAUR_IADDR1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IADDR1 field to a new value. +#define BW_ENET_IAUR_IADDR1(v) (HW_ENET_IAUR_WR((HW_ENET_IAUR_RD() & ~BM_ENET_IAUR_IADDR1) | BF_ENET_IAUR_IADDR1(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_IALR - Descriptor Individual Lower Address Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW) + * + * Reset value: 0x00000000 + * + * IALR contains the lower 32 bits of the 64-bit individual address hash table. The address + * recognition process uses this table to check for a possible match with the DA field of receive + * frames with an individual DA. This register is not reset and you must initialize it. + */ +typedef union _hw_enet_ialr +{ + reg32_t U; + struct _hw_enet_ialr_bitfields + { + unsigned IADDR2 : 32; //!< [31:0] Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. + } B; +} hw_enet_ialr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_IALR register + */ +//@{ +#define HW_ENET_IALR_ADDR (REGS_ENET_BASE + 0x11c) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_IALR (*(volatile hw_enet_ialr_t *) HW_ENET_IALR_ADDR) +#define HW_ENET_IALR_RD() (HW_ENET_IALR.U) +#define HW_ENET_IALR_WR(v) (HW_ENET_IALR.U = (v)) +#define HW_ENET_IALR_SET(v) (HW_ENET_IALR_WR(HW_ENET_IALR_RD() | (v))) +#define HW_ENET_IALR_CLR(v) (HW_ENET_IALR_WR(HW_ENET_IALR_RD() & ~(v))) +#define HW_ENET_IALR_TOG(v) (HW_ENET_IALR_WR(HW_ENET_IALR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_IALR bitfields + */ + +/*! @name Register ENET_IALR, field IADDR2[31:0] (RW) + * + * Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for + * receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of + * IADDR2 contains hash index bit 0. + */ +//@{ +#define BP_ENET_IALR_IADDR2 (0) //!< Bit position for ENET_IALR_IADDR2. +#define BM_ENET_IALR_IADDR2 (0xffffffff) //!< Bit mask for ENET_IALR_IADDR2. + +//! @brief Get value of ENET_IALR_IADDR2 from a register value. +#define BG_ENET_IALR_IADDR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_IALR_IADDR2) >> BP_ENET_IALR_IADDR2) + +//! @brief Format value for bitfield ENET_IALR_IADDR2. +#define BF_ENET_IALR_IADDR2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_IALR_IADDR2) & BM_ENET_IALR_IADDR2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IADDR2 field to a new value. +#define BW_ENET_IALR_IADDR2(v) (HW_ENET_IALR_WR((HW_ENET_IALR_RD() & ~BM_ENET_IALR_IADDR2) | BF_ENET_IALR_IADDR2(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_GAUR - Descriptor Group Upper Address Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW) + * + * Reset value: 0x00000000 + * + * GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition process + * for receive frames with a multicast address. You must initialize this register. + */ +typedef union _hw_enet_gaur +{ + reg32_t U; + struct _hw_enet_gaur_bitfields + { + unsigned GADDR1 : 32; //!< [31:0] Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. + } B; +} hw_enet_gaur_t; +#endif + +/*! + * @name Constants and macros for entire ENET_GAUR register + */ +//@{ +#define HW_ENET_GAUR_ADDR (REGS_ENET_BASE + 0x120) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_GAUR (*(volatile hw_enet_gaur_t *) HW_ENET_GAUR_ADDR) +#define HW_ENET_GAUR_RD() (HW_ENET_GAUR.U) +#define HW_ENET_GAUR_WR(v) (HW_ENET_GAUR.U = (v)) +#define HW_ENET_GAUR_SET(v) (HW_ENET_GAUR_WR(HW_ENET_GAUR_RD() | (v))) +#define HW_ENET_GAUR_CLR(v) (HW_ENET_GAUR_WR(HW_ENET_GAUR_RD() & ~(v))) +#define HW_ENET_GAUR_TOG(v) (HW_ENET_GAUR_WR(HW_ENET_GAUR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_GAUR bitfields + */ + +/*! @name Register ENET_GAUR, field GADDR1[31:0] (RW) + * + * Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for + * receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of + * GADDR1 contains hash index bit 32. + */ +//@{ +#define BP_ENET_GAUR_GADDR1 (0) //!< Bit position for ENET_GAUR_GADDR1. +#define BM_ENET_GAUR_GADDR1 (0xffffffff) //!< Bit mask for ENET_GAUR_GADDR1. + +//! @brief Get value of ENET_GAUR_GADDR1 from a register value. +#define BG_ENET_GAUR_GADDR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_GAUR_GADDR1) >> BP_ENET_GAUR_GADDR1) + +//! @brief Format value for bitfield ENET_GAUR_GADDR1. +#define BF_ENET_GAUR_GADDR1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_GAUR_GADDR1) & BM_ENET_GAUR_GADDR1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GADDR1 field to a new value. +#define BW_ENET_GAUR_GADDR1(v) (HW_ENET_GAUR_WR((HW_ENET_GAUR_RD() & ~BM_ENET_GAUR_GADDR1) | BF_ENET_GAUR_GADDR1(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_GALR - Descriptor Group Lower Address Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW) + * + * Reset value: 0x00000000 + * + * GALR contains the lower 32 bits of the 64-bit hash table used in the address recognition process + * for receive frames with a multicast address. You must initialize this register. + */ +typedef union _hw_enet_galr +{ + reg32_t U; + struct _hw_enet_galr_bitfields + { + unsigned GADDR2 : 32; //!< [31:0] Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. + } B; +} hw_enet_galr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_GALR register + */ +//@{ +#define HW_ENET_GALR_ADDR (REGS_ENET_BASE + 0x124) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_GALR (*(volatile hw_enet_galr_t *) HW_ENET_GALR_ADDR) +#define HW_ENET_GALR_RD() (HW_ENET_GALR.U) +#define HW_ENET_GALR_WR(v) (HW_ENET_GALR.U = (v)) +#define HW_ENET_GALR_SET(v) (HW_ENET_GALR_WR(HW_ENET_GALR_RD() | (v))) +#define HW_ENET_GALR_CLR(v) (HW_ENET_GALR_WR(HW_ENET_GALR_RD() & ~(v))) +#define HW_ENET_GALR_TOG(v) (HW_ENET_GALR_WR(HW_ENET_GALR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_GALR bitfields + */ + +/*! @name Register ENET_GALR, field GADDR2[31:0] (RW) + * + * Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for + * receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of + * GADDR2 contains hash index bit 0. + */ +//@{ +#define BP_ENET_GALR_GADDR2 (0) //!< Bit position for ENET_GALR_GADDR2. +#define BM_ENET_GALR_GADDR2 (0xffffffff) //!< Bit mask for ENET_GALR_GADDR2. + +//! @brief Get value of ENET_GALR_GADDR2 from a register value. +#define BG_ENET_GALR_GADDR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_GALR_GADDR2) >> BP_ENET_GALR_GADDR2) + +//! @brief Format value for bitfield ENET_GALR_GADDR2. +#define BF_ENET_GALR_GADDR2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_GALR_GADDR2) & BM_ENET_GALR_GADDR2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the GADDR2 field to a new value. +#define BW_ENET_GALR_GADDR2(v) (HW_ENET_GALR_WR((HW_ENET_GALR_RD() & ~BM_ENET_GALR_GADDR2) | BF_ENET_GALR_GADDR2(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_TFWR - Transmit FIFO Watermark Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW) + * + * Reset value: 0x00000000 + * + * If TFR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required in the transmit FIFO + * before transmission of a frame can begin. This allows you to minimize transmit latency (TFWR = 00 + * or 01) or allow for larger bus access latency (TFWR = 11) due to contention for the system bus. + * Setting the watermark to a high value minimizes the risk of transmit FIFO underrun due to + * contention for the system bus. The byte counts associated with the TFWR field may need to be + * modified to match a given system requirement. For example, worst case bus access latency by the + * transmit data DMA channel. + */ +typedef union _hw_enet_tfwr +{ + reg32_t U; + struct _hw_enet_tfwr_bitfields + { + unsigned TFWR : 6; //!< [5:0] Transmit FIFO Write + unsigned RESERVED0 : 2; //!< [7:6] + unsigned STRFWD : 1; //!< [8] Store And Forward Enable + unsigned RESERVED1 : 23; //!< [31:9] + } B; +} hw_enet_tfwr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TFWR register + */ +//@{ +#define HW_ENET_TFWR_ADDR (REGS_ENET_BASE + 0x144) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TFWR (*(volatile hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR) +#define HW_ENET_TFWR_RD() (HW_ENET_TFWR.U) +#define HW_ENET_TFWR_WR(v) (HW_ENET_TFWR.U = (v)) +#define HW_ENET_TFWR_SET(v) (HW_ENET_TFWR_WR(HW_ENET_TFWR_RD() | (v))) +#define HW_ENET_TFWR_CLR(v) (HW_ENET_TFWR_WR(HW_ENET_TFWR_RD() & ~(v))) +#define HW_ENET_TFWR_TOG(v) (HW_ENET_TFWR_WR(HW_ENET_TFWR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TFWR bitfields + */ + +/*! @name Register ENET_TFWR, field TFWR[5:0] (RW) + * + * If STRFWD is cleared, this field indicates the number of bytes written to the transmit FIFO + * before transmission of a frame begins. If a frame with less than the threshold is written, it is + * still sent independently of this threshold setting. The threshold is relevant only if the frame + * is larger than the threshold given. This chip may not support the maximum number of bytes written + * shown below. See the chip-specific information for the ENET module for this value. + * + * Values: + * - 000000 - 64 bytes written. + * - ... - ... + * - 000001 - 64 bytes written. + * - 000010 - 128 bytes written. + * - 000011 - 192 bytes written. + * - 111110 - 3968 bytes written. + * - 111111 - 4032 bytes written. + */ +//@{ +#define BP_ENET_TFWR_TFWR (0) //!< Bit position for ENET_TFWR_TFWR. +#define BM_ENET_TFWR_TFWR (0x0000003f) //!< Bit mask for ENET_TFWR_TFWR. + +//! @brief Get value of ENET_TFWR_TFWR from a register value. +#define BG_ENET_TFWR_TFWR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TFWR_TFWR) >> BP_ENET_TFWR_TFWR) + +//! @brief Format value for bitfield ENET_TFWR_TFWR. +#define BF_ENET_TFWR_TFWR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TFWR_TFWR) & BM_ENET_TFWR_TFWR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TFWR field to a new value. +#define BW_ENET_TFWR_TFWR(v) (HW_ENET_TFWR_WR((HW_ENET_TFWR_RD() & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v))) +#endif +//@} + +/*! @name Register ENET_TFWR, field STRFWD[8] (RW) + * + * Values: + * - 0 - Disabled, the transmission start threshold is programmed in TFWR. + * - 1 - Enabled. + */ +//@{ +#define BP_ENET_TFWR_STRFWD (8) //!< Bit position for ENET_TFWR_STRFWD. +#define BM_ENET_TFWR_STRFWD (0x00000100) //!< Bit mask for ENET_TFWR_STRFWD. + +//! @brief Get value of ENET_TFWR_STRFWD from a register value. +#define BG_ENET_TFWR_STRFWD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TFWR_STRFWD) >> BP_ENET_TFWR_STRFWD) + +//! @brief Format value for bitfield ENET_TFWR_STRFWD. +#define BF_ENET_TFWR_STRFWD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TFWR_STRFWD) & BM_ENET_TFWR_STRFWD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STRFWD field to a new value. +#define BW_ENET_TFWR_STRFWD(v) (HW_ENET_TFWR_WR((HW_ENET_TFWR_RD() & ~BM_ENET_TFWR_STRFWD) | BF_ENET_TFWR_STRFWD(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_RDSR - Receive Descriptor Ring Start Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW) + * + * Reset value: 0x00000000 + * + * RDSR points to the beginning of the circular receive buffer descriptor queue in external memory. + * This pointer must be 64-bit aligned (bits 2–0 must be zero); however, This register must be + * initialized prior to operation + */ +typedef union _hw_enet_rdsr +{ + reg32_t U; + struct _hw_enet_rdsr_bitfields + { + unsigned RESERVED0 : 3; //!< [2:0] + unsigned R_DES_START : 29; //!< [31:3] Pointer to the beginning of the receive buffer descriptor queue. + } B; +} hw_enet_rdsr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_RDSR register + */ +//@{ +#define HW_ENET_RDSR_ADDR (REGS_ENET_BASE + 0x180) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_RDSR (*(volatile hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR) +#define HW_ENET_RDSR_RD() (HW_ENET_RDSR.U) +#define HW_ENET_RDSR_WR(v) (HW_ENET_RDSR.U = (v)) +#define HW_ENET_RDSR_SET(v) (HW_ENET_RDSR_WR(HW_ENET_RDSR_RD() | (v))) +#define HW_ENET_RDSR_CLR(v) (HW_ENET_RDSR_WR(HW_ENET_RDSR_RD() & ~(v))) +#define HW_ENET_RDSR_TOG(v) (HW_ENET_RDSR_WR(HW_ENET_RDSR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_RDSR bitfields + */ + +/*! @name Register ENET_RDSR, field R_DES_START[31:3] (RW) + * + * Pointer to the beginning of the receive buffer descriptor queue. + */ +//@{ +#define BP_ENET_RDSR_R_DES_START (3) //!< Bit position for ENET_RDSR_R_DES_START. +#define BM_ENET_RDSR_R_DES_START (0xfffffff8) //!< Bit mask for ENET_RDSR_R_DES_START. + +//! @brief Get value of ENET_RDSR_R_DES_START from a register value. +#define BG_ENET_RDSR_R_DES_START(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RDSR_R_DES_START) >> BP_ENET_RDSR_R_DES_START) + +//! @brief Format value for bitfield ENET_RDSR_R_DES_START. +#define BF_ENET_RDSR_R_DES_START(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RDSR_R_DES_START) & BM_ENET_RDSR_R_DES_START) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the R_DES_START field to a new value. +#define BW_ENET_RDSR_R_DES_START(v) (HW_ENET_RDSR_WR((HW_ENET_RDSR_RD() & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW) + * + * Reset value: 0x00000000 + * + * TDSR provides a pointer to the beginning of the circular transmit buffer descriptor queue in + * external memory. This pointer must be 64-bit aligned (bits 2–0 must be zero); however, This + * register must be initialized prior to operation. + */ +typedef union _hw_enet_tdsr +{ + reg32_t U; + struct _hw_enet_tdsr_bitfields + { + unsigned RESERVED0 : 3; //!< [2:0] + unsigned X_DES_START : 29; //!< [31:3] Pointer to the beginning of the transmit buffer descriptor queue. + } B; +} hw_enet_tdsr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TDSR register + */ +//@{ +#define HW_ENET_TDSR_ADDR (REGS_ENET_BASE + 0x184) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TDSR (*(volatile hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR) +#define HW_ENET_TDSR_RD() (HW_ENET_TDSR.U) +#define HW_ENET_TDSR_WR(v) (HW_ENET_TDSR.U = (v)) +#define HW_ENET_TDSR_SET(v) (HW_ENET_TDSR_WR(HW_ENET_TDSR_RD() | (v))) +#define HW_ENET_TDSR_CLR(v) (HW_ENET_TDSR_WR(HW_ENET_TDSR_RD() & ~(v))) +#define HW_ENET_TDSR_TOG(v) (HW_ENET_TDSR_WR(HW_ENET_TDSR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TDSR bitfields + */ + +/*! @name Register ENET_TDSR, field X_DES_START[31:3] (RW) + * + * Pointer to the beginning of the transmit buffer descriptor queue. + */ +//@{ +#define BP_ENET_TDSR_X_DES_START (3) //!< Bit position for ENET_TDSR_X_DES_START. +#define BM_ENET_TDSR_X_DES_START (0xfffffff8) //!< Bit mask for ENET_TDSR_X_DES_START. + +//! @brief Get value of ENET_TDSR_X_DES_START from a register value. +#define BG_ENET_TDSR_X_DES_START(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TDSR_X_DES_START) >> BP_ENET_TDSR_X_DES_START) + +//! @brief Format value for bitfield ENET_TDSR_X_DES_START. +#define BF_ENET_TDSR_X_DES_START(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TDSR_X_DES_START) & BM_ENET_TDSR_X_DES_START) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the X_DES_START field to a new value. +#define BW_ENET_TDSR_X_DES_START(v) (HW_ENET_TDSR_WR((HW_ENET_TDSR_RD() & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_MRBR - Maximum Receive Buffer Size Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW) + * + * Reset value: 0x00000000 + * + * The MRBR is a user-programmable register that dictates the maximum size of all receive buffers. + * This value should take into consideration that the receive CRC is always written into the last + * receive buffer. To allow one maximum size frame per buffer, MRBR must be set to RCR[MAX_FL] or + * larger. To properly align the buffer, MRBR must be evenly divisible by To minimize bus usage + * (descriptor fetches), set MRBR greater than or equal to 256 bytes. This register must be + * initialized before operation. + */ +typedef union _hw_enet_mrbr +{ + reg32_t U; + struct _hw_enet_mrbr_bitfields + { + unsigned RESERVED0 : 4; //!< [3:0] + unsigned R_BUF_SIZE : 10; //!< [13:4] Receive buffer size in bytes. + unsigned RESERVED1 : 18; //!< [31:14] + } B; +} hw_enet_mrbr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_MRBR register + */ +//@{ +#define HW_ENET_MRBR_ADDR (REGS_ENET_BASE + 0x188) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_MRBR (*(volatile hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR) +#define HW_ENET_MRBR_RD() (HW_ENET_MRBR.U) +#define HW_ENET_MRBR_WR(v) (HW_ENET_MRBR.U = (v)) +#define HW_ENET_MRBR_SET(v) (HW_ENET_MRBR_WR(HW_ENET_MRBR_RD() | (v))) +#define HW_ENET_MRBR_CLR(v) (HW_ENET_MRBR_WR(HW_ENET_MRBR_RD() & ~(v))) +#define HW_ENET_MRBR_TOG(v) (HW_ENET_MRBR_WR(HW_ENET_MRBR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_MRBR bitfields + */ + +/*! @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW) + * + * Receive buffer size in bytes. + */ +//@{ +#define BP_ENET_MRBR_R_BUF_SIZE (4) //!< Bit position for ENET_MRBR_R_BUF_SIZE. +#define BM_ENET_MRBR_R_BUF_SIZE (0x00003ff0) //!< Bit mask for ENET_MRBR_R_BUF_SIZE. + +//! @brief Get value of ENET_MRBR_R_BUF_SIZE from a register value. +#define BG_ENET_MRBR_R_BUF_SIZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_MRBR_R_BUF_SIZE) >> BP_ENET_MRBR_R_BUF_SIZE) + +//! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE. +#define BF_ENET_MRBR_R_BUF_SIZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_MRBR_R_BUF_SIZE) & BM_ENET_MRBR_R_BUF_SIZE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the R_BUF_SIZE field to a new value. +#define BW_ENET_MRBR_R_BUF_SIZE(v) (HW_ENET_MRBR_WR((HW_ENET_MRBR_RD() & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_RSFL - Receive FIFO Section Full Threshold +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_rsfl +{ + reg32_t U; + struct _hw_enet_rsfl_bitfields + { + unsigned RESERVED0 : 32; //!< [31:0] Reserved. + } B; +} hw_enet_rsfl_t; +#endif + +/*! + * @name Constants and macros for entire ENET_RSFL register + */ +//@{ +#define HW_ENET_RSFL_ADDR (REGS_ENET_BASE + 0x190) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_RSFL (*(volatile hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR) +#define HW_ENET_RSFL_RD() (HW_ENET_RSFL.U) +#define HW_ENET_RSFL_WR(v) (HW_ENET_RSFL.U = (v)) +#define HW_ENET_RSFL_SET(v) (HW_ENET_RSFL_WR(HW_ENET_RSFL_RD() | (v))) +#define HW_ENET_RSFL_CLR(v) (HW_ENET_RSFL_WR(HW_ENET_RSFL_RD() & ~(v))) +#define HW_ENET_RSFL_TOG(v) (HW_ENET_RSFL_WR(HW_ENET_RSFL_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_RSFL bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_ENET_RSEM - Receive FIFO Section Empty Threshold +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_rsem +{ + reg32_t U; + struct _hw_enet_rsem_bitfields + { + unsigned RESERVED0 : 32; //!< [31:0] Reserved. + } B; +} hw_enet_rsem_t; +#endif + +/*! + * @name Constants and macros for entire ENET_RSEM register + */ +//@{ +#define HW_ENET_RSEM_ADDR (REGS_ENET_BASE + 0x194) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_RSEM (*(volatile hw_enet_rsem_t *) HW_ENET_RSEM_ADDR) +#define HW_ENET_RSEM_RD() (HW_ENET_RSEM.U) +#define HW_ENET_RSEM_WR(v) (HW_ENET_RSEM.U = (v)) +#define HW_ENET_RSEM_SET(v) (HW_ENET_RSEM_WR(HW_ENET_RSEM_RD() | (v))) +#define HW_ENET_RSEM_CLR(v) (HW_ENET_RSEM_WR(HW_ENET_RSEM_RD() & ~(v))) +#define HW_ENET_RSEM_TOG(v) (HW_ENET_RSEM_WR(HW_ENET_RSEM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_RSEM bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_ENET_RAEM - Receive FIFO Almost Empty Threshold +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW) + * + * Reset value: 0x00000004 + */ +typedef union _hw_enet_raem +{ + reg32_t U; + struct _hw_enet_raem_bitfields + { + unsigned RESERVED0 : 32; //!< [31:0] Reserved. + } B; +} hw_enet_raem_t; +#endif + +/*! + * @name Constants and macros for entire ENET_RAEM register + */ +//@{ +#define HW_ENET_RAEM_ADDR (REGS_ENET_BASE + 0x198) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_RAEM (*(volatile hw_enet_raem_t *) HW_ENET_RAEM_ADDR) +#define HW_ENET_RAEM_RD() (HW_ENET_RAEM.U) +#define HW_ENET_RAEM_WR(v) (HW_ENET_RAEM.U = (v)) +#define HW_ENET_RAEM_SET(v) (HW_ENET_RAEM_WR(HW_ENET_RAEM_RD() | (v))) +#define HW_ENET_RAEM_CLR(v) (HW_ENET_RAEM_WR(HW_ENET_RAEM_RD() & ~(v))) +#define HW_ENET_RAEM_TOG(v) (HW_ENET_RAEM_WR(HW_ENET_RAEM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_RAEM bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_ENET_RAFL - Receive FIFO Almost Full Threshold +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW) + * + * Reset value: 0x00000004 + */ +typedef union _hw_enet_rafl +{ + reg32_t U; + struct _hw_enet_rafl_bitfields + { + unsigned RESERVED0 : 32; //!< [31:0] Reserved. + } B; +} hw_enet_rafl_t; +#endif + +/*! + * @name Constants and macros for entire ENET_RAFL register + */ +//@{ +#define HW_ENET_RAFL_ADDR (REGS_ENET_BASE + 0x19c) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_RAFL (*(volatile hw_enet_rafl_t *) HW_ENET_RAFL_ADDR) +#define HW_ENET_RAFL_RD() (HW_ENET_RAFL.U) +#define HW_ENET_RAFL_WR(v) (HW_ENET_RAFL.U = (v)) +#define HW_ENET_RAFL_SET(v) (HW_ENET_RAFL_WR(HW_ENET_RAFL_RD() | (v))) +#define HW_ENET_RAFL_CLR(v) (HW_ENET_RAFL_WR(HW_ENET_RAFL_RD() & ~(v))) +#define HW_ENET_RAFL_TOG(v) (HW_ENET_RAFL_WR(HW_ENET_RAFL_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_RAFL bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_ENET_TSEM - Transmit FIFO Section Empty Threshold +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_tsem +{ + reg32_t U; + struct _hw_enet_tsem_bitfields + { + unsigned RESERVED0 : 32; //!< [31:0] Reserved. + } B; +} hw_enet_tsem_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TSEM register + */ +//@{ +#define HW_ENET_TSEM_ADDR (REGS_ENET_BASE + 0x1a0) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TSEM (*(volatile hw_enet_tsem_t *) HW_ENET_TSEM_ADDR) +#define HW_ENET_TSEM_RD() (HW_ENET_TSEM.U) +#define HW_ENET_TSEM_WR(v) (HW_ENET_TSEM.U = (v)) +#define HW_ENET_TSEM_SET(v) (HW_ENET_TSEM_WR(HW_ENET_TSEM_RD() | (v))) +#define HW_ENET_TSEM_CLR(v) (HW_ENET_TSEM_WR(HW_ENET_TSEM_RD() & ~(v))) +#define HW_ENET_TSEM_TOG(v) (HW_ENET_TSEM_WR(HW_ENET_TSEM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TSEM bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW) + * + * Reset value: 0x00000004 + */ +typedef union _hw_enet_taem +{ + reg32_t U; + struct _hw_enet_taem_bitfields + { + unsigned RESERVED0 : 32; //!< [31:0] Reserved. + } B; +} hw_enet_taem_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TAEM register + */ +//@{ +#define HW_ENET_TAEM_ADDR (REGS_ENET_BASE + 0x1a4) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TAEM (*(volatile hw_enet_taem_t *) HW_ENET_TAEM_ADDR) +#define HW_ENET_TAEM_RD() (HW_ENET_TAEM.U) +#define HW_ENET_TAEM_WR(v) (HW_ENET_TAEM.U = (v)) +#define HW_ENET_TAEM_SET(v) (HW_ENET_TAEM_WR(HW_ENET_TAEM_RD() | (v))) +#define HW_ENET_TAEM_CLR(v) (HW_ENET_TAEM_WR(HW_ENET_TAEM_RD() & ~(v))) +#define HW_ENET_TAEM_TOG(v) (HW_ENET_TAEM_WR(HW_ENET_TAEM_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TAEM bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_ENET_TAFL - Transmit FIFO Almost Full Threshold +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW) + * + * Reset value: 0x00000008 + */ +typedef union _hw_enet_tafl +{ + reg32_t U; + struct _hw_enet_tafl_bitfields + { + unsigned RESERVED0 : 32; //!< [31:0] Reserved. + } B; +} hw_enet_tafl_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TAFL register + */ +//@{ +#define HW_ENET_TAFL_ADDR (REGS_ENET_BASE + 0x1a8) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TAFL (*(volatile hw_enet_tafl_t *) HW_ENET_TAFL_ADDR) +#define HW_ENET_TAFL_RD() (HW_ENET_TAFL.U) +#define HW_ENET_TAFL_WR(v) (HW_ENET_TAFL.U = (v)) +#define HW_ENET_TAFL_SET(v) (HW_ENET_TAFL_WR(HW_ENET_TAFL_RD() | (v))) +#define HW_ENET_TAFL_CLR(v) (HW_ENET_TAFL_WR(HW_ENET_TAFL_RD() & ~(v))) +#define HW_ENET_TAFL_TOG(v) (HW_ENET_TAFL_WR(HW_ENET_TAFL_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TAFL bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_ENET_TIPG - Transmit Inter-Packet Gap +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW) + * + * Reset value: 0x0000000c + */ +typedef union _hw_enet_tipg +{ + reg32_t U; + struct _hw_enet_tipg_bitfields + { + unsigned IPG : 5; //!< [4:0] Transmit Inter-Packet Gap + unsigned RESERVED0 : 27; //!< [31:5] + } B; +} hw_enet_tipg_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TIPG register + */ +//@{ +#define HW_ENET_TIPG_ADDR (REGS_ENET_BASE + 0x1ac) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TIPG (*(volatile hw_enet_tipg_t *) HW_ENET_TIPG_ADDR) +#define HW_ENET_TIPG_RD() (HW_ENET_TIPG.U) +#define HW_ENET_TIPG_WR(v) (HW_ENET_TIPG.U = (v)) +#define HW_ENET_TIPG_SET(v) (HW_ENET_TIPG_WR(HW_ENET_TIPG_RD() | (v))) +#define HW_ENET_TIPG_CLR(v) (HW_ENET_TIPG_WR(HW_ENET_TIPG_RD() & ~(v))) +#define HW_ENET_TIPG_TOG(v) (HW_ENET_TIPG_WR(HW_ENET_TIPG_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TIPG bitfields + */ + +/*! @name Register ENET_TIPG, field IPG[4:0] (RW) + * + * Indicates the IPG, in bytes, between transmitted frames. Valid values range from 8 to 27. If + * value is less than 8, the IPG is 8. If value is greater than 27, the IPG is 27. + */ +//@{ +#define BP_ENET_TIPG_IPG (0) //!< Bit position for ENET_TIPG_IPG. +#define BM_ENET_TIPG_IPG (0x0000001f) //!< Bit mask for ENET_TIPG_IPG. + +//! @brief Get value of ENET_TIPG_IPG from a register value. +#define BG_ENET_TIPG_IPG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TIPG_IPG) >> BP_ENET_TIPG_IPG) + +//! @brief Format value for bitfield ENET_TIPG_IPG. +#define BF_ENET_TIPG_IPG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TIPG_IPG) & BM_ENET_TIPG_IPG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPG field to a new value. +#define BW_ENET_TIPG_IPG(v) (HW_ENET_TIPG_WR((HW_ENET_TIPG_RD() & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_FTRL - Frame Truncation Length +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_FTRL - Frame Truncation Length (RW) + * + * Reset value: 0x000007ff + */ +typedef union _hw_enet_ftrl +{ + reg32_t U; + struct _hw_enet_ftrl_bitfields + { + unsigned TRUNC_FL : 14; //!< [13:0] Frame Truncation Length + unsigned RESERVED0 : 18; //!< [31:14] + } B; +} hw_enet_ftrl_t; +#endif + +/*! + * @name Constants and macros for entire ENET_FTRL register + */ +//@{ +#define HW_ENET_FTRL_ADDR (REGS_ENET_BASE + 0x1b0) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_FTRL (*(volatile hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR) +#define HW_ENET_FTRL_RD() (HW_ENET_FTRL.U) +#define HW_ENET_FTRL_WR(v) (HW_ENET_FTRL.U = (v)) +#define HW_ENET_FTRL_SET(v) (HW_ENET_FTRL_WR(HW_ENET_FTRL_RD() | (v))) +#define HW_ENET_FTRL_CLR(v) (HW_ENET_FTRL_WR(HW_ENET_FTRL_RD() & ~(v))) +#define HW_ENET_FTRL_TOG(v) (HW_ENET_FTRL_WR(HW_ENET_FTRL_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_FTRL bitfields + */ + +/*! @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW) + * + * Indicates the value a receive frame is truncated, if it is greater than this value. Must be + * greater than or equal to RCR[MAX_FL]. Truncation happens at TRUNC_FL. However, when truncation + * occurs, the application (FIFO) may receive less data, guaranteeing that it never receives more + * than the set limit. + */ +//@{ +#define BP_ENET_FTRL_TRUNC_FL (0) //!< Bit position for ENET_FTRL_TRUNC_FL. +#define BM_ENET_FTRL_TRUNC_FL (0x00003fff) //!< Bit mask for ENET_FTRL_TRUNC_FL. + +//! @brief Get value of ENET_FTRL_TRUNC_FL from a register value. +#define BG_ENET_FTRL_TRUNC_FL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_FTRL_TRUNC_FL) >> BP_ENET_FTRL_TRUNC_FL) + +//! @brief Format value for bitfield ENET_FTRL_TRUNC_FL. +#define BF_ENET_FTRL_TRUNC_FL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_FTRL_TRUNC_FL) & BM_ENET_FTRL_TRUNC_FL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TRUNC_FL field to a new value. +#define BW_ENET_FTRL_TRUNC_FL(v) (HW_ENET_FTRL_WR((HW_ENET_FTRL_RD() & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_TACC - Transmit Accelerator Function Configuration +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW) + * + * Reset value: 0x00000000 + * + * TACC controls accelerator actions when sending frames. The register can be changed before or + * after each frame, but it must remain unmodified during frame writes into the transmit FIFO. The + * TFWR[STRFWD] field must be set to use the checksum feature. + */ +typedef union _hw_enet_tacc +{ + reg32_t U; + struct _hw_enet_tacc_bitfields + { + unsigned SHIFT16 : 1; //!< [0] TX FIFO Shift-16 + unsigned RESERVED0 : 2; //!< [2:1] + unsigned IPCHK : 1; //!< [3] Enables insertion of IP header checksum. + unsigned PROCHK : 1; //!< [4] Enables insertion of protocol checksum. + unsigned RESERVED1 : 27; //!< [31:5] + } B; +} hw_enet_tacc_t; +#endif + +/*! + * @name Constants and macros for entire ENET_TACC register + */ +//@{ +#define HW_ENET_TACC_ADDR (REGS_ENET_BASE + 0x1c0) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_TACC (*(volatile hw_enet_tacc_t *) HW_ENET_TACC_ADDR) +#define HW_ENET_TACC_RD() (HW_ENET_TACC.U) +#define HW_ENET_TACC_WR(v) (HW_ENET_TACC.U = (v)) +#define HW_ENET_TACC_SET(v) (HW_ENET_TACC_WR(HW_ENET_TACC_RD() | (v))) +#define HW_ENET_TACC_CLR(v) (HW_ENET_TACC_WR(HW_ENET_TACC_RD() & ~(v))) +#define HW_ENET_TACC_TOG(v) (HW_ENET_TACC_WR(HW_ENET_TACC_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_TACC bitfields + */ + +/*! @name Register ENET_TACC, field SHIFT16[0] (RW) + * + * Values: + * - 0 - Disabled. + * - 1 - Indicates to the transmit data FIFO that the written frames contain two additional octets before the + * frame data. This means the actual frame begins at bit 16 of the first word written into the + * FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the + * 14-byte Ethernet header is extended to a 16-byte header. + */ +//@{ +#define BP_ENET_TACC_SHIFT16 (0) //!< Bit position for ENET_TACC_SHIFT16. +#define BM_ENET_TACC_SHIFT16 (0x00000001) //!< Bit mask for ENET_TACC_SHIFT16. + +//! @brief Get value of ENET_TACC_SHIFT16 from a register value. +#define BG_ENET_TACC_SHIFT16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TACC_SHIFT16) >> BP_ENET_TACC_SHIFT16) + +//! @brief Format value for bitfield ENET_TACC_SHIFT16. +#define BF_ENET_TACC_SHIFT16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TACC_SHIFT16) & BM_ENET_TACC_SHIFT16) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SHIFT16 field to a new value. +#define BW_ENET_TACC_SHIFT16(v) (HW_ENET_TACC_WR((HW_ENET_TACC_RD() & ~BM_ENET_TACC_SHIFT16) | BF_ENET_TACC_SHIFT16(v))) +#endif +//@} + +/*! @name Register ENET_TACC, field IPCHK[3] (RW) + * + * Enables insertion of IP header checksum. + * + * Values: + * - 0 - Checksum is not inserted. + * - 1 - If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field + * must be cleared. If a non-IP frame is transmitted the frame is not modified. + */ +//@{ +#define BP_ENET_TACC_IPCHK (3) //!< Bit position for ENET_TACC_IPCHK. +#define BM_ENET_TACC_IPCHK (0x00000008) //!< Bit mask for ENET_TACC_IPCHK. + +//! @brief Get value of ENET_TACC_IPCHK from a register value. +#define BG_ENET_TACC_IPCHK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TACC_IPCHK) >> BP_ENET_TACC_IPCHK) + +//! @brief Format value for bitfield ENET_TACC_IPCHK. +#define BF_ENET_TACC_IPCHK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TACC_IPCHK) & BM_ENET_TACC_IPCHK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPCHK field to a new value. +#define BW_ENET_TACC_IPCHK(v) (HW_ENET_TACC_WR((HW_ENET_TACC_RD() & ~BM_ENET_TACC_IPCHK) | BF_ENET_TACC_IPCHK(v))) +#endif +//@} + +/*! @name Register ENET_TACC, field PROCHK[4] (RW) + * + * Enables insertion of protocol checksum. + * + * Values: + * - 0 - Checksum not inserted. + * - 1 - If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the + * frame. The checksum field must be cleared. The other frames are not modified. + */ +//@{ +#define BP_ENET_TACC_PROCHK (4) //!< Bit position for ENET_TACC_PROCHK. +#define BM_ENET_TACC_PROCHK (0x00000010) //!< Bit mask for ENET_TACC_PROCHK. + +//! @brief Get value of ENET_TACC_PROCHK from a register value. +#define BG_ENET_TACC_PROCHK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_TACC_PROCHK) >> BP_ENET_TACC_PROCHK) + +//! @brief Format value for bitfield ENET_TACC_PROCHK. +#define BF_ENET_TACC_PROCHK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_TACC_PROCHK) & BM_ENET_TACC_PROCHK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PROCHK field to a new value. +#define BW_ENET_TACC_PROCHK(v) (HW_ENET_TACC_WR((HW_ENET_TACC_RD() & ~BM_ENET_TACC_PROCHK) | BF_ENET_TACC_PROCHK(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_RACC - Receive Accelerator Function Configuration +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_racc +{ + reg32_t U; + struct _hw_enet_racc_bitfields + { + unsigned PADREM : 1; //!< [0] Enable Padding Removal For Short IP Frames + unsigned IPDIS : 1; //!< [1] Enable Discard Of Frames With Wrong IPv4 Header Checksum + unsigned PRODIS : 1; //!< [2] Enable Discard Of Frames With Wrong Protocol Checksum + unsigned RESERVED0 : 3; //!< [5:3] + unsigned LINEDIS : 1; //!< [6] Enable Discard Of Frames With MAC Layer Errors + unsigned SHIFT16 : 1; //!< [7] RX FIFO Shift-16 + unsigned RESERVED1 : 24; //!< [31:8] + } B; +} hw_enet_racc_t; +#endif + +/*! + * @name Constants and macros for entire ENET_RACC register + */ +//@{ +#define HW_ENET_RACC_ADDR (REGS_ENET_BASE + 0x1c4) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_RACC (*(volatile hw_enet_racc_t *) HW_ENET_RACC_ADDR) +#define HW_ENET_RACC_RD() (HW_ENET_RACC.U) +#define HW_ENET_RACC_WR(v) (HW_ENET_RACC.U = (v)) +#define HW_ENET_RACC_SET(v) (HW_ENET_RACC_WR(HW_ENET_RACC_RD() | (v))) +#define HW_ENET_RACC_CLR(v) (HW_ENET_RACC_WR(HW_ENET_RACC_RD() & ~(v))) +#define HW_ENET_RACC_TOG(v) (HW_ENET_RACC_WR(HW_ENET_RACC_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_RACC bitfields + */ + +/*! @name Register ENET_RACC, field PADREM[0] (RW) + * + * Values: + * - 0 - Padding not removed. + * - 1 - Any bytes following the IP payload section of the frame are removed from the frame. + */ +//@{ +#define BP_ENET_RACC_PADREM (0) //!< Bit position for ENET_RACC_PADREM. +#define BM_ENET_RACC_PADREM (0x00000001) //!< Bit mask for ENET_RACC_PADREM. + +//! @brief Get value of ENET_RACC_PADREM from a register value. +#define BG_ENET_RACC_PADREM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RACC_PADREM) >> BP_ENET_RACC_PADREM) + +//! @brief Format value for bitfield ENET_RACC_PADREM. +#define BF_ENET_RACC_PADREM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RACC_PADREM) & BM_ENET_RACC_PADREM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PADREM field to a new value. +#define BW_ENET_RACC_PADREM(v) (HW_ENET_RACC_WR((HW_ENET_RACC_RD() & ~BM_ENET_RACC_PADREM) | BF_ENET_RACC_PADREM(v))) +#endif +//@} + +/*! @name Register ENET_RACC, field IPDIS[1] (RW) + * + * Values: + * - 0 - Frames with wrong IPv4 header checksum are not discarded. + * - 1 - If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no + * header checksum and is not affected by this setting. Discarding is only available when the RX + * FIFO operates in store and forward mode (RSFL cleared). + */ +//@{ +#define BP_ENET_RACC_IPDIS (1) //!< Bit position for ENET_RACC_IPDIS. +#define BM_ENET_RACC_IPDIS (0x00000002) //!< Bit mask for ENET_RACC_IPDIS. + +//! @brief Get value of ENET_RACC_IPDIS from a register value. +#define BG_ENET_RACC_IPDIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RACC_IPDIS) >> BP_ENET_RACC_IPDIS) + +//! @brief Format value for bitfield ENET_RACC_IPDIS. +#define BF_ENET_RACC_IPDIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RACC_IPDIS) & BM_ENET_RACC_IPDIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPDIS field to a new value. +#define BW_ENET_RACC_IPDIS(v) (HW_ENET_RACC_WR((HW_ENET_RACC_RD() & ~BM_ENET_RACC_IPDIS) | BF_ENET_RACC_IPDIS(v))) +#endif +//@} + +/*! @name Register ENET_RACC, field PRODIS[2] (RW) + * + * Values: + * - 0 - Frames with wrong checksum are not discarded. + * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the + * frame is discarded. Discarding is only available when the RX FIFO operates in store and + * forward mode (RSFL cleared). + */ +//@{ +#define BP_ENET_RACC_PRODIS (2) //!< Bit position for ENET_RACC_PRODIS. +#define BM_ENET_RACC_PRODIS (0x00000004) //!< Bit mask for ENET_RACC_PRODIS. + +//! @brief Get value of ENET_RACC_PRODIS from a register value. +#define BG_ENET_RACC_PRODIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RACC_PRODIS) >> BP_ENET_RACC_PRODIS) + +//! @brief Format value for bitfield ENET_RACC_PRODIS. +#define BF_ENET_RACC_PRODIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RACC_PRODIS) & BM_ENET_RACC_PRODIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PRODIS field to a new value. +#define BW_ENET_RACC_PRODIS(v) (HW_ENET_RACC_WR((HW_ENET_RACC_RD() & ~BM_ENET_RACC_PRODIS) | BF_ENET_RACC_PRODIS(v))) +#endif +//@} + +/*! @name Register ENET_RACC, field LINEDIS[6] (RW) + * + * Values: + * - 0 - Frames with errors are not discarded. + * - 1 - Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to + * the user application interface. + */ +//@{ +#define BP_ENET_RACC_LINEDIS (6) //!< Bit position for ENET_RACC_LINEDIS. +#define BM_ENET_RACC_LINEDIS (0x00000040) //!< Bit mask for ENET_RACC_LINEDIS. + +//! @brief Get value of ENET_RACC_LINEDIS from a register value. +#define BG_ENET_RACC_LINEDIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RACC_LINEDIS) >> BP_ENET_RACC_LINEDIS) + +//! @brief Format value for bitfield ENET_RACC_LINEDIS. +#define BF_ENET_RACC_LINEDIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RACC_LINEDIS) & BM_ENET_RACC_LINEDIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LINEDIS field to a new value. +#define BW_ENET_RACC_LINEDIS(v) (HW_ENET_RACC_WR((HW_ENET_RACC_RD() & ~BM_ENET_RACC_LINEDIS) | BF_ENET_RACC_LINEDIS(v))) +#endif +//@} + +/*! @name Register ENET_RACC, field SHIFT16[7] (RW) + * + * When this field is set, the actual frame data starts at bit 16 of the first word read from the RX + * FIFO aligning the Ethernet payload on a 32-bit boundary. This function only affects the FIFO + * storage and has no influence on the statistics, which use the actual length of the frame + * received. + * + * Values: + * - 0 - Disabled. + * - 1 - Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ +//@{ +#define BP_ENET_RACC_SHIFT16 (7) //!< Bit position for ENET_RACC_SHIFT16. +#define BM_ENET_RACC_SHIFT16 (0x00000080) //!< Bit mask for ENET_RACC_SHIFT16. + +//! @brief Get value of ENET_RACC_SHIFT16 from a register value. +#define BG_ENET_RACC_SHIFT16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_RACC_SHIFT16) >> BP_ENET_RACC_SHIFT16) + +//! @brief Format value for bitfield ENET_RACC_SHIFT16. +#define BF_ENET_RACC_SHIFT16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_RACC_SHIFT16) & BM_ENET_RACC_SHIFT16) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SHIFT16 field to a new value. +#define BW_ENET_RACC_SHIFT16(v) (HW_ENET_RACC_WR((HW_ENET_RACC_RD() & ~BM_ENET_RACC_SHIFT16) | BF_ENET_RACC_SHIFT16(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_ATCR - Timer Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_ATCR - Timer Control Register (RW) + * + * Reset value: 0x00000000 + * + * ATCR command fields can trigger the corresponding events directly. It is not necessary to + * preserve any of the configuration fields when a command field is set in the register, that is, no + * read-modify-write is required. The fields are automatically cleared after the command completes. + */ +typedef union _hw_enet_atcr +{ + reg32_t U; + struct _hw_enet_atcr_bitfields + { + unsigned EN : 1; //!< [0] Enable Timer + unsigned RESERVED0 : 1; //!< [1] + unsigned OFFEN : 1; //!< [2] Enable One-Shot Offset Event + unsigned OFFRST : 1; //!< [3] Reset Timer On Offset Event + unsigned PEREN : 1; //!< [4] Enable Periodical Event + unsigned RESERVED1 : 2; //!< [6:5] + unsigned PINPER : 1; //!< [7] Enables event signal output assertion on period event. + unsigned RESERVED2 : 1; //!< [8] + unsigned RESTART : 1; //!< [9] Reset Timer + unsigned RESERVED3 : 1; //!< [10] + unsigned CAPTURE : 1; //!< [11] Capture Timer Value + unsigned RESERVED4 : 1; //!< [12] + unsigned SLAVE : 1; //!< [13] Enable Timer Slave Mode + unsigned RESERVED5 : 18; //!< [31:14] + } B; +} hw_enet_atcr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_ATCR register + */ +//@{ +#define HW_ENET_ATCR_ADDR (REGS_ENET_BASE + 0x400) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_ATCR (*(volatile hw_enet_atcr_t *) HW_ENET_ATCR_ADDR) +#define HW_ENET_ATCR_RD() (HW_ENET_ATCR.U) +#define HW_ENET_ATCR_WR(v) (HW_ENET_ATCR.U = (v)) +#define HW_ENET_ATCR_SET(v) (HW_ENET_ATCR_WR(HW_ENET_ATCR_RD() | (v))) +#define HW_ENET_ATCR_CLR(v) (HW_ENET_ATCR_WR(HW_ENET_ATCR_RD() & ~(v))) +#define HW_ENET_ATCR_TOG(v) (HW_ENET_ATCR_WR(HW_ENET_ATCR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_ATCR bitfields + */ + +/*! @name Register ENET_ATCR, field EN[0] (RW) + * + * Values: + * - 0 - The timer stops at the current value. + * - 1 - The timer starts incrementing. + */ +//@{ +#define BP_ENET_ATCR_EN (0) //!< Bit position for ENET_ATCR_EN. +#define BM_ENET_ATCR_EN (0x00000001) //!< Bit mask for ENET_ATCR_EN. + +//! @brief Get value of ENET_ATCR_EN from a register value. +#define BG_ENET_ATCR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCR_EN) >> BP_ENET_ATCR_EN) + +//! @brief Format value for bitfield ENET_ATCR_EN. +#define BF_ENET_ATCR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCR_EN) & BM_ENET_ATCR_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN field to a new value. +#define BW_ENET_ATCR_EN(v) (HW_ENET_ATCR_WR((HW_ENET_ATCR_RD() & ~BM_ENET_ATCR_EN) | BF_ENET_ATCR_EN(v))) +#endif +//@} + +/*! @name Register ENET_ATCR, field OFFEN[2] (RW) + * + * Values: + * - 0 - Disable. + * - 1 - The timer can be reset to zero when the given offset time is reached (offset event). The field is + * cleared when the offset event is reached, so no further event occurs until the field is set + * again. The timer offset value must be set before setting this field. + */ +//@{ +#define BP_ENET_ATCR_OFFEN (2) //!< Bit position for ENET_ATCR_OFFEN. +#define BM_ENET_ATCR_OFFEN (0x00000004) //!< Bit mask for ENET_ATCR_OFFEN. + +//! @brief Get value of ENET_ATCR_OFFEN from a register value. +#define BG_ENET_ATCR_OFFEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCR_OFFEN) >> BP_ENET_ATCR_OFFEN) + +//! @brief Format value for bitfield ENET_ATCR_OFFEN. +#define BF_ENET_ATCR_OFFEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCR_OFFEN) & BM_ENET_ATCR_OFFEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OFFEN field to a new value. +#define BW_ENET_ATCR_OFFEN(v) (HW_ENET_ATCR_WR((HW_ENET_ATCR_RD() & ~BM_ENET_ATCR_OFFEN) | BF_ENET_ATCR_OFFEN(v))) +#endif +//@} + +/*! @name Register ENET_ATCR, field OFFRST[3] (RW) + * + * Values: + * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does + * not cause a timer interrupt. + */ +//@{ +#define BP_ENET_ATCR_OFFRST (3) //!< Bit position for ENET_ATCR_OFFRST. +#define BM_ENET_ATCR_OFFRST (0x00000008) //!< Bit mask for ENET_ATCR_OFFRST. + +//! @brief Get value of ENET_ATCR_OFFRST from a register value. +#define BG_ENET_ATCR_OFFRST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCR_OFFRST) >> BP_ENET_ATCR_OFFRST) + +//! @brief Format value for bitfield ENET_ATCR_OFFRST. +#define BF_ENET_ATCR_OFFRST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCR_OFFRST) & BM_ENET_ATCR_OFFRST) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OFFRST field to a new value. +#define BW_ENET_ATCR_OFFRST(v) (HW_ENET_ATCR_WR((HW_ENET_ATCR_RD() & ~BM_ENET_ATCR_OFFRST) | BF_ENET_ATCR_OFFRST(v))) +#endif +//@} + +/*! @name Register ENET_ATCR, field PEREN[4] (RW) + * + * Values: + * - 0 - Disable. + * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted + * when the timer wraps around according to the periodic setting ATPER. The timer period value + * must be set before setting this bit. Not all devices contain the event signal output. See the + * chip configuration details. + */ +//@{ +#define BP_ENET_ATCR_PEREN (4) //!< Bit position for ENET_ATCR_PEREN. +#define BM_ENET_ATCR_PEREN (0x00000010) //!< Bit mask for ENET_ATCR_PEREN. + +//! @brief Get value of ENET_ATCR_PEREN from a register value. +#define BG_ENET_ATCR_PEREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCR_PEREN) >> BP_ENET_ATCR_PEREN) + +//! @brief Format value for bitfield ENET_ATCR_PEREN. +#define BF_ENET_ATCR_PEREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCR_PEREN) & BM_ENET_ATCR_PEREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PEREN field to a new value. +#define BW_ENET_ATCR_PEREN(v) (HW_ENET_ATCR_WR((HW_ENET_ATCR_RD() & ~BM_ENET_ATCR_PEREN) | BF_ENET_ATCR_PEREN(v))) +#endif +//@} + +/*! @name Register ENET_ATCR, field PINPER[7] (RW) + * + * Enables event signal output assertion on period event. Not all devices contain the event signal + * output. See the chip configuration details. + * + * Values: + * - 0 - Disable. + * - 1 - Enable. + */ +//@{ +#define BP_ENET_ATCR_PINPER (7) //!< Bit position for ENET_ATCR_PINPER. +#define BM_ENET_ATCR_PINPER (0x00000080) //!< Bit mask for ENET_ATCR_PINPER. + +//! @brief Get value of ENET_ATCR_PINPER from a register value. +#define BG_ENET_ATCR_PINPER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCR_PINPER) >> BP_ENET_ATCR_PINPER) + +//! @brief Format value for bitfield ENET_ATCR_PINPER. +#define BF_ENET_ATCR_PINPER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCR_PINPER) & BM_ENET_ATCR_PINPER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PINPER field to a new value. +#define BW_ENET_ATCR_PINPER(v) (HW_ENET_ATCR_WR((HW_ENET_ATCR_RD() & ~BM_ENET_ATCR_PINPER) | BF_ENET_ATCR_PINPER(v))) +#endif +//@} + +/*! @name Register ENET_ATCR, field RESTART[9] (RW) + * + * Resets the timer to zero. This has no effect on the counter enable. If the counter is enabled + * when this field is set, the timer is reset to zero and starts counting from there. When set, all + * other fields are ignored during a write. + */ +//@{ +#define BP_ENET_ATCR_RESTART (9) //!< Bit position for ENET_ATCR_RESTART. +#define BM_ENET_ATCR_RESTART (0x00000200) //!< Bit mask for ENET_ATCR_RESTART. + +//! @brief Get value of ENET_ATCR_RESTART from a register value. +#define BG_ENET_ATCR_RESTART(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCR_RESTART) >> BP_ENET_ATCR_RESTART) + +//! @brief Format value for bitfield ENET_ATCR_RESTART. +#define BF_ENET_ATCR_RESTART(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCR_RESTART) & BM_ENET_ATCR_RESTART) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RESTART field to a new value. +#define BW_ENET_ATCR_RESTART(v) (HW_ENET_ATCR_WR((HW_ENET_ATCR_RD() & ~BM_ENET_ATCR_RESTART) | BF_ENET_ATCR_RESTART(v))) +#endif +//@} + +/*! @name Register ENET_ATCR, field CAPTURE[11] (RW) + * + * Values: + * - 0 - No effect. + * - 1 - The current time is captured and can be read from the ATVR register. + */ +//@{ +#define BP_ENET_ATCR_CAPTURE (11) //!< Bit position for ENET_ATCR_CAPTURE. +#define BM_ENET_ATCR_CAPTURE (0x00000800) //!< Bit mask for ENET_ATCR_CAPTURE. + +//! @brief Get value of ENET_ATCR_CAPTURE from a register value. +#define BG_ENET_ATCR_CAPTURE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCR_CAPTURE) >> BP_ENET_ATCR_CAPTURE) + +//! @brief Format value for bitfield ENET_ATCR_CAPTURE. +#define BF_ENET_ATCR_CAPTURE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCR_CAPTURE) & BM_ENET_ATCR_CAPTURE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CAPTURE field to a new value. +#define BW_ENET_ATCR_CAPTURE(v) (HW_ENET_ATCR_WR((HW_ENET_ATCR_RD() & ~BM_ENET_ATCR_CAPTURE) | BF_ENET_ATCR_CAPTURE(v))) +#endif +//@} + +/*! @name Register ENET_ATCR, field SLAVE[13] (RW) + * + * Values: + * - 0 - The timer is active and all configuration fields in this register are relevant. + * - 1 - The internal timer is disabled and the externally provided timer value is used. All other fields, + * except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the + * current timer value. + */ +//@{ +#define BP_ENET_ATCR_SLAVE (13) //!< Bit position for ENET_ATCR_SLAVE. +#define BM_ENET_ATCR_SLAVE (0x00002000) //!< Bit mask for ENET_ATCR_SLAVE. + +//! @brief Get value of ENET_ATCR_SLAVE from a register value. +#define BG_ENET_ATCR_SLAVE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCR_SLAVE) >> BP_ENET_ATCR_SLAVE) + +//! @brief Format value for bitfield ENET_ATCR_SLAVE. +#define BF_ENET_ATCR_SLAVE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCR_SLAVE) & BM_ENET_ATCR_SLAVE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SLAVE field to a new value. +#define BW_ENET_ATCR_SLAVE(v) (HW_ENET_ATCR_WR((HW_ENET_ATCR_RD() & ~BM_ENET_ATCR_SLAVE) | BF_ENET_ATCR_SLAVE(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_ATVR - Timer Value Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_ATVR - Timer Value Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_atvr +{ + reg32_t U; + struct _hw_enet_atvr_bitfields + { + unsigned ATIME : 32; //!< [31:0] A write sets the timer. + } B; +} hw_enet_atvr_t; +#endif + +/*! + * @name Constants and macros for entire ENET_ATVR register + */ +//@{ +#define HW_ENET_ATVR_ADDR (REGS_ENET_BASE + 0x404) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_ATVR (*(volatile hw_enet_atvr_t *) HW_ENET_ATVR_ADDR) +#define HW_ENET_ATVR_RD() (HW_ENET_ATVR.U) +#define HW_ENET_ATVR_WR(v) (HW_ENET_ATVR.U = (v)) +#define HW_ENET_ATVR_SET(v) (HW_ENET_ATVR_WR(HW_ENET_ATVR_RD() | (v))) +#define HW_ENET_ATVR_CLR(v) (HW_ENET_ATVR_WR(HW_ENET_ATVR_RD() & ~(v))) +#define HW_ENET_ATVR_TOG(v) (HW_ENET_ATVR_WR(HW_ENET_ATVR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_ATVR bitfields + */ + +/*! @name Register ENET_ATVR, field ATIME[31:0] (RW) + * + * A write sets the timer. A read returns the last captured value. To read the current value, issue + * a capture command (set ATCR[CAPTURE]) prior to reading this register. + */ +//@{ +#define BP_ENET_ATVR_ATIME (0) //!< Bit position for ENET_ATVR_ATIME. +#define BM_ENET_ATVR_ATIME (0xffffffff) //!< Bit mask for ENET_ATVR_ATIME. + +//! @brief Get value of ENET_ATVR_ATIME from a register value. +#define BG_ENET_ATVR_ATIME(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATVR_ATIME) >> BP_ENET_ATVR_ATIME) + +//! @brief Format value for bitfield ENET_ATVR_ATIME. +#define BF_ENET_ATVR_ATIME(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATVR_ATIME) & BM_ENET_ATVR_ATIME) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ATIME field to a new value. +#define BW_ENET_ATVR_ATIME(v) (HW_ENET_ATVR_WR((HW_ENET_ATVR_RD() & ~BM_ENET_ATVR_ATIME) | BF_ENET_ATVR_ATIME(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_ATOFF - Timer Offset Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_ATOFF - Timer Offset Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_atoff +{ + reg32_t U; + struct _hw_enet_atoff_bitfields + { + unsigned OFFSET : 32; //!< [31:0] Offset value for one-shot event generation. + } B; +} hw_enet_atoff_t; +#endif + +/*! + * @name Constants and macros for entire ENET_ATOFF register + */ +//@{ +#define HW_ENET_ATOFF_ADDR (REGS_ENET_BASE + 0x408) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_ATOFF (*(volatile hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR) +#define HW_ENET_ATOFF_RD() (HW_ENET_ATOFF.U) +#define HW_ENET_ATOFF_WR(v) (HW_ENET_ATOFF.U = (v)) +#define HW_ENET_ATOFF_SET(v) (HW_ENET_ATOFF_WR(HW_ENET_ATOFF_RD() | (v))) +#define HW_ENET_ATOFF_CLR(v) (HW_ENET_ATOFF_WR(HW_ENET_ATOFF_RD() & ~(v))) +#define HW_ENET_ATOFF_TOG(v) (HW_ENET_ATOFF_WR(HW_ENET_ATOFF_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_ATOFF bitfields + */ + +/*! @name Register ENET_ATOFF, field OFFSET[31:0] (RW) + * + * Offset value for one-shot event generation. When the timer reaches the value, an event can be + * generated to reset the counter. If the increment value in ATINC is given in true nanoseconds, + * this value is also given in true nanoseconds. + */ +//@{ +#define BP_ENET_ATOFF_OFFSET (0) //!< Bit position for ENET_ATOFF_OFFSET. +#define BM_ENET_ATOFF_OFFSET (0xffffffff) //!< Bit mask for ENET_ATOFF_OFFSET. + +//! @brief Get value of ENET_ATOFF_OFFSET from a register value. +#define BG_ENET_ATOFF_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATOFF_OFFSET) >> BP_ENET_ATOFF_OFFSET) + +//! @brief Format value for bitfield ENET_ATOFF_OFFSET. +#define BF_ENET_ATOFF_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATOFF_OFFSET) & BM_ENET_ATOFF_OFFSET) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OFFSET field to a new value. +#define BW_ENET_ATOFF_OFFSET(v) (HW_ENET_ATOFF_WR((HW_ENET_ATOFF_RD() & ~BM_ENET_ATOFF_OFFSET) | BF_ENET_ATOFF_OFFSET(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_ATPER - Timer Period Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_ATPER - Timer Period Register (RW) + * + * Reset value: 0x3b9aca00 + */ +typedef union _hw_enet_atper +{ + reg32_t U; + struct _hw_enet_atper_bitfields + { + unsigned PERIOD : 32; //!< [31:0] Value for generating periodic events. + } B; +} hw_enet_atper_t; +#endif + +/*! + * @name Constants and macros for entire ENET_ATPER register + */ +//@{ +#define HW_ENET_ATPER_ADDR (REGS_ENET_BASE + 0x40c) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_ATPER (*(volatile hw_enet_atper_t *) HW_ENET_ATPER_ADDR) +#define HW_ENET_ATPER_RD() (HW_ENET_ATPER.U) +#define HW_ENET_ATPER_WR(v) (HW_ENET_ATPER.U = (v)) +#define HW_ENET_ATPER_SET(v) (HW_ENET_ATPER_WR(HW_ENET_ATPER_RD() | (v))) +#define HW_ENET_ATPER_CLR(v) (HW_ENET_ATPER_WR(HW_ENET_ATPER_RD() & ~(v))) +#define HW_ENET_ATPER_TOG(v) (HW_ENET_ATPER_WR(HW_ENET_ATPER_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_ATPER bitfields + */ + +/*! @name Register ENET_ATPER, field PERIOD[31:0] (RW) + * + * Value for generating periodic events. Each instance the timer reaches this value, the period + * event occurs and the timer restarts. If the increment value in ATINC is given in true + * nanoseconds, this value is also given in true nanoseconds. The value should be initialized to + * 1,000,000,000 (1 x 10 9 ) to represent a timer wrap around of one second. The increment value set + * in ATINC should be set to the true nanoseconds of the period of clock ts_clk, hence implementing + * a true 1 second counter. + */ +//@{ +#define BP_ENET_ATPER_PERIOD (0) //!< Bit position for ENET_ATPER_PERIOD. +#define BM_ENET_ATPER_PERIOD (0xffffffff) //!< Bit mask for ENET_ATPER_PERIOD. + +//! @brief Get value of ENET_ATPER_PERIOD from a register value. +#define BG_ENET_ATPER_PERIOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATPER_PERIOD) >> BP_ENET_ATPER_PERIOD) + +//! @brief Format value for bitfield ENET_ATPER_PERIOD. +#define BF_ENET_ATPER_PERIOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATPER_PERIOD) & BM_ENET_ATPER_PERIOD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PERIOD field to a new value. +#define BW_ENET_ATPER_PERIOD(v) (HW_ENET_ATPER_WR((HW_ENET_ATPER_RD() & ~BM_ENET_ATPER_PERIOD) | BF_ENET_ATPER_PERIOD(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_ATCOR - Timer Correction Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_ATCOR - Timer Correction Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_atcor +{ + reg32_t U; + struct _hw_enet_atcor_bitfields + { + unsigned COR : 31; //!< [30:0] Correction Counter Wrap-Around Value + unsigned RESERVED0 : 1; //!< [31] + } B; +} hw_enet_atcor_t; +#endif + +/*! + * @name Constants and macros for entire ENET_ATCOR register + */ +//@{ +#define HW_ENET_ATCOR_ADDR (REGS_ENET_BASE + 0x410) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_ATCOR (*(volatile hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR) +#define HW_ENET_ATCOR_RD() (HW_ENET_ATCOR.U) +#define HW_ENET_ATCOR_WR(v) (HW_ENET_ATCOR.U = (v)) +#define HW_ENET_ATCOR_SET(v) (HW_ENET_ATCOR_WR(HW_ENET_ATCOR_RD() | (v))) +#define HW_ENET_ATCOR_CLR(v) (HW_ENET_ATCOR_WR(HW_ENET_ATCOR_RD() & ~(v))) +#define HW_ENET_ATCOR_TOG(v) (HW_ENET_ATCOR_WR(HW_ENET_ATCOR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_ATCOR bitfields + */ + +/*! @name Register ENET_ATCOR, field COR[30:0] (RW) + * + * Defines after how many timer clock cycles (ts_clk) the correction counter should be reset and + * trigger a correction increment on the timer. The amount of correction is defined in + * ATINC[INC_CORR]. A value of 0 disables the correction counter and no corrections occur. This + * value is given in clock cycles, not in nanoseconds as all other values. + */ +//@{ +#define BP_ENET_ATCOR_COR (0) //!< Bit position for ENET_ATCOR_COR. +#define BM_ENET_ATCOR_COR (0x7fffffff) //!< Bit mask for ENET_ATCOR_COR. + +//! @brief Get value of ENET_ATCOR_COR from a register value. +#define BG_ENET_ATCOR_COR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATCOR_COR) >> BP_ENET_ATCOR_COR) + +//! @brief Format value for bitfield ENET_ATCOR_COR. +#define BF_ENET_ATCOR_COR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATCOR_COR) & BM_ENET_ATCOR_COR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the COR field to a new value. +#define BW_ENET_ATCOR_COR(v) (HW_ENET_ATCOR_WR((HW_ENET_ATCOR_RD() & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_ATINC - Time-Stamping Clock Period Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_atinc +{ + reg32_t U; + struct _hw_enet_atinc_bitfields + { + unsigned INC : 7; //!< [6:0] Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + unsigned RESERVED0 : 1; //!< [7] + unsigned INC_CORR : 7; //!< [14:8] Correction Increment Value + unsigned RESERVED1 : 17; //!< [31:15] + } B; +} hw_enet_atinc_t; +#endif + +/*! + * @name Constants and macros for entire ENET_ATINC register + */ +//@{ +#define HW_ENET_ATINC_ADDR (REGS_ENET_BASE + 0x414) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_ATINC (*(volatile hw_enet_atinc_t *) HW_ENET_ATINC_ADDR) +#define HW_ENET_ATINC_RD() (HW_ENET_ATINC.U) +#define HW_ENET_ATINC_WR(v) (HW_ENET_ATINC.U = (v)) +#define HW_ENET_ATINC_SET(v) (HW_ENET_ATINC_WR(HW_ENET_ATINC_RD() | (v))) +#define HW_ENET_ATINC_CLR(v) (HW_ENET_ATINC_WR(HW_ENET_ATINC_RD() & ~(v))) +#define HW_ENET_ATINC_TOG(v) (HW_ENET_ATINC_WR(HW_ENET_ATINC_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual ENET_ATINC bitfields + */ + +/*! @name Register ENET_ATINC, field INC[6:0] (RW) + * + * The timer increments by this amount each clock cycle. For example, set to 10 for 100 MHz, 8 for + * 125 MHz, 5 for 200 MHz. For highest precision, use a value that is an integer fraction of the + * period set in ATPER. + */ +//@{ +#define BP_ENET_ATINC_INC (0) //!< Bit position for ENET_ATINC_INC. +#define BM_ENET_ATINC_INC (0x0000007f) //!< Bit mask for ENET_ATINC_INC. + +//! @brief Get value of ENET_ATINC_INC from a register value. +#define BG_ENET_ATINC_INC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATINC_INC) >> BP_ENET_ATINC_INC) + +//! @brief Format value for bitfield ENET_ATINC_INC. +#define BF_ENET_ATINC_INC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATINC_INC) & BM_ENET_ATINC_INC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the INC field to a new value. +#define BW_ENET_ATINC_INC(v) (HW_ENET_ATINC_WR((HW_ENET_ATINC_RD() & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v))) +#endif +//@} + +/*! @name Register ENET_ATINC, field INC_CORR[14:8] (RW) + * + * This value is added every time the correction timer expires (every clock cycle given in ATCOR). A + * value smaller than INC slows the timer, while a value larger than INC speeds the timer. + */ +//@{ +#define BP_ENET_ATINC_INC_CORR (8) //!< Bit position for ENET_ATINC_INC_CORR. +#define BM_ENET_ATINC_INC_CORR (0x00007f00) //!< Bit mask for ENET_ATINC_INC_CORR. + +//! @brief Get value of ENET_ATINC_INC_CORR from a register value. +#define BG_ENET_ATINC_INC_CORR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATINC_INC_CORR) >> BP_ENET_ATINC_INC_CORR) + +//! @brief Format value for bitfield ENET_ATINC_INC_CORR. +#define BF_ENET_ATINC_INC_CORR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ENET_ATINC_INC_CORR) & BM_ENET_ATINC_INC_CORR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the INC_CORR field to a new value. +#define BW_ENET_ATINC_INC_CORR(v) (HW_ENET_ATINC_WR((HW_ENET_ATINC_RD() & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO) + * + * Reset value: 0x00000000 + */ +typedef union _hw_enet_atstmp +{ + reg32_t U; + struct _hw_enet_atstmp_bitfields + { + unsigned TIMESTAMP : 32; //!< [31:0] Timestamp of the last frame transmitted by the core that had TxBD[TS] set . + } B; +} hw_enet_atstmp_t; +#endif + +/*! + * @name Constants and macros for entire ENET_ATSTMP register + */ +//@{ +#define HW_ENET_ATSTMP_ADDR (REGS_ENET_BASE + 0x418) + +#ifndef __LANGUAGE_ASM__ +#define HW_ENET_ATSTMP (*(volatile hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR) +#define HW_ENET_ATSTMP_RD() (HW_ENET_ATSTMP.U) +#endif +//@} + +/* + * constants & macros for individual ENET_ATSTMP bitfields + */ + +/*! @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RW) + * + * Timestamp of the last frame transmitted by the core that had TxBD[TS] set . This register is only + * valid when EIR[TS_AVAIL] is set. + */ +//@{ +#define BP_ENET_ATSTMP_TIMESTAMP (0) //!< Bit position for ENET_ATSTMP_TIMESTAMP. +#define BM_ENET_ATSTMP_TIMESTAMP (0xffffffff) //!< Bit mask for ENET_ATSTMP_TIMESTAMP. + +//! @brief Get value of ENET_ATSTMP_TIMESTAMP from a register value. +#define BG_ENET_ATSTMP_TIMESTAMP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ENET_ATSTMP_TIMESTAMP) >> BP_ENET_ATSTMP_TIMESTAMP) +//@} + +//------------------------------------------------------------------------------------------- +// hw_enet_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All ENET module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_enet +{ + reg32_t _reserved0; + volatile hw_enet_eir_t EIR; //!< Interrupt Event Register + volatile hw_enet_eimr_t EIMR; //!< Interrupt Mask Register + reg32_t _reserved1; + volatile hw_enet_rdar_t RDAR; //!< Receive Descriptor Active Register + volatile hw_enet_tdar_t TDAR; //!< Transmit Descriptor Active Register + reg32_t _reserved2[3]; + volatile hw_enet_ecr_t ECR; //!< Ethernet Control Register + reg32_t _reserved3[6]; + volatile hw_enet_mmfr_t MMFR; //!< MII Management Frame Register + volatile hw_enet_mscr_t MSCR; //!< MII Speed Control Register + reg32_t _reserved4[7]; + volatile hw_enet_mibc_t MIBC; //!< MIB Control Register + reg32_t _reserved5[7]; + volatile hw_enet_rcr_t RCR; //!< Receive Control Register + reg32_t _reserved6[15]; + volatile hw_enet_tcr_t TCR; //!< Transmit Control Register + reg32_t _reserved7[7]; + volatile hw_enet_palr_t PALR; //!< Physical Address Lower Register + volatile hw_enet_paur_t PAUR; //!< Physical Address Upper Register + volatile hw_enet_opd_t OPD; //!< Opcode/Pause Duration Register + reg32_t _reserved8[10]; + volatile hw_enet_iaur_t IAUR; //!< Descriptor Individual Upper Address Register + volatile hw_enet_ialr_t IALR; //!< Descriptor Individual Lower Address Register + volatile hw_enet_gaur_t GAUR; //!< Descriptor Group Upper Address Register + volatile hw_enet_galr_t GALR; //!< Descriptor Group Lower Address Register + reg32_t _reserved9[7]; + volatile hw_enet_tfwr_t TFWR; //!< Transmit FIFO Watermark Register + reg32_t _reserved10[14]; + volatile hw_enet_rdsr_t RDSR; //!< Receive Descriptor Ring Start Register + volatile hw_enet_tdsr_t TDSR; //!< Transmit Buffer Descriptor Ring Start Register + volatile hw_enet_mrbr_t MRBR; //!< Maximum Receive Buffer Size Register + reg32_t _reserved11; + volatile hw_enet_rsfl_t RSFL; //!< Receive FIFO Section Full Threshold + volatile hw_enet_rsem_t RSEM; //!< Receive FIFO Section Empty Threshold + volatile hw_enet_raem_t RAEM; //!< Receive FIFO Almost Empty Threshold + volatile hw_enet_rafl_t RAFL; //!< Receive FIFO Almost Full Threshold + volatile hw_enet_tsem_t TSEM; //!< Transmit FIFO Section Empty Threshold + volatile hw_enet_taem_t TAEM; //!< Transmit FIFO Almost Empty Threshold + volatile hw_enet_tafl_t TAFL; //!< Transmit FIFO Almost Full Threshold + volatile hw_enet_tipg_t TIPG; //!< Transmit Inter-Packet Gap + volatile hw_enet_ftrl_t FTRL; //!< Frame Truncation Length + reg32_t _reserved12[3]; + volatile hw_enet_tacc_t TACC; //!< Transmit Accelerator Function Configuration + volatile hw_enet_racc_t RACC; //!< Receive Accelerator Function Configuration + reg32_t _reserved13[142]; + volatile hw_enet_atcr_t ATCR; //!< Timer Control Register + volatile hw_enet_atvr_t ATVR; //!< Timer Value Register + volatile hw_enet_atoff_t ATOFF; //!< Timer Offset Register + volatile hw_enet_atper_t ATPER; //!< Timer Period Register + volatile hw_enet_atcor_t ATCOR; //!< Timer Correction Register + volatile hw_enet_atinc_t ATINC; //!< Time-Stamping Clock Period Register + volatile hw_enet_atstmp_t ATSTMP; //!< Timestamp of Last Transmitted Frame +} hw_enet_t; +#pragma pack() + +//! @brief Macro to access all ENET registers. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_ENET. +#define HW_ENET (*(hw_enet_t *) REGS_ENET_BASE) +#endif + +#endif // __HW_ENET_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsepit.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsepit.h new file mode 100644 index 0000000000000000000000000000000000000000..f058483925c66dacdeb9a756ae5e912d55b39292 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsepit.h @@ -0,0 +1,718 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_EPIT_REGISTERS_H__ +#define __HW_EPIT_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL EPIT + * + * EPIT + * + * Registers defined in this header file: + * - HW_EPIT_CR - Control register + * - HW_EPIT_SR - Status register + * - HW_EPIT_LR - Load register + * - HW_EPIT_CMPR - Compare register + * - HW_EPIT_CNR - Counter register + * + * - hw_epit_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_EPIT_BASE +#define HW_EPIT_INSTANCE_COUNT (2) //!< Number of instances of the EPIT module. +#define HW_EPIT1 (1) //!< Instance number for EPIT1. +#define HW_EPIT2 (2) //!< Instance number for EPIT2. +#define REGS_EPIT1_BASE (0x020d0000) //!< Base address for EPIT instance number 1. +#define REGS_EPIT2_BASE (0x020d4000) //!< Base address for EPIT instance number 2. + +//! @brief Get the base address of EPIT by instance number. +//! @param x EPIT instance number, from 1 through 2. +#define REGS_EPIT_BASE(x) ( (x) == HW_EPIT1 ? REGS_EPIT1_BASE : (x) == HW_EPIT2 ? REGS_EPIT2_BASE : 0x00d00000) + +//! @brief Get the instance number given a base address. +//! @param b Base address for an instance of EPIT. +#define REGS_EPIT_INSTANCE(b) ( (b) == REGS_EPIT1_BASE ? HW_EPIT1 : (b) == REGS_EPIT2_BASE ? HW_EPIT2 : 0) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_EPIT_CR - Control register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_EPIT_CR - Control register (RW) + * + * Reset value: 0x00000000 + * + * The EPIT control register (EPIT_CR) is used to configure the operating settings of the EPIT. It + * contains the clock division prescaler value and also the interrupt enable bit. Additionally, it + * contains other control bits which are described below. Peripheral Bus Write access to EPIT + * Control Register (EPIT_CR) results in one cycle of the wait state, while other valid peripheral + * bus accesses are with 0 wait state. + */ +typedef union _hw_epit_cr +{ + reg32_t U; + struct _hw_epit_cr_bitfields + { + unsigned EN : 1; //!< [0] This bit enables the EPIT. + unsigned ENMOD : 1; //!< [1] EPIT enable mode. + unsigned OCIEN : 1; //!< [2] Output compare interrupt enable. + unsigned RLD : 1; //!< [3] Counter reload control. + unsigned PRESCALAR : 12; //!< [15:4] Counter clock prescaler value. + unsigned SWR : 1; //!< [16] Software reset. + unsigned IOVW : 1; //!< [17] EPIT counter overwrite enable. + unsigned DBGEN : 1; //!< [18] This bit is used to keep the EPIT functional in debug mode. + unsigned WAITEN : 1; //!< [19] This read/write control bit enables the operation of the EPIT during wait mode. + unsigned RESERVED0 : 1; //!< [20] Reserved. + unsigned STOPEN : 1; //!< [21] EPIT stop mode enable. + unsigned OM : 2; //!< [23:22] EPIT output mode.This bit field determines the mode of EPIT output on the output pin. + unsigned CLKSRC : 2; //!< [25:24] Select clock source + unsigned RESERVED1 : 6; //!< [31:26] Reserved. + } B; +} hw_epit_cr_t; +#endif + +/*! + * @name Constants and macros for entire EPIT_CR register + */ +//@{ +#define HW_EPIT_CR_ADDR(x) (REGS_EPIT_BASE(x) + 0x0) + +#ifndef __LANGUAGE_ASM__ +#define HW_EPIT_CR(x) (*(volatile hw_epit_cr_t *) HW_EPIT_CR_ADDR(x)) +#define HW_EPIT_CR_RD(x) (HW_EPIT_CR(x).U) +#define HW_EPIT_CR_WR(x, v) (HW_EPIT_CR(x).U = (v)) +#define HW_EPIT_CR_SET(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) | (v))) +#define HW_EPIT_CR_CLR(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) & ~(v))) +#define HW_EPIT_CR_TOG(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual EPIT_CR bitfields + */ + +/*! @name Register EPIT_CR, field EN[0] (RW) + * + * This bit enables the EPIT. EPIT counter and prescaler value when EPIT is enabled (EN = 1), is + * dependent upon ENMOD and RLD bit as described for ENMOD bit. It is recommended that all registers + * be properly programmed before setting this bit. This bit is reset by a hardware reset. A software + * reset does not affect this bit. + * + * Values: + * - 0 - EPIT is disabled + * - 1 - EPIT is enabled + */ +//@{ +#define BP_EPIT_CR_EN (0) //!< Bit position for EPIT_CR_EN. +#define BM_EPIT_CR_EN (0x00000001) //!< Bit mask for EPIT_CR_EN. + +//! @brief Get value of EPIT_CR_EN from a register value. +#define BG_EPIT_CR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_EN) >> BP_EPIT_CR_EN) + +//! @brief Format value for bitfield EPIT_CR_EN. +#define BF_EPIT_CR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_EN) & BM_EPIT_CR_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN field to a new value. +#define BW_EPIT_CR_EN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_EN) | BF_EPIT_CR_EN(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field ENMOD[1] (RW) + * + * EPIT enable mode. When EPIT is disabled (EN=0), both main counter and prescaler counter freeze + * their count at current count values. ENMOD bit is a r/w bit that determines the counter value + * when the EPIT is enabled again by setting EN bit. If ENMOD bit is set, then main counter is + * loaded with the load value (If RLD=1)/ 0xFFFF_FFFF (If RLD=0) and prescaler counter is reset, + * when EPIT is enabled (EN=1). If ENMOD is programmed to 0 then both main counter and prescaler + * counter restart counting from their frozen values when EPIT is enabled (EN=1). If EPIT is + * programmed to be disabled in a low-power mode (STOP/WAIT/DEBUG), then both the main counter and + * the prescaler counter freeze at their current count values when EPIT enters low-power mode. When + * EPIT exits the low-power mode, both main counter and prescaler counter start counting from their + * frozen values irrespective of the ENMOD bit. This bit is reset by a hardware reset. A software + * reset does not affect this bit. + * + * Values: + * - 0 - Counter starts counting from the value it had when it was disabled. + * - 1 - Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0) + */ +//@{ +#define BP_EPIT_CR_ENMOD (1) //!< Bit position for EPIT_CR_ENMOD. +#define BM_EPIT_CR_ENMOD (0x00000002) //!< Bit mask for EPIT_CR_ENMOD. + +//! @brief Get value of EPIT_CR_ENMOD from a register value. +#define BG_EPIT_CR_ENMOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_ENMOD) >> BP_EPIT_CR_ENMOD) + +//! @brief Format value for bitfield EPIT_CR_ENMOD. +#define BF_EPIT_CR_ENMOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_ENMOD) & BM_EPIT_CR_ENMOD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENMOD field to a new value. +#define BW_EPIT_CR_ENMOD(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_ENMOD) | BF_EPIT_CR_ENMOD(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field OCIEN[2] (RW) + * + * Output compare interrupt enable. This bit enables the generation of interrupt on occurrence of + * compare event. + * + * Values: + * - 0 - Compare interrupt disabled + * - 1 - Compare interrupt enabled + */ +//@{ +#define BP_EPIT_CR_OCIEN (2) //!< Bit position for EPIT_CR_OCIEN. +#define BM_EPIT_CR_OCIEN (0x00000004) //!< Bit mask for EPIT_CR_OCIEN. + +//! @brief Get value of EPIT_CR_OCIEN from a register value. +#define BG_EPIT_CR_OCIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_OCIEN) >> BP_EPIT_CR_OCIEN) + +//! @brief Format value for bitfield EPIT_CR_OCIEN. +#define BF_EPIT_CR_OCIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_OCIEN) & BM_EPIT_CR_OCIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OCIEN field to a new value. +#define BW_EPIT_CR_OCIEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_OCIEN) | BF_EPIT_CR_OCIEN(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field RLD[3] (RW) + * + * Counter reload control. This bit is cleared by hardware reset. It decides the counter + * functionality, whether to run in free-running mode or set-and-forget mode. + * + * Values: + * - 0 - When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode) + * - 1 - When the counter reaches zero it reloads from the modulus register (set-and-forget mode) + */ +//@{ +#define BP_EPIT_CR_RLD (3) //!< Bit position for EPIT_CR_RLD. +#define BM_EPIT_CR_RLD (0x00000008) //!< Bit mask for EPIT_CR_RLD. + +//! @brief Get value of EPIT_CR_RLD from a register value. +#define BG_EPIT_CR_RLD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_RLD) >> BP_EPIT_CR_RLD) + +//! @brief Format value for bitfield EPIT_CR_RLD. +#define BF_EPIT_CR_RLD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_RLD) & BM_EPIT_CR_RLD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RLD field to a new value. +#define BW_EPIT_CR_RLD(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_RLD) | BF_EPIT_CR_RLD(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field PRESCALAR[15:4] (RW) + * + * Counter clock prescaler value. This bit field determines the prescaler value by which the clock + * is divided before it goes to the counter + * + * Values: + * - 0x000 - Divide by 1 + * - 0x001 - Divide by 2... + * - 0xFFF - Divide by 4096 + */ +//@{ +#define BP_EPIT_CR_PRESCALAR (4) //!< Bit position for EPIT_CR_PRESCALAR. +#define BM_EPIT_CR_PRESCALAR (0x0000fff0) //!< Bit mask for EPIT_CR_PRESCALAR. + +//! @brief Get value of EPIT_CR_PRESCALAR from a register value. +#define BG_EPIT_CR_PRESCALAR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_PRESCALAR) >> BP_EPIT_CR_PRESCALAR) + +//! @brief Format value for bitfield EPIT_CR_PRESCALAR. +#define BF_EPIT_CR_PRESCALAR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_PRESCALAR) & BM_EPIT_CR_PRESCALAR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PRESCALAR field to a new value. +#define BW_EPIT_CR_PRESCALAR(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_PRESCALAR) | BF_EPIT_CR_PRESCALAR(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field SWR[16] (RW) + * + * Software reset. The EPIT is reset when this bit is set to 1. It is a self clearing bit. This bit + * is set when the block is in reset state and is cleared when the reset procedure is over. Setting + * this bit resets all the registers to their reset values, except for the EN, ENMOD, STOPEN, WAITEN + * and DBGEN bits in this control register + * + * Values: + * - 0 - EPIT is out of reset + * - 1 - EPIT is undergoing reset + */ +//@{ +#define BP_EPIT_CR_SWR (16) //!< Bit position for EPIT_CR_SWR. +#define BM_EPIT_CR_SWR (0x00010000) //!< Bit mask for EPIT_CR_SWR. + +//! @brief Get value of EPIT_CR_SWR from a register value. +#define BG_EPIT_CR_SWR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_SWR) >> BP_EPIT_CR_SWR) + +//! @brief Format value for bitfield EPIT_CR_SWR. +#define BF_EPIT_CR_SWR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_SWR) & BM_EPIT_CR_SWR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SWR field to a new value. +#define BW_EPIT_CR_SWR(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_SWR) | BF_EPIT_CR_SWR(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field IOVW[17] (RW) + * + * EPIT counter overwrite enable. This bit controls the counter data when the modulus register is + * written. When this bit is set, all writes to the load register overwrites the counter contents + * and the counter starts subsequently counting down from the programmed value. + * + * Values: + * - 0 - Write to load register does not result in counter value being overwritten. + * - 1 - Write to load register results in immediate overwriting of counter value. + */ +//@{ +#define BP_EPIT_CR_IOVW (17) //!< Bit position for EPIT_CR_IOVW. +#define BM_EPIT_CR_IOVW (0x00020000) //!< Bit mask for EPIT_CR_IOVW. + +//! @brief Get value of EPIT_CR_IOVW from a register value. +#define BG_EPIT_CR_IOVW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_IOVW) >> BP_EPIT_CR_IOVW) + +//! @brief Format value for bitfield EPIT_CR_IOVW. +#define BF_EPIT_CR_IOVW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_IOVW) & BM_EPIT_CR_IOVW) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IOVW field to a new value. +#define BW_EPIT_CR_IOVW(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_IOVW) | BF_EPIT_CR_IOVW(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field DBGEN[18] (RW) + * + * This bit is used to keep the EPIT functional in debug mode. When this bit is cleared, the input + * clock is gated off in debug mode.This bit is reset by hardware reset. A software reset does not + * affect this bit. + * + * Values: + * - 0 - Inactive in debug mode + * - 1 - Active in debug mode + */ +//@{ +#define BP_EPIT_CR_DBGEN (18) //!< Bit position for EPIT_CR_DBGEN. +#define BM_EPIT_CR_DBGEN (0x00040000) //!< Bit mask for EPIT_CR_DBGEN. + +//! @brief Get value of EPIT_CR_DBGEN from a register value. +#define BG_EPIT_CR_DBGEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_DBGEN) >> BP_EPIT_CR_DBGEN) + +//! @brief Format value for bitfield EPIT_CR_DBGEN. +#define BF_EPIT_CR_DBGEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_DBGEN) & BM_EPIT_CR_DBGEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DBGEN field to a new value. +#define BW_EPIT_CR_DBGEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_DBGEN) | BF_EPIT_CR_DBGEN(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field WAITEN[19] (RW) + * + * This read/write control bit enables the operation of the EPIT during wait mode. This bit is reset + * by a hardware reset. A software reset does not affect this bit. + * + * Values: + * - 0 - EPIT is disabled in wait mode + * - 1 - EPIT is enabled in wait mode + */ +//@{ +#define BP_EPIT_CR_WAITEN (19) //!< Bit position for EPIT_CR_WAITEN. +#define BM_EPIT_CR_WAITEN (0x00080000) //!< Bit mask for EPIT_CR_WAITEN. + +//! @brief Get value of EPIT_CR_WAITEN from a register value. +#define BG_EPIT_CR_WAITEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_WAITEN) >> BP_EPIT_CR_WAITEN) + +//! @brief Format value for bitfield EPIT_CR_WAITEN. +#define BF_EPIT_CR_WAITEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_WAITEN) & BM_EPIT_CR_WAITEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WAITEN field to a new value. +#define BW_EPIT_CR_WAITEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_WAITEN) | BF_EPIT_CR_WAITEN(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field STOPEN[21] (RW) + * + * EPIT stop mode enable. This read/write control bit enables the operation of the EPIT during stop + * mode. This bit is reset by a hardware reset and unaffected by software reset. + * + * Values: + * - 0 - EPIT is disabled in stop mode + * - 1 - EPIT is enabled in stop mode + */ +//@{ +#define BP_EPIT_CR_STOPEN (21) //!< Bit position for EPIT_CR_STOPEN. +#define BM_EPIT_CR_STOPEN (0x00200000) //!< Bit mask for EPIT_CR_STOPEN. + +//! @brief Get value of EPIT_CR_STOPEN from a register value. +#define BG_EPIT_CR_STOPEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_STOPEN) >> BP_EPIT_CR_STOPEN) + +//! @brief Format value for bitfield EPIT_CR_STOPEN. +#define BF_EPIT_CR_STOPEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_STOPEN) & BM_EPIT_CR_STOPEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STOPEN field to a new value. +#define BW_EPIT_CR_STOPEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_STOPEN) | BF_EPIT_CR_STOPEN(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field OM[23:22] (RW) + * + * EPIT output mode.This bit field determines the mode of EPIT output on the output pin. + * + * Values: + * - 00 - EPIT output is disconnected from pad + * - 01 - Toggle output pin + * - 10 - Clear output pin + * - 11 - Set output pin + */ +//@{ +#define BP_EPIT_CR_OM (22) //!< Bit position for EPIT_CR_OM. +#define BM_EPIT_CR_OM (0x00c00000) //!< Bit mask for EPIT_CR_OM. + +//! @brief Get value of EPIT_CR_OM from a register value. +#define BG_EPIT_CR_OM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_OM) >> BP_EPIT_CR_OM) + +//! @brief Format value for bitfield EPIT_CR_OM. +#define BF_EPIT_CR_OM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_OM) & BM_EPIT_CR_OM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OM field to a new value. +#define BW_EPIT_CR_OM(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_OM) | BF_EPIT_CR_OM(v))) +#endif +//@} + +/*! @name Register EPIT_CR, field CLKSRC[25:24] (RW) + * + * Select clock source These bits determine which clock input is to be selected for running the + * counter. This field value should only be changed when the EPIT is disabled by clearing the EN bit + * in this register. For other programming requirements while changing clock source, refer to . + * + * Values: + * - 00 - Clock is off + * - 01 - Peripheral clock + * - 10 - High-frequency reference clock + * - 11 - Low-frequency reference clock + */ +//@{ +#define BP_EPIT_CR_CLKSRC (24) //!< Bit position for EPIT_CR_CLKSRC. +#define BM_EPIT_CR_CLKSRC (0x03000000) //!< Bit mask for EPIT_CR_CLKSRC. + +//! @brief Get value of EPIT_CR_CLKSRC from a register value. +#define BG_EPIT_CR_CLKSRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_CLKSRC) >> BP_EPIT_CR_CLKSRC) + +//! @brief Format value for bitfield EPIT_CR_CLKSRC. +#define BF_EPIT_CR_CLKSRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_CLKSRC) & BM_EPIT_CR_CLKSRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKSRC field to a new value. +#define BW_EPIT_CR_CLKSRC(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_CLKSRC) | BF_EPIT_CR_CLKSRC(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_EPIT_SR - Status register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_EPIT_SR - Status register (RW) + * + * Reset value: 0x00000000 + * + * The EPIT status register (EPIT_SR) has a single status bit for the output compare event. The bit + * is a write 1 to clear bit. + */ +typedef union _hw_epit_sr +{ + reg32_t U; + struct _hw_epit_sr_bitfields + { + unsigned OCIF : 1; //!< [0] Output compare interrupt flag. + unsigned RESERVED0 : 31; //!< [31:1] Reserved. + } B; +} hw_epit_sr_t; +#endif + +/*! + * @name Constants and macros for entire EPIT_SR register + */ +//@{ +#define HW_EPIT_SR_ADDR(x) (REGS_EPIT_BASE(x) + 0x4) + +#ifndef __LANGUAGE_ASM__ +#define HW_EPIT_SR(x) (*(volatile hw_epit_sr_t *) HW_EPIT_SR_ADDR(x)) +#define HW_EPIT_SR_RD(x) (HW_EPIT_SR(x).U) +#define HW_EPIT_SR_WR(x, v) (HW_EPIT_SR(x).U = (v)) +#define HW_EPIT_SR_SET(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) | (v))) +#define HW_EPIT_SR_CLR(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) & ~(v))) +#define HW_EPIT_SR_TOG(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual EPIT_SR bitfields + */ + +/*! @name Register EPIT_SR, field OCIF[0] (W1C) + * + * Output compare interrupt flag. This bit is the interrupt flag that is set when the content of + * counter equals the content of the compare register (EPIT_CMPR). The bit is a write 1 to clear + * bit. + * + * Values: + * - 0 - Compare event has not occurred + * - 1 - Compare event occurred + */ +//@{ +#define BP_EPIT_SR_OCIF (0) //!< Bit position for EPIT_SR_OCIF. +#define BM_EPIT_SR_OCIF (0x00000001) //!< Bit mask for EPIT_SR_OCIF. + +//! @brief Get value of EPIT_SR_OCIF from a register value. +#define BG_EPIT_SR_OCIF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_SR_OCIF) >> BP_EPIT_SR_OCIF) + +//! @brief Format value for bitfield EPIT_SR_OCIF. +#define BF_EPIT_SR_OCIF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_SR_OCIF) & BM_EPIT_SR_OCIF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OCIF field to a new value. +#define BW_EPIT_SR_OCIF(x, v) (HW_EPIT_SR_WR(x, (HW_EPIT_SR_RD(x) & ~BM_EPIT_SR_OCIF) | BF_EPIT_SR_OCIF(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_EPIT_LR - Load register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_EPIT_LR - Load register (RW) + * + * Reset value: 0xffffffff + * + * The EPIT load register (EPIT_LR) contains the value that is to be loaded into the counter when + * EPIT counter reaches zero if the RLD bit in EPIT_CR is set. If the IOVW bit in the EPIT_CR is set + * then a write to this register overwrites the value of the EPIT counter register in addition to + * updating this registers value. This overwrite feature is active even if the RLD bit is not set. + */ +typedef union _hw_epit_lr +{ + reg32_t U; + struct _hw_epit_lr_bitfields + { + unsigned LOAD : 32; //!< [31:0] Load value. + } B; +} hw_epit_lr_t; +#endif + +/*! + * @name Constants and macros for entire EPIT_LR register + */ +//@{ +#define HW_EPIT_LR_ADDR(x) (REGS_EPIT_BASE(x) + 0x8) + +#ifndef __LANGUAGE_ASM__ +#define HW_EPIT_LR(x) (*(volatile hw_epit_lr_t *) HW_EPIT_LR_ADDR(x)) +#define HW_EPIT_LR_RD(x) (HW_EPIT_LR(x).U) +#define HW_EPIT_LR_WR(x, v) (HW_EPIT_LR(x).U = (v)) +#define HW_EPIT_LR_SET(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) | (v))) +#define HW_EPIT_LR_CLR(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) & ~(v))) +#define HW_EPIT_LR_TOG(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual EPIT_LR bitfields + */ + +/*! @name Register EPIT_LR, field LOAD[31:0] (RW) + * + * Load value. Value that is loaded into the counter at the start of each count cycle. + */ +//@{ +#define BP_EPIT_LR_LOAD (0) //!< Bit position for EPIT_LR_LOAD. +#define BM_EPIT_LR_LOAD (0xffffffff) //!< Bit mask for EPIT_LR_LOAD. + +//! @brief Get value of EPIT_LR_LOAD from a register value. +#define BG_EPIT_LR_LOAD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_LR_LOAD) >> BP_EPIT_LR_LOAD) + +//! @brief Format value for bitfield EPIT_LR_LOAD. +#define BF_EPIT_LR_LOAD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_LR_LOAD) & BM_EPIT_LR_LOAD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LOAD field to a new value. +#define BW_EPIT_LR_LOAD(x, v) (HW_EPIT_LR_WR(x, (HW_EPIT_LR_RD(x) & ~BM_EPIT_LR_LOAD) | BF_EPIT_LR_LOAD(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_EPIT_CMPR - Compare register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_EPIT_CMPR - Compare register (RW) + * + * Reset value: 0x00000000 + * + * The EPIT compare register (EPIT_CMPR) holds the value that determines when a compare event is + * generated. + */ +typedef union _hw_epit_cmpr +{ + reg32_t U; + struct _hw_epit_cmpr_bitfields + { + unsigned COMPARE : 32; //!< [31:0] Compare Value. + } B; +} hw_epit_cmpr_t; +#endif + +/*! + * @name Constants and macros for entire EPIT_CMPR register + */ +//@{ +#define HW_EPIT_CMPR_ADDR(x) (REGS_EPIT_BASE(x) + 0xc) + +#ifndef __LANGUAGE_ASM__ +#define HW_EPIT_CMPR(x) (*(volatile hw_epit_cmpr_t *) HW_EPIT_CMPR_ADDR(x)) +#define HW_EPIT_CMPR_RD(x) (HW_EPIT_CMPR(x).U) +#define HW_EPIT_CMPR_WR(x, v) (HW_EPIT_CMPR(x).U = (v)) +#define HW_EPIT_CMPR_SET(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) | (v))) +#define HW_EPIT_CMPR_CLR(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) & ~(v))) +#define HW_EPIT_CMPR_TOG(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual EPIT_CMPR bitfields + */ + +/*! @name Register EPIT_CMPR, field COMPARE[31:0] (RW) + * + * Compare Value. When the counter value equals this bit field value a compare event is generated. + */ +//@{ +#define BP_EPIT_CMPR_COMPARE (0) //!< Bit position for EPIT_CMPR_COMPARE. +#define BM_EPIT_CMPR_COMPARE (0xffffffff) //!< Bit mask for EPIT_CMPR_COMPARE. + +//! @brief Get value of EPIT_CMPR_COMPARE from a register value. +#define BG_EPIT_CMPR_COMPARE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CMPR_COMPARE) >> BP_EPIT_CMPR_COMPARE) + +//! @brief Format value for bitfield EPIT_CMPR_COMPARE. +#define BF_EPIT_CMPR_COMPARE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CMPR_COMPARE) & BM_EPIT_CMPR_COMPARE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the COMPARE field to a new value. +#define BW_EPIT_CMPR_COMPARE(x, v) (HW_EPIT_CMPR_WR(x, (HW_EPIT_CMPR_RD(x) & ~BM_EPIT_CMPR_COMPARE) | BF_EPIT_CMPR_COMPARE(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_EPIT_CNR - Counter register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_EPIT_CNR - Counter register (RO) + * + * Reset value: 0xffffffff + * + * The EPIT counter register (EPIT_CNR) contains the current count value and can be read at any time + * without disturbing the counter. This is a read-only register and any attempt to write into it + * generates a transfer error. But if the IOVW bit in EPIT_CR is set, the value of this register can + * be overwritten with a write to EPIT_LR. This change is reflected when this register is + * subsequently read. + */ +typedef union _hw_epit_cnr +{ + reg32_t U; + struct _hw_epit_cnr_bitfields + { + unsigned COUNT : 32; //!< [31:0] Counter value. + } B; +} hw_epit_cnr_t; +#endif + +/*! + * @name Constants and macros for entire EPIT_CNR register + */ +//@{ +#define HW_EPIT_CNR_ADDR(x) (REGS_EPIT_BASE(x) + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_EPIT_CNR(x) (*(volatile hw_epit_cnr_t *) HW_EPIT_CNR_ADDR(x)) +#define HW_EPIT_CNR_RD(x) (HW_EPIT_CNR(x).U) +#endif +//@} + +/* + * constants & macros for individual EPIT_CNR bitfields + */ + +/*! @name Register EPIT_CNR, field COUNT[31:0] (RO) + * + * Counter value. This contains the current value of the counter. + */ +//@{ +#define BP_EPIT_CNR_COUNT (0) //!< Bit position for EPIT_CNR_COUNT. +#define BM_EPIT_CNR_COUNT (0xffffffff) //!< Bit mask for EPIT_CNR_COUNT. + +//! @brief Get value of EPIT_CNR_COUNT from a register value. +#define BG_EPIT_CNR_COUNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CNR_COUNT) >> BP_EPIT_CNR_COUNT) +//@} + +//------------------------------------------------------------------------------------------- +// hw_epit_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All EPIT module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_epit +{ + volatile hw_epit_cr_t CR; //!< Control register + volatile hw_epit_sr_t SR; //!< Status register + volatile hw_epit_lr_t LR; //!< Load register + volatile hw_epit_cmpr_t CMPR; //!< Compare register + volatile hw_epit_cnr_t CNR; //!< Counter register +} hw_epit_t; +#pragma pack() + +//! @brief Macro to access all EPIT registers. +//! @param x EPIT instance number. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_EPIT(0). +#define HW_EPIT(x) (*(hw_epit_t *) REGS_EPIT_BASE(x)) +#endif + +#endif // __HW_EPIT_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsgpmi.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsgpmi.h new file mode 100644 index 0000000000000000000000000000000000000000..35d73eb8cc253866256e81dd66d4623084633e62 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsgpmi.h @@ -0,0 +1,2173 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ + +#ifndef _GPMI_H +#define _GPMI_H 1 + +#include "regs.h" +//#include "registers.h" + +#ifndef REGS_GPMI_BASE +#define REGS_GPMI_BASE (REGS_BASE + 0x112000) +#endif + +/* + * HW_GPMI_CTRL0 - GPMI Control Register 0 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned XFER_COUNT:16; + unsigned ADDRESS_INCREMENT:1; + unsigned ADDRESS:3; + unsigned CS:3; + unsigned WORD_LENGTH:1; + unsigned COMMAND_MODE:2; + unsigned UDMA:1; + unsigned LOCK_CS:1; + unsigned DEV_IRQ_EN:1; + unsigned RUN:1; + unsigned CLKGATE:1; + unsigned SFTRST:1; + } B; +} hw_gpmi_ctrl0_t; +#endif + +/* + * constants & macros for entire HW_GPMI_CTRL0 register + */ +#define HW_GPMI_CTRL0_ADDR (0x00112000) +#define HW_GPMI_CTRL0_SET_ADDR (0x00112004) +#define HW_GPMI_CTRL0_CLR_ADDR (0x00112008) +#define HW_GPMI_CTRL0_TOG_ADDR (0x0011200c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_CTRL0 (*(volatile hw_gpmi_ctrl0_t *) HW_GPMI_CTRL0_ADDR) +#define HW_GPMI_CTRL0_RD() (HW_GPMI_CTRL0.U) +#define HW_GPMI_CTRL0_WR(v) (HW_GPMI_CTRL0.U = (v)) +#define HW_GPMI_CTRL0_SET(v) ((*(volatile reg32_t *) HW_GPMI_CTRL0_SET_ADDR) = (v)) +#define HW_GPMI_CTRL0_CLR(v) ((*(volatile reg32_t *) HW_GPMI_CTRL0_CLR_ADDR) = (v)) +#define HW_GPMI_CTRL0_TOG(v) ((*(volatile reg32_t *) HW_GPMI_CTRL0_TOG_ADDR) = (v)) +#else +#define HW_GPMI_CTRL0_RD() (_rbase->mem32_read(HW_GPMI_CTRL0_ADDR)) +#define HW_GPMI_CTRL0_WR(v) (_rbase->mem32_write(HW_GPMI_CTRL0_ADDR,(v))) +#define HW_GPMI_CTRL0_SET(v) (_rbase->mem32_write(HW_GPMI_CTRL0_SET_ADDR,(v))) +#define HW_GPMI_CTRL0_CLR(v) (_rbase->mem32_write(HW_GPMI_CTRL0_CLR_ADDR,(v))) +#define HW_GPMI_CTRL0_TOG(v) (_rbase->mem32_write(HW_GPMI_CTRL0_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_CTRL0 bitfields + */ +/* --- Register HW_GPMI_CTRL0, field SFTRST */ + +#define BP_GPMI_CTRL0_SFTRST 31 +#define BM_GPMI_CTRL0_SFTRST 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_CTRL0_SFTRST(v) ((((reg32_t) v) << 31) & BM_GPMI_CTRL0_SFTRST) +#else +#define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & BM_GPMI_CTRL0_SFTRST) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_SFTRST(v) BF_CS1(GPMI_CTRL0, SFTRST, v) +#endif + +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 + +/* --- Register HW_GPMI_CTRL0, field CLKGATE */ + +#define BP_GPMI_CTRL0_CLKGATE 30 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 + +#define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & BM_GPMI_CTRL0_CLKGATE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_CLKGATE(v) BF_CS1(GPMI_CTRL0, CLKGATE, v) +#endif + +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 + +/* --- Register HW_GPMI_CTRL0, field RUN */ + +#define BP_GPMI_CTRL0_RUN 29 +#define BM_GPMI_CTRL0_RUN 0x20000000 + +#define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & BM_GPMI_CTRL0_RUN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_RUN(v) BF_CS1(GPMI_CTRL0, RUN, v) +#endif + +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 + +/* --- Register HW_GPMI_CTRL0, field DEV_IRQ_EN */ + +#define BP_GPMI_CTRL0_DEV_IRQ_EN 28 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 + +#define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & BM_GPMI_CTRL0_DEV_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_DEV_IRQ_EN(v) BF_CS1(GPMI_CTRL0, DEV_IRQ_EN, v) +#endif + +/* --- Register HW_GPMI_CTRL0, field LOCK_CS */ + +#define BP_GPMI_CTRL0_LOCK_CS 27 +#define BM_GPMI_CTRL0_LOCK_CS 0x08000000 + +#define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 27) & BM_GPMI_CTRL0_LOCK_CS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_LOCK_CS(v) BF_CS1(GPMI_CTRL0, LOCK_CS, v) +#endif + +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 + +/* --- Register HW_GPMI_CTRL0, field UDMA */ + +#define BP_GPMI_CTRL0_UDMA 26 +#define BM_GPMI_CTRL0_UDMA 0x04000000 + +#define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & BM_GPMI_CTRL0_UDMA) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_UDMA(v) BF_CS1(GPMI_CTRL0, UDMA, v) +#endif + +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 + +/* --- Register HW_GPMI_CTRL0, field COMMAND_MODE */ + +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 + +#define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_COMMAND_MODE(v) BF_CS1(GPMI_CTRL0, COMMAND_MODE, v) +#endif + +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 + +/* --- Register HW_GPMI_CTRL0, field WORD_LENGTH */ + +#define BP_GPMI_CTRL0_WORD_LENGTH 23 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 + +#define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & BM_GPMI_CTRL0_WORD_LENGTH) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_WORD_LENGTH(v) BF_CS1(GPMI_CTRL0, WORD_LENGTH, v) +#endif + +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 + +/* --- Register HW_GPMI_CTRL0, field CS */ + +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00700000 + +#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & BM_GPMI_CTRL0_CS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_CS(v) BF_CS1(GPMI_CTRL0, CS, v) +#endif + +/* --- Register HW_GPMI_CTRL0, field ADDRESS */ + +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 + +#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_ADDRESS(v) BF_CS1(GPMI_CTRL0, ADDRESS, v) +#endif + +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 + +/* --- Register HW_GPMI_CTRL0, field ADDRESS_INCREMENT */ + +#define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 + +#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & BM_GPMI_CTRL0_ADDRESS_INCREMENT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_ADDRESS_INCREMENT(v) BF_CS1(GPMI_CTRL0, ADDRESS_INCREMENT, v) +#endif + +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 + +/* --- Register HW_GPMI_CTRL0, field XFER_COUNT */ + +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF + +#define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_XFER_COUNT(v) (HW_GPMI_CTRL0.B.XFER_COUNT = (v)) +#endif + +/* + * HW_GPMI_COMPARE - GPMI Compare Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned REFERENCE:16; + unsigned MASK:16; + } B; +} hw_gpmi_compare_t; +#endif + +/* + * constants & macros for entire HW_GPMI_COMPARE register + */ +#define HW_GPMI_COMPARE_ADDR (0x00112010) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_COMPARE (*(volatile hw_gpmi_compare_t *) HW_GPMI_COMPARE_ADDR) +#define HW_GPMI_COMPARE_RD() (HW_GPMI_COMPARE.U) +#define HW_GPMI_COMPARE_WR(v) (HW_GPMI_COMPARE.U = (v)) +#define HW_GPMI_COMPARE_SET(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() | (v))) +#define HW_GPMI_COMPARE_CLR(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() & ~(v))) +#define HW_GPMI_COMPARE_TOG(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() ^ (v))) +#else +#define HW_GPMI_COMPARE_RD() (_rbase->mem32_read(HW_GPMI_COMPARE_ADDR)) +#define HW_GPMI_COMPARE_WR(v) (_rbase->mem32_write(HW_GPMI_COMPARE_ADDR,(v))) +#define HW_GPMI_COMPARE_SET(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() | (v))) +#define HW_GPMI_COMPARE_CLR(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() & ~(v))) +#define HW_GPMI_COMPARE_TOG(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_COMPARE bitfields + */ +/* --- Register HW_GPMI_COMPARE, field MASK */ + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_COMPARE_MASK(v) ((((reg32_t) v) << 16) & BM_GPMI_COMPARE_MASK) +#else +#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_COMPARE_MASK(v) (HW_GPMI_COMPARE.B.MASK = (v)) +#endif + +/* --- Register HW_GPMI_COMPARE, field REFERENCE */ + +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF + +#define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_COMPARE_REFERENCE(v) (HW_GPMI_COMPARE.B.REFERENCE = (v)) +#endif + +/* + * HW_GPMI_ECCCTRL - GPMI Integrated ECC Control Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned BUFFER_MASK:9; + unsigned RSVD1:3; + unsigned ENABLE_ECC:1; + unsigned ECC_CMD:2; + unsigned RSVD2:1; + unsigned HANDLE:16; + } B; +} hw_gpmi_eccctrl_t; +#endif + +/* + * constants & macros for entire HW_GPMI_ECCCTRL register + */ +#define HW_GPMI_ECCCTRL_ADDR (0x00112020) +#define HW_GPMI_ECCCTRL_SET_ADDR (0x00112024) +#define HW_GPMI_ECCCTRL_CLR_ADDR (0x00112028) +#define HW_GPMI_ECCCTRL_TOG_ADDR (0x0011202c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_ECCCTRL (*(volatile hw_gpmi_eccctrl_t *) HW_GPMI_ECCCTRL_ADDR) +#define HW_GPMI_ECCCTRL_RD() (HW_GPMI_ECCCTRL.U) +#define HW_GPMI_ECCCTRL_WR(v) (HW_GPMI_ECCCTRL.U = (v)) +#define HW_GPMI_ECCCTRL_SET(v) ((*(volatile reg32_t *) HW_GPMI_ECCCTRL_SET_ADDR) = (v)) +#define HW_GPMI_ECCCTRL_CLR(v) ((*(volatile reg32_t *) HW_GPMI_ECCCTRL_CLR_ADDR) = (v)) +#define HW_GPMI_ECCCTRL_TOG(v) ((*(volatile reg32_t *) HW_GPMI_ECCCTRL_TOG_ADDR) = (v)) +#else +#define HW_GPMI_ECCCTRL_RD() (_rbase->mem32_read(HW_GPMI_ECCCTRL_ADDR)) +#define HW_GPMI_ECCCTRL_WR(v) (_rbase->mem32_write(HW_GPMI_ECCCTRL_ADDR,(v))) +#define HW_GPMI_ECCCTRL_SET(v) (_rbase->mem32_write(HW_GPMI_ECCCTRL_SET_ADDR,(v))) +#define HW_GPMI_ECCCTRL_CLR(v) (_rbase->mem32_write(HW_GPMI_ECCCTRL_CLR_ADDR,(v))) +#define HW_GPMI_ECCCTRL_TOG(v) (_rbase->mem32_write(HW_GPMI_ECCCTRL_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_ECCCTRL bitfields + */ +/* --- Register HW_GPMI_ECCCTRL, field HANDLE */ + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_ECCCTRL_HANDLE(v) ((((reg32_t) v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#else +#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCTRL_HANDLE(v) (HW_GPMI_ECCCTRL.B.HANDLE = (v)) +#endif + +/* --- Register HW_GPMI_ECCCTRL, field RSVD2 */ + +#define BP_GPMI_ECCCTRL_RSVD2 15 +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 + +#define BF_GPMI_ECCCTRL_RSVD2(v) (((v) << 15) & BM_GPMI_ECCCTRL_RSVD2) +/* --- Register HW_GPMI_ECCCTRL, field ECC_CMD */ + +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 + +#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCTRL_ECC_CMD(v) BF_CS1(GPMI_ECCCTRL, ECC_CMD, v) +#endif + +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3 + +/* --- Register HW_GPMI_ECCCTRL, field ENABLE_ECC */ + +#define BP_GPMI_ECCCTRL_ENABLE_ECC 12 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 + +#define BF_GPMI_ECCCTRL_ENABLE_ECC(v) (((v) << 12) & BM_GPMI_ECCCTRL_ENABLE_ECC) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCTRL_ENABLE_ECC(v) BF_CS1(GPMI_ECCCTRL, ENABLE_ECC, v) +#endif + +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 + +/* --- Register HW_GPMI_ECCCTRL, field RSVD1 */ + +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 + +#define BF_GPMI_ECCCTRL_RSVD1(v) (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +/* --- Register HW_GPMI_ECCCTRL, field BUFFER_MASK */ + +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF + +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCTRL_BUFFER_MASK(v) BF_CS1(GPMI_ECCCTRL, BUFFER_MASK, v) +#endif + +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF + +/* + * HW_GPMI_ECCCOUNT - GPMI Integrated ECC Transfer Count Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned COUNT:16; + unsigned RSVD2:16; + } B; +} hw_gpmi_ecccount_t; +#endif + +/* + * constants & macros for entire HW_GPMI_ECCCOUNT register + */ +#define HW_GPMI_ECCCOUNT_ADDR (0x00112030) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_ECCCOUNT (*(volatile hw_gpmi_ecccount_t *) HW_GPMI_ECCCOUNT_ADDR) +#define HW_GPMI_ECCCOUNT_RD() (HW_GPMI_ECCCOUNT.U) +#define HW_GPMI_ECCCOUNT_WR(v) (HW_GPMI_ECCCOUNT.U = (v)) +#define HW_GPMI_ECCCOUNT_SET(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() | (v))) +#define HW_GPMI_ECCCOUNT_CLR(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() & ~(v))) +#define HW_GPMI_ECCCOUNT_TOG(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() ^ (v))) +#else +#define HW_GPMI_ECCCOUNT_RD() (_rbase->mem32_read(HW_GPMI_ECCCOUNT_ADDR)) +#define HW_GPMI_ECCCOUNT_WR(v) (_rbase->mem32_write(HW_GPMI_ECCCOUNT_ADDR,(v))) +#define HW_GPMI_ECCCOUNT_SET(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() | (v))) +#define HW_GPMI_ECCCOUNT_CLR(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() & ~(v))) +#define HW_GPMI_ECCCOUNT_TOG(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_ECCCOUNT bitfields + */ +/* --- Register HW_GPMI_ECCCOUNT, field RSVD2 */ + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_ECCCOUNT_RSVD2(v) ((((reg32_t) v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#else +#define BF_GPMI_ECCCOUNT_RSVD2(v) (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#endif +/* --- Register HW_GPMI_ECCCOUNT, field COUNT */ + +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF + +#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCOUNT_COUNT(v) (HW_GPMI_ECCCOUNT.B.COUNT = (v)) +#endif + +/* + * HW_GPMI_PAYLOAD - GPMI Payload Address Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RSVD0:2; + unsigned ADDRESS:30; + } B; +} hw_gpmi_payload_t; +#endif + +/* + * constants & macros for entire HW_GPMI_PAYLOAD register + */ +#define HW_GPMI_PAYLOAD_ADDR (0x00112040) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_PAYLOAD (*(volatile hw_gpmi_payload_t *) HW_GPMI_PAYLOAD_ADDR) +#define HW_GPMI_PAYLOAD_RD() (HW_GPMI_PAYLOAD.U) +#define HW_GPMI_PAYLOAD_WR(v) (HW_GPMI_PAYLOAD.U = (v)) +#define HW_GPMI_PAYLOAD_SET(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() | (v))) +#define HW_GPMI_PAYLOAD_CLR(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() & ~(v))) +#define HW_GPMI_PAYLOAD_TOG(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() ^ (v))) +#else +#define HW_GPMI_PAYLOAD_RD() (_rbase->mem32_read(HW_GPMI_PAYLOAD_ADDR)) +#define HW_GPMI_PAYLOAD_WR(v) (_rbase->mem32_write(HW_GPMI_PAYLOAD_ADDR,(v))) +#define HW_GPMI_PAYLOAD_SET(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() | (v))) +#define HW_GPMI_PAYLOAD_CLR(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() & ~(v))) +#define HW_GPMI_PAYLOAD_TOG(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_PAYLOAD bitfields + */ +/* --- Register HW_GPMI_PAYLOAD, field ADDRESS */ + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_PAYLOAD_ADDRESS(v) ((((reg32_t) v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#else +#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_PAYLOAD_ADDRESS(v) BF_CS1(GPMI_PAYLOAD, ADDRESS, v) +#endif + +/* --- Register HW_GPMI_PAYLOAD, field RSVD0 */ + +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 + +#define BF_GPMI_PAYLOAD_RSVD0(v) (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +/* + * HW_GPMI_AUXILIARY - GPMI Auxiliary Address Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RSVD0:2; + unsigned ADDRESS:30; + } B; +} hw_gpmi_auxiliary_t; +#endif + +/* + * constants & macros for entire HW_GPMI_AUXILIARY register + */ +#define HW_GPMI_AUXILIARY_ADDR (0x00112050) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_AUXILIARY (*(volatile hw_gpmi_auxiliary_t *) HW_GPMI_AUXILIARY_ADDR) +#define HW_GPMI_AUXILIARY_RD() (HW_GPMI_AUXILIARY.U) +#define HW_GPMI_AUXILIARY_WR(v) (HW_GPMI_AUXILIARY.U = (v)) +#define HW_GPMI_AUXILIARY_SET(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() | (v))) +#define HW_GPMI_AUXILIARY_CLR(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() & ~(v))) +#define HW_GPMI_AUXILIARY_TOG(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() ^ (v))) +#else +#define HW_GPMI_AUXILIARY_RD() (_rbase->mem32_read(HW_GPMI_AUXILIARY_ADDR)) +#define HW_GPMI_AUXILIARY_WR(v) (_rbase->mem32_write(HW_GPMI_AUXILIARY_ADDR,(v))) +#define HW_GPMI_AUXILIARY_SET(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() | (v))) +#define HW_GPMI_AUXILIARY_CLR(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() & ~(v))) +#define HW_GPMI_AUXILIARY_TOG(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_AUXILIARY bitfields + */ +/* --- Register HW_GPMI_AUXILIARY, field ADDRESS */ + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_AUXILIARY_ADDRESS(v) ((((reg32_t) v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#else +#define BF_GPMI_AUXILIARY_ADDRESS(v) (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_AUXILIARY_ADDRESS(v) BF_CS1(GPMI_AUXILIARY, ADDRESS, v) +#endif + +/* --- Register HW_GPMI_AUXILIARY, field RSVD0 */ + +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 + +#define BF_GPMI_AUXILIARY_RSVD0(v) (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +/* + * HW_GPMI_CTRL1 - GPMI Control Register 1 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned GPMI_MODE:1; + unsigned CAMERA_MODE:1; + unsigned ATA_IRQRDY_POLARITY:1; + unsigned DEV_RESET:1; + unsigned ABORT_WAIT_FOR_READY_CHANNEL:3; + unsigned ABORT_WAIT_REQUEST:1; + unsigned BURST_EN:1; + unsigned TIMEOUT_IRQ:1; + unsigned DEV_IRQ:1; + unsigned DMA2ECC_MODE:1; + unsigned RDN_DELAY:4; + unsigned HALF_PERIOD:1; + unsigned DLL_ENABLE:1; + unsigned BCH_MODE:1; + unsigned GANGED_RDYBUSY:1; + unsigned TIMEOUT_IRQ_EN:1; + unsigned RSVD1:1; + unsigned WRN_DLY_SEL:2; + unsigned DECOUPLE_CS:1; + unsigned SSYNCMODE:1; + unsigned UPDATE_CS:1; + unsigned GPMI_CLK_DIV2_EN:1; + unsigned TOGGLE_MODE:1; + unsigned WRITE_CLK_STOP:1; + unsigned SSYNC_CLK_STOP:1; + unsigned DEV_CLK_STOP:1; + } B; +} hw_gpmi_ctrl1_t; +#endif + +/* + * constants & macros for entire HW_GPMI_CTRL1 register + */ +#define HW_GPMI_CTRL1_ADDR (0x00112060) +#define HW_GPMI_CTRL1_SET_ADDR (0x00112064) +#define HW_GPMI_CTRL1_CLR_ADDR (0x00112068) +#define HW_GPMI_CTRL1_TOG_ADDR (0x0011206c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_CTRL1 (*(volatile hw_gpmi_ctrl1_t *) HW_GPMI_CTRL1_ADDR) +#define HW_GPMI_CTRL1_RD() (HW_GPMI_CTRL1.U) +#define HW_GPMI_CTRL1_WR(v) (HW_GPMI_CTRL1.U = (v)) +#define HW_GPMI_CTRL1_SET(v) ((*(volatile reg32_t *) HW_GPMI_CTRL1_SET_ADDR) = (v)) +#define HW_GPMI_CTRL1_CLR(v) ((*(volatile reg32_t *) HW_GPMI_CTRL1_CLR_ADDR) = (v)) +#define HW_GPMI_CTRL1_TOG(v) ((*(volatile reg32_t *) HW_GPMI_CTRL1_TOG_ADDR) = (v)) +#else +#define HW_GPMI_CTRL1_RD() (_rbase->mem32_read(HW_GPMI_CTRL1_ADDR)) +#define HW_GPMI_CTRL1_WR(v) (_rbase->mem32_write(HW_GPMI_CTRL1_ADDR,(v))) +#define HW_GPMI_CTRL1_SET(v) (_rbase->mem32_write(HW_GPMI_CTRL1_SET_ADDR,(v))) +#define HW_GPMI_CTRL1_CLR(v) (_rbase->mem32_write(HW_GPMI_CTRL1_CLR_ADDR,(v))) +#define HW_GPMI_CTRL1_TOG(v) (_rbase->mem32_write(HW_GPMI_CTRL1_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_CTRL1 bitfields + */ +/* --- Register HW_GPMI_CTRL1, field DEV_CLK_STOP */ + +#define BP_GPMI_CTRL1_DEV_CLK_STOP 31 +#define BM_GPMI_CTRL1_DEV_CLK_STOP 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_CTRL1_DEV_CLK_STOP(v) ((((reg32_t) v) << 31) & BM_GPMI_CTRL1_DEV_CLK_STOP) +#else +#define BF_GPMI_CTRL1_DEV_CLK_STOP(v) (((v) << 31) & BM_GPMI_CTRL1_DEV_CLK_STOP) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DEV_CLK_STOP(v) BF_CS1(GPMI_CTRL1, DEV_CLK_STOP, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field SSYNC_CLK_STOP */ + +#define BP_GPMI_CTRL1_SSYNC_CLK_STOP 30 +#define BM_GPMI_CTRL1_SSYNC_CLK_STOP 0x40000000 + +#define BF_GPMI_CTRL1_SSYNC_CLK_STOP(v) (((v) << 30) & BM_GPMI_CTRL1_SSYNC_CLK_STOP) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_SSYNC_CLK_STOP(v) BF_CS1(GPMI_CTRL1, SSYNC_CLK_STOP, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field WRITE_CLK_STOP */ + +#define BP_GPMI_CTRL1_WRITE_CLK_STOP 29 +#define BM_GPMI_CTRL1_WRITE_CLK_STOP 0x20000000 + +#define BF_GPMI_CTRL1_WRITE_CLK_STOP(v) (((v) << 29) & BM_GPMI_CTRL1_WRITE_CLK_STOP) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_WRITE_CLK_STOP(v) BF_CS1(GPMI_CTRL1, WRITE_CLK_STOP, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field TOGGLE_MODE */ + +#define BP_GPMI_CTRL1_TOGGLE_MODE 28 +#define BM_GPMI_CTRL1_TOGGLE_MODE 0x10000000 + +#define BF_GPMI_CTRL1_TOGGLE_MODE(v) (((v) << 28) & BM_GPMI_CTRL1_TOGGLE_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_TOGGLE_MODE(v) BF_CS1(GPMI_CTRL1, TOGGLE_MODE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field GPMI_CLK_DIV2_EN */ + +#define BP_GPMI_CTRL1_GPMI_CLK_DIV2_EN 27 +#define BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN 0x08000000 + +#define BF_GPMI_CTRL1_GPMI_CLK_DIV2_EN(v) (((v) << 27) & BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_GPMI_CLK_DIV2_EN(v) BF_CS1(GPMI_CTRL1, GPMI_CLK_DIV2_EN, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field UPDATE_CS */ + +#define BP_GPMI_CTRL1_UPDATE_CS 26 +#define BM_GPMI_CTRL1_UPDATE_CS 0x04000000 + +#define BF_GPMI_CTRL1_UPDATE_CS(v) (((v) << 26) & BM_GPMI_CTRL1_UPDATE_CS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_UPDATE_CS(v) BF_CS1(GPMI_CTRL1, UPDATE_CS, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field SSYNCMODE */ + +#define BP_GPMI_CTRL1_SSYNCMODE 25 +#define BM_GPMI_CTRL1_SSYNCMODE 0x02000000 + +#define BF_GPMI_CTRL1_SSYNCMODE(v) (((v) << 25) & BM_GPMI_CTRL1_SSYNCMODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_SSYNCMODE(v) BF_CS1(GPMI_CTRL1, SSYNCMODE, v) +#endif + +#define BV_GPMI_CTRL1_SSYNCMODE__ASYNC 0x0 +#define BV_GPMI_CTRL1_SSYNCMODE__SSYNC 0x1 + +/* --- Register HW_GPMI_CTRL1, field DECOUPLE_CS */ + +#define BP_GPMI_CTRL1_DECOUPLE_CS 24 +#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000 + +#define BF_GPMI_CTRL1_DECOUPLE_CS(v) (((v) << 24) & BM_GPMI_CTRL1_DECOUPLE_CS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DECOUPLE_CS(v) BF_CS1(GPMI_CTRL1, DECOUPLE_CS, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field WRN_DLY_SEL */ + +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 +#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000 + +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) (((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_WRN_DLY_SEL(v) BF_CS1(GPMI_CTRL1, WRN_DLY_SEL, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field RSVD1 */ + +#define BP_GPMI_CTRL1_RSVD1 21 +#define BM_GPMI_CTRL1_RSVD1 0x00200000 + +#define BF_GPMI_CTRL1_RSVD1(v) (((v) << 21) & BM_GPMI_CTRL1_RSVD1) +/* --- Register HW_GPMI_CTRL1, field TIMEOUT_IRQ_EN */ + +#define BP_GPMI_CTRL1_TIMEOUT_IRQ_EN 20 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000 + +#define BF_GPMI_CTRL1_TIMEOUT_IRQ_EN(v) (((v) << 20) & BM_GPMI_CTRL1_TIMEOUT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_TIMEOUT_IRQ_EN(v) BF_CS1(GPMI_CTRL1, TIMEOUT_IRQ_EN, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field GANGED_RDYBUSY */ + +#define BP_GPMI_CTRL1_GANGED_RDYBUSY 19 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 + +#define BF_GPMI_CTRL1_GANGED_RDYBUSY(v) (((v) << 19) & BM_GPMI_CTRL1_GANGED_RDYBUSY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_GANGED_RDYBUSY(v) BF_CS1(GPMI_CTRL1, GANGED_RDYBUSY, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field BCH_MODE */ + +#define BP_GPMI_CTRL1_BCH_MODE 18 +#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 + +#define BF_GPMI_CTRL1_BCH_MODE(v) (((v) << 18) & BM_GPMI_CTRL1_BCH_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_BCH_MODE(v) BF_CS1(GPMI_CTRL1, BCH_MODE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field DLL_ENABLE */ + +#define BP_GPMI_CTRL1_DLL_ENABLE 17 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 + +#define BF_GPMI_CTRL1_DLL_ENABLE(v) (((v) << 17) & BM_GPMI_CTRL1_DLL_ENABLE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DLL_ENABLE(v) BF_CS1(GPMI_CTRL1, DLL_ENABLE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field HALF_PERIOD */ + +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 + +#define BF_GPMI_CTRL1_HALF_PERIOD(v) (((v) << 16) & BM_GPMI_CTRL1_HALF_PERIOD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_HALF_PERIOD(v) BF_CS1(GPMI_CTRL1, HALF_PERIOD, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field RDN_DELAY */ + +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 + +#define BF_GPMI_CTRL1_RDN_DELAY(v) (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_RDN_DELAY(v) BF_CS1(GPMI_CTRL1, RDN_DELAY, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field DMA2ECC_MODE */ + +#define BP_GPMI_CTRL1_DMA2ECC_MODE 11 +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 + +#define BF_GPMI_CTRL1_DMA2ECC_MODE(v) (((v) << 11) & BM_GPMI_CTRL1_DMA2ECC_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DMA2ECC_MODE(v) BF_CS1(GPMI_CTRL1, DMA2ECC_MODE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field DEV_IRQ */ + +#define BP_GPMI_CTRL1_DEV_IRQ 10 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 + +#define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & BM_GPMI_CTRL1_DEV_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DEV_IRQ(v) BF_CS1(GPMI_CTRL1, DEV_IRQ, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field TIMEOUT_IRQ */ + +#define BP_GPMI_CTRL1_TIMEOUT_IRQ 9 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 + +#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & BM_GPMI_CTRL1_TIMEOUT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_TIMEOUT_IRQ(v) BF_CS1(GPMI_CTRL1, TIMEOUT_IRQ, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field BURST_EN */ + +#define BP_GPMI_CTRL1_BURST_EN 8 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 + +#define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & BM_GPMI_CTRL1_BURST_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_BURST_EN(v) BF_CS1(GPMI_CTRL1, BURST_EN, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field ABORT_WAIT_REQUEST */ + +#define BP_GPMI_CTRL1_ABORT_WAIT_REQUEST 7 +#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080 + +#define BF_GPMI_CTRL1_ABORT_WAIT_REQUEST(v) (((v) << 7) & BM_GPMI_CTRL1_ABORT_WAIT_REQUEST) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_ABORT_WAIT_REQUEST(v) BF_CS1(GPMI_CTRL1, ABORT_WAIT_REQUEST, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field ABORT_WAIT_FOR_READY_CHANNEL */ + +#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070 + +#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) BF_CS1(GPMI_CTRL1, ABORT_WAIT_FOR_READY_CHANNEL, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field DEV_RESET */ + +#define BP_GPMI_CTRL1_DEV_RESET 3 +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 + +#define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & BM_GPMI_CTRL1_DEV_RESET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DEV_RESET(v) BF_CS1(GPMI_CTRL1, DEV_RESET, v) +#endif + +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 + +/* --- Register HW_GPMI_CTRL1, field ATA_IRQRDY_POLARITY */ + +#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 + +#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) BF_CS1(GPMI_CTRL1, ATA_IRQRDY_POLARITY, v) +#endif + +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 + +/* --- Register HW_GPMI_CTRL1, field CAMERA_MODE */ + +#define BP_GPMI_CTRL1_CAMERA_MODE 1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 + +#define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & BM_GPMI_CTRL1_CAMERA_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_CAMERA_MODE(v) BF_CS1(GPMI_CTRL1, CAMERA_MODE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field GPMI_MODE */ + +#define BP_GPMI_CTRL1_GPMI_MODE 0 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 + +#define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & BM_GPMI_CTRL1_GPMI_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_GPMI_MODE(v) BF_CS1(GPMI_CTRL1, GPMI_MODE, v) +#endif + +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 + +/* + * HW_GPMI_TIMING0 - GPMI Timing Register 0 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA_SETUP:8; + unsigned DATA_HOLD:8; + unsigned ADDRESS_SETUP:8; + unsigned RSVD1:8; + } B; +} hw_gpmi_timing0_t; +#endif + +/* + * constants & macros for entire HW_GPMI_TIMING0 register + */ +#define HW_GPMI_TIMING0_ADDR (0x00112070) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_TIMING0 (*(volatile hw_gpmi_timing0_t *) HW_GPMI_TIMING0_ADDR) +#define HW_GPMI_TIMING0_RD() (HW_GPMI_TIMING0.U) +#define HW_GPMI_TIMING0_WR(v) (HW_GPMI_TIMING0.U = (v)) +#define HW_GPMI_TIMING0_SET(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() | (v))) +#define HW_GPMI_TIMING0_CLR(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() & ~(v))) +#define HW_GPMI_TIMING0_TOG(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() ^ (v))) +#else +#define HW_GPMI_TIMING0_RD() (_rbase->mem32_read(HW_GPMI_TIMING0_ADDR)) +#define HW_GPMI_TIMING0_WR(v) (_rbase->mem32_write(HW_GPMI_TIMING0_ADDR,(v))) +#define HW_GPMI_TIMING0_SET(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() | (v))) +#define HW_GPMI_TIMING0_CLR(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() & ~(v))) +#define HW_GPMI_TIMING0_TOG(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_TIMING0 bitfields + */ +/* --- Register HW_GPMI_TIMING0, field RSVD1 */ + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_TIMING0_RSVD1(v) ((((reg32_t) v) << 24) & BM_GPMI_TIMING0_RSVD1) +#else +#define BF_GPMI_TIMING0_RSVD1(v) (((v) << 24) & BM_GPMI_TIMING0_RSVD1) +#endif +/* --- Register HW_GPMI_TIMING0, field ADDRESS_SETUP */ + +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 + +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING0_ADDRESS_SETUP(v) (HW_GPMI_TIMING0.B.ADDRESS_SETUP = (v)) +#endif + +/* --- Register HW_GPMI_TIMING0, field DATA_HOLD */ + +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 + +#define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING0_DATA_HOLD(v) (HW_GPMI_TIMING0.B.DATA_HOLD = (v)) +#endif + +/* --- Register HW_GPMI_TIMING0, field DATA_SETUP */ + +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF + +#define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING0_DATA_SETUP(v) (HW_GPMI_TIMING0.B.DATA_SETUP = (v)) +#endif + +/* + * HW_GPMI_TIMING1 - GPMI Timing Register 1 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RSVD1:16; + unsigned DEVICE_BUSY_TIMEOUT:16; + } B; +} hw_gpmi_timing1_t; +#endif + +/* + * constants & macros for entire HW_GPMI_TIMING1 register + */ +#define HW_GPMI_TIMING1_ADDR (0x00112080) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_TIMING1 (*(volatile hw_gpmi_timing1_t *) HW_GPMI_TIMING1_ADDR) +#define HW_GPMI_TIMING1_RD() (HW_GPMI_TIMING1.U) +#define HW_GPMI_TIMING1_WR(v) (HW_GPMI_TIMING1.U = (v)) +#define HW_GPMI_TIMING1_SET(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() | (v))) +#define HW_GPMI_TIMING1_CLR(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() & ~(v))) +#define HW_GPMI_TIMING1_TOG(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() ^ (v))) +#else +#define HW_GPMI_TIMING1_RD() (_rbase->mem32_read(HW_GPMI_TIMING1_ADDR)) +#define HW_GPMI_TIMING1_WR(v) (_rbase->mem32_write(HW_GPMI_TIMING1_ADDR,(v))) +#define HW_GPMI_TIMING1_SET(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() | (v))) +#define HW_GPMI_TIMING1_CLR(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() & ~(v))) +#define HW_GPMI_TIMING1_TOG(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_TIMING1 bitfields + */ +/* --- Register HW_GPMI_TIMING1, field DEVICE_BUSY_TIMEOUT */ + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) ((((reg32_t) v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#else +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (HW_GPMI_TIMING1.B.DEVICE_BUSY_TIMEOUT = (v)) +#endif + +/* --- Register HW_GPMI_TIMING1, field RSVD1 */ + +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF + +#define BF_GPMI_TIMING1_RSVD1(v) (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +/* + * HW_GPMI_TIMING2 - GPMI Timing Register 2 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA_PAUSE:4; + unsigned CMDADD_PAUSE:4; + unsigned POSTAMBLE_DELAY:4; + unsigned PREAMBLE_DELAY:4; + unsigned CE_DELAY:5; + unsigned RSVD0:3; + unsigned READ_LATENCY:3; + unsigned RSVD1:5; + } B; +} hw_gpmi_timing2_t; +#endif + +/* + * constants & macros for entire HW_GPMI_TIMING2 register + */ +#define HW_GPMI_TIMING2_ADDR (0x00112090) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_TIMING2 (*(volatile hw_gpmi_timing2_t *) HW_GPMI_TIMING2_ADDR) +#define HW_GPMI_TIMING2_RD() (HW_GPMI_TIMING2.U) +#define HW_GPMI_TIMING2_WR(v) (HW_GPMI_TIMING2.U = (v)) +#define HW_GPMI_TIMING2_SET(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() | (v))) +#define HW_GPMI_TIMING2_CLR(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() & ~(v))) +#define HW_GPMI_TIMING2_TOG(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() ^ (v))) +#else +#define HW_GPMI_TIMING2_RD() (_rbase->mem32_read(HW_GPMI_TIMING2_ADDR)) +#define HW_GPMI_TIMING2_WR(v) (_rbase->mem32_write(HW_GPMI_TIMING2_ADDR,(v))) +#define HW_GPMI_TIMING2_SET(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() | (v))) +#define HW_GPMI_TIMING2_CLR(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() & ~(v))) +#define HW_GPMI_TIMING2_TOG(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_TIMING2 bitfields + */ +/* --- Register HW_GPMI_TIMING2, field RSVD1 */ + +#define BP_GPMI_TIMING2_RSVD1 27 +#define BM_GPMI_TIMING2_RSVD1 0xF8000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_TIMING2_RSVD1(v) ((((reg32_t) v) << 27) & BM_GPMI_TIMING2_RSVD1) +#else +#define BF_GPMI_TIMING2_RSVD1(v) (((v) << 27) & BM_GPMI_TIMING2_RSVD1) +#endif +/* --- Register HW_GPMI_TIMING2, field READ_LATENCY */ + +#define BP_GPMI_TIMING2_READ_LATENCY 24 +#define BM_GPMI_TIMING2_READ_LATENCY 0x07000000 + +#define BF_GPMI_TIMING2_READ_LATENCY(v) (((v) << 24) & BM_GPMI_TIMING2_READ_LATENCY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_READ_LATENCY(v) BF_CS1(GPMI_TIMING2, READ_LATENCY, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field RSVD0 */ + +#define BP_GPMI_TIMING2_RSVD0 21 +#define BM_GPMI_TIMING2_RSVD0 0x00E00000 + +#define BF_GPMI_TIMING2_RSVD0(v) (((v) << 21) & BM_GPMI_TIMING2_RSVD0) +/* --- Register HW_GPMI_TIMING2, field CE_DELAY */ + +#define BP_GPMI_TIMING2_CE_DELAY 16 +#define BM_GPMI_TIMING2_CE_DELAY 0x001F0000 + +#define BF_GPMI_TIMING2_CE_DELAY(v) (((v) << 16) & BM_GPMI_TIMING2_CE_DELAY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_CE_DELAY(v) BF_CS1(GPMI_TIMING2, CE_DELAY, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field PREAMBLE_DELAY */ + +#define BP_GPMI_TIMING2_PREAMBLE_DELAY 12 +#define BM_GPMI_TIMING2_PREAMBLE_DELAY 0x0000F000 + +#define BF_GPMI_TIMING2_PREAMBLE_DELAY(v) (((v) << 12) & BM_GPMI_TIMING2_PREAMBLE_DELAY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_PREAMBLE_DELAY(v) BF_CS1(GPMI_TIMING2, PREAMBLE_DELAY, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field POSTAMBLE_DELAY */ + +#define BP_GPMI_TIMING2_POSTAMBLE_DELAY 8 +#define BM_GPMI_TIMING2_POSTAMBLE_DELAY 0x00000F00 + +#define BF_GPMI_TIMING2_POSTAMBLE_DELAY(v) (((v) << 8) & BM_GPMI_TIMING2_POSTAMBLE_DELAY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_POSTAMBLE_DELAY(v) BF_CS1(GPMI_TIMING2, POSTAMBLE_DELAY, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field CMDADD_PAUSE */ + +#define BP_GPMI_TIMING2_CMDADD_PAUSE 4 +#define BM_GPMI_TIMING2_CMDADD_PAUSE 0x000000F0 + +#define BF_GPMI_TIMING2_CMDADD_PAUSE(v) (((v) << 4) & BM_GPMI_TIMING2_CMDADD_PAUSE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_CMDADD_PAUSE(v) BF_CS1(GPMI_TIMING2, CMDADD_PAUSE, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field DATA_PAUSE */ + +#define BP_GPMI_TIMING2_DATA_PAUSE 0 +#define BM_GPMI_TIMING2_DATA_PAUSE 0x0000000F + +#define BF_GPMI_TIMING2_DATA_PAUSE(v) (((v) << 0) & BM_GPMI_TIMING2_DATA_PAUSE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_DATA_PAUSE(v) BF_CS1(GPMI_TIMING2, DATA_PAUSE, v) +#endif + +/* + * HW_GPMI_DATA - GPMI DMA Data Transfer Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA:32; + } B; +} hw_gpmi_data_t; +#endif + +/* + * constants & macros for entire HW_GPMI_DATA register + */ +#define HW_GPMI_DATA_ADDR (0x001120a0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_DATA (*(volatile hw_gpmi_data_t *) HW_GPMI_DATA_ADDR) +#define HW_GPMI_DATA_RD() (HW_GPMI_DATA.U) +#define HW_GPMI_DATA_WR(v) (HW_GPMI_DATA.U = (v)) +#define HW_GPMI_DATA_SET(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() | (v))) +#define HW_GPMI_DATA_CLR(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() & ~(v))) +#define HW_GPMI_DATA_TOG(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() ^ (v))) +#else +#define HW_GPMI_DATA_RD() (_rbase->mem32_read(HW_GPMI_DATA_ADDR)) +#define HW_GPMI_DATA_WR(v) (_rbase->mem32_write(HW_GPMI_DATA_ADDR,(v))) +#define HW_GPMI_DATA_SET(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() | (v))) +#define HW_GPMI_DATA_CLR(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() & ~(v))) +#define HW_GPMI_DATA_TOG(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_DATA bitfields + */ +/* --- Register HW_GPMI_DATA, field DATA */ + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_DATA_DATA(v) ((reg32_t) v) +#else +#define BF_GPMI_DATA_DATA(v) (v) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_DATA_DATA(v) (HW_GPMI_DATA.B.DATA = (v)) +#endif + +/* + * HW_GPMI_STAT - GPMI Status Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned PRESENT:1; + unsigned FIFO_FULL:1; + unsigned FIFO_EMPTY:1; + unsigned INVALID_BUFFER_MASK:1; + unsigned ATA_IRQ:1; + unsigned RSVD1:3; + unsigned DEV0_ERROR:1; + unsigned DEV1_ERROR:1; + unsigned DEV2_ERROR:1; + unsigned DEV3_ERROR:1; + unsigned DEV4_ERROR:1; + unsigned DEV5_ERROR:1; + unsigned DEV6_ERROR:1; + unsigned DEV7_ERROR:1; + unsigned RDY_TIMEOUT:8; + unsigned READY_BUSY:8; + } B; +} hw_gpmi_stat_t; +#endif + +/* + * constants & macros for entire HW_GPMI_STAT register + */ +#define HW_GPMI_STAT_ADDR (0x001120b0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_STAT (*(volatile hw_gpmi_stat_t *) HW_GPMI_STAT_ADDR) +#define HW_GPMI_STAT_RD() (HW_GPMI_STAT.U) +#else +#define HW_GPMI_STAT_RD() (_rbase->mem32_read(HW_GPMI_STAT_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_STAT bitfields + */ +/* --- Register HW_GPMI_STAT, field READY_BUSY */ + +#define BP_GPMI_STAT_READY_BUSY 24 +#define BM_GPMI_STAT_READY_BUSY 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_STAT_READY_BUSY(v) ((((reg32_t) v) << 24) & BM_GPMI_STAT_READY_BUSY) +#else +#define BF_GPMI_STAT_READY_BUSY(v) (((v) << 24) & BM_GPMI_STAT_READY_BUSY) +#endif +/* --- Register HW_GPMI_STAT, field RDY_TIMEOUT */ + +#define BP_GPMI_STAT_RDY_TIMEOUT 16 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000 + +#define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT) +/* --- Register HW_GPMI_STAT, field DEV7_ERROR */ + +#define BP_GPMI_STAT_DEV7_ERROR 15 +#define BM_GPMI_STAT_DEV7_ERROR 0x00008000 + +#define BF_GPMI_STAT_DEV7_ERROR(v) (((v) << 15) & BM_GPMI_STAT_DEV7_ERROR) +/* --- Register HW_GPMI_STAT, field DEV6_ERROR */ + +#define BP_GPMI_STAT_DEV6_ERROR 14 +#define BM_GPMI_STAT_DEV6_ERROR 0x00004000 + +#define BF_GPMI_STAT_DEV6_ERROR(v) (((v) << 14) & BM_GPMI_STAT_DEV6_ERROR) +/* --- Register HW_GPMI_STAT, field DEV5_ERROR */ + +#define BP_GPMI_STAT_DEV5_ERROR 13 +#define BM_GPMI_STAT_DEV5_ERROR 0x00002000 + +#define BF_GPMI_STAT_DEV5_ERROR(v) (((v) << 13) & BM_GPMI_STAT_DEV5_ERROR) +/* --- Register HW_GPMI_STAT, field DEV4_ERROR */ + +#define BP_GPMI_STAT_DEV4_ERROR 12 +#define BM_GPMI_STAT_DEV4_ERROR 0x00001000 + +#define BF_GPMI_STAT_DEV4_ERROR(v) (((v) << 12) & BM_GPMI_STAT_DEV4_ERROR) +/* --- Register HW_GPMI_STAT, field DEV3_ERROR */ + +#define BP_GPMI_STAT_DEV3_ERROR 11 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000800 + +#define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 11) & BM_GPMI_STAT_DEV3_ERROR) +/* --- Register HW_GPMI_STAT, field DEV2_ERROR */ + +#define BP_GPMI_STAT_DEV2_ERROR 10 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000400 + +#define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 10) & BM_GPMI_STAT_DEV2_ERROR) +/* --- Register HW_GPMI_STAT, field DEV1_ERROR */ + +#define BP_GPMI_STAT_DEV1_ERROR 9 +#define BM_GPMI_STAT_DEV1_ERROR 0x00000200 + +#define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 9) & BM_GPMI_STAT_DEV1_ERROR) +/* --- Register HW_GPMI_STAT, field DEV0_ERROR */ + +#define BP_GPMI_STAT_DEV0_ERROR 8 +#define BM_GPMI_STAT_DEV0_ERROR 0x00000100 + +#define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 8) & BM_GPMI_STAT_DEV0_ERROR) +/* --- Register HW_GPMI_STAT, field RSVD1 */ + +#define BP_GPMI_STAT_RSVD1 5 +#define BM_GPMI_STAT_RSVD1 0x000000E0 + +#define BF_GPMI_STAT_RSVD1(v) (((v) << 5) & BM_GPMI_STAT_RSVD1) +/* --- Register HW_GPMI_STAT, field ATA_IRQ */ + +#define BP_GPMI_STAT_ATA_IRQ 4 +#define BM_GPMI_STAT_ATA_IRQ 0x00000010 + +#define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 4) & BM_GPMI_STAT_ATA_IRQ) +/* --- Register HW_GPMI_STAT, field INVALID_BUFFER_MASK */ + +#define BP_GPMI_STAT_INVALID_BUFFER_MASK 3 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008 + +#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 3) & BM_GPMI_STAT_INVALID_BUFFER_MASK) +/* --- Register HW_GPMI_STAT, field FIFO_EMPTY */ + +#define BP_GPMI_STAT_FIFO_EMPTY 2 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004 + +#define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 2) & BM_GPMI_STAT_FIFO_EMPTY) +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 + +/* --- Register HW_GPMI_STAT, field FIFO_FULL */ + +#define BP_GPMI_STAT_FIFO_FULL 1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000002 + +#define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 1) & BM_GPMI_STAT_FIFO_FULL) +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 + +/* --- Register HW_GPMI_STAT, field PRESENT */ + +#define BP_GPMI_STAT_PRESENT 0 +#define BM_GPMI_STAT_PRESENT 0x00000001 + +#define BF_GPMI_STAT_PRESENT(v) (((v) << 0) & BM_GPMI_STAT_PRESENT) +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 + +/* + * HW_GPMI_DEBUG - GPMI Debug Information Register + */ + /* +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CMD_END:8; + unsigned DMAREQ:8; + unsigned DMA_SENSE:8; + unsigned WAIT_FOR_READY_END:8; + } B; +} hw_gpmi_debug_t; +#endif +*/ +/* + * constants & macros for entire HW_GPMI_DEBUG register + */ +#define HW_GPMI_DEBUG_ADDR (0x001120c0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_DEBUG (*(volatile hw_gpmi_debug_t *) HW_GPMI_DEBUG_ADDR) +#define HW_GPMI_DEBUG_RD() (HW_GPMI_DEBUG.U) +#else +#define HW_GPMI_DEBUG_RD() (_rbase->mem32_read(HW_GPMI_DEBUG_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_DEBUG bitfields + */ +/* --- Register HW_GPMI_DEBUG, field WAIT_FOR_READY_END */ + +#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) ((((reg32_t) v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#else +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#endif +/* --- Register HW_GPMI_DEBUG, field DMA_SENSE */ + +#define BP_GPMI_DEBUG_DMA_SENSE 16 +#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000 + +#define BF_GPMI_DEBUG_DMA_SENSE(v) (((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE) +/* --- Register HW_GPMI_DEBUG, field DMAREQ */ + +#define BP_GPMI_DEBUG_DMAREQ 8 +#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00 + +#define BF_GPMI_DEBUG_DMAREQ(v) (((v) << 8) & BM_GPMI_DEBUG_DMAREQ) +/* --- Register HW_GPMI_DEBUG, field CMD_END */ + +#define BP_GPMI_DEBUG_CMD_END 0 +#define BM_GPMI_DEBUG_CMD_END 0x000000FF + +#define BF_GPMI_DEBUG_CMD_END(v) (((v) << 0) & BM_GPMI_DEBUG_CMD_END) + +/* + * HW_GPMI_VERSION - GPMI Version Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned STEP:16; + unsigned MINOR:8; + unsigned MAJOR:8; + } B; +} hw_gpmi_version_t; +#endif + +/* + * constants & macros for entire HW_GPMI_VERSION register + */ +#define HW_GPMI_VERSION_ADDR (0x001120d0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_VERSION (*(volatile hw_gpmi_version_t *) HW_GPMI_VERSION_ADDR) +#define HW_GPMI_VERSION_RD() (HW_GPMI_VERSION.U) +#else +#define HW_GPMI_VERSION_RD() (_rbase->mem32_read(HW_GPMI_VERSION_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_VERSION bitfields + */ +/* --- Register HW_GPMI_VERSION, field MAJOR */ + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_VERSION_MAJOR(v) ((((reg32_t) v) << 24) & BM_GPMI_VERSION_MAJOR) +#else +#define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#endif +/* --- Register HW_GPMI_VERSION, field MINOR */ + +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 + +#define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & BM_GPMI_VERSION_MINOR) +/* --- Register HW_GPMI_VERSION, field STEP */ + +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF + +#define BF_GPMI_VERSION_STEP(v) (((v) << 0) & BM_GPMI_VERSION_STEP) + +/* + * HW_GPMI_DEBUG2 - GPMI Debug2 Information Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RDN_TAP:6; + unsigned UPDATE_WINDOW:1; + unsigned VIEW_DELAYED_RDN:1; + unsigned SYND2GPMI_READY:1; + unsigned SYND2GPMI_VALID:1; + unsigned GPMI2SYND_READY:1; + unsigned GPMI2SYND_VALID:1; + unsigned SYND2GPMI_BE:4; + unsigned MAIN_STATE:4; + unsigned PIN_STATE:3; + unsigned BUSY:1; + unsigned UDMA_STATE:4; + unsigned RSVD1:4; + } B; +} hw_gpmi_debug2_t; +#endif + +/* + * constants & macros for entire HW_GPMI_DEBUG2 register + */ +#define HW_GPMI_DEBUG2_ADDR (0x001120e0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_DEBUG2 (*(volatile hw_gpmi_debug2_t *) HW_GPMI_DEBUG2_ADDR) +#define HW_GPMI_DEBUG2_RD() (HW_GPMI_DEBUG2.U) +#define HW_GPMI_DEBUG2_WR(v) (HW_GPMI_DEBUG2.U = (v)) +#define HW_GPMI_DEBUG2_SET(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() | (v))) +#define HW_GPMI_DEBUG2_CLR(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() & ~(v))) +#define HW_GPMI_DEBUG2_TOG(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() ^ (v))) +#else +#define HW_GPMI_DEBUG2_RD() (_rbase->mem32_read(HW_GPMI_DEBUG2_ADDR)) +#define HW_GPMI_DEBUG2_WR(v) (_rbase->mem32_write(HW_GPMI_DEBUG2_ADDR,(v))) +#define HW_GPMI_DEBUG2_SET(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() | (v))) +#define HW_GPMI_DEBUG2_CLR(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() & ~(v))) +#define HW_GPMI_DEBUG2_TOG(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_DEBUG2 bitfields + */ +/* --- Register HW_GPMI_DEBUG2, field RSVD1 */ + +#define BP_GPMI_DEBUG2_RSVD1 28 +#define BM_GPMI_DEBUG2_RSVD1 0xF0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_DEBUG2_RSVD1(v) ((((reg32_t) v) << 28) & BM_GPMI_DEBUG2_RSVD1) +#else +#define BF_GPMI_DEBUG2_RSVD1(v) (((v) << 28) & BM_GPMI_DEBUG2_RSVD1) +#endif +/* --- Register HW_GPMI_DEBUG2, field UDMA_STATE */ + +#define BP_GPMI_DEBUG2_UDMA_STATE 24 +#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000 + +#define BF_GPMI_DEBUG2_UDMA_STATE(v) (((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE) +/* --- Register HW_GPMI_DEBUG2, field BUSY */ + +#define BP_GPMI_DEBUG2_BUSY 23 +#define BM_GPMI_DEBUG2_BUSY 0x00800000 + +#define BF_GPMI_DEBUG2_BUSY(v) (((v) << 23) & BM_GPMI_DEBUG2_BUSY) +#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG2_BUSY__ENABLED 0x1 + +/* --- Register HW_GPMI_DEBUG2, field PIN_STATE */ + +#define BP_GPMI_DEBUG2_PIN_STATE 20 +#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000 + +#define BF_GPMI_DEBUG2_PIN_STATE(v) (((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE) +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7 + +/* --- Register HW_GPMI_DEBUG2, field MAIN_STATE */ + +#define BP_GPMI_DEBUG2_MAIN_STATE 16 +#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000 + +#define BF_GPMI_DEBUG2_MAIN_STATE(v) (((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE) +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA + +/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_BE */ + +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 + +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +/* --- Register HW_GPMI_DEBUG2, field GPMI2SYND_VALID */ + +#define BP_GPMI_DEBUG2_GPMI2SYND_VALID 11 +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 + +#define BF_GPMI_DEBUG2_GPMI2SYND_VALID(v) (((v) << 11) & BM_GPMI_DEBUG2_GPMI2SYND_VALID) +/* --- Register HW_GPMI_DEBUG2, field GPMI2SYND_READY */ + +#define BP_GPMI_DEBUG2_GPMI2SYND_READY 10 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 + +#define BF_GPMI_DEBUG2_GPMI2SYND_READY(v) (((v) << 10) & BM_GPMI_DEBUG2_GPMI2SYND_READY) +/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_VALID */ + +#define BP_GPMI_DEBUG2_SYND2GPMI_VALID 9 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 + +#define BF_GPMI_DEBUG2_SYND2GPMI_VALID(v) (((v) << 9) & BM_GPMI_DEBUG2_SYND2GPMI_VALID) +/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_READY */ + +#define BP_GPMI_DEBUG2_SYND2GPMI_READY 8 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 + +#define BF_GPMI_DEBUG2_SYND2GPMI_READY(v) (((v) << 8) & BM_GPMI_DEBUG2_SYND2GPMI_READY) +/* --- Register HW_GPMI_DEBUG2, field VIEW_DELAYED_RDN */ + +#define BP_GPMI_DEBUG2_VIEW_DELAYED_RDN 7 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 + +#define BF_GPMI_DEBUG2_VIEW_DELAYED_RDN(v) (((v) << 7) & BM_GPMI_DEBUG2_VIEW_DELAYED_RDN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_DEBUG2_VIEW_DELAYED_RDN(v) BF_CS1(GPMI_DEBUG2, VIEW_DELAYED_RDN, v) +#endif + +/* --- Register HW_GPMI_DEBUG2, field UPDATE_WINDOW */ + +#define BP_GPMI_DEBUG2_UPDATE_WINDOW 6 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 + +#define BF_GPMI_DEBUG2_UPDATE_WINDOW(v) (((v) << 6) & BM_GPMI_DEBUG2_UPDATE_WINDOW) +/* --- Register HW_GPMI_DEBUG2, field RDN_TAP */ + +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F + +#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +/* + * HW_GPMI_DEBUG3 - GPMI Debug3 Information Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DEV_WORD_CNTR:16; + unsigned APB_WORD_CNTR:16; + } B; +} hw_gpmi_debug3_t; +#endif + +/* + * constants & macros for entire HW_GPMI_DEBUG3 register + */ +#define HW_GPMI_DEBUG3_ADDR (0x001120f0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_DEBUG3 (*(volatile hw_gpmi_debug3_t *) HW_GPMI_DEBUG3_ADDR) +#define HW_GPMI_DEBUG3_RD() (HW_GPMI_DEBUG3.U) +#else +#define HW_GPMI_DEBUG3_RD() (_rbase->mem32_read(HW_GPMI_DEBUG3_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_DEBUG3 bitfields + */ +/* --- Register HW_GPMI_DEBUG3, field APB_WORD_CNTR */ + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) ((((reg32_t) v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#else +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#endif +/* --- Register HW_GPMI_DEBUG3, field DEV_WORD_CNTR */ + +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF + +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +/* + * HW_GPMI_READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register + */ + /* +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ENABLE:1; + unsigned RESET:1; + unsigned SLV_FORCE_UPD:1; + unsigned SLV_DLY_TARGET:4; + unsigned GATE_UPDATE:1; + unsigned REFCLK_ON:1; + unsigned SLV_OVERRIDE:1; + unsigned SLV_OVERRIDE_VAL:8; + unsigned RSVD1:2; + unsigned SLV_UPDATE_INT:8; + unsigned REF_UPDATE_INT:4; + } B; +} hw_gpmi_read_ddr_dll_ctrl_t; +#endif +*/ +/* + * constants & macros for entire HW_GPMI_READ_DDR_DLL_CTRL register + */ +#define HW_GPMI_READ_DDR_DLL_CTRL_ADDR (0x00112100) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_READ_DDR_DLL_CTRL (*(volatile hw_gpmi_read_ddr_dll_ctrl_t *) HW_GPMI_READ_DDR_DLL_CTRL_ADDR) +#define HW_GPMI_READ_DDR_DLL_CTRL_RD() (HW_GPMI_READ_DDR_DLL_CTRL.U) +#define HW_GPMI_READ_DDR_DLL_CTRL_WR(v) (HW_GPMI_READ_DDR_DLL_CTRL.U = (v)) +#define HW_GPMI_READ_DDR_DLL_CTRL_SET(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() | (v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_CLR(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() & ~(v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_TOG(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() ^ (v))) +#else +#define HW_GPMI_READ_DDR_DLL_CTRL_RD() (_rbase->mem32_read(HW_GPMI_READ_DDR_DLL_CTRL_ADDR)) +#define HW_GPMI_READ_DDR_DLL_CTRL_WR(v) (_rbase->mem32_write(HW_GPMI_READ_DDR_DLL_CTRL_ADDR,(v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_SET(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() | (v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_CLR(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() & ~(v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_TOG(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_READ_DDR_DLL_CTRL bitfields + */ +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field REF_UPDATE_INT */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) ((((reg32_t) v) << 28) & BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT) +#else +#define BF_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) (((v) << 28) & BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, REF_UPDATE_INT, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_UPDATE_INT */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(v) (((v) << 20) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_UPDATE_INT, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field RSVD1 */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_RSVD1 18 +#define BM_GPMI_READ_DDR_DLL_CTRL_RSVD1 0x000C0000 + +#define BF_GPMI_READ_DDR_DLL_CTRL_RSVD1(v) (((v) << 18) & BM_GPMI_READ_DDR_DLL_CTRL_RSVD1) +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_OVERRIDE_VAL */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) (((v) << 10) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_OVERRIDE_VAL, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_OVERRIDE */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE 9 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(v) (((v) << 9) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_OVERRIDE, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field REFCLK_ON */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON 8 +#define BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON 0x00000100 + +#define BF_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(v) (((v) << 8) & BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, REFCLK_ON, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field GATE_UPDATE */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE 7 +#define BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE 0x00000080 + +#define BF_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(v) (((v) << 7) & BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, GATE_UPDATE, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_DLY_TARGET */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(v) (((v) << 3) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_DLY_TARGET, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_FORCE_UPD */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD 2 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(v) (((v) << 2) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_FORCE_UPD, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field RESET */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_RESET 1 +#define BM_GPMI_READ_DDR_DLL_CTRL_RESET 0x00000002 + +#define BF_GPMI_READ_DDR_DLL_CTRL_RESET(v) (((v) << 1) & BM_GPMI_READ_DDR_DLL_CTRL_RESET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_RESET(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, RESET, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field ENABLE */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_ENABLE 0 +#define BM_GPMI_READ_DDR_DLL_CTRL_ENABLE 0x00000001 + +#define BF_GPMI_READ_DDR_DLL_CTRL_ENABLE(v) (((v) << 0) & BM_GPMI_READ_DDR_DLL_CTRL_ENABLE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_ENABLE(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, ENABLE, v) +#endif + +/* + * HW_GPMI_WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register + */ + /* +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ENABLE:1; + unsigned RESET:1; + unsigned SLV_FORCE_UPD:1; + unsigned SLV_DLY_TARGET:4; + unsigned GATE_UPDATE:1; + unsigned REFCLK_ON:1; + unsigned SLV_OVERRIDE:1; + unsigned SLV_OVERRIDE_VAL:8; + unsigned RSVD1:2; + unsigned SLV_UPDATE_INT:8; + unsigned REF_UPDATE_INT:4; + } B; +} hw_gpmi_write_ddr_dll_ctrl_t; +#endif +*/ +/* + * constants & macros for entire HW_GPMI_WRITE_DDR_DLL_CTRL register + */ +#define HW_GPMI_WRITE_DDR_DLL_CTRL_ADDR (0x00112110) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_WRITE_DDR_DLL_CTRL (*(volatile hw_gpmi_write_ddr_dll_ctrl_t *) HW_GPMI_WRITE_DDR_DLL_CTRL_ADDR) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_RD() (HW_GPMI_WRITE_DDR_DLL_CTRL.U) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_WR(v) (HW_GPMI_WRITE_DDR_DLL_CTRL.U = (v)) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_SET(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() | (v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_CLR(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() & ~(v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_TOG(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() ^ (v))) +#else +#define HW_GPMI_WRITE_DDR_DLL_CTRL_RD() (_rbase->mem32_read(HW_GPMI_WRITE_DDR_DLL_CTRL_ADDR)) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_WR(v) (_rbase->mem32_write(HW_GPMI_WRITE_DDR_DLL_CTRL_ADDR,(v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_SET(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() | (v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_CLR(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() & ~(v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_TOG(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_WRITE_DDR_DLL_CTRL bitfields + */ +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field REF_UPDATE_INT */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) ((((reg32_t) v) << 28) & BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT) +#else +#define BF_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) (((v) << 28) & BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, REF_UPDATE_INT, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_UPDATE_INT */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(v) (((v) << 20) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_UPDATE_INT, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field RSVD1 */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 18 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 0x000C0000 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_RSVD1(v) (((v) << 18) & BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1) +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_OVERRIDE_VAL */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) (((v) << 10) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_OVERRIDE_VAL, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_OVERRIDE */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE 9 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(v) (((v) << 9) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_OVERRIDE, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field REFCLK_ON */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON 8 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON 0x00000100 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(v) (((v) << 8) & BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, REFCLK_ON, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field GATE_UPDATE */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE 7 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE 0x00000080 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(v) (((v) << 7) & BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, GATE_UPDATE, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_DLY_TARGET */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(v) (((v) << 3) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_DLY_TARGET, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_FORCE_UPD */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD 2 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(v) (((v) << 2) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_FORCE_UPD, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field RESET */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_RESET 1 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_RESET 0x00000002 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_RESET(v) (((v) << 1) & BM_GPMI_WRITE_DDR_DLL_CTRL_RESET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_RESET(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, RESET, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field ENABLE */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_ENABLE 0 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE 0x00000001 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_ENABLE(v) (((v) << 0) & BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_ENABLE(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, ENABLE, v) +#endif + +/* + * HW_GPMI_READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned SLV_LOCK:1; + unsigned SLV_SEL:8; + unsigned RSVD0:7; + unsigned REF_LOCK:1; + unsigned REF_SEL:8; + unsigned RSVD1:7; + } B; +} hw_gpmi_read_ddr_dll_sts_t; +#endif + +/* + * constants & macros for entire HW_GPMI_READ_DDR_DLL_STS register + */ +#define HW_GPMI_READ_DDR_DLL_STS_ADDR (0x00112120) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_READ_DDR_DLL_STS (*(volatile hw_gpmi_read_ddr_dll_sts_t *) HW_GPMI_READ_DDR_DLL_STS_ADDR) +#define HW_GPMI_READ_DDR_DLL_STS_RD() (HW_GPMI_READ_DDR_DLL_STS.U) +#else +#define HW_GPMI_READ_DDR_DLL_STS_RD() (_rbase->mem32_read(HW_GPMI_READ_DDR_DLL_STS_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_READ_DDR_DLL_STS bitfields + */ +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field RSVD1 */ + +#define BP_GPMI_READ_DDR_DLL_STS_RSVD1 25 +#define BM_GPMI_READ_DDR_DLL_STS_RSVD1 0xFE000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_READ_DDR_DLL_STS_RSVD1(v) ((((reg32_t) v) << 25) & BM_GPMI_READ_DDR_DLL_STS_RSVD1) +#else +#define BF_GPMI_READ_DDR_DLL_STS_RSVD1(v) (((v) << 25) & BM_GPMI_READ_DDR_DLL_STS_RSVD1) +#endif +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field REF_SEL */ + +#define BP_GPMI_READ_DDR_DLL_STS_REF_SEL 17 +#define BM_GPMI_READ_DDR_DLL_STS_REF_SEL 0x01FE0000 + +#define BF_GPMI_READ_DDR_DLL_STS_REF_SEL(v) (((v) << 17) & BM_GPMI_READ_DDR_DLL_STS_REF_SEL) +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field REF_LOCK */ + +#define BP_GPMI_READ_DDR_DLL_STS_REF_LOCK 16 +#define BM_GPMI_READ_DDR_DLL_STS_REF_LOCK 0x00010000 + +#define BF_GPMI_READ_DDR_DLL_STS_REF_LOCK(v) (((v) << 16) & BM_GPMI_READ_DDR_DLL_STS_REF_LOCK) +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field RSVD0 */ + +#define BP_GPMI_READ_DDR_DLL_STS_RSVD0 9 +#define BM_GPMI_READ_DDR_DLL_STS_RSVD0 0x0000FE00 + +#define BF_GPMI_READ_DDR_DLL_STS_RSVD0(v) (((v) << 9) & BM_GPMI_READ_DDR_DLL_STS_RSVD0) +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field SLV_SEL */ + +#define BP_GPMI_READ_DDR_DLL_STS_SLV_SEL 1 +#define BM_GPMI_READ_DDR_DLL_STS_SLV_SEL 0x000001FE + +#define BF_GPMI_READ_DDR_DLL_STS_SLV_SEL(v) (((v) << 1) & BM_GPMI_READ_DDR_DLL_STS_SLV_SEL) +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field SLV_LOCK */ + +#define BP_GPMI_READ_DDR_DLL_STS_SLV_LOCK 0 +#define BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK 0x00000001 + +#define BF_GPMI_READ_DDR_DLL_STS_SLV_LOCK(v) (((v) << 0) & BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK) + +/* + * HW_GPMI_WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned SLV_LOCK:1; + unsigned SLV_SEL:8; + unsigned RSVD0:7; + unsigned REF_LOCK:1; + unsigned REF_SEL:8; + unsigned RSVD1:7; + } B; +} hw_gpmi_write_ddr_dll_sts_t; +#endif + +/* + * constants & macros for entire HW_GPMI_WRITE_DDR_DLL_STS register + */ +#define HW_GPMI_WRITE_DDR_DLL_STS_ADDR (0x00112130) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_WRITE_DDR_DLL_STS (*(volatile hw_gpmi_write_ddr_dll_sts_t *) HW_GPMI_WRITE_DDR_DLL_STS_ADDR) +#define HW_GPMI_WRITE_DDR_DLL_STS_RD() (HW_GPMI_WRITE_DDR_DLL_STS.U) +#else +#define HW_GPMI_WRITE_DDR_DLL_STS_RD() (_rbase->mem32_read(HW_GPMI_WRITE_DDR_DLL_STS_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_WRITE_DDR_DLL_STS bitfields + */ +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field RSVD1 */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD1 25 +#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD1 0xFE000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD1(v) ((((reg32_t) v) << 25) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD1) +#else +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD1(v) (((v) << 25) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD1) +#endif +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field REF_SEL */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_REF_SEL 17 +#define BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL 0x01FE0000 + +#define BF_GPMI_WRITE_DDR_DLL_STS_REF_SEL(v) (((v) << 17) & BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL) +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field REF_LOCK */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_REF_LOCK 16 +#define BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK 0x00010000 + +#define BF_GPMI_WRITE_DDR_DLL_STS_REF_LOCK(v) (((v) << 16) & BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK) +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field RSVD0 */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD0 9 +#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD0 0x0000FE00 + +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD0(v) (((v) << 9) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD0) +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field SLV_SEL */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 1 +#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 0x000001FE + +#define BF_GPMI_WRITE_DDR_DLL_STS_SLV_SEL(v) (((v) << 1) & BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL) +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field SLV_LOCK */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK 0 +#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK 0x00000001 + +#define BF_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(v) (((v) << 0) & BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK) + +#endif /* _GPMI_H */ + +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsgpt.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsgpt.h new file mode 100644 index 0000000000000000000000000000000000000000..b2dd86622af8dcc8b3b261b0a4e5591e4b233c6a --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsgpt.h @@ -0,0 +1,1416 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_GPT_REGISTERS_H__ +#define __HW_GPT_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL GPT + * + * GPT + * + * Registers defined in this header file: + * - HW_GPT_CR - GPT Control Register + * - HW_GPT_PR - GPT Prescaler Register + * - HW_GPT_SR - GPT Status Register + * - HW_GPT_IR - GPT Interrupt Register + * - HW_GPT_OCR1 - GPT Output Compare Register 1 + * - HW_GPT_OCR2 - GPT Output Compare Register 2 + * - HW_GPT_OCR3 - GPT Output Compare Register 3 + * - HW_GPT_ICR1 - GPT Input Capture Register 1 + * - HW_GPT_ICR2 - GPT Input Capture Register 2 + * - HW_GPT_CNT - GPT Counter Register + * + * - hw_gpt_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_GPT_BASE +#define HW_GPT_INSTANCE_COUNT (2) //!< Number of instances of the GPT module. +#define REGS_GPT1_BASE (0x02098000) //!< Base address for GPT. +#define REGS_GPT2_BASE (0x20E8000U) /*!< Base address for GPT2. */ +#define REGS_GPT_BASE REGS_GPT1_BASE +#define IMX_INT_GPT IMX_INT_GPT1 +#define GPT_BASE_ADDR REGS_GPT1_BASE +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_CR - GPT Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_CR - GPT Control Register (RW) + * + * Reset value: 0x00000000 + * + * The GPT Control Register (GPT_CR) is used to program and configure GPT operations. An IP Bus + * Write to the GPT Control Register occurs after one cycle of wait state, while an IP Bus Read + * occurs after 0 wait states. + */ +typedef union _hw_gpt_cr +{ + reg32_t U; + struct _hw_gpt_cr_bitfields + { + unsigned EN : 1; //!< [0] GPT Enable. + unsigned ENMOD : 1; //!< [1] GPT Enable mode. + unsigned DBGEN : 1; //!< [2] GPT debug mode enable. + unsigned WAITEN : 1; //!< [3] GPT Wait Mode enable. + unsigned DOZEEN : 1; //!< [4] GPT Doze Mode Enable. + unsigned STOPEN : 1; //!< [5] GPT Stop Mode enable. + unsigned CLKSRC : 3; //!< [8:6] Clock Source select. + unsigned FRR : 1; //!< [9] Free-Run or Restart mode. + unsigned _24MEN : 1; //!< [10] Enable 24MHz clock input from crystal. + unsigned RESERVED0 : 4; //!< [14:11] Reserved bits. + unsigned SWR : 1; //!< [15] Software reset. + unsigned IM1 : 2; //!< [17:16] See IM2 + unsigned IM2 : 2; //!< [19:18] IM2 (bits 19-18, Input Capture Channel 2 operating mode) + unsigned OM1 : 3; //!< [22:20] See OM3 + unsigned OM2 : 3; //!< [25:23] See OM3 + unsigned OM3 : 3; //!< [28:26] OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode. + unsigned FO1 : 1; //!< [29] See F03 + unsigned FO2 : 1; //!< [30] See F03 + unsigned FO3 : 1; //!< [31] FO3 Force Output Compare Channel 3 + } B; +} hw_gpt_cr_t; +#endif + +/*! + * @name Constants and macros for entire GPT_CR register + */ +//@{ +#define HW_GPT_CR_ADDR (REGS_GPT_BASE + 0x0) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_CR (*(volatile hw_gpt_cr_t *) HW_GPT_CR_ADDR) +#define HW_GPT_CR_RD() (HW_GPT_CR.U) +#define HW_GPT_CR_WR(v) (HW_GPT_CR.U = (v)) +#define HW_GPT_CR_SET(v) (HW_GPT_CR_WR(HW_GPT_CR_RD() | (v))) +#define HW_GPT_CR_CLR(v) (HW_GPT_CR_WR(HW_GPT_CR_RD() & ~(v))) +#define HW_GPT_CR_TOG(v) (HW_GPT_CR_WR(HW_GPT_CR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual GPT_CR bitfields + */ + +/*! @name Register GPT_CR, field EN[0] (RW) + * + * GPT Enable. The EN bit is the GPT module enable bit. Before setting the EN bit , we recommend + * that all registers be properly programmed . A hardware reset resets the EN bit. A software reset + * does not affect the EN bit. + * + * Values: + * - 0 - GPT is disabled. + * - 1 - GPT is enabled. + */ +//@{ +#define BP_GPT_CR_EN (0) //!< Bit position for GPT_CR_EN. +#define BM_GPT_CR_EN (0x00000001) //!< Bit mask for GPT_CR_EN. + +//! @brief Get value of GPT_CR_EN from a register value. +#define BG_GPT_CR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_EN) >> BP_GPT_CR_EN) + +//! @brief Format value for bitfield GPT_CR_EN. +#define BF_GPT_CR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_EN) & BM_GPT_CR_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN field to a new value. +#define BW_GPT_CR_EN(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_EN) | BF_GPT_CR_EN(v))) +#endif +//@} + +/*! @name Register GPT_CR, field ENMOD[1] (RW) + * + * GPT Enable mode. When the GPT is disabled (EN=0), then both the Main Counter and Prescaler + * Counter freeze their current count values . The ENMOD bit determines the value of the GPT counter + * when Counter is enabled again (if the EN bit is set). If the ENMOD bit is 1, then the Main + * Counter and Prescaler Counter values are reset to 0 after GPT is enabled (EN=1). If the ENMOD bit + * is 0, then the Main Counter and Prescaler Counter restart counting from their frozen values after + * GPT is enabled (EN=1). If GPT is programmed to be disabled in a low power mode (STOP/WAIT), then + * the Main Counter and Prescaler Counter freeze at their current count values when the GPT enters + * low power mode. When GPT exits low power mode, the Main Counter and Prescaler Counter start + * counting from their frozen values, regardless of the ENMOD bit value. Setting the SWR bit will + * clear the Main Counter and Prescaler Counter values, regardless of the value of EN or ENMOD bits. + * A hardware reset resets the ENMOD bit. A software reset does not affect the ENMOD bit. + * + * Values: + * - 0 - GPT counter will retain its value when it is disabled. + * - 1 - GPT counter value is reset to 0 when it is disabled. + */ +//@{ +#define BP_GPT_CR_ENMOD (1) //!< Bit position for GPT_CR_ENMOD. +#define BM_GPT_CR_ENMOD (0x00000002) //!< Bit mask for GPT_CR_ENMOD. + +//! @brief Get value of GPT_CR_ENMOD from a register value. +#define BG_GPT_CR_ENMOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_ENMOD) >> BP_GPT_CR_ENMOD) + +//! @brief Format value for bitfield GPT_CR_ENMOD. +#define BF_GPT_CR_ENMOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_ENMOD) & BM_GPT_CR_ENMOD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENMOD field to a new value. +#define BW_GPT_CR_ENMOD(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_ENMOD) | BF_GPT_CR_ENMOD(v))) +#endif +//@} + +/*! @name Register GPT_CR, field DBGEN[2] (RW) + * + * GPT debug mode enable. The DBGEN read/write control bit enables GPT operation during Debug mode . + * A hardware reset resets the DBGEN bit. A software reset does not affect the DBGEN bit. + * + * Values: + * - 0 - GPT is disabled in debug mode. + * - 1 - GPT is enabled in debug mode. + */ +//@{ +#define BP_GPT_CR_DBGEN (2) //!< Bit position for GPT_CR_DBGEN. +#define BM_GPT_CR_DBGEN (0x00000004) //!< Bit mask for GPT_CR_DBGEN. + +//! @brief Get value of GPT_CR_DBGEN from a register value. +#define BG_GPT_CR_DBGEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_DBGEN) >> BP_GPT_CR_DBGEN) + +//! @brief Format value for bitfield GPT_CR_DBGEN. +#define BF_GPT_CR_DBGEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_DBGEN) & BM_GPT_CR_DBGEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DBGEN field to a new value. +#define BW_GPT_CR_DBGEN(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_DBGEN) | BF_GPT_CR_DBGEN(v))) +#endif +//@} + +/*! @name Register GPT_CR, field WAITEN[3] (RW) + * + * GPT Wait Mode enable. The WAITEN read/write control bit enables GPT operation during Wait mode . + * A hardware reset resets the WAITEN bit. A software reset does not affect the WAITEN bit. + * + * Values: + * - 0 - GPT is disabled in wait mode. + * - 1 - GPT is enabled in wait mode. + */ +//@{ +#define BP_GPT_CR_WAITEN (3) //!< Bit position for GPT_CR_WAITEN. +#define BM_GPT_CR_WAITEN (0x00000008) //!< Bit mask for GPT_CR_WAITEN. + +//! @brief Get value of GPT_CR_WAITEN from a register value. +#define BG_GPT_CR_WAITEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_WAITEN) >> BP_GPT_CR_WAITEN) + +//! @brief Format value for bitfield GPT_CR_WAITEN. +#define BF_GPT_CR_WAITEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_WAITEN) & BM_GPT_CR_WAITEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WAITEN field to a new value. +#define BW_GPT_CR_WAITEN(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_WAITEN) | BF_GPT_CR_WAITEN(v))) +#endif +//@} + +/*! @name Register GPT_CR, field DOZEEN[4] (RW) + * + * GPT Doze Mode Enable. A hardware reset resets the DOZEEN bit. A software reset does not affect + * the DOZEEN bit. + * + * Values: + * - 0 - GPT is disabled in doze mode. + * - 1 - GPT is enabled in doze mode. + */ +//@{ +#define BP_GPT_CR_DOZEEN (4) //!< Bit position for GPT_CR_DOZEEN. +#define BM_GPT_CR_DOZEEN (0x00000010) //!< Bit mask for GPT_CR_DOZEEN. + +//! @brief Get value of GPT_CR_DOZEEN from a register value. +#define BG_GPT_CR_DOZEEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_DOZEEN) >> BP_GPT_CR_DOZEEN) + +//! @brief Format value for bitfield GPT_CR_DOZEEN. +#define BF_GPT_CR_DOZEEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_DOZEEN) & BM_GPT_CR_DOZEEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DOZEEN field to a new value. +#define BW_GPT_CR_DOZEEN(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_DOZEEN) | BF_GPT_CR_DOZEEN(v))) +#endif +//@} + +/*! @name Register GPT_CR, field STOPEN[5] (RW) + * + * GPT Stop Mode enable. The STOPEN read/write control bit enables GPT operation during Stop mode . + * A hardware reset resets the STOPEN bit. A software reset does not affect the STOPEN bit. + * + * Values: + * - 0 - GPT is disabled in Stop mode. + * - 1 - GPT is enabled in Stop mode. + */ +//@{ +#define BP_GPT_CR_STOPEN (5) //!< Bit position for GPT_CR_STOPEN. +#define BM_GPT_CR_STOPEN (0x00000020) //!< Bit mask for GPT_CR_STOPEN. + +//! @brief Get value of GPT_CR_STOPEN from a register value. +#define BG_GPT_CR_STOPEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_STOPEN) >> BP_GPT_CR_STOPEN) + +//! @brief Format value for bitfield GPT_CR_STOPEN. +#define BF_GPT_CR_STOPEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_STOPEN) & BM_GPT_CR_STOPEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STOPEN field to a new value. +#define BW_GPT_CR_STOPEN(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_STOPEN) | BF_GPT_CR_STOPEN(v))) +#endif +//@} + +/*! @name Register GPT_CR, field CLKSRC[8:6] (RW) + * + * Clock Source select. The CLKSRC bits select which clock will go to the prescaler (and + * subsequently be used to run the GPT counter). The CLKSRC bit field value should only be changed + * after disabling the GPT by clearing the EN bit in this register (GPT_CR). A software reset does + * not affect the CLKSRC bit. + * + * Values: + * - 000 - No clock + * - 001 - Peripheral Clock + * - 010 - High Frequency Reference Clock + * - 011 - External Clock (CLKIN) + * - 100 - Low Frequency Reference Clock + * - 101 - Crystal oscillator as Reference Clock + * - others - Reserved + */ +//@{ +#define BP_GPT_CR_CLKSRC (6) //!< Bit position for GPT_CR_CLKSRC. +#define BM_GPT_CR_CLKSRC (0x000001c0) //!< Bit mask for GPT_CR_CLKSRC. + +//! @brief Get value of GPT_CR_CLKSRC from a register value. +#define BG_GPT_CR_CLKSRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_CLKSRC) >> BP_GPT_CR_CLKSRC) + +//! @brief Format value for bitfield GPT_CR_CLKSRC. +#define BF_GPT_CR_CLKSRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_CLKSRC) & BM_GPT_CR_CLKSRC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKSRC field to a new value. +#define BW_GPT_CR_CLKSRC(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_CLKSRC) | BF_GPT_CR_CLKSRC(v))) +#endif +//@} + +/*! @name Register GPT_CR, field FRR[9] (RW) + * + * Free-Run or Restart mode. The FFR bit determines the behavior of the GPT when a compare event in + * channel 1 occurs. In Restart mode, after a compare event, the counter resets to 0x00000000 and + * resumes counting (after the occurrence of a compare event). In Free-Run mode, after a compare + * event, the counter continues counting until 0xFFFFFFFF and then rolls over to 0. + * + * Values: + * - 0 - Restart mode + * - 1 - Free-Run mode + */ +//@{ +#define BP_GPT_CR_FRR (9) //!< Bit position for GPT_CR_FRR. +#define BM_GPT_CR_FRR (0x00000200) //!< Bit mask for GPT_CR_FRR. + +//! @brief Get value of GPT_CR_FRR from a register value. +#define BG_GPT_CR_FRR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_FRR) >> BP_GPT_CR_FRR) + +//! @brief Format value for bitfield GPT_CR_FRR. +#define BF_GPT_CR_FRR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_FRR) & BM_GPT_CR_FRR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FRR field to a new value. +#define BW_GPT_CR_FRR(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_FRR) | BF_GPT_CR_FRR(v))) +#endif +//@} + +/*! @name Register GPT_CR, field _24MEN[10] (RW) + * + * Enable 24MHz clock input from crystal. A hardware reset resets the 24MEN bit. A software reset + * does not affect the 24MEN bit. + * + * Values: + * - 0 - 24M clock disabled + * - 1 - 24M clock enabled + */ +//@{ +#define BP_GPT_CR__24MEN (10) //!< Bit position for GPT_CR__24MEN. +#define BM_GPT_CR__24MEN (0x00000400) //!< Bit mask for GPT_CR__24MEN. + +//! @brief Get value of GPT_CR__24MEN from a register value. +#define BG_GPT_CR__24MEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR__24MEN) >> BP_GPT_CR__24MEN) + +//! @brief Format value for bitfield GPT_CR__24MEN. +#define BF_GPT_CR__24MEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR__24MEN) & BM_GPT_CR__24MEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the _24MEN field to a new value. +#define BW_GPT_CR__24MEN(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR__24MEN) | BF_GPT_CR__24MEN(v))) +#endif +//@} + +/*! @name Register GPT_CR, field SWR[15] (RW) + * + * Software reset. This is the software reset of the GPT module. It is a self-clearing bit. The SWR + * bit is set when the module is in reset state. The SWR bit is cleared when the reset procedure + * finishes. Setting the SWR bit resets all of the registers to their default reset values, except + * for the CLKSRC, EN, ENMOD, STOPEN, WAITEN, and DBGEN bits in the GPT Control Register (this + * control register). + * + * Values: + * - 0 - GPT is not in reset state + * - 1 - GPT is in reset state + */ +//@{ +#define BP_GPT_CR_SWR (15) //!< Bit position for GPT_CR_SWR. +#define BM_GPT_CR_SWR (0x00008000) //!< Bit mask for GPT_CR_SWR. + +//! @brief Get value of GPT_CR_SWR from a register value. +#define BG_GPT_CR_SWR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_SWR) >> BP_GPT_CR_SWR) + +//! @brief Format value for bitfield GPT_CR_SWR. +#define BF_GPT_CR_SWR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_SWR) & BM_GPT_CR_SWR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SWR field to a new value. +#define BW_GPT_CR_SWR(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_SWR) | BF_GPT_CR_SWR(v))) +#endif +//@} + +/*! @name Register GPT_CR, field IM1[17:16] (RW) + * + * See IM2 + */ +//@{ +#define BP_GPT_CR_IM1 (16) //!< Bit position for GPT_CR_IM1. +#define BM_GPT_CR_IM1 (0x00030000) //!< Bit mask for GPT_CR_IM1. + +//! @brief Get value of GPT_CR_IM1 from a register value. +#define BG_GPT_CR_IM1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_IM1) >> BP_GPT_CR_IM1) + +//! @brief Format value for bitfield GPT_CR_IM1. +#define BF_GPT_CR_IM1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_IM1) & BM_GPT_CR_IM1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IM1 field to a new value. +#define BW_GPT_CR_IM1(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_IM1) | BF_GPT_CR_IM1(v))) +#endif +//@} + +/*! @name Register GPT_CR, field IM2[19:18] (RW) + * + * IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 + * operating mode) The IM n bit field determines the transition on the input pin (for Input capture + * channel n ), which will trigger a capture event. + * + * Values: + * - 00 - capture disabled + * - 01 - capture on rising edge only + * - 10 - capture on falling edge only + * - 11 - capture on both edges + */ +//@{ +#define BP_GPT_CR_IM2 (18) //!< Bit position for GPT_CR_IM2. +#define BM_GPT_CR_IM2 (0x000c0000) //!< Bit mask for GPT_CR_IM2. + +//! @brief Get value of GPT_CR_IM2 from a register value. +#define BG_GPT_CR_IM2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_IM2) >> BP_GPT_CR_IM2) + +//! @brief Format value for bitfield GPT_CR_IM2. +#define BF_GPT_CR_IM2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_IM2) & BM_GPT_CR_IM2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IM2 field to a new value. +#define BW_GPT_CR_IM2(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_IM2) | BF_GPT_CR_IM2(v))) +#endif +//@} + +/*! @name Register GPT_CR, field OM1[22:20] (RW) + * + * See OM3 + */ +//@{ +#define BP_GPT_CR_OM1 (20) //!< Bit position for GPT_CR_OM1. +#define BM_GPT_CR_OM1 (0x00700000) //!< Bit mask for GPT_CR_OM1. + +//! @brief Get value of GPT_CR_OM1 from a register value. +#define BG_GPT_CR_OM1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_OM1) >> BP_GPT_CR_OM1) + +//! @brief Format value for bitfield GPT_CR_OM1. +#define BF_GPT_CR_OM1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_OM1) & BM_GPT_CR_OM1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OM1 field to a new value. +#define BW_GPT_CR_OM1(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_OM1) | BF_GPT_CR_OM1(v))) +#endif +//@} + +/*! @name Register GPT_CR, field OM2[25:23] (RW) + * + * See OM3 + */ +//@{ +#define BP_GPT_CR_OM2 (23) //!< Bit position for GPT_CR_OM2. +#define BM_GPT_CR_OM2 (0x03800000) //!< Bit mask for GPT_CR_OM2. + +//! @brief Get value of GPT_CR_OM2 from a register value. +#define BG_GPT_CR_OM2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_OM2) >> BP_GPT_CR_OM2) + +//! @brief Format value for bitfield GPT_CR_OM2. +#define BF_GPT_CR_OM2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_OM2) & BM_GPT_CR_OM2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OM2 field to a new value. +#define BW_GPT_CR_OM2(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_OM2) | BF_GPT_CR_OM2(v))) +#endif +//@} + +/*! @name Register GPT_CR, field OM3[28:26] (RW) + * + * OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode. OM2 (bits 25-23) controls + * the Output Compare Channel 2 operating mode. OM1 (bits 22-20) controls the Output Compare Channel + * 1 operating mode. The OM n bits specify the response that a compare event will generate on the + * output pin of Output Compare Channel n . The toggle, clear, and set options cause a change on the + * output pin only if a compare event occurs. When OM n is programmed as 1xx (active low pulse), the + * output pin is set to one immediately on the next input clock; a low pulse (that is an input clock + * in width) occurs when there is a compare event. Note that here, "input clock" refers to the clock + * selected by the CLKSRC bits of the GPT Control Register. + * + * Values: + * - 000 - Output disconnected. No response on pin. + * - 001 - Toggle output pin + * - 010 - Clear output pin + * - 011 - Set output pin + * - 1xx - Generate an active low pulse (that is one input clock wide) on the output pin. + */ +//@{ +#define BP_GPT_CR_OM3 (26) //!< Bit position for GPT_CR_OM3. +#define BM_GPT_CR_OM3 (0x1c000000) //!< Bit mask for GPT_CR_OM3. + +//! @brief Get value of GPT_CR_OM3 from a register value. +#define BG_GPT_CR_OM3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_OM3) >> BP_GPT_CR_OM3) + +//! @brief Format value for bitfield GPT_CR_OM3. +#define BF_GPT_CR_OM3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_OM3) & BM_GPT_CR_OM3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OM3 field to a new value. +#define BW_GPT_CR_OM3(v) (HW_GPT_CR_WR((HW_GPT_CR_RD() & ~BM_GPT_CR_OM3) | BF_GPT_CR_OM3(v))) +#endif +//@} + +/*! @name Register GPT_CR, field FO1[29] (WORZ) + * + * See F03 + */ +//@{ +#define BP_GPT_CR_FO1 (29) //!< Bit position for GPT_CR_FO1. +#define BM_GPT_CR_FO1 (0x20000000) //!< Bit mask for GPT_CR_FO1. + +//! @brief Get value of GPT_CR_FO1 from a register value. +#define BG_GPT_CR_FO1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_FO1) >> BP_GPT_CR_FO1) + +//! @brief Format value for bitfield GPT_CR_FO1. +#define BF_GPT_CR_FO1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_FO1) & BM_GPT_CR_FO1) +//@} + +/*! @name Register GPT_CR, field FO2[30] (WORZ) + * + * See F03 + */ +//@{ +#define BP_GPT_CR_FO2 (30) //!< Bit position for GPT_CR_FO2. +#define BM_GPT_CR_FO2 (0x40000000) //!< Bit mask for GPT_CR_FO2. + +//! @brief Get value of GPT_CR_FO2 from a register value. +#define BG_GPT_CR_FO2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_FO2) >> BP_GPT_CR_FO2) + +//! @brief Format value for bitfield GPT_CR_FO2. +#define BF_GPT_CR_FO2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_FO2) & BM_GPT_CR_FO2) +//@} + +/*! @name Register GPT_CR, field FO3[31] (WORZ) + * + * FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare + * Channel 1 The FO n bit causes the pin action programmed for the timer Output Compare n pin + * (according to the OM n bits in this register). The OF n flag (OF3, OF2, OF1) in the status + * register is not affected . This bit is self-negating and always read as zero. + * + * Values: + * - 0 - Writing a 0 has no effect. + * - 1 - Causes the programmed pin action on the timer Output Compare n pin; the OF n flag is not set. + */ +//@{ +#define BP_GPT_CR_FO3 (31) //!< Bit position for GPT_CR_FO3. +#define BM_GPT_CR_FO3 (0x80000000) //!< Bit mask for GPT_CR_FO3. + +//! @brief Get value of GPT_CR_FO3 from a register value. +#define BG_GPT_CR_FO3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CR_FO3) >> BP_GPT_CR_FO3) + +//! @brief Format value for bitfield GPT_CR_FO3. +#define BF_GPT_CR_FO3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_CR_FO3) & BM_GPT_CR_FO3) +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_PR - GPT Prescaler Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_PR - GPT Prescaler Register (RW) + * + * Reset value: 0x00000000 + * + * The GPT Prescaler Register (GPT_PR) contains bits that determine the divide value of the clock + * that runs the counter. + */ +typedef union _hw_gpt_pr +{ + reg32_t U; + struct _hw_gpt_pr_bitfields + { + unsigned PRESCALER : 12; //!< [11:0] Prescaler bits. + unsigned PRESCALER24M : 4; //!< [15:12] Prescaler bits. + unsigned RESERVED0 : 16; //!< [31:16] Reserved bits. + } B; +} hw_gpt_pr_t; +#endif + +/*! + * @name Constants and macros for entire GPT_PR register + */ +//@{ +#define HW_GPT_PR_ADDR (REGS_GPT_BASE + 0x4) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_PR (*(volatile hw_gpt_pr_t *) HW_GPT_PR_ADDR) +#define HW_GPT_PR_RD() (HW_GPT_PR.U) +#define HW_GPT_PR_WR(v) (HW_GPT_PR.U = (v)) +#define HW_GPT_PR_SET(v) (HW_GPT_PR_WR(HW_GPT_PR_RD() | (v))) +#define HW_GPT_PR_CLR(v) (HW_GPT_PR_WR(HW_GPT_PR_RD() & ~(v))) +#define HW_GPT_PR_TOG(v) (HW_GPT_PR_WR(HW_GPT_PR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual GPT_PR bitfields + */ + +/*! @name Register GPT_PR, field PRESCALER[11:0] (RW) + * + * Prescaler bits. The clock selected by the CLKSRC field is divided by [PRESCALER + 1], and then + * used to run the counter. A change in the value of the PRESCALER bits cause the Prescaler counter + * to reset and a new count period to start immediately. See for the timing diagram. + * + * Values: + * - 0x000 - Divide by 1 + * - ... - ... + * - 0x001 - Divide by 2 + * - 0xFFF - Divide by 4096 + */ +//@{ +#define BP_GPT_PR_PRESCALER (0) //!< Bit position for GPT_PR_PRESCALER. +#define BM_GPT_PR_PRESCALER (0x00000fff) //!< Bit mask for GPT_PR_PRESCALER. + +//! @brief Get value of GPT_PR_PRESCALER from a register value. +#define BG_GPT_PR_PRESCALER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_PR_PRESCALER) >> BP_GPT_PR_PRESCALER) + +//! @brief Format value for bitfield GPT_PR_PRESCALER. +#define BF_GPT_PR_PRESCALER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_PR_PRESCALER) & BM_GPT_PR_PRESCALER) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PRESCALER field to a new value. +#define BW_GPT_PR_PRESCALER(v) (HW_GPT_PR_WR((HW_GPT_PR_RD() & ~BM_GPT_PR_PRESCALER) | BF_GPT_PR_PRESCALER(v))) +#endif +//@} + +/*! @name Register GPT_PR, field PRESCALER24M[15:12] (RW) + * + * Prescaler bits. 24M crystal clock is divided by [PRESCALER24M + 1] before selected by the CLKSRC + * field. If 24M crystal clock is not selected, this feild takes no effect. + * + * Values: + * - 0x0 - Divide by 1 + * - ... - ... + * - 0x1 - Divide by 2 + * - 0xF - Divide by 16 + */ +//@{ +#define BP_GPT_PR_PRESCALER24M (12) //!< Bit position for GPT_PR_PRESCALER24M. +#define BM_GPT_PR_PRESCALER24M (0x0000f000) //!< Bit mask for GPT_PR_PRESCALER24M. + +//! @brief Get value of GPT_PR_PRESCALER24M from a register value. +#define BG_GPT_PR_PRESCALER24M(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_PR_PRESCALER24M) >> BP_GPT_PR_PRESCALER24M) + +//! @brief Format value for bitfield GPT_PR_PRESCALER24M. +#define BF_GPT_PR_PRESCALER24M(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_PR_PRESCALER24M) & BM_GPT_PR_PRESCALER24M) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PRESCALER24M field to a new value. +#define BW_GPT_PR_PRESCALER24M(v) (HW_GPT_PR_WR((HW_GPT_PR_RD() & ~BM_GPT_PR_PRESCALER24M) | BF_GPT_PR_PRESCALER24M(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_SR - GPT Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_SR - GPT Status Register (RW) + * + * Reset value: 0x00000000 + * + * The GPT Status Register (GPT_SR) contains bits that indicate that a counter has rolled over, and + * if any event has occurred on the Input Capture and Output Compare channels. The bits are cleared + * by writing a 1 to them. + */ +typedef union _hw_gpt_sr +{ + reg32_t U; + struct _hw_gpt_sr_bitfields + { + unsigned OF1 : 1; //!< [0] See OF3 + unsigned OF2 : 1; //!< [1] See OF3 + unsigned OF3 : 1; //!< [2] OF3 Output Compare 3 Flag + unsigned IF1 : 1; //!< [3] See IF2 + unsigned IF2 : 1; //!< [4] IF2 Input capture 2 Flag + unsigned ROV : 1; //!< [5] Rollover Flag. + unsigned RESERVED0 : 26; //!< [31:6] Reserved bits. + } B; +} hw_gpt_sr_t; +#endif + +/*! + * @name Constants and macros for entire GPT_SR register + */ +//@{ +#define HW_GPT_SR_ADDR (REGS_GPT_BASE + 0x8) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_SR (*(volatile hw_gpt_sr_t *) HW_GPT_SR_ADDR) +#define HW_GPT_SR_RD() (HW_GPT_SR.U) +#define HW_GPT_SR_WR(v) (HW_GPT_SR.U = (v)) +#define HW_GPT_SR_SET(v) (HW_GPT_SR_WR(HW_GPT_SR_RD() | (v))) +#define HW_GPT_SR_CLR(v) (HW_GPT_SR_WR(HW_GPT_SR_RD() & ~(v))) +#define HW_GPT_SR_TOG(v) (HW_GPT_SR_WR(HW_GPT_SR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual GPT_SR bitfields + */ + +/*! @name Register GPT_SR, field OF1[0] (W1C) + * + * See OF3 + */ +//@{ +#define BP_GPT_SR_OF1 (0) //!< Bit position for GPT_SR_OF1. +#define BM_GPT_SR_OF1 (0x00000001) //!< Bit mask for GPT_SR_OF1. + +//! @brief Get value of GPT_SR_OF1 from a register value. +#define BG_GPT_SR_OF1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_SR_OF1) >> BP_GPT_SR_OF1) + +//! @brief Format value for bitfield GPT_SR_OF1. +#define BF_GPT_SR_OF1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_SR_OF1) & BM_GPT_SR_OF1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OF1 field to a new value. +#define BW_GPT_SR_OF1(v) (HW_GPT_SR_WR((HW_GPT_SR_RD() & ~BM_GPT_SR_OF1) | BF_GPT_SR_OF1(v))) +#endif +//@} + +/*! @name Register GPT_SR, field OF2[1] (W1C) + * + * See OF3 + */ +//@{ +#define BP_GPT_SR_OF2 (1) //!< Bit position for GPT_SR_OF2. +#define BM_GPT_SR_OF2 (0x00000002) //!< Bit mask for GPT_SR_OF2. + +//! @brief Get value of GPT_SR_OF2 from a register value. +#define BG_GPT_SR_OF2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_SR_OF2) >> BP_GPT_SR_OF2) + +//! @brief Format value for bitfield GPT_SR_OF2. +#define BF_GPT_SR_OF2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_SR_OF2) & BM_GPT_SR_OF2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OF2 field to a new value. +#define BW_GPT_SR_OF2(v) (HW_GPT_SR_WR((HW_GPT_SR_RD() & ~BM_GPT_SR_OF2) | BF_GPT_SR_OF2(v))) +#endif +//@} + +/*! @name Register GPT_SR, field OF3[2] (W1C) + * + * OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OF n bit + * indicates that a compare event has occurred on Output Compare channel n . + * + * Values: + * - 0 - Compare event has not occurred. + * - 1 - Compare event has occurred. + */ +//@{ +#define BP_GPT_SR_OF3 (2) //!< Bit position for GPT_SR_OF3. +#define BM_GPT_SR_OF3 (0x00000004) //!< Bit mask for GPT_SR_OF3. + +//! @brief Get value of GPT_SR_OF3 from a register value. +#define BG_GPT_SR_OF3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_SR_OF3) >> BP_GPT_SR_OF3) + +//! @brief Format value for bitfield GPT_SR_OF3. +#define BF_GPT_SR_OF3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_SR_OF3) & BM_GPT_SR_OF3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OF3 field to a new value. +#define BW_GPT_SR_OF3(v) (HW_GPT_SR_WR((HW_GPT_SR_RD() & ~BM_GPT_SR_OF3) | BF_GPT_SR_OF3(v))) +#endif +//@} + +/*! @name Register GPT_SR, field IF1[3] (W1C) + * + * See IF2 + */ +//@{ +#define BP_GPT_SR_IF1 (3) //!< Bit position for GPT_SR_IF1. +#define BM_GPT_SR_IF1 (0x00000008) //!< Bit mask for GPT_SR_IF1. + +//! @brief Get value of GPT_SR_IF1 from a register value. +#define BG_GPT_SR_IF1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_SR_IF1) >> BP_GPT_SR_IF1) + +//! @brief Format value for bitfield GPT_SR_IF1. +#define BF_GPT_SR_IF1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_SR_IF1) & BM_GPT_SR_IF1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IF1 field to a new value. +#define BW_GPT_SR_IF1(v) (HW_GPT_SR_WR((HW_GPT_SR_RD() & ~BM_GPT_SR_IF1) | BF_GPT_SR_IF1(v))) +#endif +//@} + +/*! @name Register GPT_SR, field IF2[4] (W1C) + * + * IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IF n bit indicates that a capture event has + * occurred on Input Capture channel n . + * + * Values: + * - 0 - Capture event has not occurred. + * - 1 - Capture event has occurred. + */ +//@{ +#define BP_GPT_SR_IF2 (4) //!< Bit position for GPT_SR_IF2. +#define BM_GPT_SR_IF2 (0x00000010) //!< Bit mask for GPT_SR_IF2. + +//! @brief Get value of GPT_SR_IF2 from a register value. +#define BG_GPT_SR_IF2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_SR_IF2) >> BP_GPT_SR_IF2) + +//! @brief Format value for bitfield GPT_SR_IF2. +#define BF_GPT_SR_IF2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_SR_IF2) & BM_GPT_SR_IF2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IF2 field to a new value. +#define BW_GPT_SR_IF2(v) (HW_GPT_SR_WR((HW_GPT_SR_RD() & ~BM_GPT_SR_IF2) | BF_GPT_SR_IF2(v))) +#endif +//@} + +/*! @name Register GPT_SR, field ROV[5] (W1C) + * + * Rollover Flag. The ROV bit indicates that the counter has reached its maximum possible value and + * rolled over to 0 (from which the counter continues counting). The ROV bit is only set if the + * counter has reached 0xFFFFFFFF in both Restart and Free-Run modes. + * + * Values: + * - 0 - Rollover has not occurred. + * - 1 - Rollover has occurred. + */ +//@{ +#define BP_GPT_SR_ROV (5) //!< Bit position for GPT_SR_ROV. +#define BM_GPT_SR_ROV (0x00000020) //!< Bit mask for GPT_SR_ROV. + +//! @brief Get value of GPT_SR_ROV from a register value. +#define BG_GPT_SR_ROV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_SR_ROV) >> BP_GPT_SR_ROV) + +//! @brief Format value for bitfield GPT_SR_ROV. +#define BF_GPT_SR_ROV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_SR_ROV) & BM_GPT_SR_ROV) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ROV field to a new value. +#define BW_GPT_SR_ROV(v) (HW_GPT_SR_WR((HW_GPT_SR_RD() & ~BM_GPT_SR_ROV) | BF_GPT_SR_ROV(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_IR - GPT Interrupt Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_IR - GPT Interrupt Register (RW) + * + * Reset value: 0x00000000 + * + * The GPT Interrupt Register (GPT_IR) contains bits that control whether interrupts are generated + * after rollover, input capture and output compare events. + */ +typedef union _hw_gpt_ir +{ + reg32_t U; + struct _hw_gpt_ir_bitfields + { + unsigned OF1IE : 1; //!< [0] See OF3IE + unsigned OF2IE : 1; //!< [1] See OF3IE + unsigned OF3IE : 1; //!< [2] OF3IE Output Compare 3 Interrupt Enable + unsigned IF1IE : 1; //!< [3] See IF2IE + unsigned IF2IE : 1; //!< [4] IF2IE Input capture 2 Interrupt Enable + unsigned ROVIE : 1; //!< [5] Rollover Interrupt Enable. + unsigned RESERVED0 : 26; //!< [31:6] Reserved bits. + } B; +} hw_gpt_ir_t; +#endif + +/*! + * @name Constants and macros for entire GPT_IR register + */ +//@{ +#define HW_GPT_IR_ADDR (REGS_GPT_BASE + 0xc) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_IR (*(volatile hw_gpt_ir_t *) HW_GPT_IR_ADDR) +#define HW_GPT_IR_RD() (HW_GPT_IR.U) +#define HW_GPT_IR_WR(v) (HW_GPT_IR.U = (v)) +#define HW_GPT_IR_SET(v) (HW_GPT_IR_WR(HW_GPT_IR_RD() | (v))) +#define HW_GPT_IR_CLR(v) (HW_GPT_IR_WR(HW_GPT_IR_RD() & ~(v))) +#define HW_GPT_IR_TOG(v) (HW_GPT_IR_WR(HW_GPT_IR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual GPT_IR bitfields + */ + +/*! @name Register GPT_IR, field OF1IE[0] (RW) + * + * See OF3IE + */ +//@{ +#define BP_GPT_IR_OF1IE (0) //!< Bit position for GPT_IR_OF1IE. +#define BM_GPT_IR_OF1IE (0x00000001) //!< Bit mask for GPT_IR_OF1IE. + +//! @brief Get value of GPT_IR_OF1IE from a register value. +#define BG_GPT_IR_OF1IE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_IR_OF1IE) >> BP_GPT_IR_OF1IE) + +//! @brief Format value for bitfield GPT_IR_OF1IE. +#define BF_GPT_IR_OF1IE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_IR_OF1IE) & BM_GPT_IR_OF1IE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OF1IE field to a new value. +#define BW_GPT_IR_OF1IE(v) (HW_GPT_IR_WR((HW_GPT_IR_RD() & ~BM_GPT_IR_OF1IE) | BF_GPT_IR_OF1IE(v))) +#endif +//@} + +/*! @name Register GPT_IR, field OF2IE[1] (RW) + * + * See OF3IE + */ +//@{ +#define BP_GPT_IR_OF2IE (1) //!< Bit position for GPT_IR_OF2IE. +#define BM_GPT_IR_OF2IE (0x00000002) //!< Bit mask for GPT_IR_OF2IE. + +//! @brief Get value of GPT_IR_OF2IE from a register value. +#define BG_GPT_IR_OF2IE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_IR_OF2IE) >> BP_GPT_IR_OF2IE) + +//! @brief Format value for bitfield GPT_IR_OF2IE. +#define BF_GPT_IR_OF2IE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_IR_OF2IE) & BM_GPT_IR_OF2IE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OF2IE field to a new value. +#define BW_GPT_IR_OF2IE(v) (HW_GPT_IR_WR((HW_GPT_IR_RD() & ~BM_GPT_IR_OF2IE) | BF_GPT_IR_OF2IE(v))) +#endif +//@} + +/*! @name Register GPT_IR, field OF3IE[2] (RW) + * + * OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output + * Compare 1 Interrupt Enable The OF n IE bit controls the Output Compare Channel n interrupt. + * + * Values: + * - 0 - Output Compare Channel n interrupt is disabled. + * - 1 - Output Compare Channel n interrupt is enabled. + */ +//@{ +#define BP_GPT_IR_OF3IE (2) //!< Bit position for GPT_IR_OF3IE. +#define BM_GPT_IR_OF3IE (0x00000004) //!< Bit mask for GPT_IR_OF3IE. + +//! @brief Get value of GPT_IR_OF3IE from a register value. +#define BG_GPT_IR_OF3IE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_IR_OF3IE) >> BP_GPT_IR_OF3IE) + +//! @brief Format value for bitfield GPT_IR_OF3IE. +#define BF_GPT_IR_OF3IE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_IR_OF3IE) & BM_GPT_IR_OF3IE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OF3IE field to a new value. +#define BW_GPT_IR_OF3IE(v) (HW_GPT_IR_WR((HW_GPT_IR_RD() & ~BM_GPT_IR_OF3IE) | BF_GPT_IR_OF3IE(v))) +#endif +//@} + +/*! @name Register GPT_IR, field IF1IE[3] (RW) + * + * See IF2IE + */ +//@{ +#define BP_GPT_IR_IF1IE (3) //!< Bit position for GPT_IR_IF1IE. +#define BM_GPT_IR_IF1IE (0x00000008) //!< Bit mask for GPT_IR_IF1IE. + +//! @brief Get value of GPT_IR_IF1IE from a register value. +#define BG_GPT_IR_IF1IE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_IR_IF1IE) >> BP_GPT_IR_IF1IE) + +//! @brief Format value for bitfield GPT_IR_IF1IE. +#define BF_GPT_IR_IF1IE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_IR_IF1IE) & BM_GPT_IR_IF1IE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IF1IE field to a new value. +#define BW_GPT_IR_IF1IE(v) (HW_GPT_IR_WR((HW_GPT_IR_RD() & ~BM_GPT_IR_IF1IE) | BF_GPT_IR_IF1IE(v))) +#endif +//@} + +/*! @name Register GPT_IR, field IF2IE[4] (RW) + * + * IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IF n IE bit + * controls the IF n IE Input Capture n Interrupt Enable. + * + * Values: + * - 0 - IF2IE Input Capture n Interrupt Enable is disabled. + * - 1 - IF2IE Input Capture n Interrupt Enable is enabled. + */ +//@{ +#define BP_GPT_IR_IF2IE (4) //!< Bit position for GPT_IR_IF2IE. +#define BM_GPT_IR_IF2IE (0x00000010) //!< Bit mask for GPT_IR_IF2IE. + +//! @brief Get value of GPT_IR_IF2IE from a register value. +#define BG_GPT_IR_IF2IE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_IR_IF2IE) >> BP_GPT_IR_IF2IE) + +//! @brief Format value for bitfield GPT_IR_IF2IE. +#define BF_GPT_IR_IF2IE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_IR_IF2IE) & BM_GPT_IR_IF2IE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IF2IE field to a new value. +#define BW_GPT_IR_IF2IE(v) (HW_GPT_IR_WR((HW_GPT_IR_RD() & ~BM_GPT_IR_IF2IE) | BF_GPT_IR_IF2IE(v))) +#endif +//@} + +/*! @name Register GPT_IR, field ROVIE[5] (RW) + * + * Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. + * + * Values: + * - 0 - Rollover interrupt is disabled. + * - 1 - Rollover interrupt enabled. + */ +//@{ +#define BP_GPT_IR_ROVIE (5) //!< Bit position for GPT_IR_ROVIE. +#define BM_GPT_IR_ROVIE (0x00000020) //!< Bit mask for GPT_IR_ROVIE. + +//! @brief Get value of GPT_IR_ROVIE from a register value. +#define BG_GPT_IR_ROVIE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_IR_ROVIE) >> BP_GPT_IR_ROVIE) + +//! @brief Format value for bitfield GPT_IR_ROVIE. +#define BF_GPT_IR_ROVIE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_IR_ROVIE) & BM_GPT_IR_ROVIE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ROVIE field to a new value. +#define BW_GPT_IR_ROVIE(v) (HW_GPT_IR_WR((HW_GPT_IR_RD() & ~BM_GPT_IR_ROVIE) | BF_GPT_IR_ROVIE(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_OCR1 - GPT Output Compare Register 1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_OCR1 - GPT Output Compare Register 1 (RW) + * + * Reset value: 0xffffffff + * + * The GPT Compare Register 1 (GPT_OCR1) holds the value that determines when a compare event will + * be generated on Output Compare Channel 1. Any write access to the Compare register of Channel 1 + * while in Restart mode (FRR=0) will reset the GPT counter. An IP Bus Write access to the GPT + * Output Compare Register1 (GPT_OCR1) occurs after one cycle of wait state; an IP Bus Read access + * occurs immediately (0 wait states). + */ +typedef union _hw_gpt_ocr1 +{ + reg32_t U; + struct _hw_gpt_ocr1_bitfields + { + unsigned COMP : 32; //!< [31:0] Compare Value. + } B; +} hw_gpt_ocr1_t; +#endif + +/*! + * @name Constants and macros for entire GPT_OCR1 register + */ +//@{ +#define HW_GPT_OCR1_ADDR (REGS_GPT_BASE + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_OCR1 (*(volatile hw_gpt_ocr1_t *) HW_GPT_OCR1_ADDR) +#define HW_GPT_OCR1_RD() (HW_GPT_OCR1.U) +#define HW_GPT_OCR1_WR(v) (HW_GPT_OCR1.U = (v)) +#define HW_GPT_OCR1_SET(v) (HW_GPT_OCR1_WR(HW_GPT_OCR1_RD() | (v))) +#define HW_GPT_OCR1_CLR(v) (HW_GPT_OCR1_WR(HW_GPT_OCR1_RD() & ~(v))) +#define HW_GPT_OCR1_TOG(v) (HW_GPT_OCR1_WR(HW_GPT_OCR1_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual GPT_OCR1 bitfields + */ + +/*! @name Register GPT_OCR1, field COMP[31:0] (RW) + * + * Compare Value. When the counter value equals the COMP bit field value, a compare event is + * generated on Output Compare Channel 1. + */ +//@{ +#define BP_GPT_OCR1_COMP (0) //!< Bit position for GPT_OCR1_COMP. +#define BM_GPT_OCR1_COMP (0xffffffff) //!< Bit mask for GPT_OCR1_COMP. + +//! @brief Get value of GPT_OCR1_COMP from a register value. +#define BG_GPT_OCR1_COMP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_OCR1_COMP) >> BP_GPT_OCR1_COMP) + +//! @brief Format value for bitfield GPT_OCR1_COMP. +#define BF_GPT_OCR1_COMP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_OCR1_COMP) & BM_GPT_OCR1_COMP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the COMP field to a new value. +#define BW_GPT_OCR1_COMP(v) (HW_GPT_OCR1_WR((HW_GPT_OCR1_RD() & ~BM_GPT_OCR1_COMP) | BF_GPT_OCR1_COMP(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_OCR2 - GPT Output Compare Register 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_OCR2 - GPT Output Compare Register 2 (RW) + * + * Reset value: 0xffffffff + * + * The GPT Compare Register 2 (GPT_OCR2) holds the value that determines when a compare event will + * be generated on Output Compare Channel 2. + */ +typedef union _hw_gpt_ocr2 +{ + reg32_t U; + struct _hw_gpt_ocr2_bitfields + { + unsigned COMP : 32; //!< [31:0] Compare Value. + } B; +} hw_gpt_ocr2_t; +#endif + +/*! + * @name Constants and macros for entire GPT_OCR2 register + */ +//@{ +#define HW_GPT_OCR2_ADDR (REGS_GPT_BASE + 0x14) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_OCR2 (*(volatile hw_gpt_ocr2_t *) HW_GPT_OCR2_ADDR) +#define HW_GPT_OCR2_RD() (HW_GPT_OCR2.U) +#define HW_GPT_OCR2_WR(v) (HW_GPT_OCR2.U = (v)) +#define HW_GPT_OCR2_SET(v) (HW_GPT_OCR2_WR(HW_GPT_OCR2_RD() | (v))) +#define HW_GPT_OCR2_CLR(v) (HW_GPT_OCR2_WR(HW_GPT_OCR2_RD() & ~(v))) +#define HW_GPT_OCR2_TOG(v) (HW_GPT_OCR2_WR(HW_GPT_OCR2_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual GPT_OCR2 bitfields + */ + +/*! @name Register GPT_OCR2, field COMP[31:0] (RW) + * + * Compare Value. When the counter value equals the COMP bit field value, a compare event is + * generated on Output Compare Channel 2. + */ +//@{ +#define BP_GPT_OCR2_COMP (0) //!< Bit position for GPT_OCR2_COMP. +#define BM_GPT_OCR2_COMP (0xffffffff) //!< Bit mask for GPT_OCR2_COMP. + +//! @brief Get value of GPT_OCR2_COMP from a register value. +#define BG_GPT_OCR2_COMP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_OCR2_COMP) >> BP_GPT_OCR2_COMP) + +//! @brief Format value for bitfield GPT_OCR2_COMP. +#define BF_GPT_OCR2_COMP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_OCR2_COMP) & BM_GPT_OCR2_COMP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the COMP field to a new value. +#define BW_GPT_OCR2_COMP(v) (HW_GPT_OCR2_WR((HW_GPT_OCR2_RD() & ~BM_GPT_OCR2_COMP) | BF_GPT_OCR2_COMP(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_OCR3 - GPT Output Compare Register 3 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_OCR3 - GPT Output Compare Register 3 (RW) + * + * Reset value: 0xffffffff + * + * The GPT Compare Register 3 (GPT_OCR3) holds the value that determines when a compare event will + * be generated on Output Compare Channel 3. + */ +typedef union _hw_gpt_ocr3 +{ + reg32_t U; + struct _hw_gpt_ocr3_bitfields + { + unsigned COMP : 32; //!< [31:0] Compare Value. + } B; +} hw_gpt_ocr3_t; +#endif + +/*! + * @name Constants and macros for entire GPT_OCR3 register + */ +//@{ +#define HW_GPT_OCR3_ADDR (REGS_GPT_BASE + 0x18) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_OCR3 (*(volatile hw_gpt_ocr3_t *) HW_GPT_OCR3_ADDR) +#define HW_GPT_OCR3_RD() (HW_GPT_OCR3.U) +#define HW_GPT_OCR3_WR(v) (HW_GPT_OCR3.U = (v)) +#define HW_GPT_OCR3_SET(v) (HW_GPT_OCR3_WR(HW_GPT_OCR3_RD() | (v))) +#define HW_GPT_OCR3_CLR(v) (HW_GPT_OCR3_WR(HW_GPT_OCR3_RD() & ~(v))) +#define HW_GPT_OCR3_TOG(v) (HW_GPT_OCR3_WR(HW_GPT_OCR3_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual GPT_OCR3 bitfields + */ + +/*! @name Register GPT_OCR3, field COMP[31:0] (RW) + * + * Compare Value. When the counter value equals the COMP bit field value, a compare event is + * generated on Output Compare Channel 3. + */ +//@{ +#define BP_GPT_OCR3_COMP (0) //!< Bit position for GPT_OCR3_COMP. +#define BM_GPT_OCR3_COMP (0xffffffff) //!< Bit mask for GPT_OCR3_COMP. + +//! @brief Get value of GPT_OCR3_COMP from a register value. +#define BG_GPT_OCR3_COMP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_OCR3_COMP) >> BP_GPT_OCR3_COMP) + +//! @brief Format value for bitfield GPT_OCR3_COMP. +#define BF_GPT_OCR3_COMP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPT_OCR3_COMP) & BM_GPT_OCR3_COMP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the COMP field to a new value. +#define BW_GPT_OCR3_COMP(v) (HW_GPT_OCR3_WR((HW_GPT_OCR3_RD() & ~BM_GPT_OCR3_COMP) | BF_GPT_OCR3_COMP(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_ICR1 - GPT Input Capture Register 1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_ICR1 - GPT Input Capture Register 1 (RO) + * + * Reset value: 0x00000000 + * + * The GPT Input Capture Register 1 (GPT_ICR1) is a read-only register that holds the value that was + * in the counter during the last capture event on Input Capture Channel 1. + */ +typedef union _hw_gpt_icr1 +{ + reg32_t U; + struct _hw_gpt_icr1_bitfields + { + unsigned CAPT : 32; //!< [31:0] Capture Value. + } B; +} hw_gpt_icr1_t; +#endif + +/*! + * @name Constants and macros for entire GPT_ICR1 register + */ +//@{ +#define HW_GPT_ICR1_ADDR (REGS_GPT_BASE + 0x1c) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_ICR1 (*(volatile hw_gpt_icr1_t *) HW_GPT_ICR1_ADDR) +#define HW_GPT_ICR1_RD() (HW_GPT_ICR1.U) +#endif +//@} + +/* + * constants & macros for individual GPT_ICR1 bitfields + */ + +/*! @name Register GPT_ICR1, field CAPT[31:0] (RO) + * + * Capture Value. After a capture event on Input Capture Channel 1 occurs, the current value of the + * counter is loaded into GPT Input Capture Register 1. + */ +//@{ +#define BP_GPT_ICR1_CAPT (0) //!< Bit position for GPT_ICR1_CAPT. +#define BM_GPT_ICR1_CAPT (0xffffffff) //!< Bit mask for GPT_ICR1_CAPT. + +//! @brief Get value of GPT_ICR1_CAPT from a register value. +#define BG_GPT_ICR1_CAPT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_ICR1_CAPT) >> BP_GPT_ICR1_CAPT) +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_ICR2 - GPT Input Capture Register 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_ICR2 - GPT Input Capture Register 2 (RO) + * + * Reset value: 0x00000000 + * + * The GPT Input capture Register 2 (GPT_ICR2) is a read-only register which holds the value that + * was in the counter during the last capture event on input capture channel 2. + */ +typedef union _hw_gpt_icr2 +{ + reg32_t U; + struct _hw_gpt_icr2_bitfields + { + unsigned CAPT : 32; //!< [31:0] Capture Value. + } B; +} hw_gpt_icr2_t; +#endif + +/*! + * @name Constants and macros for entire GPT_ICR2 register + */ +//@{ +#define HW_GPT_ICR2_ADDR (REGS_GPT_BASE + 0x20) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_ICR2 (*(volatile hw_gpt_icr2_t *) HW_GPT_ICR2_ADDR) +#define HW_GPT_ICR2_RD() (HW_GPT_ICR2.U) +#endif +//@} + +/* + * constants & macros for individual GPT_ICR2 bitfields + */ + +/*! @name Register GPT_ICR2, field CAPT[31:0] (RO) + * + * Capture Value. After a capture event on Input Capture Channel 2 occurs, the current value of the + * counter is loaded into GPT Input Capture Register 2. + */ +//@{ +#define BP_GPT_ICR2_CAPT (0) //!< Bit position for GPT_ICR2_CAPT. +#define BM_GPT_ICR2_CAPT (0xffffffff) //!< Bit mask for GPT_ICR2_CAPT. + +//! @brief Get value of GPT_ICR2_CAPT from a register value. +#define BG_GPT_ICR2_CAPT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_ICR2_CAPT) >> BP_GPT_ICR2_CAPT) +//@} + +//------------------------------------------------------------------------------------------- +// HW_GPT_CNT - GPT Counter Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_GPT_CNT - GPT Counter Register (RO) + * + * Reset value: 0x00000000 + * + * The GPT Counter Register (GPT_CNT) is the main counter's register. GPT_CNT is a read-only + * register and can be read without affecting the counting process of the GPT. + */ +typedef union _hw_gpt_cnt +{ + reg32_t U; + struct _hw_gpt_cnt_bitfields + { + unsigned COUNT : 32; //!< [31:0] Counter Value. + } B; +} hw_gpt_cnt_t; +#endif + +/*! + * @name Constants and macros for entire GPT_CNT register + */ +//@{ +#define HW_GPT_CNT_ADDR (REGS_GPT_BASE + 0x24) + +#ifndef __LANGUAGE_ASM__ +#define HW_GPT_CNT (*(volatile hw_gpt_cnt_t *) HW_GPT_CNT_ADDR) +#define HW_GPT_CNT_RD() (HW_GPT_CNT.U) +#endif +//@} + +/* + * constants & macros for individual GPT_CNT bitfields + */ + +/*! @name Register GPT_CNT, field COUNT[31:0] (RO) + * + * Counter Value. The COUNT bits show the current count value of the GPT counter. + */ +//@{ +#define BP_GPT_CNT_COUNT (0) //!< Bit position for GPT_CNT_COUNT. +#define BM_GPT_CNT_COUNT (0xffffffff) //!< Bit mask for GPT_CNT_COUNT. + +//! @brief Get value of GPT_CNT_COUNT from a register value. +#define BG_GPT_CNT_COUNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPT_CNT_COUNT) >> BP_GPT_CNT_COUNT) +//@} + +//------------------------------------------------------------------------------------------- +// hw_gpt_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All GPT module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_gpt +{ + volatile hw_gpt_cr_t CR; //!< GPT Control Register + volatile hw_gpt_pr_t PR; //!< GPT Prescaler Register + volatile hw_gpt_sr_t SR; //!< GPT Status Register + volatile hw_gpt_ir_t IR; //!< GPT Interrupt Register + volatile hw_gpt_ocr1_t OCR1; //!< GPT Output Compare Register 1 + volatile hw_gpt_ocr2_t OCR2; //!< GPT Output Compare Register 2 + volatile hw_gpt_ocr3_t OCR3; //!< GPT Output Compare Register 3 + volatile hw_gpt_icr1_t ICR1; //!< GPT Input Capture Register 1 + volatile hw_gpt_icr2_t ICR2; //!< GPT Input Capture Register 2 + volatile hw_gpt_cnt_t CNT; //!< GPT Counter Register +} hw_gpt_t; +#pragma pack() + +//! @brief Macro to access all GPT registers. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_GPT. +#define HW_GPT (*(hw_gpt_t *) REGS_GPT_BASE) +#endif + +#endif // __HW_GPT_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsi2c.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsi2c.h new file mode 100644 index 0000000000000000000000000000000000000000..0ab3828248ff4227da5f99cb9edf724a52e9387c --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsi2c.h @@ -0,0 +1,707 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_I2C_REGISTERS_H__ +#define __HW_I2C_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6SDL I2C + * + * I2C + * + * Registers defined in this header file: + * - HW_I2C_IADR - I2C Address Register + * - HW_I2C_IFDR - I2C Frequency Divider Register + * - HW_I2C_I2CR - I2C Control Register + * - HW_I2C_I2SR - I2C Status Register + * - HW_I2C_I2DR - I2C Data I/O Register + * + * - hw_i2c_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_I2C_BASE +#define HW_I2C_INSTANCE_COUNT (4) //!< Number of instances of the I2C module. +#define HW_I2C1 (1) //!< Instance number for I2C1. +#define HW_I2C2 (2) //!< Instance number for I2C2. +#define HW_I2C3 (3) //!< Instance number for I2C3. +#define HW_I2C4 (4) //!< Instance number for I2C4. +#define REGS_I2C1_BASE (0x021a0000) //!< Base address for I2C instance number 1. +#define REGS_I2C2_BASE (0x021a4000) //!< Base address for I2C instance number 2. +#define REGS_I2C3_BASE (0x021a8000) //!< Base address for I2C instance number 3. +#define REGS_I2C4_BASE (0x021f8000) //!< Base address for I2C instance number 4. + +//! @brief Get the base address of I2C by instance number. +//! @param x I2C instance number, from 1 through 4. +#define REGS_I2C_BASE(x) ( (x) == HW_I2C1 ? REGS_I2C1_BASE : (x) == HW_I2C2 ? REGS_I2C2_BASE : (x) == HW_I2C3 ? REGS_I2C3_BASE : (x) == HW_I2C4 ? REGS_I2C4_BASE : 0x00d00000) + +//! @brief Get the instance number given a base address. +//! @param b Base address for an instance of I2C. +#define REGS_I2C_INSTANCE(b) ( (b) == REGS_I2C1_BASE ? HW_I2C1 : (b) == REGS_I2C2_BASE ? HW_I2C2 : (b) == REGS_I2C3_BASE ? HW_I2C3 : (b) == REGS_I2C4_BASE ? HW_I2C4 : 0) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_I2C_IADR - I2C Address Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_I2C_IADR - I2C Address Register (RW) + * + * Reset value: 0x0000 + */ +typedef union _hw_i2c_iadr +{ + reg16_t U; + struct _hw_i2c_iadr_bitfields + { + unsigned short RESERVED0 : 1; //!< [0] Reserved + unsigned short ADR : 7; //!< [7:1] Slave address. + unsigned short RESERVED1 : 8; //!< [15:8] Reserved + } B; +} hw_i2c_iadr_t; +#endif + +/*! + * @name Constants and macros for entire I2C_IADR register + */ +//@{ +#define HW_I2C_IADR_ADDR(x) (REGS_I2C_BASE(x) + 0x0) + +#ifndef __LANGUAGE_ASM__ +#define HW_I2C_IADR(x) (*(volatile hw_i2c_iadr_t *) HW_I2C_IADR_ADDR(x)) +#define HW_I2C_IADR_RD(x) (HW_I2C_IADR(x).U) +#define HW_I2C_IADR_WR(x, v) (HW_I2C_IADR(x).U = (v)) +#define HW_I2C_IADR_SET(x, v) (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) | (v))) +#define HW_I2C_IADR_CLR(x, v) (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) & ~(v))) +#define HW_I2C_IADR_TOG(x, v) (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual I2C_IADR bitfields + */ + +/*! @name Register I2C_IADR, field ADR[7:1] (RW) + * + * Slave address. Contains the specific slave address to be used by the I2C. Slave mode is the + * default I2C mode for an address match on the bus. The I2C_IADR holds the address the I2C responds + * to when addressed as a slave. The slave address is not the address sent on the bus during the + * address transfer. The register is not reset by a software reset. + */ +//@{ +#define BP_I2C_IADR_ADR (1) //!< Bit position for I2C_IADR_ADR. +#define BM_I2C_IADR_ADR (0x000000fe) //!< Bit mask for I2C_IADR_ADR. + +//! @brief Get value of I2C_IADR_ADR from a register value. +#define BG_I2C_IADR_ADR(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_IADR_ADR) >> BP_I2C_IADR_ADR) + +//! @brief Format value for bitfield I2C_IADR_ADR. +#define BF_I2C_IADR_ADR(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_IADR_ADR) & BM_I2C_IADR_ADR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADR field to a new value. +#define BW_I2C_IADR_ADR(x, v) (HW_I2C_IADR_WR(x, (HW_I2C_IADR_RD(x) & ~BM_I2C_IADR_ADR) | BF_I2C_IADR_ADR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_I2C_IFDR - I2C Frequency Divider Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_I2C_IFDR - I2C Frequency Divider Register (RW) + * + * Reset value: 0x0000 + * + * The I2C_IFDR provides a programmable prescaler to configure the clock for bit-rate selection. The + * register does not get reset by software reset. The following table describes the Divider values + * for register field "IC". Table below describes the register values for field "IC". I2C_IFDR + * Register Field Values IC Divider IC Divider IC Divider IC Divider 0x00 30 0x10 288 0x20 22 0x30 + * 160 0x01 32 0x11 320 0x21 24 0x31 192 0x02 36 0x12 384 0x22 26 0x32 224 0x03 42 0x13 480 0x23 28 + * 0x33 256 0x04 48 0x14 576 0x24 32 0x34 320 0x05 52 0x15 640 0x25 36 0x35 384 0x06 60 0x16 768 + * 0x26 40 0x36 448 0x07 72 0x17 960 0x27 44 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88 + * 0x19 1280 0x29 56 0x39 768 0x0A 104 0x1A 1536 0x2A 64 0x3A 896 0x0B 128 0x1B 1920 0x2B 72 0x3B + * 1024 0x0C 144 0x1C 2304 0x2C 80 0x3C 1280 0x0D 160 0x1D 2560 0x2D 96 0x3D 1536 0x0E 192 0x1E 3072 + * 0x2E 112 0x3E 1792 0x0F 240 0x1F 3840 0x2F 128 0x3F 2048 + */ +typedef union _hw_i2c_ifdr +{ + reg16_t U; + struct _hw_i2c_ifdr_bitfields + { + unsigned short IC : 6; //!< [5:0] I2C clock rate. + unsigned short RESERVED0 : 10; //!< [15:6] Reserved + } B; +} hw_i2c_ifdr_t; +#endif + +/*! + * @name Constants and macros for entire I2C_IFDR register + */ +//@{ +#define HW_I2C_IFDR_ADDR(x) (REGS_I2C_BASE(x) + 0x4) + +#ifndef __LANGUAGE_ASM__ +#define HW_I2C_IFDR(x) (*(volatile hw_i2c_ifdr_t *) HW_I2C_IFDR_ADDR(x)) +#define HW_I2C_IFDR_RD(x) (HW_I2C_IFDR(x).U) +#define HW_I2C_IFDR_WR(x, v) (HW_I2C_IFDR(x).U = (v)) +#define HW_I2C_IFDR_SET(x, v) (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) | (v))) +#define HW_I2C_IFDR_CLR(x, v) (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) & ~(v))) +#define HW_I2C_IFDR_TOG(x, v) (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual I2C_IFDR bitfields + */ + +/*! @name Register I2C_IFDR, field IC[5:0] (RW) + * + * I2C clock rate. Pre-scales the clock for bit-rate selection. Due to potentially slow I2Cn_SCL and + * I2Cn_SDA rise and fall times, bus signals are sampled at the prescaler frequency. The serial bit + * clock frequency may be lower than IPG_CLK_ROOT divided by the divider shown in the I2C Data I/O + * Register. The IC value should not be changed during the data transfer, however, it can be changed + * before REPEAT START or START programming sequence in I2C. The I2C protocol supports bit rates up + * to 400 kbps. The IC bits need to be programmed in accordance with this constraint. + */ +//@{ +#define BP_I2C_IFDR_IC (0) //!< Bit position for I2C_IFDR_IC. +#define BM_I2C_IFDR_IC (0x0000003f) //!< Bit mask for I2C_IFDR_IC. + +//! @brief Get value of I2C_IFDR_IC from a register value. +#define BG_I2C_IFDR_IC(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_IFDR_IC) >> BP_I2C_IFDR_IC) + +//! @brief Format value for bitfield I2C_IFDR_IC. +#define BF_I2C_IFDR_IC(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_IFDR_IC) & BM_I2C_IFDR_IC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IC field to a new value. +#define BW_I2C_IFDR_IC(x, v) (HW_I2C_IFDR_WR(x, (HW_I2C_IFDR_RD(x) & ~BM_I2C_IFDR_IC) | BF_I2C_IFDR_IC(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_I2C_I2CR - I2C Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_I2C_I2CR - I2C Control Register (RW) + * + * Reset value: 0x0000 + * + * The I2C_I2CR is used to enable the I2C and the I2C interrupt. It also contains bits that govern + * operation as a slave or a master. + */ +typedef union _hw_i2c_i2cr +{ + reg16_t U; + struct _hw_i2c_i2cr_bitfields + { + unsigned short RESERVED0 : 2; //!< [1:0] Reserved + unsigned short RSTA : 1; //!< [2] Repeat start. + unsigned short TXAK : 1; //!< [3] Transmit acknowledge enable. + unsigned short MTX : 1; //!< [4] Transmit/receive mode select bit. + unsigned short MSTA : 1; //!< [5] Master/slave mode select bit. + unsigned short IIEN : 1; //!< [6] I2C interrupt enable. + unsigned short IEN : 1; //!< [7] I2C enable. + unsigned short RESERVED1 : 8; //!< [15:8] Reserved + } B; +} hw_i2c_i2cr_t; +#endif + +/*! + * @name Constants and macros for entire I2C_I2CR register + */ +//@{ +#define HW_I2C_I2CR_ADDR(x) (REGS_I2C_BASE(x) + 0x8) + +#ifndef __LANGUAGE_ASM__ +#define HW_I2C_I2CR(x) (*(volatile hw_i2c_i2cr_t *) HW_I2C_I2CR_ADDR(x)) +#define HW_I2C_I2CR_RD(x) (HW_I2C_I2CR(x).U) +#define HW_I2C_I2CR_WR(x, v) (HW_I2C_I2CR(x).U = (v)) +#define HW_I2C_I2CR_SET(x, v) (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) | (v))) +#define HW_I2C_I2CR_CLR(x, v) (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) & ~(v))) +#define HW_I2C_I2CR_TOG(x, v) (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual I2C_I2CR bitfields + */ + +/*! @name Register I2C_I2CR, field RSTA[2] (WORZ) + * + * Repeat start. Always reads as 0. Attempting a repeat start without bus mastership causes loss of + * arbitration. + * + * Values: + * - 0 - No repeat start + * - 1 - Generates a repeated START condition + */ +//@{ +#define BP_I2C_I2CR_RSTA (2) //!< Bit position for I2C_I2CR_RSTA. +#define BM_I2C_I2CR_RSTA (0x00000004) //!< Bit mask for I2C_I2CR_RSTA. + +//! @brief Get value of I2C_I2CR_RSTA from a register value. +#define BG_I2C_I2CR_RSTA(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_RSTA) >> BP_I2C_I2CR_RSTA) + +//! @brief Format value for bitfield I2C_I2CR_RSTA. +#define BF_I2C_I2CR_RSTA(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_RSTA) & BM_I2C_I2CR_RSTA) +//@} + +/*! @name Register I2C_I2CR, field TXAK[3] (RW) + * + * Transmit acknowledge enable. Specifies the value driven onto I2Cn_SDA during acknowledge cycles + * for both master and slave receivers. Writing TXAK applies only when the I2C bus is a receiver. + * + * Values: + * - 0 - An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + * - 1 - No acknowledge signal response is sent (that is, the acknowledge bit = 1). + */ +//@{ +#define BP_I2C_I2CR_TXAK (3) //!< Bit position for I2C_I2CR_TXAK. +#define BM_I2C_I2CR_TXAK (0x00000008) //!< Bit mask for I2C_I2CR_TXAK. + +//! @brief Get value of I2C_I2CR_TXAK from a register value. +#define BG_I2C_I2CR_TXAK(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_TXAK) >> BP_I2C_I2CR_TXAK) + +//! @brief Format value for bitfield I2C_I2CR_TXAK. +#define BF_I2C_I2CR_TXAK(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_TXAK) & BM_I2C_I2CR_TXAK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXAK field to a new value. +#define BW_I2C_I2CR_TXAK(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_TXAK) | BF_I2C_I2CR_TXAK(v))) +#endif +//@} + +/*! @name Register I2C_I2CR, field MTX[4] (RW) + * + * Transmit/receive mode select bit. Selects the direction of master and slave transfers. + * + * Values: + * - 0 - Receive. When a slave is addressed, the software should set MTX according to the slave read/write + * bit in the I2C status register (I2C_I2SR[SRW]). + * - 1 - Transmit. In master mode, MTX should be set according to the type of transfer required. Therefore, + * for address cycles, MTX is always 1. + */ +//@{ +#define BP_I2C_I2CR_MTX (4) //!< Bit position for I2C_I2CR_MTX. +#define BM_I2C_I2CR_MTX (0x00000010) //!< Bit mask for I2C_I2CR_MTX. + +//! @brief Get value of I2C_I2CR_MTX from a register value. +#define BG_I2C_I2CR_MTX(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_MTX) >> BP_I2C_I2CR_MTX) + +//! @brief Format value for bitfield I2C_I2CR_MTX. +#define BF_I2C_I2CR_MTX(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_MTX) & BM_I2C_I2CR_MTX) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MTX field to a new value. +#define BW_I2C_I2CR_MTX(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_MTX) | BF_I2C_I2CR_MTX(v))) +#endif +//@} + +/*! @name Register I2C_I2CR, field MSTA[5] (RW) + * + * Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating + * a STOP signal. Module clock should be on for writing to the MSTA bit. The MSTA bit is cleared by + * software to generate a STOP condition; it can also be cleared by hardware when the I2C loses the + * bus arbitration. + * + * Values: + * - 0 - Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode. + * - 1 - Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode. + */ +//@{ +#define BP_I2C_I2CR_MSTA (5) //!< Bit position for I2C_I2CR_MSTA. +#define BM_I2C_I2CR_MSTA (0x00000020) //!< Bit mask for I2C_I2CR_MSTA. + +//! @brief Get value of I2C_I2CR_MSTA from a register value. +#define BG_I2C_I2CR_MSTA(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_MSTA) >> BP_I2C_I2CR_MSTA) + +//! @brief Format value for bitfield I2C_I2CR_MSTA. +#define BF_I2C_I2CR_MSTA(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_MSTA) & BM_I2C_I2CR_MSTA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MSTA field to a new value. +#define BW_I2C_I2CR_MSTA(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_MSTA) | BF_I2C_I2CR_MSTA(v))) +#endif +//@} + +/*! @name Register I2C_I2CR, field IIEN[6] (RW) + * + * I2C interrupt enable. If data is written during the START condition, that is, just after setting + * the I2C_I2CR[MSTA] and I2C_I2CR[MTX] bits, then the ICF bit is cleared at the falling edge of + * SCLK after START. If data is written after the START condition and falling edge of SCLK, then ICF + * bit is cleared as soon as data is written. + * + * Values: + * - 0 - I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an interrupt + * condition occurs. + * - 1 - I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + */ +//@{ +#define BP_I2C_I2CR_IIEN (6) //!< Bit position for I2C_I2CR_IIEN. +#define BM_I2C_I2CR_IIEN (0x00000040) //!< Bit mask for I2C_I2CR_IIEN. + +//! @brief Get value of I2C_I2CR_IIEN from a register value. +#define BG_I2C_I2CR_IIEN(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_IIEN) >> BP_I2C_I2CR_IIEN) + +//! @brief Format value for bitfield I2C_I2CR_IIEN. +#define BF_I2C_I2CR_IIEN(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_IIEN) & BM_I2C_I2CR_IIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IIEN field to a new value. +#define BW_I2C_I2CR_IIEN(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_IIEN) | BF_I2C_I2CR_IIEN(v))) +#endif +//@} + +/*! @name Register I2C_I2CR, field IEN[7] (RW) + * + * I2C enable. Also controls the software reset of the entire I2C. Resetting the bit generates an + * internal reset to the block. If the block is enabled in the middle of a byte transfer, slave mode + * ignores the current bus transfer and starts operating when the next start condition is detected. + * Master mode is not aware that the bus is busy so initiating a start cycle may corrupt the current + * bus cycle, ultimately causing either the current master or the I2C to lose arbitration. After + * which, bus operation returns to normal. + * + * Values: + * - 0 - The block is disabled, but registers can still be accessed. + * - 1 - The I2C is enabled. This bit must be set before any other I2C_I2CR bits have any effect. + */ +//@{ +#define BP_I2C_I2CR_IEN (7) //!< Bit position for I2C_I2CR_IEN. +#define BM_I2C_I2CR_IEN (0x00000080) //!< Bit mask for I2C_I2CR_IEN. + +//! @brief Get value of I2C_I2CR_IEN from a register value. +#define BG_I2C_I2CR_IEN(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_IEN) >> BP_I2C_I2CR_IEN) + +//! @brief Format value for bitfield I2C_I2CR_IEN. +#define BF_I2C_I2CR_IEN(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_IEN) & BM_I2C_I2CR_IEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IEN field to a new value. +#define BW_I2C_I2CR_IEN(x, v) (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_IEN) | BF_I2C_I2CR_IEN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_I2C_I2SR - I2C Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_I2C_I2SR - I2C Status Register (RW) + * + * Reset value: 0x0081 + * + * The I2C_I2SR contains bits that indicate transaction direction and status. + */ +typedef union _hw_i2c_i2sr +{ + reg16_t U; + struct _hw_i2c_i2sr_bitfields + { + unsigned short RXAK : 1; //!< [0] Received acknowledge. + unsigned short IIF : 1; //!< [1] I2C interrupt. + unsigned short SRW : 1; //!< [2] Slave read/write. + unsigned short RESERVED0 : 1; //!< [3] Reserved + unsigned short IAL : 1; //!< [4] Arbitration lost. + unsigned short IBB : 1; //!< [5] I2C bus busy bit. + unsigned short IAAS : 1; //!< [6] I2C addressed as a slave bit. + unsigned short ICF : 1; //!< [7] Data transferring bit. + unsigned short RESERVED1 : 8; //!< [15:8] Reserved + } B; +} hw_i2c_i2sr_t; +#endif + +/*! + * @name Constants and macros for entire I2C_I2SR register + */ +//@{ +#define HW_I2C_I2SR_ADDR(x) (REGS_I2C_BASE(x) + 0xc) + +#ifndef __LANGUAGE_ASM__ +#define HW_I2C_I2SR(x) (*(volatile hw_i2c_i2sr_t *) HW_I2C_I2SR_ADDR(x)) +#define HW_I2C_I2SR_RD(x) (HW_I2C_I2SR(x).U) +#define HW_I2C_I2SR_WR(x, v) (HW_I2C_I2SR(x).U = (v)) +#define HW_I2C_I2SR_SET(x, v) (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) | (v))) +#define HW_I2C_I2SR_CLR(x, v) (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) & ~(v))) +#define HW_I2C_I2SR_TOG(x, v) (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual I2C_I2SR bitfields + */ + +/*! @name Register I2C_I2SR, field RXAK[0] (RO) + * + * Received acknowledge. This is the value received of the I2Cn_SDA input for the acknowledge bit + * during a bus cycle. + * + * Values: + * - 0 - An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + * - 1 - A "No acknowledge" signal was detected at the ninth clock. + */ +//@{ +#define BP_I2C_I2SR_RXAK (0) //!< Bit position for I2C_I2SR_RXAK. +#define BM_I2C_I2SR_RXAK (0x00000001) //!< Bit mask for I2C_I2SR_RXAK. + +//! @brief Get value of I2C_I2SR_RXAK from a register value. +#define BG_I2C_I2SR_RXAK(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_RXAK) >> BP_I2C_I2SR_RXAK) +//@} + +/*! @name Register I2C_I2SR, field IIF[1] (RW) + * + * I2C interrupt. Must be cleared by the software by writing a "0" to it in the interrupt routine. + * The software cannot set the bit. + * + * Values: + * - 0 - No I2C interrupt pending. + * - 1 - An interrupt is pending. This causes a processor interrupt request (if the interrupt enable is + * asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte + * transfer is completed (the interrupt is set at the falling edge of the ninth clock). An + * address is received that matches its own specific address in slave-receive mode. Arbitration + * is lost. + */ +//@{ +#define BP_I2C_I2SR_IIF (1) //!< Bit position for I2C_I2SR_IIF. +#define BM_I2C_I2SR_IIF (0x00000002) //!< Bit mask for I2C_I2SR_IIF. + +//! @brief Get value of I2C_I2SR_IIF from a register value. +#define BG_I2C_I2SR_IIF(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IIF) >> BP_I2C_I2SR_IIF) + +//! @brief Format value for bitfield I2C_I2SR_IIF. +#define BF_I2C_I2SR_IIF(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2SR_IIF) & BM_I2C_I2SR_IIF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IIF field to a new value. +#define BW_I2C_I2SR_IIF(x, v) (HW_I2C_I2SR_WR(x, (HW_I2C_I2SR_RD(x) & ~BM_I2C_I2SR_IIF) | BF_I2C_I2SR_IIF(v))) +#endif +//@} + +/*! @name Register I2C_I2SR, field SRW[2] (RO) + * + * Slave read/write. When the I2C is addressed as a slave, IAAS is set, and the slave read/write bit + * (SRW) indicates the value of the R/W command bit of the calling address sent from the master. SRW + * is valid only when a complete transfer has occurred, no other transfers have been initiated, and + * the I2C is a slave and has an address match. + * + * Values: + * - 0 - Slave receive, master writing to slave + * - 1 - Slave transmit, master reading from slave + */ +//@{ +#define BP_I2C_I2SR_SRW (2) //!< Bit position for I2C_I2SR_SRW. +#define BM_I2C_I2SR_SRW (0x00000004) //!< Bit mask for I2C_I2SR_SRW. + +//! @brief Get value of I2C_I2SR_SRW from a register value. +#define BG_I2C_I2SR_SRW(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_SRW) >> BP_I2C_I2SR_SRW) +//@} + +/*! @name Register I2C_I2SR, field IAL[4] (RW) + * + * Arbitration lost. Set by hardware in the following circumstances (IAL must be cleared by software + * by writing a "0" to it at the start of the interrupt service routine): I2Cn_SDA input sampled low + * when the master drives high during an address or data-transmit cycle. I2Cn_SDA input sampled low + * when the master drives high during the acknowledge bit of a data-receive cycle. For the above two + * cases, the bit is set at the falling edge of 9th I2Cn_SCL clock during the ACK cycle. A start + * cycle is attempted when the bus is busy. A repeated start cycle is requested in slave mode. A + * stop condition is detected when the master did not request it. Software cannot set the bit. + * + * Values: + * - 0 - No arbitration lost. + * - 1 - Arbitration is lost. + */ +//@{ +#define BP_I2C_I2SR_IAL (4) //!< Bit position for I2C_I2SR_IAL. +#define BM_I2C_I2SR_IAL (0x00000010) //!< Bit mask for I2C_I2SR_IAL. + +//! @brief Get value of I2C_I2SR_IAL from a register value. +#define BG_I2C_I2SR_IAL(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IAL) >> BP_I2C_I2SR_IAL) + +//! @brief Format value for bitfield I2C_I2SR_IAL. +#define BF_I2C_I2SR_IAL(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2SR_IAL) & BM_I2C_I2SR_IAL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IAL field to a new value. +#define BW_I2C_I2SR_IAL(x, v) (HW_I2C_I2SR_WR(x, (HW_I2C_I2SR_RD(x) & ~BM_I2C_I2SR_IAL) | BF_I2C_I2SR_IAL(v))) +#endif +//@} + +/*! @name Register I2C_I2SR, field IBB[5] (RO) + * + * I2C bus busy bit. Indicates the status of the bus. When I2C is enabled (I2C_I2CR[IEN] = 1), it + * continuously polls the bus data (SDAK) and clock (SCLK) signals to determine a START or STOP + * condition. + * + * Values: + * - 0 - Bus is idle. If a STOP signal is detected, IBB is cleared. + * - 1 - Bus is busy. When START is detected, IBB is set. + */ +//@{ +#define BP_I2C_I2SR_IBB (5) //!< Bit position for I2C_I2SR_IBB. +#define BM_I2C_I2SR_IBB (0x00000020) //!< Bit mask for I2C_I2SR_IBB. + +//! @brief Get value of I2C_I2SR_IBB from a register value. +#define BG_I2C_I2SR_IBB(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IBB) >> BP_I2C_I2SR_IBB) +//@} + +/*! @name Register I2C_I2SR, field IAAS[6] (RO) + * + * I2C addressed as a slave bit. The ARM platform is interrupted if the interrupt enable + * (I2C_I2CR[IIEN]) is set. The ARM platform must check the slave read/write bit (SRW) and set its + * TX/RX mode accordingly. Writing to I2C_I2CR clears this bit. + * + * Values: + * - 0 - Not addressed + * - 1 - Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + */ +//@{ +#define BP_I2C_I2SR_IAAS (6) //!< Bit position for I2C_I2SR_IAAS. +#define BM_I2C_I2SR_IAAS (0x00000040) //!< Bit mask for I2C_I2SR_IAAS. + +//! @brief Get value of I2C_I2SR_IAAS from a register value. +#define BG_I2C_I2SR_IAAS(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IAAS) >> BP_I2C_I2SR_IAAS) +//@} + +/*! @name Register I2C_I2SR, field ICF[7] (RO) + * + * Data transferring bit. While one byte of data is transferred, ICF is cleared. + * + * Values: + * - 0 - Transfer is in progress. + * - 1 - Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte + * transfer. + */ +//@{ +#define BP_I2C_I2SR_ICF (7) //!< Bit position for I2C_I2SR_ICF. +#define BM_I2C_I2SR_ICF (0x00000080) //!< Bit mask for I2C_I2SR_ICF. + +//! @brief Get value of I2C_I2SR_ICF from a register value. +#define BG_I2C_I2SR_ICF(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_ICF) >> BP_I2C_I2SR_ICF) +//@} + +//------------------------------------------------------------------------------------------- +// HW_I2C_I2DR - I2C Data I/O Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_I2C_I2DR - I2C Data I/O Register (RW) + * + * Reset value: 0x0000 + * + * In master-receive mode, reading the data register allows a read to occur and initiates the next + * byte to be received. In slave mode, the same function is available after it is addressed. + */ +typedef union _hw_i2c_i2dr +{ + reg16_t U; + struct _hw_i2c_i2dr_bitfields + { + unsigned short DATA : 8; //!< [7:0] Data Byte. + unsigned short RESERVED0 : 8; //!< [15:8] Reserved + } B; +} hw_i2c_i2dr_t; +#endif + +/*! + * @name Constants and macros for entire I2C_I2DR register + */ +//@{ +#define HW_I2C_I2DR_ADDR(x) (REGS_I2C_BASE(x) + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_I2C_I2DR(x) (*(volatile hw_i2c_i2dr_t *) HW_I2C_I2DR_ADDR(x)) +#define HW_I2C_I2DR_RD(x) (HW_I2C_I2DR(x).U) +#define HW_I2C_I2DR_WR(x, v) (HW_I2C_I2DR(x).U = (v)) +#define HW_I2C_I2DR_SET(x, v) (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) | (v))) +#define HW_I2C_I2DR_CLR(x, v) (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) & ~(v))) +#define HW_I2C_I2DR_TOG(x, v) (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual I2C_I2DR bitfields + */ + +/*! @name Register I2C_I2DR, field DATA[7:0] (RW) + * + * Data Byte. Holds the last data byte received or the next data byte to be transferred. Software + * writes the next data byte to be transmitted or reads the data byte received. The core-written + * value in I2C_I2DR cannot be read back by the core. Only data written by the I2C bus side can be + * read. + */ +//@{ +#define BP_I2C_I2DR_DATA (0) //!< Bit position for I2C_I2DR_DATA. +#define BM_I2C_I2DR_DATA (0x000000ff) //!< Bit mask for I2C_I2DR_DATA. + +//! @brief Get value of I2C_I2DR_DATA from a register value. +#define BG_I2C_I2DR_DATA(r) ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2DR_DATA) >> BP_I2C_I2DR_DATA) + +//! @brief Format value for bitfield I2C_I2DR_DATA. +#define BF_I2C_I2DR_DATA(v) ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2DR_DATA) & BM_I2C_I2DR_DATA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA field to a new value. +#define BW_I2C_I2DR_DATA(x, v) (HW_I2C_I2DR_WR(x, (HW_I2C_I2DR_RD(x) & ~BM_I2C_I2DR_DATA) | BF_I2C_I2DR_DATA(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// hw_i2c_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All I2C module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_i2c +{ + volatile hw_i2c_iadr_t IADR; //!< I2C Address Register + reg16_t _reserved0; + volatile hw_i2c_ifdr_t IFDR; //!< I2C Frequency Divider Register + reg16_t _reserved1; + volatile hw_i2c_i2cr_t I2CR; //!< I2C Control Register + reg16_t _reserved2; + volatile hw_i2c_i2sr_t I2SR; //!< I2C Status Register + reg16_t _reserved3; + volatile hw_i2c_i2dr_t I2DR; //!< I2C Data I/O Register +} hw_i2c_t; +#pragma pack() + +//! @brief Macro to access all I2C registers. +//! @param x I2C instance number. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_I2C(0). +#define HW_I2C(x) (*(hw_i2c_t *) REGS_I2C_BASE(x)) +#endif + +#endif // __HW_I2C_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsocotp.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsocotp.h new file mode 100644 index 0000000000000000000000000000000000000000..da17cd8672c9c7810467367b9e439b73bbb187d7 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsocotp.h @@ -0,0 +1,9504 @@ +/* + * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. + */ + +#ifndef __HW_OCOTP_REGISTERS_H__ +#define __HW_OCOTP_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL OCOTP registers defined in this header file. + * + * - HW_OCOTP_CTRL - OTP Controller Control Register + * - HW_OCOTP_TIMING - OTP Controller Timing Register + * - HW_OCOTP_DATA - OTP Controller Write Data Register + * - HW_OCOTP_READ_CTRL - OTP Controller Write Data Register + * - HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Data Register + * - HW_OCOTP_SW_STICKY - Sticky bit Register + * - HW_OCOTP_SCS - Software Controllable Signals Register + * - HW_OCOTP_CRC_ADDR - OTP Controller CRC test address + * - HW_OCOTP_CRC_VALUE - OTP Controller CRC Value Register + * - HW_OCOTP_VERSION - OTP Controller Version Register + * - HW_OCOTP_LOCK - Value of OTP Bank0 Word0 (Lock controls) + * - HW_OCOTP_CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + * - HW_OCOTP_CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + * - HW_OCOTP_CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + * - HW_OCOTP_CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + * - HW_OCOTP_CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + * - HW_OCOTP_CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + * - HW_OCOTP_CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + * - HW_OCOTP_MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) + * - HW_OCOTP_MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) + * - HW_OCOTP_MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) + * - HW_OCOTP_MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) + * - HW_OCOTP_MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) + * - HW_OCOTP_ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) + * - HW_OCOTP_ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) + * - HW_OCOTP_ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) + * - HW_OCOTP_OTPMK0 - Shadow Register for OTP Bank2 Word0 (OTPMK and CRYPTO Key) + * - HW_OCOTP_OTPMK1 - Shadow Register for OTP Bank2 Word1 (OTPMK and CRYPTO Key) + * - HW_OCOTP_OTPMK2 - Shadow Register for OTP Bank2 Word2 (OTPMK and CRYPTO Key) + * - HW_OCOTP_OTPMK3 - Shadow Register for OTP Bank2 Word3 (OTPMK and CRYPTO Key) + * - HW_OCOTP_OTPMK4 - Shadow Register for OTP Bank2 Word4 (OTPMK Key) + * - HW_OCOTP_OTPMK5 - Shadow Register for OTP Bank2 Word5 (OTPMK Key) + * - HW_OCOTP_OTPMK6 - Shadow Register for OTP Bank2 Word6 (OTPMK Key) + * - HW_OCOTP_OTPMK7 - Shadow Register for OTP Bank2 Word7 (OTPMK Key) + * - HW_OCOTP_SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) + * - HW_OCOTP_SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) + * - HW_OCOTP_SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) + * - HW_OCOTP_SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) + * - HW_OCOTP_SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) + * - HW_OCOTP_SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) + * - HW_OCOTP_SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) + * - HW_OCOTP_SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) + * - HW_OCOTP_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) + * - HW_OCOTP_HSJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) + * - HW_OCOTP_MAC0 - Value of OTP Bank4 Word2 (MAC Address) + * - HW_OCOTP_MAC1 - Value of OTP Bank4 Word3 (MAC Address) + * - HW_OCOTP_HDCP_KSV0 - Value of OTP Bank4 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KSV1 - Value of OTP Bank4 Word5 (HW Capabilities) + * - HW_OCOTP_GP1 - Value of OTP Bank4 Word6 (HW Capabilities) + * - HW_OCOTP_GP2 - Value of OTP Bank4 Word7 (HW Capabilities) + * - HW_OCOTP_DTCP_KEY0 - Value of OTP Bank5 Word0 (HW Capabilities) + * - HW_OCOTP_DTCP_KEY1 - Value of OTP Bank5 Word1 (HW Capabilities) + * - HW_OCOTP_DTCP_KEY2 - Value of OTP Bank5 Word2 (HW Capabilities) + * - HW_OCOTP_DTCP_KEY3 - Value of OTP Bank5 Word3 (HW Capabilities) + * - HW_OCOTP_DTCP_KEY4 - Value of OTP Bank5 Word4 (HW Capabilities) + * - HW_OCOTP_MISC_CONF - Value of OTP Bank5 Word5 (HW Capabilities) + * - HW_OCOTP_FIELD_RETURN - Value of OTP Bank5 Word6 (HW Capabilities) + * - HW_OCOTP_SRK_REVOKE - Value of OTP Bank5 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY0 - Value of OTP Bank6 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY1 - Value of OTP Bank6 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY2 - Value of OTP Bank6 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY3 - Value of OTP Bank6 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY4 - Value of OTP Bank6 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY5 - Value of OTP Bank6 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY6 - Value of OTP Bank6 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY7 - Value of OTP Bank6 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY8 - Value of OTP Bank7 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY9 - Value of OTP Bank7 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY10 - Value of OTP Bank7 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY11 - Value of OTP Bank7 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY12 - Value of OTP Bank7 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY13 - Value of OTP Bank7 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY14 - Value of OTP Bank7 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY15 - Value of OTP Bank7 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY16 - Value of OTP Bank8 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY17 - Value of OTP Bank8 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY18 - Value of OTP Bank8 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY19 - Value of OTP Bank8 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY20 - Value of OTP Bank8 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY21 - Value of OTP Bank8 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY22 - Value of OTP Bank8 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY23 - Value of OTP Bank8 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY24 - Value of OTP Bank9 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY25 - Value of OTP Bank9 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY26 - Value of OTP Bank9 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY27 - Value of OTP Bank9 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY28 - Value of OTP Bank9 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY29 - Value of OTP Bank9 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY30 - Value of OTP Bank9 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY31 - Value of OTP Bank9 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY32 - Value of OTP Bank10 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY33 - Value of OTP Bank10 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY34 - Value of OTP Bank10 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY35 - Value of OTP Bank10 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY36 - Value of OTP Bank10 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY37 - Value of OTP Bank10 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY38 - Value of OTP Bank10 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY39 - Value of OTP Bank10 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY40 - Value of OTP Bank11 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY41 - Value of OTP Bank11 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY42 - Value of OTP Bank11 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY43 - Value of OTP Bank11 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY44 - Value of OTP Bank11 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY45 - Value of OTP Bank11 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY46 - Value of OTP Bank11 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY47 - Value of OTP Bank11 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY48 - Value of OTP Bank12 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY49 - Value of OTP Bank12 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY50 - Value of OTP Bank12 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY51 - Value of OTP Bank12 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY52 - Value of OTP Bank12 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY53 - Value of OTP Bank12 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY54 - Value of OTP Bank12 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY55 - Value of OTP Bank12 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY56 - Value of OTP Bank13 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY57 - Value of OTP Bank13 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY58 - Value of OTP Bank13 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY59 - Value of OTP Bank13 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY60 - Value of OTP Bank13 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY61 - Value of OTP Bank13 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY62 - Value of OTP Bank13 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY63 - Value of OTP Bank13 Word7 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY64 - Value of OTP Bank14 Word0 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY65 - Value of OTP Bank14 Word1 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY66 - Value of OTP Bank14 Word2 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY67 - Value of OTP Bank14 Word3 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY68 - Value of OTP Bank14 Word4 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY69 - Value of OTP Bank14 Word5 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY70 - Value of OTP Bank14 Word6 (HW Capabilities) + * - HW_OCOTP_HDCP_KEY71 - Value of OTP Bank14 Word7 (HW Capabilities) + * - HW_OCOTP_CRC0 - Value of OTP Bank15 Word0 (HW Capabilities) + * - HW_OCOTP_CRC1 - Value of OTP Bank15 Word1 (HW Capabilities) + * - HW_OCOTP_CRC2 - Value of OTP Bank15 Word2 (HW Capabilities) + * - HW_OCOTP_CRC3 - Value of OTP Bank15 Word3 (HW Capabilities) + * - HW_OCOTP_CRC4 - Value of OTP Bank15 Word4 (HW Capabilities) + * - HW_OCOTP_CRC5 - Value of OTP Bank15 Word5 (HW Capabilities) + * - HW_OCOTP_CRC6 - Value of OTP Bank15 Word6 (HW Capabilities) + * - HW_OCOTP_CRC7 - Value of OTP Bank15 Word5 (HW Capabilities) + * + * - hw_ocotp_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_OCOTP_BASE +#define HW_OCOTP_INSTANCE_COUNT (1) //!< Number of instances of the OCOTP module. +#define REGS_OCOTP_BASE (0x021bc000) //!< Base address for OCOTP. +#endif +//@} + + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CTRL - OTP Controller Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CTRL - OTP Controller Control Register (RW) + * + * Reset value: 0x00000000 + * + * The OCOTP Control and Status Register specifies the copy state, as well as the control required + * for random access of the OTP memory OCOTP_CTRL: 0x000 The OCOTP Control and Status Register + * provides the necessary software interface for performing read and write operations to the On-Chip + * OTP (One-Time Programmable ROM). The control fields such as WR_UNLOCK, ADDR and BUSY/ERROR may be + * used in conjuction with the HW_OCOTP_DATA register to perform write operations. Read operations + * to the On-Chip OTP are involving ADDR, BUSY/ERROR bit field and HW_OCOTP_READ_CTRL register. Read + * value is saved in HW_OCOTP_READ_FUSE_DATA register. EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_ctrl +{ + reg32_t U; + struct _hw_ocotp_ctrl_bitfields + { + unsigned ADDR : 7; //!< [6:0] OTP write and read access address register. + unsigned RESERVED0 : 1; //!< [7] Reserved + unsigned BUSY : 1; //!< [8] OTP controller status bit. + unsigned ERROR : 1; //!< [9] Set by the controller when an access to a locked region(OTP or shadow register) is requested. + unsigned RELOAD_SHADOWS : 1; //!< [10] Set to force re-loading the shadow registers (HW/SW capability and LOCK). + unsigned CRC_TEST : 1; //!< [11] Set to calculate CRC according to start address and end address in CRC_ADDR register.And compare with CRC fuse word according CRC address in CRC_ADDR register to generate CRC_FAIL flag + unsigned CRC_FAIL : 1; //!< [12] Set by controller when calculated CRC value is not equal to appointed CRC fuse word + unsigned RESERVED1 : 3; //!< [15:13] Reserved + unsigned WR_UNLOCK : 16; //!< [31:16] Write 0x3E77 to enable OTP write accesses. + } B; +} hw_ocotp_ctrl_t; +#endif + +/* + * constants & macros for entire OCOTP_CTRL register + */ +#define HW_OCOTP_CTRL_ADDR (REGS_OCOTP_BASE + 0x0) +#define HW_OCOTP_CTRL_SET_ADDR (HW_OCOTP_CTRL_ADDR + 0x4) +#define HW_OCOTP_CTRL_CLR_ADDR (HW_OCOTP_CTRL_ADDR + 0x8) +#define HW_OCOTP_CTRL_TOG_ADDR (HW_OCOTP_CTRL_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CTRL (*(volatile hw_ocotp_ctrl_t *) HW_OCOTP_CTRL_ADDR) +#define HW_OCOTP_CTRL_RD() (HW_OCOTP_CTRL.U) +#define HW_OCOTP_CTRL_WR(v) (HW_OCOTP_CTRL.U = (v)) +#define HW_OCOTP_CTRL_SET(v) ((*(volatile reg32_t *) HW_OCOTP_CTRL_SET_ADDR) = (v)) +#define HW_OCOTP_CTRL_CLR(v) ((*(volatile reg32_t *) HW_OCOTP_CTRL_CLR_ADDR) = (v)) +#define HW_OCOTP_CTRL_TOG(v) ((*(volatile reg32_t *) HW_OCOTP_CTRL_TOG_ADDR) = (v)) +#endif + +/* + * constants & macros for individual OCOTP_CTRL bitfields + */ + +/* --- Register HW_OCOTP_CTRL, field ADDR[6:0] (RW) + * + * OTP write and read access address register. Specifies one of 128 word address locations (0x00 - + * 0x7f). If a valid access is accepted by the controller, the controller makes an internal copy of + * this value. This internal copy will not update until the access is complete. + */ + +#define BP_OCOTP_CTRL_ADDR (0) //!< Bit position for OCOTP_CTRL_ADDR. +#define BM_OCOTP_CTRL_ADDR (0x0000007f) //!< Bit mask for OCOTP_CTRL_ADDR. + +//! @brief Get value of OCOTP_CTRL_ADDR from a register value. +#define BG_OCOTP_CTRL_ADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CTRL_ADDR) >> BP_OCOTP_CTRL_ADDR) + +//! @brief Format value for bitfield OCOTP_CTRL_ADDR. +#define BF_OCOTP_CTRL_ADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CTRL_ADDR) & BM_OCOTP_CTRL_ADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADDR field to a new value. +#define BW_OCOTP_CTRL_ADDR(v) BF_CS1(OCOTP_CTRL, ADDR, v) +#endif + +/* --- Register HW_OCOTP_CTRL, field BUSY[8] (RO) + * + * OTP controller status bit. When active, no new write access or read access to OTP(including + * RELOAD_SHADOWS) can be performed. Cleared by controller when access complete. After reset (or + * after setting RELOAD_SHADOWS), this bit is set by the controller until the HW/SW and LOCK + * registers are successfully copied, after which time it is automatically cleared by the + * controller. + */ + +#define BP_OCOTP_CTRL_BUSY (8) //!< Bit position for OCOTP_CTRL_BUSY. +#define BM_OCOTP_CTRL_BUSY (0x00000100) //!< Bit mask for OCOTP_CTRL_BUSY. + +//! @brief Get value of OCOTP_CTRL_BUSY from a register value. +#define BG_OCOTP_CTRL_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CTRL_BUSY) >> BP_OCOTP_CTRL_BUSY) + +/* --- Register HW_OCOTP_CTRL, field ERROR[9] (RW) + * + * Set by the controller when an access to a locked region(OTP or shadow register) is requested. + * Must be cleared before any further access can be performed. This bit can only be set by the + * controller. This bit is also set if the Pin interface is active and software requests an access + * to the OTP. In this instance, the ERROR bit cannot be cleared until the Pin interface access has + * completed. Reset this bit by writing a one to the SCT clear address space and not by a general + * write. + */ + +#define BP_OCOTP_CTRL_ERROR (9) //!< Bit position for OCOTP_CTRL_ERROR. +#define BM_OCOTP_CTRL_ERROR (0x00000200) //!< Bit mask for OCOTP_CTRL_ERROR. + +//! @brief Get value of OCOTP_CTRL_ERROR from a register value. +#define BG_OCOTP_CTRL_ERROR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CTRL_ERROR) >> BP_OCOTP_CTRL_ERROR) + +//! @brief Format value for bitfield OCOTP_CTRL_ERROR. +#define BF_OCOTP_CTRL_ERROR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CTRL_ERROR) & BM_OCOTP_CTRL_ERROR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ERROR field to a new value. +#define BW_OCOTP_CTRL_ERROR(v) BF_CS1(OCOTP_CTRL, ERROR, v) +#endif + +/* --- Register HW_OCOTP_CTRL, field RELOAD_SHADOWS[10] (RW) + * + * Set to force re-loading the shadow registers (HW/SW capability and LOCK). This operation will + * automatically set BUSY. Once the shadow registers have been re-loaded, BUSY and RELOAD_SHADOWS + * are automatically cleared by the controller. + */ + +#define BP_OCOTP_CTRL_RELOAD_SHADOWS (10) //!< Bit position for OCOTP_CTRL_RELOAD_SHADOWS. +#define BM_OCOTP_CTRL_RELOAD_SHADOWS (0x00000400) //!< Bit mask for OCOTP_CTRL_RELOAD_SHADOWS. + +//! @brief Get value of OCOTP_CTRL_RELOAD_SHADOWS from a register value. +#define BG_OCOTP_CTRL_RELOAD_SHADOWS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CTRL_RELOAD_SHADOWS) >> BP_OCOTP_CTRL_RELOAD_SHADOWS) + +//! @brief Format value for bitfield OCOTP_CTRL_RELOAD_SHADOWS. +#define BF_OCOTP_CTRL_RELOAD_SHADOWS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CTRL_RELOAD_SHADOWS) & BM_OCOTP_CTRL_RELOAD_SHADOWS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RELOAD_SHADOWS field to a new value. +#define BW_OCOTP_CTRL_RELOAD_SHADOWS(v) BF_CS1(OCOTP_CTRL, RELOAD_SHADOWS, v) +#endif + +/* --- Register HW_OCOTP_CTRL, field CRC_TEST[11] (RW) + * + * Set to calculate CRC according to start address and end address in CRC_ADDR register.And compare + * with CRC fuse word according CRC address in CRC_ADDR register to generate CRC_FAIL flag + */ + +#define BP_OCOTP_CTRL_CRC_TEST (11) //!< Bit position for OCOTP_CTRL_CRC_TEST. +#define BM_OCOTP_CTRL_CRC_TEST (0x00000800) //!< Bit mask for OCOTP_CTRL_CRC_TEST. + +//! @brief Get value of OCOTP_CTRL_CRC_TEST from a register value. +#define BG_OCOTP_CTRL_CRC_TEST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CTRL_CRC_TEST) >> BP_OCOTP_CTRL_CRC_TEST) + +//! @brief Format value for bitfield OCOTP_CTRL_CRC_TEST. +#define BF_OCOTP_CTRL_CRC_TEST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CTRL_CRC_TEST) & BM_OCOTP_CTRL_CRC_TEST) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRC_TEST field to a new value. +#define BW_OCOTP_CTRL_CRC_TEST(v) BF_CS1(OCOTP_CTRL, CRC_TEST, v) +#endif + +/* --- Register HW_OCOTP_CTRL, field CRC_FAIL[12] (RW) + * + * Set by controller when calculated CRC value is not equal to appointed CRC fuse word + */ + +#define BP_OCOTP_CTRL_CRC_FAIL (12) //!< Bit position for OCOTP_CTRL_CRC_FAIL. +#define BM_OCOTP_CTRL_CRC_FAIL (0x00001000) //!< Bit mask for OCOTP_CTRL_CRC_FAIL. + +//! @brief Get value of OCOTP_CTRL_CRC_FAIL from a register value. +#define BG_OCOTP_CTRL_CRC_FAIL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CTRL_CRC_FAIL) >> BP_OCOTP_CTRL_CRC_FAIL) + +//! @brief Format value for bitfield OCOTP_CTRL_CRC_FAIL. +#define BF_OCOTP_CTRL_CRC_FAIL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CTRL_CRC_FAIL) & BM_OCOTP_CTRL_CRC_FAIL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRC_FAIL field to a new value. +#define BW_OCOTP_CTRL_CRC_FAIL(v) BF_CS1(OCOTP_CTRL, CRC_FAIL, v) +#endif + +/* --- Register HW_OCOTP_CTRL, field WR_UNLOCK[31:16] (RW) + * + * Write 0x3E77 to enable OTP write accesses. NOTE: This register must be unlocked on a write-by- + * write basis (a write is initiated when HW_OCOTP_DATA is written), so the UNLOCK bitfield must + * contain the correct key value during all writes to HW_OCOTP_DATA, otherwise a write shall not be + * initiated. This field is automatically cleared after a successful write completion (clearing of + * BUSY). + * + * Values: + * KEY = 0x3E77 - Key needed to unlock HW_OCOTP_DATA register. + */ + +#define BP_OCOTP_CTRL_WR_UNLOCK (16) //!< Bit position for OCOTP_CTRL_WR_UNLOCK. +#define BM_OCOTP_CTRL_WR_UNLOCK (0xffff0000) //!< Bit mask for OCOTP_CTRL_WR_UNLOCK. + +//! @brief Get value of OCOTP_CTRL_WR_UNLOCK from a register value. +#define BG_OCOTP_CTRL_WR_UNLOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CTRL_WR_UNLOCK) >> BP_OCOTP_CTRL_WR_UNLOCK) + +//! @brief Format value for bitfield OCOTP_CTRL_WR_UNLOCK. +#define BF_OCOTP_CTRL_WR_UNLOCK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CTRL_WR_UNLOCK) & BM_OCOTP_CTRL_WR_UNLOCK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WR_UNLOCK field to a new value. +#define BW_OCOTP_CTRL_WR_UNLOCK(v) BF_CS1(OCOTP_CTRL, WR_UNLOCK, v) +#endif + +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY (0x3e77) //!< Key needed to unlock HW_OCOTP_DATA register. + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_TIMING - OTP Controller Timing Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_TIMING - OTP Controller Timing Register (RW) + * + * Reset value: 0x01461299 + * + * The OCOTP Data Register is used for OTP Programming This register specifies timing parameters + * for programming and reading the OCOTP fuse array. EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_timing +{ + reg32_t U; + struct _hw_ocotp_timing_bitfields + { + unsigned STROBE_PROG : 12; //!< [11:0] This count value specifies the strobe period in one time write OTP. + unsigned RELAX : 4; //!< [15:12] This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd. + unsigned STROBE_READ : 6; //!< [21:16] This count value specifies the strobe period in one time read OTP. + unsigned WAIT : 6; //!< [27:22] This count value specifies time interval between auto read and write access in one time program. + unsigned RESERVED0 : 4; //!< [31:28] These bits always read back zero. + } B; +} hw_ocotp_timing_t; +#endif + +/* + * constants & macros for entire OCOTP_TIMING register + */ +#define HW_OCOTP_TIMING_ADDR (REGS_OCOTP_BASE + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_TIMING (*(volatile hw_ocotp_timing_t *) HW_OCOTP_TIMING_ADDR) +#define HW_OCOTP_TIMING_RD() (HW_OCOTP_TIMING.U) +#define HW_OCOTP_TIMING_WR(v) (HW_OCOTP_TIMING.U = (v)) +#define HW_OCOTP_TIMING_SET(v) (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() | (v))) +#define HW_OCOTP_TIMING_CLR(v) (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() & ~(v))) +#define HW_OCOTP_TIMING_TOG(v) (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_TIMING bitfields + */ + +/* --- Register HW_OCOTP_TIMING, field STROBE_PROG[11:0] (RW) + * + * This count value specifies the strobe period in one time write OTP. Tpgm = ((STROBE_PROG+1)- + * 2*(RELAX+1)) /ipg_clk_freq. It is given in number of ipg_clk periods. + */ + +#define BP_OCOTP_TIMING_STROBE_PROG (0) //!< Bit position for OCOTP_TIMING_STROBE_PROG. +#define BM_OCOTP_TIMING_STROBE_PROG (0x00000fff) //!< Bit mask for OCOTP_TIMING_STROBE_PROG. + +//! @brief Get value of OCOTP_TIMING_STROBE_PROG from a register value. +#define BG_OCOTP_TIMING_STROBE_PROG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_TIMING_STROBE_PROG) >> BP_OCOTP_TIMING_STROBE_PROG) + +//! @brief Format value for bitfield OCOTP_TIMING_STROBE_PROG. +#define BF_OCOTP_TIMING_STROBE_PROG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_TIMING_STROBE_PROG) & BM_OCOTP_TIMING_STROBE_PROG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STROBE_PROG field to a new value. +#define BW_OCOTP_TIMING_STROBE_PROG(v) (HW_OCOTP_TIMING_WR((HW_OCOTP_TIMING_RD() & ~BM_OCOTP_TIMING_STROBE_PROG) | BF_OCOTP_TIMING_STROBE_PROG(v))) +#endif + +/* --- Register HW_OCOTP_TIMING, field RELAX[15:12] (RW) + * + * This count value specifies the time to add to all default timing parameters other than the Tpgm + * and Trd. It is given in number of ipg_clk periods. + */ + +#define BP_OCOTP_TIMING_RELAX (12) //!< Bit position for OCOTP_TIMING_RELAX. +#define BM_OCOTP_TIMING_RELAX (0x0000f000) //!< Bit mask for OCOTP_TIMING_RELAX. + +//! @brief Get value of OCOTP_TIMING_RELAX from a register value. +#define BG_OCOTP_TIMING_RELAX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_TIMING_RELAX) >> BP_OCOTP_TIMING_RELAX) + +//! @brief Format value for bitfield OCOTP_TIMING_RELAX. +#define BF_OCOTP_TIMING_RELAX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_TIMING_RELAX) & BM_OCOTP_TIMING_RELAX) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RELAX field to a new value. +#define BW_OCOTP_TIMING_RELAX(v) (HW_OCOTP_TIMING_WR((HW_OCOTP_TIMING_RD() & ~BM_OCOTP_TIMING_RELAX) | BF_OCOTP_TIMING_RELAX(v))) +#endif + +/* --- Register HW_OCOTP_TIMING, field STROBE_READ[21:16] (RW) + * + * This count value specifies the strobe period in one time read OTP. Trd = ((STROBE_READ+1)- + * 2*(RELAX+1)) /ipg_clk_freq. It is given in number of ipg_clk periods. + */ + +#define BP_OCOTP_TIMING_STROBE_READ (16) //!< Bit position for OCOTP_TIMING_STROBE_READ. +#define BM_OCOTP_TIMING_STROBE_READ (0x003f0000) //!< Bit mask for OCOTP_TIMING_STROBE_READ. + +//! @brief Get value of OCOTP_TIMING_STROBE_READ from a register value. +#define BG_OCOTP_TIMING_STROBE_READ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_TIMING_STROBE_READ) >> BP_OCOTP_TIMING_STROBE_READ) + +//! @brief Format value for bitfield OCOTP_TIMING_STROBE_READ. +#define BF_OCOTP_TIMING_STROBE_READ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_TIMING_STROBE_READ) & BM_OCOTP_TIMING_STROBE_READ) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STROBE_READ field to a new value. +#define BW_OCOTP_TIMING_STROBE_READ(v) (HW_OCOTP_TIMING_WR((HW_OCOTP_TIMING_RD() & ~BM_OCOTP_TIMING_STROBE_READ) | BF_OCOTP_TIMING_STROBE_READ(v))) +#endif + +/* --- Register HW_OCOTP_TIMING, field WAIT[27:22] (RW) + * + * This count value specifies time interval between auto read and write access in one time program. + * It is given in number of ipg_clk periods. + */ + +#define BP_OCOTP_TIMING_WAIT (22) //!< Bit position for OCOTP_TIMING_WAIT. +#define BM_OCOTP_TIMING_WAIT (0x0fc00000) //!< Bit mask for OCOTP_TIMING_WAIT. + +//! @brief Get value of OCOTP_TIMING_WAIT from a register value. +#define BG_OCOTP_TIMING_WAIT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_TIMING_WAIT) >> BP_OCOTP_TIMING_WAIT) + +//! @brief Format value for bitfield OCOTP_TIMING_WAIT. +#define BF_OCOTP_TIMING_WAIT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_TIMING_WAIT) & BM_OCOTP_TIMING_WAIT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WAIT field to a new value. +#define BW_OCOTP_TIMING_WAIT(v) (HW_OCOTP_TIMING_WR((HW_OCOTP_TIMING_RD() & ~BM_OCOTP_TIMING_WAIT) | BF_OCOTP_TIMING_WAIT(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_DATA - OTP Controller Write Data Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_DATA - OTP Controller Write Data Register (RW) + * + * Reset value: 0x00000000 + * + * The OCOTP Data Register is used for OTP Programming This register is used in conjuction with + * HW_OCOTP_CTRL to perform one-time writes to the OTP. Please see the "Software Write Sequence" + * section for operating details. EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_data +{ + reg32_t U; + struct _hw_ocotp_data_bitfields + { + unsigned DATA : 32; //!< [31:0] Used to initiate a write to OTP. + } B; +} hw_ocotp_data_t; +#endif + +/* + * constants & macros for entire OCOTP_DATA register + */ +#define HW_OCOTP_DATA_ADDR (REGS_OCOTP_BASE + 0x20) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_DATA (*(volatile hw_ocotp_data_t *) HW_OCOTP_DATA_ADDR) +#define HW_OCOTP_DATA_RD() (HW_OCOTP_DATA.U) +#define HW_OCOTP_DATA_WR(v) (HW_OCOTP_DATA.U = (v)) +#define HW_OCOTP_DATA_SET(v) (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() | (v))) +#define HW_OCOTP_DATA_CLR(v) (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() & ~(v))) +#define HW_OCOTP_DATA_TOG(v) (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_DATA bitfields + */ + +/* --- Register HW_OCOTP_DATA, field DATA[31:0] (RW) + * + * Used to initiate a write to OTP. Please see the "Software Write Sequence" section for operating + * details. + */ + +#define BP_OCOTP_DATA_DATA (0) //!< Bit position for OCOTP_DATA_DATA. +#define BM_OCOTP_DATA_DATA (0xffffffff) //!< Bit mask for OCOTP_DATA_DATA. + +//! @brief Get value of OCOTP_DATA_DATA from a register value. +#define BG_OCOTP_DATA_DATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_DATA_DATA) >> BP_OCOTP_DATA_DATA) + +//! @brief Format value for bitfield OCOTP_DATA_DATA. +#define BF_OCOTP_DATA_DATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_DATA_DATA) & BM_OCOTP_DATA_DATA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA field to a new value. +#define BW_OCOTP_DATA_DATA(v) (HW_OCOTP_DATA_WR((HW_OCOTP_DATA_RD() & ~BM_OCOTP_DATA_DATA) | BF_OCOTP_DATA_DATA(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_READ_CTRL - OTP Controller Write Data Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_READ_CTRL - OTP Controller Write Data Register (RW) + * + * Reset value: 0x00000000 + * + * The OCOTP Register is used for OTP Read This register is used in conjuction with HW_OCOTP_CTRL + * to perform one time read to the OTP. Please see the "Software read Sequence" section for + * operating details. EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_read_ctrl +{ + reg32_t U; + struct _hw_ocotp_read_ctrl_bitfields + { + unsigned READ_FUSE : 1; //!< [0] Used to initiate a read to OTP. + unsigned RESERVED0 : 31; //!< [31:1] Reserved + } B; +} hw_ocotp_read_ctrl_t; +#endif + +/* + * constants & macros for entire OCOTP_READ_CTRL register + */ +#define HW_OCOTP_READ_CTRL_ADDR (REGS_OCOTP_BASE + 0x30) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_READ_CTRL (*(volatile hw_ocotp_read_ctrl_t *) HW_OCOTP_READ_CTRL_ADDR) +#define HW_OCOTP_READ_CTRL_RD() (HW_OCOTP_READ_CTRL.U) +#define HW_OCOTP_READ_CTRL_WR(v) (HW_OCOTP_READ_CTRL.U = (v)) +#define HW_OCOTP_READ_CTRL_SET(v) (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() | (v))) +#define HW_OCOTP_READ_CTRL_CLR(v) (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() & ~(v))) +#define HW_OCOTP_READ_CTRL_TOG(v) (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_READ_CTRL bitfields + */ + +/* --- Register HW_OCOTP_READ_CTRL, field READ_FUSE[0] (RW) + * + * Used to initiate a read to OTP. Please see the "Software read Sequence" section for operating + * details. + */ + +#define BP_OCOTP_READ_CTRL_READ_FUSE (0) //!< Bit position for OCOTP_READ_CTRL_READ_FUSE. +#define BM_OCOTP_READ_CTRL_READ_FUSE (0x00000001) //!< Bit mask for OCOTP_READ_CTRL_READ_FUSE. + +//! @brief Get value of OCOTP_READ_CTRL_READ_FUSE from a register value. +#define BG_OCOTP_READ_CTRL_READ_FUSE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_READ_CTRL_READ_FUSE) >> BP_OCOTP_READ_CTRL_READ_FUSE) + +//! @brief Format value for bitfield OCOTP_READ_CTRL_READ_FUSE. +#define BF_OCOTP_READ_CTRL_READ_FUSE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_READ_CTRL_READ_FUSE) & BM_OCOTP_READ_CTRL_READ_FUSE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the READ_FUSE field to a new value. +#define BW_OCOTP_READ_CTRL_READ_FUSE(v) (HW_OCOTP_READ_CTRL_WR((HW_OCOTP_READ_CTRL_RD() & ~BM_OCOTP_READ_CTRL_READ_FUSE) | BF_OCOTP_READ_CTRL_READ_FUSE(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Data Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Data Register (RW) + * + * Reset value: 0x00000000 + * + * The OCOTP Data Register is used for OTP Read The data read from OTP EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_read_fuse_data +{ + reg32_t U; + struct _hw_ocotp_read_fuse_data_bitfields + { + unsigned DATA : 32; //!< [31:0] The data read from OTP + } B; +} hw_ocotp_read_fuse_data_t; +#endif + +/* + * constants & macros for entire OCOTP_READ_FUSE_DATA register + */ +#define HW_OCOTP_READ_FUSE_DATA_ADDR (REGS_OCOTP_BASE + 0x40) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_READ_FUSE_DATA (*(volatile hw_ocotp_read_fuse_data_t *) HW_OCOTP_READ_FUSE_DATA_ADDR) +#define HW_OCOTP_READ_FUSE_DATA_RD() (HW_OCOTP_READ_FUSE_DATA.U) +#define HW_OCOTP_READ_FUSE_DATA_WR(v) (HW_OCOTP_READ_FUSE_DATA.U = (v)) +#define HW_OCOTP_READ_FUSE_DATA_SET(v) (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() | (v))) +#define HW_OCOTP_READ_FUSE_DATA_CLR(v) (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() & ~(v))) +#define HW_OCOTP_READ_FUSE_DATA_TOG(v) (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_READ_FUSE_DATA bitfields + */ + +/* --- Register HW_OCOTP_READ_FUSE_DATA, field DATA[31:0] (RW) + * + * The data read from OTP + */ + +#define BP_OCOTP_READ_FUSE_DATA_DATA (0) //!< Bit position for OCOTP_READ_FUSE_DATA_DATA. +#define BM_OCOTP_READ_FUSE_DATA_DATA (0xffffffff) //!< Bit mask for OCOTP_READ_FUSE_DATA_DATA. + +//! @brief Get value of OCOTP_READ_FUSE_DATA_DATA from a register value. +#define BG_OCOTP_READ_FUSE_DATA_DATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_READ_FUSE_DATA_DATA) >> BP_OCOTP_READ_FUSE_DATA_DATA) + +//! @brief Format value for bitfield OCOTP_READ_FUSE_DATA_DATA. +#define BF_OCOTP_READ_FUSE_DATA_DATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_READ_FUSE_DATA_DATA) & BM_OCOTP_READ_FUSE_DATA_DATA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA field to a new value. +#define BW_OCOTP_READ_FUSE_DATA_DATA(v) (HW_OCOTP_READ_FUSE_DATA_WR((HW_OCOTP_READ_FUSE_DATA_RD() & ~BM_OCOTP_READ_FUSE_DATA_DATA) | BF_OCOTP_READ_FUSE_DATA_DATA(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SW_STICKY - Sticky bit Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SW_STICKY - Sticky bit Register (RW) + * + * Reset value: 0x00000000 + * + * Some SW sticky bits . Some sticky bits are used by SW to lock some fuse area , shadow registers + * and other features. EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_sw_sticky +{ + reg32_t U; + struct _hw_ocotp_sw_sticky_bitfields + { + unsigned RESERVED0 : 1; //!< [0] Reserved. + unsigned SRK_REVOKE_LOCK : 1; //!< [1] Shadow register write and OTP write lock for SRK_REVOKE region. + unsigned FIELD_RETURN_LOCK : 1; //!< [2] Shadow register write and OTP write lock for FIELD_RETURN region. + unsigned RESERVED1 : 29; //!< [31:3] Reserved + } B; +} hw_ocotp_sw_sticky_t; +#endif + +/* + * constants & macros for entire OCOTP_SW_STICKY register + */ +#define HW_OCOTP_SW_STICKY_ADDR (REGS_OCOTP_BASE + 0x50) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SW_STICKY (*(volatile hw_ocotp_sw_sticky_t *) HW_OCOTP_SW_STICKY_ADDR) +#define HW_OCOTP_SW_STICKY_RD() (HW_OCOTP_SW_STICKY.U) +#define HW_OCOTP_SW_STICKY_WR(v) (HW_OCOTP_SW_STICKY.U = (v)) +#define HW_OCOTP_SW_STICKY_SET(v) (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() | (v))) +#define HW_OCOTP_SW_STICKY_CLR(v) (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() & ~(v))) +#define HW_OCOTP_SW_STICKY_TOG(v) (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SW_STICKY bitfields + */ + +/* --- Register HW_OCOTP_SW_STICKY, field SRK_REVOKE_LOCK[1] (RW) + * + * Shadow register write and OTP write lock for SRK_REVOKE region. When set, the writing of this + * region's shadow register and OTP fuse word are blocked. Once this bit is set, it is always high + * unless a POR is issued. + */ + +#define BP_OCOTP_SW_STICKY_SRK_REVOKE_LOCK (1) //!< Bit position for OCOTP_SW_STICKY_SRK_REVOKE_LOCK. +#define BM_OCOTP_SW_STICKY_SRK_REVOKE_LOCK (0x00000002) //!< Bit mask for OCOTP_SW_STICKY_SRK_REVOKE_LOCK. + +//! @brief Get value of OCOTP_SW_STICKY_SRK_REVOKE_LOCK from a register value. +#define BG_OCOTP_SW_STICKY_SRK_REVOKE_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SW_STICKY_SRK_REVOKE_LOCK) >> BP_OCOTP_SW_STICKY_SRK_REVOKE_LOCK) + +//! @brief Format value for bitfield OCOTP_SW_STICKY_SRK_REVOKE_LOCK. +#define BF_OCOTP_SW_STICKY_SRK_REVOKE_LOCK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SW_STICKY_SRK_REVOKE_LOCK) & BM_OCOTP_SW_STICKY_SRK_REVOKE_LOCK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SRK_REVOKE_LOCK field to a new value. +#define BW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK(v) (HW_OCOTP_SW_STICKY_WR((HW_OCOTP_SW_STICKY_RD() & ~BM_OCOTP_SW_STICKY_SRK_REVOKE_LOCK) | BF_OCOTP_SW_STICKY_SRK_REVOKE_LOCK(v))) +#endif + +/* --- Register HW_OCOTP_SW_STICKY, field FIELD_RETURN_LOCK[2] (RW) + * + * Shadow register write and OTP write lock for FIELD_RETURN region. When set, the writing of this + * region's shadow register and OTP fuse word are blocked.Once this bit is set, it is always high + * unless a POR is issued. + */ + +#define BP_OCOTP_SW_STICKY_FIELD_RETURN_LOCK (2) //!< Bit position for OCOTP_SW_STICKY_FIELD_RETURN_LOCK. +#define BM_OCOTP_SW_STICKY_FIELD_RETURN_LOCK (0x00000004) //!< Bit mask for OCOTP_SW_STICKY_FIELD_RETURN_LOCK. + +//! @brief Get value of OCOTP_SW_STICKY_FIELD_RETURN_LOCK from a register value. +#define BG_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SW_STICKY_FIELD_RETURN_LOCK) >> BP_OCOTP_SW_STICKY_FIELD_RETURN_LOCK) + +//! @brief Format value for bitfield OCOTP_SW_STICKY_FIELD_RETURN_LOCK. +#define BF_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SW_STICKY_FIELD_RETURN_LOCK) & BM_OCOTP_SW_STICKY_FIELD_RETURN_LOCK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FIELD_RETURN_LOCK field to a new value. +#define BW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(v) (HW_OCOTP_SW_STICKY_WR((HW_OCOTP_SW_STICKY_RD() & ~BM_OCOTP_SW_STICKY_FIELD_RETURN_LOCK) | BF_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SCS - Software Controllable Signals Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SCS - Software Controllable Signals Register (RW) + * + * Reset value: 0x00000000 + * + * HW_OCOTP_SCS: 0x060 This register holds volatile configuration values that can be set and locked + * by trusted software. All values are returned to their defualt values after POR. EXAMPLE Empty + * Example. + */ +typedef union _hw_ocotp_scs +{ + reg32_t U; + struct _hw_ocotp_scs_bitfields + { + unsigned HAB_JDE : 1; //!< [0] HAB JTAG Debug Enable. + unsigned SPARE : 30; //!< [30:1] Unallocated read/write bits for implementation specific software use. + unsigned LOCK : 1; //!< [31] When set, all of the bits in this register are locked and can not be changed through SW programming. + } B; +} hw_ocotp_scs_t; +#endif + +/* + * constants & macros for entire OCOTP_SCS register + */ +#define HW_OCOTP_SCS_ADDR (REGS_OCOTP_BASE + 0x60) +#define HW_OCOTP_SCS_SET_ADDR (HW_OCOTP_SCS_ADDR + 0x4) +#define HW_OCOTP_SCS_CLR_ADDR (HW_OCOTP_SCS_ADDR + 0x8) +#define HW_OCOTP_SCS_TOG_ADDR (HW_OCOTP_SCS_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SCS (*(volatile hw_ocotp_scs_t *) HW_OCOTP_SCS_ADDR) +#define HW_OCOTP_SCS_RD() (HW_OCOTP_SCS.U) +#define HW_OCOTP_SCS_WR(v) (HW_OCOTP_SCS.U = (v)) +#define HW_OCOTP_SCS_SET(v) ((*(volatile reg32_t *) HW_OCOTP_SCS_SET_ADDR) = (v)) +#define HW_OCOTP_SCS_CLR(v) ((*(volatile reg32_t *) HW_OCOTP_SCS_CLR_ADDR) = (v)) +#define HW_OCOTP_SCS_TOG(v) ((*(volatile reg32_t *) HW_OCOTP_SCS_TOG_ADDR) = (v)) +#endif + +/* + * constants & macros for individual OCOTP_SCS bitfields + */ + +/* --- Register HW_OCOTP_SCS, field HAB_JDE[0] (RW) + * + * HAB JTAG Debug Enable. This bit is used by the HAB to enable JTAG debugging, assuming that a + * properlay signed command to do so is found and validated by the HAB. The HAB must lock the + * register before passing control to the OS whether or not JTAG debugging has been enabled. Once + * JTAG is enabled by this bit, it can not be disabled unless the system is reset by POR. 0: JTAG + * debugging is not enabled by the HAB (it may still be enabled by other mechanisms). 1: JTAG + * debugging is enabled by the HAB (though this signal may be gated off). + * + * Values: + * 1 - JTAG debugging is enabled by the HAB (though this signal may be gated off) + */ + +#define BP_OCOTP_SCS_HAB_JDE (0) //!< Bit position for OCOTP_SCS_HAB_JDE. +#define BM_OCOTP_SCS_HAB_JDE (0x00000001) //!< Bit mask for OCOTP_SCS_HAB_JDE. + +//! @brief Get value of OCOTP_SCS_HAB_JDE from a register value. +#define BG_OCOTP_SCS_HAB_JDE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SCS_HAB_JDE) >> BP_OCOTP_SCS_HAB_JDE) + +//! @brief Format value for bitfield OCOTP_SCS_HAB_JDE. +#define BF_OCOTP_SCS_HAB_JDE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SCS_HAB_JDE) & BM_OCOTP_SCS_HAB_JDE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HAB_JDE field to a new value. +#define BW_OCOTP_SCS_HAB_JDE(v) BF_CS1(OCOTP_SCS, HAB_JDE, v) +#endif + + +/* --- Register HW_OCOTP_SCS, field SPARE[30:1] (RW) + * + * Unallocated read/write bits for implementation specific software use. + */ + +#define BP_OCOTP_SCS_SPARE (1) //!< Bit position for OCOTP_SCS_SPARE. +#define BM_OCOTP_SCS_SPARE (0x7ffffffe) //!< Bit mask for OCOTP_SCS_SPARE. + +//! @brief Get value of OCOTP_SCS_SPARE from a register value. +#define BG_OCOTP_SCS_SPARE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SCS_SPARE) >> BP_OCOTP_SCS_SPARE) + +//! @brief Format value for bitfield OCOTP_SCS_SPARE. +#define BF_OCOTP_SCS_SPARE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SCS_SPARE) & BM_OCOTP_SCS_SPARE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SPARE field to a new value. +#define BW_OCOTP_SCS_SPARE(v) BF_CS1(OCOTP_SCS, SPARE, v) +#endif + +/* --- Register HW_OCOTP_SCS, field LOCK[31] (RW) + * + * When set, all of the bits in this register are locked and can not be changed through SW + * programming. This bit is only reset after a POR is issued. + */ + +#define BP_OCOTP_SCS_LOCK (31) //!< Bit position for OCOTP_SCS_LOCK. +#define BM_OCOTP_SCS_LOCK (0x80000000) //!< Bit mask for OCOTP_SCS_LOCK. + +//! @brief Get value of OCOTP_SCS_LOCK from a register value. +#define BG_OCOTP_SCS_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SCS_LOCK) >> BP_OCOTP_SCS_LOCK) + +//! @brief Format value for bitfield OCOTP_SCS_LOCK. +#define BF_OCOTP_SCS_LOCK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SCS_LOCK) & BM_OCOTP_SCS_LOCK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LOCK field to a new value. +#define BW_OCOTP_SCS_LOCK(v) BF_CS1(OCOTP_SCS, LOCK, v) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC_ADDR - OTP Controller CRC test address +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC_ADDR - OTP Controller CRC test address (RW) + * + * Reset value: 0x00000000 + * + * The OCOTP Data Register is used for OTP Read The address for CRC calculation EXAMPLE Empty + * Example. + */ +typedef union _hw_ocotp_crc_addr +{ + reg32_t U; + struct _hw_ocotp_crc_addr_bitfields + { + unsigned DATA_START_ADDR : 8; //!< [7:0] End address of fuse location for CRC calculation + unsigned DATA_END_ADDR : 8; //!< [15:8] Start address of fuse location for CRC calculation + unsigned CRC_ADDR : 3; //!< [18:16] Address of 32-bit CRC result for comparing + unsigned RESERVED0 : 13; //!< [31:19] Reserved + } B; +} hw_ocotp_crc_addr_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC_ADDR register + */ +#define HW_OCOTP_CRC_ADDR_ADDR (REGS_OCOTP_BASE + 0x70) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC_ADDR (*(volatile hw_ocotp_crc_addr_t *) HW_OCOTP_CRC_ADDR_ADDR) +#define HW_OCOTP_CRC_ADDR_RD() (HW_OCOTP_CRC_ADDR.U) +#define HW_OCOTP_CRC_ADDR_WR(v) (HW_OCOTP_CRC_ADDR.U = (v)) +#define HW_OCOTP_CRC_ADDR_SET(v) (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() | (v))) +#define HW_OCOTP_CRC_ADDR_CLR(v) (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() & ~(v))) +#define HW_OCOTP_CRC_ADDR_TOG(v) (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC_ADDR bitfields + */ + +/* --- Register HW_OCOTP_CRC_ADDR, field DATA_START_ADDR[7:0] (RW) + * + * End address of fuse location for CRC calculation + */ + +#define BP_OCOTP_CRC_ADDR_DATA_START_ADDR (0) //!< Bit position for OCOTP_CRC_ADDR_DATA_START_ADDR. +#define BM_OCOTP_CRC_ADDR_DATA_START_ADDR (0x000000ff) //!< Bit mask for OCOTP_CRC_ADDR_DATA_START_ADDR. + +//! @brief Get value of OCOTP_CRC_ADDR_DATA_START_ADDR from a register value. +#define BG_OCOTP_CRC_ADDR_DATA_START_ADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC_ADDR_DATA_START_ADDR) >> BP_OCOTP_CRC_ADDR_DATA_START_ADDR) + +//! @brief Format value for bitfield OCOTP_CRC_ADDR_DATA_START_ADDR. +#define BF_OCOTP_CRC_ADDR_DATA_START_ADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC_ADDR_DATA_START_ADDR) & BM_OCOTP_CRC_ADDR_DATA_START_ADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA_START_ADDR field to a new value. +#define BW_OCOTP_CRC_ADDR_DATA_START_ADDR(v) (HW_OCOTP_CRC_ADDR_WR((HW_OCOTP_CRC_ADDR_RD() & ~BM_OCOTP_CRC_ADDR_DATA_START_ADDR) | BF_OCOTP_CRC_ADDR_DATA_START_ADDR(v))) +#endif + +/* --- Register HW_OCOTP_CRC_ADDR, field DATA_END_ADDR[15:8] (RW) + * + * Start address of fuse location for CRC calculation + */ + +#define BP_OCOTP_CRC_ADDR_DATA_END_ADDR (8) //!< Bit position for OCOTP_CRC_ADDR_DATA_END_ADDR. +#define BM_OCOTP_CRC_ADDR_DATA_END_ADDR (0x0000ff00) //!< Bit mask for OCOTP_CRC_ADDR_DATA_END_ADDR. + +//! @brief Get value of OCOTP_CRC_ADDR_DATA_END_ADDR from a register value. +#define BG_OCOTP_CRC_ADDR_DATA_END_ADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC_ADDR_DATA_END_ADDR) >> BP_OCOTP_CRC_ADDR_DATA_END_ADDR) + +//! @brief Format value for bitfield OCOTP_CRC_ADDR_DATA_END_ADDR. +#define BF_OCOTP_CRC_ADDR_DATA_END_ADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC_ADDR_DATA_END_ADDR) & BM_OCOTP_CRC_ADDR_DATA_END_ADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA_END_ADDR field to a new value. +#define BW_OCOTP_CRC_ADDR_DATA_END_ADDR(v) (HW_OCOTP_CRC_ADDR_WR((HW_OCOTP_CRC_ADDR_RD() & ~BM_OCOTP_CRC_ADDR_DATA_END_ADDR) | BF_OCOTP_CRC_ADDR_DATA_END_ADDR(v))) +#endif + +/* --- Register HW_OCOTP_CRC_ADDR, field CRC_ADDR[18:16] (RW) + * + * Address of 32-bit CRC result for comparing + */ + +#define BP_OCOTP_CRC_ADDR_CRC_ADDR (16) //!< Bit position for OCOTP_CRC_ADDR_CRC_ADDR. +#define BM_OCOTP_CRC_ADDR_CRC_ADDR (0x00070000) //!< Bit mask for OCOTP_CRC_ADDR_CRC_ADDR. + +//! @brief Get value of OCOTP_CRC_ADDR_CRC_ADDR from a register value. +#define BG_OCOTP_CRC_ADDR_CRC_ADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC_ADDR_CRC_ADDR) >> BP_OCOTP_CRC_ADDR_CRC_ADDR) + +//! @brief Format value for bitfield OCOTP_CRC_ADDR_CRC_ADDR. +#define BF_OCOTP_CRC_ADDR_CRC_ADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC_ADDR_CRC_ADDR) & BM_OCOTP_CRC_ADDR_CRC_ADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRC_ADDR field to a new value. +#define BW_OCOTP_CRC_ADDR_CRC_ADDR(v) (HW_OCOTP_CRC_ADDR_WR((HW_OCOTP_CRC_ADDR_RD() & ~BM_OCOTP_CRC_ADDR_CRC_ADDR) | BF_OCOTP_CRC_ADDR_CRC_ADDR(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC_VALUE - OTP Controller CRC Value Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC_VALUE - OTP Controller CRC Value Register (RW) + * + * Reset value: 0x00000000 + * + * The OCOTP Data Register is used for OTP Read The crc32 value based on CRC_ADDR EXAMPLE Empty + * Example. + */ +typedef union _hw_ocotp_crc_value +{ + reg32_t U; + struct _hw_ocotp_crc_value_bitfields + { + unsigned DATA : 32; //!< [31:0] The crc32 value based on CRC_ADDR + } B; +} hw_ocotp_crc_value_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC_VALUE register + */ +#define HW_OCOTP_CRC_VALUE_ADDR (REGS_OCOTP_BASE + 0x80) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC_VALUE (*(volatile hw_ocotp_crc_value_t *) HW_OCOTP_CRC_VALUE_ADDR) +#define HW_OCOTP_CRC_VALUE_RD() (HW_OCOTP_CRC_VALUE.U) +#define HW_OCOTP_CRC_VALUE_WR(v) (HW_OCOTP_CRC_VALUE.U = (v)) +#define HW_OCOTP_CRC_VALUE_SET(v) (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() | (v))) +#define HW_OCOTP_CRC_VALUE_CLR(v) (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() & ~(v))) +#define HW_OCOTP_CRC_VALUE_TOG(v) (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC_VALUE bitfields + */ + +/* --- Register HW_OCOTP_CRC_VALUE, field DATA[31:0] (RW) + * + * The crc32 value based on CRC_ADDR + */ + +#define BP_OCOTP_CRC_VALUE_DATA (0) //!< Bit position for OCOTP_CRC_VALUE_DATA. +#define BM_OCOTP_CRC_VALUE_DATA (0xffffffff) //!< Bit mask for OCOTP_CRC_VALUE_DATA. + +//! @brief Get value of OCOTP_CRC_VALUE_DATA from a register value. +#define BG_OCOTP_CRC_VALUE_DATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC_VALUE_DATA) >> BP_OCOTP_CRC_VALUE_DATA) + +//! @brief Format value for bitfield OCOTP_CRC_VALUE_DATA. +#define BF_OCOTP_CRC_VALUE_DATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC_VALUE_DATA) & BM_OCOTP_CRC_VALUE_DATA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA field to a new value. +#define BW_OCOTP_CRC_VALUE_DATA(v) (HW_OCOTP_CRC_VALUE_WR((HW_OCOTP_CRC_VALUE_RD() & ~BM_OCOTP_CRC_VALUE_DATA) | BF_OCOTP_CRC_VALUE_DATA(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_VERSION - OTP Controller Version Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_VERSION - OTP Controller Version Register (RO) + * + * Reset value: 0x02000000 + * + * This register always returns a known read value for debug purposes it indicates the version of + * the block. This register indicates the RTL version in use. EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_version +{ + reg32_t U; + struct _hw_ocotp_version_bitfields + { + unsigned STEP : 16; //!< [15:0] Fixed read-only value reflecting the stepping of the RTL version. + unsigned MINOR : 8; //!< [23:16] Fixed read-only value reflecting the MINOR field of the RTL version. + unsigned MAJOR : 8; //!< [31:24] Fixed read-only value reflecting the MAJOR field of the RTL version. + } B; +} hw_ocotp_version_t; +#endif + +/* + * constants & macros for entire OCOTP_VERSION register + */ +#define HW_OCOTP_VERSION_ADDR (REGS_OCOTP_BASE + 0x90) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_VERSION (*(volatile hw_ocotp_version_t *) HW_OCOTP_VERSION_ADDR) +#define HW_OCOTP_VERSION_RD() (HW_OCOTP_VERSION.U) +#endif + +/* + * constants & macros for individual OCOTP_VERSION bitfields + */ + +/* --- Register HW_OCOTP_VERSION, field STEP[15:0] (RO) + * + * Fixed read-only value reflecting the stepping of the RTL version. + */ + +#define BP_OCOTP_VERSION_STEP (0) //!< Bit position for OCOTP_VERSION_STEP. +#define BM_OCOTP_VERSION_STEP (0x0000ffff) //!< Bit mask for OCOTP_VERSION_STEP. + +//! @brief Get value of OCOTP_VERSION_STEP from a register value. +#define BG_OCOTP_VERSION_STEP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_VERSION_STEP) >> BP_OCOTP_VERSION_STEP) + +/* --- Register HW_OCOTP_VERSION, field MINOR[23:16] (RO) + * + * Fixed read-only value reflecting the MINOR field of the RTL version. + */ + +#define BP_OCOTP_VERSION_MINOR (16) //!< Bit position for OCOTP_VERSION_MINOR. +#define BM_OCOTP_VERSION_MINOR (0x00ff0000) //!< Bit mask for OCOTP_VERSION_MINOR. + +//! @brief Get value of OCOTP_VERSION_MINOR from a register value. +#define BG_OCOTP_VERSION_MINOR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_VERSION_MINOR) >> BP_OCOTP_VERSION_MINOR) + +/* --- Register HW_OCOTP_VERSION, field MAJOR[31:24] (RO) + * + * Fixed read-only value reflecting the MAJOR field of the RTL version. + */ + +#define BP_OCOTP_VERSION_MAJOR (24) //!< Bit position for OCOTP_VERSION_MAJOR. +#define BM_OCOTP_VERSION_MAJOR (0xff000000) //!< Bit mask for OCOTP_VERSION_MAJOR. + +//! @brief Get value of OCOTP_VERSION_MAJOR from a register value. +#define BG_OCOTP_VERSION_MAJOR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_VERSION_MAJOR) >> BP_OCOTP_VERSION_MAJOR) + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_LOCK - Value of OTP Bank0 Word0 (Lock controls) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_LOCK - Value of OTP Bank0 Word0 (Lock controls) (RO) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 0, word 0 (ADDR = 0x00). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_lock +{ + reg32_t U; + struct _hw_ocotp_lock_bitfields + { + unsigned TESTER : 2; //!< [1:0] Status of shadow register and OTP write lock for tester region. + unsigned BOOT_CFG : 2; //!< [3:2] Status of shadow register and OTP write lock for boot_cfg region. + unsigned MEM_TRIM : 2; //!< [5:4] Status of shadow register and OTP write lock for mem_trim region. + unsigned SJC_RESP : 1; //!< [6] Status of shadow register read and write, OTP read and write lock for sjc_resp region. + unsigned RESERVED0 : 1; //!< [7] Reserved + unsigned MAC_ADDR : 2; //!< [9:8] Status of shadow register and OTP write lock for mac_addr region. + unsigned GP1 : 2; //!< [11:10] Status of shadow register and OTP write lock for gp2 region. + unsigned GP2 : 2; //!< [13:12] Status of shadow register and OTP write lock for gp2 region. + unsigned SRK : 1; //!< [14] Status of shadow register and OTP write lock for srk region. + unsigned RESERVED1 : 1; //!< [15] Reserved + unsigned DTCP_KEY : 1; //!< [16] Status of shadow register read and write, OTP read and write lock for dtcp_key region. + unsigned OTPMK : 1; //!< [17] Status of shadow register read and write, OTP read and write lock for otpmk region. + unsigned ANALOG : 2; //!< [19:18] Status of shadow register and OTP write lock for analog region. + unsigned HDCP_KSV : 1; //!< [20] Status of shadow register and OTP write lock for hdcp_ksv region. + unsigned HDCP_KEYS : 1; //!< [21] Status of OTP write, shadow register read and write for hdcp_key region. + unsigned MISC_CONF : 1; //!< [22] Status of shadow register and OTP write lock for misc_conf region. + unsigned DTCP_DEV_CERT : 1; //!< [23] Status of shadow register and OTP write lock for dtcp_dev_cert region. + unsigned RESERVED2 : 1; //!< [24] Reserved + unsigned PIN : 1; //!< [25] Status of Pin access lock bit. + unsigned CRC_GP_LO_LOCK : 2; //!< [27:26] Status of shadow register write and read, OTP program and read lock for lower 128 bits CRC region. + unsigned CRC_GP_HI_LOCK : 2; //!< [29:28] Status of shadow register write and read, OTP program and read lock for upper 128 bits CRC region. + unsigned UNALLOCATED : 2; //!< [31:30] Value of un-used portion of LOCK word + } B; +} hw_ocotp_lock_t; +#endif + +/* + * constants & macros for entire OCOTP_LOCK register + */ +#define HW_OCOTP_LOCK_ADDR (REGS_OCOTP_BASE + 0x400) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_LOCK (*(volatile hw_ocotp_lock_t *) HW_OCOTP_LOCK_ADDR) +#define HW_OCOTP_LOCK_RD() (HW_OCOTP_LOCK.U) +#endif + +/* + * constants & macros for individual OCOTP_LOCK bitfields + */ + +/* --- Register HW_OCOTP_LOCK, field TESTER[1:0] (RO) + * + * Status of shadow register and OTP write lock for tester region. When bit 1 is set, the writing of + * this region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP + * fuse word is blocked. + */ + +#define BP_OCOTP_LOCK_TESTER (0) //!< Bit position for OCOTP_LOCK_TESTER. +#define BM_OCOTP_LOCK_TESTER (0x00000003) //!< Bit mask for OCOTP_LOCK_TESTER. + +//! @brief Get value of OCOTP_LOCK_TESTER from a register value. +#define BG_OCOTP_LOCK_TESTER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_TESTER) >> BP_OCOTP_LOCK_TESTER) + +/* --- Register HW_OCOTP_LOCK, field BOOT_CFG[3:2] (RO) + * + * Status of shadow register and OTP write lock for boot_cfg region. When bit 1 is set, the writing + * of this region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP + * fuse word is blocked. + */ + +#define BP_OCOTP_LOCK_BOOT_CFG (2) //!< Bit position for OCOTP_LOCK_BOOT_CFG. +#define BM_OCOTP_LOCK_BOOT_CFG (0x0000000c) //!< Bit mask for OCOTP_LOCK_BOOT_CFG. + +//! @brief Get value of OCOTP_LOCK_BOOT_CFG from a register value. +#define BG_OCOTP_LOCK_BOOT_CFG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_BOOT_CFG) >> BP_OCOTP_LOCK_BOOT_CFG) + +/* --- Register HW_OCOTP_LOCK, field MEM_TRIM[5:4] (RO) + * + * Status of shadow register and OTP write lock for mem_trim region. When bit 1 is set, the writing + * of this region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP + * fuse word is blocked. + */ + +#define BP_OCOTP_LOCK_MEM_TRIM (4) //!< Bit position for OCOTP_LOCK_MEM_TRIM. +#define BM_OCOTP_LOCK_MEM_TRIM (0x00000030) //!< Bit mask for OCOTP_LOCK_MEM_TRIM. + +//! @brief Get value of OCOTP_LOCK_MEM_TRIM from a register value. +#define BG_OCOTP_LOCK_MEM_TRIM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_MEM_TRIM) >> BP_OCOTP_LOCK_MEM_TRIM) + +/* --- Register HW_OCOTP_LOCK, field SJC_RESP[6] (RO) + * + * Status of shadow register read and write, OTP read and write lock for sjc_resp region. When set, + * the writing of this region's shadow register and OTP fuse word are blocked. The read of this + * region's shadow register and OTP fuse word are also blocked. + */ + +#define BP_OCOTP_LOCK_SJC_RESP (6) //!< Bit position for OCOTP_LOCK_SJC_RESP. +#define BM_OCOTP_LOCK_SJC_RESP (0x00000040) //!< Bit mask for OCOTP_LOCK_SJC_RESP. + +//! @brief Get value of OCOTP_LOCK_SJC_RESP from a register value. +#define BG_OCOTP_LOCK_SJC_RESP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_SJC_RESP) >> BP_OCOTP_LOCK_SJC_RESP) + +/* --- Register HW_OCOTP_LOCK, field MAC_ADDR[9:8] (RO) + * + * Status of shadow register and OTP write lock for mac_addr region. When bit 1 is set, the writing + * of this region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP + * fuse word is blocked. + */ + +#define BP_OCOTP_LOCK_MAC_ADDR (8) //!< Bit position for OCOTP_LOCK_MAC_ADDR. +#define BM_OCOTP_LOCK_MAC_ADDR (0x00000300) //!< Bit mask for OCOTP_LOCK_MAC_ADDR. + +//! @brief Get value of OCOTP_LOCK_MAC_ADDR from a register value. +#define BG_OCOTP_LOCK_MAC_ADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_MAC_ADDR) >> BP_OCOTP_LOCK_MAC_ADDR) + +/* --- Register HW_OCOTP_LOCK, field GP1[11:10] (RO) + * + * Status of shadow register and OTP write lock for gp2 region. When bit 1 is set, the writing of + * this region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP + * fuse word is blocked. + */ + +#define BP_OCOTP_LOCK_GP1 (10) //!< Bit position for OCOTP_LOCK_GP1. +#define BM_OCOTP_LOCK_GP1 (0x00000c00) //!< Bit mask for OCOTP_LOCK_GP1. + +//! @brief Get value of OCOTP_LOCK_GP1 from a register value. +#define BG_OCOTP_LOCK_GP1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_GP1) >> BP_OCOTP_LOCK_GP1) + +/* --- Register HW_OCOTP_LOCK, field GP2[13:12] (RO) + * + * Status of shadow register and OTP write lock for gp2 region. When bit 1 is set, the writing of + * this region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP + * fuse word is blocked. + */ + +#define BP_OCOTP_LOCK_GP2 (12) //!< Bit position for OCOTP_LOCK_GP2. +#define BM_OCOTP_LOCK_GP2 (0x00003000) //!< Bit mask for OCOTP_LOCK_GP2. + +//! @brief Get value of OCOTP_LOCK_GP2 from a register value. +#define BG_OCOTP_LOCK_GP2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_GP2) >> BP_OCOTP_LOCK_GP2) + +/* --- Register HW_OCOTP_LOCK, field SRK[14] (RO) + * + * Status of shadow register and OTP write lock for srk region. When set, the writing of this + * region's shadow register and OTP fuse word are blocked. + */ + +#define BP_OCOTP_LOCK_SRK (14) //!< Bit position for OCOTP_LOCK_SRK. +#define BM_OCOTP_LOCK_SRK (0x00004000) //!< Bit mask for OCOTP_LOCK_SRK. + +//! @brief Get value of OCOTP_LOCK_SRK from a register value. +#define BG_OCOTP_LOCK_SRK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_SRK) >> BP_OCOTP_LOCK_SRK) + +/* --- Register HW_OCOTP_LOCK, field DTCP_KEY[16] (RO) + * + * Status of shadow register read and write, OTP read and write lock for dtcp_key region. When set, + * the writing of this region's shadow register and OTP fuse word are blocked. The read of this + * region's shadow register and OTP fuse word are also blocked. + */ + +#define BP_OCOTP_LOCK_DTCP_KEY (16) //!< Bit position for OCOTP_LOCK_DTCP_KEY. +#define BM_OCOTP_LOCK_DTCP_KEY (0x00010000) //!< Bit mask for OCOTP_LOCK_DTCP_KEY. + +//! @brief Get value of OCOTP_LOCK_DTCP_KEY from a register value. +#define BG_OCOTP_LOCK_DTCP_KEY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_DTCP_KEY) >> BP_OCOTP_LOCK_DTCP_KEY) + +/* --- Register HW_OCOTP_LOCK, field OTPMK[17] (RO) + * + * Status of shadow register read and write, OTP read and write lock for otpmk region. When set, the + * writing of this region's shadow register and OTP fuse word are blocked. The read of this region's + * shadow register and OTP fuse word are also blocked. + */ + +#define BP_OCOTP_LOCK_OTPMK (17) //!< Bit position for OCOTP_LOCK_OTPMK. +#define BM_OCOTP_LOCK_OTPMK (0x00020000) //!< Bit mask for OCOTP_LOCK_OTPMK. + +//! @brief Get value of OCOTP_LOCK_OTPMK from a register value. +#define BG_OCOTP_LOCK_OTPMK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_OTPMK) >> BP_OCOTP_LOCK_OTPMK) + +/* --- Register HW_OCOTP_LOCK, field ANALOG[19:18] (RO) + * + * Status of shadow register and OTP write lock for analog region. When bit 1 is set, the writing of + * this region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP + * fuse word is blocked. + */ + +#define BP_OCOTP_LOCK_ANALOG (18) //!< Bit position for OCOTP_LOCK_ANALOG. +#define BM_OCOTP_LOCK_ANALOG (0x000c0000) //!< Bit mask for OCOTP_LOCK_ANALOG. + +//! @brief Get value of OCOTP_LOCK_ANALOG from a register value. +#define BG_OCOTP_LOCK_ANALOG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_ANALOG) >> BP_OCOTP_LOCK_ANALOG) + +/* --- Register HW_OCOTP_LOCK, field HDCP_KSV[20] (RO) + * + * Status of shadow register and OTP write lock for hdcp_ksv region. When set, the writing of this + * region's shadow register and OTP fuse word are blocked. + */ + +#define BP_OCOTP_LOCK_HDCP_KSV (20) //!< Bit position for OCOTP_LOCK_HDCP_KSV. +#define BM_OCOTP_LOCK_HDCP_KSV (0x00100000) //!< Bit mask for OCOTP_LOCK_HDCP_KSV. + +//! @brief Get value of OCOTP_LOCK_HDCP_KSV from a register value. +#define BG_OCOTP_LOCK_HDCP_KSV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_HDCP_KSV) >> BP_OCOTP_LOCK_HDCP_KSV) + +/* --- Register HW_OCOTP_LOCK, field HDCP_KEYS[21] (RO) + * + * Status of OTP write, shadow register read and write for hdcp_key region. When set, the writing of + * this region's shadow register and OTP fuse word are blocked. HDTP key shadow register also can be + * not read by ARM if set. The HDCP key region can not support OTP read feature in any case. + */ + +#define BP_OCOTP_LOCK_HDCP_KEYS (21) //!< Bit position for OCOTP_LOCK_HDCP_KEYS. +#define BM_OCOTP_LOCK_HDCP_KEYS (0x00200000) //!< Bit mask for OCOTP_LOCK_HDCP_KEYS. + +//! @brief Get value of OCOTP_LOCK_HDCP_KEYS from a register value. +#define BG_OCOTP_LOCK_HDCP_KEYS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_HDCP_KEYS) >> BP_OCOTP_LOCK_HDCP_KEYS) + +/* --- Register HW_OCOTP_LOCK, field MISC_CONF[22] (RO) + * + * Status of shadow register and OTP write lock for misc_conf region. When set, the writing of this + * region's shadow register and OTP fuse word are blocked. + */ + +#define BP_OCOTP_LOCK_MISC_CONF (22) //!< Bit position for OCOTP_LOCK_MISC_CONF. +#define BM_OCOTP_LOCK_MISC_CONF (0x00400000) //!< Bit mask for OCOTP_LOCK_MISC_CONF. + +//! @brief Get value of OCOTP_LOCK_MISC_CONF from a register value. +#define BG_OCOTP_LOCK_MISC_CONF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_MISC_CONF) >> BP_OCOTP_LOCK_MISC_CONF) + +/* --- Register HW_OCOTP_LOCK, field DTCP_DEV_CERT[23] (RO) + * + * Status of shadow register and OTP write lock for dtcp_dev_cert region. When set, the writing of + * this region's shadow register and OTP fuse word are blocked. + */ + +#define BP_OCOTP_LOCK_DTCP_DEV_CERT (23) //!< Bit position for OCOTP_LOCK_DTCP_DEV_CERT. +#define BM_OCOTP_LOCK_DTCP_DEV_CERT (0x00800000) //!< Bit mask for OCOTP_LOCK_DTCP_DEV_CERT. + +//! @brief Get value of OCOTP_LOCK_DTCP_DEV_CERT from a register value. +#define BG_OCOTP_LOCK_DTCP_DEV_CERT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_DTCP_DEV_CERT) >> BP_OCOTP_LOCK_DTCP_DEV_CERT) + +/* --- Register HW_OCOTP_LOCK, field PIN[25] (RO) + * + * Status of Pin access lock bit. When set, pin access is disabled. + */ + +#define BP_OCOTP_LOCK_PIN (25) //!< Bit position for OCOTP_LOCK_PIN. +#define BM_OCOTP_LOCK_PIN (0x02000000) //!< Bit mask for OCOTP_LOCK_PIN. + +//! @brief Get value of OCOTP_LOCK_PIN from a register value. +#define BG_OCOTP_LOCK_PIN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_PIN) >> BP_OCOTP_LOCK_PIN) + +/* --- Register HW_OCOTP_LOCK, field CRC_GP_LO_LOCK[27:26] (RO) + * + * Status of shadow register write and read, OTP program and read lock for lower 128 bits CRC + * region. When bit 1 is set, the reading and writing of this region's OTP fuse and reading of + * shadow register are blocked.When bit 0 is set, the writing of this region's shadow register and + * OTP fuse are blocked. + */ + +#define BP_OCOTP_LOCK_CRC_GP_LO_LOCK (26) //!< Bit position for OCOTP_LOCK_CRC_GP_LO_LOCK. +#define BM_OCOTP_LOCK_CRC_GP_LO_LOCK (0x0c000000) //!< Bit mask for OCOTP_LOCK_CRC_GP_LO_LOCK. + +//! @brief Get value of OCOTP_LOCK_CRC_GP_LO_LOCK from a register value. +#define BG_OCOTP_LOCK_CRC_GP_LO_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_CRC_GP_LO_LOCK) >> BP_OCOTP_LOCK_CRC_GP_LO_LOCK) + +/* --- Register HW_OCOTP_LOCK, field CRC_GP_HI_LOCK[29:28] (RO) + * + * Status of shadow register write and read, OTP program and read lock for upper 128 bits CRC + * region. When bit 1 is set, the reading and writing of this region's OTP fuse and reading of + * shadow register are blocked.When bit 0 is set, the writing of this region's shadow register and + * OTP fuse are blocked. + */ + +#define BP_OCOTP_LOCK_CRC_GP_HI_LOCK (28) //!< Bit position for OCOTP_LOCK_CRC_GP_HI_LOCK. +#define BM_OCOTP_LOCK_CRC_GP_HI_LOCK (0x30000000) //!< Bit mask for OCOTP_LOCK_CRC_GP_HI_LOCK. + +//! @brief Get value of OCOTP_LOCK_CRC_GP_HI_LOCK from a register value. +#define BG_OCOTP_LOCK_CRC_GP_HI_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_CRC_GP_HI_LOCK) >> BP_OCOTP_LOCK_CRC_GP_HI_LOCK) + +/* --- Register HW_OCOTP_LOCK, field UNALLOCATED[31:30] (RO) + * + * Value of un-used portion of LOCK word + */ + +#define BP_OCOTP_LOCK_UNALLOCATED (30) //!< Bit position for OCOTP_LOCK_UNALLOCATED. +#define BM_OCOTP_LOCK_UNALLOCATED (0xc0000000) //!< Bit mask for OCOTP_LOCK_UNALLOCATED. + +//! @brief Get value of OCOTP_LOCK_UNALLOCATED from a register value. +#define BG_OCOTP_LOCK_UNALLOCATED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_LOCK_UNALLOCATED) >> BP_OCOTP_LOCK_UNALLOCATED) + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 0, word 1 (ADDR = 0x01). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_cfg0 +{ + reg32_t U; + struct _hw_ocotp_cfg0_bitfields + { + unsigned BITS : 32; //!< [31:0] This register contains 32 bits of the Unique ID and SJC_CHALLENGE field. + } B; +} hw_ocotp_cfg0_t; +#endif + +/* + * constants & macros for entire OCOTP_CFG0 register + */ +#define HW_OCOTP_CFG0_ADDR (REGS_OCOTP_BASE + 0x410) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CFG0 (*(volatile hw_ocotp_cfg0_t *) HW_OCOTP_CFG0_ADDR) +#define HW_OCOTP_CFG0_RD() (HW_OCOTP_CFG0.U) +#define HW_OCOTP_CFG0_WR(v) (HW_OCOTP_CFG0.U = (v)) +#define HW_OCOTP_CFG0_SET(v) (HW_OCOTP_CFG0_WR(HW_OCOTP_CFG0_RD() | (v))) +#define HW_OCOTP_CFG0_CLR(v) (HW_OCOTP_CFG0_WR(HW_OCOTP_CFG0_RD() & ~(v))) +#define HW_OCOTP_CFG0_TOG(v) (HW_OCOTP_CFG0_WR(HW_OCOTP_CFG0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CFG0 bitfields + */ + +/* --- Register HW_OCOTP_CFG0, field BITS[31:0] (RW) + * + * This register contains 32 bits of the Unique ID and SJC_CHALLENGE field. Reflects value of OTP + * Bank 0, word 1 (ADDR = 0x01). These bits become read-only after the HW_OCOTP_LOCK_TESTER[1] bit + * is set. + */ + +#define BP_OCOTP_CFG0_BITS (0) //!< Bit position for OCOTP_CFG0_BITS. +#define BM_OCOTP_CFG0_BITS (0xffffffff) //!< Bit mask for OCOTP_CFG0_BITS. + +//! @brief Get value of OCOTP_CFG0_BITS from a register value. +#define BG_OCOTP_CFG0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CFG0_BITS) >> BP_OCOTP_CFG0_BITS) + +//! @brief Format value for bitfield OCOTP_CFG0_BITS. +#define BF_OCOTP_CFG0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CFG0_BITS) & BM_OCOTP_CFG0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CFG0_BITS(v) (HW_OCOTP_CFG0_WR((HW_OCOTP_CFG0_RD() & ~BM_OCOTP_CFG0_BITS) | BF_OCOTP_CFG0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] shadowed memory mapped access to OTP Bank 0, word 2 (ADDR = 0x02). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_cfg1 +{ + reg32_t U; + struct _hw_ocotp_cfg1_bitfields + { + unsigned BITS : 32; //!< [31:0] This register contains 32 bits of the Unique ID and SJC_CHALLENGE field. + } B; +} hw_ocotp_cfg1_t; +#endif + +/* + * constants & macros for entire OCOTP_CFG1 register + */ +#define HW_OCOTP_CFG1_ADDR (REGS_OCOTP_BASE + 0x420) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CFG1 (*(volatile hw_ocotp_cfg1_t *) HW_OCOTP_CFG1_ADDR) +#define HW_OCOTP_CFG1_RD() (HW_OCOTP_CFG1.U) +#define HW_OCOTP_CFG1_WR(v) (HW_OCOTP_CFG1.U = (v)) +#define HW_OCOTP_CFG1_SET(v) (HW_OCOTP_CFG1_WR(HW_OCOTP_CFG1_RD() | (v))) +#define HW_OCOTP_CFG1_CLR(v) (HW_OCOTP_CFG1_WR(HW_OCOTP_CFG1_RD() & ~(v))) +#define HW_OCOTP_CFG1_TOG(v) (HW_OCOTP_CFG1_WR(HW_OCOTP_CFG1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CFG1 bitfields + */ + +/* --- Register HW_OCOTP_CFG1, field BITS[31:0] (RW) + * + * This register contains 32 bits of the Unique ID and SJC_CHALLENGE field. Reflects value of OTP + * Bank 0, word 2 (ADDR = 0x02). These bits become read-only after the HW_OCOTP_LOCK_TESTER[1] bit + * is set. + */ + +#define BP_OCOTP_CFG1_BITS (0) //!< Bit position for OCOTP_CFG1_BITS. +#define BM_OCOTP_CFG1_BITS (0xffffffff) //!< Bit mask for OCOTP_CFG1_BITS. + +//! @brief Get value of OCOTP_CFG1_BITS from a register value. +#define BG_OCOTP_CFG1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CFG1_BITS) >> BP_OCOTP_CFG1_BITS) + +//! @brief Format value for bitfield OCOTP_CFG1_BITS. +#define BF_OCOTP_CFG1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CFG1_BITS) & BM_OCOTP_CFG1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CFG1_BITS(v) (HW_OCOTP_CFG1_WR((HW_OCOTP_CFG1_RD() & ~BM_OCOTP_CFG1_BITS) | BF_OCOTP_CFG1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 0, word 3 (ADDR = 0x03). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_cfg2 +{ + reg32_t U; + struct _hw_ocotp_cfg2_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 0, word 3 (ADDR = 0x03). + } B; +} hw_ocotp_cfg2_t; +#endif + +/* + * constants & macros for entire OCOTP_CFG2 register + */ +#define HW_OCOTP_CFG2_ADDR (REGS_OCOTP_BASE + 0x430) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CFG2 (*(volatile hw_ocotp_cfg2_t *) HW_OCOTP_CFG2_ADDR) +#define HW_OCOTP_CFG2_RD() (HW_OCOTP_CFG2.U) +#define HW_OCOTP_CFG2_WR(v) (HW_OCOTP_CFG2.U = (v)) +#define HW_OCOTP_CFG2_SET(v) (HW_OCOTP_CFG2_WR(HW_OCOTP_CFG2_RD() | (v))) +#define HW_OCOTP_CFG2_CLR(v) (HW_OCOTP_CFG2_WR(HW_OCOTP_CFG2_RD() & ~(v))) +#define HW_OCOTP_CFG2_TOG(v) (HW_OCOTP_CFG2_WR(HW_OCOTP_CFG2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CFG2 bitfields + */ + +/* --- Register HW_OCOTP_CFG2, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 0, word 3 (ADDR = 0x03). These bits become read-only after the + * HW_OCOTP_LOCK_TESTER[1] bit is set. + */ + +#define BP_OCOTP_CFG2_BITS (0) //!< Bit position for OCOTP_CFG2_BITS. +#define BM_OCOTP_CFG2_BITS (0xffffffff) //!< Bit mask for OCOTP_CFG2_BITS. + +//! @brief Get value of OCOTP_CFG2_BITS from a register value. +#define BG_OCOTP_CFG2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CFG2_BITS) >> BP_OCOTP_CFG2_BITS) + +//! @brief Format value for bitfield OCOTP_CFG2_BITS. +#define BF_OCOTP_CFG2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CFG2_BITS) & BM_OCOTP_CFG2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CFG2_BITS(v) (HW_OCOTP_CFG2_WR((HW_OCOTP_CFG2_RD() & ~BM_OCOTP_CFG2_BITS) | BF_OCOTP_CFG2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Non-shadowed memory mapped access to OTP Bank 0, word 4 (ADDR = + * 0x04). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_cfg3 +{ + reg32_t U; + struct _hw_ocotp_cfg3_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 0, word 4 (ADDR = 0x04). + } B; +} hw_ocotp_cfg3_t; +#endif + +/* + * constants & macros for entire OCOTP_CFG3 register + */ +#define HW_OCOTP_CFG3_ADDR (REGS_OCOTP_BASE + 0x440) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CFG3 (*(volatile hw_ocotp_cfg3_t *) HW_OCOTP_CFG3_ADDR) +#define HW_OCOTP_CFG3_RD() (HW_OCOTP_CFG3.U) +#define HW_OCOTP_CFG3_WR(v) (HW_OCOTP_CFG3.U = (v)) +#define HW_OCOTP_CFG3_SET(v) (HW_OCOTP_CFG3_WR(HW_OCOTP_CFG3_RD() | (v))) +#define HW_OCOTP_CFG3_CLR(v) (HW_OCOTP_CFG3_WR(HW_OCOTP_CFG3_RD() & ~(v))) +#define HW_OCOTP_CFG3_TOG(v) (HW_OCOTP_CFG3_WR(HW_OCOTP_CFG3_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CFG3 bitfields + */ + +/* --- Register HW_OCOTP_CFG3, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 0, word 4 (ADDR = 0x04). These bits become read-only after the + * HW_OCOTP_LOCK_TESTER[1] bit is set. + */ + +#define BP_OCOTP_CFG3_BITS (0) //!< Bit position for OCOTP_CFG3_BITS. +#define BM_OCOTP_CFG3_BITS (0xffffffff) //!< Bit mask for OCOTP_CFG3_BITS. + +//! @brief Get value of OCOTP_CFG3_BITS from a register value. +#define BG_OCOTP_CFG3_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CFG3_BITS) >> BP_OCOTP_CFG3_BITS) + +//! @brief Format value for bitfield OCOTP_CFG3_BITS. +#define BF_OCOTP_CFG3_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CFG3_BITS) & BM_OCOTP_CFG3_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CFG3_BITS(v) (HW_OCOTP_CFG3_WR((HW_OCOTP_CFG3_RD() & ~BM_OCOTP_CFG3_BITS) | BF_OCOTP_CFG3_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 0, word 5 (ADDR = 0x05). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_cfg4 +{ + reg32_t U; + struct _hw_ocotp_cfg4_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 0, word 5 (ADDR = 0x05). + } B; +} hw_ocotp_cfg4_t; +#endif + +/* + * constants & macros for entire OCOTP_CFG4 register + */ +#define HW_OCOTP_CFG4_ADDR (REGS_OCOTP_BASE + 0x450) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CFG4 (*(volatile hw_ocotp_cfg4_t *) HW_OCOTP_CFG4_ADDR) +#define HW_OCOTP_CFG4_RD() (HW_OCOTP_CFG4.U) +#define HW_OCOTP_CFG4_WR(v) (HW_OCOTP_CFG4.U = (v)) +#define HW_OCOTP_CFG4_SET(v) (HW_OCOTP_CFG4_WR(HW_OCOTP_CFG4_RD() | (v))) +#define HW_OCOTP_CFG4_CLR(v) (HW_OCOTP_CFG4_WR(HW_OCOTP_CFG4_RD() & ~(v))) +#define HW_OCOTP_CFG4_TOG(v) (HW_OCOTP_CFG4_WR(HW_OCOTP_CFG4_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CFG4 bitfields + */ + +/* --- Register HW_OCOTP_CFG4, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 0, word 5 (ADDR = 0x05). These bits become read-only after the + * HW_OCOTP_LOCK_BOOT_CFG[1] bit is set. + */ + +#define BP_OCOTP_CFG4_BITS (0) //!< Bit position for OCOTP_CFG4_BITS. +#define BM_OCOTP_CFG4_BITS (0xffffffff) //!< Bit mask for OCOTP_CFG4_BITS. + +//! @brief Get value of OCOTP_CFG4_BITS from a register value. +#define BG_OCOTP_CFG4_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CFG4_BITS) >> BP_OCOTP_CFG4_BITS) + +//! @brief Format value for bitfield OCOTP_CFG4_BITS. +#define BF_OCOTP_CFG4_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CFG4_BITS) & BM_OCOTP_CFG4_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CFG4_BITS(v) (HW_OCOTP_CFG4_WR((HW_OCOTP_CFG4_RD() & ~BM_OCOTP_CFG4_BITS) | BF_OCOTP_CFG4_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 0, word 6 (ADDR = 0x06). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_cfg5 +{ + reg32_t U; + struct _hw_ocotp_cfg5_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 0, word 6 (ADDR = 0x06). + } B; +} hw_ocotp_cfg5_t; +#endif + +/* + * constants & macros for entire OCOTP_CFG5 register + */ +#define HW_OCOTP_CFG5_ADDR (REGS_OCOTP_BASE + 0x460) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CFG5 (*(volatile hw_ocotp_cfg5_t *) HW_OCOTP_CFG5_ADDR) +#define HW_OCOTP_CFG5_RD() (HW_OCOTP_CFG5.U) +#define HW_OCOTP_CFG5_WR(v) (HW_OCOTP_CFG5.U = (v)) +#define HW_OCOTP_CFG5_SET(v) (HW_OCOTP_CFG5_WR(HW_OCOTP_CFG5_RD() | (v))) +#define HW_OCOTP_CFG5_CLR(v) (HW_OCOTP_CFG5_WR(HW_OCOTP_CFG5_RD() & ~(v))) +#define HW_OCOTP_CFG5_TOG(v) (HW_OCOTP_CFG5_WR(HW_OCOTP_CFG5_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CFG5 bitfields + */ + +/* --- Register HW_OCOTP_CFG5, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 0, word 6 (ADDR = 0x06). These bits become read-only after the + * HW_OCOTP_LOCK_BOOT_CFG[1] bit is set. + */ + +#define BP_OCOTP_CFG5_BITS (0) //!< Bit position for OCOTP_CFG5_BITS. +#define BM_OCOTP_CFG5_BITS (0xffffffff) //!< Bit mask for OCOTP_CFG5_BITS. + +//! @brief Get value of OCOTP_CFG5_BITS from a register value. +#define BG_OCOTP_CFG5_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CFG5_BITS) >> BP_OCOTP_CFG5_BITS) + +//! @brief Format value for bitfield OCOTP_CFG5_BITS. +#define BF_OCOTP_CFG5_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CFG5_BITS) & BM_OCOTP_CFG5_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CFG5_BITS(v) (HW_OCOTP_CFG5_WR((HW_OCOTP_CFG5_RD() & ~BM_OCOTP_CFG5_BITS) | BF_OCOTP_CFG5_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 0, word 7 (ADDR = 0x07). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_cfg6 +{ + reg32_t U; + struct _hw_ocotp_cfg6_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 0, word 7 (ADDR = 0x07). + } B; +} hw_ocotp_cfg6_t; +#endif + +/* + * constants & macros for entire OCOTP_CFG6 register + */ +#define HW_OCOTP_CFG6_ADDR (REGS_OCOTP_BASE + 0x470) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CFG6 (*(volatile hw_ocotp_cfg6_t *) HW_OCOTP_CFG6_ADDR) +#define HW_OCOTP_CFG6_RD() (HW_OCOTP_CFG6.U) +#define HW_OCOTP_CFG6_WR(v) (HW_OCOTP_CFG6.U = (v)) +#define HW_OCOTP_CFG6_SET(v) (HW_OCOTP_CFG6_WR(HW_OCOTP_CFG6_RD() | (v))) +#define HW_OCOTP_CFG6_CLR(v) (HW_OCOTP_CFG6_WR(HW_OCOTP_CFG6_RD() & ~(v))) +#define HW_OCOTP_CFG6_TOG(v) (HW_OCOTP_CFG6_WR(HW_OCOTP_CFG6_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CFG6 bitfields + */ + +/* --- Register HW_OCOTP_CFG6, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 0, word 7 (ADDR = 0x07). These bits become read-only after the + * HW_OCOTP_LOCK_BOOT_CFG[1] bit is set. + */ + +#define BP_OCOTP_CFG6_BITS (0) //!< Bit position for OCOTP_CFG6_BITS. +#define BM_OCOTP_CFG6_BITS (0xffffffff) //!< Bit mask for OCOTP_CFG6_BITS. + +//! @brief Get value of OCOTP_CFG6_BITS from a register value. +#define BG_OCOTP_CFG6_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CFG6_BITS) >> BP_OCOTP_CFG6_BITS) + +//! @brief Format value for bitfield OCOTP_CFG6_BITS. +#define BF_OCOTP_CFG6_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CFG6_BITS) & BM_OCOTP_CFG6_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CFG6_BITS(v) (HW_OCOTP_CFG6_WR((HW_OCOTP_CFG6_RD() & ~BM_OCOTP_CFG6_BITS) | BF_OCOTP_CFG6_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 0 (ADDR = 0x08). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_mem0 +{ + reg32_t U; + struct _hw_ocotp_mem0_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP bank 1, word 0 (ADDR = 0x08). + } B; +} hw_ocotp_mem0_t; +#endif + +/* + * constants & macros for entire OCOTP_MEM0 register + */ +#define HW_OCOTP_MEM0_ADDR (REGS_OCOTP_BASE + 0x480) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_MEM0 (*(volatile hw_ocotp_mem0_t *) HW_OCOTP_MEM0_ADDR) +#define HW_OCOTP_MEM0_RD() (HW_OCOTP_MEM0.U) +#define HW_OCOTP_MEM0_WR(v) (HW_OCOTP_MEM0.U = (v)) +#define HW_OCOTP_MEM0_SET(v) (HW_OCOTP_MEM0_WR(HW_OCOTP_MEM0_RD() | (v))) +#define HW_OCOTP_MEM0_CLR(v) (HW_OCOTP_MEM0_WR(HW_OCOTP_MEM0_RD() & ~(v))) +#define HW_OCOTP_MEM0_TOG(v) (HW_OCOTP_MEM0_WR(HW_OCOTP_MEM0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_MEM0 bitfields + */ + +/* --- Register HW_OCOTP_MEM0, field BITS[31:0] (RW) + * + * Reflects value of OTP bank 1, word 0 (ADDR = 0x08). These bits become read-only after the + * HW_OCOTP_LOCK_MEM_TRIM[1] bit is set. + */ + +#define BP_OCOTP_MEM0_BITS (0) //!< Bit position for OCOTP_MEM0_BITS. +#define BM_OCOTP_MEM0_BITS (0xffffffff) //!< Bit mask for OCOTP_MEM0_BITS. + +//! @brief Get value of OCOTP_MEM0_BITS from a register value. +#define BG_OCOTP_MEM0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_MEM0_BITS) >> BP_OCOTP_MEM0_BITS) + +//! @brief Format value for bitfield OCOTP_MEM0_BITS. +#define BF_OCOTP_MEM0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_MEM0_BITS) & BM_OCOTP_MEM0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_MEM0_BITS(v) (HW_OCOTP_MEM0_WR((HW_OCOTP_MEM0_RD() & ~BM_OCOTP_MEM0_BITS) | BF_OCOTP_MEM0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 1 (ADDR = 0x09). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_mem1 +{ + reg32_t U; + struct _hw_ocotp_mem1_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP bank 1, word 1 (ADDR = 0x09). + } B; +} hw_ocotp_mem1_t; +#endif + +/* + * constants & macros for entire OCOTP_MEM1 register + */ +#define HW_OCOTP_MEM1_ADDR (REGS_OCOTP_BASE + 0x490) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_MEM1 (*(volatile hw_ocotp_mem1_t *) HW_OCOTP_MEM1_ADDR) +#define HW_OCOTP_MEM1_RD() (HW_OCOTP_MEM1.U) +#define HW_OCOTP_MEM1_WR(v) (HW_OCOTP_MEM1.U = (v)) +#define HW_OCOTP_MEM1_SET(v) (HW_OCOTP_MEM1_WR(HW_OCOTP_MEM1_RD() | (v))) +#define HW_OCOTP_MEM1_CLR(v) (HW_OCOTP_MEM1_WR(HW_OCOTP_MEM1_RD() & ~(v))) +#define HW_OCOTP_MEM1_TOG(v) (HW_OCOTP_MEM1_WR(HW_OCOTP_MEM1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_MEM1 bitfields + */ + +/* --- Register HW_OCOTP_MEM1, field BITS[31:0] (RW) + * + * Reflects value of OTP bank 1, word 1 (ADDR = 0x09). These bits become read-only after the + * HW_OCOTP_LOCK_MEM_TRIM[1] bit is set. + */ + +#define BP_OCOTP_MEM1_BITS (0) //!< Bit position for OCOTP_MEM1_BITS. +#define BM_OCOTP_MEM1_BITS (0xffffffff) //!< Bit mask for OCOTP_MEM1_BITS. + +//! @brief Get value of OCOTP_MEM1_BITS from a register value. +#define BG_OCOTP_MEM1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_MEM1_BITS) >> BP_OCOTP_MEM1_BITS) + +//! @brief Format value for bitfield OCOTP_MEM1_BITS. +#define BF_OCOTP_MEM1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_MEM1_BITS) & BM_OCOTP_MEM1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_MEM1_BITS(v) (HW_OCOTP_MEM1_WR((HW_OCOTP_MEM1_RD() & ~BM_OCOTP_MEM1_BITS) | BF_OCOTP_MEM1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 2 (ADDR = 0x0A). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_mem2 +{ + reg32_t U; + struct _hw_ocotp_mem2_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP bank 1, word 2 (ADDR = 0x0A). + } B; +} hw_ocotp_mem2_t; +#endif + +/* + * constants & macros for entire OCOTP_MEM2 register + */ +#define HW_OCOTP_MEM2_ADDR (REGS_OCOTP_BASE + 0x4a0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_MEM2 (*(volatile hw_ocotp_mem2_t *) HW_OCOTP_MEM2_ADDR) +#define HW_OCOTP_MEM2_RD() (HW_OCOTP_MEM2.U) +#define HW_OCOTP_MEM2_WR(v) (HW_OCOTP_MEM2.U = (v)) +#define HW_OCOTP_MEM2_SET(v) (HW_OCOTP_MEM2_WR(HW_OCOTP_MEM2_RD() | (v))) +#define HW_OCOTP_MEM2_CLR(v) (HW_OCOTP_MEM2_WR(HW_OCOTP_MEM2_RD() & ~(v))) +#define HW_OCOTP_MEM2_TOG(v) (HW_OCOTP_MEM2_WR(HW_OCOTP_MEM2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_MEM2 bitfields + */ + +/* --- Register HW_OCOTP_MEM2, field BITS[31:0] (RW) + * + * Reflects value of OTP bank 1, word 2 (ADDR = 0x0A). These bits become read-only after the + * HW_OCOTP_LOCK_MEM_TRIM[1] bit is set. + */ + +#define BP_OCOTP_MEM2_BITS (0) //!< Bit position for OCOTP_MEM2_BITS. +#define BM_OCOTP_MEM2_BITS (0xffffffff) //!< Bit mask for OCOTP_MEM2_BITS. + +//! @brief Get value of OCOTP_MEM2_BITS from a register value. +#define BG_OCOTP_MEM2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_MEM2_BITS) >> BP_OCOTP_MEM2_BITS) + +//! @brief Format value for bitfield OCOTP_MEM2_BITS. +#define BF_OCOTP_MEM2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_MEM2_BITS) & BM_OCOTP_MEM2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_MEM2_BITS(v) (HW_OCOTP_MEM2_WR((HW_OCOTP_MEM2_RD() & ~BM_OCOTP_MEM2_BITS) | BF_OCOTP_MEM2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 3 (ADDR = 0x0B). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_mem3 +{ + reg32_t U; + struct _hw_ocotp_mem3_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP bank 1, word 3 (ADDR = 0x0B). + } B; +} hw_ocotp_mem3_t; +#endif + +/* + * constants & macros for entire OCOTP_MEM3 register + */ +#define HW_OCOTP_MEM3_ADDR (REGS_OCOTP_BASE + 0x4b0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_MEM3 (*(volatile hw_ocotp_mem3_t *) HW_OCOTP_MEM3_ADDR) +#define HW_OCOTP_MEM3_RD() (HW_OCOTP_MEM3.U) +#define HW_OCOTP_MEM3_WR(v) (HW_OCOTP_MEM3.U = (v)) +#define HW_OCOTP_MEM3_SET(v) (HW_OCOTP_MEM3_WR(HW_OCOTP_MEM3_RD() | (v))) +#define HW_OCOTP_MEM3_CLR(v) (HW_OCOTP_MEM3_WR(HW_OCOTP_MEM3_RD() & ~(v))) +#define HW_OCOTP_MEM3_TOG(v) (HW_OCOTP_MEM3_WR(HW_OCOTP_MEM3_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_MEM3 bitfields + */ + +/* --- Register HW_OCOTP_MEM3, field BITS[31:0] (RW) + * + * Reflects value of OTP bank 1, word 3 (ADDR = 0x0B). These bits become read-only after the + * HW_OCOTP_LOCK_MEM_TRIM[1] bit is set. + */ + +#define BP_OCOTP_MEM3_BITS (0) //!< Bit position for OCOTP_MEM3_BITS. +#define BM_OCOTP_MEM3_BITS (0xffffffff) //!< Bit mask for OCOTP_MEM3_BITS. + +//! @brief Get value of OCOTP_MEM3_BITS from a register value. +#define BG_OCOTP_MEM3_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_MEM3_BITS) >> BP_OCOTP_MEM3_BITS) + +//! @brief Format value for bitfield OCOTP_MEM3_BITS. +#define BF_OCOTP_MEM3_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_MEM3_BITS) & BM_OCOTP_MEM3_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_MEM3_BITS(v) (HW_OCOTP_MEM3_WR((HW_OCOTP_MEM3_RD() & ~BM_OCOTP_MEM3_BITS) | BF_OCOTP_MEM3_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 4 (ADDR = 0x0C). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_mem4 +{ + reg32_t U; + struct _hw_ocotp_mem4_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP bank 1, word 4 (ADDR = 0x0C). + } B; +} hw_ocotp_mem4_t; +#endif + +/* + * constants & macros for entire OCOTP_MEM4 register + */ +#define HW_OCOTP_MEM4_ADDR (REGS_OCOTP_BASE + 0x4c0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_MEM4 (*(volatile hw_ocotp_mem4_t *) HW_OCOTP_MEM4_ADDR) +#define HW_OCOTP_MEM4_RD() (HW_OCOTP_MEM4.U) +#define HW_OCOTP_MEM4_WR(v) (HW_OCOTP_MEM4.U = (v)) +#define HW_OCOTP_MEM4_SET(v) (HW_OCOTP_MEM4_WR(HW_OCOTP_MEM4_RD() | (v))) +#define HW_OCOTP_MEM4_CLR(v) (HW_OCOTP_MEM4_WR(HW_OCOTP_MEM4_RD() & ~(v))) +#define HW_OCOTP_MEM4_TOG(v) (HW_OCOTP_MEM4_WR(HW_OCOTP_MEM4_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_MEM4 bitfields + */ + +/* --- Register HW_OCOTP_MEM4, field BITS[31:0] (RW) + * + * Reflects value of OTP bank 1, word 4 (ADDR = 0x0C). These bits become read-only after the + * HW_OCOTP_LOCK_MEM_TRIM[1] bit is set. + */ + +#define BP_OCOTP_MEM4_BITS (0) //!< Bit position for OCOTP_MEM4_BITS. +#define BM_OCOTP_MEM4_BITS (0xffffffff) //!< Bit mask for OCOTP_MEM4_BITS. + +//! @brief Get value of OCOTP_MEM4_BITS from a register value. +#define BG_OCOTP_MEM4_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_MEM4_BITS) >> BP_OCOTP_MEM4_BITS) + +//! @brief Format value for bitfield OCOTP_MEM4_BITS. +#define BF_OCOTP_MEM4_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_MEM4_BITS) & BM_OCOTP_MEM4_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_MEM4_BITS(v) (HW_OCOTP_MEM4_WR((HW_OCOTP_MEM4_RD() & ~BM_OCOTP_MEM4_BITS) | BF_OCOTP_MEM4_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 5 (ADDR = 0x0D). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_ana0 +{ + reg32_t U; + struct _hw_ocotp_ana0_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP bank 1, word 5 (ADDR = 0x0D). + } B; +} hw_ocotp_ana0_t; +#endif + +/* + * constants & macros for entire OCOTP_ANA0 register + */ +#define HW_OCOTP_ANA0_ADDR (REGS_OCOTP_BASE + 0x4d0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_ANA0 (*(volatile hw_ocotp_ana0_t *) HW_OCOTP_ANA0_ADDR) +#define HW_OCOTP_ANA0_RD() (HW_OCOTP_ANA0.U) +#define HW_OCOTP_ANA0_WR(v) (HW_OCOTP_ANA0.U = (v)) +#define HW_OCOTP_ANA0_SET(v) (HW_OCOTP_ANA0_WR(HW_OCOTP_ANA0_RD() | (v))) +#define HW_OCOTP_ANA0_CLR(v) (HW_OCOTP_ANA0_WR(HW_OCOTP_ANA0_RD() & ~(v))) +#define HW_OCOTP_ANA0_TOG(v) (HW_OCOTP_ANA0_WR(HW_OCOTP_ANA0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_ANA0 bitfields + */ + +/* --- Register HW_OCOTP_ANA0, field BITS[31:0] (RW) + * + * Reflects value of OTP bank 1, word 5 (ADDR = 0x0D). These bits become read-only after the + * HW_OCOTP_LOCK_ANALOG[1] bit is set. + */ + +#define BP_OCOTP_ANA0_BITS (0) //!< Bit position for OCOTP_ANA0_BITS. +#define BM_OCOTP_ANA0_BITS (0xffffffff) //!< Bit mask for OCOTP_ANA0_BITS. + +//! @brief Get value of OCOTP_ANA0_BITS from a register value. +#define BG_OCOTP_ANA0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_ANA0_BITS) >> BP_OCOTP_ANA0_BITS) + +//! @brief Format value for bitfield OCOTP_ANA0_BITS. +#define BF_OCOTP_ANA0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_ANA0_BITS) & BM_OCOTP_ANA0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_ANA0_BITS(v) (HW_OCOTP_ANA0_WR((HW_OCOTP_ANA0_RD() & ~BM_OCOTP_ANA0_BITS) | BF_OCOTP_ANA0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 6 (ADDR = 0x0E). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_ana1 +{ + reg32_t U; + struct _hw_ocotp_ana1_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP bank 1, word 6 (ADDR = 0x0E). + } B; +} hw_ocotp_ana1_t; +#endif + +/* + * constants & macros for entire OCOTP_ANA1 register + */ +#define HW_OCOTP_ANA1_ADDR (REGS_OCOTP_BASE + 0x4e0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_ANA1 (*(volatile hw_ocotp_ana1_t *) HW_OCOTP_ANA1_ADDR) +#define HW_OCOTP_ANA1_RD() (HW_OCOTP_ANA1.U) +#define HW_OCOTP_ANA1_WR(v) (HW_OCOTP_ANA1.U = (v)) +#define HW_OCOTP_ANA1_SET(v) (HW_OCOTP_ANA1_WR(HW_OCOTP_ANA1_RD() | (v))) +#define HW_OCOTP_ANA1_CLR(v) (HW_OCOTP_ANA1_WR(HW_OCOTP_ANA1_RD() & ~(v))) +#define HW_OCOTP_ANA1_TOG(v) (HW_OCOTP_ANA1_WR(HW_OCOTP_ANA1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_ANA1 bitfields + */ + +/* --- Register HW_OCOTP_ANA1, field BITS[31:0] (RW) + * + * Reflects value of OTP bank 1, word 6 (ADDR = 0x0E). These bits become read-only after the + * HW_OCOTP_LOCK_ANALOG[1] bit is set. + */ + +#define BP_OCOTP_ANA1_BITS (0) //!< Bit position for OCOTP_ANA1_BITS. +#define BM_OCOTP_ANA1_BITS (0xffffffff) //!< Bit mask for OCOTP_ANA1_BITS. + +//! @brief Get value of OCOTP_ANA1_BITS from a register value. +#define BG_OCOTP_ANA1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_ANA1_BITS) >> BP_OCOTP_ANA1_BITS) + +//! @brief Format value for bitfield OCOTP_ANA1_BITS. +#define BF_OCOTP_ANA1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_ANA1_BITS) & BM_OCOTP_ANA1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_ANA1_BITS(v) (HW_OCOTP_ANA1_WR((HW_OCOTP_ANA1_RD() & ~BM_OCOTP_ANA1_BITS) | BF_OCOTP_ANA1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 7 (ADDR = 0x0F). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_ana2 +{ + reg32_t U; + struct _hw_ocotp_ana2_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP bank 1, word 7 (ADDR = 0x0F). + } B; +} hw_ocotp_ana2_t; +#endif + +/* + * constants & macros for entire OCOTP_ANA2 register + */ +#define HW_OCOTP_ANA2_ADDR (REGS_OCOTP_BASE + 0x4f0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_ANA2 (*(volatile hw_ocotp_ana2_t *) HW_OCOTP_ANA2_ADDR) +#define HW_OCOTP_ANA2_RD() (HW_OCOTP_ANA2.U) +#define HW_OCOTP_ANA2_WR(v) (HW_OCOTP_ANA2.U = (v)) +#define HW_OCOTP_ANA2_SET(v) (HW_OCOTP_ANA2_WR(HW_OCOTP_ANA2_RD() | (v))) +#define HW_OCOTP_ANA2_CLR(v) (HW_OCOTP_ANA2_WR(HW_OCOTP_ANA2_RD() & ~(v))) +#define HW_OCOTP_ANA2_TOG(v) (HW_OCOTP_ANA2_WR(HW_OCOTP_ANA2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_ANA2 bitfields + */ + +/* --- Register HW_OCOTP_ANA2, field BITS[31:0] (RW) + * + * Reflects value of OTP bank 1, word 7 (ADDR = 0x0F). These bits become read-only after the + * HW_OCOTP_LOCK_ANALOG[1] bit is set. + */ + +#define BP_OCOTP_ANA2_BITS (0) //!< Bit position for OCOTP_ANA2_BITS. +#define BM_OCOTP_ANA2_BITS (0xffffffff) //!< Bit mask for OCOTP_ANA2_BITS. + +//! @brief Get value of OCOTP_ANA2_BITS from a register value. +#define BG_OCOTP_ANA2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_ANA2_BITS) >> BP_OCOTP_ANA2_BITS) + +//! @brief Format value for bitfield OCOTP_ANA2_BITS. +#define BF_OCOTP_ANA2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_ANA2_BITS) & BM_OCOTP_ANA2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_ANA2_BITS(v) (HW_OCOTP_ANA2_WR((HW_OCOTP_ANA2_RD() & ~BM_OCOTP_ANA2_BITS) | BF_OCOTP_ANA2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_OTPMK0 - Shadow Register for OTP Bank2 Word0 (OTPMK and CRYPTO Key) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_OTPMK0 - Shadow Register for OTP Bank2 Word0 (OTPMK and CRYPTO Key) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 2, word 0 (ADDR = + * 0x10). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_otpmk0 +{ + reg32_t U; + struct _hw_ocotp_otpmk0_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 0 (ADDR = 0x10)). + } B; +} hw_ocotp_otpmk0_t; +#endif + +/* + * constants & macros for entire OCOTP_OTPMK0 register + */ +#define HW_OCOTP_OTPMK0_ADDR (REGS_OCOTP_BASE + 0x500) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_OTPMK0 (*(volatile hw_ocotp_otpmk0_t *) HW_OCOTP_OTPMK0_ADDR) +#define HW_OCOTP_OTPMK0_RD() (HW_OCOTP_OTPMK0.U) +#define HW_OCOTP_OTPMK0_WR(v) (HW_OCOTP_OTPMK0.U = (v)) +#define HW_OCOTP_OTPMK0_SET(v) (HW_OCOTP_OTPMK0_WR(HW_OCOTP_OTPMK0_RD() | (v))) +#define HW_OCOTP_OTPMK0_CLR(v) (HW_OCOTP_OTPMK0_WR(HW_OCOTP_OTPMK0_RD() & ~(v))) +#define HW_OCOTP_OTPMK0_TOG(v) (HW_OCOTP_OTPMK0_WR(HW_OCOTP_OTPMK0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_OTPMK0 bitfields + */ + +/* --- Register HW_OCOTP_OTPMK0, field BITS[31:0] (RW) + * + * Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 0 (ADDR = 0x10)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_OTPMK bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_OTPMK0_BITS (0) //!< Bit position for OCOTP_OTPMK0_BITS. +#define BM_OCOTP_OTPMK0_BITS (0xffffffff) //!< Bit mask for OCOTP_OTPMK0_BITS. + +//! @brief Get value of OCOTP_OTPMK0_BITS from a register value. +#define BG_OCOTP_OTPMK0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_OTPMK0_BITS) >> BP_OCOTP_OTPMK0_BITS) + +//! @brief Format value for bitfield OCOTP_OTPMK0_BITS. +#define BF_OCOTP_OTPMK0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_OTPMK0_BITS) & BM_OCOTP_OTPMK0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_OTPMK0_BITS(v) (HW_OCOTP_OTPMK0_WR((HW_OCOTP_OTPMK0_RD() & ~BM_OCOTP_OTPMK0_BITS) | BF_OCOTP_OTPMK0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_OTPMK1 - Shadow Register for OTP Bank2 Word1 (OTPMK and CRYPTO Key) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_OTPMK1 - Shadow Register for OTP Bank2 Word1 (OTPMK and CRYPTO Key) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 2, word 1 (ADDR = + * 0x11). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_otpmk1 +{ + reg32_t U; + struct _hw_ocotp_otpmk1_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the OTPMK Key word1 (Copy of OTP Bank 2, word 1 (ADDR = 0x11)). + } B; +} hw_ocotp_otpmk1_t; +#endif + +/* + * constants & macros for entire OCOTP_OTPMK1 register + */ +#define HW_OCOTP_OTPMK1_ADDR (REGS_OCOTP_BASE + 0x510) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_OTPMK1 (*(volatile hw_ocotp_otpmk1_t *) HW_OCOTP_OTPMK1_ADDR) +#define HW_OCOTP_OTPMK1_RD() (HW_OCOTP_OTPMK1.U) +#define HW_OCOTP_OTPMK1_WR(v) (HW_OCOTP_OTPMK1.U = (v)) +#define HW_OCOTP_OTPMK1_SET(v) (HW_OCOTP_OTPMK1_WR(HW_OCOTP_OTPMK1_RD() | (v))) +#define HW_OCOTP_OTPMK1_CLR(v) (HW_OCOTP_OTPMK1_WR(HW_OCOTP_OTPMK1_RD() & ~(v))) +#define HW_OCOTP_OTPMK1_TOG(v) (HW_OCOTP_OTPMK1_WR(HW_OCOTP_OTPMK1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_OTPMK1 bitfields + */ + +/* --- Register HW_OCOTP_OTPMK1, field BITS[31:0] (RW) + * + * Shadow register for the OTPMK Key word1 (Copy of OTP Bank 2, word 1 (ADDR = 0x11)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_OTPMK bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_OTPMK1_BITS (0) //!< Bit position for OCOTP_OTPMK1_BITS. +#define BM_OCOTP_OTPMK1_BITS (0xffffffff) //!< Bit mask for OCOTP_OTPMK1_BITS. + +//! @brief Get value of OCOTP_OTPMK1_BITS from a register value. +#define BG_OCOTP_OTPMK1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_OTPMK1_BITS) >> BP_OCOTP_OTPMK1_BITS) + +//! @brief Format value for bitfield OCOTP_OTPMK1_BITS. +#define BF_OCOTP_OTPMK1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_OTPMK1_BITS) & BM_OCOTP_OTPMK1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_OTPMK1_BITS(v) (HW_OCOTP_OTPMK1_WR((HW_OCOTP_OTPMK1_RD() & ~BM_OCOTP_OTPMK1_BITS) | BF_OCOTP_OTPMK1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_OTPMK2 - Shadow Register for OTP Bank2 Word2 (OTPMK and CRYPTO Key) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_OTPMK2 - Shadow Register for OTP Bank2 Word2 (OTPMK and CRYPTO Key) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 2, word 2 (ADDR = + * 0x12). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_otpmk2 +{ + reg32_t U; + struct _hw_ocotp_otpmk2_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the OTPMK Key word2 (Copy of OTP Bank 2, word 2 (ADDR = 0x12)). + } B; +} hw_ocotp_otpmk2_t; +#endif + +/* + * constants & macros for entire OCOTP_OTPMK2 register + */ +#define HW_OCOTP_OTPMK2_ADDR (REGS_OCOTP_BASE + 0x520) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_OTPMK2 (*(volatile hw_ocotp_otpmk2_t *) HW_OCOTP_OTPMK2_ADDR) +#define HW_OCOTP_OTPMK2_RD() (HW_OCOTP_OTPMK2.U) +#define HW_OCOTP_OTPMK2_WR(v) (HW_OCOTP_OTPMK2.U = (v)) +#define HW_OCOTP_OTPMK2_SET(v) (HW_OCOTP_OTPMK2_WR(HW_OCOTP_OTPMK2_RD() | (v))) +#define HW_OCOTP_OTPMK2_CLR(v) (HW_OCOTP_OTPMK2_WR(HW_OCOTP_OTPMK2_RD() & ~(v))) +#define HW_OCOTP_OTPMK2_TOG(v) (HW_OCOTP_OTPMK2_WR(HW_OCOTP_OTPMK2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_OTPMK2 bitfields + */ + +/* --- Register HW_OCOTP_OTPMK2, field BITS[31:0] (RW) + * + * Shadow register for the OTPMK Key word2 (Copy of OTP Bank 2, word 2 (ADDR = 0x12)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_OTPMK bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_OTPMK2_BITS (0) //!< Bit position for OCOTP_OTPMK2_BITS. +#define BM_OCOTP_OTPMK2_BITS (0xffffffff) //!< Bit mask for OCOTP_OTPMK2_BITS. + +//! @brief Get value of OCOTP_OTPMK2_BITS from a register value. +#define BG_OCOTP_OTPMK2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_OTPMK2_BITS) >> BP_OCOTP_OTPMK2_BITS) + +//! @brief Format value for bitfield OCOTP_OTPMK2_BITS. +#define BF_OCOTP_OTPMK2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_OTPMK2_BITS) & BM_OCOTP_OTPMK2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_OTPMK2_BITS(v) (HW_OCOTP_OTPMK2_WR((HW_OCOTP_OTPMK2_RD() & ~BM_OCOTP_OTPMK2_BITS) | BF_OCOTP_OTPMK2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_OTPMK3 - Shadow Register for OTP Bank2 Word3 (OTPMK and CRYPTO Key) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_OTPMK3 - Shadow Register for OTP Bank2 Word3 (OTPMK and CRYPTO Key) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 2, word 3 (ADDR = + * 0x13). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_otpmk3 +{ + reg32_t U; + struct _hw_ocotp_otpmk3_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the OTPMK Key word3 (Copy of OTP Bank 2, word 3 (ADDR = 0x13)). + } B; +} hw_ocotp_otpmk3_t; +#endif + +/* + * constants & macros for entire OCOTP_OTPMK3 register + */ +#define HW_OCOTP_OTPMK3_ADDR (REGS_OCOTP_BASE + 0x530) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_OTPMK3 (*(volatile hw_ocotp_otpmk3_t *) HW_OCOTP_OTPMK3_ADDR) +#define HW_OCOTP_OTPMK3_RD() (HW_OCOTP_OTPMK3.U) +#define HW_OCOTP_OTPMK3_WR(v) (HW_OCOTP_OTPMK3.U = (v)) +#define HW_OCOTP_OTPMK3_SET(v) (HW_OCOTP_OTPMK3_WR(HW_OCOTP_OTPMK3_RD() | (v))) +#define HW_OCOTP_OTPMK3_CLR(v) (HW_OCOTP_OTPMK3_WR(HW_OCOTP_OTPMK3_RD() & ~(v))) +#define HW_OCOTP_OTPMK3_TOG(v) (HW_OCOTP_OTPMK3_WR(HW_OCOTP_OTPMK3_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_OTPMK3 bitfields + */ + +/* --- Register HW_OCOTP_OTPMK3, field BITS[31:0] (RW) + * + * Shadow register for the OTPMK Key word3 (Copy of OTP Bank 2, word 3 (ADDR = 0x13)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_OTPMK bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_OTPMK3_BITS (0) //!< Bit position for OCOTP_OTPMK3_BITS. +#define BM_OCOTP_OTPMK3_BITS (0xffffffff) //!< Bit mask for OCOTP_OTPMK3_BITS. + +//! @brief Get value of OCOTP_OTPMK3_BITS from a register value. +#define BG_OCOTP_OTPMK3_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_OTPMK3_BITS) >> BP_OCOTP_OTPMK3_BITS) + +//! @brief Format value for bitfield OCOTP_OTPMK3_BITS. +#define BF_OCOTP_OTPMK3_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_OTPMK3_BITS) & BM_OCOTP_OTPMK3_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_OTPMK3_BITS(v) (HW_OCOTP_OTPMK3_WR((HW_OCOTP_OTPMK3_RD() & ~BM_OCOTP_OTPMK3_BITS) | BF_OCOTP_OTPMK3_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_OTPMK4 - Shadow Register for OTP Bank2 Word4 (OTPMK Key) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_OTPMK4 - Shadow Register for OTP Bank2 Word4 (OTPMK Key) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 2, word 4 (ADDR = + * 0x14). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_otpmk4 +{ + reg32_t U; + struct _hw_ocotp_otpmk4_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the OTPMK Key word4 (Copy of OTP Bank 2, word 4 (ADDR = 0x14)). + } B; +} hw_ocotp_otpmk4_t; +#endif + +/* + * constants & macros for entire OCOTP_OTPMK4 register + */ +#define HW_OCOTP_OTPMK4_ADDR (REGS_OCOTP_BASE + 0x540) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_OTPMK4 (*(volatile hw_ocotp_otpmk4_t *) HW_OCOTP_OTPMK4_ADDR) +#define HW_OCOTP_OTPMK4_RD() (HW_OCOTP_OTPMK4.U) +#define HW_OCOTP_OTPMK4_WR(v) (HW_OCOTP_OTPMK4.U = (v)) +#define HW_OCOTP_OTPMK4_SET(v) (HW_OCOTP_OTPMK4_WR(HW_OCOTP_OTPMK4_RD() | (v))) +#define HW_OCOTP_OTPMK4_CLR(v) (HW_OCOTP_OTPMK4_WR(HW_OCOTP_OTPMK4_RD() & ~(v))) +#define HW_OCOTP_OTPMK4_TOG(v) (HW_OCOTP_OTPMK4_WR(HW_OCOTP_OTPMK4_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_OTPMK4 bitfields + */ + +/* --- Register HW_OCOTP_OTPMK4, field BITS[31:0] (RW) + * + * Shadow register for the OTPMK Key word4 (Copy of OTP Bank 2, word 4 (ADDR = 0x14)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_OTPMK bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_OTPMK4_BITS (0) //!< Bit position for OCOTP_OTPMK4_BITS. +#define BM_OCOTP_OTPMK4_BITS (0xffffffff) //!< Bit mask for OCOTP_OTPMK4_BITS. + +//! @brief Get value of OCOTP_OTPMK4_BITS from a register value. +#define BG_OCOTP_OTPMK4_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_OTPMK4_BITS) >> BP_OCOTP_OTPMK4_BITS) + +//! @brief Format value for bitfield OCOTP_OTPMK4_BITS. +#define BF_OCOTP_OTPMK4_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_OTPMK4_BITS) & BM_OCOTP_OTPMK4_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_OTPMK4_BITS(v) (HW_OCOTP_OTPMK4_WR((HW_OCOTP_OTPMK4_RD() & ~BM_OCOTP_OTPMK4_BITS) | BF_OCOTP_OTPMK4_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_OTPMK5 - Shadow Register for OTP Bank2 Word5 (OTPMK Key) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_OTPMK5 - Shadow Register for OTP Bank2 Word5 (OTPMK Key) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 2, word 5 (ADDR = + * 0x15). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_otpmk5 +{ + reg32_t U; + struct _hw_ocotp_otpmk5_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the OTPMK Key word5 (Copy of OTP Bank 2, word 5 (ADDR = 0x15)). + } B; +} hw_ocotp_otpmk5_t; +#endif + +/* + * constants & macros for entire OCOTP_OTPMK5 register + */ +#define HW_OCOTP_OTPMK5_ADDR (REGS_OCOTP_BASE + 0x550) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_OTPMK5 (*(volatile hw_ocotp_otpmk5_t *) HW_OCOTP_OTPMK5_ADDR) +#define HW_OCOTP_OTPMK5_RD() (HW_OCOTP_OTPMK5.U) +#define HW_OCOTP_OTPMK5_WR(v) (HW_OCOTP_OTPMK5.U = (v)) +#define HW_OCOTP_OTPMK5_SET(v) (HW_OCOTP_OTPMK5_WR(HW_OCOTP_OTPMK5_RD() | (v))) +#define HW_OCOTP_OTPMK5_CLR(v) (HW_OCOTP_OTPMK5_WR(HW_OCOTP_OTPMK5_RD() & ~(v))) +#define HW_OCOTP_OTPMK5_TOG(v) (HW_OCOTP_OTPMK5_WR(HW_OCOTP_OTPMK5_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_OTPMK5 bitfields + */ + +/* --- Register HW_OCOTP_OTPMK5, field BITS[31:0] (RW) + * + * Shadow register for the OTPMK Key word5 (Copy of OTP Bank 2, word 5 (ADDR = 0x15)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_OTPMK bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_OTPMK5_BITS (0) //!< Bit position for OCOTP_OTPMK5_BITS. +#define BM_OCOTP_OTPMK5_BITS (0xffffffff) //!< Bit mask for OCOTP_OTPMK5_BITS. + +//! @brief Get value of OCOTP_OTPMK5_BITS from a register value. +#define BG_OCOTP_OTPMK5_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_OTPMK5_BITS) >> BP_OCOTP_OTPMK5_BITS) + +//! @brief Format value for bitfield OCOTP_OTPMK5_BITS. +#define BF_OCOTP_OTPMK5_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_OTPMK5_BITS) & BM_OCOTP_OTPMK5_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_OTPMK5_BITS(v) (HW_OCOTP_OTPMK5_WR((HW_OCOTP_OTPMK5_RD() & ~BM_OCOTP_OTPMK5_BITS) | BF_OCOTP_OTPMK5_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_OTPMK6 - Shadow Register for OTP Bank2 Word6 (OTPMK Key) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_OTPMK6 - Shadow Register for OTP Bank2 Word6 (OTPMK Key) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 2, word 6 (ADDR = + * 0x16). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_otpmk6 +{ + reg32_t U; + struct _hw_ocotp_otpmk6_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the OTPMK Key word6 (Copy of OTP Bank 2, word 6 (ADDR = 0x16)). + } B; +} hw_ocotp_otpmk6_t; +#endif + +/* + * constants & macros for entire OCOTP_OTPMK6 register + */ +#define HW_OCOTP_OTPMK6_ADDR (REGS_OCOTP_BASE + 0x560) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_OTPMK6 (*(volatile hw_ocotp_otpmk6_t *) HW_OCOTP_OTPMK6_ADDR) +#define HW_OCOTP_OTPMK6_RD() (HW_OCOTP_OTPMK6.U) +#define HW_OCOTP_OTPMK6_WR(v) (HW_OCOTP_OTPMK6.U = (v)) +#define HW_OCOTP_OTPMK6_SET(v) (HW_OCOTP_OTPMK6_WR(HW_OCOTP_OTPMK6_RD() | (v))) +#define HW_OCOTP_OTPMK6_CLR(v) (HW_OCOTP_OTPMK6_WR(HW_OCOTP_OTPMK6_RD() & ~(v))) +#define HW_OCOTP_OTPMK6_TOG(v) (HW_OCOTP_OTPMK6_WR(HW_OCOTP_OTPMK6_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_OTPMK6 bitfields + */ + +/* --- Register HW_OCOTP_OTPMK6, field BITS[31:0] (RW) + * + * Shadow register for the OTPMK Key word6 (Copy of OTP Bank 2, word 6 (ADDR = 0x16)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_OTPMK bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_OTPMK6_BITS (0) //!< Bit position for OCOTP_OTPMK6_BITS. +#define BM_OCOTP_OTPMK6_BITS (0xffffffff) //!< Bit mask for OCOTP_OTPMK6_BITS. + +//! @brief Get value of OCOTP_OTPMK6_BITS from a register value. +#define BG_OCOTP_OTPMK6_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_OTPMK6_BITS) >> BP_OCOTP_OTPMK6_BITS) + +//! @brief Format value for bitfield OCOTP_OTPMK6_BITS. +#define BF_OCOTP_OTPMK6_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_OTPMK6_BITS) & BM_OCOTP_OTPMK6_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_OTPMK6_BITS(v) (HW_OCOTP_OTPMK6_WR((HW_OCOTP_OTPMK6_RD() & ~BM_OCOTP_OTPMK6_BITS) | BF_OCOTP_OTPMK6_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_OTPMK7 - Shadow Register for OTP Bank2 Word7 (OTPMK Key) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_OTPMK7 - Shadow Register for OTP Bank2 Word7 (OTPMK Key) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 2, word 7 (ADDR = + * 0x17). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_otpmk7 +{ + reg32_t U; + struct _hw_ocotp_otpmk7_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the OTPMK Key word7 (Copy of OTP Bank 2, word 7 (ADDR = 0x17)). + } B; +} hw_ocotp_otpmk7_t; +#endif + +/* + * constants & macros for entire OCOTP_OTPMK7 register + */ +#define HW_OCOTP_OTPMK7_ADDR (REGS_OCOTP_BASE + 0x570) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_OTPMK7 (*(volatile hw_ocotp_otpmk7_t *) HW_OCOTP_OTPMK7_ADDR) +#define HW_OCOTP_OTPMK7_RD() (HW_OCOTP_OTPMK7.U) +#define HW_OCOTP_OTPMK7_WR(v) (HW_OCOTP_OTPMK7.U = (v)) +#define HW_OCOTP_OTPMK7_SET(v) (HW_OCOTP_OTPMK7_WR(HW_OCOTP_OTPMK7_RD() | (v))) +#define HW_OCOTP_OTPMK7_CLR(v) (HW_OCOTP_OTPMK7_WR(HW_OCOTP_OTPMK7_RD() & ~(v))) +#define HW_OCOTP_OTPMK7_TOG(v) (HW_OCOTP_OTPMK7_WR(HW_OCOTP_OTPMK7_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_OTPMK7 bitfields + */ + +/* --- Register HW_OCOTP_OTPMK7, field BITS[31:0] (RW) + * + * Shadow register for the OTPMK Key word7 (Copy of OTP Bank 2, word 7 (ADDR = 0x17)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_OTPMK bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_OTPMK7_BITS (0) //!< Bit position for OCOTP_OTPMK7_BITS. +#define BM_OCOTP_OTPMK7_BITS (0xffffffff) //!< Bit mask for OCOTP_OTPMK7_BITS. + +//! @brief Get value of OCOTP_OTPMK7_BITS from a register value. +#define BG_OCOTP_OTPMK7_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_OTPMK7_BITS) >> BP_OCOTP_OTPMK7_BITS) + +//! @brief Format value for bitfield OCOTP_OTPMK7_BITS. +#define BF_OCOTP_OTPMK7_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_OTPMK7_BITS) & BM_OCOTP_OTPMK7_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_OTPMK7_BITS(v) (HW_OCOTP_OTPMK7_WR((HW_OCOTP_OTPMK7_RD() & ~BM_OCOTP_OTPMK7_BITS) | BF_OCOTP_OTPMK7_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 0 (ADDR = + * 0x18). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk0 +{ + reg32_t U; + struct _hw_ocotp_srk0_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x1C)). + } B; +} hw_ocotp_srk0_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK0 register + */ +#define HW_OCOTP_SRK0_ADDR (REGS_OCOTP_BASE + 0x580) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK0 (*(volatile hw_ocotp_srk0_t *) HW_OCOTP_SRK0_ADDR) +#define HW_OCOTP_SRK0_RD() (HW_OCOTP_SRK0.U) +#define HW_OCOTP_SRK0_WR(v) (HW_OCOTP_SRK0.U = (v)) +#define HW_OCOTP_SRK0_SET(v) (HW_OCOTP_SRK0_WR(HW_OCOTP_SRK0_RD() | (v))) +#define HW_OCOTP_SRK0_CLR(v) (HW_OCOTP_SRK0_WR(HW_OCOTP_SRK0_RD() & ~(v))) +#define HW_OCOTP_SRK0_TOG(v) (HW_OCOTP_SRK0_WR(HW_OCOTP_SRK0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK0 bitfields + */ + +/* --- Register HW_OCOTP_SRK0, field BITS[31:0] (RW) + * + * Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = + * 0x1C)). These bits become read-only after the HW_OCOTP_LOCK_SRK bit is set. + */ + +#define BP_OCOTP_SRK0_BITS (0) //!< Bit position for OCOTP_SRK0_BITS. +#define BM_OCOTP_SRK0_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK0_BITS. + +//! @brief Get value of OCOTP_SRK0_BITS from a register value. +#define BG_OCOTP_SRK0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK0_BITS) >> BP_OCOTP_SRK0_BITS) + +//! @brief Format value for bitfield OCOTP_SRK0_BITS. +#define BF_OCOTP_SRK0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK0_BITS) & BM_OCOTP_SRK0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK0_BITS(v) (HW_OCOTP_SRK0_WR((HW_OCOTP_SRK0_RD() & ~BM_OCOTP_SRK0_BITS) | BF_OCOTP_SRK0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 1 (ADDR = + * 0x19). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk1 +{ + reg32_t U; + struct _hw_ocotp_srk1_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x1D)). + } B; +} hw_ocotp_srk1_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK1 register + */ +#define HW_OCOTP_SRK1_ADDR (REGS_OCOTP_BASE + 0x590) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK1 (*(volatile hw_ocotp_srk1_t *) HW_OCOTP_SRK1_ADDR) +#define HW_OCOTP_SRK1_RD() (HW_OCOTP_SRK1.U) +#define HW_OCOTP_SRK1_WR(v) (HW_OCOTP_SRK1.U = (v)) +#define HW_OCOTP_SRK1_SET(v) (HW_OCOTP_SRK1_WR(HW_OCOTP_SRK1_RD() | (v))) +#define HW_OCOTP_SRK1_CLR(v) (HW_OCOTP_SRK1_WR(HW_OCOTP_SRK1_RD() & ~(v))) +#define HW_OCOTP_SRK1_TOG(v) (HW_OCOTP_SRK1_WR(HW_OCOTP_SRK1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK1 bitfields + */ + +/* --- Register HW_OCOTP_SRK1, field BITS[31:0] (RW) + * + * Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = + * 0x1D)). These bits become read-only after the HW_OCOTP_LOCK_SRK bit is set. + */ + +#define BP_OCOTP_SRK1_BITS (0) //!< Bit position for OCOTP_SRK1_BITS. +#define BM_OCOTP_SRK1_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK1_BITS. + +//! @brief Get value of OCOTP_SRK1_BITS from a register value. +#define BG_OCOTP_SRK1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK1_BITS) >> BP_OCOTP_SRK1_BITS) + +//! @brief Format value for bitfield OCOTP_SRK1_BITS. +#define BF_OCOTP_SRK1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK1_BITS) & BM_OCOTP_SRK1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK1_BITS(v) (HW_OCOTP_SRK1_WR((HW_OCOTP_SRK1_RD() & ~BM_OCOTP_SRK1_BITS) | BF_OCOTP_SRK1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 2 (ADDR = + * 0x1A). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk2 +{ + reg32_t U; + struct _hw_ocotp_srk2_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1E)). + } B; +} hw_ocotp_srk2_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK2 register + */ +#define HW_OCOTP_SRK2_ADDR (REGS_OCOTP_BASE + 0x5a0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK2 (*(volatile hw_ocotp_srk2_t *) HW_OCOTP_SRK2_ADDR) +#define HW_OCOTP_SRK2_RD() (HW_OCOTP_SRK2.U) +#define HW_OCOTP_SRK2_WR(v) (HW_OCOTP_SRK2.U = (v)) +#define HW_OCOTP_SRK2_SET(v) (HW_OCOTP_SRK2_WR(HW_OCOTP_SRK2_RD() | (v))) +#define HW_OCOTP_SRK2_CLR(v) (HW_OCOTP_SRK2_WR(HW_OCOTP_SRK2_RD() & ~(v))) +#define HW_OCOTP_SRK2_TOG(v) (HW_OCOTP_SRK2_WR(HW_OCOTP_SRK2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK2 bitfields + */ + +/* --- Register HW_OCOTP_SRK2, field BITS[31:0] (RW) + * + * Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = + * 0x1E)). These bits become read-only after the HW_OCOTP_LOCK_SRK bit is set. + */ + +#define BP_OCOTP_SRK2_BITS (0) //!< Bit position for OCOTP_SRK2_BITS. +#define BM_OCOTP_SRK2_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK2_BITS. + +//! @brief Get value of OCOTP_SRK2_BITS from a register value. +#define BG_OCOTP_SRK2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK2_BITS) >> BP_OCOTP_SRK2_BITS) + +//! @brief Format value for bitfield OCOTP_SRK2_BITS. +#define BF_OCOTP_SRK2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK2_BITS) & BM_OCOTP_SRK2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK2_BITS(v) (HW_OCOTP_SRK2_WR((HW_OCOTP_SRK2_RD() & ~BM_OCOTP_SRK2_BITS) | BF_OCOTP_SRK2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 3 (ADDR = + * 0x1B). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk3 +{ + reg32_t U; + struct _hw_ocotp_srk3_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1F)). + } B; +} hw_ocotp_srk3_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK3 register + */ +#define HW_OCOTP_SRK3_ADDR (REGS_OCOTP_BASE + 0x5b0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK3 (*(volatile hw_ocotp_srk3_t *) HW_OCOTP_SRK3_ADDR) +#define HW_OCOTP_SRK3_RD() (HW_OCOTP_SRK3.U) +#define HW_OCOTP_SRK3_WR(v) (HW_OCOTP_SRK3.U = (v)) +#define HW_OCOTP_SRK3_SET(v) (HW_OCOTP_SRK3_WR(HW_OCOTP_SRK3_RD() | (v))) +#define HW_OCOTP_SRK3_CLR(v) (HW_OCOTP_SRK3_WR(HW_OCOTP_SRK3_RD() & ~(v))) +#define HW_OCOTP_SRK3_TOG(v) (HW_OCOTP_SRK3_WR(HW_OCOTP_SRK3_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK3 bitfields + */ + +/* --- Register HW_OCOTP_SRK3, field BITS[31:0] (RW) + * + * Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = + * 0x1F)). These bits become read-only after the HW_OCOTP_LOCK_SRK bit is set. + */ + +#define BP_OCOTP_SRK3_BITS (0) //!< Bit position for OCOTP_SRK3_BITS. +#define BM_OCOTP_SRK3_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK3_BITS. + +//! @brief Get value of OCOTP_SRK3_BITS from a register value. +#define BG_OCOTP_SRK3_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK3_BITS) >> BP_OCOTP_SRK3_BITS) + +//! @brief Format value for bitfield OCOTP_SRK3_BITS. +#define BF_OCOTP_SRK3_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK3_BITS) & BM_OCOTP_SRK3_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK3_BITS(v) (HW_OCOTP_SRK3_WR((HW_OCOTP_SRK3_RD() & ~BM_OCOTP_SRK3_BITS) | BF_OCOTP_SRK3_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 4 (ADDR = + * 0x1C). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk4 +{ + reg32_t U; + struct _hw_ocotp_srk4_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x20)). + } B; +} hw_ocotp_srk4_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK4 register + */ +#define HW_OCOTP_SRK4_ADDR (REGS_OCOTP_BASE + 0x5c0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK4 (*(volatile hw_ocotp_srk4_t *) HW_OCOTP_SRK4_ADDR) +#define HW_OCOTP_SRK4_RD() (HW_OCOTP_SRK4.U) +#define HW_OCOTP_SRK4_WR(v) (HW_OCOTP_SRK4.U = (v)) +#define HW_OCOTP_SRK4_SET(v) (HW_OCOTP_SRK4_WR(HW_OCOTP_SRK4_RD() | (v))) +#define HW_OCOTP_SRK4_CLR(v) (HW_OCOTP_SRK4_WR(HW_OCOTP_SRK4_RD() & ~(v))) +#define HW_OCOTP_SRK4_TOG(v) (HW_OCOTP_SRK4_WR(HW_OCOTP_SRK4_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK4 bitfields + */ + +/* --- Register HW_OCOTP_SRK4, field BITS[31:0] (RW) + * + * Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = + * 0x20)). These bits become read-only after the HW_OCOTP_LOCK_SRK bit is set. + */ + +#define BP_OCOTP_SRK4_BITS (0) //!< Bit position for OCOTP_SRK4_BITS. +#define BM_OCOTP_SRK4_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK4_BITS. + +//! @brief Get value of OCOTP_SRK4_BITS from a register value. +#define BG_OCOTP_SRK4_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK4_BITS) >> BP_OCOTP_SRK4_BITS) + +//! @brief Format value for bitfield OCOTP_SRK4_BITS. +#define BF_OCOTP_SRK4_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK4_BITS) & BM_OCOTP_SRK4_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK4_BITS(v) (HW_OCOTP_SRK4_WR((HW_OCOTP_SRK4_RD() & ~BM_OCOTP_SRK4_BITS) | BF_OCOTP_SRK4_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 5 (ADDR = + * 0x1D). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk5 +{ + reg32_t U; + struct _hw_ocotp_srk5_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x21)). + } B; +} hw_ocotp_srk5_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK5 register + */ +#define HW_OCOTP_SRK5_ADDR (REGS_OCOTP_BASE + 0x5d0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK5 (*(volatile hw_ocotp_srk5_t *) HW_OCOTP_SRK5_ADDR) +#define HW_OCOTP_SRK5_RD() (HW_OCOTP_SRK5.U) +#define HW_OCOTP_SRK5_WR(v) (HW_OCOTP_SRK5.U = (v)) +#define HW_OCOTP_SRK5_SET(v) (HW_OCOTP_SRK5_WR(HW_OCOTP_SRK5_RD() | (v))) +#define HW_OCOTP_SRK5_CLR(v) (HW_OCOTP_SRK5_WR(HW_OCOTP_SRK5_RD() & ~(v))) +#define HW_OCOTP_SRK5_TOG(v) (HW_OCOTP_SRK5_WR(HW_OCOTP_SRK5_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK5 bitfields + */ + +/* --- Register HW_OCOTP_SRK5, field BITS[31:0] (RW) + * + * Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = + * 0x21)). These bits become read-only after the HW_OCOTP_LOCK_SRK bit is set. + */ + +#define BP_OCOTP_SRK5_BITS (0) //!< Bit position for OCOTP_SRK5_BITS. +#define BM_OCOTP_SRK5_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK5_BITS. + +//! @brief Get value of OCOTP_SRK5_BITS from a register value. +#define BG_OCOTP_SRK5_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK5_BITS) >> BP_OCOTP_SRK5_BITS) + +//! @brief Format value for bitfield OCOTP_SRK5_BITS. +#define BF_OCOTP_SRK5_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK5_BITS) & BM_OCOTP_SRK5_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK5_BITS(v) (HW_OCOTP_SRK5_WR((HW_OCOTP_SRK5_RD() & ~BM_OCOTP_SRK5_BITS) | BF_OCOTP_SRK5_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 6 (ADDR = + * 0x1E). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk6 +{ + reg32_t U; + struct _hw_ocotp_srk6_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x22)). + } B; +} hw_ocotp_srk6_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK6 register + */ +#define HW_OCOTP_SRK6_ADDR (REGS_OCOTP_BASE + 0x5e0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK6 (*(volatile hw_ocotp_srk6_t *) HW_OCOTP_SRK6_ADDR) +#define HW_OCOTP_SRK6_RD() (HW_OCOTP_SRK6.U) +#define HW_OCOTP_SRK6_WR(v) (HW_OCOTP_SRK6.U = (v)) +#define HW_OCOTP_SRK6_SET(v) (HW_OCOTP_SRK6_WR(HW_OCOTP_SRK6_RD() | (v))) +#define HW_OCOTP_SRK6_CLR(v) (HW_OCOTP_SRK6_WR(HW_OCOTP_SRK6_RD() & ~(v))) +#define HW_OCOTP_SRK6_TOG(v) (HW_OCOTP_SRK6_WR(HW_OCOTP_SRK6_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK6 bitfields + */ + +/* --- Register HW_OCOTP_SRK6, field BITS[31:0] (RW) + * + * Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = + * 0x22)). These bits become read-only after the HW_OCOTP_LOCK_SRK bit is set. + */ + +#define BP_OCOTP_SRK6_BITS (0) //!< Bit position for OCOTP_SRK6_BITS. +#define BM_OCOTP_SRK6_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK6_BITS. + +//! @brief Get value of OCOTP_SRK6_BITS from a register value. +#define BG_OCOTP_SRK6_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK6_BITS) >> BP_OCOTP_SRK6_BITS) + +//! @brief Format value for bitfield OCOTP_SRK6_BITS. +#define BF_OCOTP_SRK6_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK6_BITS) & BM_OCOTP_SRK6_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK6_BITS(v) (HW_OCOTP_SRK6_WR((HW_OCOTP_SRK6_RD() & ~BM_OCOTP_SRK6_BITS) | BF_OCOTP_SRK6_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 7 (ADDR = + * 0x1F). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk7 +{ + reg32_t U; + struct _hw_ocotp_srk7_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x23)). + } B; +} hw_ocotp_srk7_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK7 register + */ +#define HW_OCOTP_SRK7_ADDR (REGS_OCOTP_BASE + 0x5f0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK7 (*(volatile hw_ocotp_srk7_t *) HW_OCOTP_SRK7_ADDR) +#define HW_OCOTP_SRK7_RD() (HW_OCOTP_SRK7.U) +#define HW_OCOTP_SRK7_WR(v) (HW_OCOTP_SRK7.U = (v)) +#define HW_OCOTP_SRK7_SET(v) (HW_OCOTP_SRK7_WR(HW_OCOTP_SRK7_RD() | (v))) +#define HW_OCOTP_SRK7_CLR(v) (HW_OCOTP_SRK7_WR(HW_OCOTP_SRK7_RD() & ~(v))) +#define HW_OCOTP_SRK7_TOG(v) (HW_OCOTP_SRK7_WR(HW_OCOTP_SRK7_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK7 bitfields + */ + +/* --- Register HW_OCOTP_SRK7, field BITS[31:0] (RW) + * + * Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = + * 0x23)). These bits become read-only after the HW_OCOTP_LOCK_SRK bit is set. + */ + +#define BP_OCOTP_SRK7_BITS (0) //!< Bit position for OCOTP_SRK7_BITS. +#define BM_OCOTP_SRK7_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK7_BITS. + +//! @brief Get value of OCOTP_SRK7_BITS from a register value. +#define BG_OCOTP_SRK7_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK7_BITS) >> BP_OCOTP_SRK7_BITS) + +//! @brief Format value for bitfield OCOTP_SRK7_BITS. +#define BF_OCOTP_SRK7_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK7_BITS) & BM_OCOTP_SRK7_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK7_BITS(v) (HW_OCOTP_SRK7_WR((HW_OCOTP_SRK7_RD() & ~BM_OCOTP_SRK7_BITS) | BF_OCOTP_SRK7_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 4, word 0 (ADDR = 0x20). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_resp0 +{ + reg32_t U; + struct _hw_ocotp_resp0_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20)). + } B; +} hw_ocotp_resp0_t; +#endif + +/* + * constants & macros for entire OCOTP_RESP0 register + */ +#define HW_OCOTP_RESP0_ADDR (REGS_OCOTP_BASE + 0x600) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_RESP0 (*(volatile hw_ocotp_resp0_t *) HW_OCOTP_RESP0_ADDR) +#define HW_OCOTP_RESP0_RD() (HW_OCOTP_RESP0.U) +#define HW_OCOTP_RESP0_WR(v) (HW_OCOTP_RESP0.U = (v)) +#define HW_OCOTP_RESP0_SET(v) (HW_OCOTP_RESP0_WR(HW_OCOTP_RESP0_RD() | (v))) +#define HW_OCOTP_RESP0_CLR(v) (HW_OCOTP_RESP0_WR(HW_OCOTP_RESP0_RD() & ~(v))) +#define HW_OCOTP_RESP0_TOG(v) (HW_OCOTP_RESP0_WR(HW_OCOTP_RESP0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_RESP0 bitfields + */ + +/* --- Register HW_OCOTP_RESP0, field BITS[31:0] (RW) + * + * Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_SJC_RESP bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_RESP0_BITS (0) //!< Bit position for OCOTP_RESP0_BITS. +#define BM_OCOTP_RESP0_BITS (0xffffffff) //!< Bit mask for OCOTP_RESP0_BITS. + +//! @brief Get value of OCOTP_RESP0_BITS from a register value. +#define BG_OCOTP_RESP0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_RESP0_BITS) >> BP_OCOTP_RESP0_BITS) + +//! @brief Format value for bitfield OCOTP_RESP0_BITS. +#define BF_OCOTP_RESP0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_RESP0_BITS) & BM_OCOTP_RESP0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_RESP0_BITS(v) (HW_OCOTP_RESP0_WR((HW_OCOTP_RESP0_RD() & ~BM_OCOTP_RESP0_BITS) | BF_OCOTP_RESP0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HSJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HSJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 4, word 1 (ADDR = 0x21). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hsjc_resp1 +{ + reg32_t U; + struct _hw_ocotp_hsjc_resp1_bitfields + { + unsigned BITS : 32; //!< [31:0] Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21)). + } B; +} hw_ocotp_hsjc_resp1_t; +#endif + +/* + * constants & macros for entire OCOTP_HSJC_RESP1 register + */ +#define HW_OCOTP_HSJC_RESP1_ADDR (REGS_OCOTP_BASE + 0x610) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HSJC_RESP1 (*(volatile hw_ocotp_hsjc_resp1_t *) HW_OCOTP_HSJC_RESP1_ADDR) +#define HW_OCOTP_HSJC_RESP1_RD() (HW_OCOTP_HSJC_RESP1.U) +#define HW_OCOTP_HSJC_RESP1_WR(v) (HW_OCOTP_HSJC_RESP1.U = (v)) +#define HW_OCOTP_HSJC_RESP1_SET(v) (HW_OCOTP_HSJC_RESP1_WR(HW_OCOTP_HSJC_RESP1_RD() | (v))) +#define HW_OCOTP_HSJC_RESP1_CLR(v) (HW_OCOTP_HSJC_RESP1_WR(HW_OCOTP_HSJC_RESP1_RD() & ~(v))) +#define HW_OCOTP_HSJC_RESP1_TOG(v) (HW_OCOTP_HSJC_RESP1_WR(HW_OCOTP_HSJC_RESP1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HSJC_RESP1 bitfields + */ + +/* --- Register HW_OCOTP_HSJC_RESP1, field BITS[31:0] (RW) + * + * Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21)). These bits + * can be not read and wrotten after the HW_OCOTP_LOCK_SJC_RESP bit is set. If read, returns + * 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR]. + */ + +#define BP_OCOTP_HSJC_RESP1_BITS (0) //!< Bit position for OCOTP_HSJC_RESP1_BITS. +#define BM_OCOTP_HSJC_RESP1_BITS (0xffffffff) //!< Bit mask for OCOTP_HSJC_RESP1_BITS. + +//! @brief Get value of OCOTP_HSJC_RESP1_BITS from a register value. +#define BG_OCOTP_HSJC_RESP1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HSJC_RESP1_BITS) >> BP_OCOTP_HSJC_RESP1_BITS) + +//! @brief Format value for bitfield OCOTP_HSJC_RESP1_BITS. +#define BF_OCOTP_HSJC_RESP1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HSJC_RESP1_BITS) & BM_OCOTP_HSJC_RESP1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HSJC_RESP1_BITS(v) (HW_OCOTP_HSJC_RESP1_WR((HW_OCOTP_HSJC_RESP1_RD() & ~BM_OCOTP_HSJC_RESP1_BITS) | BF_OCOTP_HSJC_RESP1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_MAC0 - Value of OTP Bank4 Word2 (MAC Address) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_MAC0 - Value of OTP Bank4 Word2 (MAC Address) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 4, word 2 (ADDR = 0x22). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_mac0 +{ + reg32_t U; + struct _hw_ocotp_mac0_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 4, word 2 (ADDR = 0x22). + } B; +} hw_ocotp_mac0_t; +#endif + +/* + * constants & macros for entire OCOTP_MAC0 register + */ +#define HW_OCOTP_MAC0_ADDR (REGS_OCOTP_BASE + 0x620) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_MAC0 (*(volatile hw_ocotp_mac0_t *) HW_OCOTP_MAC0_ADDR) +#define HW_OCOTP_MAC0_RD() (HW_OCOTP_MAC0.U) +#define HW_OCOTP_MAC0_WR(v) (HW_OCOTP_MAC0.U = (v)) +#define HW_OCOTP_MAC0_SET(v) (HW_OCOTP_MAC0_WR(HW_OCOTP_MAC0_RD() | (v))) +#define HW_OCOTP_MAC0_CLR(v) (HW_OCOTP_MAC0_WR(HW_OCOTP_MAC0_RD() & ~(v))) +#define HW_OCOTP_MAC0_TOG(v) (HW_OCOTP_MAC0_WR(HW_OCOTP_MAC0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_MAC0 bitfields + */ + +/* --- Register HW_OCOTP_MAC0, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 4, word 2 (ADDR = 0x22). + */ + +#define BP_OCOTP_MAC0_BITS (0) //!< Bit position for OCOTP_MAC0_BITS. +#define BM_OCOTP_MAC0_BITS (0xffffffff) //!< Bit mask for OCOTP_MAC0_BITS. + +//! @brief Get value of OCOTP_MAC0_BITS from a register value. +#define BG_OCOTP_MAC0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_MAC0_BITS) >> BP_OCOTP_MAC0_BITS) + +//! @brief Format value for bitfield OCOTP_MAC0_BITS. +#define BF_OCOTP_MAC0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_MAC0_BITS) & BM_OCOTP_MAC0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_MAC0_BITS(v) (HW_OCOTP_MAC0_WR((HW_OCOTP_MAC0_RD() & ~BM_OCOTP_MAC0_BITS) | BF_OCOTP_MAC0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_MAC1 - Value of OTP Bank4 Word3 (MAC Address) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_MAC1 - Value of OTP Bank4 Word3 (MAC Address) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 4, word 3 (ADDR = 0x23). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_mac1 +{ + reg32_t U; + struct _hw_ocotp_mac1_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 4, word 3 (ADDR = 0x23). + } B; +} hw_ocotp_mac1_t; +#endif + +/* + * constants & macros for entire OCOTP_MAC1 register + */ +#define HW_OCOTP_MAC1_ADDR (REGS_OCOTP_BASE + 0x630) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_MAC1 (*(volatile hw_ocotp_mac1_t *) HW_OCOTP_MAC1_ADDR) +#define HW_OCOTP_MAC1_RD() (HW_OCOTP_MAC1.U) +#define HW_OCOTP_MAC1_WR(v) (HW_OCOTP_MAC1.U = (v)) +#define HW_OCOTP_MAC1_SET(v) (HW_OCOTP_MAC1_WR(HW_OCOTP_MAC1_RD() | (v))) +#define HW_OCOTP_MAC1_CLR(v) (HW_OCOTP_MAC1_WR(HW_OCOTP_MAC1_RD() & ~(v))) +#define HW_OCOTP_MAC1_TOG(v) (HW_OCOTP_MAC1_WR(HW_OCOTP_MAC1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_MAC1 bitfields + */ + +/* --- Register HW_OCOTP_MAC1, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 4, word 3 (ADDR = 0x23). + */ + +#define BP_OCOTP_MAC1_BITS (0) //!< Bit position for OCOTP_MAC1_BITS. +#define BM_OCOTP_MAC1_BITS (0xffffffff) //!< Bit mask for OCOTP_MAC1_BITS. + +//! @brief Get value of OCOTP_MAC1_BITS from a register value. +#define BG_OCOTP_MAC1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_MAC1_BITS) >> BP_OCOTP_MAC1_BITS) + +//! @brief Format value for bitfield OCOTP_MAC1_BITS. +#define BF_OCOTP_MAC1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_MAC1_BITS) & BM_OCOTP_MAC1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_MAC1_BITS(v) (HW_OCOTP_MAC1_WR((HW_OCOTP_MAC1_RD() & ~BM_OCOTP_MAC1_BITS) | BF_OCOTP_MAC1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KSV0 - Value of OTP Bank4 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KSV0 - Value of OTP Bank4 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 4, word 4 (ADDR = 0x24). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_ksv0 +{ + reg32_t U; + struct _hw_ocotp_hdcp_ksv0_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 4, word 4 (ADDR = 0x24). + } B; +} hw_ocotp_hdcp_ksv0_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KSV0 register + */ +#define HW_OCOTP_HDCP_KSV0_ADDR (REGS_OCOTP_BASE + 0x640) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KSV0 (*(volatile hw_ocotp_hdcp_ksv0_t *) HW_OCOTP_HDCP_KSV0_ADDR) +#define HW_OCOTP_HDCP_KSV0_RD() (HW_OCOTP_HDCP_KSV0.U) +#define HW_OCOTP_HDCP_KSV0_WR(v) (HW_OCOTP_HDCP_KSV0.U = (v)) +#define HW_OCOTP_HDCP_KSV0_SET(v) (HW_OCOTP_HDCP_KSV0_WR(HW_OCOTP_HDCP_KSV0_RD() | (v))) +#define HW_OCOTP_HDCP_KSV0_CLR(v) (HW_OCOTP_HDCP_KSV0_WR(HW_OCOTP_HDCP_KSV0_RD() & ~(v))) +#define HW_OCOTP_HDCP_KSV0_TOG(v) (HW_OCOTP_HDCP_KSV0_WR(HW_OCOTP_HDCP_KSV0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KSV0 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KSV0, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 4, word 4 (ADDR = 0x24). + */ + +#define BP_OCOTP_HDCP_KSV0_BITS (0) //!< Bit position for OCOTP_HDCP_KSV0_BITS. +#define BM_OCOTP_HDCP_KSV0_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KSV0_BITS. + +//! @brief Get value of OCOTP_HDCP_KSV0_BITS from a register value. +#define BG_OCOTP_HDCP_KSV0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KSV0_BITS) >> BP_OCOTP_HDCP_KSV0_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KSV0_BITS. +#define BF_OCOTP_HDCP_KSV0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KSV0_BITS) & BM_OCOTP_HDCP_KSV0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KSV0_BITS(v) (HW_OCOTP_HDCP_KSV0_WR((HW_OCOTP_HDCP_KSV0_RD() & ~BM_OCOTP_HDCP_KSV0_BITS) | BF_OCOTP_HDCP_KSV0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KSV1 - Value of OTP Bank4 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KSV1 - Value of OTP Bank4 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 4, word 5 (ADDR = 0x25). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_ksv1 +{ + reg32_t U; + struct _hw_ocotp_hdcp_ksv1_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 4, word 5 (ADDR = 0x25). + } B; +} hw_ocotp_hdcp_ksv1_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KSV1 register + */ +#define HW_OCOTP_HDCP_KSV1_ADDR (REGS_OCOTP_BASE + 0x650) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KSV1 (*(volatile hw_ocotp_hdcp_ksv1_t *) HW_OCOTP_HDCP_KSV1_ADDR) +#define HW_OCOTP_HDCP_KSV1_RD() (HW_OCOTP_HDCP_KSV1.U) +#define HW_OCOTP_HDCP_KSV1_WR(v) (HW_OCOTP_HDCP_KSV1.U = (v)) +#define HW_OCOTP_HDCP_KSV1_SET(v) (HW_OCOTP_HDCP_KSV1_WR(HW_OCOTP_HDCP_KSV1_RD() | (v))) +#define HW_OCOTP_HDCP_KSV1_CLR(v) (HW_OCOTP_HDCP_KSV1_WR(HW_OCOTP_HDCP_KSV1_RD() & ~(v))) +#define HW_OCOTP_HDCP_KSV1_TOG(v) (HW_OCOTP_HDCP_KSV1_WR(HW_OCOTP_HDCP_KSV1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KSV1 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KSV1, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 4, word 5 (ADDR = 0x25). + */ + +#define BP_OCOTP_HDCP_KSV1_BITS (0) //!< Bit position for OCOTP_HDCP_KSV1_BITS. +#define BM_OCOTP_HDCP_KSV1_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KSV1_BITS. + +//! @brief Get value of OCOTP_HDCP_KSV1_BITS from a register value. +#define BG_OCOTP_HDCP_KSV1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KSV1_BITS) >> BP_OCOTP_HDCP_KSV1_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KSV1_BITS. +#define BF_OCOTP_HDCP_KSV1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KSV1_BITS) & BM_OCOTP_HDCP_KSV1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KSV1_BITS(v) (HW_OCOTP_HDCP_KSV1_WR((HW_OCOTP_HDCP_KSV1_RD() & ~BM_OCOTP_HDCP_KSV1_BITS) | BF_OCOTP_HDCP_KSV1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_GP1 - Value of OTP Bank4 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_GP1 - Value of OTP Bank4 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 4, word 6 (ADDR = 0x26). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_gp1 +{ + reg32_t U; + struct _hw_ocotp_gp1_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 4, word 6 (ADDR = 0x26). + } B; +} hw_ocotp_gp1_t; +#endif + +/* + * constants & macros for entire OCOTP_GP1 register + */ +#define HW_OCOTP_GP1_ADDR (REGS_OCOTP_BASE + 0x660) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_GP1 (*(volatile hw_ocotp_gp1_t *) HW_OCOTP_GP1_ADDR) +#define HW_OCOTP_GP1_RD() (HW_OCOTP_GP1.U) +#define HW_OCOTP_GP1_WR(v) (HW_OCOTP_GP1.U = (v)) +#define HW_OCOTP_GP1_SET(v) (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() | (v))) +#define HW_OCOTP_GP1_CLR(v) (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() & ~(v))) +#define HW_OCOTP_GP1_TOG(v) (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_GP1 bitfields + */ + +/* --- Register HW_OCOTP_GP1, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 4, word 6 (ADDR = 0x26). + */ + +#define BP_OCOTP_GP1_BITS (0) //!< Bit position for OCOTP_GP1_BITS. +#define BM_OCOTP_GP1_BITS (0xffffffff) //!< Bit mask for OCOTP_GP1_BITS. + +//! @brief Get value of OCOTP_GP1_BITS from a register value. +#define BG_OCOTP_GP1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_GP1_BITS) >> BP_OCOTP_GP1_BITS) + +//! @brief Format value for bitfield OCOTP_GP1_BITS. +#define BF_OCOTP_GP1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_GP1_BITS) & BM_OCOTP_GP1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_GP1_BITS(v) (HW_OCOTP_GP1_WR((HW_OCOTP_GP1_RD() & ~BM_OCOTP_GP1_BITS) | BF_OCOTP_GP1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_GP2 - Value of OTP Bank4 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_GP2 - Value of OTP Bank4 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 4, word 7 (ADDR = 0x27). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_gp2 +{ + reg32_t U; + struct _hw_ocotp_gp2_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 4, word 7 (ADDR = 0x27). + } B; +} hw_ocotp_gp2_t; +#endif + +/* + * constants & macros for entire OCOTP_GP2 register + */ +#define HW_OCOTP_GP2_ADDR (REGS_OCOTP_BASE + 0x670) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_GP2 (*(volatile hw_ocotp_gp2_t *) HW_OCOTP_GP2_ADDR) +#define HW_OCOTP_GP2_RD() (HW_OCOTP_GP2.U) +#define HW_OCOTP_GP2_WR(v) (HW_OCOTP_GP2.U = (v)) +#define HW_OCOTP_GP2_SET(v) (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() | (v))) +#define HW_OCOTP_GP2_CLR(v) (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() & ~(v))) +#define HW_OCOTP_GP2_TOG(v) (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_GP2 bitfields + */ + +/* --- Register HW_OCOTP_GP2, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 4, word 7 (ADDR = 0x27). + */ + +#define BP_OCOTP_GP2_BITS (0) //!< Bit position for OCOTP_GP2_BITS. +#define BM_OCOTP_GP2_BITS (0xffffffff) //!< Bit mask for OCOTP_GP2_BITS. + +//! @brief Get value of OCOTP_GP2_BITS from a register value. +#define BG_OCOTP_GP2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_GP2_BITS) >> BP_OCOTP_GP2_BITS) + +//! @brief Format value for bitfield OCOTP_GP2_BITS. +#define BF_OCOTP_GP2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_GP2_BITS) & BM_OCOTP_GP2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_GP2_BITS(v) (HW_OCOTP_GP2_WR((HW_OCOTP_GP2_RD() & ~BM_OCOTP_GP2_BITS) | BF_OCOTP_GP2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_DTCP_KEY0 - Value of OTP Bank5 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_DTCP_KEY0 - Value of OTP Bank5 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 5, word 0 (ADDR = 0x28). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_dtcp_key0 +{ + reg32_t U; + struct _hw_ocotp_dtcp_key0_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 5, word 0 (ADDR = 0x28). + } B; +} hw_ocotp_dtcp_key0_t; +#endif + +/* + * constants & macros for entire OCOTP_DTCP_KEY0 register + */ +#define HW_OCOTP_DTCP_KEY0_ADDR (REGS_OCOTP_BASE + 0x680) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_DTCP_KEY0 (*(volatile hw_ocotp_dtcp_key0_t *) HW_OCOTP_DTCP_KEY0_ADDR) +#define HW_OCOTP_DTCP_KEY0_RD() (HW_OCOTP_DTCP_KEY0.U) +#define HW_OCOTP_DTCP_KEY0_WR(v) (HW_OCOTP_DTCP_KEY0.U = (v)) +#define HW_OCOTP_DTCP_KEY0_SET(v) (HW_OCOTP_DTCP_KEY0_WR(HW_OCOTP_DTCP_KEY0_RD() | (v))) +#define HW_OCOTP_DTCP_KEY0_CLR(v) (HW_OCOTP_DTCP_KEY0_WR(HW_OCOTP_DTCP_KEY0_RD() & ~(v))) +#define HW_OCOTP_DTCP_KEY0_TOG(v) (HW_OCOTP_DTCP_KEY0_WR(HW_OCOTP_DTCP_KEY0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_DTCP_KEY0 bitfields + */ + +/* --- Register HW_OCOTP_DTCP_KEY0, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 5, word 0 (ADDR = 0x28). + */ + +#define BP_OCOTP_DTCP_KEY0_BITS (0) //!< Bit position for OCOTP_DTCP_KEY0_BITS. +#define BM_OCOTP_DTCP_KEY0_BITS (0xffffffff) //!< Bit mask for OCOTP_DTCP_KEY0_BITS. + +//! @brief Get value of OCOTP_DTCP_KEY0_BITS from a register value. +#define BG_OCOTP_DTCP_KEY0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_DTCP_KEY0_BITS) >> BP_OCOTP_DTCP_KEY0_BITS) + +//! @brief Format value for bitfield OCOTP_DTCP_KEY0_BITS. +#define BF_OCOTP_DTCP_KEY0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_DTCP_KEY0_BITS) & BM_OCOTP_DTCP_KEY0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_DTCP_KEY0_BITS(v) (HW_OCOTP_DTCP_KEY0_WR((HW_OCOTP_DTCP_KEY0_RD() & ~BM_OCOTP_DTCP_KEY0_BITS) | BF_OCOTP_DTCP_KEY0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_DTCP_KEY1 - Value of OTP Bank5 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_DTCP_KEY1 - Value of OTP Bank5 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 5, word 1 (ADDR = 0x29). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_dtcp_key1 +{ + reg32_t U; + struct _hw_ocotp_dtcp_key1_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 5, word 1 (ADDR = 0x29). + } B; +} hw_ocotp_dtcp_key1_t; +#endif + +/* + * constants & macros for entire OCOTP_DTCP_KEY1 register + */ +#define HW_OCOTP_DTCP_KEY1_ADDR (REGS_OCOTP_BASE + 0x690) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_DTCP_KEY1 (*(volatile hw_ocotp_dtcp_key1_t *) HW_OCOTP_DTCP_KEY1_ADDR) +#define HW_OCOTP_DTCP_KEY1_RD() (HW_OCOTP_DTCP_KEY1.U) +#define HW_OCOTP_DTCP_KEY1_WR(v) (HW_OCOTP_DTCP_KEY1.U = (v)) +#define HW_OCOTP_DTCP_KEY1_SET(v) (HW_OCOTP_DTCP_KEY1_WR(HW_OCOTP_DTCP_KEY1_RD() | (v))) +#define HW_OCOTP_DTCP_KEY1_CLR(v) (HW_OCOTP_DTCP_KEY1_WR(HW_OCOTP_DTCP_KEY1_RD() & ~(v))) +#define HW_OCOTP_DTCP_KEY1_TOG(v) (HW_OCOTP_DTCP_KEY1_WR(HW_OCOTP_DTCP_KEY1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_DTCP_KEY1 bitfields + */ + +/* --- Register HW_OCOTP_DTCP_KEY1, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 5, word 1 (ADDR = 0x29). + */ + +#define BP_OCOTP_DTCP_KEY1_BITS (0) //!< Bit position for OCOTP_DTCP_KEY1_BITS. +#define BM_OCOTP_DTCP_KEY1_BITS (0xffffffff) //!< Bit mask for OCOTP_DTCP_KEY1_BITS. + +//! @brief Get value of OCOTP_DTCP_KEY1_BITS from a register value. +#define BG_OCOTP_DTCP_KEY1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_DTCP_KEY1_BITS) >> BP_OCOTP_DTCP_KEY1_BITS) + +//! @brief Format value for bitfield OCOTP_DTCP_KEY1_BITS. +#define BF_OCOTP_DTCP_KEY1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_DTCP_KEY1_BITS) & BM_OCOTP_DTCP_KEY1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_DTCP_KEY1_BITS(v) (HW_OCOTP_DTCP_KEY1_WR((HW_OCOTP_DTCP_KEY1_RD() & ~BM_OCOTP_DTCP_KEY1_BITS) | BF_OCOTP_DTCP_KEY1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_DTCP_KEY2 - Value of OTP Bank5 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_DTCP_KEY2 - Value of OTP Bank5 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 5, word 2 (ADDR = 0x2a). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_dtcp_key2 +{ + reg32_t U; + struct _hw_ocotp_dtcp_key2_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a). + } B; +} hw_ocotp_dtcp_key2_t; +#endif + +/* + * constants & macros for entire OCOTP_DTCP_KEY2 register + */ +#define HW_OCOTP_DTCP_KEY2_ADDR (REGS_OCOTP_BASE + 0x6a0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_DTCP_KEY2 (*(volatile hw_ocotp_dtcp_key2_t *) HW_OCOTP_DTCP_KEY2_ADDR) +#define HW_OCOTP_DTCP_KEY2_RD() (HW_OCOTP_DTCP_KEY2.U) +#define HW_OCOTP_DTCP_KEY2_WR(v) (HW_OCOTP_DTCP_KEY2.U = (v)) +#define HW_OCOTP_DTCP_KEY2_SET(v) (HW_OCOTP_DTCP_KEY2_WR(HW_OCOTP_DTCP_KEY2_RD() | (v))) +#define HW_OCOTP_DTCP_KEY2_CLR(v) (HW_OCOTP_DTCP_KEY2_WR(HW_OCOTP_DTCP_KEY2_RD() & ~(v))) +#define HW_OCOTP_DTCP_KEY2_TOG(v) (HW_OCOTP_DTCP_KEY2_WR(HW_OCOTP_DTCP_KEY2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_DTCP_KEY2 bitfields + */ + +/* --- Register HW_OCOTP_DTCP_KEY2, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a). + */ + +#define BP_OCOTP_DTCP_KEY2_BITS (0) //!< Bit position for OCOTP_DTCP_KEY2_BITS. +#define BM_OCOTP_DTCP_KEY2_BITS (0xffffffff) //!< Bit mask for OCOTP_DTCP_KEY2_BITS. + +//! @brief Get value of OCOTP_DTCP_KEY2_BITS from a register value. +#define BG_OCOTP_DTCP_KEY2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_DTCP_KEY2_BITS) >> BP_OCOTP_DTCP_KEY2_BITS) + +//! @brief Format value for bitfield OCOTP_DTCP_KEY2_BITS. +#define BF_OCOTP_DTCP_KEY2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_DTCP_KEY2_BITS) & BM_OCOTP_DTCP_KEY2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_DTCP_KEY2_BITS(v) (HW_OCOTP_DTCP_KEY2_WR((HW_OCOTP_DTCP_KEY2_RD() & ~BM_OCOTP_DTCP_KEY2_BITS) | BF_OCOTP_DTCP_KEY2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_DTCP_KEY3 - Value of OTP Bank5 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_DTCP_KEY3 - Value of OTP Bank5 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 5, word 3 (ADDR = 0x2b). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_dtcp_key3 +{ + reg32_t U; + struct _hw_ocotp_dtcp_key3_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b). + } B; +} hw_ocotp_dtcp_key3_t; +#endif + +/* + * constants & macros for entire OCOTP_DTCP_KEY3 register + */ +#define HW_OCOTP_DTCP_KEY3_ADDR (REGS_OCOTP_BASE + 0x6b0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_DTCP_KEY3 (*(volatile hw_ocotp_dtcp_key3_t *) HW_OCOTP_DTCP_KEY3_ADDR) +#define HW_OCOTP_DTCP_KEY3_RD() (HW_OCOTP_DTCP_KEY3.U) +#define HW_OCOTP_DTCP_KEY3_WR(v) (HW_OCOTP_DTCP_KEY3.U = (v)) +#define HW_OCOTP_DTCP_KEY3_SET(v) (HW_OCOTP_DTCP_KEY3_WR(HW_OCOTP_DTCP_KEY3_RD() | (v))) +#define HW_OCOTP_DTCP_KEY3_CLR(v) (HW_OCOTP_DTCP_KEY3_WR(HW_OCOTP_DTCP_KEY3_RD() & ~(v))) +#define HW_OCOTP_DTCP_KEY3_TOG(v) (HW_OCOTP_DTCP_KEY3_WR(HW_OCOTP_DTCP_KEY3_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_DTCP_KEY3 bitfields + */ + +/* --- Register HW_OCOTP_DTCP_KEY3, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b). + */ + +#define BP_OCOTP_DTCP_KEY3_BITS (0) //!< Bit position for OCOTP_DTCP_KEY3_BITS. +#define BM_OCOTP_DTCP_KEY3_BITS (0xffffffff) //!< Bit mask for OCOTP_DTCP_KEY3_BITS. + +//! @brief Get value of OCOTP_DTCP_KEY3_BITS from a register value. +#define BG_OCOTP_DTCP_KEY3_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_DTCP_KEY3_BITS) >> BP_OCOTP_DTCP_KEY3_BITS) + +//! @brief Format value for bitfield OCOTP_DTCP_KEY3_BITS. +#define BF_OCOTP_DTCP_KEY3_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_DTCP_KEY3_BITS) & BM_OCOTP_DTCP_KEY3_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_DTCP_KEY3_BITS(v) (HW_OCOTP_DTCP_KEY3_WR((HW_OCOTP_DTCP_KEY3_RD() & ~BM_OCOTP_DTCP_KEY3_BITS) | BF_OCOTP_DTCP_KEY3_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_DTCP_KEY4 - Value of OTP Bank5 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_DTCP_KEY4 - Value of OTP Bank5 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 5, word 4 (ADDR = 0x2c). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_dtcp_key4 +{ + reg32_t U; + struct _hw_ocotp_dtcp_key4_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c). + } B; +} hw_ocotp_dtcp_key4_t; +#endif + +/* + * constants & macros for entire OCOTP_DTCP_KEY4 register + */ +#define HW_OCOTP_DTCP_KEY4_ADDR (REGS_OCOTP_BASE + 0x6c0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_DTCP_KEY4 (*(volatile hw_ocotp_dtcp_key4_t *) HW_OCOTP_DTCP_KEY4_ADDR) +#define HW_OCOTP_DTCP_KEY4_RD() (HW_OCOTP_DTCP_KEY4.U) +#define HW_OCOTP_DTCP_KEY4_WR(v) (HW_OCOTP_DTCP_KEY4.U = (v)) +#define HW_OCOTP_DTCP_KEY4_SET(v) (HW_OCOTP_DTCP_KEY4_WR(HW_OCOTP_DTCP_KEY4_RD() | (v))) +#define HW_OCOTP_DTCP_KEY4_CLR(v) (HW_OCOTP_DTCP_KEY4_WR(HW_OCOTP_DTCP_KEY4_RD() & ~(v))) +#define HW_OCOTP_DTCP_KEY4_TOG(v) (HW_OCOTP_DTCP_KEY4_WR(HW_OCOTP_DTCP_KEY4_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_DTCP_KEY4 bitfields + */ + +/* --- Register HW_OCOTP_DTCP_KEY4, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c). + */ + +#define BP_OCOTP_DTCP_KEY4_BITS (0) //!< Bit position for OCOTP_DTCP_KEY4_BITS. +#define BM_OCOTP_DTCP_KEY4_BITS (0xffffffff) //!< Bit mask for OCOTP_DTCP_KEY4_BITS. + +//! @brief Get value of OCOTP_DTCP_KEY4_BITS from a register value. +#define BG_OCOTP_DTCP_KEY4_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_DTCP_KEY4_BITS) >> BP_OCOTP_DTCP_KEY4_BITS) + +//! @brief Format value for bitfield OCOTP_DTCP_KEY4_BITS. +#define BF_OCOTP_DTCP_KEY4_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_DTCP_KEY4_BITS) & BM_OCOTP_DTCP_KEY4_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_DTCP_KEY4_BITS(v) (HW_OCOTP_DTCP_KEY4_WR((HW_OCOTP_DTCP_KEY4_RD() & ~BM_OCOTP_DTCP_KEY4_BITS) | BF_OCOTP_DTCP_KEY4_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_MISC_CONF - Value of OTP Bank5 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_MISC_CONF - Value of OTP Bank5 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 5, word 5 (ADDR = 0x2d). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_misc_conf +{ + reg32_t U; + struct _hw_ocotp_misc_conf_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d). + } B; +} hw_ocotp_misc_conf_t; +#endif + +/* + * constants & macros for entire OCOTP_MISC_CONF register + */ +#define HW_OCOTP_MISC_CONF_ADDR (REGS_OCOTP_BASE + 0x6d0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_MISC_CONF (*(volatile hw_ocotp_misc_conf_t *) HW_OCOTP_MISC_CONF_ADDR) +#define HW_OCOTP_MISC_CONF_RD() (HW_OCOTP_MISC_CONF.U) +#define HW_OCOTP_MISC_CONF_WR(v) (HW_OCOTP_MISC_CONF.U = (v)) +#define HW_OCOTP_MISC_CONF_SET(v) (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() | (v))) +#define HW_OCOTP_MISC_CONF_CLR(v) (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() & ~(v))) +#define HW_OCOTP_MISC_CONF_TOG(v) (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_MISC_CONF bitfields + */ + +/* --- Register HW_OCOTP_MISC_CONF, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d). + */ + +#define BP_OCOTP_MISC_CONF_BITS (0) //!< Bit position for OCOTP_MISC_CONF_BITS. +#define BM_OCOTP_MISC_CONF_BITS (0xffffffff) //!< Bit mask for OCOTP_MISC_CONF_BITS. + +//! @brief Get value of OCOTP_MISC_CONF_BITS from a register value. +#define BG_OCOTP_MISC_CONF_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_MISC_CONF_BITS) >> BP_OCOTP_MISC_CONF_BITS) + +//! @brief Format value for bitfield OCOTP_MISC_CONF_BITS. +#define BF_OCOTP_MISC_CONF_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_MISC_CONF_BITS) & BM_OCOTP_MISC_CONF_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_MISC_CONF_BITS(v) (HW_OCOTP_MISC_CONF_WR((HW_OCOTP_MISC_CONF_RD() & ~BM_OCOTP_MISC_CONF_BITS) | BF_OCOTP_MISC_CONF_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_FIELD_RETURN - Value of OTP Bank5 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_FIELD_RETURN - Value of OTP Bank5 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 5, word 6 (ADDR = 0x2e). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_field_return +{ + reg32_t U; + struct _hw_ocotp_field_return_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e). + } B; +} hw_ocotp_field_return_t; +#endif + +/* + * constants & macros for entire OCOTP_FIELD_RETURN register + */ +#define HW_OCOTP_FIELD_RETURN_ADDR (REGS_OCOTP_BASE + 0x6e0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_FIELD_RETURN (*(volatile hw_ocotp_field_return_t *) HW_OCOTP_FIELD_RETURN_ADDR) +#define HW_OCOTP_FIELD_RETURN_RD() (HW_OCOTP_FIELD_RETURN.U) +#define HW_OCOTP_FIELD_RETURN_WR(v) (HW_OCOTP_FIELD_RETURN.U = (v)) +#define HW_OCOTP_FIELD_RETURN_SET(v) (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() | (v))) +#define HW_OCOTP_FIELD_RETURN_CLR(v) (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() & ~(v))) +#define HW_OCOTP_FIELD_RETURN_TOG(v) (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_FIELD_RETURN bitfields + */ + +/* --- Register HW_OCOTP_FIELD_RETURN, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e). + */ + +#define BP_OCOTP_FIELD_RETURN_BITS (0) //!< Bit position for OCOTP_FIELD_RETURN_BITS. +#define BM_OCOTP_FIELD_RETURN_BITS (0xffffffff) //!< Bit mask for OCOTP_FIELD_RETURN_BITS. + +//! @brief Get value of OCOTP_FIELD_RETURN_BITS from a register value. +#define BG_OCOTP_FIELD_RETURN_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_FIELD_RETURN_BITS) >> BP_OCOTP_FIELD_RETURN_BITS) + +//! @brief Format value for bitfield OCOTP_FIELD_RETURN_BITS. +#define BF_OCOTP_FIELD_RETURN_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_FIELD_RETURN_BITS) & BM_OCOTP_FIELD_RETURN_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_FIELD_RETURN_BITS(v) (HW_OCOTP_FIELD_RETURN_WR((HW_OCOTP_FIELD_RETURN_RD() & ~BM_OCOTP_FIELD_RETURN_BITS) | BF_OCOTP_FIELD_RETURN_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_SRK_REVOKE - Value of OTP Bank5 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_SRK_REVOKE - Value of OTP Bank5 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 5, word 7 (ADDR = 0x2f). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_srk_revoke +{ + reg32_t U; + struct _hw_ocotp_srk_revoke_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f). + } B; +} hw_ocotp_srk_revoke_t; +#endif + +/* + * constants & macros for entire OCOTP_SRK_REVOKE register + */ +#define HW_OCOTP_SRK_REVOKE_ADDR (REGS_OCOTP_BASE + 0x6f0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_SRK_REVOKE (*(volatile hw_ocotp_srk_revoke_t *) HW_OCOTP_SRK_REVOKE_ADDR) +#define HW_OCOTP_SRK_REVOKE_RD() (HW_OCOTP_SRK_REVOKE.U) +#define HW_OCOTP_SRK_REVOKE_WR(v) (HW_OCOTP_SRK_REVOKE.U = (v)) +#define HW_OCOTP_SRK_REVOKE_SET(v) (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() | (v))) +#define HW_OCOTP_SRK_REVOKE_CLR(v) (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() & ~(v))) +#define HW_OCOTP_SRK_REVOKE_TOG(v) (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_SRK_REVOKE bitfields + */ + +/* --- Register HW_OCOTP_SRK_REVOKE, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f). + */ + +#define BP_OCOTP_SRK_REVOKE_BITS (0) //!< Bit position for OCOTP_SRK_REVOKE_BITS. +#define BM_OCOTP_SRK_REVOKE_BITS (0xffffffff) //!< Bit mask for OCOTP_SRK_REVOKE_BITS. + +//! @brief Get value of OCOTP_SRK_REVOKE_BITS from a register value. +#define BG_OCOTP_SRK_REVOKE_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_SRK_REVOKE_BITS) >> BP_OCOTP_SRK_REVOKE_BITS) + +//! @brief Format value for bitfield OCOTP_SRK_REVOKE_BITS. +#define BF_OCOTP_SRK_REVOKE_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_SRK_REVOKE_BITS) & BM_OCOTP_SRK_REVOKE_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_SRK_REVOKE_BITS(v) (HW_OCOTP_SRK_REVOKE_WR((HW_OCOTP_SRK_REVOKE_RD() & ~BM_OCOTP_SRK_REVOKE_BITS) | BF_OCOTP_SRK_REVOKE_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY0 - Value of OTP Bank6 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY0 - Value of OTP Bank6 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 6, word 0 (ADDR = 0x30). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key0 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key0_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 6, word 0 (ADDR = 0x30). + } B; +} hw_ocotp_hdcp_key0_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY0 register + */ +#define HW_OCOTP_HDCP_KEY0_ADDR (REGS_OCOTP_BASE + 0x800) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY0 (*(volatile hw_ocotp_hdcp_key0_t *) HW_OCOTP_HDCP_KEY0_ADDR) +#define HW_OCOTP_HDCP_KEY0_RD() (HW_OCOTP_HDCP_KEY0.U) +#define HW_OCOTP_HDCP_KEY0_WR(v) (HW_OCOTP_HDCP_KEY0.U = (v)) +#define HW_OCOTP_HDCP_KEY0_SET(v) (HW_OCOTP_HDCP_KEY0_WR(HW_OCOTP_HDCP_KEY0_RD() | (v))) +#define HW_OCOTP_HDCP_KEY0_CLR(v) (HW_OCOTP_HDCP_KEY0_WR(HW_OCOTP_HDCP_KEY0_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY0_TOG(v) (HW_OCOTP_HDCP_KEY0_WR(HW_OCOTP_HDCP_KEY0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY0 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY0, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 6, word 0 (ADDR = 0x30). + */ + +#define BP_OCOTP_HDCP_KEY0_BITS (0) //!< Bit position for OCOTP_HDCP_KEY0_BITS. +#define BM_OCOTP_HDCP_KEY0_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY0_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY0_BITS from a register value. +#define BG_OCOTP_HDCP_KEY0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY0_BITS) >> BP_OCOTP_HDCP_KEY0_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY0_BITS. +#define BF_OCOTP_HDCP_KEY0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY0_BITS) & BM_OCOTP_HDCP_KEY0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY0_BITS(v) (HW_OCOTP_HDCP_KEY0_WR((HW_OCOTP_HDCP_KEY0_RD() & ~BM_OCOTP_HDCP_KEY0_BITS) | BF_OCOTP_HDCP_KEY0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY1 - Value of OTP Bank6 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY1 - Value of OTP Bank6 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 6, word 1 (ADDR = 0x31). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key1 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key1_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 6, word 1 (ADDR = 0x31). + } B; +} hw_ocotp_hdcp_key1_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY1 register + */ +#define HW_OCOTP_HDCP_KEY1_ADDR (REGS_OCOTP_BASE + 0x810) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY1 (*(volatile hw_ocotp_hdcp_key1_t *) HW_OCOTP_HDCP_KEY1_ADDR) +#define HW_OCOTP_HDCP_KEY1_RD() (HW_OCOTP_HDCP_KEY1.U) +#define HW_OCOTP_HDCP_KEY1_WR(v) (HW_OCOTP_HDCP_KEY1.U = (v)) +#define HW_OCOTP_HDCP_KEY1_SET(v) (HW_OCOTP_HDCP_KEY1_WR(HW_OCOTP_HDCP_KEY1_RD() | (v))) +#define HW_OCOTP_HDCP_KEY1_CLR(v) (HW_OCOTP_HDCP_KEY1_WR(HW_OCOTP_HDCP_KEY1_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY1_TOG(v) (HW_OCOTP_HDCP_KEY1_WR(HW_OCOTP_HDCP_KEY1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY1 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY1, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 6, word 1 (ADDR = 0x31). + */ + +#define BP_OCOTP_HDCP_KEY1_BITS (0) //!< Bit position for OCOTP_HDCP_KEY1_BITS. +#define BM_OCOTP_HDCP_KEY1_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY1_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY1_BITS from a register value. +#define BG_OCOTP_HDCP_KEY1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY1_BITS) >> BP_OCOTP_HDCP_KEY1_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY1_BITS. +#define BF_OCOTP_HDCP_KEY1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY1_BITS) & BM_OCOTP_HDCP_KEY1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY1_BITS(v) (HW_OCOTP_HDCP_KEY1_WR((HW_OCOTP_HDCP_KEY1_RD() & ~BM_OCOTP_HDCP_KEY1_BITS) | BF_OCOTP_HDCP_KEY1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY2 - Value of OTP Bank6 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY2 - Value of OTP Bank6 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 6, word 2 (ADDR = 0x32). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key2 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key2_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 6, word 2 (ADDR = 0x32). + } B; +} hw_ocotp_hdcp_key2_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY2 register + */ +#define HW_OCOTP_HDCP_KEY2_ADDR (REGS_OCOTP_BASE + 0x820) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY2 (*(volatile hw_ocotp_hdcp_key2_t *) HW_OCOTP_HDCP_KEY2_ADDR) +#define HW_OCOTP_HDCP_KEY2_RD() (HW_OCOTP_HDCP_KEY2.U) +#define HW_OCOTP_HDCP_KEY2_WR(v) (HW_OCOTP_HDCP_KEY2.U = (v)) +#define HW_OCOTP_HDCP_KEY2_SET(v) (HW_OCOTP_HDCP_KEY2_WR(HW_OCOTP_HDCP_KEY2_RD() | (v))) +#define HW_OCOTP_HDCP_KEY2_CLR(v) (HW_OCOTP_HDCP_KEY2_WR(HW_OCOTP_HDCP_KEY2_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY2_TOG(v) (HW_OCOTP_HDCP_KEY2_WR(HW_OCOTP_HDCP_KEY2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY2 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY2, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 6, word 2 (ADDR = 0x32). + */ + +#define BP_OCOTP_HDCP_KEY2_BITS (0) //!< Bit position for OCOTP_HDCP_KEY2_BITS. +#define BM_OCOTP_HDCP_KEY2_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY2_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY2_BITS from a register value. +#define BG_OCOTP_HDCP_KEY2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY2_BITS) >> BP_OCOTP_HDCP_KEY2_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY2_BITS. +#define BF_OCOTP_HDCP_KEY2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY2_BITS) & BM_OCOTP_HDCP_KEY2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY2_BITS(v) (HW_OCOTP_HDCP_KEY2_WR((HW_OCOTP_HDCP_KEY2_RD() & ~BM_OCOTP_HDCP_KEY2_BITS) | BF_OCOTP_HDCP_KEY2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY3 - Value of OTP Bank6 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY3 - Value of OTP Bank6 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 6, word 3 (ADDR = 0x33). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key3 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key3_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 6, word 3 (ADDR = 0x33). + } B; +} hw_ocotp_hdcp_key3_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY3 register + */ +#define HW_OCOTP_HDCP_KEY3_ADDR (REGS_OCOTP_BASE + 0x830) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY3 (*(volatile hw_ocotp_hdcp_key3_t *) HW_OCOTP_HDCP_KEY3_ADDR) +#define HW_OCOTP_HDCP_KEY3_RD() (HW_OCOTP_HDCP_KEY3.U) +#define HW_OCOTP_HDCP_KEY3_WR(v) (HW_OCOTP_HDCP_KEY3.U = (v)) +#define HW_OCOTP_HDCP_KEY3_SET(v) (HW_OCOTP_HDCP_KEY3_WR(HW_OCOTP_HDCP_KEY3_RD() | (v))) +#define HW_OCOTP_HDCP_KEY3_CLR(v) (HW_OCOTP_HDCP_KEY3_WR(HW_OCOTP_HDCP_KEY3_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY3_TOG(v) (HW_OCOTP_HDCP_KEY3_WR(HW_OCOTP_HDCP_KEY3_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY3 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY3, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 6, word 3 (ADDR = 0x33). + */ + +#define BP_OCOTP_HDCP_KEY3_BITS (0) //!< Bit position for OCOTP_HDCP_KEY3_BITS. +#define BM_OCOTP_HDCP_KEY3_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY3_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY3_BITS from a register value. +#define BG_OCOTP_HDCP_KEY3_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY3_BITS) >> BP_OCOTP_HDCP_KEY3_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY3_BITS. +#define BF_OCOTP_HDCP_KEY3_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY3_BITS) & BM_OCOTP_HDCP_KEY3_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY3_BITS(v) (HW_OCOTP_HDCP_KEY3_WR((HW_OCOTP_HDCP_KEY3_RD() & ~BM_OCOTP_HDCP_KEY3_BITS) | BF_OCOTP_HDCP_KEY3_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY4 - Value of OTP Bank6 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY4 - Value of OTP Bank6 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank Bank 6, word 4 (ADDR = + * 0x34). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key4 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key4_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 6, word 4 (ADDR = 0x34). + } B; +} hw_ocotp_hdcp_key4_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY4 register + */ +#define HW_OCOTP_HDCP_KEY4_ADDR (REGS_OCOTP_BASE + 0x840) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY4 (*(volatile hw_ocotp_hdcp_key4_t *) HW_OCOTP_HDCP_KEY4_ADDR) +#define HW_OCOTP_HDCP_KEY4_RD() (HW_OCOTP_HDCP_KEY4.U) +#define HW_OCOTP_HDCP_KEY4_WR(v) (HW_OCOTP_HDCP_KEY4.U = (v)) +#define HW_OCOTP_HDCP_KEY4_SET(v) (HW_OCOTP_HDCP_KEY4_WR(HW_OCOTP_HDCP_KEY4_RD() | (v))) +#define HW_OCOTP_HDCP_KEY4_CLR(v) (HW_OCOTP_HDCP_KEY4_WR(HW_OCOTP_HDCP_KEY4_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY4_TOG(v) (HW_OCOTP_HDCP_KEY4_WR(HW_OCOTP_HDCP_KEY4_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY4 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY4, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 6, word 4 (ADDR = 0x34). + */ + +#define BP_OCOTP_HDCP_KEY4_BITS (0) //!< Bit position for OCOTP_HDCP_KEY4_BITS. +#define BM_OCOTP_HDCP_KEY4_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY4_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY4_BITS from a register value. +#define BG_OCOTP_HDCP_KEY4_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY4_BITS) >> BP_OCOTP_HDCP_KEY4_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY4_BITS. +#define BF_OCOTP_HDCP_KEY4_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY4_BITS) & BM_OCOTP_HDCP_KEY4_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY4_BITS(v) (HW_OCOTP_HDCP_KEY4_WR((HW_OCOTP_HDCP_KEY4_RD() & ~BM_OCOTP_HDCP_KEY4_BITS) | BF_OCOTP_HDCP_KEY4_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY5 - Value of OTP Bank6 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY5 - Value of OTP Bank6 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 6, word 5 (ADDR = 0x35). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key5 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key5_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 6, word 5 (ADDR = 0x35). + } B; +} hw_ocotp_hdcp_key5_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY5 register + */ +#define HW_OCOTP_HDCP_KEY5_ADDR (REGS_OCOTP_BASE + 0x850) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY5 (*(volatile hw_ocotp_hdcp_key5_t *) HW_OCOTP_HDCP_KEY5_ADDR) +#define HW_OCOTP_HDCP_KEY5_RD() (HW_OCOTP_HDCP_KEY5.U) +#define HW_OCOTP_HDCP_KEY5_WR(v) (HW_OCOTP_HDCP_KEY5.U = (v)) +#define HW_OCOTP_HDCP_KEY5_SET(v) (HW_OCOTP_HDCP_KEY5_WR(HW_OCOTP_HDCP_KEY5_RD() | (v))) +#define HW_OCOTP_HDCP_KEY5_CLR(v) (HW_OCOTP_HDCP_KEY5_WR(HW_OCOTP_HDCP_KEY5_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY5_TOG(v) (HW_OCOTP_HDCP_KEY5_WR(HW_OCOTP_HDCP_KEY5_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY5 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY5, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 6, word 5 (ADDR = 0x35). + */ + +#define BP_OCOTP_HDCP_KEY5_BITS (0) //!< Bit position for OCOTP_HDCP_KEY5_BITS. +#define BM_OCOTP_HDCP_KEY5_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY5_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY5_BITS from a register value. +#define BG_OCOTP_HDCP_KEY5_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY5_BITS) >> BP_OCOTP_HDCP_KEY5_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY5_BITS. +#define BF_OCOTP_HDCP_KEY5_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY5_BITS) & BM_OCOTP_HDCP_KEY5_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY5_BITS(v) (HW_OCOTP_HDCP_KEY5_WR((HW_OCOTP_HDCP_KEY5_RD() & ~BM_OCOTP_HDCP_KEY5_BITS) | BF_OCOTP_HDCP_KEY5_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY6 - Value of OTP Bank6 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY6 - Value of OTP Bank6 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 6, word 6 (ADDR = 0x36). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key6 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key6_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 6, word 6 (ADDR = 0x36). + } B; +} hw_ocotp_hdcp_key6_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY6 register + */ +#define HW_OCOTP_HDCP_KEY6_ADDR (REGS_OCOTP_BASE + 0x860) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY6 (*(volatile hw_ocotp_hdcp_key6_t *) HW_OCOTP_HDCP_KEY6_ADDR) +#define HW_OCOTP_HDCP_KEY6_RD() (HW_OCOTP_HDCP_KEY6.U) +#define HW_OCOTP_HDCP_KEY6_WR(v) (HW_OCOTP_HDCP_KEY6.U = (v)) +#define HW_OCOTP_HDCP_KEY6_SET(v) (HW_OCOTP_HDCP_KEY6_WR(HW_OCOTP_HDCP_KEY6_RD() | (v))) +#define HW_OCOTP_HDCP_KEY6_CLR(v) (HW_OCOTP_HDCP_KEY6_WR(HW_OCOTP_HDCP_KEY6_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY6_TOG(v) (HW_OCOTP_HDCP_KEY6_WR(HW_OCOTP_HDCP_KEY6_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY6 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY6, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 6, word 6 (ADDR = 0x36). + */ + +#define BP_OCOTP_HDCP_KEY6_BITS (0) //!< Bit position for OCOTP_HDCP_KEY6_BITS. +#define BM_OCOTP_HDCP_KEY6_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY6_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY6_BITS from a register value. +#define BG_OCOTP_HDCP_KEY6_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY6_BITS) >> BP_OCOTP_HDCP_KEY6_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY6_BITS. +#define BF_OCOTP_HDCP_KEY6_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY6_BITS) & BM_OCOTP_HDCP_KEY6_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY6_BITS(v) (HW_OCOTP_HDCP_KEY6_WR((HW_OCOTP_HDCP_KEY6_RD() & ~BM_OCOTP_HDCP_KEY6_BITS) | BF_OCOTP_HDCP_KEY6_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY7 - Value of OTP Bank6 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY7 - Value of OTP Bank6 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 6, word 7 (ADDR = 0x37). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key7 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key7_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 6, word 7 (ADDR = 0x37). + } B; +} hw_ocotp_hdcp_key7_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY7 register + */ +#define HW_OCOTP_HDCP_KEY7_ADDR (REGS_OCOTP_BASE + 0x870) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY7 (*(volatile hw_ocotp_hdcp_key7_t *) HW_OCOTP_HDCP_KEY7_ADDR) +#define HW_OCOTP_HDCP_KEY7_RD() (HW_OCOTP_HDCP_KEY7.U) +#define HW_OCOTP_HDCP_KEY7_WR(v) (HW_OCOTP_HDCP_KEY7.U = (v)) +#define HW_OCOTP_HDCP_KEY7_SET(v) (HW_OCOTP_HDCP_KEY7_WR(HW_OCOTP_HDCP_KEY7_RD() | (v))) +#define HW_OCOTP_HDCP_KEY7_CLR(v) (HW_OCOTP_HDCP_KEY7_WR(HW_OCOTP_HDCP_KEY7_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY7_TOG(v) (HW_OCOTP_HDCP_KEY7_WR(HW_OCOTP_HDCP_KEY7_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY7 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY7, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 6, word 7 (ADDR = 0x37). + */ + +#define BP_OCOTP_HDCP_KEY7_BITS (0) //!< Bit position for OCOTP_HDCP_KEY7_BITS. +#define BM_OCOTP_HDCP_KEY7_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY7_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY7_BITS from a register value. +#define BG_OCOTP_HDCP_KEY7_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY7_BITS) >> BP_OCOTP_HDCP_KEY7_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY7_BITS. +#define BF_OCOTP_HDCP_KEY7_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY7_BITS) & BM_OCOTP_HDCP_KEY7_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY7_BITS(v) (HW_OCOTP_HDCP_KEY7_WR((HW_OCOTP_HDCP_KEY7_RD() & ~BM_OCOTP_HDCP_KEY7_BITS) | BF_OCOTP_HDCP_KEY7_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY8 - Value of OTP Bank7 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY8 - Value of OTP Bank7 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 7, word 0 (ADDR = 0x38). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key8 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key8_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 7, word 0 (ADDR = 0x38). + } B; +} hw_ocotp_hdcp_key8_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY8 register + */ +#define HW_OCOTP_HDCP_KEY8_ADDR (REGS_OCOTP_BASE + 0x880) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY8 (*(volatile hw_ocotp_hdcp_key8_t *) HW_OCOTP_HDCP_KEY8_ADDR) +#define HW_OCOTP_HDCP_KEY8_RD() (HW_OCOTP_HDCP_KEY8.U) +#define HW_OCOTP_HDCP_KEY8_WR(v) (HW_OCOTP_HDCP_KEY8.U = (v)) +#define HW_OCOTP_HDCP_KEY8_SET(v) (HW_OCOTP_HDCP_KEY8_WR(HW_OCOTP_HDCP_KEY8_RD() | (v))) +#define HW_OCOTP_HDCP_KEY8_CLR(v) (HW_OCOTP_HDCP_KEY8_WR(HW_OCOTP_HDCP_KEY8_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY8_TOG(v) (HW_OCOTP_HDCP_KEY8_WR(HW_OCOTP_HDCP_KEY8_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY8 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY8, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 7, word 0 (ADDR = 0x38). + */ + +#define BP_OCOTP_HDCP_KEY8_BITS (0) //!< Bit position for OCOTP_HDCP_KEY8_BITS. +#define BM_OCOTP_HDCP_KEY8_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY8_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY8_BITS from a register value. +#define BG_OCOTP_HDCP_KEY8_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY8_BITS) >> BP_OCOTP_HDCP_KEY8_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY8_BITS. +#define BF_OCOTP_HDCP_KEY8_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY8_BITS) & BM_OCOTP_HDCP_KEY8_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY8_BITS(v) (HW_OCOTP_HDCP_KEY8_WR((HW_OCOTP_HDCP_KEY8_RD() & ~BM_OCOTP_HDCP_KEY8_BITS) | BF_OCOTP_HDCP_KEY8_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY9 - Value of OTP Bank7 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY9 - Value of OTP Bank7 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 7, word 1 (ADDR = 0x39). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key9 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key9_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 7, word 1 (ADDR = 0x39). + } B; +} hw_ocotp_hdcp_key9_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY9 register + */ +#define HW_OCOTP_HDCP_KEY9_ADDR (REGS_OCOTP_BASE + 0x890) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY9 (*(volatile hw_ocotp_hdcp_key9_t *) HW_OCOTP_HDCP_KEY9_ADDR) +#define HW_OCOTP_HDCP_KEY9_RD() (HW_OCOTP_HDCP_KEY9.U) +#define HW_OCOTP_HDCP_KEY9_WR(v) (HW_OCOTP_HDCP_KEY9.U = (v)) +#define HW_OCOTP_HDCP_KEY9_SET(v) (HW_OCOTP_HDCP_KEY9_WR(HW_OCOTP_HDCP_KEY9_RD() | (v))) +#define HW_OCOTP_HDCP_KEY9_CLR(v) (HW_OCOTP_HDCP_KEY9_WR(HW_OCOTP_HDCP_KEY9_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY9_TOG(v) (HW_OCOTP_HDCP_KEY9_WR(HW_OCOTP_HDCP_KEY9_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY9 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY9, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 7, word 1 (ADDR = 0x39). + */ + +#define BP_OCOTP_HDCP_KEY9_BITS (0) //!< Bit position for OCOTP_HDCP_KEY9_BITS. +#define BM_OCOTP_HDCP_KEY9_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY9_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY9_BITS from a register value. +#define BG_OCOTP_HDCP_KEY9_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY9_BITS) >> BP_OCOTP_HDCP_KEY9_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY9_BITS. +#define BF_OCOTP_HDCP_KEY9_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY9_BITS) & BM_OCOTP_HDCP_KEY9_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY9_BITS(v) (HW_OCOTP_HDCP_KEY9_WR((HW_OCOTP_HDCP_KEY9_RD() & ~BM_OCOTP_HDCP_KEY9_BITS) | BF_OCOTP_HDCP_KEY9_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY10 - Value of OTP Bank7 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY10 - Value of OTP Bank7 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 7, word 2 (ADDR = 0x3a). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key10 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key10_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 7, word 2 (ADDR = 0x3a). + } B; +} hw_ocotp_hdcp_key10_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY10 register + */ +#define HW_OCOTP_HDCP_KEY10_ADDR (REGS_OCOTP_BASE + 0x8a0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY10 (*(volatile hw_ocotp_hdcp_key10_t *) HW_OCOTP_HDCP_KEY10_ADDR) +#define HW_OCOTP_HDCP_KEY10_RD() (HW_OCOTP_HDCP_KEY10.U) +#define HW_OCOTP_HDCP_KEY10_WR(v) (HW_OCOTP_HDCP_KEY10.U = (v)) +#define HW_OCOTP_HDCP_KEY10_SET(v) (HW_OCOTP_HDCP_KEY10_WR(HW_OCOTP_HDCP_KEY10_RD() | (v))) +#define HW_OCOTP_HDCP_KEY10_CLR(v) (HW_OCOTP_HDCP_KEY10_WR(HW_OCOTP_HDCP_KEY10_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY10_TOG(v) (HW_OCOTP_HDCP_KEY10_WR(HW_OCOTP_HDCP_KEY10_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY10 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY10, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 7, word 2 (ADDR = 0x3a). + */ + +#define BP_OCOTP_HDCP_KEY10_BITS (0) //!< Bit position for OCOTP_HDCP_KEY10_BITS. +#define BM_OCOTP_HDCP_KEY10_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY10_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY10_BITS from a register value. +#define BG_OCOTP_HDCP_KEY10_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY10_BITS) >> BP_OCOTP_HDCP_KEY10_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY10_BITS. +#define BF_OCOTP_HDCP_KEY10_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY10_BITS) & BM_OCOTP_HDCP_KEY10_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY10_BITS(v) (HW_OCOTP_HDCP_KEY10_WR((HW_OCOTP_HDCP_KEY10_RD() & ~BM_OCOTP_HDCP_KEY10_BITS) | BF_OCOTP_HDCP_KEY10_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY11 - Value of OTP Bank7 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY11 - Value of OTP Bank7 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 7, word 3 (ADDR = 0x3b). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key11 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key11_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 7, word 3 (ADDR = 0x3b). + } B; +} hw_ocotp_hdcp_key11_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY11 register + */ +#define HW_OCOTP_HDCP_KEY11_ADDR (REGS_OCOTP_BASE + 0x8b0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY11 (*(volatile hw_ocotp_hdcp_key11_t *) HW_OCOTP_HDCP_KEY11_ADDR) +#define HW_OCOTP_HDCP_KEY11_RD() (HW_OCOTP_HDCP_KEY11.U) +#define HW_OCOTP_HDCP_KEY11_WR(v) (HW_OCOTP_HDCP_KEY11.U = (v)) +#define HW_OCOTP_HDCP_KEY11_SET(v) (HW_OCOTP_HDCP_KEY11_WR(HW_OCOTP_HDCP_KEY11_RD() | (v))) +#define HW_OCOTP_HDCP_KEY11_CLR(v) (HW_OCOTP_HDCP_KEY11_WR(HW_OCOTP_HDCP_KEY11_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY11_TOG(v) (HW_OCOTP_HDCP_KEY11_WR(HW_OCOTP_HDCP_KEY11_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY11 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY11, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 7, word 3 (ADDR = 0x3b). + */ + +#define BP_OCOTP_HDCP_KEY11_BITS (0) //!< Bit position for OCOTP_HDCP_KEY11_BITS. +#define BM_OCOTP_HDCP_KEY11_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY11_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY11_BITS from a register value. +#define BG_OCOTP_HDCP_KEY11_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY11_BITS) >> BP_OCOTP_HDCP_KEY11_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY11_BITS. +#define BF_OCOTP_HDCP_KEY11_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY11_BITS) & BM_OCOTP_HDCP_KEY11_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY11_BITS(v) (HW_OCOTP_HDCP_KEY11_WR((HW_OCOTP_HDCP_KEY11_RD() & ~BM_OCOTP_HDCP_KEY11_BITS) | BF_OCOTP_HDCP_KEY11_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY12 - Value of OTP Bank7 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY12 - Value of OTP Bank7 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 7, word 4 (ADDR = 0x3c). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key12 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key12_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 7, word 4 (ADDR = 0x3c). + } B; +} hw_ocotp_hdcp_key12_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY12 register + */ +#define HW_OCOTP_HDCP_KEY12_ADDR (REGS_OCOTP_BASE + 0x8c0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY12 (*(volatile hw_ocotp_hdcp_key12_t *) HW_OCOTP_HDCP_KEY12_ADDR) +#define HW_OCOTP_HDCP_KEY12_RD() (HW_OCOTP_HDCP_KEY12.U) +#define HW_OCOTP_HDCP_KEY12_WR(v) (HW_OCOTP_HDCP_KEY12.U = (v)) +#define HW_OCOTP_HDCP_KEY12_SET(v) (HW_OCOTP_HDCP_KEY12_WR(HW_OCOTP_HDCP_KEY12_RD() | (v))) +#define HW_OCOTP_HDCP_KEY12_CLR(v) (HW_OCOTP_HDCP_KEY12_WR(HW_OCOTP_HDCP_KEY12_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY12_TOG(v) (HW_OCOTP_HDCP_KEY12_WR(HW_OCOTP_HDCP_KEY12_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY12 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY12, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 7, word 4 (ADDR = 0x3c). + */ + +#define BP_OCOTP_HDCP_KEY12_BITS (0) //!< Bit position for OCOTP_HDCP_KEY12_BITS. +#define BM_OCOTP_HDCP_KEY12_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY12_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY12_BITS from a register value. +#define BG_OCOTP_HDCP_KEY12_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY12_BITS) >> BP_OCOTP_HDCP_KEY12_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY12_BITS. +#define BF_OCOTP_HDCP_KEY12_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY12_BITS) & BM_OCOTP_HDCP_KEY12_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY12_BITS(v) (HW_OCOTP_HDCP_KEY12_WR((HW_OCOTP_HDCP_KEY12_RD() & ~BM_OCOTP_HDCP_KEY12_BITS) | BF_OCOTP_HDCP_KEY12_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY13 - Value of OTP Bank7 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY13 - Value of OTP Bank7 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 7, word 5 (ADDR = 0x3d). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key13 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key13_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 7, word 5 (ADDR = 0x3d). + } B; +} hw_ocotp_hdcp_key13_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY13 register + */ +#define HW_OCOTP_HDCP_KEY13_ADDR (REGS_OCOTP_BASE + 0x8d0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY13 (*(volatile hw_ocotp_hdcp_key13_t *) HW_OCOTP_HDCP_KEY13_ADDR) +#define HW_OCOTP_HDCP_KEY13_RD() (HW_OCOTP_HDCP_KEY13.U) +#define HW_OCOTP_HDCP_KEY13_WR(v) (HW_OCOTP_HDCP_KEY13.U = (v)) +#define HW_OCOTP_HDCP_KEY13_SET(v) (HW_OCOTP_HDCP_KEY13_WR(HW_OCOTP_HDCP_KEY13_RD() | (v))) +#define HW_OCOTP_HDCP_KEY13_CLR(v) (HW_OCOTP_HDCP_KEY13_WR(HW_OCOTP_HDCP_KEY13_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY13_TOG(v) (HW_OCOTP_HDCP_KEY13_WR(HW_OCOTP_HDCP_KEY13_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY13 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY13, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 7, word 5 (ADDR = 0x3d). + */ + +#define BP_OCOTP_HDCP_KEY13_BITS (0) //!< Bit position for OCOTP_HDCP_KEY13_BITS. +#define BM_OCOTP_HDCP_KEY13_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY13_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY13_BITS from a register value. +#define BG_OCOTP_HDCP_KEY13_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY13_BITS) >> BP_OCOTP_HDCP_KEY13_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY13_BITS. +#define BF_OCOTP_HDCP_KEY13_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY13_BITS) & BM_OCOTP_HDCP_KEY13_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY13_BITS(v) (HW_OCOTP_HDCP_KEY13_WR((HW_OCOTP_HDCP_KEY13_RD() & ~BM_OCOTP_HDCP_KEY13_BITS) | BF_OCOTP_HDCP_KEY13_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY14 - Value of OTP Bank7 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY14 - Value of OTP Bank7 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 7, word 6 (ADDR = 0x3e). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key14 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key14_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 7, word 6 (ADDR = 0x3e). + } B; +} hw_ocotp_hdcp_key14_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY14 register + */ +#define HW_OCOTP_HDCP_KEY14_ADDR (REGS_OCOTP_BASE + 0x8e0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY14 (*(volatile hw_ocotp_hdcp_key14_t *) HW_OCOTP_HDCP_KEY14_ADDR) +#define HW_OCOTP_HDCP_KEY14_RD() (HW_OCOTP_HDCP_KEY14.U) +#define HW_OCOTP_HDCP_KEY14_WR(v) (HW_OCOTP_HDCP_KEY14.U = (v)) +#define HW_OCOTP_HDCP_KEY14_SET(v) (HW_OCOTP_HDCP_KEY14_WR(HW_OCOTP_HDCP_KEY14_RD() | (v))) +#define HW_OCOTP_HDCP_KEY14_CLR(v) (HW_OCOTP_HDCP_KEY14_WR(HW_OCOTP_HDCP_KEY14_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY14_TOG(v) (HW_OCOTP_HDCP_KEY14_WR(HW_OCOTP_HDCP_KEY14_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY14 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY14, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 7, word 6 (ADDR = 0x3e). + */ + +#define BP_OCOTP_HDCP_KEY14_BITS (0) //!< Bit position for OCOTP_HDCP_KEY14_BITS. +#define BM_OCOTP_HDCP_KEY14_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY14_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY14_BITS from a register value. +#define BG_OCOTP_HDCP_KEY14_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY14_BITS) >> BP_OCOTP_HDCP_KEY14_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY14_BITS. +#define BF_OCOTP_HDCP_KEY14_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY14_BITS) & BM_OCOTP_HDCP_KEY14_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY14_BITS(v) (HW_OCOTP_HDCP_KEY14_WR((HW_OCOTP_HDCP_KEY14_RD() & ~BM_OCOTP_HDCP_KEY14_BITS) | BF_OCOTP_HDCP_KEY14_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY15 - Value of OTP Bank7 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY15 - Value of OTP Bank7 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 7, word 7 (ADDR = 0x3f). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key15 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key15_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 7, word 7 (ADDR = 0x3f). + } B; +} hw_ocotp_hdcp_key15_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY15 register + */ +#define HW_OCOTP_HDCP_KEY15_ADDR (REGS_OCOTP_BASE + 0x8f0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY15 (*(volatile hw_ocotp_hdcp_key15_t *) HW_OCOTP_HDCP_KEY15_ADDR) +#define HW_OCOTP_HDCP_KEY15_RD() (HW_OCOTP_HDCP_KEY15.U) +#define HW_OCOTP_HDCP_KEY15_WR(v) (HW_OCOTP_HDCP_KEY15.U = (v)) +#define HW_OCOTP_HDCP_KEY15_SET(v) (HW_OCOTP_HDCP_KEY15_WR(HW_OCOTP_HDCP_KEY15_RD() | (v))) +#define HW_OCOTP_HDCP_KEY15_CLR(v) (HW_OCOTP_HDCP_KEY15_WR(HW_OCOTP_HDCP_KEY15_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY15_TOG(v) (HW_OCOTP_HDCP_KEY15_WR(HW_OCOTP_HDCP_KEY15_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY15 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY15, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 7, word 7 (ADDR = 0x3f). + */ + +#define BP_OCOTP_HDCP_KEY15_BITS (0) //!< Bit position for OCOTP_HDCP_KEY15_BITS. +#define BM_OCOTP_HDCP_KEY15_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY15_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY15_BITS from a register value. +#define BG_OCOTP_HDCP_KEY15_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY15_BITS) >> BP_OCOTP_HDCP_KEY15_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY15_BITS. +#define BF_OCOTP_HDCP_KEY15_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY15_BITS) & BM_OCOTP_HDCP_KEY15_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY15_BITS(v) (HW_OCOTP_HDCP_KEY15_WR((HW_OCOTP_HDCP_KEY15_RD() & ~BM_OCOTP_HDCP_KEY15_BITS) | BF_OCOTP_HDCP_KEY15_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY16 - Value of OTP Bank8 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY16 - Value of OTP Bank8 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 8, word 0 (ADDR = 0x40). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key16 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key16_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 8, word 0 (ADDR = 0x40). + } B; +} hw_ocotp_hdcp_key16_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY16 register + */ +#define HW_OCOTP_HDCP_KEY16_ADDR (REGS_OCOTP_BASE + 0x900) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY16 (*(volatile hw_ocotp_hdcp_key16_t *) HW_OCOTP_HDCP_KEY16_ADDR) +#define HW_OCOTP_HDCP_KEY16_RD() (HW_OCOTP_HDCP_KEY16.U) +#define HW_OCOTP_HDCP_KEY16_WR(v) (HW_OCOTP_HDCP_KEY16.U = (v)) +#define HW_OCOTP_HDCP_KEY16_SET(v) (HW_OCOTP_HDCP_KEY16_WR(HW_OCOTP_HDCP_KEY16_RD() | (v))) +#define HW_OCOTP_HDCP_KEY16_CLR(v) (HW_OCOTP_HDCP_KEY16_WR(HW_OCOTP_HDCP_KEY16_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY16_TOG(v) (HW_OCOTP_HDCP_KEY16_WR(HW_OCOTP_HDCP_KEY16_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY16 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY16, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 8, word 0 (ADDR = 0x40). + */ + +#define BP_OCOTP_HDCP_KEY16_BITS (0) //!< Bit position for OCOTP_HDCP_KEY16_BITS. +#define BM_OCOTP_HDCP_KEY16_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY16_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY16_BITS from a register value. +#define BG_OCOTP_HDCP_KEY16_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY16_BITS) >> BP_OCOTP_HDCP_KEY16_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY16_BITS. +#define BF_OCOTP_HDCP_KEY16_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY16_BITS) & BM_OCOTP_HDCP_KEY16_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY16_BITS(v) (HW_OCOTP_HDCP_KEY16_WR((HW_OCOTP_HDCP_KEY16_RD() & ~BM_OCOTP_HDCP_KEY16_BITS) | BF_OCOTP_HDCP_KEY16_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY17 - Value of OTP Bank8 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY17 - Value of OTP Bank8 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 8, word 1 (ADDR = 0x41). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key17 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key17_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 8, word 1 (ADDR = 0x41). + } B; +} hw_ocotp_hdcp_key17_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY17 register + */ +#define HW_OCOTP_HDCP_KEY17_ADDR (REGS_OCOTP_BASE + 0x910) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY17 (*(volatile hw_ocotp_hdcp_key17_t *) HW_OCOTP_HDCP_KEY17_ADDR) +#define HW_OCOTP_HDCP_KEY17_RD() (HW_OCOTP_HDCP_KEY17.U) +#define HW_OCOTP_HDCP_KEY17_WR(v) (HW_OCOTP_HDCP_KEY17.U = (v)) +#define HW_OCOTP_HDCP_KEY17_SET(v) (HW_OCOTP_HDCP_KEY17_WR(HW_OCOTP_HDCP_KEY17_RD() | (v))) +#define HW_OCOTP_HDCP_KEY17_CLR(v) (HW_OCOTP_HDCP_KEY17_WR(HW_OCOTP_HDCP_KEY17_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY17_TOG(v) (HW_OCOTP_HDCP_KEY17_WR(HW_OCOTP_HDCP_KEY17_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY17 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY17, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 8, word 1 (ADDR = 0x41). + */ + +#define BP_OCOTP_HDCP_KEY17_BITS (0) //!< Bit position for OCOTP_HDCP_KEY17_BITS. +#define BM_OCOTP_HDCP_KEY17_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY17_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY17_BITS from a register value. +#define BG_OCOTP_HDCP_KEY17_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY17_BITS) >> BP_OCOTP_HDCP_KEY17_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY17_BITS. +#define BF_OCOTP_HDCP_KEY17_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY17_BITS) & BM_OCOTP_HDCP_KEY17_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY17_BITS(v) (HW_OCOTP_HDCP_KEY17_WR((HW_OCOTP_HDCP_KEY17_RD() & ~BM_OCOTP_HDCP_KEY17_BITS) | BF_OCOTP_HDCP_KEY17_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY18 - Value of OTP Bank8 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY18 - Value of OTP Bank8 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 8, word 2 (ADDR = 0x42). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key18 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key18_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 8, word 2 (ADDR = 0x42). + } B; +} hw_ocotp_hdcp_key18_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY18 register + */ +#define HW_OCOTP_HDCP_KEY18_ADDR (REGS_OCOTP_BASE + 0x920) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY18 (*(volatile hw_ocotp_hdcp_key18_t *) HW_OCOTP_HDCP_KEY18_ADDR) +#define HW_OCOTP_HDCP_KEY18_RD() (HW_OCOTP_HDCP_KEY18.U) +#define HW_OCOTP_HDCP_KEY18_WR(v) (HW_OCOTP_HDCP_KEY18.U = (v)) +#define HW_OCOTP_HDCP_KEY18_SET(v) (HW_OCOTP_HDCP_KEY18_WR(HW_OCOTP_HDCP_KEY18_RD() | (v))) +#define HW_OCOTP_HDCP_KEY18_CLR(v) (HW_OCOTP_HDCP_KEY18_WR(HW_OCOTP_HDCP_KEY18_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY18_TOG(v) (HW_OCOTP_HDCP_KEY18_WR(HW_OCOTP_HDCP_KEY18_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY18 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY18, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 8, word 2 (ADDR = 0x42). + */ + +#define BP_OCOTP_HDCP_KEY18_BITS (0) //!< Bit position for OCOTP_HDCP_KEY18_BITS. +#define BM_OCOTP_HDCP_KEY18_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY18_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY18_BITS from a register value. +#define BG_OCOTP_HDCP_KEY18_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY18_BITS) >> BP_OCOTP_HDCP_KEY18_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY18_BITS. +#define BF_OCOTP_HDCP_KEY18_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY18_BITS) & BM_OCOTP_HDCP_KEY18_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY18_BITS(v) (HW_OCOTP_HDCP_KEY18_WR((HW_OCOTP_HDCP_KEY18_RD() & ~BM_OCOTP_HDCP_KEY18_BITS) | BF_OCOTP_HDCP_KEY18_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY19 - Value of OTP Bank8 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY19 - Value of OTP Bank8 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 8, word 3 (ADDR = 0x43). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key19 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key19_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 8, word 3 (ADDR = 0x43). + } B; +} hw_ocotp_hdcp_key19_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY19 register + */ +#define HW_OCOTP_HDCP_KEY19_ADDR (REGS_OCOTP_BASE + 0x930) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY19 (*(volatile hw_ocotp_hdcp_key19_t *) HW_OCOTP_HDCP_KEY19_ADDR) +#define HW_OCOTP_HDCP_KEY19_RD() (HW_OCOTP_HDCP_KEY19.U) +#define HW_OCOTP_HDCP_KEY19_WR(v) (HW_OCOTP_HDCP_KEY19.U = (v)) +#define HW_OCOTP_HDCP_KEY19_SET(v) (HW_OCOTP_HDCP_KEY19_WR(HW_OCOTP_HDCP_KEY19_RD() | (v))) +#define HW_OCOTP_HDCP_KEY19_CLR(v) (HW_OCOTP_HDCP_KEY19_WR(HW_OCOTP_HDCP_KEY19_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY19_TOG(v) (HW_OCOTP_HDCP_KEY19_WR(HW_OCOTP_HDCP_KEY19_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY19 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY19, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 8, word 3 (ADDR = 0x43). + */ + +#define BP_OCOTP_HDCP_KEY19_BITS (0) //!< Bit position for OCOTP_HDCP_KEY19_BITS. +#define BM_OCOTP_HDCP_KEY19_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY19_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY19_BITS from a register value. +#define BG_OCOTP_HDCP_KEY19_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY19_BITS) >> BP_OCOTP_HDCP_KEY19_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY19_BITS. +#define BF_OCOTP_HDCP_KEY19_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY19_BITS) & BM_OCOTP_HDCP_KEY19_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY19_BITS(v) (HW_OCOTP_HDCP_KEY19_WR((HW_OCOTP_HDCP_KEY19_RD() & ~BM_OCOTP_HDCP_KEY19_BITS) | BF_OCOTP_HDCP_KEY19_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY20 - Value of OTP Bank8 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY20 - Value of OTP Bank8 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 8, word 4 (ADDR = 0x44). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key20 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key20_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 8, word 4 (ADDR = 0x44). + } B; +} hw_ocotp_hdcp_key20_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY20 register + */ +#define HW_OCOTP_HDCP_KEY20_ADDR (REGS_OCOTP_BASE + 0x940) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY20 (*(volatile hw_ocotp_hdcp_key20_t *) HW_OCOTP_HDCP_KEY20_ADDR) +#define HW_OCOTP_HDCP_KEY20_RD() (HW_OCOTP_HDCP_KEY20.U) +#define HW_OCOTP_HDCP_KEY20_WR(v) (HW_OCOTP_HDCP_KEY20.U = (v)) +#define HW_OCOTP_HDCP_KEY20_SET(v) (HW_OCOTP_HDCP_KEY20_WR(HW_OCOTP_HDCP_KEY20_RD() | (v))) +#define HW_OCOTP_HDCP_KEY20_CLR(v) (HW_OCOTP_HDCP_KEY20_WR(HW_OCOTP_HDCP_KEY20_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY20_TOG(v) (HW_OCOTP_HDCP_KEY20_WR(HW_OCOTP_HDCP_KEY20_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY20 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY20, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 8, word 4 (ADDR = 0x44). + */ + +#define BP_OCOTP_HDCP_KEY20_BITS (0) //!< Bit position for OCOTP_HDCP_KEY20_BITS. +#define BM_OCOTP_HDCP_KEY20_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY20_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY20_BITS from a register value. +#define BG_OCOTP_HDCP_KEY20_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY20_BITS) >> BP_OCOTP_HDCP_KEY20_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY20_BITS. +#define BF_OCOTP_HDCP_KEY20_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY20_BITS) & BM_OCOTP_HDCP_KEY20_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY20_BITS(v) (HW_OCOTP_HDCP_KEY20_WR((HW_OCOTP_HDCP_KEY20_RD() & ~BM_OCOTP_HDCP_KEY20_BITS) | BF_OCOTP_HDCP_KEY20_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY21 - Value of OTP Bank8 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY21 - Value of OTP Bank8 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 8, word 5 (ADDR = 0x45). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key21 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key21_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 8, word 5 (ADDR = 0x45). + } B; +} hw_ocotp_hdcp_key21_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY21 register + */ +#define HW_OCOTP_HDCP_KEY21_ADDR (REGS_OCOTP_BASE + 0x950) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY21 (*(volatile hw_ocotp_hdcp_key21_t *) HW_OCOTP_HDCP_KEY21_ADDR) +#define HW_OCOTP_HDCP_KEY21_RD() (HW_OCOTP_HDCP_KEY21.U) +#define HW_OCOTP_HDCP_KEY21_WR(v) (HW_OCOTP_HDCP_KEY21.U = (v)) +#define HW_OCOTP_HDCP_KEY21_SET(v) (HW_OCOTP_HDCP_KEY21_WR(HW_OCOTP_HDCP_KEY21_RD() | (v))) +#define HW_OCOTP_HDCP_KEY21_CLR(v) (HW_OCOTP_HDCP_KEY21_WR(HW_OCOTP_HDCP_KEY21_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY21_TOG(v) (HW_OCOTP_HDCP_KEY21_WR(HW_OCOTP_HDCP_KEY21_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY21 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY21, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 8, word 5 (ADDR = 0x45). + */ + +#define BP_OCOTP_HDCP_KEY21_BITS (0) //!< Bit position for OCOTP_HDCP_KEY21_BITS. +#define BM_OCOTP_HDCP_KEY21_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY21_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY21_BITS from a register value. +#define BG_OCOTP_HDCP_KEY21_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY21_BITS) >> BP_OCOTP_HDCP_KEY21_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY21_BITS. +#define BF_OCOTP_HDCP_KEY21_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY21_BITS) & BM_OCOTP_HDCP_KEY21_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY21_BITS(v) (HW_OCOTP_HDCP_KEY21_WR((HW_OCOTP_HDCP_KEY21_RD() & ~BM_OCOTP_HDCP_KEY21_BITS) | BF_OCOTP_HDCP_KEY21_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY22 - Value of OTP Bank8 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY22 - Value of OTP Bank8 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 8, word 6 (ADDR = 0x46). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key22 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key22_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 8, word 6 (ADDR = 0x46). + } B; +} hw_ocotp_hdcp_key22_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY22 register + */ +#define HW_OCOTP_HDCP_KEY22_ADDR (REGS_OCOTP_BASE + 0x960) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY22 (*(volatile hw_ocotp_hdcp_key22_t *) HW_OCOTP_HDCP_KEY22_ADDR) +#define HW_OCOTP_HDCP_KEY22_RD() (HW_OCOTP_HDCP_KEY22.U) +#define HW_OCOTP_HDCP_KEY22_WR(v) (HW_OCOTP_HDCP_KEY22.U = (v)) +#define HW_OCOTP_HDCP_KEY22_SET(v) (HW_OCOTP_HDCP_KEY22_WR(HW_OCOTP_HDCP_KEY22_RD() | (v))) +#define HW_OCOTP_HDCP_KEY22_CLR(v) (HW_OCOTP_HDCP_KEY22_WR(HW_OCOTP_HDCP_KEY22_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY22_TOG(v) (HW_OCOTP_HDCP_KEY22_WR(HW_OCOTP_HDCP_KEY22_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY22 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY22, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 8, word 6 (ADDR = 0x46). + */ + +#define BP_OCOTP_HDCP_KEY22_BITS (0) //!< Bit position for OCOTP_HDCP_KEY22_BITS. +#define BM_OCOTP_HDCP_KEY22_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY22_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY22_BITS from a register value. +#define BG_OCOTP_HDCP_KEY22_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY22_BITS) >> BP_OCOTP_HDCP_KEY22_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY22_BITS. +#define BF_OCOTP_HDCP_KEY22_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY22_BITS) & BM_OCOTP_HDCP_KEY22_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY22_BITS(v) (HW_OCOTP_HDCP_KEY22_WR((HW_OCOTP_HDCP_KEY22_RD() & ~BM_OCOTP_HDCP_KEY22_BITS) | BF_OCOTP_HDCP_KEY22_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY23 - Value of OTP Bank8 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY23 - Value of OTP Bank8 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 8, word 7 (ADDR = 0x47). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key23 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key23_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 8, word 7 (ADDR = 0x47). + } B; +} hw_ocotp_hdcp_key23_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY23 register + */ +#define HW_OCOTP_HDCP_KEY23_ADDR (REGS_OCOTP_BASE + 0x970) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY23 (*(volatile hw_ocotp_hdcp_key23_t *) HW_OCOTP_HDCP_KEY23_ADDR) +#define HW_OCOTP_HDCP_KEY23_RD() (HW_OCOTP_HDCP_KEY23.U) +#define HW_OCOTP_HDCP_KEY23_WR(v) (HW_OCOTP_HDCP_KEY23.U = (v)) +#define HW_OCOTP_HDCP_KEY23_SET(v) (HW_OCOTP_HDCP_KEY23_WR(HW_OCOTP_HDCP_KEY23_RD() | (v))) +#define HW_OCOTP_HDCP_KEY23_CLR(v) (HW_OCOTP_HDCP_KEY23_WR(HW_OCOTP_HDCP_KEY23_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY23_TOG(v) (HW_OCOTP_HDCP_KEY23_WR(HW_OCOTP_HDCP_KEY23_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY23 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY23, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 8, word 7 (ADDR = 0x47). + */ + +#define BP_OCOTP_HDCP_KEY23_BITS (0) //!< Bit position for OCOTP_HDCP_KEY23_BITS. +#define BM_OCOTP_HDCP_KEY23_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY23_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY23_BITS from a register value. +#define BG_OCOTP_HDCP_KEY23_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY23_BITS) >> BP_OCOTP_HDCP_KEY23_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY23_BITS. +#define BF_OCOTP_HDCP_KEY23_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY23_BITS) & BM_OCOTP_HDCP_KEY23_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY23_BITS(v) (HW_OCOTP_HDCP_KEY23_WR((HW_OCOTP_HDCP_KEY23_RD() & ~BM_OCOTP_HDCP_KEY23_BITS) | BF_OCOTP_HDCP_KEY23_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY24 - Value of OTP Bank9 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY24 - Value of OTP Bank9 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 9, word 0 (ADDR = 0x48). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key24 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key24_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 9, word 0 (ADDR = 0x48). + } B; +} hw_ocotp_hdcp_key24_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY24 register + */ +#define HW_OCOTP_HDCP_KEY24_ADDR (REGS_OCOTP_BASE + 0x980) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY24 (*(volatile hw_ocotp_hdcp_key24_t *) HW_OCOTP_HDCP_KEY24_ADDR) +#define HW_OCOTP_HDCP_KEY24_RD() (HW_OCOTP_HDCP_KEY24.U) +#define HW_OCOTP_HDCP_KEY24_WR(v) (HW_OCOTP_HDCP_KEY24.U = (v)) +#define HW_OCOTP_HDCP_KEY24_SET(v) (HW_OCOTP_HDCP_KEY24_WR(HW_OCOTP_HDCP_KEY24_RD() | (v))) +#define HW_OCOTP_HDCP_KEY24_CLR(v) (HW_OCOTP_HDCP_KEY24_WR(HW_OCOTP_HDCP_KEY24_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY24_TOG(v) (HW_OCOTP_HDCP_KEY24_WR(HW_OCOTP_HDCP_KEY24_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY24 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY24, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 9, word 0 (ADDR = 0x48). + */ + +#define BP_OCOTP_HDCP_KEY24_BITS (0) //!< Bit position for OCOTP_HDCP_KEY24_BITS. +#define BM_OCOTP_HDCP_KEY24_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY24_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY24_BITS from a register value. +#define BG_OCOTP_HDCP_KEY24_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY24_BITS) >> BP_OCOTP_HDCP_KEY24_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY24_BITS. +#define BF_OCOTP_HDCP_KEY24_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY24_BITS) & BM_OCOTP_HDCP_KEY24_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY24_BITS(v) (HW_OCOTP_HDCP_KEY24_WR((HW_OCOTP_HDCP_KEY24_RD() & ~BM_OCOTP_HDCP_KEY24_BITS) | BF_OCOTP_HDCP_KEY24_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY25 - Value of OTP Bank9 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY25 - Value of OTP Bank9 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 9, word 1 (ADDR = 0x49). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key25 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key25_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 9, word 1 (ADDR = 0x49). + } B; +} hw_ocotp_hdcp_key25_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY25 register + */ +#define HW_OCOTP_HDCP_KEY25_ADDR (REGS_OCOTP_BASE + 0x990) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY25 (*(volatile hw_ocotp_hdcp_key25_t *) HW_OCOTP_HDCP_KEY25_ADDR) +#define HW_OCOTP_HDCP_KEY25_RD() (HW_OCOTP_HDCP_KEY25.U) +#define HW_OCOTP_HDCP_KEY25_WR(v) (HW_OCOTP_HDCP_KEY25.U = (v)) +#define HW_OCOTP_HDCP_KEY25_SET(v) (HW_OCOTP_HDCP_KEY25_WR(HW_OCOTP_HDCP_KEY25_RD() | (v))) +#define HW_OCOTP_HDCP_KEY25_CLR(v) (HW_OCOTP_HDCP_KEY25_WR(HW_OCOTP_HDCP_KEY25_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY25_TOG(v) (HW_OCOTP_HDCP_KEY25_WR(HW_OCOTP_HDCP_KEY25_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY25 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY25, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 9, word 1 (ADDR = 0x49). + */ + +#define BP_OCOTP_HDCP_KEY25_BITS (0) //!< Bit position for OCOTP_HDCP_KEY25_BITS. +#define BM_OCOTP_HDCP_KEY25_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY25_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY25_BITS from a register value. +#define BG_OCOTP_HDCP_KEY25_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY25_BITS) >> BP_OCOTP_HDCP_KEY25_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY25_BITS. +#define BF_OCOTP_HDCP_KEY25_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY25_BITS) & BM_OCOTP_HDCP_KEY25_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY25_BITS(v) (HW_OCOTP_HDCP_KEY25_WR((HW_OCOTP_HDCP_KEY25_RD() & ~BM_OCOTP_HDCP_KEY25_BITS) | BF_OCOTP_HDCP_KEY25_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY26 - Value of OTP Bank9 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY26 - Value of OTP Bank9 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 9, word 2 (ADDR = 0x4a). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key26 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key26_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 9, word 2 (ADDR = 0x4a). + } B; +} hw_ocotp_hdcp_key26_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY26 register + */ +#define HW_OCOTP_HDCP_KEY26_ADDR (REGS_OCOTP_BASE + 0x9a0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY26 (*(volatile hw_ocotp_hdcp_key26_t *) HW_OCOTP_HDCP_KEY26_ADDR) +#define HW_OCOTP_HDCP_KEY26_RD() (HW_OCOTP_HDCP_KEY26.U) +#define HW_OCOTP_HDCP_KEY26_WR(v) (HW_OCOTP_HDCP_KEY26.U = (v)) +#define HW_OCOTP_HDCP_KEY26_SET(v) (HW_OCOTP_HDCP_KEY26_WR(HW_OCOTP_HDCP_KEY26_RD() | (v))) +#define HW_OCOTP_HDCP_KEY26_CLR(v) (HW_OCOTP_HDCP_KEY26_WR(HW_OCOTP_HDCP_KEY26_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY26_TOG(v) (HW_OCOTP_HDCP_KEY26_WR(HW_OCOTP_HDCP_KEY26_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY26 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY26, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 9, word 2 (ADDR = 0x4a). + */ + +#define BP_OCOTP_HDCP_KEY26_BITS (0) //!< Bit position for OCOTP_HDCP_KEY26_BITS. +#define BM_OCOTP_HDCP_KEY26_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY26_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY26_BITS from a register value. +#define BG_OCOTP_HDCP_KEY26_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY26_BITS) >> BP_OCOTP_HDCP_KEY26_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY26_BITS. +#define BF_OCOTP_HDCP_KEY26_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY26_BITS) & BM_OCOTP_HDCP_KEY26_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY26_BITS(v) (HW_OCOTP_HDCP_KEY26_WR((HW_OCOTP_HDCP_KEY26_RD() & ~BM_OCOTP_HDCP_KEY26_BITS) | BF_OCOTP_HDCP_KEY26_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY27 - Value of OTP Bank9 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY27 - Value of OTP Bank9 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 9, word 3 (ADDR = 0x4b). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key27 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key27_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 9, word 3 (ADDR = 0x4b). + } B; +} hw_ocotp_hdcp_key27_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY27 register + */ +#define HW_OCOTP_HDCP_KEY27_ADDR (REGS_OCOTP_BASE + 0x9b0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY27 (*(volatile hw_ocotp_hdcp_key27_t *) HW_OCOTP_HDCP_KEY27_ADDR) +#define HW_OCOTP_HDCP_KEY27_RD() (HW_OCOTP_HDCP_KEY27.U) +#define HW_OCOTP_HDCP_KEY27_WR(v) (HW_OCOTP_HDCP_KEY27.U = (v)) +#define HW_OCOTP_HDCP_KEY27_SET(v) (HW_OCOTP_HDCP_KEY27_WR(HW_OCOTP_HDCP_KEY27_RD() | (v))) +#define HW_OCOTP_HDCP_KEY27_CLR(v) (HW_OCOTP_HDCP_KEY27_WR(HW_OCOTP_HDCP_KEY27_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY27_TOG(v) (HW_OCOTP_HDCP_KEY27_WR(HW_OCOTP_HDCP_KEY27_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY27 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY27, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 9, word 3 (ADDR = 0x4b). + */ + +#define BP_OCOTP_HDCP_KEY27_BITS (0) //!< Bit position for OCOTP_HDCP_KEY27_BITS. +#define BM_OCOTP_HDCP_KEY27_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY27_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY27_BITS from a register value. +#define BG_OCOTP_HDCP_KEY27_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY27_BITS) >> BP_OCOTP_HDCP_KEY27_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY27_BITS. +#define BF_OCOTP_HDCP_KEY27_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY27_BITS) & BM_OCOTP_HDCP_KEY27_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY27_BITS(v) (HW_OCOTP_HDCP_KEY27_WR((HW_OCOTP_HDCP_KEY27_RD() & ~BM_OCOTP_HDCP_KEY27_BITS) | BF_OCOTP_HDCP_KEY27_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY28 - Value of OTP Bank9 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY28 - Value of OTP Bank9 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 9, word 4 (ADDR = 0x4c). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key28 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key28_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 9, word 4 (ADDR = 0x4c). + } B; +} hw_ocotp_hdcp_key28_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY28 register + */ +#define HW_OCOTP_HDCP_KEY28_ADDR (REGS_OCOTP_BASE + 0x9c0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY28 (*(volatile hw_ocotp_hdcp_key28_t *) HW_OCOTP_HDCP_KEY28_ADDR) +#define HW_OCOTP_HDCP_KEY28_RD() (HW_OCOTP_HDCP_KEY28.U) +#define HW_OCOTP_HDCP_KEY28_WR(v) (HW_OCOTP_HDCP_KEY28.U = (v)) +#define HW_OCOTP_HDCP_KEY28_SET(v) (HW_OCOTP_HDCP_KEY28_WR(HW_OCOTP_HDCP_KEY28_RD() | (v))) +#define HW_OCOTP_HDCP_KEY28_CLR(v) (HW_OCOTP_HDCP_KEY28_WR(HW_OCOTP_HDCP_KEY28_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY28_TOG(v) (HW_OCOTP_HDCP_KEY28_WR(HW_OCOTP_HDCP_KEY28_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY28 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY28, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 9, word 4 (ADDR = 0x4c). + */ + +#define BP_OCOTP_HDCP_KEY28_BITS (0) //!< Bit position for OCOTP_HDCP_KEY28_BITS. +#define BM_OCOTP_HDCP_KEY28_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY28_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY28_BITS from a register value. +#define BG_OCOTP_HDCP_KEY28_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY28_BITS) >> BP_OCOTP_HDCP_KEY28_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY28_BITS. +#define BF_OCOTP_HDCP_KEY28_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY28_BITS) & BM_OCOTP_HDCP_KEY28_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY28_BITS(v) (HW_OCOTP_HDCP_KEY28_WR((HW_OCOTP_HDCP_KEY28_RD() & ~BM_OCOTP_HDCP_KEY28_BITS) | BF_OCOTP_HDCP_KEY28_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY29 - Value of OTP Bank9 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY29 - Value of OTP Bank9 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 9, word 5 (ADDR = 0x4d). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key29 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key29_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 9, word 5 (ADDR = 0x4d). + } B; +} hw_ocotp_hdcp_key29_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY29 register + */ +#define HW_OCOTP_HDCP_KEY29_ADDR (REGS_OCOTP_BASE + 0x9d0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY29 (*(volatile hw_ocotp_hdcp_key29_t *) HW_OCOTP_HDCP_KEY29_ADDR) +#define HW_OCOTP_HDCP_KEY29_RD() (HW_OCOTP_HDCP_KEY29.U) +#define HW_OCOTP_HDCP_KEY29_WR(v) (HW_OCOTP_HDCP_KEY29.U = (v)) +#define HW_OCOTP_HDCP_KEY29_SET(v) (HW_OCOTP_HDCP_KEY29_WR(HW_OCOTP_HDCP_KEY29_RD() | (v))) +#define HW_OCOTP_HDCP_KEY29_CLR(v) (HW_OCOTP_HDCP_KEY29_WR(HW_OCOTP_HDCP_KEY29_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY29_TOG(v) (HW_OCOTP_HDCP_KEY29_WR(HW_OCOTP_HDCP_KEY29_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY29 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY29, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 9, word 5 (ADDR = 0x4d). + */ + +#define BP_OCOTP_HDCP_KEY29_BITS (0) //!< Bit position for OCOTP_HDCP_KEY29_BITS. +#define BM_OCOTP_HDCP_KEY29_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY29_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY29_BITS from a register value. +#define BG_OCOTP_HDCP_KEY29_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY29_BITS) >> BP_OCOTP_HDCP_KEY29_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY29_BITS. +#define BF_OCOTP_HDCP_KEY29_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY29_BITS) & BM_OCOTP_HDCP_KEY29_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY29_BITS(v) (HW_OCOTP_HDCP_KEY29_WR((HW_OCOTP_HDCP_KEY29_RD() & ~BM_OCOTP_HDCP_KEY29_BITS) | BF_OCOTP_HDCP_KEY29_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY30 - Value of OTP Bank9 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY30 - Value of OTP Bank9 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 9, word 6 (ADDR = 0x4e). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key30 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key30_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 9, word 6 (ADDR = 0x4e). + } B; +} hw_ocotp_hdcp_key30_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY30 register + */ +#define HW_OCOTP_HDCP_KEY30_ADDR (REGS_OCOTP_BASE + 0x9e0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY30 (*(volatile hw_ocotp_hdcp_key30_t *) HW_OCOTP_HDCP_KEY30_ADDR) +#define HW_OCOTP_HDCP_KEY30_RD() (HW_OCOTP_HDCP_KEY30.U) +#define HW_OCOTP_HDCP_KEY30_WR(v) (HW_OCOTP_HDCP_KEY30.U = (v)) +#define HW_OCOTP_HDCP_KEY30_SET(v) (HW_OCOTP_HDCP_KEY30_WR(HW_OCOTP_HDCP_KEY30_RD() | (v))) +#define HW_OCOTP_HDCP_KEY30_CLR(v) (HW_OCOTP_HDCP_KEY30_WR(HW_OCOTP_HDCP_KEY30_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY30_TOG(v) (HW_OCOTP_HDCP_KEY30_WR(HW_OCOTP_HDCP_KEY30_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY30 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY30, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 9, word 6 (ADDR = 0x4e). + */ + +#define BP_OCOTP_HDCP_KEY30_BITS (0) //!< Bit position for OCOTP_HDCP_KEY30_BITS. +#define BM_OCOTP_HDCP_KEY30_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY30_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY30_BITS from a register value. +#define BG_OCOTP_HDCP_KEY30_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY30_BITS) >> BP_OCOTP_HDCP_KEY30_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY30_BITS. +#define BF_OCOTP_HDCP_KEY30_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY30_BITS) & BM_OCOTP_HDCP_KEY30_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY30_BITS(v) (HW_OCOTP_HDCP_KEY30_WR((HW_OCOTP_HDCP_KEY30_RD() & ~BM_OCOTP_HDCP_KEY30_BITS) | BF_OCOTP_HDCP_KEY30_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY31 - Value of OTP Bank9 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY31 - Value of OTP Bank9 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 9, word 7 (ADDR = 0x4f). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key31 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key31_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 9, word 7 (ADDR = 0x4f). + } B; +} hw_ocotp_hdcp_key31_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY31 register + */ +#define HW_OCOTP_HDCP_KEY31_ADDR (REGS_OCOTP_BASE + 0x9f0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY31 (*(volatile hw_ocotp_hdcp_key31_t *) HW_OCOTP_HDCP_KEY31_ADDR) +#define HW_OCOTP_HDCP_KEY31_RD() (HW_OCOTP_HDCP_KEY31.U) +#define HW_OCOTP_HDCP_KEY31_WR(v) (HW_OCOTP_HDCP_KEY31.U = (v)) +#define HW_OCOTP_HDCP_KEY31_SET(v) (HW_OCOTP_HDCP_KEY31_WR(HW_OCOTP_HDCP_KEY31_RD() | (v))) +#define HW_OCOTP_HDCP_KEY31_CLR(v) (HW_OCOTP_HDCP_KEY31_WR(HW_OCOTP_HDCP_KEY31_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY31_TOG(v) (HW_OCOTP_HDCP_KEY31_WR(HW_OCOTP_HDCP_KEY31_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY31 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY31, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 9, word 7 (ADDR = 0x4f). + */ + +#define BP_OCOTP_HDCP_KEY31_BITS (0) //!< Bit position for OCOTP_HDCP_KEY31_BITS. +#define BM_OCOTP_HDCP_KEY31_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY31_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY31_BITS from a register value. +#define BG_OCOTP_HDCP_KEY31_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY31_BITS) >> BP_OCOTP_HDCP_KEY31_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY31_BITS. +#define BF_OCOTP_HDCP_KEY31_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY31_BITS) & BM_OCOTP_HDCP_KEY31_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY31_BITS(v) (HW_OCOTP_HDCP_KEY31_WR((HW_OCOTP_HDCP_KEY31_RD() & ~BM_OCOTP_HDCP_KEY31_BITS) | BF_OCOTP_HDCP_KEY31_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY32 - Value of OTP Bank10 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY32 - Value of OTP Bank10 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 10, word 0 (ADDR = + * 0x50). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key32 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key32_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 10, word 0 (ADDR = 0x50). + } B; +} hw_ocotp_hdcp_key32_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY32 register + */ +#define HW_OCOTP_HDCP_KEY32_ADDR (REGS_OCOTP_BASE + 0xa00) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY32 (*(volatile hw_ocotp_hdcp_key32_t *) HW_OCOTP_HDCP_KEY32_ADDR) +#define HW_OCOTP_HDCP_KEY32_RD() (HW_OCOTP_HDCP_KEY32.U) +#define HW_OCOTP_HDCP_KEY32_WR(v) (HW_OCOTP_HDCP_KEY32.U = (v)) +#define HW_OCOTP_HDCP_KEY32_SET(v) (HW_OCOTP_HDCP_KEY32_WR(HW_OCOTP_HDCP_KEY32_RD() | (v))) +#define HW_OCOTP_HDCP_KEY32_CLR(v) (HW_OCOTP_HDCP_KEY32_WR(HW_OCOTP_HDCP_KEY32_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY32_TOG(v) (HW_OCOTP_HDCP_KEY32_WR(HW_OCOTP_HDCP_KEY32_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY32 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY32, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 10, word 0 (ADDR = 0x50). + */ + +#define BP_OCOTP_HDCP_KEY32_BITS (0) //!< Bit position for OCOTP_HDCP_KEY32_BITS. +#define BM_OCOTP_HDCP_KEY32_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY32_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY32_BITS from a register value. +#define BG_OCOTP_HDCP_KEY32_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY32_BITS) >> BP_OCOTP_HDCP_KEY32_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY32_BITS. +#define BF_OCOTP_HDCP_KEY32_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY32_BITS) & BM_OCOTP_HDCP_KEY32_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY32_BITS(v) (HW_OCOTP_HDCP_KEY32_WR((HW_OCOTP_HDCP_KEY32_RD() & ~BM_OCOTP_HDCP_KEY32_BITS) | BF_OCOTP_HDCP_KEY32_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY33 - Value of OTP Bank10 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY33 - Value of OTP Bank10 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 10, word 1 (ADDR = + * 0x51). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key33 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key33_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 10, word 1 (ADDR = 0x51). + } B; +} hw_ocotp_hdcp_key33_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY33 register + */ +#define HW_OCOTP_HDCP_KEY33_ADDR (REGS_OCOTP_BASE + 0xa10) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY33 (*(volatile hw_ocotp_hdcp_key33_t *) HW_OCOTP_HDCP_KEY33_ADDR) +#define HW_OCOTP_HDCP_KEY33_RD() (HW_OCOTP_HDCP_KEY33.U) +#define HW_OCOTP_HDCP_KEY33_WR(v) (HW_OCOTP_HDCP_KEY33.U = (v)) +#define HW_OCOTP_HDCP_KEY33_SET(v) (HW_OCOTP_HDCP_KEY33_WR(HW_OCOTP_HDCP_KEY33_RD() | (v))) +#define HW_OCOTP_HDCP_KEY33_CLR(v) (HW_OCOTP_HDCP_KEY33_WR(HW_OCOTP_HDCP_KEY33_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY33_TOG(v) (HW_OCOTP_HDCP_KEY33_WR(HW_OCOTP_HDCP_KEY33_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY33 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY33, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 10, word 1 (ADDR = 0x51). + */ + +#define BP_OCOTP_HDCP_KEY33_BITS (0) //!< Bit position for OCOTP_HDCP_KEY33_BITS. +#define BM_OCOTP_HDCP_KEY33_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY33_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY33_BITS from a register value. +#define BG_OCOTP_HDCP_KEY33_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY33_BITS) >> BP_OCOTP_HDCP_KEY33_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY33_BITS. +#define BF_OCOTP_HDCP_KEY33_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY33_BITS) & BM_OCOTP_HDCP_KEY33_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY33_BITS(v) (HW_OCOTP_HDCP_KEY33_WR((HW_OCOTP_HDCP_KEY33_RD() & ~BM_OCOTP_HDCP_KEY33_BITS) | BF_OCOTP_HDCP_KEY33_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY34 - Value of OTP Bank10 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY34 - Value of OTP Bank10 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 10, word 2 (ADDR = + * 0x52). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key34 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key34_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 10, word 2 (ADDR = 0x52). + } B; +} hw_ocotp_hdcp_key34_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY34 register + */ +#define HW_OCOTP_HDCP_KEY34_ADDR (REGS_OCOTP_BASE + 0xa20) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY34 (*(volatile hw_ocotp_hdcp_key34_t *) HW_OCOTP_HDCP_KEY34_ADDR) +#define HW_OCOTP_HDCP_KEY34_RD() (HW_OCOTP_HDCP_KEY34.U) +#define HW_OCOTP_HDCP_KEY34_WR(v) (HW_OCOTP_HDCP_KEY34.U = (v)) +#define HW_OCOTP_HDCP_KEY34_SET(v) (HW_OCOTP_HDCP_KEY34_WR(HW_OCOTP_HDCP_KEY34_RD() | (v))) +#define HW_OCOTP_HDCP_KEY34_CLR(v) (HW_OCOTP_HDCP_KEY34_WR(HW_OCOTP_HDCP_KEY34_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY34_TOG(v) (HW_OCOTP_HDCP_KEY34_WR(HW_OCOTP_HDCP_KEY34_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY34 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY34, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 10, word 2 (ADDR = 0x52). + */ + +#define BP_OCOTP_HDCP_KEY34_BITS (0) //!< Bit position for OCOTP_HDCP_KEY34_BITS. +#define BM_OCOTP_HDCP_KEY34_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY34_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY34_BITS from a register value. +#define BG_OCOTP_HDCP_KEY34_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY34_BITS) >> BP_OCOTP_HDCP_KEY34_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY34_BITS. +#define BF_OCOTP_HDCP_KEY34_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY34_BITS) & BM_OCOTP_HDCP_KEY34_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY34_BITS(v) (HW_OCOTP_HDCP_KEY34_WR((HW_OCOTP_HDCP_KEY34_RD() & ~BM_OCOTP_HDCP_KEY34_BITS) | BF_OCOTP_HDCP_KEY34_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY35 - Value of OTP Bank10 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY35 - Value of OTP Bank10 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 10, word 3 (ADDR = + * 0x53). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key35 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key35_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 10, word 3 (ADDR = 0x53). + } B; +} hw_ocotp_hdcp_key35_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY35 register + */ +#define HW_OCOTP_HDCP_KEY35_ADDR (REGS_OCOTP_BASE + 0xa30) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY35 (*(volatile hw_ocotp_hdcp_key35_t *) HW_OCOTP_HDCP_KEY35_ADDR) +#define HW_OCOTP_HDCP_KEY35_RD() (HW_OCOTP_HDCP_KEY35.U) +#define HW_OCOTP_HDCP_KEY35_WR(v) (HW_OCOTP_HDCP_KEY35.U = (v)) +#define HW_OCOTP_HDCP_KEY35_SET(v) (HW_OCOTP_HDCP_KEY35_WR(HW_OCOTP_HDCP_KEY35_RD() | (v))) +#define HW_OCOTP_HDCP_KEY35_CLR(v) (HW_OCOTP_HDCP_KEY35_WR(HW_OCOTP_HDCP_KEY35_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY35_TOG(v) (HW_OCOTP_HDCP_KEY35_WR(HW_OCOTP_HDCP_KEY35_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY35 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY35, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 10, word 3 (ADDR = 0x53). + */ + +#define BP_OCOTP_HDCP_KEY35_BITS (0) //!< Bit position for OCOTP_HDCP_KEY35_BITS. +#define BM_OCOTP_HDCP_KEY35_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY35_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY35_BITS from a register value. +#define BG_OCOTP_HDCP_KEY35_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY35_BITS) >> BP_OCOTP_HDCP_KEY35_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY35_BITS. +#define BF_OCOTP_HDCP_KEY35_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY35_BITS) & BM_OCOTP_HDCP_KEY35_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY35_BITS(v) (HW_OCOTP_HDCP_KEY35_WR((HW_OCOTP_HDCP_KEY35_RD() & ~BM_OCOTP_HDCP_KEY35_BITS) | BF_OCOTP_HDCP_KEY35_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY36 - Value of OTP Bank10 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY36 - Value of OTP Bank10 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 10, word 4 (ADDR = + * 0x54). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key36 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key36_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 10, word 4 (ADDR = 0x54). + } B; +} hw_ocotp_hdcp_key36_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY36 register + */ +#define HW_OCOTP_HDCP_KEY36_ADDR (REGS_OCOTP_BASE + 0xa40) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY36 (*(volatile hw_ocotp_hdcp_key36_t *) HW_OCOTP_HDCP_KEY36_ADDR) +#define HW_OCOTP_HDCP_KEY36_RD() (HW_OCOTP_HDCP_KEY36.U) +#define HW_OCOTP_HDCP_KEY36_WR(v) (HW_OCOTP_HDCP_KEY36.U = (v)) +#define HW_OCOTP_HDCP_KEY36_SET(v) (HW_OCOTP_HDCP_KEY36_WR(HW_OCOTP_HDCP_KEY36_RD() | (v))) +#define HW_OCOTP_HDCP_KEY36_CLR(v) (HW_OCOTP_HDCP_KEY36_WR(HW_OCOTP_HDCP_KEY36_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY36_TOG(v) (HW_OCOTP_HDCP_KEY36_WR(HW_OCOTP_HDCP_KEY36_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY36 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY36, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 10, word 4 (ADDR = 0x54). + */ + +#define BP_OCOTP_HDCP_KEY36_BITS (0) //!< Bit position for OCOTP_HDCP_KEY36_BITS. +#define BM_OCOTP_HDCP_KEY36_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY36_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY36_BITS from a register value. +#define BG_OCOTP_HDCP_KEY36_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY36_BITS) >> BP_OCOTP_HDCP_KEY36_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY36_BITS. +#define BF_OCOTP_HDCP_KEY36_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY36_BITS) & BM_OCOTP_HDCP_KEY36_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY36_BITS(v) (HW_OCOTP_HDCP_KEY36_WR((HW_OCOTP_HDCP_KEY36_RD() & ~BM_OCOTP_HDCP_KEY36_BITS) | BF_OCOTP_HDCP_KEY36_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY37 - Value of OTP Bank10 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY37 - Value of OTP Bank10 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 10, word 5 (ADDR = + * 0x55). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key37 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key37_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 10, word 5 (ADDR = 0x55). + } B; +} hw_ocotp_hdcp_key37_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY37 register + */ +#define HW_OCOTP_HDCP_KEY37_ADDR (REGS_OCOTP_BASE + 0xa50) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY37 (*(volatile hw_ocotp_hdcp_key37_t *) HW_OCOTP_HDCP_KEY37_ADDR) +#define HW_OCOTP_HDCP_KEY37_RD() (HW_OCOTP_HDCP_KEY37.U) +#define HW_OCOTP_HDCP_KEY37_WR(v) (HW_OCOTP_HDCP_KEY37.U = (v)) +#define HW_OCOTP_HDCP_KEY37_SET(v) (HW_OCOTP_HDCP_KEY37_WR(HW_OCOTP_HDCP_KEY37_RD() | (v))) +#define HW_OCOTP_HDCP_KEY37_CLR(v) (HW_OCOTP_HDCP_KEY37_WR(HW_OCOTP_HDCP_KEY37_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY37_TOG(v) (HW_OCOTP_HDCP_KEY37_WR(HW_OCOTP_HDCP_KEY37_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY37 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY37, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 10, word 5 (ADDR = 0x55). + */ + +#define BP_OCOTP_HDCP_KEY37_BITS (0) //!< Bit position for OCOTP_HDCP_KEY37_BITS. +#define BM_OCOTP_HDCP_KEY37_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY37_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY37_BITS from a register value. +#define BG_OCOTP_HDCP_KEY37_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY37_BITS) >> BP_OCOTP_HDCP_KEY37_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY37_BITS. +#define BF_OCOTP_HDCP_KEY37_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY37_BITS) & BM_OCOTP_HDCP_KEY37_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY37_BITS(v) (HW_OCOTP_HDCP_KEY37_WR((HW_OCOTP_HDCP_KEY37_RD() & ~BM_OCOTP_HDCP_KEY37_BITS) | BF_OCOTP_HDCP_KEY37_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY38 - Value of OTP Bank10 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY38 - Value of OTP Bank10 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 10, word 6 (ADDR = + * 0x56). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key38 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key38_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 10, word 6 (ADDR = 0x56). + } B; +} hw_ocotp_hdcp_key38_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY38 register + */ +#define HW_OCOTP_HDCP_KEY38_ADDR (REGS_OCOTP_BASE + 0xa60) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY38 (*(volatile hw_ocotp_hdcp_key38_t *) HW_OCOTP_HDCP_KEY38_ADDR) +#define HW_OCOTP_HDCP_KEY38_RD() (HW_OCOTP_HDCP_KEY38.U) +#define HW_OCOTP_HDCP_KEY38_WR(v) (HW_OCOTP_HDCP_KEY38.U = (v)) +#define HW_OCOTP_HDCP_KEY38_SET(v) (HW_OCOTP_HDCP_KEY38_WR(HW_OCOTP_HDCP_KEY38_RD() | (v))) +#define HW_OCOTP_HDCP_KEY38_CLR(v) (HW_OCOTP_HDCP_KEY38_WR(HW_OCOTP_HDCP_KEY38_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY38_TOG(v) (HW_OCOTP_HDCP_KEY38_WR(HW_OCOTP_HDCP_KEY38_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY38 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY38, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 10, word 6 (ADDR = 0x56). + */ + +#define BP_OCOTP_HDCP_KEY38_BITS (0) //!< Bit position for OCOTP_HDCP_KEY38_BITS. +#define BM_OCOTP_HDCP_KEY38_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY38_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY38_BITS from a register value. +#define BG_OCOTP_HDCP_KEY38_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY38_BITS) >> BP_OCOTP_HDCP_KEY38_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY38_BITS. +#define BF_OCOTP_HDCP_KEY38_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY38_BITS) & BM_OCOTP_HDCP_KEY38_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY38_BITS(v) (HW_OCOTP_HDCP_KEY38_WR((HW_OCOTP_HDCP_KEY38_RD() & ~BM_OCOTP_HDCP_KEY38_BITS) | BF_OCOTP_HDCP_KEY38_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY39 - Value of OTP Bank10 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY39 - Value of OTP Bank10 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 10, word 7 (ADDR = + * 0x57). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key39 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key39_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 10, word 7 (ADDR = 0x57). + } B; +} hw_ocotp_hdcp_key39_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY39 register + */ +#define HW_OCOTP_HDCP_KEY39_ADDR (REGS_OCOTP_BASE + 0xa70) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY39 (*(volatile hw_ocotp_hdcp_key39_t *) HW_OCOTP_HDCP_KEY39_ADDR) +#define HW_OCOTP_HDCP_KEY39_RD() (HW_OCOTP_HDCP_KEY39.U) +#define HW_OCOTP_HDCP_KEY39_WR(v) (HW_OCOTP_HDCP_KEY39.U = (v)) +#define HW_OCOTP_HDCP_KEY39_SET(v) (HW_OCOTP_HDCP_KEY39_WR(HW_OCOTP_HDCP_KEY39_RD() | (v))) +#define HW_OCOTP_HDCP_KEY39_CLR(v) (HW_OCOTP_HDCP_KEY39_WR(HW_OCOTP_HDCP_KEY39_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY39_TOG(v) (HW_OCOTP_HDCP_KEY39_WR(HW_OCOTP_HDCP_KEY39_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY39 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY39, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 10, word 7 (ADDR = 0x57). + */ + +#define BP_OCOTP_HDCP_KEY39_BITS (0) //!< Bit position for OCOTP_HDCP_KEY39_BITS. +#define BM_OCOTP_HDCP_KEY39_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY39_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY39_BITS from a register value. +#define BG_OCOTP_HDCP_KEY39_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY39_BITS) >> BP_OCOTP_HDCP_KEY39_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY39_BITS. +#define BF_OCOTP_HDCP_KEY39_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY39_BITS) & BM_OCOTP_HDCP_KEY39_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY39_BITS(v) (HW_OCOTP_HDCP_KEY39_WR((HW_OCOTP_HDCP_KEY39_RD() & ~BM_OCOTP_HDCP_KEY39_BITS) | BF_OCOTP_HDCP_KEY39_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY40 - Value of OTP Bank11 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY40 - Value of OTP Bank11 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 11, word 0 (ADDR = + * 0x58). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key40 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key40_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 11, word 0 (ADDR = 0x58). + } B; +} hw_ocotp_hdcp_key40_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY40 register + */ +#define HW_OCOTP_HDCP_KEY40_ADDR (REGS_OCOTP_BASE + 0xa80) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY40 (*(volatile hw_ocotp_hdcp_key40_t *) HW_OCOTP_HDCP_KEY40_ADDR) +#define HW_OCOTP_HDCP_KEY40_RD() (HW_OCOTP_HDCP_KEY40.U) +#define HW_OCOTP_HDCP_KEY40_WR(v) (HW_OCOTP_HDCP_KEY40.U = (v)) +#define HW_OCOTP_HDCP_KEY40_SET(v) (HW_OCOTP_HDCP_KEY40_WR(HW_OCOTP_HDCP_KEY40_RD() | (v))) +#define HW_OCOTP_HDCP_KEY40_CLR(v) (HW_OCOTP_HDCP_KEY40_WR(HW_OCOTP_HDCP_KEY40_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY40_TOG(v) (HW_OCOTP_HDCP_KEY40_WR(HW_OCOTP_HDCP_KEY40_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY40 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY40, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 11, word 0 (ADDR = 0x58). + */ + +#define BP_OCOTP_HDCP_KEY40_BITS (0) //!< Bit position for OCOTP_HDCP_KEY40_BITS. +#define BM_OCOTP_HDCP_KEY40_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY40_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY40_BITS from a register value. +#define BG_OCOTP_HDCP_KEY40_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY40_BITS) >> BP_OCOTP_HDCP_KEY40_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY40_BITS. +#define BF_OCOTP_HDCP_KEY40_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY40_BITS) & BM_OCOTP_HDCP_KEY40_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY40_BITS(v) (HW_OCOTP_HDCP_KEY40_WR((HW_OCOTP_HDCP_KEY40_RD() & ~BM_OCOTP_HDCP_KEY40_BITS) | BF_OCOTP_HDCP_KEY40_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY41 - Value of OTP Bank11 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY41 - Value of OTP Bank11 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 11, word 1 (ADDR = + * 0x59). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key41 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key41_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 11, word 1 (ADDR = 0x59). + } B; +} hw_ocotp_hdcp_key41_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY41 register + */ +#define HW_OCOTP_HDCP_KEY41_ADDR (REGS_OCOTP_BASE + 0xa90) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY41 (*(volatile hw_ocotp_hdcp_key41_t *) HW_OCOTP_HDCP_KEY41_ADDR) +#define HW_OCOTP_HDCP_KEY41_RD() (HW_OCOTP_HDCP_KEY41.U) +#define HW_OCOTP_HDCP_KEY41_WR(v) (HW_OCOTP_HDCP_KEY41.U = (v)) +#define HW_OCOTP_HDCP_KEY41_SET(v) (HW_OCOTP_HDCP_KEY41_WR(HW_OCOTP_HDCP_KEY41_RD() | (v))) +#define HW_OCOTP_HDCP_KEY41_CLR(v) (HW_OCOTP_HDCP_KEY41_WR(HW_OCOTP_HDCP_KEY41_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY41_TOG(v) (HW_OCOTP_HDCP_KEY41_WR(HW_OCOTP_HDCP_KEY41_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY41 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY41, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 11, word 1 (ADDR = 0x59). + */ + +#define BP_OCOTP_HDCP_KEY41_BITS (0) //!< Bit position for OCOTP_HDCP_KEY41_BITS. +#define BM_OCOTP_HDCP_KEY41_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY41_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY41_BITS from a register value. +#define BG_OCOTP_HDCP_KEY41_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY41_BITS) >> BP_OCOTP_HDCP_KEY41_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY41_BITS. +#define BF_OCOTP_HDCP_KEY41_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY41_BITS) & BM_OCOTP_HDCP_KEY41_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY41_BITS(v) (HW_OCOTP_HDCP_KEY41_WR((HW_OCOTP_HDCP_KEY41_RD() & ~BM_OCOTP_HDCP_KEY41_BITS) | BF_OCOTP_HDCP_KEY41_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY42 - Value of OTP Bank11 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY42 - Value of OTP Bank11 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 11, word 2 (ADDR = + * 0x5a). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key42 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key42_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 11, word 2 (ADDR = 0x5a). + } B; +} hw_ocotp_hdcp_key42_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY42 register + */ +#define HW_OCOTP_HDCP_KEY42_ADDR (REGS_OCOTP_BASE + 0xaa0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY42 (*(volatile hw_ocotp_hdcp_key42_t *) HW_OCOTP_HDCP_KEY42_ADDR) +#define HW_OCOTP_HDCP_KEY42_RD() (HW_OCOTP_HDCP_KEY42.U) +#define HW_OCOTP_HDCP_KEY42_WR(v) (HW_OCOTP_HDCP_KEY42.U = (v)) +#define HW_OCOTP_HDCP_KEY42_SET(v) (HW_OCOTP_HDCP_KEY42_WR(HW_OCOTP_HDCP_KEY42_RD() | (v))) +#define HW_OCOTP_HDCP_KEY42_CLR(v) (HW_OCOTP_HDCP_KEY42_WR(HW_OCOTP_HDCP_KEY42_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY42_TOG(v) (HW_OCOTP_HDCP_KEY42_WR(HW_OCOTP_HDCP_KEY42_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY42 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY42, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 11, word 2 (ADDR = 0x5a). + */ + +#define BP_OCOTP_HDCP_KEY42_BITS (0) //!< Bit position for OCOTP_HDCP_KEY42_BITS. +#define BM_OCOTP_HDCP_KEY42_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY42_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY42_BITS from a register value. +#define BG_OCOTP_HDCP_KEY42_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY42_BITS) >> BP_OCOTP_HDCP_KEY42_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY42_BITS. +#define BF_OCOTP_HDCP_KEY42_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY42_BITS) & BM_OCOTP_HDCP_KEY42_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY42_BITS(v) (HW_OCOTP_HDCP_KEY42_WR((HW_OCOTP_HDCP_KEY42_RD() & ~BM_OCOTP_HDCP_KEY42_BITS) | BF_OCOTP_HDCP_KEY42_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY43 - Value of OTP Bank11 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY43 - Value of OTP Bank11 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 11, word 3 (ADDR = + * 0x5b). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key43 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key43_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 11, word 3 (ADDR = 0x5b). + } B; +} hw_ocotp_hdcp_key43_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY43 register + */ +#define HW_OCOTP_HDCP_KEY43_ADDR (REGS_OCOTP_BASE + 0xab0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY43 (*(volatile hw_ocotp_hdcp_key43_t *) HW_OCOTP_HDCP_KEY43_ADDR) +#define HW_OCOTP_HDCP_KEY43_RD() (HW_OCOTP_HDCP_KEY43.U) +#define HW_OCOTP_HDCP_KEY43_WR(v) (HW_OCOTP_HDCP_KEY43.U = (v)) +#define HW_OCOTP_HDCP_KEY43_SET(v) (HW_OCOTP_HDCP_KEY43_WR(HW_OCOTP_HDCP_KEY43_RD() | (v))) +#define HW_OCOTP_HDCP_KEY43_CLR(v) (HW_OCOTP_HDCP_KEY43_WR(HW_OCOTP_HDCP_KEY43_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY43_TOG(v) (HW_OCOTP_HDCP_KEY43_WR(HW_OCOTP_HDCP_KEY43_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY43 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY43, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 11, word 3 (ADDR = 0x5b). + */ + +#define BP_OCOTP_HDCP_KEY43_BITS (0) //!< Bit position for OCOTP_HDCP_KEY43_BITS. +#define BM_OCOTP_HDCP_KEY43_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY43_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY43_BITS from a register value. +#define BG_OCOTP_HDCP_KEY43_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY43_BITS) >> BP_OCOTP_HDCP_KEY43_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY43_BITS. +#define BF_OCOTP_HDCP_KEY43_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY43_BITS) & BM_OCOTP_HDCP_KEY43_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY43_BITS(v) (HW_OCOTP_HDCP_KEY43_WR((HW_OCOTP_HDCP_KEY43_RD() & ~BM_OCOTP_HDCP_KEY43_BITS) | BF_OCOTP_HDCP_KEY43_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY44 - Value of OTP Bank11 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY44 - Value of OTP Bank11 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 11, word 4 (ADDR = + * 0x5c). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key44 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key44_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 11, word 4 (ADDR = 0x5c). + } B; +} hw_ocotp_hdcp_key44_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY44 register + */ +#define HW_OCOTP_HDCP_KEY44_ADDR (REGS_OCOTP_BASE + 0xac0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY44 (*(volatile hw_ocotp_hdcp_key44_t *) HW_OCOTP_HDCP_KEY44_ADDR) +#define HW_OCOTP_HDCP_KEY44_RD() (HW_OCOTP_HDCP_KEY44.U) +#define HW_OCOTP_HDCP_KEY44_WR(v) (HW_OCOTP_HDCP_KEY44.U = (v)) +#define HW_OCOTP_HDCP_KEY44_SET(v) (HW_OCOTP_HDCP_KEY44_WR(HW_OCOTP_HDCP_KEY44_RD() | (v))) +#define HW_OCOTP_HDCP_KEY44_CLR(v) (HW_OCOTP_HDCP_KEY44_WR(HW_OCOTP_HDCP_KEY44_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY44_TOG(v) (HW_OCOTP_HDCP_KEY44_WR(HW_OCOTP_HDCP_KEY44_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY44 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY44, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 11, word 4 (ADDR = 0x5c). + */ + +#define BP_OCOTP_HDCP_KEY44_BITS (0) //!< Bit position for OCOTP_HDCP_KEY44_BITS. +#define BM_OCOTP_HDCP_KEY44_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY44_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY44_BITS from a register value. +#define BG_OCOTP_HDCP_KEY44_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY44_BITS) >> BP_OCOTP_HDCP_KEY44_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY44_BITS. +#define BF_OCOTP_HDCP_KEY44_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY44_BITS) & BM_OCOTP_HDCP_KEY44_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY44_BITS(v) (HW_OCOTP_HDCP_KEY44_WR((HW_OCOTP_HDCP_KEY44_RD() & ~BM_OCOTP_HDCP_KEY44_BITS) | BF_OCOTP_HDCP_KEY44_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY45 - Value of OTP Bank11 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY45 - Value of OTP Bank11 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 11, word 5 (ADDR = + * 0x5d). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key45 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key45_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 11, word 5 (ADDR = 0x5d). + } B; +} hw_ocotp_hdcp_key45_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY45 register + */ +#define HW_OCOTP_HDCP_KEY45_ADDR (REGS_OCOTP_BASE + 0xad0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY45 (*(volatile hw_ocotp_hdcp_key45_t *) HW_OCOTP_HDCP_KEY45_ADDR) +#define HW_OCOTP_HDCP_KEY45_RD() (HW_OCOTP_HDCP_KEY45.U) +#define HW_OCOTP_HDCP_KEY45_WR(v) (HW_OCOTP_HDCP_KEY45.U = (v)) +#define HW_OCOTP_HDCP_KEY45_SET(v) (HW_OCOTP_HDCP_KEY45_WR(HW_OCOTP_HDCP_KEY45_RD() | (v))) +#define HW_OCOTP_HDCP_KEY45_CLR(v) (HW_OCOTP_HDCP_KEY45_WR(HW_OCOTP_HDCP_KEY45_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY45_TOG(v) (HW_OCOTP_HDCP_KEY45_WR(HW_OCOTP_HDCP_KEY45_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY45 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY45, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 11, word 5 (ADDR = 0x5d). + */ + +#define BP_OCOTP_HDCP_KEY45_BITS (0) //!< Bit position for OCOTP_HDCP_KEY45_BITS. +#define BM_OCOTP_HDCP_KEY45_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY45_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY45_BITS from a register value. +#define BG_OCOTP_HDCP_KEY45_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY45_BITS) >> BP_OCOTP_HDCP_KEY45_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY45_BITS. +#define BF_OCOTP_HDCP_KEY45_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY45_BITS) & BM_OCOTP_HDCP_KEY45_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY45_BITS(v) (HW_OCOTP_HDCP_KEY45_WR((HW_OCOTP_HDCP_KEY45_RD() & ~BM_OCOTP_HDCP_KEY45_BITS) | BF_OCOTP_HDCP_KEY45_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY46 - Value of OTP Bank11 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY46 - Value of OTP Bank11 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 11, word 6 (ADDR = + * 0x5e). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key46 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key46_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 11, word 6 (ADDR = 0x5e). + } B; +} hw_ocotp_hdcp_key46_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY46 register + */ +#define HW_OCOTP_HDCP_KEY46_ADDR (REGS_OCOTP_BASE + 0xae0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY46 (*(volatile hw_ocotp_hdcp_key46_t *) HW_OCOTP_HDCP_KEY46_ADDR) +#define HW_OCOTP_HDCP_KEY46_RD() (HW_OCOTP_HDCP_KEY46.U) +#define HW_OCOTP_HDCP_KEY46_WR(v) (HW_OCOTP_HDCP_KEY46.U = (v)) +#define HW_OCOTP_HDCP_KEY46_SET(v) (HW_OCOTP_HDCP_KEY46_WR(HW_OCOTP_HDCP_KEY46_RD() | (v))) +#define HW_OCOTP_HDCP_KEY46_CLR(v) (HW_OCOTP_HDCP_KEY46_WR(HW_OCOTP_HDCP_KEY46_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY46_TOG(v) (HW_OCOTP_HDCP_KEY46_WR(HW_OCOTP_HDCP_KEY46_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY46 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY46, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 11, word 6 (ADDR = 0x5e). + */ + +#define BP_OCOTP_HDCP_KEY46_BITS (0) //!< Bit position for OCOTP_HDCP_KEY46_BITS. +#define BM_OCOTP_HDCP_KEY46_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY46_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY46_BITS from a register value. +#define BG_OCOTP_HDCP_KEY46_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY46_BITS) >> BP_OCOTP_HDCP_KEY46_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY46_BITS. +#define BF_OCOTP_HDCP_KEY46_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY46_BITS) & BM_OCOTP_HDCP_KEY46_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY46_BITS(v) (HW_OCOTP_HDCP_KEY46_WR((HW_OCOTP_HDCP_KEY46_RD() & ~BM_OCOTP_HDCP_KEY46_BITS) | BF_OCOTP_HDCP_KEY46_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY47 - Value of OTP Bank11 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY47 - Value of OTP Bank11 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 11, word 7 (ADDR = + * 0x5f). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key47 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key47_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 11, word 7 (ADDR = 0x5f). + } B; +} hw_ocotp_hdcp_key47_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY47 register + */ +#define HW_OCOTP_HDCP_KEY47_ADDR (REGS_OCOTP_BASE + 0xaf0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY47 (*(volatile hw_ocotp_hdcp_key47_t *) HW_OCOTP_HDCP_KEY47_ADDR) +#define HW_OCOTP_HDCP_KEY47_RD() (HW_OCOTP_HDCP_KEY47.U) +#define HW_OCOTP_HDCP_KEY47_WR(v) (HW_OCOTP_HDCP_KEY47.U = (v)) +#define HW_OCOTP_HDCP_KEY47_SET(v) (HW_OCOTP_HDCP_KEY47_WR(HW_OCOTP_HDCP_KEY47_RD() | (v))) +#define HW_OCOTP_HDCP_KEY47_CLR(v) (HW_OCOTP_HDCP_KEY47_WR(HW_OCOTP_HDCP_KEY47_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY47_TOG(v) (HW_OCOTP_HDCP_KEY47_WR(HW_OCOTP_HDCP_KEY47_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY47 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY47, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 11, word 7 (ADDR = 0x5f). + */ + +#define BP_OCOTP_HDCP_KEY47_BITS (0) //!< Bit position for OCOTP_HDCP_KEY47_BITS. +#define BM_OCOTP_HDCP_KEY47_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY47_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY47_BITS from a register value. +#define BG_OCOTP_HDCP_KEY47_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY47_BITS) >> BP_OCOTP_HDCP_KEY47_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY47_BITS. +#define BF_OCOTP_HDCP_KEY47_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY47_BITS) & BM_OCOTP_HDCP_KEY47_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY47_BITS(v) (HW_OCOTP_HDCP_KEY47_WR((HW_OCOTP_HDCP_KEY47_RD() & ~BM_OCOTP_HDCP_KEY47_BITS) | BF_OCOTP_HDCP_KEY47_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY48 - Value of OTP Bank12 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY48 - Value of OTP Bank12 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 12, word 0 (ADDR = + * 0x60). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key48 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key48_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 12, word 0 (ADDR = 0x60). + } B; +} hw_ocotp_hdcp_key48_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY48 register + */ +#define HW_OCOTP_HDCP_KEY48_ADDR (REGS_OCOTP_BASE + 0xb00) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY48 (*(volatile hw_ocotp_hdcp_key48_t *) HW_OCOTP_HDCP_KEY48_ADDR) +#define HW_OCOTP_HDCP_KEY48_RD() (HW_OCOTP_HDCP_KEY48.U) +#define HW_OCOTP_HDCP_KEY48_WR(v) (HW_OCOTP_HDCP_KEY48.U = (v)) +#define HW_OCOTP_HDCP_KEY48_SET(v) (HW_OCOTP_HDCP_KEY48_WR(HW_OCOTP_HDCP_KEY48_RD() | (v))) +#define HW_OCOTP_HDCP_KEY48_CLR(v) (HW_OCOTP_HDCP_KEY48_WR(HW_OCOTP_HDCP_KEY48_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY48_TOG(v) (HW_OCOTP_HDCP_KEY48_WR(HW_OCOTP_HDCP_KEY48_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY48 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY48, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 12, word 0 (ADDR = 0x60). + */ + +#define BP_OCOTP_HDCP_KEY48_BITS (0) //!< Bit position for OCOTP_HDCP_KEY48_BITS. +#define BM_OCOTP_HDCP_KEY48_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY48_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY48_BITS from a register value. +#define BG_OCOTP_HDCP_KEY48_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY48_BITS) >> BP_OCOTP_HDCP_KEY48_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY48_BITS. +#define BF_OCOTP_HDCP_KEY48_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY48_BITS) & BM_OCOTP_HDCP_KEY48_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY48_BITS(v) (HW_OCOTP_HDCP_KEY48_WR((HW_OCOTP_HDCP_KEY48_RD() & ~BM_OCOTP_HDCP_KEY48_BITS) | BF_OCOTP_HDCP_KEY48_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY49 - Value of OTP Bank12 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY49 - Value of OTP Bank12 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 12, word 1 (ADDR = + * 0x61). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key49 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key49_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 12, word 1 (ADDR = 0x61). + } B; +} hw_ocotp_hdcp_key49_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY49 register + */ +#define HW_OCOTP_HDCP_KEY49_ADDR (REGS_OCOTP_BASE + 0xb10) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY49 (*(volatile hw_ocotp_hdcp_key49_t *) HW_OCOTP_HDCP_KEY49_ADDR) +#define HW_OCOTP_HDCP_KEY49_RD() (HW_OCOTP_HDCP_KEY49.U) +#define HW_OCOTP_HDCP_KEY49_WR(v) (HW_OCOTP_HDCP_KEY49.U = (v)) +#define HW_OCOTP_HDCP_KEY49_SET(v) (HW_OCOTP_HDCP_KEY49_WR(HW_OCOTP_HDCP_KEY49_RD() | (v))) +#define HW_OCOTP_HDCP_KEY49_CLR(v) (HW_OCOTP_HDCP_KEY49_WR(HW_OCOTP_HDCP_KEY49_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY49_TOG(v) (HW_OCOTP_HDCP_KEY49_WR(HW_OCOTP_HDCP_KEY49_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY49 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY49, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 12, word 1 (ADDR = 0x61). + */ + +#define BP_OCOTP_HDCP_KEY49_BITS (0) //!< Bit position for OCOTP_HDCP_KEY49_BITS. +#define BM_OCOTP_HDCP_KEY49_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY49_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY49_BITS from a register value. +#define BG_OCOTP_HDCP_KEY49_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY49_BITS) >> BP_OCOTP_HDCP_KEY49_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY49_BITS. +#define BF_OCOTP_HDCP_KEY49_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY49_BITS) & BM_OCOTP_HDCP_KEY49_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY49_BITS(v) (HW_OCOTP_HDCP_KEY49_WR((HW_OCOTP_HDCP_KEY49_RD() & ~BM_OCOTP_HDCP_KEY49_BITS) | BF_OCOTP_HDCP_KEY49_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY50 - Value of OTP Bank12 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY50 - Value of OTP Bank12 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 12, word 2 (ADDR = + * 0x62). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key50 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key50_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 12, word 2 (ADDR = 0x62). + } B; +} hw_ocotp_hdcp_key50_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY50 register + */ +#define HW_OCOTP_HDCP_KEY50_ADDR (REGS_OCOTP_BASE + 0xb20) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY50 (*(volatile hw_ocotp_hdcp_key50_t *) HW_OCOTP_HDCP_KEY50_ADDR) +#define HW_OCOTP_HDCP_KEY50_RD() (HW_OCOTP_HDCP_KEY50.U) +#define HW_OCOTP_HDCP_KEY50_WR(v) (HW_OCOTP_HDCP_KEY50.U = (v)) +#define HW_OCOTP_HDCP_KEY50_SET(v) (HW_OCOTP_HDCP_KEY50_WR(HW_OCOTP_HDCP_KEY50_RD() | (v))) +#define HW_OCOTP_HDCP_KEY50_CLR(v) (HW_OCOTP_HDCP_KEY50_WR(HW_OCOTP_HDCP_KEY50_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY50_TOG(v) (HW_OCOTP_HDCP_KEY50_WR(HW_OCOTP_HDCP_KEY50_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY50 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY50, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 12, word 2 (ADDR = 0x62). + */ + +#define BP_OCOTP_HDCP_KEY50_BITS (0) //!< Bit position for OCOTP_HDCP_KEY50_BITS. +#define BM_OCOTP_HDCP_KEY50_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY50_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY50_BITS from a register value. +#define BG_OCOTP_HDCP_KEY50_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY50_BITS) >> BP_OCOTP_HDCP_KEY50_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY50_BITS. +#define BF_OCOTP_HDCP_KEY50_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY50_BITS) & BM_OCOTP_HDCP_KEY50_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY50_BITS(v) (HW_OCOTP_HDCP_KEY50_WR((HW_OCOTP_HDCP_KEY50_RD() & ~BM_OCOTP_HDCP_KEY50_BITS) | BF_OCOTP_HDCP_KEY50_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY51 - Value of OTP Bank12 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY51 - Value of OTP Bank12 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 12, word 3 (ADDR = + * 0x63). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key51 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key51_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 12, word 3 (ADDR = 0x63). + } B; +} hw_ocotp_hdcp_key51_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY51 register + */ +#define HW_OCOTP_HDCP_KEY51_ADDR (REGS_OCOTP_BASE + 0xb30) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY51 (*(volatile hw_ocotp_hdcp_key51_t *) HW_OCOTP_HDCP_KEY51_ADDR) +#define HW_OCOTP_HDCP_KEY51_RD() (HW_OCOTP_HDCP_KEY51.U) +#define HW_OCOTP_HDCP_KEY51_WR(v) (HW_OCOTP_HDCP_KEY51.U = (v)) +#define HW_OCOTP_HDCP_KEY51_SET(v) (HW_OCOTP_HDCP_KEY51_WR(HW_OCOTP_HDCP_KEY51_RD() | (v))) +#define HW_OCOTP_HDCP_KEY51_CLR(v) (HW_OCOTP_HDCP_KEY51_WR(HW_OCOTP_HDCP_KEY51_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY51_TOG(v) (HW_OCOTP_HDCP_KEY51_WR(HW_OCOTP_HDCP_KEY51_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY51 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY51, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 12, word 3 (ADDR = 0x63). + */ + +#define BP_OCOTP_HDCP_KEY51_BITS (0) //!< Bit position for OCOTP_HDCP_KEY51_BITS. +#define BM_OCOTP_HDCP_KEY51_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY51_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY51_BITS from a register value. +#define BG_OCOTP_HDCP_KEY51_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY51_BITS) >> BP_OCOTP_HDCP_KEY51_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY51_BITS. +#define BF_OCOTP_HDCP_KEY51_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY51_BITS) & BM_OCOTP_HDCP_KEY51_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY51_BITS(v) (HW_OCOTP_HDCP_KEY51_WR((HW_OCOTP_HDCP_KEY51_RD() & ~BM_OCOTP_HDCP_KEY51_BITS) | BF_OCOTP_HDCP_KEY51_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY52 - Value of OTP Bank12 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY52 - Value of OTP Bank12 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 12, word 4 (ADDR = + * 0x64). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key52 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key52_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 12, word 4 (ADDR = 0x64). + } B; +} hw_ocotp_hdcp_key52_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY52 register + */ +#define HW_OCOTP_HDCP_KEY52_ADDR (REGS_OCOTP_BASE + 0xb40) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY52 (*(volatile hw_ocotp_hdcp_key52_t *) HW_OCOTP_HDCP_KEY52_ADDR) +#define HW_OCOTP_HDCP_KEY52_RD() (HW_OCOTP_HDCP_KEY52.U) +#define HW_OCOTP_HDCP_KEY52_WR(v) (HW_OCOTP_HDCP_KEY52.U = (v)) +#define HW_OCOTP_HDCP_KEY52_SET(v) (HW_OCOTP_HDCP_KEY52_WR(HW_OCOTP_HDCP_KEY52_RD() | (v))) +#define HW_OCOTP_HDCP_KEY52_CLR(v) (HW_OCOTP_HDCP_KEY52_WR(HW_OCOTP_HDCP_KEY52_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY52_TOG(v) (HW_OCOTP_HDCP_KEY52_WR(HW_OCOTP_HDCP_KEY52_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY52 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY52, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 12, word 4 (ADDR = 0x64). + */ + +#define BP_OCOTP_HDCP_KEY52_BITS (0) //!< Bit position for OCOTP_HDCP_KEY52_BITS. +#define BM_OCOTP_HDCP_KEY52_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY52_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY52_BITS from a register value. +#define BG_OCOTP_HDCP_KEY52_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY52_BITS) >> BP_OCOTP_HDCP_KEY52_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY52_BITS. +#define BF_OCOTP_HDCP_KEY52_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY52_BITS) & BM_OCOTP_HDCP_KEY52_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY52_BITS(v) (HW_OCOTP_HDCP_KEY52_WR((HW_OCOTP_HDCP_KEY52_RD() & ~BM_OCOTP_HDCP_KEY52_BITS) | BF_OCOTP_HDCP_KEY52_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY53 - Value of OTP Bank12 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY53 - Value of OTP Bank12 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 12, word 5 (ADDR = + * 0x65). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key53 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key53_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 12, word 5 (ADDR = 0x65). + } B; +} hw_ocotp_hdcp_key53_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY53 register + */ +#define HW_OCOTP_HDCP_KEY53_ADDR (REGS_OCOTP_BASE + 0xb50) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY53 (*(volatile hw_ocotp_hdcp_key53_t *) HW_OCOTP_HDCP_KEY53_ADDR) +#define HW_OCOTP_HDCP_KEY53_RD() (HW_OCOTP_HDCP_KEY53.U) +#define HW_OCOTP_HDCP_KEY53_WR(v) (HW_OCOTP_HDCP_KEY53.U = (v)) +#define HW_OCOTP_HDCP_KEY53_SET(v) (HW_OCOTP_HDCP_KEY53_WR(HW_OCOTP_HDCP_KEY53_RD() | (v))) +#define HW_OCOTP_HDCP_KEY53_CLR(v) (HW_OCOTP_HDCP_KEY53_WR(HW_OCOTP_HDCP_KEY53_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY53_TOG(v) (HW_OCOTP_HDCP_KEY53_WR(HW_OCOTP_HDCP_KEY53_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY53 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY53, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 12, word 5 (ADDR = 0x65). + */ + +#define BP_OCOTP_HDCP_KEY53_BITS (0) //!< Bit position for OCOTP_HDCP_KEY53_BITS. +#define BM_OCOTP_HDCP_KEY53_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY53_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY53_BITS from a register value. +#define BG_OCOTP_HDCP_KEY53_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY53_BITS) >> BP_OCOTP_HDCP_KEY53_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY53_BITS. +#define BF_OCOTP_HDCP_KEY53_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY53_BITS) & BM_OCOTP_HDCP_KEY53_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY53_BITS(v) (HW_OCOTP_HDCP_KEY53_WR((HW_OCOTP_HDCP_KEY53_RD() & ~BM_OCOTP_HDCP_KEY53_BITS) | BF_OCOTP_HDCP_KEY53_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY54 - Value of OTP Bank12 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY54 - Value of OTP Bank12 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 12, word 6 (ADDR = + * 0x66). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key54 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key54_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 12, word 6 (ADDR = 0x66). + } B; +} hw_ocotp_hdcp_key54_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY54 register + */ +#define HW_OCOTP_HDCP_KEY54_ADDR (REGS_OCOTP_BASE + 0xb60) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY54 (*(volatile hw_ocotp_hdcp_key54_t *) HW_OCOTP_HDCP_KEY54_ADDR) +#define HW_OCOTP_HDCP_KEY54_RD() (HW_OCOTP_HDCP_KEY54.U) +#define HW_OCOTP_HDCP_KEY54_WR(v) (HW_OCOTP_HDCP_KEY54.U = (v)) +#define HW_OCOTP_HDCP_KEY54_SET(v) (HW_OCOTP_HDCP_KEY54_WR(HW_OCOTP_HDCP_KEY54_RD() | (v))) +#define HW_OCOTP_HDCP_KEY54_CLR(v) (HW_OCOTP_HDCP_KEY54_WR(HW_OCOTP_HDCP_KEY54_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY54_TOG(v) (HW_OCOTP_HDCP_KEY54_WR(HW_OCOTP_HDCP_KEY54_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY54 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY54, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 12, word 6 (ADDR = 0x66). + */ + +#define BP_OCOTP_HDCP_KEY54_BITS (0) //!< Bit position for OCOTP_HDCP_KEY54_BITS. +#define BM_OCOTP_HDCP_KEY54_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY54_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY54_BITS from a register value. +#define BG_OCOTP_HDCP_KEY54_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY54_BITS) >> BP_OCOTP_HDCP_KEY54_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY54_BITS. +#define BF_OCOTP_HDCP_KEY54_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY54_BITS) & BM_OCOTP_HDCP_KEY54_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY54_BITS(v) (HW_OCOTP_HDCP_KEY54_WR((HW_OCOTP_HDCP_KEY54_RD() & ~BM_OCOTP_HDCP_KEY54_BITS) | BF_OCOTP_HDCP_KEY54_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY55 - Value of OTP Bank12 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY55 - Value of OTP Bank12 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 12, word 7 (ADDR = + * 0x67). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key55 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key55_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 12, word 7 (ADDR = 0x67). + } B; +} hw_ocotp_hdcp_key55_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY55 register + */ +#define HW_OCOTP_HDCP_KEY55_ADDR (REGS_OCOTP_BASE + 0xb70) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY55 (*(volatile hw_ocotp_hdcp_key55_t *) HW_OCOTP_HDCP_KEY55_ADDR) +#define HW_OCOTP_HDCP_KEY55_RD() (HW_OCOTP_HDCP_KEY55.U) +#define HW_OCOTP_HDCP_KEY55_WR(v) (HW_OCOTP_HDCP_KEY55.U = (v)) +#define HW_OCOTP_HDCP_KEY55_SET(v) (HW_OCOTP_HDCP_KEY55_WR(HW_OCOTP_HDCP_KEY55_RD() | (v))) +#define HW_OCOTP_HDCP_KEY55_CLR(v) (HW_OCOTP_HDCP_KEY55_WR(HW_OCOTP_HDCP_KEY55_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY55_TOG(v) (HW_OCOTP_HDCP_KEY55_WR(HW_OCOTP_HDCP_KEY55_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY55 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY55, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 12, word 7 (ADDR = 0x67). + */ + +#define BP_OCOTP_HDCP_KEY55_BITS (0) //!< Bit position for OCOTP_HDCP_KEY55_BITS. +#define BM_OCOTP_HDCP_KEY55_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY55_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY55_BITS from a register value. +#define BG_OCOTP_HDCP_KEY55_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY55_BITS) >> BP_OCOTP_HDCP_KEY55_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY55_BITS. +#define BF_OCOTP_HDCP_KEY55_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY55_BITS) & BM_OCOTP_HDCP_KEY55_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY55_BITS(v) (HW_OCOTP_HDCP_KEY55_WR((HW_OCOTP_HDCP_KEY55_RD() & ~BM_OCOTP_HDCP_KEY55_BITS) | BF_OCOTP_HDCP_KEY55_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY56 - Value of OTP Bank13 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY56 - Value of OTP Bank13 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 13, word 0 (ADDR = + * 0x68). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key56 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key56_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 13, word 0 (ADDR = 0x68). + } B; +} hw_ocotp_hdcp_key56_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY56 register + */ +#define HW_OCOTP_HDCP_KEY56_ADDR (REGS_OCOTP_BASE + 0xb80) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY56 (*(volatile hw_ocotp_hdcp_key56_t *) HW_OCOTP_HDCP_KEY56_ADDR) +#define HW_OCOTP_HDCP_KEY56_RD() (HW_OCOTP_HDCP_KEY56.U) +#define HW_OCOTP_HDCP_KEY56_WR(v) (HW_OCOTP_HDCP_KEY56.U = (v)) +#define HW_OCOTP_HDCP_KEY56_SET(v) (HW_OCOTP_HDCP_KEY56_WR(HW_OCOTP_HDCP_KEY56_RD() | (v))) +#define HW_OCOTP_HDCP_KEY56_CLR(v) (HW_OCOTP_HDCP_KEY56_WR(HW_OCOTP_HDCP_KEY56_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY56_TOG(v) (HW_OCOTP_HDCP_KEY56_WR(HW_OCOTP_HDCP_KEY56_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY56 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY56, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 13, word 0 (ADDR = 0x68). + */ + +#define BP_OCOTP_HDCP_KEY56_BITS (0) //!< Bit position for OCOTP_HDCP_KEY56_BITS. +#define BM_OCOTP_HDCP_KEY56_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY56_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY56_BITS from a register value. +#define BG_OCOTP_HDCP_KEY56_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY56_BITS) >> BP_OCOTP_HDCP_KEY56_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY56_BITS. +#define BF_OCOTP_HDCP_KEY56_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY56_BITS) & BM_OCOTP_HDCP_KEY56_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY56_BITS(v) (HW_OCOTP_HDCP_KEY56_WR((HW_OCOTP_HDCP_KEY56_RD() & ~BM_OCOTP_HDCP_KEY56_BITS) | BF_OCOTP_HDCP_KEY56_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY57 - Value of OTP Bank13 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY57 - Value of OTP Bank13 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 13, word 1 (ADDR = + * 0x69). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key57 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key57_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 13, word 1 (ADDR = 0x69). + } B; +} hw_ocotp_hdcp_key57_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY57 register + */ +#define HW_OCOTP_HDCP_KEY57_ADDR (REGS_OCOTP_BASE + 0xb90) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY57 (*(volatile hw_ocotp_hdcp_key57_t *) HW_OCOTP_HDCP_KEY57_ADDR) +#define HW_OCOTP_HDCP_KEY57_RD() (HW_OCOTP_HDCP_KEY57.U) +#define HW_OCOTP_HDCP_KEY57_WR(v) (HW_OCOTP_HDCP_KEY57.U = (v)) +#define HW_OCOTP_HDCP_KEY57_SET(v) (HW_OCOTP_HDCP_KEY57_WR(HW_OCOTP_HDCP_KEY57_RD() | (v))) +#define HW_OCOTP_HDCP_KEY57_CLR(v) (HW_OCOTP_HDCP_KEY57_WR(HW_OCOTP_HDCP_KEY57_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY57_TOG(v) (HW_OCOTP_HDCP_KEY57_WR(HW_OCOTP_HDCP_KEY57_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY57 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY57, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 13, word 1 (ADDR = 0x69). + */ + +#define BP_OCOTP_HDCP_KEY57_BITS (0) //!< Bit position for OCOTP_HDCP_KEY57_BITS. +#define BM_OCOTP_HDCP_KEY57_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY57_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY57_BITS from a register value. +#define BG_OCOTP_HDCP_KEY57_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY57_BITS) >> BP_OCOTP_HDCP_KEY57_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY57_BITS. +#define BF_OCOTP_HDCP_KEY57_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY57_BITS) & BM_OCOTP_HDCP_KEY57_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY57_BITS(v) (HW_OCOTP_HDCP_KEY57_WR((HW_OCOTP_HDCP_KEY57_RD() & ~BM_OCOTP_HDCP_KEY57_BITS) | BF_OCOTP_HDCP_KEY57_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY58 - Value of OTP Bank13 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY58 - Value of OTP Bank13 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 13, word 2 (ADDR = + * 0x6a). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key58 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key58_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 13, word 2 (ADDR = 0x6a). + } B; +} hw_ocotp_hdcp_key58_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY58 register + */ +#define HW_OCOTP_HDCP_KEY58_ADDR (REGS_OCOTP_BASE + 0xba0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY58 (*(volatile hw_ocotp_hdcp_key58_t *) HW_OCOTP_HDCP_KEY58_ADDR) +#define HW_OCOTP_HDCP_KEY58_RD() (HW_OCOTP_HDCP_KEY58.U) +#define HW_OCOTP_HDCP_KEY58_WR(v) (HW_OCOTP_HDCP_KEY58.U = (v)) +#define HW_OCOTP_HDCP_KEY58_SET(v) (HW_OCOTP_HDCP_KEY58_WR(HW_OCOTP_HDCP_KEY58_RD() | (v))) +#define HW_OCOTP_HDCP_KEY58_CLR(v) (HW_OCOTP_HDCP_KEY58_WR(HW_OCOTP_HDCP_KEY58_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY58_TOG(v) (HW_OCOTP_HDCP_KEY58_WR(HW_OCOTP_HDCP_KEY58_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY58 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY58, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 13, word 2 (ADDR = 0x6a). + */ + +#define BP_OCOTP_HDCP_KEY58_BITS (0) //!< Bit position for OCOTP_HDCP_KEY58_BITS. +#define BM_OCOTP_HDCP_KEY58_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY58_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY58_BITS from a register value. +#define BG_OCOTP_HDCP_KEY58_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY58_BITS) >> BP_OCOTP_HDCP_KEY58_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY58_BITS. +#define BF_OCOTP_HDCP_KEY58_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY58_BITS) & BM_OCOTP_HDCP_KEY58_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY58_BITS(v) (HW_OCOTP_HDCP_KEY58_WR((HW_OCOTP_HDCP_KEY58_RD() & ~BM_OCOTP_HDCP_KEY58_BITS) | BF_OCOTP_HDCP_KEY58_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY59 - Value of OTP Bank13 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY59 - Value of OTP Bank13 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 13, word 3 (ADDR = + * 0x6b). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key59 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key59_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 13, word 3 (ADDR = 0x6b). + } B; +} hw_ocotp_hdcp_key59_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY59 register + */ +#define HW_OCOTP_HDCP_KEY59_ADDR (REGS_OCOTP_BASE + 0xbb0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY59 (*(volatile hw_ocotp_hdcp_key59_t *) HW_OCOTP_HDCP_KEY59_ADDR) +#define HW_OCOTP_HDCP_KEY59_RD() (HW_OCOTP_HDCP_KEY59.U) +#define HW_OCOTP_HDCP_KEY59_WR(v) (HW_OCOTP_HDCP_KEY59.U = (v)) +#define HW_OCOTP_HDCP_KEY59_SET(v) (HW_OCOTP_HDCP_KEY59_WR(HW_OCOTP_HDCP_KEY59_RD() | (v))) +#define HW_OCOTP_HDCP_KEY59_CLR(v) (HW_OCOTP_HDCP_KEY59_WR(HW_OCOTP_HDCP_KEY59_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY59_TOG(v) (HW_OCOTP_HDCP_KEY59_WR(HW_OCOTP_HDCP_KEY59_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY59 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY59, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 13, word 3 (ADDR = 0x6b). + */ + +#define BP_OCOTP_HDCP_KEY59_BITS (0) //!< Bit position for OCOTP_HDCP_KEY59_BITS. +#define BM_OCOTP_HDCP_KEY59_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY59_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY59_BITS from a register value. +#define BG_OCOTP_HDCP_KEY59_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY59_BITS) >> BP_OCOTP_HDCP_KEY59_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY59_BITS. +#define BF_OCOTP_HDCP_KEY59_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY59_BITS) & BM_OCOTP_HDCP_KEY59_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY59_BITS(v) (HW_OCOTP_HDCP_KEY59_WR((HW_OCOTP_HDCP_KEY59_RD() & ~BM_OCOTP_HDCP_KEY59_BITS) | BF_OCOTP_HDCP_KEY59_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY60 - Value of OTP Bank13 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY60 - Value of OTP Bank13 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 13, word 4 (ADDR = + * 0x6c). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key60 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key60_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 13, word 4 (ADDR = 0x6c). + } B; +} hw_ocotp_hdcp_key60_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY60 register + */ +#define HW_OCOTP_HDCP_KEY60_ADDR (REGS_OCOTP_BASE + 0xbc0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY60 (*(volatile hw_ocotp_hdcp_key60_t *) HW_OCOTP_HDCP_KEY60_ADDR) +#define HW_OCOTP_HDCP_KEY60_RD() (HW_OCOTP_HDCP_KEY60.U) +#define HW_OCOTP_HDCP_KEY60_WR(v) (HW_OCOTP_HDCP_KEY60.U = (v)) +#define HW_OCOTP_HDCP_KEY60_SET(v) (HW_OCOTP_HDCP_KEY60_WR(HW_OCOTP_HDCP_KEY60_RD() | (v))) +#define HW_OCOTP_HDCP_KEY60_CLR(v) (HW_OCOTP_HDCP_KEY60_WR(HW_OCOTP_HDCP_KEY60_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY60_TOG(v) (HW_OCOTP_HDCP_KEY60_WR(HW_OCOTP_HDCP_KEY60_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY60 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY60, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 13, word 4 (ADDR = 0x6c). + */ + +#define BP_OCOTP_HDCP_KEY60_BITS (0) //!< Bit position for OCOTP_HDCP_KEY60_BITS. +#define BM_OCOTP_HDCP_KEY60_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY60_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY60_BITS from a register value. +#define BG_OCOTP_HDCP_KEY60_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY60_BITS) >> BP_OCOTP_HDCP_KEY60_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY60_BITS. +#define BF_OCOTP_HDCP_KEY60_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY60_BITS) & BM_OCOTP_HDCP_KEY60_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY60_BITS(v) (HW_OCOTP_HDCP_KEY60_WR((HW_OCOTP_HDCP_KEY60_RD() & ~BM_OCOTP_HDCP_KEY60_BITS) | BF_OCOTP_HDCP_KEY60_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY61 - Value of OTP Bank13 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY61 - Value of OTP Bank13 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 13, word 5 (ADDR = + * 0x6d). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key61 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key61_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 13, word 5 (ADDR = 0x6d). + } B; +} hw_ocotp_hdcp_key61_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY61 register + */ +#define HW_OCOTP_HDCP_KEY61_ADDR (REGS_OCOTP_BASE + 0xbd0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY61 (*(volatile hw_ocotp_hdcp_key61_t *) HW_OCOTP_HDCP_KEY61_ADDR) +#define HW_OCOTP_HDCP_KEY61_RD() (HW_OCOTP_HDCP_KEY61.U) +#define HW_OCOTP_HDCP_KEY61_WR(v) (HW_OCOTP_HDCP_KEY61.U = (v)) +#define HW_OCOTP_HDCP_KEY61_SET(v) (HW_OCOTP_HDCP_KEY61_WR(HW_OCOTP_HDCP_KEY61_RD() | (v))) +#define HW_OCOTP_HDCP_KEY61_CLR(v) (HW_OCOTP_HDCP_KEY61_WR(HW_OCOTP_HDCP_KEY61_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY61_TOG(v) (HW_OCOTP_HDCP_KEY61_WR(HW_OCOTP_HDCP_KEY61_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY61 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY61, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 13, word 5 (ADDR = 0x6d). + */ + +#define BP_OCOTP_HDCP_KEY61_BITS (0) //!< Bit position for OCOTP_HDCP_KEY61_BITS. +#define BM_OCOTP_HDCP_KEY61_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY61_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY61_BITS from a register value. +#define BG_OCOTP_HDCP_KEY61_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY61_BITS) >> BP_OCOTP_HDCP_KEY61_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY61_BITS. +#define BF_OCOTP_HDCP_KEY61_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY61_BITS) & BM_OCOTP_HDCP_KEY61_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY61_BITS(v) (HW_OCOTP_HDCP_KEY61_WR((HW_OCOTP_HDCP_KEY61_RD() & ~BM_OCOTP_HDCP_KEY61_BITS) | BF_OCOTP_HDCP_KEY61_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY62 - Value of OTP Bank13 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY62 - Value of OTP Bank13 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to Bank 13, word 6 (ADDR = 0x6e). + * EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key62 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key62_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of Bank 13, word 6 (ADDR = 0x6e). + } B; +} hw_ocotp_hdcp_key62_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY62 register + */ +#define HW_OCOTP_HDCP_KEY62_ADDR (REGS_OCOTP_BASE + 0xbe0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY62 (*(volatile hw_ocotp_hdcp_key62_t *) HW_OCOTP_HDCP_KEY62_ADDR) +#define HW_OCOTP_HDCP_KEY62_RD() (HW_OCOTP_HDCP_KEY62.U) +#define HW_OCOTP_HDCP_KEY62_WR(v) (HW_OCOTP_HDCP_KEY62.U = (v)) +#define HW_OCOTP_HDCP_KEY62_SET(v) (HW_OCOTP_HDCP_KEY62_WR(HW_OCOTP_HDCP_KEY62_RD() | (v))) +#define HW_OCOTP_HDCP_KEY62_CLR(v) (HW_OCOTP_HDCP_KEY62_WR(HW_OCOTP_HDCP_KEY62_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY62_TOG(v) (HW_OCOTP_HDCP_KEY62_WR(HW_OCOTP_HDCP_KEY62_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY62 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY62, field BITS[31:0] (RW) + * + * Reflects value of Bank 13, word 6 (ADDR = 0x6e). + */ + +#define BP_OCOTP_HDCP_KEY62_BITS (0) //!< Bit position for OCOTP_HDCP_KEY62_BITS. +#define BM_OCOTP_HDCP_KEY62_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY62_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY62_BITS from a register value. +#define BG_OCOTP_HDCP_KEY62_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY62_BITS) >> BP_OCOTP_HDCP_KEY62_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY62_BITS. +#define BF_OCOTP_HDCP_KEY62_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY62_BITS) & BM_OCOTP_HDCP_KEY62_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY62_BITS(v) (HW_OCOTP_HDCP_KEY62_WR((HW_OCOTP_HDCP_KEY62_RD() & ~BM_OCOTP_HDCP_KEY62_BITS) | BF_OCOTP_HDCP_KEY62_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY63 - Value of OTP Bank13 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY63 - Value of OTP Bank13 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 13, word 7 (ADDR = + * 0x6f). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key63 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key63_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 13, word 7 (ADDR = 0x6f). + } B; +} hw_ocotp_hdcp_key63_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY63 register + */ +#define HW_OCOTP_HDCP_KEY63_ADDR (REGS_OCOTP_BASE + 0xbf0) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY63 (*(volatile hw_ocotp_hdcp_key63_t *) HW_OCOTP_HDCP_KEY63_ADDR) +#define HW_OCOTP_HDCP_KEY63_RD() (HW_OCOTP_HDCP_KEY63.U) +#define HW_OCOTP_HDCP_KEY63_WR(v) (HW_OCOTP_HDCP_KEY63.U = (v)) +#define HW_OCOTP_HDCP_KEY63_SET(v) (HW_OCOTP_HDCP_KEY63_WR(HW_OCOTP_HDCP_KEY63_RD() | (v))) +#define HW_OCOTP_HDCP_KEY63_CLR(v) (HW_OCOTP_HDCP_KEY63_WR(HW_OCOTP_HDCP_KEY63_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY63_TOG(v) (HW_OCOTP_HDCP_KEY63_WR(HW_OCOTP_HDCP_KEY63_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY63 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY63, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 13, word 7 (ADDR = 0x6f). + */ + +#define BP_OCOTP_HDCP_KEY63_BITS (0) //!< Bit position for OCOTP_HDCP_KEY63_BITS. +#define BM_OCOTP_HDCP_KEY63_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY63_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY63_BITS from a register value. +#define BG_OCOTP_HDCP_KEY63_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY63_BITS) >> BP_OCOTP_HDCP_KEY63_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY63_BITS. +#define BF_OCOTP_HDCP_KEY63_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY63_BITS) & BM_OCOTP_HDCP_KEY63_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY63_BITS(v) (HW_OCOTP_HDCP_KEY63_WR((HW_OCOTP_HDCP_KEY63_RD() & ~BM_OCOTP_HDCP_KEY63_BITS) | BF_OCOTP_HDCP_KEY63_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY64 - Value of OTP Bank14 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY64 - Value of OTP Bank14 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 14, word 0 (ADDR = + * 0x70). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key64 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key64_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 14, word 0 (ADDR = 0x70). + } B; +} hw_ocotp_hdcp_key64_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY64 register + */ +#define HW_OCOTP_HDCP_KEY64_ADDR (REGS_OCOTP_BASE + 0xc00) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY64 (*(volatile hw_ocotp_hdcp_key64_t *) HW_OCOTP_HDCP_KEY64_ADDR) +#define HW_OCOTP_HDCP_KEY64_RD() (HW_OCOTP_HDCP_KEY64.U) +#define HW_OCOTP_HDCP_KEY64_WR(v) (HW_OCOTP_HDCP_KEY64.U = (v)) +#define HW_OCOTP_HDCP_KEY64_SET(v) (HW_OCOTP_HDCP_KEY64_WR(HW_OCOTP_HDCP_KEY64_RD() | (v))) +#define HW_OCOTP_HDCP_KEY64_CLR(v) (HW_OCOTP_HDCP_KEY64_WR(HW_OCOTP_HDCP_KEY64_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY64_TOG(v) (HW_OCOTP_HDCP_KEY64_WR(HW_OCOTP_HDCP_KEY64_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY64 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY64, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 14, word 0 (ADDR = 0x70). + */ + +#define BP_OCOTP_HDCP_KEY64_BITS (0) //!< Bit position for OCOTP_HDCP_KEY64_BITS. +#define BM_OCOTP_HDCP_KEY64_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY64_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY64_BITS from a register value. +#define BG_OCOTP_HDCP_KEY64_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY64_BITS) >> BP_OCOTP_HDCP_KEY64_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY64_BITS. +#define BF_OCOTP_HDCP_KEY64_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY64_BITS) & BM_OCOTP_HDCP_KEY64_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY64_BITS(v) (HW_OCOTP_HDCP_KEY64_WR((HW_OCOTP_HDCP_KEY64_RD() & ~BM_OCOTP_HDCP_KEY64_BITS) | BF_OCOTP_HDCP_KEY64_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY65 - Value of OTP Bank14 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY65 - Value of OTP Bank14 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 14, word 1 (ADDR = + * 0x71). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key65 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key65_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 14, word 1 (ADDR = 0x71). + } B; +} hw_ocotp_hdcp_key65_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY65 register + */ +#define HW_OCOTP_HDCP_KEY65_ADDR (REGS_OCOTP_BASE + 0xc10) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY65 (*(volatile hw_ocotp_hdcp_key65_t *) HW_OCOTP_HDCP_KEY65_ADDR) +#define HW_OCOTP_HDCP_KEY65_RD() (HW_OCOTP_HDCP_KEY65.U) +#define HW_OCOTP_HDCP_KEY65_WR(v) (HW_OCOTP_HDCP_KEY65.U = (v)) +#define HW_OCOTP_HDCP_KEY65_SET(v) (HW_OCOTP_HDCP_KEY65_WR(HW_OCOTP_HDCP_KEY65_RD() | (v))) +#define HW_OCOTP_HDCP_KEY65_CLR(v) (HW_OCOTP_HDCP_KEY65_WR(HW_OCOTP_HDCP_KEY65_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY65_TOG(v) (HW_OCOTP_HDCP_KEY65_WR(HW_OCOTP_HDCP_KEY65_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY65 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY65, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 14, word 1 (ADDR = 0x71). + */ + +#define BP_OCOTP_HDCP_KEY65_BITS (0) //!< Bit position for OCOTP_HDCP_KEY65_BITS. +#define BM_OCOTP_HDCP_KEY65_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY65_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY65_BITS from a register value. +#define BG_OCOTP_HDCP_KEY65_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY65_BITS) >> BP_OCOTP_HDCP_KEY65_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY65_BITS. +#define BF_OCOTP_HDCP_KEY65_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY65_BITS) & BM_OCOTP_HDCP_KEY65_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY65_BITS(v) (HW_OCOTP_HDCP_KEY65_WR((HW_OCOTP_HDCP_KEY65_RD() & ~BM_OCOTP_HDCP_KEY65_BITS) | BF_OCOTP_HDCP_KEY65_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY66 - Value of OTP Bank14 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY66 - Value of OTP Bank14 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 14, word 2 (ADDR = + * 0x72). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key66 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key66_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 14, word 2 (ADDR = 0x72). + } B; +} hw_ocotp_hdcp_key66_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY66 register + */ +#define HW_OCOTP_HDCP_KEY66_ADDR (REGS_OCOTP_BASE + 0xc20) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY66 (*(volatile hw_ocotp_hdcp_key66_t *) HW_OCOTP_HDCP_KEY66_ADDR) +#define HW_OCOTP_HDCP_KEY66_RD() (HW_OCOTP_HDCP_KEY66.U) +#define HW_OCOTP_HDCP_KEY66_WR(v) (HW_OCOTP_HDCP_KEY66.U = (v)) +#define HW_OCOTP_HDCP_KEY66_SET(v) (HW_OCOTP_HDCP_KEY66_WR(HW_OCOTP_HDCP_KEY66_RD() | (v))) +#define HW_OCOTP_HDCP_KEY66_CLR(v) (HW_OCOTP_HDCP_KEY66_WR(HW_OCOTP_HDCP_KEY66_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY66_TOG(v) (HW_OCOTP_HDCP_KEY66_WR(HW_OCOTP_HDCP_KEY66_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY66 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY66, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 14, word 2 (ADDR = 0x72). + */ + +#define BP_OCOTP_HDCP_KEY66_BITS (0) //!< Bit position for OCOTP_HDCP_KEY66_BITS. +#define BM_OCOTP_HDCP_KEY66_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY66_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY66_BITS from a register value. +#define BG_OCOTP_HDCP_KEY66_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY66_BITS) >> BP_OCOTP_HDCP_KEY66_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY66_BITS. +#define BF_OCOTP_HDCP_KEY66_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY66_BITS) & BM_OCOTP_HDCP_KEY66_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY66_BITS(v) (HW_OCOTP_HDCP_KEY66_WR((HW_OCOTP_HDCP_KEY66_RD() & ~BM_OCOTP_HDCP_KEY66_BITS) | BF_OCOTP_HDCP_KEY66_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY67 - Value of OTP Bank14 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY67 - Value of OTP Bank14 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 14, word 3 (ADDR = + * 0x73). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key67 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key67_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 14, word 3 (ADDR = 0x73). + } B; +} hw_ocotp_hdcp_key67_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY67 register + */ +#define HW_OCOTP_HDCP_KEY67_ADDR (REGS_OCOTP_BASE + 0xc30) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY67 (*(volatile hw_ocotp_hdcp_key67_t *) HW_OCOTP_HDCP_KEY67_ADDR) +#define HW_OCOTP_HDCP_KEY67_RD() (HW_OCOTP_HDCP_KEY67.U) +#define HW_OCOTP_HDCP_KEY67_WR(v) (HW_OCOTP_HDCP_KEY67.U = (v)) +#define HW_OCOTP_HDCP_KEY67_SET(v) (HW_OCOTP_HDCP_KEY67_WR(HW_OCOTP_HDCP_KEY67_RD() | (v))) +#define HW_OCOTP_HDCP_KEY67_CLR(v) (HW_OCOTP_HDCP_KEY67_WR(HW_OCOTP_HDCP_KEY67_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY67_TOG(v) (HW_OCOTP_HDCP_KEY67_WR(HW_OCOTP_HDCP_KEY67_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY67 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY67, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 14, word 3 (ADDR = 0x73). + */ + +#define BP_OCOTP_HDCP_KEY67_BITS (0) //!< Bit position for OCOTP_HDCP_KEY67_BITS. +#define BM_OCOTP_HDCP_KEY67_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY67_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY67_BITS from a register value. +#define BG_OCOTP_HDCP_KEY67_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY67_BITS) >> BP_OCOTP_HDCP_KEY67_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY67_BITS. +#define BF_OCOTP_HDCP_KEY67_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY67_BITS) & BM_OCOTP_HDCP_KEY67_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY67_BITS(v) (HW_OCOTP_HDCP_KEY67_WR((HW_OCOTP_HDCP_KEY67_RD() & ~BM_OCOTP_HDCP_KEY67_BITS) | BF_OCOTP_HDCP_KEY67_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY68 - Value of OTP Bank14 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY68 - Value of OTP Bank14 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 14, word 4 (ADDR = + * 0x74). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key68 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key68_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 14, word 4 (ADDR = 0x74). + } B; +} hw_ocotp_hdcp_key68_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY68 register + */ +#define HW_OCOTP_HDCP_KEY68_ADDR (REGS_OCOTP_BASE + 0xc40) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY68 (*(volatile hw_ocotp_hdcp_key68_t *) HW_OCOTP_HDCP_KEY68_ADDR) +#define HW_OCOTP_HDCP_KEY68_RD() (HW_OCOTP_HDCP_KEY68.U) +#define HW_OCOTP_HDCP_KEY68_WR(v) (HW_OCOTP_HDCP_KEY68.U = (v)) +#define HW_OCOTP_HDCP_KEY68_SET(v) (HW_OCOTP_HDCP_KEY68_WR(HW_OCOTP_HDCP_KEY68_RD() | (v))) +#define HW_OCOTP_HDCP_KEY68_CLR(v) (HW_OCOTP_HDCP_KEY68_WR(HW_OCOTP_HDCP_KEY68_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY68_TOG(v) (HW_OCOTP_HDCP_KEY68_WR(HW_OCOTP_HDCP_KEY68_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY68 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY68, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 14, word 4 (ADDR = 0x74). + */ + +#define BP_OCOTP_HDCP_KEY68_BITS (0) //!< Bit position for OCOTP_HDCP_KEY68_BITS. +#define BM_OCOTP_HDCP_KEY68_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY68_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY68_BITS from a register value. +#define BG_OCOTP_HDCP_KEY68_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY68_BITS) >> BP_OCOTP_HDCP_KEY68_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY68_BITS. +#define BF_OCOTP_HDCP_KEY68_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY68_BITS) & BM_OCOTP_HDCP_KEY68_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY68_BITS(v) (HW_OCOTP_HDCP_KEY68_WR((HW_OCOTP_HDCP_KEY68_RD() & ~BM_OCOTP_HDCP_KEY68_BITS) | BF_OCOTP_HDCP_KEY68_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY69 - Value of OTP Bank14 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY69 - Value of OTP Bank14 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 14, word 5 (ADDR = + * 0x75). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key69 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key69_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 14, word 5 (ADDR = 0x75). + } B; +} hw_ocotp_hdcp_key69_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY69 register + */ +#define HW_OCOTP_HDCP_KEY69_ADDR (REGS_OCOTP_BASE + 0xc50) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY69 (*(volatile hw_ocotp_hdcp_key69_t *) HW_OCOTP_HDCP_KEY69_ADDR) +#define HW_OCOTP_HDCP_KEY69_RD() (HW_OCOTP_HDCP_KEY69.U) +#define HW_OCOTP_HDCP_KEY69_WR(v) (HW_OCOTP_HDCP_KEY69.U = (v)) +#define HW_OCOTP_HDCP_KEY69_SET(v) (HW_OCOTP_HDCP_KEY69_WR(HW_OCOTP_HDCP_KEY69_RD() | (v))) +#define HW_OCOTP_HDCP_KEY69_CLR(v) (HW_OCOTP_HDCP_KEY69_WR(HW_OCOTP_HDCP_KEY69_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY69_TOG(v) (HW_OCOTP_HDCP_KEY69_WR(HW_OCOTP_HDCP_KEY69_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY69 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY69, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 14, word 5 (ADDR = 0x75). + */ + +#define BP_OCOTP_HDCP_KEY69_BITS (0) //!< Bit position for OCOTP_HDCP_KEY69_BITS. +#define BM_OCOTP_HDCP_KEY69_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY69_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY69_BITS from a register value. +#define BG_OCOTP_HDCP_KEY69_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY69_BITS) >> BP_OCOTP_HDCP_KEY69_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY69_BITS. +#define BF_OCOTP_HDCP_KEY69_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY69_BITS) & BM_OCOTP_HDCP_KEY69_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY69_BITS(v) (HW_OCOTP_HDCP_KEY69_WR((HW_OCOTP_HDCP_KEY69_RD() & ~BM_OCOTP_HDCP_KEY69_BITS) | BF_OCOTP_HDCP_KEY69_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY70 - Value of OTP Bank14 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY70 - Value of OTP Bank14 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 14, word 6 (ADDR = + * 0x76). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key70 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key70_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 14, word 6 (ADDR = 0x76). + } B; +} hw_ocotp_hdcp_key70_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY70 register + */ +#define HW_OCOTP_HDCP_KEY70_ADDR (REGS_OCOTP_BASE + 0xc60) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY70 (*(volatile hw_ocotp_hdcp_key70_t *) HW_OCOTP_HDCP_KEY70_ADDR) +#define HW_OCOTP_HDCP_KEY70_RD() (HW_OCOTP_HDCP_KEY70.U) +#define HW_OCOTP_HDCP_KEY70_WR(v) (HW_OCOTP_HDCP_KEY70.U = (v)) +#define HW_OCOTP_HDCP_KEY70_SET(v) (HW_OCOTP_HDCP_KEY70_WR(HW_OCOTP_HDCP_KEY70_RD() | (v))) +#define HW_OCOTP_HDCP_KEY70_CLR(v) (HW_OCOTP_HDCP_KEY70_WR(HW_OCOTP_HDCP_KEY70_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY70_TOG(v) (HW_OCOTP_HDCP_KEY70_WR(HW_OCOTP_HDCP_KEY70_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY70 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY70, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 14, word 6 (ADDR = 0x76). + */ + +#define BP_OCOTP_HDCP_KEY70_BITS (0) //!< Bit position for OCOTP_HDCP_KEY70_BITS. +#define BM_OCOTP_HDCP_KEY70_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY70_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY70_BITS from a register value. +#define BG_OCOTP_HDCP_KEY70_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY70_BITS) >> BP_OCOTP_HDCP_KEY70_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY70_BITS. +#define BF_OCOTP_HDCP_KEY70_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY70_BITS) & BM_OCOTP_HDCP_KEY70_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY70_BITS(v) (HW_OCOTP_HDCP_KEY70_WR((HW_OCOTP_HDCP_KEY70_RD() & ~BM_OCOTP_HDCP_KEY70_BITS) | BF_OCOTP_HDCP_KEY70_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_HDCP_KEY71 - Value of OTP Bank14 Word7 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_HDCP_KEY71 - Value of OTP Bank14 Word7 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 14, word 7 (ADDR = + * 0x77). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_hdcp_key71 +{ + reg32_t U; + struct _hw_ocotp_hdcp_key71_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 14, word 7 (ADDR = 0x77). + } B; +} hw_ocotp_hdcp_key71_t; +#endif + +/* + * constants & macros for entire OCOTP_HDCP_KEY71 register + */ +#define HW_OCOTP_HDCP_KEY71_ADDR (REGS_OCOTP_BASE + 0xc70) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_HDCP_KEY71 (*(volatile hw_ocotp_hdcp_key71_t *) HW_OCOTP_HDCP_KEY71_ADDR) +#define HW_OCOTP_HDCP_KEY71_RD() (HW_OCOTP_HDCP_KEY71.U) +#define HW_OCOTP_HDCP_KEY71_WR(v) (HW_OCOTP_HDCP_KEY71.U = (v)) +#define HW_OCOTP_HDCP_KEY71_SET(v) (HW_OCOTP_HDCP_KEY71_WR(HW_OCOTP_HDCP_KEY71_RD() | (v))) +#define HW_OCOTP_HDCP_KEY71_CLR(v) (HW_OCOTP_HDCP_KEY71_WR(HW_OCOTP_HDCP_KEY71_RD() & ~(v))) +#define HW_OCOTP_HDCP_KEY71_TOG(v) (HW_OCOTP_HDCP_KEY71_WR(HW_OCOTP_HDCP_KEY71_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_HDCP_KEY71 bitfields + */ + +/* --- Register HW_OCOTP_HDCP_KEY71, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 14, word 7 (ADDR = 0x77). + */ + +#define BP_OCOTP_HDCP_KEY71_BITS (0) //!< Bit position for OCOTP_HDCP_KEY71_BITS. +#define BM_OCOTP_HDCP_KEY71_BITS (0xffffffff) //!< Bit mask for OCOTP_HDCP_KEY71_BITS. + +//! @brief Get value of OCOTP_HDCP_KEY71_BITS from a register value. +#define BG_OCOTP_HDCP_KEY71_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_HDCP_KEY71_BITS) >> BP_OCOTP_HDCP_KEY71_BITS) + +//! @brief Format value for bitfield OCOTP_HDCP_KEY71_BITS. +#define BF_OCOTP_HDCP_KEY71_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_HDCP_KEY71_BITS) & BM_OCOTP_HDCP_KEY71_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_HDCP_KEY71_BITS(v) (HW_OCOTP_HDCP_KEY71_WR((HW_OCOTP_HDCP_KEY71_RD() & ~BM_OCOTP_HDCP_KEY71_BITS) | BF_OCOTP_HDCP_KEY71_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC0 - Value of OTP Bank15 Word0 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC0 - Value of OTP Bank15 Word0 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 15, word 0 (ADDR = + * 0x78). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_crc0 +{ + reg32_t U; + struct _hw_ocotp_crc0_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 15, word 0 (ADDR = 0x78). + } B; +} hw_ocotp_crc0_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC0 register + */ +#define HW_OCOTP_CRC0_ADDR (REGS_OCOTP_BASE + 0xd00) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC0 (*(volatile hw_ocotp_crc0_t *) HW_OCOTP_CRC0_ADDR) +#define HW_OCOTP_CRC0_RD() (HW_OCOTP_CRC0.U) +#define HW_OCOTP_CRC0_WR(v) (HW_OCOTP_CRC0.U = (v)) +#define HW_OCOTP_CRC0_SET(v) (HW_OCOTP_CRC0_WR(HW_OCOTP_CRC0_RD() | (v))) +#define HW_OCOTP_CRC0_CLR(v) (HW_OCOTP_CRC0_WR(HW_OCOTP_CRC0_RD() & ~(v))) +#define HW_OCOTP_CRC0_TOG(v) (HW_OCOTP_CRC0_WR(HW_OCOTP_CRC0_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC0 bitfields + */ + +/* --- Register HW_OCOTP_CRC0, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 15, word 0 (ADDR = 0x78). + */ + +#define BP_OCOTP_CRC0_BITS (0) //!< Bit position for OCOTP_CRC0_BITS. +#define BM_OCOTP_CRC0_BITS (0xffffffff) //!< Bit mask for OCOTP_CRC0_BITS. + +//! @brief Get value of OCOTP_CRC0_BITS from a register value. +#define BG_OCOTP_CRC0_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC0_BITS) >> BP_OCOTP_CRC0_BITS) + +//! @brief Format value for bitfield OCOTP_CRC0_BITS. +#define BF_OCOTP_CRC0_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC0_BITS) & BM_OCOTP_CRC0_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CRC0_BITS(v) (HW_OCOTP_CRC0_WR((HW_OCOTP_CRC0_RD() & ~BM_OCOTP_CRC0_BITS) | BF_OCOTP_CRC0_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC1 - Value of OTP Bank15 Word1 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC1 - Value of OTP Bank15 Word1 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 15, word 1 (ADDR = + * 0x79). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_crc1 +{ + reg32_t U; + struct _hw_ocotp_crc1_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 15, word 1 (ADDR = 0x79). + } B; +} hw_ocotp_crc1_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC1 register + */ +#define HW_OCOTP_CRC1_ADDR (REGS_OCOTP_BASE + 0xd10) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC1 (*(volatile hw_ocotp_crc1_t *) HW_OCOTP_CRC1_ADDR) +#define HW_OCOTP_CRC1_RD() (HW_OCOTP_CRC1.U) +#define HW_OCOTP_CRC1_WR(v) (HW_OCOTP_CRC1.U = (v)) +#define HW_OCOTP_CRC1_SET(v) (HW_OCOTP_CRC1_WR(HW_OCOTP_CRC1_RD() | (v))) +#define HW_OCOTP_CRC1_CLR(v) (HW_OCOTP_CRC1_WR(HW_OCOTP_CRC1_RD() & ~(v))) +#define HW_OCOTP_CRC1_TOG(v) (HW_OCOTP_CRC1_WR(HW_OCOTP_CRC1_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC1 bitfields + */ + +/* --- Register HW_OCOTP_CRC1, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 15, word 1 (ADDR = 0x79). + */ + +#define BP_OCOTP_CRC1_BITS (0) //!< Bit position for OCOTP_CRC1_BITS. +#define BM_OCOTP_CRC1_BITS (0xffffffff) //!< Bit mask for OCOTP_CRC1_BITS. + +//! @brief Get value of OCOTP_CRC1_BITS from a register value. +#define BG_OCOTP_CRC1_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC1_BITS) >> BP_OCOTP_CRC1_BITS) + +//! @brief Format value for bitfield OCOTP_CRC1_BITS. +#define BF_OCOTP_CRC1_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC1_BITS) & BM_OCOTP_CRC1_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CRC1_BITS(v) (HW_OCOTP_CRC1_WR((HW_OCOTP_CRC1_RD() & ~BM_OCOTP_CRC1_BITS) | BF_OCOTP_CRC1_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC2 - Value of OTP Bank15 Word2 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC2 - Value of OTP Bank15 Word2 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 15, word 2 (ADDR = + * 0x7A). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_crc2 +{ + reg32_t U; + struct _hw_ocotp_crc2_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 15, word 2 (ADDR = 0x7A). + } B; +} hw_ocotp_crc2_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC2 register + */ +#define HW_OCOTP_CRC2_ADDR (REGS_OCOTP_BASE + 0xd20) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC2 (*(volatile hw_ocotp_crc2_t *) HW_OCOTP_CRC2_ADDR) +#define HW_OCOTP_CRC2_RD() (HW_OCOTP_CRC2.U) +#define HW_OCOTP_CRC2_WR(v) (HW_OCOTP_CRC2.U = (v)) +#define HW_OCOTP_CRC2_SET(v) (HW_OCOTP_CRC2_WR(HW_OCOTP_CRC2_RD() | (v))) +#define HW_OCOTP_CRC2_CLR(v) (HW_OCOTP_CRC2_WR(HW_OCOTP_CRC2_RD() & ~(v))) +#define HW_OCOTP_CRC2_TOG(v) (HW_OCOTP_CRC2_WR(HW_OCOTP_CRC2_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC2 bitfields + */ + +/* --- Register HW_OCOTP_CRC2, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 15, word 2 (ADDR = 0x7A). + */ + +#define BP_OCOTP_CRC2_BITS (0) //!< Bit position for OCOTP_CRC2_BITS. +#define BM_OCOTP_CRC2_BITS (0xffffffff) //!< Bit mask for OCOTP_CRC2_BITS. + +//! @brief Get value of OCOTP_CRC2_BITS from a register value. +#define BG_OCOTP_CRC2_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC2_BITS) >> BP_OCOTP_CRC2_BITS) + +//! @brief Format value for bitfield OCOTP_CRC2_BITS. +#define BF_OCOTP_CRC2_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC2_BITS) & BM_OCOTP_CRC2_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CRC2_BITS(v) (HW_OCOTP_CRC2_WR((HW_OCOTP_CRC2_RD() & ~BM_OCOTP_CRC2_BITS) | BF_OCOTP_CRC2_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC3 - Value of OTP Bank15 Word3 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC3 - Value of OTP Bank15 Word3 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 15, word 3 (ADDR = + * 0x7B). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_crc3 +{ + reg32_t U; + struct _hw_ocotp_crc3_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 15, word 3 (ADDR = 0x7B). + } B; +} hw_ocotp_crc3_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC3 register + */ +#define HW_OCOTP_CRC3_ADDR (REGS_OCOTP_BASE + 0xd30) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC3 (*(volatile hw_ocotp_crc3_t *) HW_OCOTP_CRC3_ADDR) +#define HW_OCOTP_CRC3_RD() (HW_OCOTP_CRC3.U) +#define HW_OCOTP_CRC3_WR(v) (HW_OCOTP_CRC3.U = (v)) +#define HW_OCOTP_CRC3_SET(v) (HW_OCOTP_CRC3_WR(HW_OCOTP_CRC3_RD() | (v))) +#define HW_OCOTP_CRC3_CLR(v) (HW_OCOTP_CRC3_WR(HW_OCOTP_CRC3_RD() & ~(v))) +#define HW_OCOTP_CRC3_TOG(v) (HW_OCOTP_CRC3_WR(HW_OCOTP_CRC3_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC3 bitfields + */ + +/* --- Register HW_OCOTP_CRC3, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 15, word 3 (ADDR = 0x7B). + */ + +#define BP_OCOTP_CRC3_BITS (0) //!< Bit position for OCOTP_CRC3_BITS. +#define BM_OCOTP_CRC3_BITS (0xffffffff) //!< Bit mask for OCOTP_CRC3_BITS. + +//! @brief Get value of OCOTP_CRC3_BITS from a register value. +#define BG_OCOTP_CRC3_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC3_BITS) >> BP_OCOTP_CRC3_BITS) + +//! @brief Format value for bitfield OCOTP_CRC3_BITS. +#define BF_OCOTP_CRC3_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC3_BITS) & BM_OCOTP_CRC3_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CRC3_BITS(v) (HW_OCOTP_CRC3_WR((HW_OCOTP_CRC3_RD() & ~BM_OCOTP_CRC3_BITS) | BF_OCOTP_CRC3_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC4 - Value of OTP Bank15 Word4 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC4 - Value of OTP Bank15 Word4 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 15, word 4 (ADDR = + * 0x7C). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_crc4 +{ + reg32_t U; + struct _hw_ocotp_crc4_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 15, word 4 (ADDR = 0x7C). + } B; +} hw_ocotp_crc4_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC4 register + */ +#define HW_OCOTP_CRC4_ADDR (REGS_OCOTP_BASE + 0xd40) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC4 (*(volatile hw_ocotp_crc4_t *) HW_OCOTP_CRC4_ADDR) +#define HW_OCOTP_CRC4_RD() (HW_OCOTP_CRC4.U) +#define HW_OCOTP_CRC4_WR(v) (HW_OCOTP_CRC4.U = (v)) +#define HW_OCOTP_CRC4_SET(v) (HW_OCOTP_CRC4_WR(HW_OCOTP_CRC4_RD() | (v))) +#define HW_OCOTP_CRC4_CLR(v) (HW_OCOTP_CRC4_WR(HW_OCOTP_CRC4_RD() & ~(v))) +#define HW_OCOTP_CRC4_TOG(v) (HW_OCOTP_CRC4_WR(HW_OCOTP_CRC4_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC4 bitfields + */ + +/* --- Register HW_OCOTP_CRC4, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 15, word 4 (ADDR = 0x7C). + */ + +#define BP_OCOTP_CRC4_BITS (0) //!< Bit position for OCOTP_CRC4_BITS. +#define BM_OCOTP_CRC4_BITS (0xffffffff) //!< Bit mask for OCOTP_CRC4_BITS. + +//! @brief Get value of OCOTP_CRC4_BITS from a register value. +#define BG_OCOTP_CRC4_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC4_BITS) >> BP_OCOTP_CRC4_BITS) + +//! @brief Format value for bitfield OCOTP_CRC4_BITS. +#define BF_OCOTP_CRC4_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC4_BITS) & BM_OCOTP_CRC4_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CRC4_BITS(v) (HW_OCOTP_CRC4_WR((HW_OCOTP_CRC4_RD() & ~BM_OCOTP_CRC4_BITS) | BF_OCOTP_CRC4_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC5 - Value of OTP Bank15 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC5 - Value of OTP Bank15 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 15, word 5 (ADDR = + * 0x7D). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_crc5 +{ + reg32_t U; + struct _hw_ocotp_crc5_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 15, word 5 (ADDR = 0x7D). + } B; +} hw_ocotp_crc5_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC5 register + */ +#define HW_OCOTP_CRC5_ADDR (REGS_OCOTP_BASE + 0xd50) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC5 (*(volatile hw_ocotp_crc5_t *) HW_OCOTP_CRC5_ADDR) +#define HW_OCOTP_CRC5_RD() (HW_OCOTP_CRC5.U) +#define HW_OCOTP_CRC5_WR(v) (HW_OCOTP_CRC5.U = (v)) +#define HW_OCOTP_CRC5_SET(v) (HW_OCOTP_CRC5_WR(HW_OCOTP_CRC5_RD() | (v))) +#define HW_OCOTP_CRC5_CLR(v) (HW_OCOTP_CRC5_WR(HW_OCOTP_CRC5_RD() & ~(v))) +#define HW_OCOTP_CRC5_TOG(v) (HW_OCOTP_CRC5_WR(HW_OCOTP_CRC5_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC5 bitfields + */ + +/* --- Register HW_OCOTP_CRC5, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 15, word 5 (ADDR = 0x7D). + */ + +#define BP_OCOTP_CRC5_BITS (0) //!< Bit position for OCOTP_CRC5_BITS. +#define BM_OCOTP_CRC5_BITS (0xffffffff) //!< Bit mask for OCOTP_CRC5_BITS. + +//! @brief Get value of OCOTP_CRC5_BITS from a register value. +#define BG_OCOTP_CRC5_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC5_BITS) >> BP_OCOTP_CRC5_BITS) + +//! @brief Format value for bitfield OCOTP_CRC5_BITS. +#define BF_OCOTP_CRC5_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC5_BITS) & BM_OCOTP_CRC5_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CRC5_BITS(v) (HW_OCOTP_CRC5_WR((HW_OCOTP_CRC5_RD() & ~BM_OCOTP_CRC5_BITS) | BF_OCOTP_CRC5_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC6 - Value of OTP Bank15 Word6 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC6 - Value of OTP Bank15 Word6 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 15, word 6 (ADDR = + * 0x7E). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_crc6 +{ + reg32_t U; + struct _hw_ocotp_crc6_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 15, word 6 (ADDR = 0x7E). + } B; +} hw_ocotp_crc6_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC6 register + */ +#define HW_OCOTP_CRC6_ADDR (REGS_OCOTP_BASE + 0xd60) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC6 (*(volatile hw_ocotp_crc6_t *) HW_OCOTP_CRC6_ADDR) +#define HW_OCOTP_CRC6_RD() (HW_OCOTP_CRC6.U) +#define HW_OCOTP_CRC6_WR(v) (HW_OCOTP_CRC6.U = (v)) +#define HW_OCOTP_CRC6_SET(v) (HW_OCOTP_CRC6_WR(HW_OCOTP_CRC6_RD() | (v))) +#define HW_OCOTP_CRC6_CLR(v) (HW_OCOTP_CRC6_WR(HW_OCOTP_CRC6_RD() & ~(v))) +#define HW_OCOTP_CRC6_TOG(v) (HW_OCOTP_CRC6_WR(HW_OCOTP_CRC6_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC6 bitfields + */ + +/* --- Register HW_OCOTP_CRC6, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 15, word 6 (ADDR = 0x7E). + */ + +#define BP_OCOTP_CRC6_BITS (0) //!< Bit position for OCOTP_CRC6_BITS. +#define BM_OCOTP_CRC6_BITS (0xffffffff) //!< Bit mask for OCOTP_CRC6_BITS. + +//! @brief Get value of OCOTP_CRC6_BITS from a register value. +#define BG_OCOTP_CRC6_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC6_BITS) >> BP_OCOTP_CRC6_BITS) + +//! @brief Format value for bitfield OCOTP_CRC6_BITS. +#define BF_OCOTP_CRC6_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC6_BITS) & BM_OCOTP_CRC6_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CRC6_BITS(v) (HW_OCOTP_CRC6_WR((HW_OCOTP_CRC6_RD() & ~BM_OCOTP_CRC6_BITS) | BF_OCOTP_CRC6_BITS(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_OCOTP_CRC7 - Value of OTP Bank15 Word5 (HW Capabilities) +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_OCOTP_CRC7 - Value of OTP Bank15 Word5 (HW Capabilities) (RW) + * + * Reset value: 0x00000000 + * + * Copied from the OTP automatically after reset. Can be re-loaded by setting + * HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP Bank 15, word 7 (ADDR = + * 0x7F). EXAMPLE Empty Example. + */ +typedef union _hw_ocotp_crc7 +{ + reg32_t U; + struct _hw_ocotp_crc7_bitfields + { + unsigned BITS : 32; //!< [31:0] Reflects value of OTP Bank 15, word 7 (ADDR = 0x7F). + } B; +} hw_ocotp_crc7_t; +#endif + +/* + * constants & macros for entire OCOTP_CRC7 register + */ +#define HW_OCOTP_CRC7_ADDR (REGS_OCOTP_BASE + 0xd70) + +#ifndef __LANGUAGE_ASM__ +#define HW_OCOTP_CRC7 (*(volatile hw_ocotp_crc7_t *) HW_OCOTP_CRC7_ADDR) +#define HW_OCOTP_CRC7_RD() (HW_OCOTP_CRC7.U) +#define HW_OCOTP_CRC7_WR(v) (HW_OCOTP_CRC7.U = (v)) +#define HW_OCOTP_CRC7_SET(v) (HW_OCOTP_CRC7_WR(HW_OCOTP_CRC7_RD() | (v))) +#define HW_OCOTP_CRC7_CLR(v) (HW_OCOTP_CRC7_WR(HW_OCOTP_CRC7_RD() & ~(v))) +#define HW_OCOTP_CRC7_TOG(v) (HW_OCOTP_CRC7_WR(HW_OCOTP_CRC7_RD() ^ (v))) +#endif + +/* + * constants & macros for individual OCOTP_CRC7 bitfields + */ + +/* --- Register HW_OCOTP_CRC7, field BITS[31:0] (RW) + * + * Reflects value of OTP Bank 15, word 7 (ADDR = 0x7F). + */ + +#define BP_OCOTP_CRC7_BITS (0) //!< Bit position for OCOTP_CRC7_BITS. +#define BM_OCOTP_CRC7_BITS (0xffffffff) //!< Bit mask for OCOTP_CRC7_BITS. + +//! @brief Get value of OCOTP_CRC7_BITS from a register value. +#define BG_OCOTP_CRC7_BITS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_OCOTP_CRC7_BITS) >> BP_OCOTP_CRC7_BITS) + +//! @brief Format value for bitfield OCOTP_CRC7_BITS. +#define BF_OCOTP_CRC7_BITS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_OCOTP_CRC7_BITS) & BM_OCOTP_CRC7_BITS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BITS field to a new value. +#define BW_OCOTP_CRC7_BITS(v) (HW_OCOTP_CRC7_WR((HW_OCOTP_CRC7_RD() & ~BM_OCOTP_CRC7_BITS) | BF_OCOTP_CRC7_BITS(v))) +#endif + + +/*! + * @brief All OCOTP module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_ocotp +{ + volatile hw_ocotp_ctrl_t CTRL; //!< OTP Controller Control Register + volatile reg32_t CTRL_SET; //!< OTP Controller Control Register Set + volatile reg32_t CTRL_CLR; //!< OTP Controller Control Register Clear + volatile reg32_t CTRL_TOG; //!< OTP Controller Control Register Toggle + volatile hw_ocotp_timing_t TIMING; //!< OTP Controller Timing Register + reg32_t _reserved0[3]; + volatile hw_ocotp_data_t DATA; //!< OTP Controller Write Data Register + reg32_t _reserved1[3]; + volatile hw_ocotp_read_ctrl_t READ_CTRL; //!< OTP Controller Write Data Register + reg32_t _reserved2[3]; + volatile hw_ocotp_read_fuse_data_t READ_FUSE_DATA; //!< OTP Controller Read Data Register + reg32_t _reserved3[3]; + volatile hw_ocotp_sw_sticky_t SW_STICKY; //!< Sticky bit Register + reg32_t _reserved4[3]; + volatile hw_ocotp_scs_t SCS; //!< Software Controllable Signals Register + volatile reg32_t SCS_SET; //!< Software Controllable Signals Register Set + volatile reg32_t SCS_CLR; //!< Software Controllable Signals Register Clear + volatile reg32_t SCS_TOG; //!< Software Controllable Signals Register Toggle + volatile hw_ocotp_crc_addr_t CRC_ADDR; //!< OTP Controller CRC test address + reg32_t _reserved5[3]; + volatile hw_ocotp_crc_value_t CRC_VALUE; //!< OTP Controller CRC Value Register + reg32_t _reserved6[3]; + volatile hw_ocotp_version_t VERSION; //!< OTP Controller Version Register + reg32_t _reserved7[219]; + volatile hw_ocotp_lock_t LOCK; //!< Value of OTP Bank0 Word0 (Lock controls) + reg32_t _reserved8[3]; + volatile hw_ocotp_cfg0_t CFG0; //!< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + reg32_t _reserved9[3]; + volatile hw_ocotp_cfg1_t CFG1; //!< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + reg32_t _reserved10[3]; + volatile hw_ocotp_cfg2_t CFG2; //!< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + reg32_t _reserved11[3]; + volatile hw_ocotp_cfg3_t CFG3; //!< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + reg32_t _reserved12[3]; + volatile hw_ocotp_cfg4_t CFG4; //!< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + reg32_t _reserved13[3]; + volatile hw_ocotp_cfg5_t CFG5; //!< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + reg32_t _reserved14[3]; + volatile hw_ocotp_cfg6_t CFG6; //!< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + reg32_t _reserved15[3]; + volatile hw_ocotp_mem0_t MEM0; //!< Value of OTP Bank1 Word0 (Memory Related Info.) + reg32_t _reserved16[3]; + volatile hw_ocotp_mem1_t MEM1; //!< Value of OTP Bank1 Word1 (Memory Related Info.) + reg32_t _reserved17[3]; + volatile hw_ocotp_mem2_t MEM2; //!< Value of OTP Bank1 Word2 (Memory Related Info.) + reg32_t _reserved18[3]; + volatile hw_ocotp_mem3_t MEM3; //!< Value of OTP Bank1 Word3 (Memory Related Info.) + reg32_t _reserved19[3]; + volatile hw_ocotp_mem4_t MEM4; //!< Value of OTP Bank1 Word4 (Memory Related Info.) + reg32_t _reserved20[3]; + volatile hw_ocotp_ana0_t ANA0; //!< Value of OTP Bank1 Word5 (Memory Related Info.) + reg32_t _reserved21[3]; + volatile hw_ocotp_ana1_t ANA1; //!< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) + reg32_t _reserved22[3]; + volatile hw_ocotp_ana2_t ANA2; //!< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) + reg32_t _reserved23[3]; + volatile hw_ocotp_otpmk0_t OTPMK0; //!< Shadow Register for OTP Bank2 Word0 (OTPMK and CRYPTO Key) + reg32_t _reserved24[3]; + volatile hw_ocotp_otpmk1_t OTPMK1; //!< Shadow Register for OTP Bank2 Word1 (OTPMK and CRYPTO Key) + reg32_t _reserved25[3]; + volatile hw_ocotp_otpmk2_t OTPMK2; //!< Shadow Register for OTP Bank2 Word2 (OTPMK and CRYPTO Key) + reg32_t _reserved26[3]; + volatile hw_ocotp_otpmk3_t OTPMK3; //!< Shadow Register for OTP Bank2 Word3 (OTPMK and CRYPTO Key) + reg32_t _reserved27[3]; + volatile hw_ocotp_otpmk4_t OTPMK4; //!< Shadow Register for OTP Bank2 Word4 (OTPMK Key) + reg32_t _reserved28[3]; + volatile hw_ocotp_otpmk5_t OTPMK5; //!< Shadow Register for OTP Bank2 Word5 (OTPMK Key) + reg32_t _reserved29[3]; + volatile hw_ocotp_otpmk6_t OTPMK6; //!< Shadow Register for OTP Bank2 Word6 (OTPMK Key) + reg32_t _reserved30[3]; + volatile hw_ocotp_otpmk7_t OTPMK7; //!< Shadow Register for OTP Bank2 Word7 (OTPMK Key) + reg32_t _reserved31[3]; + volatile hw_ocotp_srk0_t SRK0; //!< Shadow Register for OTP Bank3 Word0 (SRK Hash) + reg32_t _reserved32[3]; + volatile hw_ocotp_srk1_t SRK1; //!< Shadow Register for OTP Bank3 Word1 (SRK Hash) + reg32_t _reserved33[3]; + volatile hw_ocotp_srk2_t SRK2; //!< Shadow Register for OTP Bank3 Word2 (SRK Hash) + reg32_t _reserved34[3]; + volatile hw_ocotp_srk3_t SRK3; //!< Shadow Register for OTP Bank3 Word3 (SRK Hash) + reg32_t _reserved35[3]; + volatile hw_ocotp_srk4_t SRK4; //!< Shadow Register for OTP Bank3 Word4 (SRK Hash) + reg32_t _reserved36[3]; + volatile hw_ocotp_srk5_t SRK5; //!< Shadow Register for OTP Bank3 Word5 (SRK Hash) + reg32_t _reserved37[3]; + volatile hw_ocotp_srk6_t SRK6; //!< Shadow Register for OTP Bank3 Word6 (SRK Hash) + reg32_t _reserved38[3]; + volatile hw_ocotp_srk7_t SRK7; //!< Shadow Register for OTP Bank3 Word7 (SRK Hash) + reg32_t _reserved39[3]; + volatile hw_ocotp_resp0_t RESP0; //!< Value of OTP Bank4 Word0 (Secure JTAG Response Field) + reg32_t _reserved40[3]; + volatile hw_ocotp_hsjc_resp1_t HSJC_RESP1; //!< Value of OTP Bank4 Word1 (Secure JTAG Response Field) + reg32_t _reserved41[3]; + volatile hw_ocotp_mac0_t MAC0; //!< Value of OTP Bank4 Word2 (MAC Address) + reg32_t _reserved42[3]; + volatile hw_ocotp_mac1_t MAC1; //!< Value of OTP Bank4 Word3 (MAC Address) + reg32_t _reserved43[3]; + volatile hw_ocotp_hdcp_ksv0_t HDCP_KSV0; //!< Value of OTP Bank4 Word4 (HW Capabilities) + reg32_t _reserved44[3]; + volatile hw_ocotp_hdcp_ksv1_t HDCP_KSV1; //!< Value of OTP Bank4 Word5 (HW Capabilities) + reg32_t _reserved45[3]; + volatile hw_ocotp_gp1_t GP1; //!< Value of OTP Bank4 Word6 (HW Capabilities) + reg32_t _reserved46[3]; + volatile hw_ocotp_gp2_t GP2; //!< Value of OTP Bank4 Word7 (HW Capabilities) + reg32_t _reserved47[3]; + volatile hw_ocotp_dtcp_key0_t DTCP_KEY0; //!< Value of OTP Bank5 Word0 (HW Capabilities) + reg32_t _reserved48[3]; + volatile hw_ocotp_dtcp_key1_t DTCP_KEY1; //!< Value of OTP Bank5 Word1 (HW Capabilities) + reg32_t _reserved49[3]; + volatile hw_ocotp_dtcp_key2_t DTCP_KEY2; //!< Value of OTP Bank5 Word2 (HW Capabilities) + reg32_t _reserved50[3]; + volatile hw_ocotp_dtcp_key3_t DTCP_KEY3; //!< Value of OTP Bank5 Word3 (HW Capabilities) + reg32_t _reserved51[3]; + volatile hw_ocotp_dtcp_key4_t DTCP_KEY4; //!< Value of OTP Bank5 Word4 (HW Capabilities) + reg32_t _reserved52[3]; + volatile hw_ocotp_misc_conf_t MISC_CONF; //!< Value of OTP Bank5 Word5 (HW Capabilities) + reg32_t _reserved53[3]; + volatile hw_ocotp_field_return_t FIELD_RETURN; //!< Value of OTP Bank5 Word6 (HW Capabilities) + reg32_t _reserved54[3]; + volatile hw_ocotp_srk_revoke_t SRK_REVOKE; //!< Value of OTP Bank5 Word7 (HW Capabilities) + reg32_t _reserved55[67]; + volatile hw_ocotp_hdcp_key0_t HDCP_KEY0; //!< Value of OTP Bank6 Word0 (HW Capabilities) + reg32_t _reserved56[3]; + volatile hw_ocotp_hdcp_key1_t HDCP_KEY1; //!< Value of OTP Bank6 Word1 (HW Capabilities) + reg32_t _reserved57[3]; + volatile hw_ocotp_hdcp_key2_t HDCP_KEY2; //!< Value of OTP Bank6 Word2 (HW Capabilities) + reg32_t _reserved58[3]; + volatile hw_ocotp_hdcp_key3_t HDCP_KEY3; //!< Value of OTP Bank6 Word3 (HW Capabilities) + reg32_t _reserved59[3]; + volatile hw_ocotp_hdcp_key4_t HDCP_KEY4; //!< Value of OTP Bank6 Word4 (HW Capabilities) + reg32_t _reserved60[3]; + volatile hw_ocotp_hdcp_key5_t HDCP_KEY5; //!< Value of OTP Bank6 Word5 (HW Capabilities) + reg32_t _reserved61[3]; + volatile hw_ocotp_hdcp_key6_t HDCP_KEY6; //!< Value of OTP Bank6 Word6 (HW Capabilities) + reg32_t _reserved62[3]; + volatile hw_ocotp_hdcp_key7_t HDCP_KEY7; //!< Value of OTP Bank6 Word7 (HW Capabilities) + reg32_t _reserved63[3]; + volatile hw_ocotp_hdcp_key8_t HDCP_KEY8; //!< Value of OTP Bank7 Word0 (HW Capabilities) + reg32_t _reserved64[3]; + volatile hw_ocotp_hdcp_key9_t HDCP_KEY9; //!< Value of OTP Bank7 Word1 (HW Capabilities) + reg32_t _reserved65[3]; + volatile hw_ocotp_hdcp_key10_t HDCP_KEY10; //!< Value of OTP Bank7 Word2 (HW Capabilities) + reg32_t _reserved66[3]; + volatile hw_ocotp_hdcp_key11_t HDCP_KEY11; //!< Value of OTP Bank7 Word3 (HW Capabilities) + reg32_t _reserved67[3]; + volatile hw_ocotp_hdcp_key12_t HDCP_KEY12; //!< Value of OTP Bank7 Word4 (HW Capabilities) + reg32_t _reserved68[3]; + volatile hw_ocotp_hdcp_key13_t HDCP_KEY13; //!< Value of OTP Bank7 Word5 (HW Capabilities) + reg32_t _reserved69[3]; + volatile hw_ocotp_hdcp_key14_t HDCP_KEY14; //!< Value of OTP Bank7 Word6 (HW Capabilities) + reg32_t _reserved70[3]; + volatile hw_ocotp_hdcp_key15_t HDCP_KEY15; //!< Value of OTP Bank7 Word7 (HW Capabilities) + reg32_t _reserved71[3]; + volatile hw_ocotp_hdcp_key16_t HDCP_KEY16; //!< Value of OTP Bank8 Word0 (HW Capabilities) + reg32_t _reserved72[3]; + volatile hw_ocotp_hdcp_key17_t HDCP_KEY17; //!< Value of OTP Bank8 Word1 (HW Capabilities) + reg32_t _reserved73[3]; + volatile hw_ocotp_hdcp_key18_t HDCP_KEY18; //!< Value of OTP Bank8 Word2 (HW Capabilities) + reg32_t _reserved74[3]; + volatile hw_ocotp_hdcp_key19_t HDCP_KEY19; //!< Value of OTP Bank8 Word3 (HW Capabilities) + reg32_t _reserved75[3]; + volatile hw_ocotp_hdcp_key20_t HDCP_KEY20; //!< Value of OTP Bank8 Word4 (HW Capabilities) + reg32_t _reserved76[3]; + volatile hw_ocotp_hdcp_key21_t HDCP_KEY21; //!< Value of OTP Bank8 Word5 (HW Capabilities) + reg32_t _reserved77[3]; + volatile hw_ocotp_hdcp_key22_t HDCP_KEY22; //!< Value of OTP Bank8 Word6 (HW Capabilities) + reg32_t _reserved78[3]; + volatile hw_ocotp_hdcp_key23_t HDCP_KEY23; //!< Value of OTP Bank8 Word7 (HW Capabilities) + reg32_t _reserved79[3]; + volatile hw_ocotp_hdcp_key24_t HDCP_KEY24; //!< Value of OTP Bank9 Word0 (HW Capabilities) + reg32_t _reserved80[3]; + volatile hw_ocotp_hdcp_key25_t HDCP_KEY25; //!< Value of OTP Bank9 Word1 (HW Capabilities) + reg32_t _reserved81[3]; + volatile hw_ocotp_hdcp_key26_t HDCP_KEY26; //!< Value of OTP Bank9 Word2 (HW Capabilities) + reg32_t _reserved82[3]; + volatile hw_ocotp_hdcp_key27_t HDCP_KEY27; //!< Value of OTP Bank9 Word3 (HW Capabilities) + reg32_t _reserved83[3]; + volatile hw_ocotp_hdcp_key28_t HDCP_KEY28; //!< Value of OTP Bank9 Word4 (HW Capabilities) + reg32_t _reserved84[3]; + volatile hw_ocotp_hdcp_key29_t HDCP_KEY29; //!< Value of OTP Bank9 Word5 (HW Capabilities) + reg32_t _reserved85[3]; + volatile hw_ocotp_hdcp_key30_t HDCP_KEY30; //!< Value of OTP Bank9 Word6 (HW Capabilities) + reg32_t _reserved86[3]; + volatile hw_ocotp_hdcp_key31_t HDCP_KEY31; //!< Value of OTP Bank9 Word7 (HW Capabilities) + reg32_t _reserved87[3]; + volatile hw_ocotp_hdcp_key32_t HDCP_KEY32; //!< Value of OTP Bank10 Word0 (HW Capabilities) + reg32_t _reserved88[3]; + volatile hw_ocotp_hdcp_key33_t HDCP_KEY33; //!< Value of OTP Bank10 Word1 (HW Capabilities) + reg32_t _reserved89[3]; + volatile hw_ocotp_hdcp_key34_t HDCP_KEY34; //!< Value of OTP Bank10 Word2 (HW Capabilities) + reg32_t _reserved90[3]; + volatile hw_ocotp_hdcp_key35_t HDCP_KEY35; //!< Value of OTP Bank10 Word3 (HW Capabilities) + reg32_t _reserved91[3]; + volatile hw_ocotp_hdcp_key36_t HDCP_KEY36; //!< Value of OTP Bank10 Word4 (HW Capabilities) + reg32_t _reserved92[3]; + volatile hw_ocotp_hdcp_key37_t HDCP_KEY37; //!< Value of OTP Bank10 Word5 (HW Capabilities) + reg32_t _reserved93[3]; + volatile hw_ocotp_hdcp_key38_t HDCP_KEY38; //!< Value of OTP Bank10 Word6 (HW Capabilities) + reg32_t _reserved94[3]; + volatile hw_ocotp_hdcp_key39_t HDCP_KEY39; //!< Value of OTP Bank10 Word7 (HW Capabilities) + reg32_t _reserved95[3]; + volatile hw_ocotp_hdcp_key40_t HDCP_KEY40; //!< Value of OTP Bank11 Word0 (HW Capabilities) + reg32_t _reserved96[3]; + volatile hw_ocotp_hdcp_key41_t HDCP_KEY41; //!< Value of OTP Bank11 Word1 (HW Capabilities) + reg32_t _reserved97[3]; + volatile hw_ocotp_hdcp_key42_t HDCP_KEY42; //!< Value of OTP Bank11 Word2 (HW Capabilities) + reg32_t _reserved98[3]; + volatile hw_ocotp_hdcp_key43_t HDCP_KEY43; //!< Value of OTP Bank11 Word3 (HW Capabilities) + reg32_t _reserved99[3]; + volatile hw_ocotp_hdcp_key44_t HDCP_KEY44; //!< Value of OTP Bank11 Word4 (HW Capabilities) + reg32_t _reserved100[3]; + volatile hw_ocotp_hdcp_key45_t HDCP_KEY45; //!< Value of OTP Bank11 Word5 (HW Capabilities) + reg32_t _reserved101[3]; + volatile hw_ocotp_hdcp_key46_t HDCP_KEY46; //!< Value of OTP Bank11 Word6 (HW Capabilities) + reg32_t _reserved102[3]; + volatile hw_ocotp_hdcp_key47_t HDCP_KEY47; //!< Value of OTP Bank11 Word7 (HW Capabilities) + reg32_t _reserved103[3]; + volatile hw_ocotp_hdcp_key48_t HDCP_KEY48; //!< Value of OTP Bank12 Word0 (HW Capabilities) + reg32_t _reserved104[3]; + volatile hw_ocotp_hdcp_key49_t HDCP_KEY49; //!< Value of OTP Bank12 Word1 (HW Capabilities) + reg32_t _reserved105[3]; + volatile hw_ocotp_hdcp_key50_t HDCP_KEY50; //!< Value of OTP Bank12 Word2 (HW Capabilities) + reg32_t _reserved106[3]; + volatile hw_ocotp_hdcp_key51_t HDCP_KEY51; //!< Value of OTP Bank12 Word3 (HW Capabilities) + reg32_t _reserved107[3]; + volatile hw_ocotp_hdcp_key52_t HDCP_KEY52; //!< Value of OTP Bank12 Word4 (HW Capabilities) + reg32_t _reserved108[3]; + volatile hw_ocotp_hdcp_key53_t HDCP_KEY53; //!< Value of OTP Bank12 Word5 (HW Capabilities) + reg32_t _reserved109[3]; + volatile hw_ocotp_hdcp_key54_t HDCP_KEY54; //!< Value of OTP Bank12 Word6 (HW Capabilities) + reg32_t _reserved110[3]; + volatile hw_ocotp_hdcp_key55_t HDCP_KEY55; //!< Value of OTP Bank12 Word7 (HW Capabilities) + reg32_t _reserved111[3]; + volatile hw_ocotp_hdcp_key56_t HDCP_KEY56; //!< Value of OTP Bank13 Word0 (HW Capabilities) + reg32_t _reserved112[3]; + volatile hw_ocotp_hdcp_key57_t HDCP_KEY57; //!< Value of OTP Bank13 Word1 (HW Capabilities) + reg32_t _reserved113[3]; + volatile hw_ocotp_hdcp_key58_t HDCP_KEY58; //!< Value of OTP Bank13 Word2 (HW Capabilities) + reg32_t _reserved114[3]; + volatile hw_ocotp_hdcp_key59_t HDCP_KEY59; //!< Value of OTP Bank13 Word3 (HW Capabilities) + reg32_t _reserved115[3]; + volatile hw_ocotp_hdcp_key60_t HDCP_KEY60; //!< Value of OTP Bank13 Word4 (HW Capabilities) + reg32_t _reserved116[3]; + volatile hw_ocotp_hdcp_key61_t HDCP_KEY61; //!< Value of OTP Bank13 Word5 (HW Capabilities) + reg32_t _reserved117[3]; + volatile hw_ocotp_hdcp_key62_t HDCP_KEY62; //!< Value of OTP Bank13 Word6 (HW Capabilities) + reg32_t _reserved118[3]; + volatile hw_ocotp_hdcp_key63_t HDCP_KEY63; //!< Value of OTP Bank13 Word7 (HW Capabilities) + reg32_t _reserved119[3]; + volatile hw_ocotp_hdcp_key64_t HDCP_KEY64; //!< Value of OTP Bank14 Word0 (HW Capabilities) + reg32_t _reserved120[3]; + volatile hw_ocotp_hdcp_key65_t HDCP_KEY65; //!< Value of OTP Bank14 Word1 (HW Capabilities) + reg32_t _reserved121[3]; + volatile hw_ocotp_hdcp_key66_t HDCP_KEY66; //!< Value of OTP Bank14 Word2 (HW Capabilities) + reg32_t _reserved122[3]; + volatile hw_ocotp_hdcp_key67_t HDCP_KEY67; //!< Value of OTP Bank14 Word3 (HW Capabilities) + reg32_t _reserved123[3]; + volatile hw_ocotp_hdcp_key68_t HDCP_KEY68; //!< Value of OTP Bank14 Word4 (HW Capabilities) + reg32_t _reserved124[3]; + volatile hw_ocotp_hdcp_key69_t HDCP_KEY69; //!< Value of OTP Bank14 Word5 (HW Capabilities) + reg32_t _reserved125[3]; + volatile hw_ocotp_hdcp_key70_t HDCP_KEY70; //!< Value of OTP Bank14 Word6 (HW Capabilities) + reg32_t _reserved126[3]; + volatile hw_ocotp_hdcp_key71_t HDCP_KEY71; //!< Value of OTP Bank14 Word7 (HW Capabilities) + reg32_t _reserved127[35]; + volatile hw_ocotp_crc0_t CRC0; //!< Value of OTP Bank15 Word0 (HW Capabilities) + reg32_t _reserved128[3]; + volatile hw_ocotp_crc1_t CRC1; //!< Value of OTP Bank15 Word1 (HW Capabilities) + reg32_t _reserved129[3]; + volatile hw_ocotp_crc2_t CRC2; //!< Value of OTP Bank15 Word2 (HW Capabilities) + reg32_t _reserved130[3]; + volatile hw_ocotp_crc3_t CRC3; //!< Value of OTP Bank15 Word3 (HW Capabilities) + reg32_t _reserved131[3]; + volatile hw_ocotp_crc4_t CRC4; //!< Value of OTP Bank15 Word4 (HW Capabilities) + reg32_t _reserved132[3]; + volatile hw_ocotp_crc5_t CRC5; //!< Value of OTP Bank15 Word5 (HW Capabilities) + reg32_t _reserved133[3]; + volatile hw_ocotp_crc6_t CRC6; //!< Value of OTP Bank15 Word6 (HW Capabilities) + reg32_t _reserved134[3]; + volatile hw_ocotp_crc7_t CRC7; //!< Value of OTP Bank15 Word5 (HW Capabilities) +} hw_ocotp_t; +#pragma pack() + +//! @brief Macro to access all OCOTP registers. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_OCOTP(0). +#define HW_OCOTP (*(volatile hw_ocotp_t *) REGS_OCOTP_BASE) + +#endif + + +#endif // __HW_OCOTP_REGISTERS_H__ diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regssdmaarm.h b/bsp/imx6ul/platform/include/mx6ul/registers/regssdmaarm.h new file mode 100644 index 0000000000000000000000000000000000000000..6186745f70695b94a5c2a9a03986ce3547b00e2a --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regssdmaarm.h @@ -0,0 +1,2546 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_SDMAARM_REGISTERS_H__ +#define __HW_SDMAARM_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL SDMAARM + * + * SDMA + * + * Registers defined in this header file: + * - HW_SDMAARM_MC0PTR - ARM platform Channel 0 Pointer + * - HW_SDMAARM_INTR - Channel Interrupts + * - HW_SDMAARM_STOP_STAT - Channel Stop/Channel Status + * - HW_SDMAARM_HSTART - Channel Start + * - HW_SDMAARM_EVTOVR - Channel Event Override + * - HW_SDMAARM_DSPOVR - Channel BP Override + * - HW_SDMAARM_HOSTOVR - Channel ARM platform Override + * - HW_SDMAARM_EVTPEND - Channel Event Pending + * - HW_SDMAARM_RESET - Reset Register + * - HW_SDMAARM_EVTERR - DMA Request Error Register + * - HW_SDMAARM_INTRMASK - Channel ARM platform Interrupt Mask + * - HW_SDMAARM_PSW - Schedule Status + * - HW_SDMAARM_EVTERRDBG - DMA Request Error Register + * - HW_SDMAARM_CONFIG - Configuration Register + * - HW_SDMAARM_SDMA_LOCK - SDMA LOCK + * - HW_SDMAARM_ONCE_ENB - OnCE Enable + * - HW_SDMAARM_ONCE_DATA - OnCE Data Register + * - HW_SDMAARM_ONCE_INSTR - OnCE Instruction Register + * - HW_SDMAARM_ONCE_STAT - OnCE Status Register + * - HW_SDMAARM_ONCE_CMD - OnCE Command Register + * - HW_SDMAARM_ILLINSTADDR - Illegal Instruction Trap Address + * - HW_SDMAARM_CHN0ADDR - Channel 0 Boot Address + * - HW_SDMAARM_EVT_MIRROR - DMA Requests + * - HW_SDMAARM_EVT_MIRROR2 - DMA Requests 2 + * - HW_SDMAARM_XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 + * - HW_SDMAARM_XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 + * - HW_SDMAARM_SDMA_CHNPRIn - Channel Priority Registers + * - HW_SDMAARM_CHNENBLn - Channel Enable RAM + * + * - hw_sdmaarm_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_SDMAARM_BASE +#define HW_SDMAARM_INSTANCE_COUNT (1) //!< Number of instances of the SDMAARM module. +#define REGS_SDMAARM_BASE (0x020ec000) //!< Base address for SDMAARM. +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_MC0PTR - ARM platform Channel 0 Pointer +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_MC0PTR - ARM platform Channel 0 Pointer (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_mc0ptr +{ + reg32_t U; + struct _hw_sdmaarm_mc0ptr_bitfields + { + unsigned MC0PTR : 32; //!< [31:0] Channel 0 Pointer contains the 32-bit address, in ARM platform memory, of channel 0 control block (the boot channel). + } B; +} hw_sdmaarm_mc0ptr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_MC0PTR register + */ +//@{ +#define HW_SDMAARM_MC0PTR_ADDR (REGS_SDMAARM_BASE + 0x0) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_MC0PTR (*(volatile hw_sdmaarm_mc0ptr_t *) HW_SDMAARM_MC0PTR_ADDR) +#define HW_SDMAARM_MC0PTR_RD() (HW_SDMAARM_MC0PTR.U) +#define HW_SDMAARM_MC0PTR_WR(v) (HW_SDMAARM_MC0PTR.U = (v)) +#define HW_SDMAARM_MC0PTR_SET(v) (HW_SDMAARM_MC0PTR_WR(HW_SDMAARM_MC0PTR_RD() | (v))) +#define HW_SDMAARM_MC0PTR_CLR(v) (HW_SDMAARM_MC0PTR_WR(HW_SDMAARM_MC0PTR_RD() & ~(v))) +#define HW_SDMAARM_MC0PTR_TOG(v) (HW_SDMAARM_MC0PTR_WR(HW_SDMAARM_MC0PTR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_MC0PTR bitfields + */ + +/*! @name Register SDMAARM_MC0PTR, field MC0PTR[31:0] (RW) + * + * Channel 0 Pointer contains the 32-bit address, in ARM platform memory, of channel 0 control block + * (the boot channel). Appendix A fully describes the SDMA Application Programming Interface (API). + * The ARM platform has a read/write access and the SDMA has a read-only access. + */ +//@{ +#define BP_SDMAARM_MC0PTR_MC0PTR (0) //!< Bit position for SDMAARM_MC0PTR_MC0PTR. +#define BM_SDMAARM_MC0PTR_MC0PTR (0xffffffff) //!< Bit mask for SDMAARM_MC0PTR_MC0PTR. + +//! @brief Get value of SDMAARM_MC0PTR_MC0PTR from a register value. +#define BG_SDMAARM_MC0PTR_MC0PTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_MC0PTR_MC0PTR) >> BP_SDMAARM_MC0PTR_MC0PTR) + +//! @brief Format value for bitfield SDMAARM_MC0PTR_MC0PTR. +#define BF_SDMAARM_MC0PTR_MC0PTR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_MC0PTR_MC0PTR) & BM_SDMAARM_MC0PTR_MC0PTR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MC0PTR field to a new value. +#define BW_SDMAARM_MC0PTR_MC0PTR(v) (HW_SDMAARM_MC0PTR_WR((HW_SDMAARM_MC0PTR_RD() & ~BM_SDMAARM_MC0PTR_MC0PTR) | BF_SDMAARM_MC0PTR_MC0PTR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_INTR - Channel Interrupts +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_INTR - Channel Interrupts (W1C) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_intr +{ + reg32_t U; + struct _hw_sdmaarm_intr_bitfields + { + unsigned HI : 32; //!< [31:0] The ARM platform Interrupts register contains the 32 HI[i] bits. + } B; +} hw_sdmaarm_intr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_INTR register + */ +//@{ +#define HW_SDMAARM_INTR_ADDR (REGS_SDMAARM_BASE + 0x4) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_INTR (*(volatile hw_sdmaarm_intr_t *) HW_SDMAARM_INTR_ADDR) +#define HW_SDMAARM_INTR_RD() (HW_SDMAARM_INTR.U) +#define HW_SDMAARM_INTR_WR(v) (HW_SDMAARM_INTR.U = (v)) +#define HW_SDMAARM_INTR_SET(v) (HW_SDMAARM_INTR_WR(HW_SDMAARM_INTR_RD() | (v))) +#define HW_SDMAARM_INTR_CLR(v) (HW_SDMAARM_INTR_WR(HW_SDMAARM_INTR_RD() & ~(v))) +#define HW_SDMAARM_INTR_TOG(v) (HW_SDMAARM_INTR_WR(HW_SDMAARM_INTR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_INTR bitfields + */ + +/*! @name Register SDMAARM_INTR, field HI[31:0] (W1C) + * + * The ARM platform Interrupts register contains the 32 HI[i] bits. If any bit is set, it will cause + * an interrupt to the ARM platform. This register is a "write-ones" register to the ARM platform. + * When the ARM platform sets a bit in this register the corresponding HI[i] bit is cleared. The + * interrupt service routine should clear individual channel bits when their interrupts are + * serviced, failure to do so will cause continuous interrupts. The SDMA is responsible for setting + * the HI[i] bit corresponding to the current channel when the corresponding done instruction is + * executed. + */ +//@{ +#define BP_SDMAARM_INTR_HI (0) //!< Bit position for SDMAARM_INTR_HI. +#define BM_SDMAARM_INTR_HI (0xffffffff) //!< Bit mask for SDMAARM_INTR_HI. + +//! @brief Get value of SDMAARM_INTR_HI from a register value. +#define BG_SDMAARM_INTR_HI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_INTR_HI) >> BP_SDMAARM_INTR_HI) + +//! @brief Format value for bitfield SDMAARM_INTR_HI. +#define BF_SDMAARM_INTR_HI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_INTR_HI) & BM_SDMAARM_INTR_HI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HI field to a new value. +#define BW_SDMAARM_INTR_HI(v) (HW_SDMAARM_INTR_WR((HW_SDMAARM_INTR_RD() & ~BM_SDMAARM_INTR_HI) | BF_SDMAARM_INTR_HI(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_STOP_STAT - Channel Stop/Channel Status +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_STOP_STAT - Channel Stop/Channel Status (W1C) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_stop_stat +{ + reg32_t U; + struct _hw_sdmaarm_stop_stat_bitfields + { + unsigned HE : 32; //!< [31:0] This 32-bit register gives access to the ARM platform Enable bits. + } B; +} hw_sdmaarm_stop_stat_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_STOP_STAT register + */ +//@{ +#define HW_SDMAARM_STOP_STAT_ADDR (REGS_SDMAARM_BASE + 0x8) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_STOP_STAT (*(volatile hw_sdmaarm_stop_stat_t *) HW_SDMAARM_STOP_STAT_ADDR) +#define HW_SDMAARM_STOP_STAT_RD() (HW_SDMAARM_STOP_STAT.U) +#define HW_SDMAARM_STOP_STAT_WR(v) (HW_SDMAARM_STOP_STAT.U = (v)) +#define HW_SDMAARM_STOP_STAT_SET(v) (HW_SDMAARM_STOP_STAT_WR(HW_SDMAARM_STOP_STAT_RD() | (v))) +#define HW_SDMAARM_STOP_STAT_CLR(v) (HW_SDMAARM_STOP_STAT_WR(HW_SDMAARM_STOP_STAT_RD() & ~(v))) +#define HW_SDMAARM_STOP_STAT_TOG(v) (HW_SDMAARM_STOP_STAT_WR(HW_SDMAARM_STOP_STAT_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_STOP_STAT bitfields + */ + +/*! @name Register SDMAARM_STOP_STAT, field HE[31:0] (W1C) + * + * This 32-bit register gives access to the ARM platform Enable bits. There is one bit for every + * channel. This register is a "write-ones" register to the ARM platform. When the ARM platform + * writes 1 in bit i of this register, it clears the HE[i] and HSTART[i] bits. Reading this register + * yields the current state of the HE[i] bits. + */ +//@{ +#define BP_SDMAARM_STOP_STAT_HE (0) //!< Bit position for SDMAARM_STOP_STAT_HE. +#define BM_SDMAARM_STOP_STAT_HE (0xffffffff) //!< Bit mask for SDMAARM_STOP_STAT_HE. + +//! @brief Get value of SDMAARM_STOP_STAT_HE from a register value. +#define BG_SDMAARM_STOP_STAT_HE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_STOP_STAT_HE) >> BP_SDMAARM_STOP_STAT_HE) + +//! @brief Format value for bitfield SDMAARM_STOP_STAT_HE. +#define BF_SDMAARM_STOP_STAT_HE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_STOP_STAT_HE) & BM_SDMAARM_STOP_STAT_HE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HE field to a new value. +#define BW_SDMAARM_STOP_STAT_HE(v) (HW_SDMAARM_STOP_STAT_WR((HW_SDMAARM_STOP_STAT_RD() & ~BM_SDMAARM_STOP_STAT_HE) | BF_SDMAARM_STOP_STAT_HE(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_HSTART - Channel Start +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_HSTART - Channel Start (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_hstart +{ + reg32_t U; + struct _hw_sdmaarm_hstart_bitfields + { + unsigned HSTART_HE : 32; //!< [31:0] The HSTART_HE registers are 32 bits wide with one bit for every channel. + } B; +} hw_sdmaarm_hstart_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_HSTART register + */ +//@{ +#define HW_SDMAARM_HSTART_ADDR (REGS_SDMAARM_BASE + 0xc) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_HSTART (*(volatile hw_sdmaarm_hstart_t *) HW_SDMAARM_HSTART_ADDR) +#define HW_SDMAARM_HSTART_RD() (HW_SDMAARM_HSTART.U) +#define HW_SDMAARM_HSTART_WR(v) (HW_SDMAARM_HSTART.U = (v)) +#define HW_SDMAARM_HSTART_SET(v) (HW_SDMAARM_HSTART_WR(HW_SDMAARM_HSTART_RD() | (v))) +#define HW_SDMAARM_HSTART_CLR(v) (HW_SDMAARM_HSTART_WR(HW_SDMAARM_HSTART_RD() & ~(v))) +#define HW_SDMAARM_HSTART_TOG(v) (HW_SDMAARM_HSTART_WR(HW_SDMAARM_HSTART_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_HSTART bitfields + */ + +/*! @name Register SDMAARM_HSTART, field HSTART_HE[31:0] (W1C) + * + * The HSTART_HE registers are 32 bits wide with one bit for every channel. When a bit is written to + * 1, it enables the corresponding channel. Two physical registers are accessed with that address + * (HSTART and HE), which enables the ARM platform to trigger a channel a second time before the + * first trigger is processed. This register is a "write-ones" register to the ARM platform. Neither + * HSTART[i] bit can be set while the corresponding HE[i] bit is cleared. When the ARM platform + * tries to set the HSTART[i] bit by writing a one (if the corresponding HE[i] bit is clear), the + * bit in the HSTART[i] register will remain cleared and the HE[i] bit will be set. If the + * corresponding HE[i] bit was already set, the HSTART[i] bit will be set. The next time the SDMA + * channel i attempts to clear the HE[i] bit by means of a done instruction, the bit in the + * HSTART[i] register will be cleared and the HE[i] bit will take the old value of the HSTART[i] + * bit. Reading this register yields the current state of the HSTART[i] bits. This mechanism enables + * the ARM platform to pipeline two HSTART commands per channel. + */ +//@{ +#define BP_SDMAARM_HSTART_HSTART_HE (0) //!< Bit position for SDMAARM_HSTART_HSTART_HE. +#define BM_SDMAARM_HSTART_HSTART_HE (0xffffffff) //!< Bit mask for SDMAARM_HSTART_HSTART_HE. + +//! @brief Get value of SDMAARM_HSTART_HSTART_HE from a register value. +#define BG_SDMAARM_HSTART_HSTART_HE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_HSTART_HSTART_HE) >> BP_SDMAARM_HSTART_HSTART_HE) + +//! @brief Format value for bitfield SDMAARM_HSTART_HSTART_HE. +#define BF_SDMAARM_HSTART_HSTART_HE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_HSTART_HSTART_HE) & BM_SDMAARM_HSTART_HSTART_HE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HSTART_HE field to a new value. +#define BW_SDMAARM_HSTART_HSTART_HE(v) (HW_SDMAARM_HSTART_WR((HW_SDMAARM_HSTART_RD() & ~BM_SDMAARM_HSTART_HSTART_HE) | BF_SDMAARM_HSTART_HSTART_HE(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_EVTOVR - Channel Event Override +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_EVTOVR - Channel Event Override (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_evtovr +{ + reg32_t U; + struct _hw_sdmaarm_evtovr_bitfields + { + unsigned EO : 32; //!< [31:0] The Channel Event Override register contains the 32 EO[i] bits. + } B; +} hw_sdmaarm_evtovr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_EVTOVR register + */ +//@{ +#define HW_SDMAARM_EVTOVR_ADDR (REGS_SDMAARM_BASE + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_EVTOVR (*(volatile hw_sdmaarm_evtovr_t *) HW_SDMAARM_EVTOVR_ADDR) +#define HW_SDMAARM_EVTOVR_RD() (HW_SDMAARM_EVTOVR.U) +#define HW_SDMAARM_EVTOVR_WR(v) (HW_SDMAARM_EVTOVR.U = (v)) +#define HW_SDMAARM_EVTOVR_SET(v) (HW_SDMAARM_EVTOVR_WR(HW_SDMAARM_EVTOVR_RD() | (v))) +#define HW_SDMAARM_EVTOVR_CLR(v) (HW_SDMAARM_EVTOVR_WR(HW_SDMAARM_EVTOVR_RD() & ~(v))) +#define HW_SDMAARM_EVTOVR_TOG(v) (HW_SDMAARM_EVTOVR_WR(HW_SDMAARM_EVTOVR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_EVTOVR bitfields + */ + +/*! @name Register SDMAARM_EVTOVR, field EO[31:0] (RW) + * + * The Channel Event Override register contains the 32 EO[i] bits. A bit set in this register causes + * the SDMA to ignore DMA requests when scheduling the corresponding channel. + */ +//@{ +#define BP_SDMAARM_EVTOVR_EO (0) //!< Bit position for SDMAARM_EVTOVR_EO. +#define BM_SDMAARM_EVTOVR_EO (0xffffffff) //!< Bit mask for SDMAARM_EVTOVR_EO. + +//! @brief Get value of SDMAARM_EVTOVR_EO from a register value. +#define BG_SDMAARM_EVTOVR_EO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_EVTOVR_EO) >> BP_SDMAARM_EVTOVR_EO) + +//! @brief Format value for bitfield SDMAARM_EVTOVR_EO. +#define BF_SDMAARM_EVTOVR_EO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_EVTOVR_EO) & BM_SDMAARM_EVTOVR_EO) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EO field to a new value. +#define BW_SDMAARM_EVTOVR_EO(v) (HW_SDMAARM_EVTOVR_WR((HW_SDMAARM_EVTOVR_RD() & ~BM_SDMAARM_EVTOVR_EO) | BF_SDMAARM_EVTOVR_EO(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_DSPOVR - Channel BP Override +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_DSPOVR - Channel BP Override (RW) + * + * Reset value: 0xffffffff + */ +typedef union _hw_sdmaarm_dspovr +{ + reg32_t U; + struct _hw_sdmaarm_dspovr_bitfields + { + unsigned DO : 32; //!< [31:0] This register is reserved. + } B; +} hw_sdmaarm_dspovr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_DSPOVR register + */ +//@{ +#define HW_SDMAARM_DSPOVR_ADDR (REGS_SDMAARM_BASE + 0x14) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_DSPOVR (*(volatile hw_sdmaarm_dspovr_t *) HW_SDMAARM_DSPOVR_ADDR) +#define HW_SDMAARM_DSPOVR_RD() (HW_SDMAARM_DSPOVR.U) +#define HW_SDMAARM_DSPOVR_WR(v) (HW_SDMAARM_DSPOVR.U = (v)) +#define HW_SDMAARM_DSPOVR_SET(v) (HW_SDMAARM_DSPOVR_WR(HW_SDMAARM_DSPOVR_RD() | (v))) +#define HW_SDMAARM_DSPOVR_CLR(v) (HW_SDMAARM_DSPOVR_WR(HW_SDMAARM_DSPOVR_RD() & ~(v))) +#define HW_SDMAARM_DSPOVR_TOG(v) (HW_SDMAARM_DSPOVR_WR(HW_SDMAARM_DSPOVR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_DSPOVR bitfields + */ + +/*! @name Register SDMAARM_DSPOVR, field DO[31:0] (RW) + * + * This register is reserved. All DO bits should be set to the reset value of 1. A setting of 0 will + * prevent SDMA channels from starting according to the condition described in . + * + * Values: + * - 0 - - Reserved + * - 1 - - Reset value. + */ +//@{ +#define BP_SDMAARM_DSPOVR_DO (0) //!< Bit position for SDMAARM_DSPOVR_DO. +#define BM_SDMAARM_DSPOVR_DO (0xffffffff) //!< Bit mask for SDMAARM_DSPOVR_DO. + +//! @brief Get value of SDMAARM_DSPOVR_DO from a register value. +#define BG_SDMAARM_DSPOVR_DO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_DSPOVR_DO) >> BP_SDMAARM_DSPOVR_DO) + +//! @brief Format value for bitfield SDMAARM_DSPOVR_DO. +#define BF_SDMAARM_DSPOVR_DO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_DSPOVR_DO) & BM_SDMAARM_DSPOVR_DO) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DO field to a new value. +#define BW_SDMAARM_DSPOVR_DO(v) (HW_SDMAARM_DSPOVR_WR((HW_SDMAARM_DSPOVR_RD() & ~BM_SDMAARM_DSPOVR_DO) | BF_SDMAARM_DSPOVR_DO(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_HOSTOVR - Channel ARM platform Override +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_HOSTOVR - Channel ARM platform Override (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_hostovr +{ + reg32_t U; + struct _hw_sdmaarm_hostovr_bitfields + { + unsigned HO : 32; //!< [31:0] The Channel ARM platform Override register contains the 32 HO[i] bits. + } B; +} hw_sdmaarm_hostovr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_HOSTOVR register + */ +//@{ +#define HW_SDMAARM_HOSTOVR_ADDR (REGS_SDMAARM_BASE + 0x18) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_HOSTOVR (*(volatile hw_sdmaarm_hostovr_t *) HW_SDMAARM_HOSTOVR_ADDR) +#define HW_SDMAARM_HOSTOVR_RD() (HW_SDMAARM_HOSTOVR.U) +#define HW_SDMAARM_HOSTOVR_WR(v) (HW_SDMAARM_HOSTOVR.U = (v)) +#define HW_SDMAARM_HOSTOVR_SET(v) (HW_SDMAARM_HOSTOVR_WR(HW_SDMAARM_HOSTOVR_RD() | (v))) +#define HW_SDMAARM_HOSTOVR_CLR(v) (HW_SDMAARM_HOSTOVR_WR(HW_SDMAARM_HOSTOVR_RD() & ~(v))) +#define HW_SDMAARM_HOSTOVR_TOG(v) (HW_SDMAARM_HOSTOVR_WR(HW_SDMAARM_HOSTOVR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_HOSTOVR bitfields + */ + +/*! @name Register SDMAARM_HOSTOVR, field HO[31:0] (RW) + * + * The Channel ARM platform Override register contains the 32 HO[i] bits. A bit set in this register + * causes the SDMA to ignore the ARM platform enable bit (HE) when scheduling the corresponding + * channel. + */ +//@{ +#define BP_SDMAARM_HOSTOVR_HO (0) //!< Bit position for SDMAARM_HOSTOVR_HO. +#define BM_SDMAARM_HOSTOVR_HO (0xffffffff) //!< Bit mask for SDMAARM_HOSTOVR_HO. + +//! @brief Get value of SDMAARM_HOSTOVR_HO from a register value. +#define BG_SDMAARM_HOSTOVR_HO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_HOSTOVR_HO) >> BP_SDMAARM_HOSTOVR_HO) + +//! @brief Format value for bitfield SDMAARM_HOSTOVR_HO. +#define BF_SDMAARM_HOSTOVR_HO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_HOSTOVR_HO) & BM_SDMAARM_HOSTOVR_HO) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HO field to a new value. +#define BW_SDMAARM_HOSTOVR_HO(v) (HW_SDMAARM_HOSTOVR_WR((HW_SDMAARM_HOSTOVR_RD() & ~BM_SDMAARM_HOSTOVR_HO) | BF_SDMAARM_HOSTOVR_HO(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_EVTPEND - Channel Event Pending +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_EVTPEND - Channel Event Pending (W1C) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_evtpend +{ + reg32_t U; + struct _hw_sdmaarm_evtpend_bitfields + { + unsigned EP : 32; //!< [31:0] The Channel Event Pending register contains the 32 EP[i] bits. + } B; +} hw_sdmaarm_evtpend_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_EVTPEND register + */ +//@{ +#define HW_SDMAARM_EVTPEND_ADDR (REGS_SDMAARM_BASE + 0x1c) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_EVTPEND (*(volatile hw_sdmaarm_evtpend_t *) HW_SDMAARM_EVTPEND_ADDR) +#define HW_SDMAARM_EVTPEND_RD() (HW_SDMAARM_EVTPEND.U) +#define HW_SDMAARM_EVTPEND_WR(v) (HW_SDMAARM_EVTPEND.U = (v)) +#define HW_SDMAARM_EVTPEND_SET(v) (HW_SDMAARM_EVTPEND_WR(HW_SDMAARM_EVTPEND_RD() | (v))) +#define HW_SDMAARM_EVTPEND_CLR(v) (HW_SDMAARM_EVTPEND_WR(HW_SDMAARM_EVTPEND_RD() & ~(v))) +#define HW_SDMAARM_EVTPEND_TOG(v) (HW_SDMAARM_EVTPEND_WR(HW_SDMAARM_EVTPEND_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_EVTPEND bitfields + */ + +/*! @name Register SDMAARM_EVTPEND, field EP[31:0] (W1C) + * + * The Channel Event Pending register contains the 32 EP[i] bits. Reading this register enables the + * ARM platform to determine what channels are pending after the reception of a DMA request. Setting + * a bit in this register causes the SDMA to reevaluate scheduling as if a DMA request mapped on + * this channel had occurred. This is useful for starting up channels, so that initialization is + * done before awaiting the first request. The scheduler can also set bits in the EVTPEND register + * according to the received DMA requests. The EP[i] bit may be cleared by the done instruction when + * running the channel i script. This a "write-ones" mechanism: Writing a '0' does not clear the + * corresponding bit. + */ +//@{ +#define BP_SDMAARM_EVTPEND_EP (0) //!< Bit position for SDMAARM_EVTPEND_EP. +#define BM_SDMAARM_EVTPEND_EP (0xffffffff) //!< Bit mask for SDMAARM_EVTPEND_EP. + +//! @brief Get value of SDMAARM_EVTPEND_EP from a register value. +#define BG_SDMAARM_EVTPEND_EP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_EVTPEND_EP) >> BP_SDMAARM_EVTPEND_EP) + +//! @brief Format value for bitfield SDMAARM_EVTPEND_EP. +#define BF_SDMAARM_EVTPEND_EP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_EVTPEND_EP) & BM_SDMAARM_EVTPEND_EP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EP field to a new value. +#define BW_SDMAARM_EVTPEND_EP(v) (HW_SDMAARM_EVTPEND_WR((HW_SDMAARM_EVTPEND_RD() & ~BM_SDMAARM_EVTPEND_EP) | BF_SDMAARM_EVTPEND_EP(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_RESET - Reset Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_RESET - Reset Register (RO) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_reset +{ + reg32_t U; + struct _hw_sdmaarm_reset_bitfields + { + unsigned RESET : 1; //!< [0] When set, this bit causes the SDMA to be held in a software reset. + unsigned RESCHED : 1; //!< [1] When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction. + unsigned RESERVED0 : 30; //!< [31:2] Reserved + } B; +} hw_sdmaarm_reset_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_RESET register + */ +//@{ +#define HW_SDMAARM_RESET_ADDR (REGS_SDMAARM_BASE + 0x24) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_RESET (*(volatile hw_sdmaarm_reset_t *) HW_SDMAARM_RESET_ADDR) +#define HW_SDMAARM_RESET_RD() (HW_SDMAARM_RESET.U) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_RESET bitfields + */ + +/*! @name Register SDMAARM_RESET, field RESET[0] (RO) + * + * When set, this bit causes the SDMA to be held in a software reset. The internal reset signal is + * held low 16 cycles; the RESET bit is automatically cleared when the internal reset signal rises. + */ +//@{ +#define BP_SDMAARM_RESET_RESET (0) //!< Bit position for SDMAARM_RESET_RESET. +#define BM_SDMAARM_RESET_RESET (0x00000001) //!< Bit mask for SDMAARM_RESET_RESET. + +//! @brief Get value of SDMAARM_RESET_RESET from a register value. +#define BG_SDMAARM_RESET_RESET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_RESET_RESET) >> BP_SDMAARM_RESET_RESET) +//@} + +/*! @name Register SDMAARM_RESET, field RESCHED[1] (RO) + * + * When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction. + * This enables the ARM platform to recover from a runaway script on a channel by clearing its HE[i] + * bit via the STOP register, and then forcing a reschedule via the RESCHED bit. The RESCHED bit is + * cleared when the context switch starts. + */ +//@{ +#define BP_SDMAARM_RESET_RESCHED (1) //!< Bit position for SDMAARM_RESET_RESCHED. +#define BM_SDMAARM_RESET_RESCHED (0x00000002) //!< Bit mask for SDMAARM_RESET_RESCHED. + +//! @brief Get value of SDMAARM_RESET_RESCHED from a register value. +#define BG_SDMAARM_RESET_RESCHED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_RESET_RESCHED) >> BP_SDMAARM_RESET_RESCHED) +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_EVTERR - DMA Request Error Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_EVTERR - DMA Request Error Register (RO) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_evterr +{ + reg32_t U; + struct _hw_sdmaarm_evterr_bitfields + { + unsigned CHNERR : 32; //!< [31:0] This register is used by the SDMA to warn the ARM platform when an incoming DMA request was detected and it triggers a channel that is already pending or being serviced. + } B; +} hw_sdmaarm_evterr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_EVTERR register + */ +//@{ +#define HW_SDMAARM_EVTERR_ADDR (REGS_SDMAARM_BASE + 0x28) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_EVTERR (*(volatile hw_sdmaarm_evterr_t *) HW_SDMAARM_EVTERR_ADDR) +#define HW_SDMAARM_EVTERR_RD() (HW_SDMAARM_EVTERR.U) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_EVTERR bitfields + */ + +/*! @name Register SDMAARM_EVTERR, field CHNERR[31:0] (RO) + * + * This register is used by the SDMA to warn the ARM platform when an incoming DMA request was + * detected and it triggers a channel that is already pending or being serviced. This probably means + * there is an overflow of data for that channel. An interrupt is sent to the ARM platform if the + * corresponding channel bit is set in the INTRMASK register. This is a "write-ones" register for + * the scheduler. It is only able to set the flags. The flags are cleared when the register is read + * by the ARM platform or during SDMA reset. The CHNERR[i] bit is set when a DMA request that + * triggers channel i is received through the corresponding input pins and the EP[i] bit is already + * set; the EVTERR[i] bit is unaffected if the ARM platform tries to set the EP[i] bit, whereas, + * that EP[i] bit is already set. + */ +//@{ +#define BP_SDMAARM_EVTERR_CHNERR (0) //!< Bit position for SDMAARM_EVTERR_CHNERR. +#define BM_SDMAARM_EVTERR_CHNERR (0xffffffff) //!< Bit mask for SDMAARM_EVTERR_CHNERR. + +//! @brief Get value of SDMAARM_EVTERR_CHNERR from a register value. +#define BG_SDMAARM_EVTERR_CHNERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_EVTERR_CHNERR) >> BP_SDMAARM_EVTERR_CHNERR) +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_INTRMASK - Channel ARM platform Interrupt Mask +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_INTRMASK - Channel ARM platform Interrupt Mask (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_intrmask +{ + reg32_t U; + struct _hw_sdmaarm_intrmask_bitfields + { + unsigned HIMASK : 32; //!< [31:0] The Interrupt Mask Register contains 32 interrupt generation mask bits. + } B; +} hw_sdmaarm_intrmask_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_INTRMASK register + */ +//@{ +#define HW_SDMAARM_INTRMASK_ADDR (REGS_SDMAARM_BASE + 0x2c) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_INTRMASK (*(volatile hw_sdmaarm_intrmask_t *) HW_SDMAARM_INTRMASK_ADDR) +#define HW_SDMAARM_INTRMASK_RD() (HW_SDMAARM_INTRMASK.U) +#define HW_SDMAARM_INTRMASK_WR(v) (HW_SDMAARM_INTRMASK.U = (v)) +#define HW_SDMAARM_INTRMASK_SET(v) (HW_SDMAARM_INTRMASK_WR(HW_SDMAARM_INTRMASK_RD() | (v))) +#define HW_SDMAARM_INTRMASK_CLR(v) (HW_SDMAARM_INTRMASK_WR(HW_SDMAARM_INTRMASK_RD() & ~(v))) +#define HW_SDMAARM_INTRMASK_TOG(v) (HW_SDMAARM_INTRMASK_WR(HW_SDMAARM_INTRMASK_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_INTRMASK bitfields + */ + +/*! @name Register SDMAARM_INTRMASK, field HIMASK[31:0] (RW) + * + * The Interrupt Mask Register contains 32 interrupt generation mask bits. If bit HIMASK[i] is set, + * the HI[i] bit is set and an interrupt is sent to the ARM platform when a DMA request error is + * detected on channel i (for example, EVTERR[i] is set). + */ +//@{ +#define BP_SDMAARM_INTRMASK_HIMASK (0) //!< Bit position for SDMAARM_INTRMASK_HIMASK. +#define BM_SDMAARM_INTRMASK_HIMASK (0xffffffff) //!< Bit mask for SDMAARM_INTRMASK_HIMASK. + +//! @brief Get value of SDMAARM_INTRMASK_HIMASK from a register value. +#define BG_SDMAARM_INTRMASK_HIMASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_INTRMASK_HIMASK) >> BP_SDMAARM_INTRMASK_HIMASK) + +//! @brief Format value for bitfield SDMAARM_INTRMASK_HIMASK. +#define BF_SDMAARM_INTRMASK_HIMASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_INTRMASK_HIMASK) & BM_SDMAARM_INTRMASK_HIMASK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HIMASK field to a new value. +#define BW_SDMAARM_INTRMASK_HIMASK(v) (HW_SDMAARM_INTRMASK_WR((HW_SDMAARM_INTRMASK_RD() & ~BM_SDMAARM_INTRMASK_HIMASK) | BF_SDMAARM_INTRMASK_HIMASK(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_PSW - Schedule Status +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_PSW - Schedule Status (RO) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_psw +{ + reg32_t U; + struct _hw_sdmaarm_psw_bitfields + { + unsigned CCR : 4; //!< [3:0] The Current Channel Register indicates the number of the channel that is being executed by the SDMA. + unsigned CCP : 4; //!< [7:4] The Current Channel Priority indicates the priority of the current active channel. + unsigned NCR : 5; //!< [12:8] The Next Channel Register indicates the number of the next scheduled pending channel with the highest priority. + unsigned NCP : 3; //!< [15:13] The Next Channel Priority gives the next pending channel priority. + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_sdmaarm_psw_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_PSW register + */ +//@{ +#define HW_SDMAARM_PSW_ADDR (REGS_SDMAARM_BASE + 0x30) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_PSW (*(volatile hw_sdmaarm_psw_t *) HW_SDMAARM_PSW_ADDR) +#define HW_SDMAARM_PSW_RD() (HW_SDMAARM_PSW.U) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_PSW bitfields + */ + +/*! @name Register SDMAARM_PSW, field CCR[3:0] (RO) + * + * The Current Channel Register indicates the number of the channel that is being executed by the + * SDMA. SDMA. In the case that the SDMA has finished running the channel and has entered sleep + * state, CCR will indicate the previous running channel. + */ +//@{ +#define BP_SDMAARM_PSW_CCR (0) //!< Bit position for SDMAARM_PSW_CCR. +#define BM_SDMAARM_PSW_CCR (0x0000000f) //!< Bit mask for SDMAARM_PSW_CCR. + +//! @brief Get value of SDMAARM_PSW_CCR from a register value. +#define BG_SDMAARM_PSW_CCR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_PSW_CCR) >> BP_SDMAARM_PSW_CCR) +//@} + +/*! @name Register SDMAARM_PSW, field CCP[7:4] (RO) + * + * The Current Channel Priority indicates the priority of the current active channel. When the + * priority is 0, no channel is running: The SDMA is idle and the CCR value has no meaning. In the + * case that the SDMA has finished running the channel and has entered sleep state, CCP will + * indicate the priority of previous running channel. + * + * Values: + * - 0 - No running channel + * - 1 - Active channel priority + */ +//@{ +#define BP_SDMAARM_PSW_CCP (4) //!< Bit position for SDMAARM_PSW_CCP. +#define BM_SDMAARM_PSW_CCP (0x000000f0) //!< Bit mask for SDMAARM_PSW_CCP. + +//! @brief Get value of SDMAARM_PSW_CCP from a register value. +#define BG_SDMAARM_PSW_CCP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_PSW_CCP) >> BP_SDMAARM_PSW_CCP) +//@} + +/*! @name Register SDMAARM_PSW, field NCR[12:8] (RO) + * + * The Next Channel Register indicates the number of the next scheduled pending channel with the + * highest priority. + */ +//@{ +#define BP_SDMAARM_PSW_NCR (8) //!< Bit position for SDMAARM_PSW_NCR. +#define BM_SDMAARM_PSW_NCR (0x00001f00) //!< Bit mask for SDMAARM_PSW_NCR. + +//! @brief Get value of SDMAARM_PSW_NCR from a register value. +#define BG_SDMAARM_PSW_NCR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_PSW_NCR) >> BP_SDMAARM_PSW_NCR) +//@} + +/*! @name Register SDMAARM_PSW, field NCP[15:13] (RO) + * + * The Next Channel Priority gives the next pending channel priority. When the priority is 0, it + * means there is no pending channel and the NCR value has no meaning. + * + * Values: + * - 0 - No running channel + * - 1 - Active channel priority + */ +//@{ +#define BP_SDMAARM_PSW_NCP (13) //!< Bit position for SDMAARM_PSW_NCP. +#define BM_SDMAARM_PSW_NCP (0x0000e000) //!< Bit mask for SDMAARM_PSW_NCP. + +//! @brief Get value of SDMAARM_PSW_NCP from a register value. +#define BG_SDMAARM_PSW_NCP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_PSW_NCP) >> BP_SDMAARM_PSW_NCP) +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_EVTERRDBG - DMA Request Error Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_EVTERRDBG - DMA Request Error Register (RO) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_evterrdbg +{ + reg32_t U; + struct _hw_sdmaarm_evterrdbg_bitfields + { + unsigned CHNERR : 32; //!< [31:0] This register is the same as EVTERR, except reading it does not clear its contents. + } B; +} hw_sdmaarm_evterrdbg_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_EVTERRDBG register + */ +//@{ +#define HW_SDMAARM_EVTERRDBG_ADDR (REGS_SDMAARM_BASE + 0x34) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_EVTERRDBG (*(volatile hw_sdmaarm_evterrdbg_t *) HW_SDMAARM_EVTERRDBG_ADDR) +#define HW_SDMAARM_EVTERRDBG_RD() (HW_SDMAARM_EVTERRDBG.U) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_EVTERRDBG bitfields + */ + +/*! @name Register SDMAARM_EVTERRDBG, field CHNERR[31:0] (RO) + * + * This register is the same as EVTERR, except reading it does not clear its contents. This address + * is meant to be used in debug mode. The ARM platform OnCE may check this register value without + * modifying it. + */ +//@{ +#define BP_SDMAARM_EVTERRDBG_CHNERR (0) //!< Bit position for SDMAARM_EVTERRDBG_CHNERR. +#define BM_SDMAARM_EVTERRDBG_CHNERR (0xffffffff) //!< Bit mask for SDMAARM_EVTERRDBG_CHNERR. + +//! @brief Get value of SDMAARM_EVTERRDBG_CHNERR from a register value. +#define BG_SDMAARM_EVTERRDBG_CHNERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_EVTERRDBG_CHNERR) >> BP_SDMAARM_EVTERRDBG_CHNERR) +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_CONFIG - Configuration Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_CONFIG - Configuration Register (RW) + * + * Reset value: 0x00000003 + */ +typedef union _hw_sdmaarm_config +{ + reg32_t U; + struct _hw_sdmaarm_config_bitfields + { + unsigned CSM : 2; //!< [1:0] Selects the Context Switch Mode. + unsigned RESERVED0 : 2; //!< [3:2] Reserved + unsigned ACR : 1; //!< [4] ARM platform DMA / SDMA Core Clock Ratio. + unsigned RESERVED1 : 6; //!< [10:5] Reserved + unsigned RTDOBS : 1; //!< [11] Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power consumption. + unsigned DSPDMA : 1; //!< [12] This bit's function is reserved and should be configured as zero. + unsigned RESERVED2 : 19; //!< [31:13] Reserved + } B; +} hw_sdmaarm_config_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_CONFIG register + */ +//@{ +#define HW_SDMAARM_CONFIG_ADDR (REGS_SDMAARM_BASE + 0x38) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_CONFIG (*(volatile hw_sdmaarm_config_t *) HW_SDMAARM_CONFIG_ADDR) +#define HW_SDMAARM_CONFIG_RD() (HW_SDMAARM_CONFIG.U) +#define HW_SDMAARM_CONFIG_WR(v) (HW_SDMAARM_CONFIG.U = (v)) +#define HW_SDMAARM_CONFIG_SET(v) (HW_SDMAARM_CONFIG_WR(HW_SDMAARM_CONFIG_RD() | (v))) +#define HW_SDMAARM_CONFIG_CLR(v) (HW_SDMAARM_CONFIG_WR(HW_SDMAARM_CONFIG_RD() & ~(v))) +#define HW_SDMAARM_CONFIG_TOG(v) (HW_SDMAARM_CONFIG_WR(HW_SDMAARM_CONFIG_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_CONFIG bitfields + */ + +/*! @name Register SDMAARM_CONFIG, field CSM[1:0] (RW) + * + * Selects the Context Switch Mode. The ARM platform has a read/write access. The SDMA cannot modify + * that register. The value at reset is 3, which selects the dynamic context switch by default. That + * register can be modified at anytime but the new context switch configuration will only be taken + * into account at the start of the next restore phase. NOTE: The first call to SDMA's channel 0 + * Bootload script after reset should use static context switch mode to ensure the context RAM for + * channel 0 is initialized in the channel SAVE Phase. After Channel 0 is run once, then any of the + * dynamic context modes can be used. + * + * Values: + * - 0 - static + * - 1 - dynamic low power + * - 2 - dynamic with no loop + * - 3 - dynamic + */ +//@{ +#define BP_SDMAARM_CONFIG_CSM (0) //!< Bit position for SDMAARM_CONFIG_CSM. +#define BM_SDMAARM_CONFIG_CSM (0x00000003) //!< Bit mask for SDMAARM_CONFIG_CSM. + +//! @brief Get value of SDMAARM_CONFIG_CSM from a register value. +#define BG_SDMAARM_CONFIG_CSM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_CONFIG_CSM) >> BP_SDMAARM_CONFIG_CSM) + +//! @brief Format value for bitfield SDMAARM_CONFIG_CSM. +#define BF_SDMAARM_CONFIG_CSM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_CONFIG_CSM) & BM_SDMAARM_CONFIG_CSM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CSM field to a new value. +#define BW_SDMAARM_CONFIG_CSM(v) (HW_SDMAARM_CONFIG_WR((HW_SDMAARM_CONFIG_RD() & ~BM_SDMAARM_CONFIG_CSM) | BF_SDMAARM_CONFIG_CSM(v))) +#endif +//@} + +/*! @name Register SDMAARM_CONFIG, field ACR[4] (RW) + * + * ARM platform DMA / SDMA Core Clock Ratio. Selects the clock ratio between ARM platform DMA + * interfaces (burst DMA and peripheral DMA ) and the internal SDMA core clock. The frequency + * selection is determined separately by the chip clock controller. This bit has to match the + * configuration of the chip clock controller that generates the clocks used in the SDMA. + * + * Values: + * - 0 - ARM platform DMA interface frequency equals twice core frequency + * - 1 - ARM platform DMA interface frequency equals core frequency + */ +//@{ +#define BP_SDMAARM_CONFIG_ACR (4) //!< Bit position for SDMAARM_CONFIG_ACR. +#define BM_SDMAARM_CONFIG_ACR (0x00000010) //!< Bit mask for SDMAARM_CONFIG_ACR. + +//! @brief Get value of SDMAARM_CONFIG_ACR from a register value. +#define BG_SDMAARM_CONFIG_ACR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_CONFIG_ACR) >> BP_SDMAARM_CONFIG_ACR) + +//! @brief Format value for bitfield SDMAARM_CONFIG_ACR. +#define BF_SDMAARM_CONFIG_ACR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_CONFIG_ACR) & BM_SDMAARM_CONFIG_ACR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ACR field to a new value. +#define BW_SDMAARM_CONFIG_ACR(v) (HW_SDMAARM_CONFIG_WR((HW_SDMAARM_CONFIG_RD() & ~BM_SDMAARM_CONFIG_ACR) | BF_SDMAARM_CONFIG_ACR(v))) +#endif +//@} + +/*! @name Register SDMAARM_CONFIG, field RTDOBS[11] (RW) + * + * Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce + * power consumption. + * + * Values: + * - 0 - RTD pins disabled + * - 1 - RTD pins enabled + */ +//@{ +#define BP_SDMAARM_CONFIG_RTDOBS (11) //!< Bit position for SDMAARM_CONFIG_RTDOBS. +#define BM_SDMAARM_CONFIG_RTDOBS (0x00000800) //!< Bit mask for SDMAARM_CONFIG_RTDOBS. + +//! @brief Get value of SDMAARM_CONFIG_RTDOBS from a register value. +#define BG_SDMAARM_CONFIG_RTDOBS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_CONFIG_RTDOBS) >> BP_SDMAARM_CONFIG_RTDOBS) + +//! @brief Format value for bitfield SDMAARM_CONFIG_RTDOBS. +#define BF_SDMAARM_CONFIG_RTDOBS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_CONFIG_RTDOBS) & BM_SDMAARM_CONFIG_RTDOBS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTDOBS field to a new value. +#define BW_SDMAARM_CONFIG_RTDOBS(v) (HW_SDMAARM_CONFIG_WR((HW_SDMAARM_CONFIG_RD() & ~BM_SDMAARM_CONFIG_RTDOBS) | BF_SDMAARM_CONFIG_RTDOBS(v))) +#endif +//@} + +/*! @name Register SDMAARM_CONFIG, field DSPDMA[12] (RW) + * + * This bit's function is reserved and should be configured as zero. + * + * Values: + * - 0 - - Reset Value + * - 1 - - Reserved + */ +//@{ +#define BP_SDMAARM_CONFIG_DSPDMA (12) //!< Bit position for SDMAARM_CONFIG_DSPDMA. +#define BM_SDMAARM_CONFIG_DSPDMA (0x00001000) //!< Bit mask for SDMAARM_CONFIG_DSPDMA. + +//! @brief Get value of SDMAARM_CONFIG_DSPDMA from a register value. +#define BG_SDMAARM_CONFIG_DSPDMA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_CONFIG_DSPDMA) >> BP_SDMAARM_CONFIG_DSPDMA) + +//! @brief Format value for bitfield SDMAARM_CONFIG_DSPDMA. +#define BF_SDMAARM_CONFIG_DSPDMA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_CONFIG_DSPDMA) & BM_SDMAARM_CONFIG_DSPDMA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DSPDMA field to a new value. +#define BW_SDMAARM_CONFIG_DSPDMA(v) (HW_SDMAARM_CONFIG_WR((HW_SDMAARM_CONFIG_RD() & ~BM_SDMAARM_CONFIG_DSPDMA) | BF_SDMAARM_CONFIG_DSPDMA(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_SDMA_LOCK - SDMA LOCK +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_SDMA_LOCK - SDMA LOCK (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_sdma_lock +{ + reg32_t U; + struct _hw_sdmaarm_sdma_lock_bitfields + { + unsigned LOCK : 1; //!< [0] The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts and through the OnCE interface under ARM platform control. + unsigned SRESET_LOCK_CLR : 1; //!< [1] The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing to the RESET register. + unsigned RESERVED0 : 30; //!< [31:2] Reserved + } B; +} hw_sdmaarm_sdma_lock_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_SDMA_LOCK register + */ +//@{ +#define HW_SDMAARM_SDMA_LOCK_ADDR (REGS_SDMAARM_BASE + 0x3c) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_SDMA_LOCK (*(volatile hw_sdmaarm_sdma_lock_t *) HW_SDMAARM_SDMA_LOCK_ADDR) +#define HW_SDMAARM_SDMA_LOCK_RD() (HW_SDMAARM_SDMA_LOCK.U) +#define HW_SDMAARM_SDMA_LOCK_WR(v) (HW_SDMAARM_SDMA_LOCK.U = (v)) +#define HW_SDMAARM_SDMA_LOCK_SET(v) (HW_SDMAARM_SDMA_LOCK_WR(HW_SDMAARM_SDMA_LOCK_RD() | (v))) +#define HW_SDMAARM_SDMA_LOCK_CLR(v) (HW_SDMAARM_SDMA_LOCK_WR(HW_SDMAARM_SDMA_LOCK_RD() & ~(v))) +#define HW_SDMAARM_SDMA_LOCK_TOG(v) (HW_SDMAARM_SDMA_LOCK_WR(HW_SDMAARM_SDMA_LOCK_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_SDMA_LOCK bitfields + */ + +/*! @name Register SDMAARM_SDMA_LOCK, field LOCK[0] (RW) + * + * The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero + * scripts and through the OnCE interface under ARM platform control. The LOCK bit is set: The + * SDMA_LOCK, ONCE_ENB,CH0ADDR, and ILLINSTADDR registers cannot be written. These registers can be + * read, but writes are ignored. SDMA software executing out of ROM or RAM may check the LOCK bit in + * the LOCK register to determine if certain operations are allowed, such as up-loading new scripts. + * Once the LOCK bit is set to 1, only a reset can clear it. The LOCK bit is cleared by a hardware + * reset. LOCK is cleared by a software reset only if SRESET_LOCK_CLR is set. + * + * Values: + * - 0 - LOCK disengaged. + * - 1 - LOCK enabled. + */ +//@{ +#define BP_SDMAARM_SDMA_LOCK_LOCK (0) //!< Bit position for SDMAARM_SDMA_LOCK_LOCK. +#define BM_SDMAARM_SDMA_LOCK_LOCK (0x00000001) //!< Bit mask for SDMAARM_SDMA_LOCK_LOCK. + +//! @brief Get value of SDMAARM_SDMA_LOCK_LOCK from a register value. +#define BG_SDMAARM_SDMA_LOCK_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_SDMA_LOCK_LOCK) >> BP_SDMAARM_SDMA_LOCK_LOCK) + +//! @brief Format value for bitfield SDMAARM_SDMA_LOCK_LOCK. +#define BF_SDMAARM_SDMA_LOCK_LOCK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_SDMA_LOCK_LOCK) & BM_SDMAARM_SDMA_LOCK_LOCK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LOCK field to a new value. +#define BW_SDMAARM_SDMA_LOCK_LOCK(v) (HW_SDMAARM_SDMA_LOCK_WR((HW_SDMAARM_SDMA_LOCK_RD() & ~BM_SDMAARM_SDMA_LOCK_LOCK) | BF_SDMAARM_SDMA_LOCK_LOCK(v))) +#endif +//@} + +/*! @name Register SDMAARM_SDMA_LOCK, field SRESET_LOCK_CLR[1] (RW) + * + * The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by + * writing to the RESET register. This bit cannot be changed if LOCK=1. SREST_LOCK_CLR is cleared by + * conditions that clear the LOCK bit. + * + * Values: + * - 0 - Software Reset does not clear the LOCK bit. + * - 1 - Software Reset clears the LOCK bit. + */ +//@{ +#define BP_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR (1) //!< Bit position for SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR. +#define BM_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR (0x00000002) //!< Bit mask for SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR. + +//! @brief Get value of SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR from a register value. +#define BG_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR) >> BP_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR) + +//! @brief Format value for bitfield SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR. +#define BF_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR) & BM_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SRESET_LOCK_CLR field to a new value. +#define BW_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(v) (HW_SDMAARM_SDMA_LOCK_WR((HW_SDMAARM_SDMA_LOCK_RD() & ~BM_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR) | BF_SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_ONCE_ENB - OnCE Enable +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_ONCE_ENB - OnCE Enable (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_once_enb +{ + reg32_t U; + struct _hw_sdmaarm_once_enb_bitfields + { + unsigned ENB : 1; //!< [0] The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers are accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the ARM platform through the addresses described, as follows. + unsigned RESERVED0 : 31; //!< [31:1] Reserved + } B; +} hw_sdmaarm_once_enb_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_ONCE_ENB register + */ +//@{ +#define HW_SDMAARM_ONCE_ENB_ADDR (REGS_SDMAARM_BASE + 0x40) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_ONCE_ENB (*(volatile hw_sdmaarm_once_enb_t *) HW_SDMAARM_ONCE_ENB_ADDR) +#define HW_SDMAARM_ONCE_ENB_RD() (HW_SDMAARM_ONCE_ENB.U) +#define HW_SDMAARM_ONCE_ENB_WR(v) (HW_SDMAARM_ONCE_ENB.U = (v)) +#define HW_SDMAARM_ONCE_ENB_SET(v) (HW_SDMAARM_ONCE_ENB_WR(HW_SDMAARM_ONCE_ENB_RD() | (v))) +#define HW_SDMAARM_ONCE_ENB_CLR(v) (HW_SDMAARM_ONCE_ENB_WR(HW_SDMAARM_ONCE_ENB_RD() & ~(v))) +#define HW_SDMAARM_ONCE_ENB_TOG(v) (HW_SDMAARM_ONCE_ENB_WR(HW_SDMAARM_ONCE_ENB_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_ONCE_ENB bitfields + */ + +/*! @name Register SDMAARM_ONCE_ENB, field ENB[0] (RW) + * + * The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers + * are accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the + * ARM platform through the addresses described, as follows. After reset, the OnCE registers are + * accessed through the JTAG interface. Writing a 1 to ENB enables the ARM platform to access the + * ONCE_* as any other SDMA control register. When cleared (0), all the ONCE_xxx registers cannot be + * written. The value of ENB cannot be changed if the LOCK bit in the SDMA_LOCK register is set. + */ +//@{ +#define BP_SDMAARM_ONCE_ENB_ENB (0) //!< Bit position for SDMAARM_ONCE_ENB_ENB. +#define BM_SDMAARM_ONCE_ENB_ENB (0x00000001) //!< Bit mask for SDMAARM_ONCE_ENB_ENB. + +//! @brief Get value of SDMAARM_ONCE_ENB_ENB from a register value. +#define BG_SDMAARM_ONCE_ENB_ENB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_ENB_ENB) >> BP_SDMAARM_ONCE_ENB_ENB) + +//! @brief Format value for bitfield SDMAARM_ONCE_ENB_ENB. +#define BF_SDMAARM_ONCE_ENB_ENB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_ONCE_ENB_ENB) & BM_SDMAARM_ONCE_ENB_ENB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENB field to a new value. +#define BW_SDMAARM_ONCE_ENB_ENB(v) (HW_SDMAARM_ONCE_ENB_WR((HW_SDMAARM_ONCE_ENB_RD() & ~BM_SDMAARM_ONCE_ENB_ENB) | BF_SDMAARM_ONCE_ENB_ENB(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_ONCE_DATA - OnCE Data Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_ONCE_DATA - OnCE Data Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_once_data +{ + reg32_t U; + struct _hw_sdmaarm_once_data_bitfields + { + unsigned DATA : 32; //!< [31:0] Data register of the OnCE JTAG controller. + } B; +} hw_sdmaarm_once_data_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_ONCE_DATA register + */ +//@{ +#define HW_SDMAARM_ONCE_DATA_ADDR (REGS_SDMAARM_BASE + 0x44) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_ONCE_DATA (*(volatile hw_sdmaarm_once_data_t *) HW_SDMAARM_ONCE_DATA_ADDR) +#define HW_SDMAARM_ONCE_DATA_RD() (HW_SDMAARM_ONCE_DATA.U) +#define HW_SDMAARM_ONCE_DATA_WR(v) (HW_SDMAARM_ONCE_DATA.U = (v)) +#define HW_SDMAARM_ONCE_DATA_SET(v) (HW_SDMAARM_ONCE_DATA_WR(HW_SDMAARM_ONCE_DATA_RD() | (v))) +#define HW_SDMAARM_ONCE_DATA_CLR(v) (HW_SDMAARM_ONCE_DATA_WR(HW_SDMAARM_ONCE_DATA_RD() & ~(v))) +#define HW_SDMAARM_ONCE_DATA_TOG(v) (HW_SDMAARM_ONCE_DATA_WR(HW_SDMAARM_ONCE_DATA_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_ONCE_DATA bitfields + */ + +/*! @name Register SDMAARM_ONCE_DATA, field DATA[31:0] (RW) + * + * Data register of the OnCE JTAG controller. Refer to for information on this register. + */ +//@{ +#define BP_SDMAARM_ONCE_DATA_DATA (0) //!< Bit position for SDMAARM_ONCE_DATA_DATA. +#define BM_SDMAARM_ONCE_DATA_DATA (0xffffffff) //!< Bit mask for SDMAARM_ONCE_DATA_DATA. + +//! @brief Get value of SDMAARM_ONCE_DATA_DATA from a register value. +#define BG_SDMAARM_ONCE_DATA_DATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_DATA_DATA) >> BP_SDMAARM_ONCE_DATA_DATA) + +//! @brief Format value for bitfield SDMAARM_ONCE_DATA_DATA. +#define BF_SDMAARM_ONCE_DATA_DATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_ONCE_DATA_DATA) & BM_SDMAARM_ONCE_DATA_DATA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATA field to a new value. +#define BW_SDMAARM_ONCE_DATA_DATA(v) (HW_SDMAARM_ONCE_DATA_WR((HW_SDMAARM_ONCE_DATA_RD() & ~BM_SDMAARM_ONCE_DATA_DATA) | BF_SDMAARM_ONCE_DATA_DATA(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_ONCE_INSTR - OnCE Instruction Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_ONCE_INSTR - OnCE Instruction Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_once_instr +{ + reg32_t U; + struct _hw_sdmaarm_once_instr_bitfields + { + unsigned INSTR : 16; //!< [15:0] Instruction register of the OnCE JTAG controller. + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_sdmaarm_once_instr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_ONCE_INSTR register + */ +//@{ +#define HW_SDMAARM_ONCE_INSTR_ADDR (REGS_SDMAARM_BASE + 0x48) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_ONCE_INSTR (*(volatile hw_sdmaarm_once_instr_t *) HW_SDMAARM_ONCE_INSTR_ADDR) +#define HW_SDMAARM_ONCE_INSTR_RD() (HW_SDMAARM_ONCE_INSTR.U) +#define HW_SDMAARM_ONCE_INSTR_WR(v) (HW_SDMAARM_ONCE_INSTR.U = (v)) +#define HW_SDMAARM_ONCE_INSTR_SET(v) (HW_SDMAARM_ONCE_INSTR_WR(HW_SDMAARM_ONCE_INSTR_RD() | (v))) +#define HW_SDMAARM_ONCE_INSTR_CLR(v) (HW_SDMAARM_ONCE_INSTR_WR(HW_SDMAARM_ONCE_INSTR_RD() & ~(v))) +#define HW_SDMAARM_ONCE_INSTR_TOG(v) (HW_SDMAARM_ONCE_INSTR_WR(HW_SDMAARM_ONCE_INSTR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_ONCE_INSTR bitfields + */ + +/*! @name Register SDMAARM_ONCE_INSTR, field INSTR[15:0] (RW) + * + * Instruction register of the OnCE JTAG controller. Refer to for information on this register. + */ +//@{ +#define BP_SDMAARM_ONCE_INSTR_INSTR (0) //!< Bit position for SDMAARM_ONCE_INSTR_INSTR. +#define BM_SDMAARM_ONCE_INSTR_INSTR (0x0000ffff) //!< Bit mask for SDMAARM_ONCE_INSTR_INSTR. + +//! @brief Get value of SDMAARM_ONCE_INSTR_INSTR from a register value. +#define BG_SDMAARM_ONCE_INSTR_INSTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_INSTR_INSTR) >> BP_SDMAARM_ONCE_INSTR_INSTR) + +//! @brief Format value for bitfield SDMAARM_ONCE_INSTR_INSTR. +#define BF_SDMAARM_ONCE_INSTR_INSTR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_ONCE_INSTR_INSTR) & BM_SDMAARM_ONCE_INSTR_INSTR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the INSTR field to a new value. +#define BW_SDMAARM_ONCE_INSTR_INSTR(v) (HW_SDMAARM_ONCE_INSTR_WR((HW_SDMAARM_ONCE_INSTR_RD() & ~BM_SDMAARM_ONCE_INSTR_INSTR) | BF_SDMAARM_ONCE_INSTR_INSTR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_ONCE_STAT - OnCE Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_ONCE_STAT - OnCE Status Register (RO) + * + * Reset value: 0x0000e000 + */ +typedef union _hw_sdmaarm_once_stat +{ + reg32_t U; + struct _hw_sdmaarm_once_stat_bitfields + { + unsigned ECDR : 3; //!< [2:0] Event Cell Debug Request. + unsigned RESERVED0 : 4; //!< [6:3] Reserved + unsigned MST : 1; //!< [7] This flag is raised when the OnCE is controlled from the ARM platform peripheral interface. + unsigned SWB : 1; //!< [8] This flag is raised when the SDMA has entered debug mode after a software breakpoint. + unsigned ODR : 1; //!< [9] This flag is raised when the SDMA has entered debug mode after a OnCE debug request. + unsigned EDR : 1; //!< [10] This flag is raised when the SDMA has entered debug mode after an external debug request. + unsigned RCV : 1; //!< [11] After each write access to the real time buffer (RTB), the RCV bit is set. + unsigned PST : 4; //!< [15:12] The Processor Status bits reflect the state of the SDMA RISC engine. + unsigned RESERVED1 : 16; //!< [31:16] Reserved + } B; +} hw_sdmaarm_once_stat_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_ONCE_STAT register + */ +//@{ +#define HW_SDMAARM_ONCE_STAT_ADDR (REGS_SDMAARM_BASE + 0x4c) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_ONCE_STAT (*(volatile hw_sdmaarm_once_stat_t *) HW_SDMAARM_ONCE_STAT_ADDR) +#define HW_SDMAARM_ONCE_STAT_RD() (HW_SDMAARM_ONCE_STAT.U) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_ONCE_STAT bitfields + */ + +/*! @name Register SDMAARM_ONCE_STAT, field ECDR[2:0] (RO) + * + * Event Cell Debug Request. If the debug request comes from the event cell, the reason for entering + * debug mode is given by the EDR bits. If all three bits of the EDR are reset, then it did not + * generate any debug request. If the cell did generate a debug request, then at least one of the + * EDR bits is set (the meaning of the encoding is given below). The encoding of the EDR bits is + * useful to find out more precisely why the debug request was generated. A debug request from an + * event cell is generated for a specific combination of the addra_cond, addrb_cond, and data_cond + * conditions. The value of those fields is given by the EDR bits. + * + * Values: + * - 0 - 1 matched addra_cond + * - 1 - 1 matched addrb_cond + * - 2 - 1 matched data_cond + */ +//@{ +#define BP_SDMAARM_ONCE_STAT_ECDR (0) //!< Bit position for SDMAARM_ONCE_STAT_ECDR. +#define BM_SDMAARM_ONCE_STAT_ECDR (0x00000007) //!< Bit mask for SDMAARM_ONCE_STAT_ECDR. + +//! @brief Get value of SDMAARM_ONCE_STAT_ECDR from a register value. +#define BG_SDMAARM_ONCE_STAT_ECDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_STAT_ECDR) >> BP_SDMAARM_ONCE_STAT_ECDR) +//@} + +/*! @name Register SDMAARM_ONCE_STAT, field MST[7] (RO) + * + * This flag is raised when the OnCE is controlled from the ARM platform peripheral interface. + * + * Values: + * - 0 - The JTAG interface controls the OnCE. + * - 1 - The ARM platform peripheral interface controls the OnCE. + */ +//@{ +#define BP_SDMAARM_ONCE_STAT_MST (7) //!< Bit position for SDMAARM_ONCE_STAT_MST. +#define BM_SDMAARM_ONCE_STAT_MST (0x00000080) //!< Bit mask for SDMAARM_ONCE_STAT_MST. + +//! @brief Get value of SDMAARM_ONCE_STAT_MST from a register value. +#define BG_SDMAARM_ONCE_STAT_MST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_STAT_MST) >> BP_SDMAARM_ONCE_STAT_MST) +//@} + +/*! @name Register SDMAARM_ONCE_STAT, field SWB[8] (RO) + * + * This flag is raised when the SDMA has entered debug mode after a software breakpoint. + */ +//@{ +#define BP_SDMAARM_ONCE_STAT_SWB (8) //!< Bit position for SDMAARM_ONCE_STAT_SWB. +#define BM_SDMAARM_ONCE_STAT_SWB (0x00000100) //!< Bit mask for SDMAARM_ONCE_STAT_SWB. + +//! @brief Get value of SDMAARM_ONCE_STAT_SWB from a register value. +#define BG_SDMAARM_ONCE_STAT_SWB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_STAT_SWB) >> BP_SDMAARM_ONCE_STAT_SWB) +//@} + +/*! @name Register SDMAARM_ONCE_STAT, field ODR[9] (RO) + * + * This flag is raised when the SDMA has entered debug mode after a OnCE debug request. + */ +//@{ +#define BP_SDMAARM_ONCE_STAT_ODR (9) //!< Bit position for SDMAARM_ONCE_STAT_ODR. +#define BM_SDMAARM_ONCE_STAT_ODR (0x00000200) //!< Bit mask for SDMAARM_ONCE_STAT_ODR. + +//! @brief Get value of SDMAARM_ONCE_STAT_ODR from a register value. +#define BG_SDMAARM_ONCE_STAT_ODR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_STAT_ODR) >> BP_SDMAARM_ONCE_STAT_ODR) +//@} + +/*! @name Register SDMAARM_ONCE_STAT, field EDR[10] (RO) + * + * This flag is raised when the SDMA has entered debug mode after an external debug request. + */ +//@{ +#define BP_SDMAARM_ONCE_STAT_EDR (10) //!< Bit position for SDMAARM_ONCE_STAT_EDR. +#define BM_SDMAARM_ONCE_STAT_EDR (0x00000400) //!< Bit mask for SDMAARM_ONCE_STAT_EDR. + +//! @brief Get value of SDMAARM_ONCE_STAT_EDR from a register value. +#define BG_SDMAARM_ONCE_STAT_EDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_STAT_EDR) >> BP_SDMAARM_ONCE_STAT_EDR) +//@} + +/*! @name Register SDMAARM_ONCE_STAT, field RCV[11] (RO) + * + * After each write access to the real time buffer (RTB), the RCV bit is set. This bit is cleared + * after execution of an rbuffer command and on a JTAG reset. + */ +//@{ +#define BP_SDMAARM_ONCE_STAT_RCV (11) //!< Bit position for SDMAARM_ONCE_STAT_RCV. +#define BM_SDMAARM_ONCE_STAT_RCV (0x00000800) //!< Bit mask for SDMAARM_ONCE_STAT_RCV. + +//! @brief Get value of SDMAARM_ONCE_STAT_RCV from a register value. +#define BG_SDMAARM_ONCE_STAT_RCV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_STAT_RCV) >> BP_SDMAARM_ONCE_STAT_RCV) +//@} + +/*! @name Register SDMAARM_ONCE_STAT, field PST[15:12] (RO) + * + * The Processor Status bits reflect the state of the SDMA RISC engine. Its states are as follows: + * The "Program" state is the usual instruction execution cycle. The "Data" state is inserted when + * there are wait-states during a load or a store on the data bus (ld or st). The "Change of Flow" + * state is the second cycle of any instruction that breaks the sequence of instructions (jumps and + * channel switching instructions). The "Change of Flow in Loop" state is used when an error causes + * a hardware loop exit. The "Debug" state means the SDMA is in debug mode. The "Functional Unit" + * state is inserted when there are wait-states during a load or a store on the functional units bus + * (ldf or stf). In "Sleep" modes, no script is running (this is the RISC engine idle state). The + * "after Reset" is slightly different because no context restoring phase will happen when a channel + * is triggered: The script located at address 0 will be executed (boot operation). The "in Sleep" + * states are the same as above except they do not have any corresponding channel: They are used + * when entering debug mode after reset. The reason is that it is necessary to return to the "Sleep + * after Reset" state when leaving debug mode. + * + * Values: + * - 0 - Program + * - 1 - Data + * - 2 - Change of Flow + * - 3 - Change of Flow in Loop + * - 4 - Debug + * - 5 - Functional Unit + * - 6 - Sleep + * - 7 - Save + * - 8 - Program in Sleep + * - 9 - Data in Sleep + * - 10 - Change of Flow in Sleep + * - 11 - Change Flow in Loop in Sleep + * - 12 - Debug in Sleep + * - 13 - Functional Unit in Sleep + * - 14 - Sleep after Reset + * - 15 - Restore + */ +//@{ +#define BP_SDMAARM_ONCE_STAT_PST (12) //!< Bit position for SDMAARM_ONCE_STAT_PST. +#define BM_SDMAARM_ONCE_STAT_PST (0x0000f000) //!< Bit mask for SDMAARM_ONCE_STAT_PST. + +//! @brief Get value of SDMAARM_ONCE_STAT_PST from a register value. +#define BG_SDMAARM_ONCE_STAT_PST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_STAT_PST) >> BP_SDMAARM_ONCE_STAT_PST) +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_ONCE_CMD - OnCE Command Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_ONCE_CMD - OnCE Command Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_once_cmd +{ + reg32_t U; + struct _hw_sdmaarm_once_cmd_bitfields + { + unsigned CMD : 4; //!< [3:0] Writing to this register will cause the OnCE to execute the command that is written. + unsigned RESERVED0 : 28; //!< [31:4] Reserved + } B; +} hw_sdmaarm_once_cmd_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_ONCE_CMD register + */ +//@{ +#define HW_SDMAARM_ONCE_CMD_ADDR (REGS_SDMAARM_BASE + 0x50) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_ONCE_CMD (*(volatile hw_sdmaarm_once_cmd_t *) HW_SDMAARM_ONCE_CMD_ADDR) +#define HW_SDMAARM_ONCE_CMD_RD() (HW_SDMAARM_ONCE_CMD.U) +#define HW_SDMAARM_ONCE_CMD_WR(v) (HW_SDMAARM_ONCE_CMD.U = (v)) +#define HW_SDMAARM_ONCE_CMD_SET(v) (HW_SDMAARM_ONCE_CMD_WR(HW_SDMAARM_ONCE_CMD_RD() | (v))) +#define HW_SDMAARM_ONCE_CMD_CLR(v) (HW_SDMAARM_ONCE_CMD_WR(HW_SDMAARM_ONCE_CMD_RD() & ~(v))) +#define HW_SDMAARM_ONCE_CMD_TOG(v) (HW_SDMAARM_ONCE_CMD_WR(HW_SDMAARM_ONCE_CMD_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_ONCE_CMD bitfields + */ + +/*! @name Register SDMAARM_ONCE_CMD, field CMD[3:0] (RW) + * + * Writing to this register will cause the OnCE to execute the command that is written. When needed, + * the ONCE_DATA and ONCE_INSTR registers should be loaded with the correct value before writing the + * command to that register. For a list of the OnCE commands and their usage, see . 7-15 reserved + * + * Values: + * - 0 - rstatus + * - 1 - dmov + * - 2 - exec_once + * - 3 - run_core + * - 4 - exec_core + * - 5 - debug_rqst + * - 6 - rbuffer + */ +//@{ +#define BP_SDMAARM_ONCE_CMD_CMD (0) //!< Bit position for SDMAARM_ONCE_CMD_CMD. +#define BM_SDMAARM_ONCE_CMD_CMD (0x0000000f) //!< Bit mask for SDMAARM_ONCE_CMD_CMD. + +//! @brief Get value of SDMAARM_ONCE_CMD_CMD from a register value. +#define BG_SDMAARM_ONCE_CMD_CMD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ONCE_CMD_CMD) >> BP_SDMAARM_ONCE_CMD_CMD) + +//! @brief Format value for bitfield SDMAARM_ONCE_CMD_CMD. +#define BF_SDMAARM_ONCE_CMD_CMD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_ONCE_CMD_CMD) & BM_SDMAARM_ONCE_CMD_CMD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CMD field to a new value. +#define BW_SDMAARM_ONCE_CMD_CMD(v) (HW_SDMAARM_ONCE_CMD_WR((HW_SDMAARM_ONCE_CMD_RD() & ~BM_SDMAARM_ONCE_CMD_CMD) | BF_SDMAARM_ONCE_CMD_CMD(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_ILLINSTADDR - Illegal Instruction Trap Address +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_ILLINSTADDR - Illegal Instruction Trap Address (RW) + * + * Reset value: 0x00000001 + */ +typedef union _hw_sdmaarm_illinstaddr +{ + reg32_t U; + struct _hw_sdmaarm_illinstaddr_bitfields + { + unsigned ILLINSTADDR : 14; //!< [13:0] The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is executed. + unsigned RESERVED0 : 18; //!< [31:14] Reserved + } B; +} hw_sdmaarm_illinstaddr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_ILLINSTADDR register + */ +//@{ +#define HW_SDMAARM_ILLINSTADDR_ADDR (REGS_SDMAARM_BASE + 0x58) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_ILLINSTADDR (*(volatile hw_sdmaarm_illinstaddr_t *) HW_SDMAARM_ILLINSTADDR_ADDR) +#define HW_SDMAARM_ILLINSTADDR_RD() (HW_SDMAARM_ILLINSTADDR.U) +#define HW_SDMAARM_ILLINSTADDR_WR(v) (HW_SDMAARM_ILLINSTADDR.U = (v)) +#define HW_SDMAARM_ILLINSTADDR_SET(v) (HW_SDMAARM_ILLINSTADDR_WR(HW_SDMAARM_ILLINSTADDR_RD() | (v))) +#define HW_SDMAARM_ILLINSTADDR_CLR(v) (HW_SDMAARM_ILLINSTADDR_WR(HW_SDMAARM_ILLINSTADDR_RD() & ~(v))) +#define HW_SDMAARM_ILLINSTADDR_TOG(v) (HW_SDMAARM_ILLINSTADDR_WR(HW_SDMAARM_ILLINSTADDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_ILLINSTADDR bitfields + */ + +/*! @name Register SDMAARM_ILLINSTADDR, field ILLINSTADDR[13:0] (RW) + * + * The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal + * instruction is executed. It is 0x0001 after reset. The value of ILLINSTADDR cannot be changed if + * the LOCK bit in the SDMA_LOCK register is set. + */ +//@{ +#define BP_SDMAARM_ILLINSTADDR_ILLINSTADDR (0) //!< Bit position for SDMAARM_ILLINSTADDR_ILLINSTADDR. +#define BM_SDMAARM_ILLINSTADDR_ILLINSTADDR (0x00003fff) //!< Bit mask for SDMAARM_ILLINSTADDR_ILLINSTADDR. + +//! @brief Get value of SDMAARM_ILLINSTADDR_ILLINSTADDR from a register value. +#define BG_SDMAARM_ILLINSTADDR_ILLINSTADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_ILLINSTADDR_ILLINSTADDR) >> BP_SDMAARM_ILLINSTADDR_ILLINSTADDR) + +//! @brief Format value for bitfield SDMAARM_ILLINSTADDR_ILLINSTADDR. +#define BF_SDMAARM_ILLINSTADDR_ILLINSTADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_ILLINSTADDR_ILLINSTADDR) & BM_SDMAARM_ILLINSTADDR_ILLINSTADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ILLINSTADDR field to a new value. +#define BW_SDMAARM_ILLINSTADDR_ILLINSTADDR(v) (HW_SDMAARM_ILLINSTADDR_WR((HW_SDMAARM_ILLINSTADDR_RD() & ~BM_SDMAARM_ILLINSTADDR_ILLINSTADDR) | BF_SDMAARM_ILLINSTADDR_ILLINSTADDR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_CHN0ADDR - Channel 0 Boot Address +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_CHN0ADDR - Channel 0 Boot Address (RW) + * + * Reset value: 0x00000050 + */ +typedef union _hw_sdmaarm_chn0addr +{ + reg32_t U; + struct _hw_sdmaarm_chn0addr_bitfields + { + unsigned CHN0ADDR : 14; //!< [13:0] This 14-bit register is used by the boot code of the SDMA. + unsigned SMSZ : 1; //!< [14] The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel context. + unsigned RESERVED0 : 17; //!< [31:15] Reserved + } B; +} hw_sdmaarm_chn0addr_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_CHN0ADDR register + */ +//@{ +#define HW_SDMAARM_CHN0ADDR_ADDR (REGS_SDMAARM_BASE + 0x5c) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_CHN0ADDR (*(volatile hw_sdmaarm_chn0addr_t *) HW_SDMAARM_CHN0ADDR_ADDR) +#define HW_SDMAARM_CHN0ADDR_RD() (HW_SDMAARM_CHN0ADDR.U) +#define HW_SDMAARM_CHN0ADDR_WR(v) (HW_SDMAARM_CHN0ADDR.U = (v)) +#define HW_SDMAARM_CHN0ADDR_SET(v) (HW_SDMAARM_CHN0ADDR_WR(HW_SDMAARM_CHN0ADDR_RD() | (v))) +#define HW_SDMAARM_CHN0ADDR_CLR(v) (HW_SDMAARM_CHN0ADDR_WR(HW_SDMAARM_CHN0ADDR_RD() & ~(v))) +#define HW_SDMAARM_CHN0ADDR_TOG(v) (HW_SDMAARM_CHN0ADDR_WR(HW_SDMAARM_CHN0ADDR_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_CHN0ADDR bitfields + */ + +/*! @name Register SDMAARM_CHN0ADDR, field CHN0ADDR[13:0] (RW) + * + * This 14-bit register is used by the boot code of the SDMA. After reset, it points to the standard + * boot routine in ROM (channel 0 routine). By changing this address, you can perform a boot + * sequence with your own routine. The very first instructions of the boot code fetch the contents + * of this register (it is also mapped in the SDMA memory space) and jump to the given address. The + * reset value is 0x0050 (decimal 80). The value of CHN0ADDR cannot be changed if the LOCK bit in + * the SDMA_LOCK register is set. + */ +//@{ +#define BP_SDMAARM_CHN0ADDR_CHN0ADDR (0) //!< Bit position for SDMAARM_CHN0ADDR_CHN0ADDR. +#define BM_SDMAARM_CHN0ADDR_CHN0ADDR (0x00003fff) //!< Bit mask for SDMAARM_CHN0ADDR_CHN0ADDR. + +//! @brief Get value of SDMAARM_CHN0ADDR_CHN0ADDR from a register value. +#define BG_SDMAARM_CHN0ADDR_CHN0ADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_CHN0ADDR_CHN0ADDR) >> BP_SDMAARM_CHN0ADDR_CHN0ADDR) + +//! @brief Format value for bitfield SDMAARM_CHN0ADDR_CHN0ADDR. +#define BF_SDMAARM_CHN0ADDR_CHN0ADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_CHN0ADDR_CHN0ADDR) & BM_SDMAARM_CHN0ADDR_CHN0ADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHN0ADDR field to a new value. +#define BW_SDMAARM_CHN0ADDR_CHN0ADDR(v) (HW_SDMAARM_CHN0ADDR_WR((HW_SDMAARM_CHN0ADDR_RD() & ~BM_SDMAARM_CHN0ADDR_CHN0ADDR) | BF_SDMAARM_CHN0ADDR_CHN0ADDR(v))) +#endif +//@} + +/*! @name Register SDMAARM_CHN0ADDR, field SMSZ[14] (RW) + * + * The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every + * channel context. After reset, it is equal to 0, which defines a RAM space of 24 words for each + * channel. All of this area stores the channel context. By setting this bit, 32 words are reserved + * for every channel context, which gives eight additional words that can be used by the channel + * script to store any type of data. Those words are never erased by the context switching + * mechanism. The value of SMSZ cannot be changed if the LOCK bit in the SDMA_LOCK register is set. + * + * Values: + * - 0 - 24 words per context + * - 1 - 32 words per context + */ +//@{ +#define BP_SDMAARM_CHN0ADDR_SMSZ (14) //!< Bit position for SDMAARM_CHN0ADDR_SMSZ. +#define BM_SDMAARM_CHN0ADDR_SMSZ (0x00004000) //!< Bit mask for SDMAARM_CHN0ADDR_SMSZ. + +//! @brief Get value of SDMAARM_CHN0ADDR_SMSZ from a register value. +#define BG_SDMAARM_CHN0ADDR_SMSZ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_CHN0ADDR_SMSZ) >> BP_SDMAARM_CHN0ADDR_SMSZ) + +//! @brief Format value for bitfield SDMAARM_CHN0ADDR_SMSZ. +#define BF_SDMAARM_CHN0ADDR_SMSZ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_CHN0ADDR_SMSZ) & BM_SDMAARM_CHN0ADDR_SMSZ) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SMSZ field to a new value. +#define BW_SDMAARM_CHN0ADDR_SMSZ(v) (HW_SDMAARM_CHN0ADDR_WR((HW_SDMAARM_CHN0ADDR_RD() & ~BM_SDMAARM_CHN0ADDR_SMSZ) | BF_SDMAARM_CHN0ADDR_SMSZ(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_EVT_MIRROR - DMA Requests +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_EVT_MIRROR - DMA Requests (RO) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_evt_mirror +{ + reg32_t U; + struct _hw_sdmaarm_evt_mirror_bitfields + { + unsigned EVENTS : 32; //!< [31:0] This register reflects the DMA requests received by the SDMA for events 31-0. + } B; +} hw_sdmaarm_evt_mirror_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_EVT_MIRROR register + */ +//@{ +#define HW_SDMAARM_EVT_MIRROR_ADDR (REGS_SDMAARM_BASE + 0x60) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_EVT_MIRROR (*(volatile hw_sdmaarm_evt_mirror_t *) HW_SDMAARM_EVT_MIRROR_ADDR) +#define HW_SDMAARM_EVT_MIRROR_RD() (HW_SDMAARM_EVT_MIRROR.U) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_EVT_MIRROR bitfields + */ + +/*! @name Register SDMAARM_EVT_MIRROR, field EVENTS[31:0] (RO) + * + * This register reflects the DMA requests received by the SDMA for events 31-0. The ARM platform + * and the SDMA have a read-only access. There is one bit associated with each of 32 DMA request + * events. This information may be useful during debug of the blocks that generate the DMA requests. + * The EVT_MIRROR register is cleared following read access. + * + * Values: + * - 0 - DMA request event not pending + * - 1 - DMA request event pending + */ +//@{ +#define BP_SDMAARM_EVT_MIRROR_EVENTS (0) //!< Bit position for SDMAARM_EVT_MIRROR_EVENTS. +#define BM_SDMAARM_EVT_MIRROR_EVENTS (0xffffffff) //!< Bit mask for SDMAARM_EVT_MIRROR_EVENTS. + +//! @brief Get value of SDMAARM_EVT_MIRROR_EVENTS from a register value. +#define BG_SDMAARM_EVT_MIRROR_EVENTS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_EVT_MIRROR_EVENTS) >> BP_SDMAARM_EVT_MIRROR_EVENTS) +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_EVT_MIRROR2 - DMA Requests 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_EVT_MIRROR2 - DMA Requests 2 (RO) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_evt_mirror2 +{ + reg32_t U; + struct _hw_sdmaarm_evt_mirror2_bitfields + { + unsigned EVENTS : 16; //!< [15:0] This register reflects the DMA requests received by the SDMA for events 47-32. + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_sdmaarm_evt_mirror2_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_EVT_MIRROR2 register + */ +//@{ +#define HW_SDMAARM_EVT_MIRROR2_ADDR (REGS_SDMAARM_BASE + 0x64) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_EVT_MIRROR2 (*(volatile hw_sdmaarm_evt_mirror2_t *) HW_SDMAARM_EVT_MIRROR2_ADDR) +#define HW_SDMAARM_EVT_MIRROR2_RD() (HW_SDMAARM_EVT_MIRROR2.U) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_EVT_MIRROR2 bitfields + */ + +/*! @name Register SDMAARM_EVT_MIRROR2, field EVENTS[15:0] (RO) + * + * This register reflects the DMA requests received by the SDMA for events 47-32. The ARM platform + * and the SDMA have a read-only access. There is one bit associated with each of DMA request + * events. This information may be useful during debug of the blocks that generate the DMA requests. + * The EVT_MIRROR2 register is cleared following read access. + * + * Values: + * - 0 - - DMA request event not pending + * - 1- - DMA request event pending + */ +//@{ +#define BP_SDMAARM_EVT_MIRROR2_EVENTS (0) //!< Bit position for SDMAARM_EVT_MIRROR2_EVENTS. +#define BM_SDMAARM_EVT_MIRROR2_EVENTS (0x0000ffff) //!< Bit mask for SDMAARM_EVT_MIRROR2_EVENTS. + +//! @brief Get value of SDMAARM_EVT_MIRROR2_EVENTS from a register value. +#define BG_SDMAARM_EVT_MIRROR2_EVENTS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_EVT_MIRROR2_EVENTS) >> BP_SDMAARM_EVT_MIRROR2_EVENTS) +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_xtrig_conf1 +{ + reg32_t U; + struct _hw_sdmaarm_xtrig_conf1_bitfields + { + unsigned NUM0 : 6; //!< [5:0] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i . + unsigned CNF0 : 1; //!< [6] Configuration of the SDMA event line number i that is connected to the cross-trigger. + unsigned RESERVED0 : 1; //!< [7] Reserved + unsigned NUM1 : 6; //!< [13:8] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i . + unsigned CNF1 : 1; //!< [14] Configuration of the SDMA event line number i that is connected to the cross-trigger. + unsigned RESERVED1 : 1; //!< [15] Reserved + unsigned NUM2 : 6; //!< [21:16] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i . + unsigned CNF2 : 1; //!< [22] Configuration of the SDMA event line number i that is connected to the cross-trigger. + unsigned RESERVED2 : 1; //!< [23] Reserved + unsigned NUM3 : 6; //!< [29:24] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i . + unsigned CNF3 : 1; //!< [30] Configuration of the SDMA event line number i that is connected to the cross-trigger. + unsigned RESERVED3 : 1; //!< [31] Reserved + } B; +} hw_sdmaarm_xtrig_conf1_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_XTRIG_CONF1 register + */ +//@{ +#define HW_SDMAARM_XTRIG_CONF1_ADDR (REGS_SDMAARM_BASE + 0x70) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_XTRIG_CONF1 (*(volatile hw_sdmaarm_xtrig_conf1_t *) HW_SDMAARM_XTRIG_CONF1_ADDR) +#define HW_SDMAARM_XTRIG_CONF1_RD() (HW_SDMAARM_XTRIG_CONF1.U) +#define HW_SDMAARM_XTRIG_CONF1_WR(v) (HW_SDMAARM_XTRIG_CONF1.U = (v)) +#define HW_SDMAARM_XTRIG_CONF1_SET(v) (HW_SDMAARM_XTRIG_CONF1_WR(HW_SDMAARM_XTRIG_CONF1_RD() | (v))) +#define HW_SDMAARM_XTRIG_CONF1_CLR(v) (HW_SDMAARM_XTRIG_CONF1_WR(HW_SDMAARM_XTRIG_CONF1_RD() & ~(v))) +#define HW_SDMAARM_XTRIG_CONF1_TOG(v) (HW_SDMAARM_XTRIG_CONF1_WR(HW_SDMAARM_XTRIG_CONF1_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_XTRIG_CONF1 bitfields + */ + +/*! @name Register SDMAARM_XTRIG_CONF1, field NUM0[5:0] (RW) + * + * Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger + * event line number i . + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF1_NUM0 (0) //!< Bit position for SDMAARM_XTRIG_CONF1_NUM0. +#define BM_SDMAARM_XTRIG_CONF1_NUM0 (0x0000003f) //!< Bit mask for SDMAARM_XTRIG_CONF1_NUM0. + +//! @brief Get value of SDMAARM_XTRIG_CONF1_NUM0 from a register value. +#define BG_SDMAARM_XTRIG_CONF1_NUM0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF1_NUM0) >> BP_SDMAARM_XTRIG_CONF1_NUM0) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF1_NUM0. +#define BF_SDMAARM_XTRIG_CONF1_NUM0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF1_NUM0) & BM_SDMAARM_XTRIG_CONF1_NUM0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NUM0 field to a new value. +#define BW_SDMAARM_XTRIG_CONF1_NUM0(v) (HW_SDMAARM_XTRIG_CONF1_WR((HW_SDMAARM_XTRIG_CONF1_RD() & ~BM_SDMAARM_XTRIG_CONF1_NUM0) | BF_SDMAARM_XTRIG_CONF1_NUM0(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF1, field CNF0[6] (RW) + * + * Configuration of the SDMA event line number i that is connected to the cross-trigger. It + * determines whether the event line pulse is generated by receiving a DMA request or by starting a + * channel script execution. + * + * Values: + * - 0 - channel + * - 1 - DMA request + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF1_CNF0 (6) //!< Bit position for SDMAARM_XTRIG_CONF1_CNF0. +#define BM_SDMAARM_XTRIG_CONF1_CNF0 (0x00000040) //!< Bit mask for SDMAARM_XTRIG_CONF1_CNF0. + +//! @brief Get value of SDMAARM_XTRIG_CONF1_CNF0 from a register value. +#define BG_SDMAARM_XTRIG_CONF1_CNF0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF1_CNF0) >> BP_SDMAARM_XTRIG_CONF1_CNF0) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF1_CNF0. +#define BF_SDMAARM_XTRIG_CONF1_CNF0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF1_CNF0) & BM_SDMAARM_XTRIG_CONF1_CNF0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CNF0 field to a new value. +#define BW_SDMAARM_XTRIG_CONF1_CNF0(v) (HW_SDMAARM_XTRIG_CONF1_WR((HW_SDMAARM_XTRIG_CONF1_RD() & ~BM_SDMAARM_XTRIG_CONF1_CNF0) | BF_SDMAARM_XTRIG_CONF1_CNF0(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF1, field NUM1[13:8] (RW) + * + * Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger + * event line number i . + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF1_NUM1 (8) //!< Bit position for SDMAARM_XTRIG_CONF1_NUM1. +#define BM_SDMAARM_XTRIG_CONF1_NUM1 (0x00003f00) //!< Bit mask for SDMAARM_XTRIG_CONF1_NUM1. + +//! @brief Get value of SDMAARM_XTRIG_CONF1_NUM1 from a register value. +#define BG_SDMAARM_XTRIG_CONF1_NUM1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF1_NUM1) >> BP_SDMAARM_XTRIG_CONF1_NUM1) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF1_NUM1. +#define BF_SDMAARM_XTRIG_CONF1_NUM1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF1_NUM1) & BM_SDMAARM_XTRIG_CONF1_NUM1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NUM1 field to a new value. +#define BW_SDMAARM_XTRIG_CONF1_NUM1(v) (HW_SDMAARM_XTRIG_CONF1_WR((HW_SDMAARM_XTRIG_CONF1_RD() & ~BM_SDMAARM_XTRIG_CONF1_NUM1) | BF_SDMAARM_XTRIG_CONF1_NUM1(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF1, field CNF1[14] (RW) + * + * Configuration of the SDMA event line number i that is connected to the cross-trigger. It + * determines whether the event line pulse is generated by receiving a DMA request or by starting a + * channel script execution. + * + * Values: + * - 0 - channel + * - 1 - DMA request + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF1_CNF1 (14) //!< Bit position for SDMAARM_XTRIG_CONF1_CNF1. +#define BM_SDMAARM_XTRIG_CONF1_CNF1 (0x00004000) //!< Bit mask for SDMAARM_XTRIG_CONF1_CNF1. + +//! @brief Get value of SDMAARM_XTRIG_CONF1_CNF1 from a register value. +#define BG_SDMAARM_XTRIG_CONF1_CNF1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF1_CNF1) >> BP_SDMAARM_XTRIG_CONF1_CNF1) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF1_CNF1. +#define BF_SDMAARM_XTRIG_CONF1_CNF1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF1_CNF1) & BM_SDMAARM_XTRIG_CONF1_CNF1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CNF1 field to a new value. +#define BW_SDMAARM_XTRIG_CONF1_CNF1(v) (HW_SDMAARM_XTRIG_CONF1_WR((HW_SDMAARM_XTRIG_CONF1_RD() & ~BM_SDMAARM_XTRIG_CONF1_CNF1) | BF_SDMAARM_XTRIG_CONF1_CNF1(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF1, field NUM2[21:16] (RW) + * + * Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger + * event line number i . + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF1_NUM2 (16) //!< Bit position for SDMAARM_XTRIG_CONF1_NUM2. +#define BM_SDMAARM_XTRIG_CONF1_NUM2 (0x003f0000) //!< Bit mask for SDMAARM_XTRIG_CONF1_NUM2. + +//! @brief Get value of SDMAARM_XTRIG_CONF1_NUM2 from a register value. +#define BG_SDMAARM_XTRIG_CONF1_NUM2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF1_NUM2) >> BP_SDMAARM_XTRIG_CONF1_NUM2) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF1_NUM2. +#define BF_SDMAARM_XTRIG_CONF1_NUM2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF1_NUM2) & BM_SDMAARM_XTRIG_CONF1_NUM2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NUM2 field to a new value. +#define BW_SDMAARM_XTRIG_CONF1_NUM2(v) (HW_SDMAARM_XTRIG_CONF1_WR((HW_SDMAARM_XTRIG_CONF1_RD() & ~BM_SDMAARM_XTRIG_CONF1_NUM2) | BF_SDMAARM_XTRIG_CONF1_NUM2(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF1, field CNF2[22] (RW) + * + * Configuration of the SDMA event line number i that is connected to the cross-trigger. It + * determines whether the event line pulse is generated by receiving a DMA request or by starting a + * channel script execution. + * + * Values: + * - 0 - channel + * - 1 - DMA request + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF1_CNF2 (22) //!< Bit position for SDMAARM_XTRIG_CONF1_CNF2. +#define BM_SDMAARM_XTRIG_CONF1_CNF2 (0x00400000) //!< Bit mask for SDMAARM_XTRIG_CONF1_CNF2. + +//! @brief Get value of SDMAARM_XTRIG_CONF1_CNF2 from a register value. +#define BG_SDMAARM_XTRIG_CONF1_CNF2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF1_CNF2) >> BP_SDMAARM_XTRIG_CONF1_CNF2) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF1_CNF2. +#define BF_SDMAARM_XTRIG_CONF1_CNF2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF1_CNF2) & BM_SDMAARM_XTRIG_CONF1_CNF2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CNF2 field to a new value. +#define BW_SDMAARM_XTRIG_CONF1_CNF2(v) (HW_SDMAARM_XTRIG_CONF1_WR((HW_SDMAARM_XTRIG_CONF1_RD() & ~BM_SDMAARM_XTRIG_CONF1_CNF2) | BF_SDMAARM_XTRIG_CONF1_CNF2(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF1, field NUM3[29:24] (RW) + * + * Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger + * event line number i . + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF1_NUM3 (24) //!< Bit position for SDMAARM_XTRIG_CONF1_NUM3. +#define BM_SDMAARM_XTRIG_CONF1_NUM3 (0x3f000000) //!< Bit mask for SDMAARM_XTRIG_CONF1_NUM3. + +//! @brief Get value of SDMAARM_XTRIG_CONF1_NUM3 from a register value. +#define BG_SDMAARM_XTRIG_CONF1_NUM3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF1_NUM3) >> BP_SDMAARM_XTRIG_CONF1_NUM3) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF1_NUM3. +#define BF_SDMAARM_XTRIG_CONF1_NUM3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF1_NUM3) & BM_SDMAARM_XTRIG_CONF1_NUM3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NUM3 field to a new value. +#define BW_SDMAARM_XTRIG_CONF1_NUM3(v) (HW_SDMAARM_XTRIG_CONF1_WR((HW_SDMAARM_XTRIG_CONF1_RD() & ~BM_SDMAARM_XTRIG_CONF1_NUM3) | BF_SDMAARM_XTRIG_CONF1_NUM3(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF1, field CNF3[30] (RW) + * + * Configuration of the SDMA event line number i that is connected to the cross-trigger. It + * determines whether the event line pulse is generated by the reception of a DMA request or by the + * starting of a channel script execution. + * + * Values: + * - 0 - channel + * - 1 - DMA request + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF1_CNF3 (30) //!< Bit position for SDMAARM_XTRIG_CONF1_CNF3. +#define BM_SDMAARM_XTRIG_CONF1_CNF3 (0x40000000) //!< Bit mask for SDMAARM_XTRIG_CONF1_CNF3. + +//! @brief Get value of SDMAARM_XTRIG_CONF1_CNF3 from a register value. +#define BG_SDMAARM_XTRIG_CONF1_CNF3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF1_CNF3) >> BP_SDMAARM_XTRIG_CONF1_CNF3) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF1_CNF3. +#define BF_SDMAARM_XTRIG_CONF1_CNF3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF1_CNF3) & BM_SDMAARM_XTRIG_CONF1_CNF3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CNF3 field to a new value. +#define BW_SDMAARM_XTRIG_CONF1_CNF3(v) (HW_SDMAARM_XTRIG_CONF1_WR((HW_SDMAARM_XTRIG_CONF1_RD() & ~BM_SDMAARM_XTRIG_CONF1_CNF3) | BF_SDMAARM_XTRIG_CONF1_CNF3(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_xtrig_conf2 +{ + reg32_t U; + struct _hw_sdmaarm_xtrig_conf2_bitfields + { + unsigned NUM4 : 6; //!< [5:0] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i . + unsigned CNF4 : 1; //!< [6] Configuration of the SDMA event line number i that is connected to the cross-trigger. + unsigned RESERVED0 : 1; //!< [7] Reserved + unsigned NUM5 : 6; //!< [13:8] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i . + unsigned CNF5 : 1; //!< [14] Configuration of the SDMA event line number i that is connected to the cross-trigger. + unsigned RESERVED1 : 1; //!< [15] Reserved + unsigned NUM6 : 6; //!< [21:16] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i . + unsigned CNF6 : 1; //!< [22] Configuration of the SDMA event line number i that is connected to the cross-trigger. + unsigned RESERVED2 : 1; //!< [23] Reserved + unsigned NUM7 : 6; //!< [29:24] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i . + unsigned CNF7 : 1; //!< [30] Configuration of the SDMA event line number i that is connected to the cross-trigger. + unsigned RESERVED3 : 1; //!< [31] Reserved + } B; +} hw_sdmaarm_xtrig_conf2_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_XTRIG_CONF2 register + */ +//@{ +#define HW_SDMAARM_XTRIG_CONF2_ADDR (REGS_SDMAARM_BASE + 0x74) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_XTRIG_CONF2 (*(volatile hw_sdmaarm_xtrig_conf2_t *) HW_SDMAARM_XTRIG_CONF2_ADDR) +#define HW_SDMAARM_XTRIG_CONF2_RD() (HW_SDMAARM_XTRIG_CONF2.U) +#define HW_SDMAARM_XTRIG_CONF2_WR(v) (HW_SDMAARM_XTRIG_CONF2.U = (v)) +#define HW_SDMAARM_XTRIG_CONF2_SET(v) (HW_SDMAARM_XTRIG_CONF2_WR(HW_SDMAARM_XTRIG_CONF2_RD() | (v))) +#define HW_SDMAARM_XTRIG_CONF2_CLR(v) (HW_SDMAARM_XTRIG_CONF2_WR(HW_SDMAARM_XTRIG_CONF2_RD() & ~(v))) +#define HW_SDMAARM_XTRIG_CONF2_TOG(v) (HW_SDMAARM_XTRIG_CONF2_WR(HW_SDMAARM_XTRIG_CONF2_RD() ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_XTRIG_CONF2 bitfields + */ + +/*! @name Register SDMAARM_XTRIG_CONF2, field NUM4[5:0] (RW) + * + * Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger + * event line number i . + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF2_NUM4 (0) //!< Bit position for SDMAARM_XTRIG_CONF2_NUM4. +#define BM_SDMAARM_XTRIG_CONF2_NUM4 (0x0000003f) //!< Bit mask for SDMAARM_XTRIG_CONF2_NUM4. + +//! @brief Get value of SDMAARM_XTRIG_CONF2_NUM4 from a register value. +#define BG_SDMAARM_XTRIG_CONF2_NUM4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF2_NUM4) >> BP_SDMAARM_XTRIG_CONF2_NUM4) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF2_NUM4. +#define BF_SDMAARM_XTRIG_CONF2_NUM4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF2_NUM4) & BM_SDMAARM_XTRIG_CONF2_NUM4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NUM4 field to a new value. +#define BW_SDMAARM_XTRIG_CONF2_NUM4(v) (HW_SDMAARM_XTRIG_CONF2_WR((HW_SDMAARM_XTRIG_CONF2_RD() & ~BM_SDMAARM_XTRIG_CONF2_NUM4) | BF_SDMAARM_XTRIG_CONF2_NUM4(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF2, field CNF4[6] (RW) + * + * Configuration of the SDMA event line number i that is connected to the cross-trigger. It + * determines whether the event line pulse is generated by receiving a DMA request or by starting a + * channel script execution. + * + * Values: + * - 0 - channel + * - 1 - DMA request + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF2_CNF4 (6) //!< Bit position for SDMAARM_XTRIG_CONF2_CNF4. +#define BM_SDMAARM_XTRIG_CONF2_CNF4 (0x00000040) //!< Bit mask for SDMAARM_XTRIG_CONF2_CNF4. + +//! @brief Get value of SDMAARM_XTRIG_CONF2_CNF4 from a register value. +#define BG_SDMAARM_XTRIG_CONF2_CNF4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF2_CNF4) >> BP_SDMAARM_XTRIG_CONF2_CNF4) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF2_CNF4. +#define BF_SDMAARM_XTRIG_CONF2_CNF4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF2_CNF4) & BM_SDMAARM_XTRIG_CONF2_CNF4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CNF4 field to a new value. +#define BW_SDMAARM_XTRIG_CONF2_CNF4(v) (HW_SDMAARM_XTRIG_CONF2_WR((HW_SDMAARM_XTRIG_CONF2_RD() & ~BM_SDMAARM_XTRIG_CONF2_CNF4) | BF_SDMAARM_XTRIG_CONF2_CNF4(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF2, field NUM5[13:8] (RW) + * + * Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger + * event line number i . + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF2_NUM5 (8) //!< Bit position for SDMAARM_XTRIG_CONF2_NUM5. +#define BM_SDMAARM_XTRIG_CONF2_NUM5 (0x00003f00) //!< Bit mask for SDMAARM_XTRIG_CONF2_NUM5. + +//! @brief Get value of SDMAARM_XTRIG_CONF2_NUM5 from a register value. +#define BG_SDMAARM_XTRIG_CONF2_NUM5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF2_NUM5) >> BP_SDMAARM_XTRIG_CONF2_NUM5) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF2_NUM5. +#define BF_SDMAARM_XTRIG_CONF2_NUM5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF2_NUM5) & BM_SDMAARM_XTRIG_CONF2_NUM5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NUM5 field to a new value. +#define BW_SDMAARM_XTRIG_CONF2_NUM5(v) (HW_SDMAARM_XTRIG_CONF2_WR((HW_SDMAARM_XTRIG_CONF2_RD() & ~BM_SDMAARM_XTRIG_CONF2_NUM5) | BF_SDMAARM_XTRIG_CONF2_NUM5(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF2, field CNF5[14] (RW) + * + * Configuration of the SDMA event line number i that is connected to the cross-trigger. It + * determines whether the event line pulse is generated by receiving a DMA request or by starting a + * channel script execution + * + * Values: + * - 0 - channel + * - 1 - DMA request + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF2_CNF5 (14) //!< Bit position for SDMAARM_XTRIG_CONF2_CNF5. +#define BM_SDMAARM_XTRIG_CONF2_CNF5 (0x00004000) //!< Bit mask for SDMAARM_XTRIG_CONF2_CNF5. + +//! @brief Get value of SDMAARM_XTRIG_CONF2_CNF5 from a register value. +#define BG_SDMAARM_XTRIG_CONF2_CNF5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF2_CNF5) >> BP_SDMAARM_XTRIG_CONF2_CNF5) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF2_CNF5. +#define BF_SDMAARM_XTRIG_CONF2_CNF5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF2_CNF5) & BM_SDMAARM_XTRIG_CONF2_CNF5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CNF5 field to a new value. +#define BW_SDMAARM_XTRIG_CONF2_CNF5(v) (HW_SDMAARM_XTRIG_CONF2_WR((HW_SDMAARM_XTRIG_CONF2_RD() & ~BM_SDMAARM_XTRIG_CONF2_CNF5) | BF_SDMAARM_XTRIG_CONF2_CNF5(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF2, field NUM6[21:16] (RW) + * + * Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger + * event line number i . + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF2_NUM6 (16) //!< Bit position for SDMAARM_XTRIG_CONF2_NUM6. +#define BM_SDMAARM_XTRIG_CONF2_NUM6 (0x003f0000) //!< Bit mask for SDMAARM_XTRIG_CONF2_NUM6. + +//! @brief Get value of SDMAARM_XTRIG_CONF2_NUM6 from a register value. +#define BG_SDMAARM_XTRIG_CONF2_NUM6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF2_NUM6) >> BP_SDMAARM_XTRIG_CONF2_NUM6) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF2_NUM6. +#define BF_SDMAARM_XTRIG_CONF2_NUM6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF2_NUM6) & BM_SDMAARM_XTRIG_CONF2_NUM6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NUM6 field to a new value. +#define BW_SDMAARM_XTRIG_CONF2_NUM6(v) (HW_SDMAARM_XTRIG_CONF2_WR((HW_SDMAARM_XTRIG_CONF2_RD() & ~BM_SDMAARM_XTRIG_CONF2_NUM6) | BF_SDMAARM_XTRIG_CONF2_NUM6(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF2, field CNF6[22] (RW) + * + * Configuration of the SDMA event line number i that is connected to the cross-trigger. It + * determines whether the event line pulse is generated by receiving a DMA request or by starting a + * channel script execution. + * + * Values: + * - 0 - channel + * - 1 - DMA request + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF2_CNF6 (22) //!< Bit position for SDMAARM_XTRIG_CONF2_CNF6. +#define BM_SDMAARM_XTRIG_CONF2_CNF6 (0x00400000) //!< Bit mask for SDMAARM_XTRIG_CONF2_CNF6. + +//! @brief Get value of SDMAARM_XTRIG_CONF2_CNF6 from a register value. +#define BG_SDMAARM_XTRIG_CONF2_CNF6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF2_CNF6) >> BP_SDMAARM_XTRIG_CONF2_CNF6) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF2_CNF6. +#define BF_SDMAARM_XTRIG_CONF2_CNF6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF2_CNF6) & BM_SDMAARM_XTRIG_CONF2_CNF6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CNF6 field to a new value. +#define BW_SDMAARM_XTRIG_CONF2_CNF6(v) (HW_SDMAARM_XTRIG_CONF2_WR((HW_SDMAARM_XTRIG_CONF2_RD() & ~BM_SDMAARM_XTRIG_CONF2_CNF6) | BF_SDMAARM_XTRIG_CONF2_CNF6(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF2, field NUM7[29:24] (RW) + * + * Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger + * event line number i . + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF2_NUM7 (24) //!< Bit position for SDMAARM_XTRIG_CONF2_NUM7. +#define BM_SDMAARM_XTRIG_CONF2_NUM7 (0x3f000000) //!< Bit mask for SDMAARM_XTRIG_CONF2_NUM7. + +//! @brief Get value of SDMAARM_XTRIG_CONF2_NUM7 from a register value. +#define BG_SDMAARM_XTRIG_CONF2_NUM7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF2_NUM7) >> BP_SDMAARM_XTRIG_CONF2_NUM7) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF2_NUM7. +#define BF_SDMAARM_XTRIG_CONF2_NUM7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF2_NUM7) & BM_SDMAARM_XTRIG_CONF2_NUM7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NUM7 field to a new value. +#define BW_SDMAARM_XTRIG_CONF2_NUM7(v) (HW_SDMAARM_XTRIG_CONF2_WR((HW_SDMAARM_XTRIG_CONF2_RD() & ~BM_SDMAARM_XTRIG_CONF2_NUM7) | BF_SDMAARM_XTRIG_CONF2_NUM7(v))) +#endif +//@} + +/*! @name Register SDMAARM_XTRIG_CONF2, field CNF7[30] (RW) + * + * Configuration of the SDMA event line number i that is connected to the cross-trigger. It + * determines whether the event line pulse is generated by receiving a DMA request or by starting a + * channel script execution. + * + * Values: + * - 0 - channel + * - 1 - DMA request + */ +//@{ +#define BP_SDMAARM_XTRIG_CONF2_CNF7 (30) //!< Bit position for SDMAARM_XTRIG_CONF2_CNF7. +#define BM_SDMAARM_XTRIG_CONF2_CNF7 (0x40000000) //!< Bit mask for SDMAARM_XTRIG_CONF2_CNF7. + +//! @brief Get value of SDMAARM_XTRIG_CONF2_CNF7 from a register value. +#define BG_SDMAARM_XTRIG_CONF2_CNF7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_XTRIG_CONF2_CNF7) >> BP_SDMAARM_XTRIG_CONF2_CNF7) + +//! @brief Format value for bitfield SDMAARM_XTRIG_CONF2_CNF7. +#define BF_SDMAARM_XTRIG_CONF2_CNF7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_XTRIG_CONF2_CNF7) & BM_SDMAARM_XTRIG_CONF2_CNF7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CNF7 field to a new value. +#define BW_SDMAARM_XTRIG_CONF2_CNF7(v) (HW_SDMAARM_XTRIG_CONF2_WR((HW_SDMAARM_XTRIG_CONF2_RD() & ~BM_SDMAARM_XTRIG_CONF2_CNF7) | BF_SDMAARM_XTRIG_CONF2_CNF7(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_SDMA_CHNPRIn - Channel Priority Registers +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_SDMA_CHNPRIn - Channel Priority Registers (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_sdma_chnprin +{ + reg32_t U; + struct _hw_sdmaarm_sdma_chnprin_bitfields + { + unsigned CHNPRIN : 3; //!< [2:0] This contains the priority of channel number n . + unsigned RESERVED0 : 29; //!< [31:3] Reserved + } B; +} hw_sdmaarm_sdma_chnprin_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_SDMA_CHNPRIn register + */ +//@{ +//! @brief Number of instances of the SDMAARM_SDMA_CHNPRIn register. +#define HW_SDMAARM_SDMA_CHNPRIn_COUNT (32) + +#define HW_SDMAARM_SDMA_CHNPRIn_ADDR(n) (REGS_SDMAARM_BASE + 0x100 + (0x4 * (n))) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_SDMA_CHNPRIn(n) (*(volatile hw_sdmaarm_sdma_chnprin_t *) HW_SDMAARM_SDMA_CHNPRIn_ADDR(n)) +#define HW_SDMAARM_SDMA_CHNPRIn_RD(n) (HW_SDMAARM_SDMA_CHNPRIn(n).U) +#define HW_SDMAARM_SDMA_CHNPRIn_WR(n, v) (HW_SDMAARM_SDMA_CHNPRIn(n).U = (v)) +#define HW_SDMAARM_SDMA_CHNPRIn_SET(n, v) (HW_SDMAARM_SDMA_CHNPRIn_WR(n, HW_SDMAARM_SDMA_CHNPRIn_RD(n) | (v))) +#define HW_SDMAARM_SDMA_CHNPRIn_CLR(n, v) (HW_SDMAARM_SDMA_CHNPRIn_WR(n, HW_SDMAARM_SDMA_CHNPRIn_RD(n) & ~(v))) +#define HW_SDMAARM_SDMA_CHNPRIn_TOG(n, v) (HW_SDMAARM_SDMA_CHNPRIn_WR(n, HW_SDMAARM_SDMA_CHNPRIn_RD(n) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_SDMA_CHNPRIn bitfields + */ + +/*! @name Register SDMAARM_SDMA_CHNPRIn, field CHNPRIN[2:0] (RW) + * + * This contains the priority of channel number n . Useful values are between 1 and 7; 0 is reserved + * by the SDMA hardware to determine when there is no pending channel. Reset value is 0, which + * prevents the channels from starting. + */ +//@{ +#define BP_SDMAARM_SDMA_CHNPRIn_CHNPRIN (0) //!< Bit position for SDMAARM_SDMA_CHNPRIn_CHNPRIN. +#define BM_SDMAARM_SDMA_CHNPRIn_CHNPRIN (0x00000007) //!< Bit mask for SDMAARM_SDMA_CHNPRIn_CHNPRIN. + +//! @brief Get value of SDMAARM_SDMA_CHNPRIn_CHNPRIN from a register value. +#define BG_SDMAARM_SDMA_CHNPRIn_CHNPRIN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_SDMA_CHNPRIn_CHNPRIN) >> BP_SDMAARM_SDMA_CHNPRIn_CHNPRIN) + +//! @brief Format value for bitfield SDMAARM_SDMA_CHNPRIn_CHNPRIN. +#define BF_SDMAARM_SDMA_CHNPRIn_CHNPRIN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_SDMA_CHNPRIn_CHNPRIN) & BM_SDMAARM_SDMA_CHNPRIn_CHNPRIN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHNPRIN field to a new value. +#define BW_SDMAARM_SDMA_CHNPRIn_CHNPRIN(n, v) (HW_SDMAARM_SDMA_CHNPRIn_WR(n, (HW_SDMAARM_SDMA_CHNPRIn_RD(n) & ~BM_SDMAARM_SDMA_CHNPRIn_CHNPRIN) | BF_SDMAARM_SDMA_CHNPRIn_CHNPRIN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SDMAARM_CHNENBLn - Channel Enable RAM +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SDMAARM_CHNENBLn - Channel Enable RAM (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_sdmaarm_chnenbln +{ + reg32_t U; + struct _hw_sdmaarm_chnenbln_bitfields + { + unsigned ENBLN : 32; //!< [31:0] This 32-bit value selects the channels that are triggered by the DMA request number n . + } B; +} hw_sdmaarm_chnenbln_t; +#endif + +/*! + * @name Constants and macros for entire SDMAARM_CHNENBLn register + */ +//@{ +//! @brief Number of instances of the SDMAARM_CHNENBLn register. +#define HW_SDMAARM_CHNENBLn_COUNT (48) + +#define HW_SDMAARM_CHNENBLn_ADDR(n) (REGS_SDMAARM_BASE + 0x200 + (0x4 * (n))) + +#ifndef __LANGUAGE_ASM__ +#define HW_SDMAARM_CHNENBLn(n) (*(volatile hw_sdmaarm_chnenbln_t *) HW_SDMAARM_CHNENBLn_ADDR(n)) +#define HW_SDMAARM_CHNENBLn_RD(n) (HW_SDMAARM_CHNENBLn(n).U) +#define HW_SDMAARM_CHNENBLn_WR(n, v) (HW_SDMAARM_CHNENBLn(n).U = (v)) +#define HW_SDMAARM_CHNENBLn_SET(n, v) (HW_SDMAARM_CHNENBLn_WR(n, HW_SDMAARM_CHNENBLn_RD(n) | (v))) +#define HW_SDMAARM_CHNENBLn_CLR(n, v) (HW_SDMAARM_CHNENBLn_WR(n, HW_SDMAARM_CHNENBLn_RD(n) & ~(v))) +#define HW_SDMAARM_CHNENBLn_TOG(n, v) (HW_SDMAARM_CHNENBLn_WR(n, HW_SDMAARM_CHNENBLn_RD(n) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SDMAARM_CHNENBLn bitfields + */ + +/*! @name Register SDMAARM_CHNENBLn, field ENBLN[31:0] (RW) + * + * This 32-bit value selects the channels that are triggered by the DMA request number n . If + * ENBLn[i] is set to 1, bit EP[i] will be set when the DMA request n is received. These 48 32-bit + * registers are physically located in a RAM, with no known reset value. It is thus essential for + * the ARM platform to program them before any DMA request is triggered to the SDMA, otherwise an + * unpredictable combination of channels may be started. + */ +//@{ +#define BP_SDMAARM_CHNENBLn_ENBLN (0) //!< Bit position for SDMAARM_CHNENBLn_ENBLN. +#define BM_SDMAARM_CHNENBLn_ENBLN (0xffffffff) //!< Bit mask for SDMAARM_CHNENBLn_ENBLN. + +//! @brief Get value of SDMAARM_CHNENBLn_ENBLN from a register value. +#define BG_SDMAARM_CHNENBLn_ENBLN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMAARM_CHNENBLn_ENBLN) >> BP_SDMAARM_CHNENBLn_ENBLN) + +//! @brief Format value for bitfield SDMAARM_CHNENBLn_ENBLN. +#define BF_SDMAARM_CHNENBLn_ENBLN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMAARM_CHNENBLn_ENBLN) & BM_SDMAARM_CHNENBLn_ENBLN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENBLN field to a new value. +#define BW_SDMAARM_CHNENBLn_ENBLN(n, v) (HW_SDMAARM_CHNENBLn_WR(n, (HW_SDMAARM_CHNENBLn_RD(n) & ~BM_SDMAARM_CHNENBLn_ENBLN) | BF_SDMAARM_CHNENBLn_ENBLN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// hw_sdmaarm_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All SDMAARM module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_sdmaarm +{ + volatile hw_sdmaarm_mc0ptr_t MC0PTR; //!< ARM platform Channel 0 Pointer + volatile hw_sdmaarm_intr_t INTR; //!< Channel Interrupts + volatile hw_sdmaarm_stop_stat_t STOP_STAT; //!< Channel Stop/Channel Status + volatile hw_sdmaarm_hstart_t HSTART; //!< Channel Start + volatile hw_sdmaarm_evtovr_t EVTOVR; //!< Channel Event Override + volatile hw_sdmaarm_dspovr_t DSPOVR; //!< Channel BP Override + volatile hw_sdmaarm_hostovr_t HOSTOVR; //!< Channel ARM platform Override + volatile hw_sdmaarm_evtpend_t EVTPEND; //!< Channel Event Pending + reg32_t _reserved0; + volatile hw_sdmaarm_reset_t RESET; //!< Reset Register + volatile hw_sdmaarm_evterr_t EVTERR; //!< DMA Request Error Register + volatile hw_sdmaarm_intrmask_t INTRMASK; //!< Channel ARM platform Interrupt Mask + volatile hw_sdmaarm_psw_t PSW; //!< Schedule Status + volatile hw_sdmaarm_evterrdbg_t EVTERRDBG; //!< DMA Request Error Register + volatile hw_sdmaarm_config_t CONFIG; //!< Configuration Register + volatile hw_sdmaarm_sdma_lock_t SDMA_LOCK; //!< SDMA LOCK + volatile hw_sdmaarm_once_enb_t ONCE_ENB; //!< OnCE Enable + volatile hw_sdmaarm_once_data_t ONCE_DATA; //!< OnCE Data Register + volatile hw_sdmaarm_once_instr_t ONCE_INSTR; //!< OnCE Instruction Register + volatile hw_sdmaarm_once_stat_t ONCE_STAT; //!< OnCE Status Register + volatile hw_sdmaarm_once_cmd_t ONCE_CMD; //!< OnCE Command Register + reg32_t _reserved1; + volatile hw_sdmaarm_illinstaddr_t ILLINSTADDR; //!< Illegal Instruction Trap Address + volatile hw_sdmaarm_chn0addr_t CHN0ADDR; //!< Channel 0 Boot Address + volatile hw_sdmaarm_evt_mirror_t EVT_MIRROR; //!< DMA Requests + volatile hw_sdmaarm_evt_mirror2_t EVT_MIRROR2; //!< DMA Requests 2 + reg32_t _reserved2[2]; + volatile hw_sdmaarm_xtrig_conf1_t XTRIG_CONF1; //!< Cross-Trigger Events Configuration Register 1 + volatile hw_sdmaarm_xtrig_conf2_t XTRIG_CONF2; //!< Cross-Trigger Events Configuration Register 2 + reg32_t _reserved3[34]; + volatile hw_sdmaarm_sdma_chnprin_t SDMA_CHNPRIn[32]; //!< Channel Priority Registers + reg32_t _reserved4[32]; + volatile hw_sdmaarm_chnenbln_t CHNENBLn[48]; //!< Channel Enable RAM +} hw_sdmaarm_t; +#pragma pack() + +//! @brief Macro to access all SDMAARM registers. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_SDMAARM. +#define HW_SDMAARM (*(hw_sdmaarm_t *) REGS_SDMAARM_BASE) +#endif + +#endif // __HW_SDMAARM_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsspba.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsspba.h new file mode 100644 index 0000000000000000000000000000000000000000..01fd2cbc307e2e7ee6197268d55057bbd9ffa47f --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsspba.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_SPBA_REGISTERS_H__ +#define __HW_SPBA_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL SPBA + * + * Temperature Monitor + * + * Registers defined in this header file: + * - HW_SPBA_PRRn - Peripheral Rights Register + * + * - hw_spba_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_SPBA_BASE +#define HW_SPBA_INSTANCE_COUNT (1) //!< Number of instances of the SPBA module. +#define REGS_SPBA_BASE (0x0203c000) //!< Base address for SPBA. +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_SPBA_PRRn - Peripheral Rights Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_SPBA_PRRn - Peripheral Rights Register (RW) + * + * Reset value: 0x00000007 + * + * This register controls master ownership and access for a peripheral. + */ +typedef union _hw_spba_prrn +{ + reg32_t U; + struct _hw_spba_prrn_bitfields + { + unsigned RARA : 1; //!< [0] Resource Access Right. + unsigned RARB : 1; //!< [1] Resource Access Right. + unsigned RARC : 1; //!< [2] Resource Access Right. + unsigned RESERVED0 : 13; //!< [15:3] Reserved + unsigned ROI : 2; //!< [17:16] Resource Owner ID. + unsigned RESERVED1 : 12; //!< [29:18] Reserved + unsigned RMO : 2; //!< [31:30] Requesting Master Owner. + } B; +} hw_spba_prrn_t; +#endif + +/*! + * @name Constants and macros for entire SPBA_PRRn register + */ +//@{ +//! @brief Number of instances of the SPBA_PRRn register. +#define HW_SPBA_PRRn_COUNT (32) + +#define HW_SPBA_PRRn_ADDR(n) (REGS_SPBA_BASE + 0x0 + (0x4 * (n))) + +#ifndef __LANGUAGE_ASM__ +#define HW_SPBA_PRRn(n) (*(volatile hw_spba_prrn_t *) HW_SPBA_PRRn_ADDR(n)) +#define HW_SPBA_PRRn_RD(n) (HW_SPBA_PRRn(n).U) +#define HW_SPBA_PRRn_WR(n, v) (HW_SPBA_PRRn(n).U = (v)) +#define HW_SPBA_PRRn_SET(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) | (v))) +#define HW_SPBA_PRRn_CLR(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) & ~(v))) +#define HW_SPBA_PRRn_TOG(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual SPBA_PRRn bitfields + */ + +/*! @name Register SPBA_PRRn, field RARA[0] (RW) + * + * Resource Access Right. Control and Status bit for master A. This field indicates whether master A + * can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all + * the master can be granted on a peripheral, but only one access at a time will be granted by + * SPBA). + * + * Values: + * - PROHIBITED = 0 - Access to peripheral is not allowed. + * - ALLOWED = 1 - Access to peripheral is granted. + */ +//@{ +#define BP_SPBA_PRRn_RARA (0) //!< Bit position for SPBA_PRRn_RARA. +#define BM_SPBA_PRRn_RARA (0x00000001) //!< Bit mask for SPBA_PRRn_RARA. + +//! @brief Get value of SPBA_PRRn_RARA from a register value. +#define BG_SPBA_PRRn_RARA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARA) >> BP_SPBA_PRRn_RARA) + +//! @brief Format value for bitfield SPBA_PRRn_RARA. +#define BF_SPBA_PRRn_RARA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARA) & BM_SPBA_PRRn_RARA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RARA field to a new value. +#define BW_SPBA_PRRn_RARA(n, v) (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARA) | BF_SPBA_PRRn_RARA(v))) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_SPBA_PRRn_RARA_V(v) BF_SPBA_PRRn_RARA(BV_SPBA_PRRn_RARA__##v) + +#define BV_SPBA_PRRn_RARA__PROHIBITED (0x0) //!< Access to peripheral is not allowed. +#define BV_SPBA_PRRn_RARA__ALLOWED (0x1) //!< Access to peripheral is granted. +//@} + +/*! @name Register SPBA_PRRn, field RARB[1] (RW) + * + * Resource Access Right. Control and Status bit for master B. This field indicates whether master B + * can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all + * the master can be granted on a peripheral, but only one access at a time will be granted by + * SPBA). + * + * Values: + * - PROHIBITED = 0 - Access to peripheral is not allowed. + * - ALLOWED = 1 - Access to peripheral is granted. + */ +//@{ +#define BP_SPBA_PRRn_RARB (1) //!< Bit position for SPBA_PRRn_RARB. +#define BM_SPBA_PRRn_RARB (0x00000002) //!< Bit mask for SPBA_PRRn_RARB. + +//! @brief Get value of SPBA_PRRn_RARB from a register value. +#define BG_SPBA_PRRn_RARB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARB) >> BP_SPBA_PRRn_RARB) + +//! @brief Format value for bitfield SPBA_PRRn_RARB. +#define BF_SPBA_PRRn_RARB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARB) & BM_SPBA_PRRn_RARB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RARB field to a new value. +#define BW_SPBA_PRRn_RARB(n, v) (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARB) | BF_SPBA_PRRn_RARB(v))) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_SPBA_PRRn_RARB_V(v) BF_SPBA_PRRn_RARB(BV_SPBA_PRRn_RARB__##v) + +#define BV_SPBA_PRRn_RARB__PROHIBITED (0x0) //!< Access to peripheral is not allowed. +#define BV_SPBA_PRRn_RARB__ALLOWED (0x1) //!< Access to peripheral is granted. +//@} + +/*! @name Register SPBA_PRRn, field RARC[2] (RW) + * + * Resource Access Right. Control and Status bit for master C. This field indicates whether master C + * can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all + * the master can be granted on a peripheral, but only one access at a time will be granted by + * SPBA). + * + * Values: + * - PROHIBITED = 0 - Access to peripheral is not allowed. + * - ALLOWED = 1 - Access to peripheral is granted. + */ +//@{ +#define BP_SPBA_PRRn_RARC (2) //!< Bit position for SPBA_PRRn_RARC. +#define BM_SPBA_PRRn_RARC (0x00000004) //!< Bit mask for SPBA_PRRn_RARC. + +//! @brief Get value of SPBA_PRRn_RARC from a register value. +#define BG_SPBA_PRRn_RARC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARC) >> BP_SPBA_PRRn_RARC) + +//! @brief Format value for bitfield SPBA_PRRn_RARC. +#define BF_SPBA_PRRn_RARC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARC) & BM_SPBA_PRRn_RARC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RARC field to a new value. +#define BW_SPBA_PRRn_RARC(n, v) (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARC) | BF_SPBA_PRRn_RARC(v))) +#endif + +//! @brief Macro to simplify usage of value macros. +#define BF_SPBA_PRRn_RARC_V(v) BF_SPBA_PRRn_RARC(BV_SPBA_PRRn_RARC__##v) + +#define BV_SPBA_PRRn_RARC__PROHIBITED (0x0) //!< Access to peripheral is not allowed. +#define BV_SPBA_PRRn_RARC__ALLOWED (0x1) //!< Access to peripheral is granted. +//@} + +/*! @name Register SPBA_PRRn, field ROI[17:16] (RO) + * + * Resource Owner ID. This field indicates which master (one at a time) can access to the PRR for + * rights modification. This is a read-only register. After reset, ROI bits are cleared ("00" -> un- + * owned resource). A master performing a write access to the an un-owned PRR will get its ID + * automatically written into ROI, while modifying RARx bits. It can then read back the RMO, RAR, + * ROI bits to make sure RMO returns the right value, ROI bits contain its ID and RARx bits are + * correctly asserted. Then no other master (whom ID is different from the one stored in ROI) will + * be able to modify RAR fields. Owner master of a peripheral can assert its dead_owner signal, or + * write 1'b0 in the RARx to release the ownership (ROI[1:0] reset to 2'b0). + * + * Values: + * - UNOWNED = 00 - Unowned resource. + * - MASTER_A = 01 - The resource is owned by master A port. + * - MASTER_B = 10 - The resource is owned by master B port. + * - MASTER_C = 11 - The resource is owned by master C port. + */ +//@{ +#define BP_SPBA_PRRn_ROI (16) //!< Bit position for SPBA_PRRn_ROI. +#define BM_SPBA_PRRn_ROI (0x00030000) //!< Bit mask for SPBA_PRRn_ROI. + +//! @brief Get value of SPBA_PRRn_ROI from a register value. +#define BG_SPBA_PRRn_ROI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_ROI) >> BP_SPBA_PRRn_ROI) + +//! @brief Macro to simplify usage of value macros. +#define BF_SPBA_PRRn_ROI_V(v) BF_SPBA_PRRn_ROI(BV_SPBA_PRRn_ROI__##v) + +#define BV_SPBA_PRRn_ROI__UNOWNED (0x0) //!< Unowned resource. +#define BV_SPBA_PRRn_ROI__MASTER_A (0x1) //!< The resource is owned by master A port. +#define BV_SPBA_PRRn_ROI__MASTER_B (0x2) //!< The resource is owned by master B port. +#define BV_SPBA_PRRn_ROI__MASTER_C (0x3) //!< The resource is owned by master C port. +//@} + +/*! @name Register SPBA_PRRn, field RMO[31:30] (RO) + * + * Requesting Master Owner. This 2-bit register field indicates if the corresponding resource is + * owned by the requesting master or not. This register is reset to 2'b0 if ROI = 2'b0. + * + * Values: + * - UNOWNED = 00 - The resource is unowned. + * - 01 - Reserved. + * - ANOTHER_MASTER = 10 - The resource is owned by another master. + * - REQUESTING_MASTER = 11 - The resource is owned by the requesting master. + */ +//@{ +#define BP_SPBA_PRRn_RMO (30) //!< Bit position for SPBA_PRRn_RMO. +#define BM_SPBA_PRRn_RMO (0xc0000000) //!< Bit mask for SPBA_PRRn_RMO. + +//! @brief Get value of SPBA_PRRn_RMO from a register value. +#define BG_SPBA_PRRn_RMO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RMO) >> BP_SPBA_PRRn_RMO) + +//! @brief Macro to simplify usage of value macros. +#define BF_SPBA_PRRn_RMO_V(v) BF_SPBA_PRRn_RMO(BV_SPBA_PRRn_RMO__##v) + +#define BV_SPBA_PRRn_RMO__UNOWNED (0x0) //!< The resource is unowned. +#define BV_SPBA_PRRn_RMO__ANOTHER_MASTER (0x2) //!< The resource is owned by another master. +#define BV_SPBA_PRRn_RMO__REQUESTING_MASTER (0x3) //!< The resource is owned by the requesting master. +//@} + +//------------------------------------------------------------------------------------------- +// hw_spba_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All SPBA module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_spba +{ + volatile hw_spba_prrn_t PRRn[32]; //!< Peripheral Rights Register +} hw_spba_t; +#pragma pack() + +//! @brief Macro to access all SPBA registers. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_SPBA. +#define HW_SPBA (*(hw_spba_t *) REGS_SPBA_BASE) +#endif + +#endif // __HW_SPBA_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsuart.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsuart.h new file mode 100644 index 0000000000000000000000000000000000000000..7309438067f5487fad0d8b336b3fa2bcca9123bf --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsuart.h @@ -0,0 +1,3848 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_UART_REGISTERS_H__ +#define __HW_UART_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL UART + * + * UARTv2 + * + * Registers defined in this header file: + * - HW_UART_URXD - UART Receiver Register + * - HW_UART_UTXD - UART Transmitter Register + * - HW_UART_UCR1 - UART Control Register 1 + * - HW_UART_UCR2 - UART Control Register 2 + * - HW_UART_UCR3 - UART Control Register 3 + * - HW_UART_UCR4 - UART Control Register 4 + * - HW_UART_UFCR - UART FIFO Control Register + * - HW_UART_USR1 - UART Status Register 1 + * - HW_UART_USR2 - UART Status Register 2 + * - HW_UART_UESC - UART Escape Character Register + * - HW_UART_UTIM - UART Escape Timer Register + * - HW_UART_UBIR - UART BRM Incremental Register + * - HW_UART_UBMR - UART BRM Modulator Register + * - HW_UART_UBRC - UART Baud Rate Count Register + * - HW_UART_ONEMS - UART One Millisecond Register + * - HW_UART_UTS - UART Test Register + * - HW_UART_UMCR - UART RS-485 Mode Control Register + * + * - hw_uart_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_UART_BASE +#define HW_UART_INSTANCE_COUNT (8) //!< Number of instances of the UART module. +#define HW_UART1 (1) //!< Instance number for UART1. +#define HW_UART2 (2) //!< Instance number for UART2. +#define HW_UART3 (3) //!< Instance number for UART3. +#define HW_UART4 (4) //!< Instance number for UART4. +#define HW_UART5 (5) /*!< Instance number for UART5. */ +#define HW_UART6 (6) /*!< Instance number for UART6. */ +#define HW_UART7 (7) /*!< Instance number for UART7. */ +#define HW_UART8 (8) /*!< Instance number for UART8. */ + +#define REGS_UART1_BASE (0x02020000) //!< Base address for UART instance number 1. +#define REGS_UART2_BASE (0x021e8000) //!< Base address for UART instance number 2. +#define REGS_UART3_BASE (0x021ec000) //!< Base address for UART instance number 3. +#define REGS_UART4_BASE (0x021f0000) //!< Base address for UART instance number 4. +#define REGS_UART5_BASE (0x021f4000) //!< Base address for UART instance number 5. +#define REGS_UART6_BASE (0x21FC000U) //!< Base address for UART instance number 6. +#define REGS_UART7_BASE (0x2018000U) //!< Base address for UART instance number 7. +#define REGS_UART8_BASE (0x2024000U) //!< Base address for UART instance number 8. + +//! @brief Get the base address of UART by instance number. +//! @param x UART instance number, from 1 through 5. +#define REGS_UART_BASE(x) ( (x) == HW_UART1 ? REGS_UART1_BASE : (x) == HW_UART2 ? REGS_UART2_BASE : (x) == HW_UART3 ? REGS_UART3_BASE : (x) == HW_UART4 ? REGS_UART4_BASE : (x) == HW_UART5 ? REGS_UART5_BASE : (x) == HW_UART6 ? REGS_UART6_BASE : (x) == HW_UART7 ? REGS_UART7_BASE : REGS_UART8_BASE) + +//! @brief Get the instance number given a base address. +//! @param b Base address for an instance of UART. +#define REGS_UART_INSTANCE(b) ( (b) == REGS_UART1_BASE ? HW_UART1 : (b) == REGS_UART2_BASE ? HW_UART2 : (b) == REGS_UART3_BASE ? HW_UART3 : (b) == REGS_UART4_BASE ? HW_UART4 : (b) == REGS_UART5_BASE ? HW_UART5 : (b) == REGS_UART6_BASE ? HW_UART6 : (b) == REGS_UART7_BASE ? HW_UART7 : (b) == REGS_UART8_BASE ? HW_UART8 : 0) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_URXD - UART Receiver Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_URXD - UART Receiver Register (RO) + * + * Reset value: 0x00000000 + * + * The UART will yield a transfer error on the peripheral bus when core is reading URXD register + * with receive interface disabled (RXEN=0 or UARTEN=0). + */ +typedef union _hw_uart_urxd +{ + reg32_t U; + struct _hw_uart_urxd_bitfields + { + unsigned RX_DATA : 8; //!< [7:0] Received Data . + unsigned RESERVED0 : 2; //!< [9:8] Reserved + unsigned PRERR : 1; //!< [10] In RS-485 mode, it holds the ninth data bit (bit [8]) of received 9-bit RS-485 data + unsigned BRK : 1; //!< [11] BREAK Detect. + unsigned FRMERR : 1; //!< [12] Frame Error. + unsigned OVRRUN : 1; //!< [13] Receiver Overrun. + unsigned ERR : 1; //!< [14] Error Detect. + unsigned CHARRDY : 1; //!< [15] Character Ready. + unsigned RESERVED1 : 16; //!< [31:16] Reserved + } B; +} hw_uart_urxd_t; +#endif + +/*! + * @name Constants and macros for entire UART_URXD register + */ +//@{ +#define HW_UART_URXD_ADDR(x) (REGS_UART_BASE(x) + 0x0) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_URXD(x) (*(volatile hw_uart_urxd_t *) HW_UART_URXD_ADDR(x)) +#define HW_UART_URXD_RD(x) (HW_UART_URXD(x).U) +#endif +//@} + +/* + * constants & macros for individual UART_URXD bitfields + */ + +/*! @name Register UART_URXD, field RX_DATA[7:0] (RO) + * + * Received Data . Holds the received character. In 7-bit mode, the most significant bit (MSB) is + * forced to 0. In 8-bit mode, all bits are active. + */ +//@{ +#define BP_UART_URXD_RX_DATA (0) //!< Bit position for UART_URXD_RX_DATA. +#define BM_UART_URXD_RX_DATA (0x000000ff) //!< Bit mask for UART_URXD_RX_DATA. + +//! @brief Get value of UART_URXD_RX_DATA from a register value. +#define BG_UART_URXD_RX_DATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_URXD_RX_DATA) >> BP_UART_URXD_RX_DATA) +//@} + +/*! @name Register UART_URXD, field PRERR[10] (RO) + * + * In RS-485 mode, it holds the ninth data bit (bit [8]) of received 9-bit RS-485 data In RS232/IrDA + * mode, it is the Parity Error flag . Indicates whether the current character was detected with a + * parity error and is possibly corrupted. PRERR is updated for each character read from the RxFIFO. + * When parity is disabled, PRERR always reads as 0. + * + * Values: + * - 0 - = No parity error was detected for data in the RX_DATA field + * - 1 - = A parity error was detected for data in the RX_DATA field + */ +//@{ +#define BP_UART_URXD_PRERR (10) //!< Bit position for UART_URXD_PRERR. +#define BM_UART_URXD_PRERR (0x00000400) //!< Bit mask for UART_URXD_PRERR. + +//! @brief Get value of UART_URXD_PRERR from a register value. +#define BG_UART_URXD_PRERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_URXD_PRERR) >> BP_UART_URXD_PRERR) +//@} + +/*! @name Register UART_URXD, field BRK[11] (RO) + * + * BREAK Detect. Indicates whether the current character was detected as a BREAK character. The data + * bits and the stop bit are all 0. The FRMERR bit is set when BRK is set. When odd parity is + * selected, PRERR is also set when BRK is set. BRK is valid for each character read from the + * RxFIFO. + * + * Values: + * - 0 - The current character is not a BREAK character + * - 1 - The current character is a BREAK character + */ +//@{ +#define BP_UART_URXD_BRK (11) //!< Bit position for UART_URXD_BRK. +#define BM_UART_URXD_BRK (0x00000800) //!< Bit mask for UART_URXD_BRK. + +//! @brief Get value of UART_URXD_BRK from a register value. +#define BG_UART_URXD_BRK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_URXD_BRK) >> BP_UART_URXD_BRK) +//@} + +/*! @name Register UART_URXD, field FRMERR[12] (RO) + * + * Frame Error. Indicates whether the current character had a framing error (a missing stop bit) and + * is possibly corrupted. FRMERR is updated for each character read from the RxFIFO. + * + * Values: + * - 0 - The current character has no framing error + * - 1 - The current character has a framing error + */ +//@{ +#define BP_UART_URXD_FRMERR (12) //!< Bit position for UART_URXD_FRMERR. +#define BM_UART_URXD_FRMERR (0x00001000) //!< Bit mask for UART_URXD_FRMERR. + +//! @brief Get value of UART_URXD_FRMERR from a register value. +#define BG_UART_URXD_FRMERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_URXD_FRMERR) >> BP_UART_URXD_FRMERR) +//@} + +/*! @name Register UART_URXD, field OVRRUN[13] (RO) + * + * Receiver Overrun. This read-only bit, when HIGH, indicates that the corresponding character was + * stored in the last position (32nd) of the Rx FIFO. Even if a 33rd character has not been + * detected, this bit will be set to '1' for the 32nd character. + * + * Values: + * - 0 - No RxFIFO overrun was detected + * - 1 - A RxFIFO overrun was detected + */ +//@{ +#define BP_UART_URXD_OVRRUN (13) //!< Bit position for UART_URXD_OVRRUN. +#define BM_UART_URXD_OVRRUN (0x00002000) //!< Bit mask for UART_URXD_OVRRUN. + +//! @brief Get value of UART_URXD_OVRRUN from a register value. +#define BG_UART_URXD_OVRRUN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_URXD_OVRRUN) >> BP_UART_URXD_OVRRUN) +//@} + +/*! @name Register UART_URXD, field ERR[14] (RO) + * + * Error Detect. Indicates whether the character present in the RX_DATA field has an error (OVRRUN, + * FRMERR, BRK or PRERR) status. The ERR bit is updated and valid for each received character. + * + * Values: + * - 0 - No error status was detected + * - 1 - An error status was detected + */ +//@{ +#define BP_UART_URXD_ERR (14) //!< Bit position for UART_URXD_ERR. +#define BM_UART_URXD_ERR (0x00004000) //!< Bit mask for UART_URXD_ERR. + +//! @brief Get value of UART_URXD_ERR from a register value. +#define BG_UART_URXD_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_URXD_ERR) >> BP_UART_URXD_ERR) +//@} + +/*! @name Register UART_URXD, field CHARRDY[15] (RO) + * + * Character Ready. This read-only bit indicates an invalid read when the FIFO becomes empty and + * software tries to read the same old data. This bit should not be used for polling for data + * written to the RX FIFO. + * + * Values: + * - 0 - Character in RX_DATA field and associated flags are invalid. + * - 1 - Character in RX_DATA field and associated flags valid and ready for reading. + */ +//@{ +#define BP_UART_URXD_CHARRDY (15) //!< Bit position for UART_URXD_CHARRDY. +#define BM_UART_URXD_CHARRDY (0x00008000) //!< Bit mask for UART_URXD_CHARRDY. + +//! @brief Get value of UART_URXD_CHARRDY from a register value. +#define BG_UART_URXD_CHARRDY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_URXD_CHARRDY) >> BP_UART_URXD_CHARRDY) +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UTXD - UART Transmitter Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UTXD - UART Transmitter Register (WO) + * + * Reset value: 0x00000000 + * + * The UART will yield a transfer error on the peripheral bus when core is writing into UART_URXD + * register with transmit interface disabled (TXEN=0 or UARTEN=0). Memory space between UART_URXD + * and UART_UTXD registers is reserved. Any read or write access to this space will be considered as + * an invalid access and yield a transfer error . + */ +typedef union _hw_uart_utxd +{ + reg32_t U; + struct _hw_uart_utxd_bitfields + { + unsigned TX_DATA : 8; //!< [7:0] Transmit Data . + unsigned RESERVED0 : 24; //!< [31:8] Reserved. + } B; +} hw_uart_utxd_t; +#endif + +/*! + * @name Constants and macros for entire UART_UTXD register + */ +//@{ +#define HW_UART_UTXD_ADDR(x) (REGS_UART_BASE(x) + 0x40) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UTXD(x) (*(volatile hw_uart_utxd_t *) HW_UART_UTXD_ADDR(x)) +#define HW_UART_UTXD_WR(x, v) (HW_UART_UTXD(x).U = (v)) +#endif +//@} + +/* + * constants & macros for individual UART_UTXD bitfields + */ + +/*! @name Register UART_UTXD, field TX_DATA[7:0] (WO) + * + * Transmit Data . Holds the parallel transmit data inputs. In 7-bit mode, D7 is ignored. In 8-bit + * mode, all bits are used. Data is transmitted least significant bit (LSB) first. A new character + * is transmitted when the TX_DATA field is written. The TX_DATA field must be written only when the + * TRDY bit is high to ensure that corrupted data is not sent. + */ +//@{ +#define BP_UART_UTXD_TX_DATA (0) //!< Bit position for UART_UTXD_TX_DATA. +#define BM_UART_UTXD_TX_DATA (0x000000ff) //!< Bit mask for UART_UTXD_TX_DATA. + +//! @brief Get value of UART_UTXD_TX_DATA from a register value. +#define BG_UART_UTXD_TX_DATA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTXD_TX_DATA) >> BP_UART_UTXD_TX_DATA) + +//! @brief Format value for bitfield UART_UTXD_TX_DATA. +#define BF_UART_UTXD_TX_DATA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTXD_TX_DATA) & BM_UART_UTXD_TX_DATA) +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UCR1 - UART Control Register 1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UCR1 - UART Control Register 1 (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_uart_ucr1 +{ + reg32_t U; + struct _hw_uart_ucr1_bitfields + { + unsigned UARTEN : 1; //!< [0] UART Enable . + unsigned DOZE : 1; //!< [1] DOZE . + unsigned ATDMAEN : 1; //!< [2] Aging DMA Timer Enable . + unsigned TXDMAEN : 1; //!< [3] Transmitter Ready DMA Enable . + unsigned SNDBRK : 1; //!< [4] Send BREAK . + unsigned RTSDEN : 1; //!< [5] RTS Delta Interrupt Enable . + unsigned TXMPTYEN : 1; //!< [6] Transmitter Empty Interrupt Enable . + unsigned IREN : 1; //!< [7] Infrared Interface Enable . + unsigned RXDMAEN : 1; //!< [8] Receive Ready DMA Enable . + unsigned RRDYEN : 1; //!< [9] Receiver Ready Interrupt Enable . + unsigned ICD : 2; //!< [11:10] Idle Condition Detect . + unsigned IDEN : 1; //!< [12] Idle Condition Detected Interrupt Enable . + unsigned TRDYEN : 1; //!< [13] Transmitter Ready Interrupt Enable . + unsigned ADBR : 1; //!< [14] Automatic Detection of Baud Rate . + unsigned ADEN : 1; //!< [15] Automatic Baud Rate Detection Interrupt Enable . + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_ucr1_t; +#endif + +/*! + * @name Constants and macros for entire UART_UCR1 register + */ +//@{ +#define HW_UART_UCR1_ADDR(x) (REGS_UART_BASE(x) + 0x80) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UCR1(x) (*(volatile hw_uart_ucr1_t *) HW_UART_UCR1_ADDR(x)) +#define HW_UART_UCR1_RD(x) (HW_UART_UCR1(x).U) +#define HW_UART_UCR1_WR(x, v) (HW_UART_UCR1(x).U = (v)) +#define HW_UART_UCR1_SET(x, v) (HW_UART_UCR1_WR(x, HW_UART_UCR1_RD(x) | (v))) +#define HW_UART_UCR1_CLR(x, v) (HW_UART_UCR1_WR(x, HW_UART_UCR1_RD(x) & ~(v))) +#define HW_UART_UCR1_TOG(x, v) (HW_UART_UCR1_WR(x, HW_UART_UCR1_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UCR1 bitfields + */ + +/*! @name Register UART_UCR1, field UARTEN[0] (RW) + * + * UART Enable . Enables/Disables the UART. If UARTEN is negated in the middle of a transmission, + * the transmitter stops and pulls the TXD line to a logic 1. UARTEN must be set to 1 before any + * access to UTXD and URXD registers, otherwise a transfer error is returned. This bit can be set to + * 1 along with other bits in this register. There is no restriction to the sequence of programing + * this bit and other control registers. + * + * Values: + * - 0 - Disable the UART + * - 1 - Enable the UART + */ +//@{ +#define BP_UART_UCR1_UARTEN (0) //!< Bit position for UART_UCR1_UARTEN. +#define BM_UART_UCR1_UARTEN (0x00000001) //!< Bit mask for UART_UCR1_UARTEN. + +//! @brief Get value of UART_UCR1_UARTEN from a register value. +#define BG_UART_UCR1_UARTEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_UARTEN) >> BP_UART_UCR1_UARTEN) + +//! @brief Format value for bitfield UART_UCR1_UARTEN. +#define BF_UART_UCR1_UARTEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_UARTEN) & BM_UART_UCR1_UARTEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the UARTEN field to a new value. +#define BW_UART_UCR1_UARTEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_UARTEN) | BF_UART_UCR1_UARTEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field DOZE[1] (RW) + * + * DOZE . Determines the UART enable condition in the DOZE state. When doze_req input pin is at '1', + * (the ARM Platform executes a doze instruction and the system is placed in the Doze State), the + * DOZE bit affects operation of the UART. While in the Doze State, if this bit is asserted, the + * UART is disabled. See the description in . + * + * Values: + * - 0 - The UART is enabled when in DOZE state + * - 1 - The UART is disabled when in DOZE state + */ +//@{ +#define BP_UART_UCR1_DOZE (1) //!< Bit position for UART_UCR1_DOZE. +#define BM_UART_UCR1_DOZE (0x00000002) //!< Bit mask for UART_UCR1_DOZE. + +//! @brief Get value of UART_UCR1_DOZE from a register value. +#define BG_UART_UCR1_DOZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_DOZE) >> BP_UART_UCR1_DOZE) + +//! @brief Format value for bitfield UART_UCR1_DOZE. +#define BF_UART_UCR1_DOZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_DOZE) & BM_UART_UCR1_DOZE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DOZE field to a new value. +#define BW_UART_UCR1_DOZE(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_DOZE) | BF_UART_UCR1_DOZE(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field ATDMAEN[2] (RW) + * + * Aging DMA Timer Enable . Enables/Disables the receive DMA request dma_req_rx for the aging timer + * interrupt (triggered with AGTIM flag in USR1[8]). + * + * Values: + * - 0 - Disable AGTIM DMA request + * - 1 - Enable AGTIM DMA request + */ +//@{ +#define BP_UART_UCR1_ATDMAEN (2) //!< Bit position for UART_UCR1_ATDMAEN. +#define BM_UART_UCR1_ATDMAEN (0x00000004) //!< Bit mask for UART_UCR1_ATDMAEN. + +//! @brief Get value of UART_UCR1_ATDMAEN from a register value. +#define BG_UART_UCR1_ATDMAEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_ATDMAEN) >> BP_UART_UCR1_ATDMAEN) + +//! @brief Format value for bitfield UART_UCR1_ATDMAEN. +#define BF_UART_UCR1_ATDMAEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_ATDMAEN) & BM_UART_UCR1_ATDMAEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ATDMAEN field to a new value. +#define BW_UART_UCR1_ATDMAEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_ATDMAEN) | BF_UART_UCR1_ATDMAEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field TXDMAEN[3] (RW) + * + * Transmitter Ready DMA Enable . Enables/Disables the transmit DMA request dma_req_tx when the + * transmitter has one or more slots available in the TxFIFO. The fill level in the TxFIFO that + * generates the dma_req_tx is controlled by the TXTL bits. A DMA request will be issued as long as + * TXDMAEN and TRDY are high even if the transmitter is not enabled. In general, user should enable + * the transmitter before enabling the transmit DMA request. + * + * Values: + * - 0 - Disable transmit DMA request + * - 1 - Enable transmit DMA request + */ +//@{ +#define BP_UART_UCR1_TXDMAEN (3) //!< Bit position for UART_UCR1_TXDMAEN. +#define BM_UART_UCR1_TXDMAEN (0x00000008) //!< Bit mask for UART_UCR1_TXDMAEN. + +//! @brief Get value of UART_UCR1_TXDMAEN from a register value. +#define BG_UART_UCR1_TXDMAEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_TXDMAEN) >> BP_UART_UCR1_TXDMAEN) + +//! @brief Format value for bitfield UART_UCR1_TXDMAEN. +#define BF_UART_UCR1_TXDMAEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_TXDMAEN) & BM_UART_UCR1_TXDMAEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXDMAEN field to a new value. +#define BW_UART_UCR1_TXDMAEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_TXDMAEN) | BF_UART_UCR1_TXDMAEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field SNDBRK[4] (RW) + * + * Send BREAK . Forces the transmitter to send a BREAK character. The transmitter finishes sending + * the character in progress (if any) and sends BREAK characters until SNDBRK is reset. Because the + * transmitter samples SNDBRK after every bit is transmitted, it is important that SNDBRK is + * asserted high for a sufficient period of time to generate a valid BREAK. After the BREAK + * transmission completes, the UART transmits 2 mark bits. The user can continue to fill the TxFIFO + * and any characters remaining are transmitted when the BREAK is terminated. + * + * Values: + * - 0 - Do not send a BREAK character + * - 1 - Send a BREAK character (continuous 0s) + */ +//@{ +#define BP_UART_UCR1_SNDBRK (4) //!< Bit position for UART_UCR1_SNDBRK. +#define BM_UART_UCR1_SNDBRK (0x00000010) //!< Bit mask for UART_UCR1_SNDBRK. + +//! @brief Get value of UART_UCR1_SNDBRK from a register value. +#define BG_UART_UCR1_SNDBRK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_SNDBRK) >> BP_UART_UCR1_SNDBRK) + +//! @brief Format value for bitfield UART_UCR1_SNDBRK. +#define BF_UART_UCR1_SNDBRK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_SNDBRK) & BM_UART_UCR1_SNDBRK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SNDBRK field to a new value. +#define BW_UART_UCR1_SNDBRK(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_SNDBRK) | BF_UART_UCR1_SNDBRK(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field RTSDEN[5] (RW) + * + * RTS Delta Interrupt Enable . Enables/Disables the RTSD interrupt. The current status of the RTS + * pin is read in the RTSS bit. + * + * Values: + * - 0 - Disable RTSD interrupt + * - 1 - Enable RTSD interrupt + */ +//@{ +#define BP_UART_UCR1_RTSDEN (5) //!< Bit position for UART_UCR1_RTSDEN. +#define BM_UART_UCR1_RTSDEN (0x00000020) //!< Bit mask for UART_UCR1_RTSDEN. + +//! @brief Get value of UART_UCR1_RTSDEN from a register value. +#define BG_UART_UCR1_RTSDEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_RTSDEN) >> BP_UART_UCR1_RTSDEN) + +//! @brief Format value for bitfield UART_UCR1_RTSDEN. +#define BF_UART_UCR1_RTSDEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_RTSDEN) & BM_UART_UCR1_RTSDEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTSDEN field to a new value. +#define BW_UART_UCR1_RTSDEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_RTSDEN) | BF_UART_UCR1_RTSDEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field TXMPTYEN[6] (RW) + * + * Transmitter Empty Interrupt Enable . Enables/Disables the transmitter FIFO empty (TXFE) + * interrupt. interrupt_uart . When negated, the TXFE interrupt is disabled. An interrupt will be + * issued as long as TXMPTYEN and TXFE are high even if the transmitter is not enabled. In general, + * user should enable the transmitter before enabling the TXFE interrupt. + * + * Values: + * - 0 - Disable the transmitter FIFO empty interrupt + * - 1 - Enable the transmitter FIFO empty interrupt + */ +//@{ +#define BP_UART_UCR1_TXMPTYEN (6) //!< Bit position for UART_UCR1_TXMPTYEN. +#define BM_UART_UCR1_TXMPTYEN (0x00000040) //!< Bit mask for UART_UCR1_TXMPTYEN. + +//! @brief Get value of UART_UCR1_TXMPTYEN from a register value. +#define BG_UART_UCR1_TXMPTYEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_TXMPTYEN) >> BP_UART_UCR1_TXMPTYEN) + +//! @brief Format value for bitfield UART_UCR1_TXMPTYEN. +#define BF_UART_UCR1_TXMPTYEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_TXMPTYEN) & BM_UART_UCR1_TXMPTYEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXMPTYEN field to a new value. +#define BW_UART_UCR1_TXMPTYEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_TXMPTYEN) | BF_UART_UCR1_TXMPTYEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field IREN[7] (RW) + * + * Infrared Interface Enable . Enables/Disables the IR interface. See the IR interface description + * in , for more information. Note: MDEN(UMCR[0]) must be cleared to 0 when using IrDA interface. + * See + * + * Values: + * - 0 - Disable the IR interface + * - 1 - Enable the IR interface + */ +//@{ +#define BP_UART_UCR1_IREN (7) //!< Bit position for UART_UCR1_IREN. +#define BM_UART_UCR1_IREN (0x00000080) //!< Bit mask for UART_UCR1_IREN. + +//! @brief Get value of UART_UCR1_IREN from a register value. +#define BG_UART_UCR1_IREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_IREN) >> BP_UART_UCR1_IREN) + +//! @brief Format value for bitfield UART_UCR1_IREN. +#define BF_UART_UCR1_IREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_IREN) & BM_UART_UCR1_IREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IREN field to a new value. +#define BW_UART_UCR1_IREN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_IREN) | BF_UART_UCR1_IREN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field RXDMAEN[8] (RW) + * + * Receive Ready DMA Enable . Enables/Disables the receive DMA request dma_req_rx when the receiver + * has data in the RxFIFO. The fill level in the RxFIFO at which a DMA request is generated is + * controlled by the RXTL bits. When negated, the receive DMA request is disabled. + * + * Values: + * - 0 - Disable DMA request + * - 1 - Enable DMA request + */ +//@{ +#define BP_UART_UCR1_RXDMAEN (8) //!< Bit position for UART_UCR1_RXDMAEN. +#define BM_UART_UCR1_RXDMAEN (0x00000100) //!< Bit mask for UART_UCR1_RXDMAEN. + +//! @brief Get value of UART_UCR1_RXDMAEN from a register value. +#define BG_UART_UCR1_RXDMAEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_RXDMAEN) >> BP_UART_UCR1_RXDMAEN) + +//! @brief Format value for bitfield UART_UCR1_RXDMAEN. +#define BF_UART_UCR1_RXDMAEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_RXDMAEN) & BM_UART_UCR1_RXDMAEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXDMAEN field to a new value. +#define BW_UART_UCR1_RXDMAEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_RXDMAEN) | BF_UART_UCR1_RXDMAEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field RRDYEN[9] (RW) + * + * Receiver Ready Interrupt Enable . Enables/Disables the RRDY interrupt when the RxFIFO contains + * data. The fill level in the RxFIFO at which an interrupt is generated is controlled by the RXTL + * bits. When RRDYEN is negated, the receiver ready interrupt is disabled. + * + * Values: + * - 0 - Disables the RRDY interrupt + * - 1 - Enables the RRDY interrupt + */ +//@{ +#define BP_UART_UCR1_RRDYEN (9) //!< Bit position for UART_UCR1_RRDYEN. +#define BM_UART_UCR1_RRDYEN (0x00000200) //!< Bit mask for UART_UCR1_RRDYEN. + +//! @brief Get value of UART_UCR1_RRDYEN from a register value. +#define BG_UART_UCR1_RRDYEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_RRDYEN) >> BP_UART_UCR1_RRDYEN) + +//! @brief Format value for bitfield UART_UCR1_RRDYEN. +#define BF_UART_UCR1_RRDYEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_RRDYEN) & BM_UART_UCR1_RRDYEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RRDYEN field to a new value. +#define BW_UART_UCR1_RRDYEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_RRDYEN) | BF_UART_UCR1_RRDYEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field ICD[11:10] (RW) + * + * Idle Condition Detect . Controls the number of frames RXD is allowed to be idle before an idle + * condition is reported. + * + * Values: + * - 00 - Idle for more than 4 frames + * - 01 - Idle for more than 8 frames + * - 10 - Idle for more than 16 frames + * - 11 - Idle for more than 32 frames + */ +//@{ +#define BP_UART_UCR1_ICD (10) //!< Bit position for UART_UCR1_ICD. +#define BM_UART_UCR1_ICD (0x00000c00) //!< Bit mask for UART_UCR1_ICD. + +//! @brief Get value of UART_UCR1_ICD from a register value. +#define BG_UART_UCR1_ICD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_ICD) >> BP_UART_UCR1_ICD) + +//! @brief Format value for bitfield UART_UCR1_ICD. +#define BF_UART_UCR1_ICD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_ICD) & BM_UART_UCR1_ICD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ICD field to a new value. +#define BW_UART_UCR1_ICD(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_ICD) | BF_UART_UCR1_ICD(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field IDEN[12] (RW) + * + * Idle Condition Detected Interrupt Enable . Enables/Disables the IDLE bit to generate an interrupt + * ( interrupt_uart = 0). + * + * Values: + * - 0 - Disable the IDLE interrupt + * - 1 - Enable the IDLE interrupt + */ +//@{ +#define BP_UART_UCR1_IDEN (12) //!< Bit position for UART_UCR1_IDEN. +#define BM_UART_UCR1_IDEN (0x00001000) //!< Bit mask for UART_UCR1_IDEN. + +//! @brief Get value of UART_UCR1_IDEN from a register value. +#define BG_UART_UCR1_IDEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_IDEN) >> BP_UART_UCR1_IDEN) + +//! @brief Format value for bitfield UART_UCR1_IDEN. +#define BF_UART_UCR1_IDEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_IDEN) & BM_UART_UCR1_IDEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IDEN field to a new value. +#define BW_UART_UCR1_IDEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_IDEN) | BF_UART_UCR1_IDEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field TRDYEN[13] (RW) + * + * Transmitter Ready Interrupt Enable . Enables/Disables the transmitter Ready Interrupt (TRDY) when + * the transmitter has one or more slots available in the TxFIFO. The fill level in the TXFIFO at + * which an interrupt is generated is controlled by TxTL bits. When TRDYEN is negated, the + * transmitter ready interrupt is disabled. An interrupt will be issued as long as TRDYEN and TRDY + * are high even if the transmitter is not enabled. In general, user should enable the transmitter + * before enabling the TRDY interrupt. + * + * Values: + * - 0 - Disable the transmitter ready interrupt + * - 1 - Enable the transmitter ready interrupt + */ +//@{ +#define BP_UART_UCR1_TRDYEN (13) //!< Bit position for UART_UCR1_TRDYEN. +#define BM_UART_UCR1_TRDYEN (0x00002000) //!< Bit mask for UART_UCR1_TRDYEN. + +//! @brief Get value of UART_UCR1_TRDYEN from a register value. +#define BG_UART_UCR1_TRDYEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_TRDYEN) >> BP_UART_UCR1_TRDYEN) + +//! @brief Format value for bitfield UART_UCR1_TRDYEN. +#define BF_UART_UCR1_TRDYEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_TRDYEN) & BM_UART_UCR1_TRDYEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TRDYEN field to a new value. +#define BW_UART_UCR1_TRDYEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_TRDYEN) | BF_UART_UCR1_TRDYEN(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field ADBR[14] (RW) + * + * Automatic Detection of Baud Rate . Enables/Disables automatic baud rate detection. When the ADBR + * bit is set and the ADET bit is cleared, the receiver detects the incoming baud rate + * automatically. The ADET flag is set when the receiver verifies that the incoming baud rate is + * detected properly by detecting an ASCII character "A" or "a" (0x41 or 0x61). + * + * Values: + * - 0 - Disable automatic detection of baud rate + * - 1 - Enable automatic detection of baud rate + */ +//@{ +#define BP_UART_UCR1_ADBR (14) //!< Bit position for UART_UCR1_ADBR. +#define BM_UART_UCR1_ADBR (0x00004000) //!< Bit mask for UART_UCR1_ADBR. + +//! @brief Get value of UART_UCR1_ADBR from a register value. +#define BG_UART_UCR1_ADBR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_ADBR) >> BP_UART_UCR1_ADBR) + +//! @brief Format value for bitfield UART_UCR1_ADBR. +#define BF_UART_UCR1_ADBR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_ADBR) & BM_UART_UCR1_ADBR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADBR field to a new value. +#define BW_UART_UCR1_ADBR(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_ADBR) | BF_UART_UCR1_ADBR(v))) +#endif +//@} + +/*! @name Register UART_UCR1, field ADEN[15] (RW) + * + * Automatic Baud Rate Detection Interrupt Enable . Enables/Disables the automatic baud rate detect + * complete (ADET) bit to generate an interrupt ( interrupt_uart = 0). + * + * Values: + * - 0 - Disable the automatic baud rate detection interrupt + * - 1 - Enable the automatic baud rate detection interrupt + */ +//@{ +#define BP_UART_UCR1_ADEN (15) //!< Bit position for UART_UCR1_ADEN. +#define BM_UART_UCR1_ADEN (0x00008000) //!< Bit mask for UART_UCR1_ADEN. + +//! @brief Get value of UART_UCR1_ADEN from a register value. +#define BG_UART_UCR1_ADEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR1_ADEN) >> BP_UART_UCR1_ADEN) + +//! @brief Format value for bitfield UART_UCR1_ADEN. +#define BF_UART_UCR1_ADEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR1_ADEN) & BM_UART_UCR1_ADEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADEN field to a new value. +#define BW_UART_UCR1_ADEN(x, v) (HW_UART_UCR1_WR(x, (HW_UART_UCR1_RD(x) & ~BM_UART_UCR1_ADEN) | BF_UART_UCR1_ADEN(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UCR2 - UART Control Register 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UCR2 - UART Control Register 2 (RW) + * + * Reset value: 0x00000001 + */ +typedef union _hw_uart_ucr2 +{ + reg32_t U; + struct _hw_uart_ucr2_bitfields + { + unsigned SRST : 1; //!< [0] Software Reset . + unsigned RXEN : 1; //!< [1] Receiver Enable . + unsigned TXEN : 1; //!< [2] Transmitter Enable . + unsigned ATEN : 1; //!< [3] Aging Timer Enable . + unsigned RTSEN : 1; //!< [4] Request to Send Interrupt Enable. + unsigned WS : 1; //!< [5] Word Size . + unsigned STPB : 1; //!< [6] Stop . + unsigned PROE : 1; //!< [7] Parity Odd/Even . + unsigned PREN : 1; //!< [8] Parity Enable . + unsigned RTEC : 2; //!< [10:9] Request to Send Edge Control . + unsigned ESCEN : 1; //!< [11] Escape Enable . + unsigned CTS : 1; //!< [12] Clear to Send . + unsigned CTSC : 1; //!< [13] CTS Pin Control . + unsigned IRTS : 1; //!< [14] Ignore RTS Pin . + unsigned ESCI : 1; //!< [15] Escape Sequence Interrupt Enable . + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_ucr2_t; +#endif + +/*! + * @name Constants and macros for entire UART_UCR2 register + */ +//@{ +#define HW_UART_UCR2_ADDR(x) (REGS_UART_BASE(x) + 0x84) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UCR2(x) (*(volatile hw_uart_ucr2_t *) HW_UART_UCR2_ADDR(x)) +#define HW_UART_UCR2_RD(x) (HW_UART_UCR2(x).U) +#define HW_UART_UCR2_WR(x, v) (HW_UART_UCR2(x).U = (v)) +#define HW_UART_UCR2_SET(x, v) (HW_UART_UCR2_WR(x, HW_UART_UCR2_RD(x) | (v))) +#define HW_UART_UCR2_CLR(x, v) (HW_UART_UCR2_WR(x, HW_UART_UCR2_RD(x) & ~(v))) +#define HW_UART_UCR2_TOG(x, v) (HW_UART_UCR2_WR(x, HW_UART_UCR2_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UCR2 bitfields + */ + +/*! @name Register UART_UCR2, field SRST[0] (RW) + * + * Software Reset . Once the software writes 0 to SRST , the software reset remains active for 4 + * module_clock cycles before the hardware deasserts SRST . The software can only write 0 to SRST . + * Writing 1 to SRST is ignored. + * + * Values: + * - 0 - Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , + * URXD, UTXD and UTS[6-3]. + * - 1 - No reset + */ +//@{ +#define BP_UART_UCR2_SRST (0) //!< Bit position for UART_UCR2_SRST. +#define BM_UART_UCR2_SRST (0x00000001) //!< Bit mask for UART_UCR2_SRST. + +//! @brief Get value of UART_UCR2_SRST from a register value. +#define BG_UART_UCR2_SRST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_SRST) >> BP_UART_UCR2_SRST) + +//! @brief Format value for bitfield UART_UCR2_SRST. +#define BF_UART_UCR2_SRST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_SRST) & BM_UART_UCR2_SRST) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SRST field to a new value. +#define BW_UART_UCR2_SRST(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_SRST) | BF_UART_UCR2_SRST(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field RXEN[1] (RW) + * + * Receiver Enable . Enables/Disables the receiver. When the receiver is enabled, if the RXD input + * is already low, the receiver does not recognize BREAK characters, because it requires a valid + * 1-to-0 transition before it can accept any character. + * + * Values: + * - 0 - Disable the receiver + * - 1 - Enable the receiver + */ +//@{ +#define BP_UART_UCR2_RXEN (1) //!< Bit position for UART_UCR2_RXEN. +#define BM_UART_UCR2_RXEN (0x00000002) //!< Bit mask for UART_UCR2_RXEN. + +//! @brief Get value of UART_UCR2_RXEN from a register value. +#define BG_UART_UCR2_RXEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_RXEN) >> BP_UART_UCR2_RXEN) + +//! @brief Format value for bitfield UART_UCR2_RXEN. +#define BF_UART_UCR2_RXEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_RXEN) & BM_UART_UCR2_RXEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXEN field to a new value. +#define BW_UART_UCR2_RXEN(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_RXEN) | BF_UART_UCR2_RXEN(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field TXEN[2] (RW) + * + * Transmitter Enable . Enables/Disables the transmitter. When TXEN is negated the transmitter is + * disabled and idle. When the UARTEN and TXEN bits are set the transmitter is enabled. If TXEN is + * negated in the middle of a transmission, the UART disables the transmitter immediately, and + * starts marking 1s. The transmitter FIFO cannot be written when this bit is cleared. + * + * Values: + * - 0 - Disable the transmitter + * - 1 - Enable the transmitter + */ +//@{ +#define BP_UART_UCR2_TXEN (2) //!< Bit position for UART_UCR2_TXEN. +#define BM_UART_UCR2_TXEN (0x00000004) //!< Bit mask for UART_UCR2_TXEN. + +//! @brief Get value of UART_UCR2_TXEN from a register value. +#define BG_UART_UCR2_TXEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_TXEN) >> BP_UART_UCR2_TXEN) + +//! @brief Format value for bitfield UART_UCR2_TXEN. +#define BF_UART_UCR2_TXEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_TXEN) & BM_UART_UCR2_TXEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXEN field to a new value. +#define BW_UART_UCR2_TXEN(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_TXEN) | BF_UART_UCR2_TXEN(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field ATEN[3] (RW) + * + * Aging Timer Enable . This bit is used to enable the aging timer interrupt (triggered with AGTIM) + * + * Values: + * - 0 - AGTIM interrupt disabled + * - 1 - AGTIM interrupt enabled + */ +//@{ +#define BP_UART_UCR2_ATEN (3) //!< Bit position for UART_UCR2_ATEN. +#define BM_UART_UCR2_ATEN (0x00000008) //!< Bit mask for UART_UCR2_ATEN. + +//! @brief Get value of UART_UCR2_ATEN from a register value. +#define BG_UART_UCR2_ATEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_ATEN) >> BP_UART_UCR2_ATEN) + +//! @brief Format value for bitfield UART_UCR2_ATEN. +#define BF_UART_UCR2_ATEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_ATEN) & BM_UART_UCR2_ATEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ATEN field to a new value. +#define BW_UART_UCR2_ATEN(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_ATEN) | BF_UART_UCR2_ATEN(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field RTSEN[4] (RW) + * + * Request to Send Interrupt Enable. Controls the RTS edge sensitive interrupt. When RTSEN is + * asserted and the programmed edge is detected on the RTS pin (the RTSF bit is asserted), an + * interrupt will be generated on the interrupt_uart pin. (See .) + * + * Values: + * - 0 - Disable request to send interrupt + * - 1 - Enable request to send interrupt + */ +//@{ +#define BP_UART_UCR2_RTSEN (4) //!< Bit position for UART_UCR2_RTSEN. +#define BM_UART_UCR2_RTSEN (0x00000010) //!< Bit mask for UART_UCR2_RTSEN. + +//! @brief Get value of UART_UCR2_RTSEN from a register value. +#define BG_UART_UCR2_RTSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_RTSEN) >> BP_UART_UCR2_RTSEN) + +//! @brief Format value for bitfield UART_UCR2_RTSEN. +#define BF_UART_UCR2_RTSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_RTSEN) & BM_UART_UCR2_RTSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTSEN field to a new value. +#define BW_UART_UCR2_RTSEN(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_RTSEN) | BF_UART_UCR2_RTSEN(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field WS[5] (RW) + * + * Word Size . Controls the character length. When WS is high, the transmitter and receiver are in + * 8-bit mode. When WS is low, they are in 7-bit mode. The transmitter ignores bit 7 and the + * receiver sets bit 7 to 0. WS can be changed in-between transmission (reception) of characters, + * however not when a transmission (reception) is in progress, in which case the length of the + * current character being transmitted (received) is unpredictable. + * + * Values: + * - 0 - 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + * - 1 - 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + */ +//@{ +#define BP_UART_UCR2_WS (5) //!< Bit position for UART_UCR2_WS. +#define BM_UART_UCR2_WS (0x00000020) //!< Bit mask for UART_UCR2_WS. + +//! @brief Get value of UART_UCR2_WS from a register value. +#define BG_UART_UCR2_WS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_WS) >> BP_UART_UCR2_WS) + +//! @brief Format value for bitfield UART_UCR2_WS. +#define BF_UART_UCR2_WS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_WS) & BM_UART_UCR2_WS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WS field to a new value. +#define BW_UART_UCR2_WS(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_WS) | BF_UART_UCR2_WS(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field STPB[6] (RW) + * + * Stop . Controls the number of stop bits after a character. When STPB is low, 1 stop bit is sent. + * When STPB is high, 2 stop bits are sent. STPB also affects the receiver. + * + * Values: + * - 0 - The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + * - 1 - The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + */ +//@{ +#define BP_UART_UCR2_STPB (6) //!< Bit position for UART_UCR2_STPB. +#define BM_UART_UCR2_STPB (0x00000040) //!< Bit mask for UART_UCR2_STPB. + +//! @brief Get value of UART_UCR2_STPB from a register value. +#define BG_UART_UCR2_STPB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_STPB) >> BP_UART_UCR2_STPB) + +//! @brief Format value for bitfield UART_UCR2_STPB. +#define BF_UART_UCR2_STPB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_STPB) & BM_UART_UCR2_STPB) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the STPB field to a new value. +#define BW_UART_UCR2_STPB(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_STPB) | BF_UART_UCR2_STPB(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field PROE[7] (RW) + * + * Parity Odd/Even . Controls the sense of the parity generator and checker. When PROE is high, odd + * parity is generated and expected. When PROE is low, even parity is generated and expected. PROE + * has no function if PREN is low. + * + * Values: + * - 0 - Even parity + * - 1 - Odd parity + */ +//@{ +#define BP_UART_UCR2_PROE (7) //!< Bit position for UART_UCR2_PROE. +#define BM_UART_UCR2_PROE (0x00000080) //!< Bit mask for UART_UCR2_PROE. + +//! @brief Get value of UART_UCR2_PROE from a register value. +#define BG_UART_UCR2_PROE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_PROE) >> BP_UART_UCR2_PROE) + +//! @brief Format value for bitfield UART_UCR2_PROE. +#define BF_UART_UCR2_PROE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_PROE) & BM_UART_UCR2_PROE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PROE field to a new value. +#define BW_UART_UCR2_PROE(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_PROE) | BF_UART_UCR2_PROE(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field PREN[8] (RW) + * + * Parity Enable . Enables/Disables the parity generator in the transmitter and parity checker in + * the receiver. When PREN is asserted, the parity generator and checker are enabled, and disabled + * when PREN is negated. + * + * Values: + * - 0 - Disable parity generator and checker + * - 1 - Enable parity generator and checker + */ +//@{ +#define BP_UART_UCR2_PREN (8) //!< Bit position for UART_UCR2_PREN. +#define BM_UART_UCR2_PREN (0x00000100) //!< Bit mask for UART_UCR2_PREN. + +//! @brief Get value of UART_UCR2_PREN from a register value. +#define BG_UART_UCR2_PREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_PREN) >> BP_UART_UCR2_PREN) + +//! @brief Format value for bitfield UART_UCR2_PREN. +#define BF_UART_UCR2_PREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_PREN) & BM_UART_UCR2_PREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PREN field to a new value. +#define BW_UART_UCR2_PREN(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_PREN) | BF_UART_UCR2_PREN(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field RTEC[10:9] (RW) + * + * Request to Send Edge Control . Selects the edge that triggers the RTS interrupt. This has no + * effect on the RTS delta interrupt. RTEC has an effect only when RTSEN = 1 (see ). + * + * Values: + * - 00 - Trigger interrupt on a rising edge + * - 01 - Trigger interrupt on a falling edge + * - 1X - Trigger interrupt on any edge + */ +//@{ +#define BP_UART_UCR2_RTEC (9) //!< Bit position for UART_UCR2_RTEC. +#define BM_UART_UCR2_RTEC (0x00000600) //!< Bit mask for UART_UCR2_RTEC. + +//! @brief Get value of UART_UCR2_RTEC from a register value. +#define BG_UART_UCR2_RTEC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_RTEC) >> BP_UART_UCR2_RTEC) + +//! @brief Format value for bitfield UART_UCR2_RTEC. +#define BF_UART_UCR2_RTEC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_RTEC) & BM_UART_UCR2_RTEC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTEC field to a new value. +#define BW_UART_UCR2_RTEC(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_RTEC) | BF_UART_UCR2_RTEC(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field ESCEN[11] (RW) + * + * Escape Enable . Enables/Disables the escape sequence detection logic. + * + * Values: + * - 0 - Disable escape sequence detection + * - 1 - Enable escape sequence detection + */ +//@{ +#define BP_UART_UCR2_ESCEN (11) //!< Bit position for UART_UCR2_ESCEN. +#define BM_UART_UCR2_ESCEN (0x00000800) //!< Bit mask for UART_UCR2_ESCEN. + +//! @brief Get value of UART_UCR2_ESCEN from a register value. +#define BG_UART_UCR2_ESCEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_ESCEN) >> BP_UART_UCR2_ESCEN) + +//! @brief Format value for bitfield UART_UCR2_ESCEN. +#define BF_UART_UCR2_ESCEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_ESCEN) & BM_UART_UCR2_ESCEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ESCEN field to a new value. +#define BW_UART_UCR2_ESCEN(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_ESCEN) | BF_UART_UCR2_ESCEN(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field CTS[12] (RW) + * + * Clear to Send . Controls the CTS pin when the CTSC bit is negated. CTS has no function when CTSC + * is asserted. + * + * Values: + * - 0 - The CTS pin is high (inactive) + * - 1 - The CTS pin is low (active) + */ +//@{ +#define BP_UART_UCR2_CTS (12) //!< Bit position for UART_UCR2_CTS. +#define BM_UART_UCR2_CTS (0x00001000) //!< Bit mask for UART_UCR2_CTS. + +//! @brief Get value of UART_UCR2_CTS from a register value. +#define BG_UART_UCR2_CTS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_CTS) >> BP_UART_UCR2_CTS) + +//! @brief Format value for bitfield UART_UCR2_CTS. +#define BF_UART_UCR2_CTS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_CTS) & BM_UART_UCR2_CTS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CTS field to a new value. +#define BW_UART_UCR2_CTS(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_CTS) | BF_UART_UCR2_CTS(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field CTSC[13] (RW) + * + * CTS Pin Control . Controls the operation of the CTS output pin. When CTSC is asserted, the CTS + * output pin is controlled by the receiver. When the RxFIFO is filled to the level of the + * programmed trigger level and the start bit of the overflowing character (TRIGGER LEVEL + 1) is + * validated, the CTS output pin is negated to indicate to the far-end transmitter to stop + * transmitting. When the trigger level is programmed for less than 32, the receiver continues to + * receive data until the RxFIFO is full. When the CTSC bit is negated, the CTS output pin is + * controlled by the CTS bit. On reset, because CTSC is cleared to 0, the CTS pin is controlled by + * the CTS bit, which again is cleared to 0 on reset. This means that on reset the CTS signal is + * negated. + * + * Values: + * - 0 - The CTS pin is controlled by the CTS bit + * - 1 - The CTS pin is controlled by the receiver + */ +//@{ +#define BP_UART_UCR2_CTSC (13) //!< Bit position for UART_UCR2_CTSC. +#define BM_UART_UCR2_CTSC (0x00002000) //!< Bit mask for UART_UCR2_CTSC. + +//! @brief Get value of UART_UCR2_CTSC from a register value. +#define BG_UART_UCR2_CTSC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_CTSC) >> BP_UART_UCR2_CTSC) + +//! @brief Format value for bitfield UART_UCR2_CTSC. +#define BF_UART_UCR2_CTSC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_CTSC) & BM_UART_UCR2_CTSC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CTSC field to a new value. +#define BW_UART_UCR2_CTSC(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_CTSC) | BF_UART_UCR2_CTSC(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field IRTS[14] (RW) + * + * Ignore RTS Pin . Forces the RTS input signal presented to the transmitter to always be asserted + * (set to low), effectively ignoring the external pin. When in this mode, the RTS pin serves as a + * general purpose input. + * + * Values: + * - 0 - Transmit only when the RTS pin is asserted + * - 1 - Ignore the RTS pin + */ +//@{ +#define BP_UART_UCR2_IRTS (14) //!< Bit position for UART_UCR2_IRTS. +#define BM_UART_UCR2_IRTS (0x00004000) //!< Bit mask for UART_UCR2_IRTS. + +//! @brief Get value of UART_UCR2_IRTS from a register value. +#define BG_UART_UCR2_IRTS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_IRTS) >> BP_UART_UCR2_IRTS) + +//! @brief Format value for bitfield UART_UCR2_IRTS. +#define BF_UART_UCR2_IRTS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_IRTS) & BM_UART_UCR2_IRTS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IRTS field to a new value. +#define BW_UART_UCR2_IRTS(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_IRTS) | BF_UART_UCR2_IRTS(v))) +#endif +//@} + +/*! @name Register UART_UCR2, field ESCI[15] (RW) + * + * Escape Sequence Interrupt Enable . Enables/Disables the ESCF bit to generate an interrupt. + * + * Values: + * - 0 - Disable the escape sequence interrupt + * - 1 - Enable the escape sequence interrupt + */ +//@{ +#define BP_UART_UCR2_ESCI (15) //!< Bit position for UART_UCR2_ESCI. +#define BM_UART_UCR2_ESCI (0x00008000) //!< Bit mask for UART_UCR2_ESCI. + +//! @brief Get value of UART_UCR2_ESCI from a register value. +#define BG_UART_UCR2_ESCI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR2_ESCI) >> BP_UART_UCR2_ESCI) + +//! @brief Format value for bitfield UART_UCR2_ESCI. +#define BF_UART_UCR2_ESCI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR2_ESCI) & BM_UART_UCR2_ESCI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ESCI field to a new value. +#define BW_UART_UCR2_ESCI(x, v) (HW_UART_UCR2_WR(x, (HW_UART_UCR2_RD(x) & ~BM_UART_UCR2_ESCI) | BF_UART_UCR2_ESCI(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UCR3 - UART Control Register 3 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UCR3 - UART Control Register 3 (RW) + * + * Reset value: 0x00000700 + */ +typedef union _hw_uart_ucr3 +{ + reg32_t U; + struct _hw_uart_ucr3_bitfields + { + unsigned ACIEN : 1; //!< [0] Autobaud Counter Interrupt Enable. + unsigned INVT : 1; //!< [1] Invert TXD output in RS-232/RS-485 mode, set TXD active level in IrDA mode. + unsigned RXDMUXSEL : 1; //!< [2] RXD Muxed Input Selected. + unsigned DTRDEN : 1; //!< [3] Data Terminal Ready Delta Enable . + unsigned AWAKEN : 1; //!< [4] Asynchronous WAKE Interrupt Enable. + unsigned AIRINTEN : 1; //!< [5] Asynchronous IR WAKE Interrupt Enable. + unsigned RXDSEN : 1; //!< [6] Receive Status Interrupt Enable. + unsigned ADNIMP : 1; //!< [7] Autobaud Detection Not Improved-. + unsigned RI : 1; //!< [8] Ring Indicator . + unsigned DCD : 1; //!< [9] Data Carrier Detect . + unsigned DSR : 1; //!< [10] Data Set Ready . + unsigned FRAERREN : 1; //!< [11] Frame Error Interrupt Enable. + unsigned PARERREN : 1; //!< [12] Parity Error Interrupt Enable. + unsigned DTREN : 1; //!< [13] Data Terminal Ready Interrupt Enable . + unsigned DPEC : 2; //!< [15:14] DTR/DSR Interrupt Edge Control . + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_ucr3_t; +#endif + +/*! + * @name Constants and macros for entire UART_UCR3 register + */ +//@{ +#define HW_UART_UCR3_ADDR(x) (REGS_UART_BASE(x) + 0x88) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UCR3(x) (*(volatile hw_uart_ucr3_t *) HW_UART_UCR3_ADDR(x)) +#define HW_UART_UCR3_RD(x) (HW_UART_UCR3(x).U) +#define HW_UART_UCR3_WR(x, v) (HW_UART_UCR3(x).U = (v)) +#define HW_UART_UCR3_SET(x, v) (HW_UART_UCR3_WR(x, HW_UART_UCR3_RD(x) | (v))) +#define HW_UART_UCR3_CLR(x, v) (HW_UART_UCR3_WR(x, HW_UART_UCR3_RD(x) & ~(v))) +#define HW_UART_UCR3_TOG(x, v) (HW_UART_UCR3_WR(x, HW_UART_UCR3_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UCR3 bitfields + */ + +/*! @name Register UART_UCR3, field ACIEN[0] (RW) + * + * Autobaud Counter Interrupt Enable. This bit is used to enable the autobaud counter stopped + * interrupt (triggered with ACST (USR2[11]). + * + * Values: + * - 0 - ACST interrupt disabled + * - 1 - ACST interrupt enabled + */ +//@{ +#define BP_UART_UCR3_ACIEN (0) //!< Bit position for UART_UCR3_ACIEN. +#define BM_UART_UCR3_ACIEN (0x00000001) //!< Bit mask for UART_UCR3_ACIEN. + +//! @brief Get value of UART_UCR3_ACIEN from a register value. +#define BG_UART_UCR3_ACIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_ACIEN) >> BP_UART_UCR3_ACIEN) + +//! @brief Format value for bitfield UART_UCR3_ACIEN. +#define BF_UART_UCR3_ACIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_ACIEN) & BM_UART_UCR3_ACIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ACIEN field to a new value. +#define BW_UART_UCR3_ACIEN(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_ACIEN) | BF_UART_UCR3_ACIEN(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field INVT[1] (RW) + * + * Invert TXD output in RS-232/RS-485 mode, set TXD active level in IrDA mode. In RS232/RS-485 + * mode(UMCR[0] = 1), if this bit is set to 1, the TXD output is inverted before transmitted. In + * IrDA mode , when INVT is cleared, the infrared logic block transmits a positive IR 3/16 pulse for + * all 0s and 0s are transmitted for 1s. When INVT is set (INVT = 1), the infrared logic block + * transmits an active low or negative infrared 3/16 pulse for all 0s and 1s are transmitted for 1s. + * + * Values: + * - 0 - TXD is not inverted + * - 0 - TXD Active low transmission + * - 1 - TXD is inverted + * - 1 - TXD Active high transmission + */ +//@{ +#define BP_UART_UCR3_INVT (1) //!< Bit position for UART_UCR3_INVT. +#define BM_UART_UCR3_INVT (0x00000002) //!< Bit mask for UART_UCR3_INVT. + +//! @brief Get value of UART_UCR3_INVT from a register value. +#define BG_UART_UCR3_INVT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_INVT) >> BP_UART_UCR3_INVT) + +//! @brief Format value for bitfield UART_UCR3_INVT. +#define BF_UART_UCR3_INVT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_INVT) & BM_UART_UCR3_INVT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the INVT field to a new value. +#define BW_UART_UCR3_INVT(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_INVT) | BF_UART_UCR3_INVT(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field RXDMUXSEL[2] (RW) + * + * RXD Muxed Input Selected. Selects proper input pins for serial and Infrared input signal. In this + * chip, UARTs are used in MUXED mode, so that this bit should always be set. + */ +//@{ +#define BP_UART_UCR3_RXDMUXSEL (2) //!< Bit position for UART_UCR3_RXDMUXSEL. +#define BM_UART_UCR3_RXDMUXSEL (0x00000004) //!< Bit mask for UART_UCR3_RXDMUXSEL. + +//! @brief Get value of UART_UCR3_RXDMUXSEL from a register value. +#define BG_UART_UCR3_RXDMUXSEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_RXDMUXSEL) >> BP_UART_UCR3_RXDMUXSEL) + +//! @brief Format value for bitfield UART_UCR3_RXDMUXSEL. +#define BF_UART_UCR3_RXDMUXSEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_RXDMUXSEL) & BM_UART_UCR3_RXDMUXSEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXDMUXSEL field to a new value. +#define BW_UART_UCR3_RXDMUXSEL(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_RXDMUXSEL) | BF_UART_UCR3_RXDMUXSEL(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field DTRDEN[3] (RW) + * + * Data Terminal Ready Delta Enable . Enables / Disables the asynchronous DTRD interrupt. When + * DTRDEN is asserted and an edge (rising or falling) is detected on DTR (in DCE mode) or on DSR (in + * DTE mode), then an interrupt is generated. + * + * Values: + * - 0 - Disable DTRD interrupt + * - 1 - Enable DTRD interrupt + */ +//@{ +#define BP_UART_UCR3_DTRDEN (3) //!< Bit position for UART_UCR3_DTRDEN. +#define BM_UART_UCR3_DTRDEN (0x00000008) //!< Bit mask for UART_UCR3_DTRDEN. + +//! @brief Get value of UART_UCR3_DTRDEN from a register value. +#define BG_UART_UCR3_DTRDEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_DTRDEN) >> BP_UART_UCR3_DTRDEN) + +//! @brief Format value for bitfield UART_UCR3_DTRDEN. +#define BF_UART_UCR3_DTRDEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_DTRDEN) & BM_UART_UCR3_DTRDEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTRDEN field to a new value. +#define BW_UART_UCR3_DTRDEN(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_DTRDEN) | BF_UART_UCR3_DTRDEN(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field AWAKEN[4] (RW) + * + * Asynchronous WAKE Interrupt Enable. Controls the asynchronous WAKE interrupt. An interrupt is + * generated when AWAKEN is asserted and a falling edge is detected on the RXD pin. + * + * Values: + * - 0 - Disable the AWAKE interrupt + * - 1 - Enable the AWAKE interrupt + */ +//@{ +#define BP_UART_UCR3_AWAKEN (4) //!< Bit position for UART_UCR3_AWAKEN. +#define BM_UART_UCR3_AWAKEN (0x00000010) //!< Bit mask for UART_UCR3_AWAKEN. + +//! @brief Get value of UART_UCR3_AWAKEN from a register value. +#define BG_UART_UCR3_AWAKEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_AWAKEN) >> BP_UART_UCR3_AWAKEN) + +//! @brief Format value for bitfield UART_UCR3_AWAKEN. +#define BF_UART_UCR3_AWAKEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_AWAKEN) & BM_UART_UCR3_AWAKEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AWAKEN field to a new value. +#define BW_UART_UCR3_AWAKEN(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_AWAKEN) | BF_UART_UCR3_AWAKEN(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field AIRINTEN[5] (RW) + * + * Asynchronous IR WAKE Interrupt Enable. Controls the asynchronous IR WAKE interrupt. An interrupt + * is generated when AIRINTEN is asserted and a pulse is detected on the RXD pin. + * + * Values: + * - 0 - Disable the AIRINT interrupt + * - 1 - Enable the AIRINT interrupt + */ +//@{ +#define BP_UART_UCR3_AIRINTEN (5) //!< Bit position for UART_UCR3_AIRINTEN. +#define BM_UART_UCR3_AIRINTEN (0x00000020) //!< Bit mask for UART_UCR3_AIRINTEN. + +//! @brief Get value of UART_UCR3_AIRINTEN from a register value. +#define BG_UART_UCR3_AIRINTEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_AIRINTEN) >> BP_UART_UCR3_AIRINTEN) + +//! @brief Format value for bitfield UART_UCR3_AIRINTEN. +#define BF_UART_UCR3_AIRINTEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_AIRINTEN) & BM_UART_UCR3_AIRINTEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AIRINTEN field to a new value. +#define BW_UART_UCR3_AIRINTEN(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_AIRINTEN) | BF_UART_UCR3_AIRINTEN(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field RXDSEN[6] (RW) + * + * Receive Status Interrupt Enable. Controls the receive status interrupt ( interrupt_uart ). When + * this bit is enabled and RXDS status bit is set, the interrupt interrupt_uart will be generated. + * + * Values: + * - 0 - Disable the RXDS interrupt + * - 1 - Enable the RXDS interrupt + */ +//@{ +#define BP_UART_UCR3_RXDSEN (6) //!< Bit position for UART_UCR3_RXDSEN. +#define BM_UART_UCR3_RXDSEN (0x00000040) //!< Bit mask for UART_UCR3_RXDSEN. + +//! @brief Get value of UART_UCR3_RXDSEN from a register value. +#define BG_UART_UCR3_RXDSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_RXDSEN) >> BP_UART_UCR3_RXDSEN) + +//! @brief Format value for bitfield UART_UCR3_RXDSEN. +#define BF_UART_UCR3_RXDSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_RXDSEN) & BM_UART_UCR3_RXDSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXDSEN field to a new value. +#define BW_UART_UCR3_RXDSEN(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_RXDSEN) | BF_UART_UCR3_RXDSEN(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field ADNIMP[7] (RW) + * + * Autobaud Detection Not Improved-. Disables new features of autobaud detection (See , for more + * details). + * + * Values: + * - 0 - Autobaud detection new features selected + * - 1 - Keep old autobaud detection mechanism + */ +//@{ +#define BP_UART_UCR3_ADNIMP (7) //!< Bit position for UART_UCR3_ADNIMP. +#define BM_UART_UCR3_ADNIMP (0x00000080) //!< Bit mask for UART_UCR3_ADNIMP. + +//! @brief Get value of UART_UCR3_ADNIMP from a register value. +#define BG_UART_UCR3_ADNIMP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_ADNIMP) >> BP_UART_UCR3_ADNIMP) + +//! @brief Format value for bitfield UART_UCR3_ADNIMP. +#define BF_UART_UCR3_ADNIMP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_ADNIMP) & BM_UART_UCR3_ADNIMP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADNIMP field to a new value. +#define BW_UART_UCR3_ADNIMP(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_ADNIMP) | BF_UART_UCR3_ADNIMP(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field RI[8] (RW) + * + * Ring Indicator . In DCE mode this bit is used by software to control the RI output pin for the + * modem interface. In DTE mode, when this bit is set, it will enable the status bit RIDELT (USR2 + * (10)) to cause an interrupt. + * + * Values: + * - 0 - RI pin is logic zero (DCE mode) + * - 0 - RIDELT interrupt disabled (DTE mode) + * - 1 - RI pin is logic one (DCE mode) + * - 1 - RIDELT interrupt enabled (DTE mode) + */ +//@{ +#define BP_UART_UCR3_RI (8) //!< Bit position for UART_UCR3_RI. +#define BM_UART_UCR3_RI (0x00000100) //!< Bit mask for UART_UCR3_RI. + +//! @brief Get value of UART_UCR3_RI from a register value. +#define BG_UART_UCR3_RI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_RI) >> BP_UART_UCR3_RI) + +//! @brief Format value for bitfield UART_UCR3_RI. +#define BF_UART_UCR3_RI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_RI) & BM_UART_UCR3_RI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RI field to a new value. +#define BW_UART_UCR3_RI(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_RI) | BF_UART_UCR3_RI(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field DCD[9] (RW) + * + * Data Carrier Detect . In DCE mode this bit is used by software to control the DCD output pin for + * the modem interface. In DTE mode, when this bit is set, it will enable the status bit DCDDELT + * (USR2 (6)) to cause an interrupt. + * + * Values: + * - 0 - DCD pin is logic zero (DCE mode) + * - 0 - DCDDELT interrupt disabled (DTE mode) + * - 1 - DCD pin is logic one (DCE mode) + * - 1 - DCDDELT interrupt enabled (DTE mode) + */ +//@{ +#define BP_UART_UCR3_DCD (9) //!< Bit position for UART_UCR3_DCD. +#define BM_UART_UCR3_DCD (0x00000200) //!< Bit mask for UART_UCR3_DCD. + +//! @brief Get value of UART_UCR3_DCD from a register value. +#define BG_UART_UCR3_DCD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_DCD) >> BP_UART_UCR3_DCD) + +//! @brief Format value for bitfield UART_UCR3_DCD. +#define BF_UART_UCR3_DCD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_DCD) & BM_UART_UCR3_DCD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DCD field to a new value. +#define BW_UART_UCR3_DCD(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_DCD) | BF_UART_UCR3_DCD(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field DSR[10] (RW) + * + * Data Set Ready . This bit is used by software to control the DSR/DTR output pin for the modem + * interface. In DCE mode it applies to DSR and in DTE mode it applies to DTR . + * + * Values: + * - 0 - DSR/ DTR pin is logic zero + * - 1 - DSR/ DTR pin is logic one + */ +//@{ +#define BP_UART_UCR3_DSR (10) //!< Bit position for UART_UCR3_DSR. +#define BM_UART_UCR3_DSR (0x00000400) //!< Bit mask for UART_UCR3_DSR. + +//! @brief Get value of UART_UCR3_DSR from a register value. +#define BG_UART_UCR3_DSR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_DSR) >> BP_UART_UCR3_DSR) + +//! @brief Format value for bitfield UART_UCR3_DSR. +#define BF_UART_UCR3_DSR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_DSR) & BM_UART_UCR3_DSR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DSR field to a new value. +#define BW_UART_UCR3_DSR(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_DSR) | BF_UART_UCR3_DSR(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field FRAERREN[11] (RW) + * + * Frame Error Interrupt Enable. Enables/Disables the interrupt. When asserted, FRAERREN causes the + * FRAMERR bit to generate an interrupt. + * + * Values: + * - 0 - Disable the frame error interrupt + * - 1 - Enable the frame error interrupt + */ +//@{ +#define BP_UART_UCR3_FRAERREN (11) //!< Bit position for UART_UCR3_FRAERREN. +#define BM_UART_UCR3_FRAERREN (0x00000800) //!< Bit mask for UART_UCR3_FRAERREN. + +//! @brief Get value of UART_UCR3_FRAERREN from a register value. +#define BG_UART_UCR3_FRAERREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_FRAERREN) >> BP_UART_UCR3_FRAERREN) + +//! @brief Format value for bitfield UART_UCR3_FRAERREN. +#define BF_UART_UCR3_FRAERREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_FRAERREN) & BM_UART_UCR3_FRAERREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FRAERREN field to a new value. +#define BW_UART_UCR3_FRAERREN(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_FRAERREN) | BF_UART_UCR3_FRAERREN(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field PARERREN[12] (RW) + * + * Parity Error Interrupt Enable. Enables/Disables the interrupt. When asserted, PARERREN causes the + * PARITYERR bit to generate an interrupt. + * + * Values: + * - 0 - Disable the parity error interrupt + * - 1 - Enable the parity error interrupt + */ +//@{ +#define BP_UART_UCR3_PARERREN (12) //!< Bit position for UART_UCR3_PARERREN. +#define BM_UART_UCR3_PARERREN (0x00001000) //!< Bit mask for UART_UCR3_PARERREN. + +//! @brief Get value of UART_UCR3_PARERREN from a register value. +#define BG_UART_UCR3_PARERREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_PARERREN) >> BP_UART_UCR3_PARERREN) + +//! @brief Format value for bitfield UART_UCR3_PARERREN. +#define BF_UART_UCR3_PARERREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_PARERREN) & BM_UART_UCR3_PARERREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PARERREN field to a new value. +#define BW_UART_UCR3_PARERREN(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_PARERREN) | BF_UART_UCR3_PARERREN(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field DTREN[13] (RW) + * + * Data Terminal Ready Interrupt Enable . When this bit is set, it will enable the status bit DTRF + * (USR2 [13]) (DTR/DSR edge sensitive interrupt) to cause an interrupt. + * + * Values: + * - 0 - Data Terminal Ready Interrupt Disabled + * - 1 - Data Terminal Ready Interrupt Enabled + */ +//@{ +#define BP_UART_UCR3_DTREN (13) //!< Bit position for UART_UCR3_DTREN. +#define BM_UART_UCR3_DTREN (0x00002000) //!< Bit mask for UART_UCR3_DTREN. + +//! @brief Get value of UART_UCR3_DTREN from a register value. +#define BG_UART_UCR3_DTREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_DTREN) >> BP_UART_UCR3_DTREN) + +//! @brief Format value for bitfield UART_UCR3_DTREN. +#define BF_UART_UCR3_DTREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_DTREN) & BM_UART_UCR3_DTREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTREN field to a new value. +#define BW_UART_UCR3_DTREN(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_DTREN) | BF_UART_UCR3_DTREN(v))) +#endif +//@} + +/*! @name Register UART_UCR3, field DPEC[15:14] (RW) + * + * DTR/DSR Interrupt Edge Control . These bits control the edge of DTR (DCE) or DSR (DTE) on which + * an interrupt will be generated. An interrupt will only be generated if the DTREN bit is set. + * + * Values: + * - 00 - interrupt generated on rising edge + * - 01 - interrupt generated on falling edge + * - 1X - interrupt generated on either edge + */ +//@{ +#define BP_UART_UCR3_DPEC (14) //!< Bit position for UART_UCR3_DPEC. +#define BM_UART_UCR3_DPEC (0x0000c000) //!< Bit mask for UART_UCR3_DPEC. + +//! @brief Get value of UART_UCR3_DPEC from a register value. +#define BG_UART_UCR3_DPEC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR3_DPEC) >> BP_UART_UCR3_DPEC) + +//! @brief Format value for bitfield UART_UCR3_DPEC. +#define BF_UART_UCR3_DPEC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR3_DPEC) & BM_UART_UCR3_DPEC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DPEC field to a new value. +#define BW_UART_UCR3_DPEC(x, v) (HW_UART_UCR3_WR(x, (HW_UART_UCR3_RD(x) & ~BM_UART_UCR3_DPEC) | BF_UART_UCR3_DPEC(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UCR4 - UART Control Register 4 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UCR4 - UART Control Register 4 (RW) + * + * Reset value: 0x00008000 + */ +typedef union _hw_uart_ucr4 +{ + reg32_t U; + struct _hw_uart_ucr4_bitfields + { + unsigned DREN : 1; //!< [0] Receive Data Ready Interrupt Enable . + unsigned OREN : 1; //!< [1] Receiver Overrun Interrupt Enable . + unsigned BKEN : 1; //!< [2] BREAK Condition Detected Interrupt Enable . + unsigned TCEN : 1; //!< [3] Transmit Complete Interrupt Enable . + unsigned LPBYP : 1; //!< [4] Low Power Bypass . + unsigned IRSC : 1; //!< [5] IR Special Case . + unsigned IDDMAEN : 1; //!< [6] DMA IDLE Condition Detected Interrupt Enable Enables/Disables the receive DMA request dma_req_rx for the IDLE interrupt (triggered with IDLE flag in USR2[12]). + unsigned WKEN : 1; //!< [7] WAKE Interrupt Enable . + unsigned ENIRI : 1; //!< [8] Serial Infrared Interrupt Enable . + unsigned INVR : 1; //!< [9] Invert RXD input in RS-232/RS-485 Mode, d etermine RXD input logic level being sampled in In IrDA mode. + unsigned CTSTL : 6; //!< [15:10] CTS Trigger Level . + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_ucr4_t; +#endif + +/*! + * @name Constants and macros for entire UART_UCR4 register + */ +//@{ +#define HW_UART_UCR4_ADDR(x) (REGS_UART_BASE(x) + 0x8c) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UCR4(x) (*(volatile hw_uart_ucr4_t *) HW_UART_UCR4_ADDR(x)) +#define HW_UART_UCR4_RD(x) (HW_UART_UCR4(x).U) +#define HW_UART_UCR4_WR(x, v) (HW_UART_UCR4(x).U = (v)) +#define HW_UART_UCR4_SET(x, v) (HW_UART_UCR4_WR(x, HW_UART_UCR4_RD(x) | (v))) +#define HW_UART_UCR4_CLR(x, v) (HW_UART_UCR4_WR(x, HW_UART_UCR4_RD(x) & ~(v))) +#define HW_UART_UCR4_TOG(x, v) (HW_UART_UCR4_WR(x, HW_UART_UCR4_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UCR4 bitfields + */ + +/*! @name Register UART_UCR4, field DREN[0] (RW) + * + * Receive Data Ready Interrupt Enable . Enables/Disables the RDR bit to generate an interrupt. + * + * Values: + * - 0 - Disable RDR interrupt + * - 1 - Enable RDR interrupt + */ +//@{ +#define BP_UART_UCR4_DREN (0) //!< Bit position for UART_UCR4_DREN. +#define BM_UART_UCR4_DREN (0x00000001) //!< Bit mask for UART_UCR4_DREN. + +//! @brief Get value of UART_UCR4_DREN from a register value. +#define BG_UART_UCR4_DREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_DREN) >> BP_UART_UCR4_DREN) + +//! @brief Format value for bitfield UART_UCR4_DREN. +#define BF_UART_UCR4_DREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_DREN) & BM_UART_UCR4_DREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DREN field to a new value. +#define BW_UART_UCR4_DREN(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_DREN) | BF_UART_UCR4_DREN(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field OREN[1] (RW) + * + * Receiver Overrun Interrupt Enable . Enables/Disables the ORE bit to generate an interrupt. + * + * Values: + * - 0 - Disable ORE interrupt + * - 1 - Enable ORE interrupt + */ +//@{ +#define BP_UART_UCR4_OREN (1) //!< Bit position for UART_UCR4_OREN. +#define BM_UART_UCR4_OREN (0x00000002) //!< Bit mask for UART_UCR4_OREN. + +//! @brief Get value of UART_UCR4_OREN from a register value. +#define BG_UART_UCR4_OREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_OREN) >> BP_UART_UCR4_OREN) + +//! @brief Format value for bitfield UART_UCR4_OREN. +#define BF_UART_UCR4_OREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_OREN) & BM_UART_UCR4_OREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the OREN field to a new value. +#define BW_UART_UCR4_OREN(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_OREN) | BF_UART_UCR4_OREN(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field BKEN[2] (RW) + * + * BREAK Condition Detected Interrupt Enable . Enables/Disables the BRCD bit to generate an + * interrupt. + * + * Values: + * - 0 - Disable the BRCD interrupt + * - 1 - Enable the BRCD interrupt + */ +//@{ +#define BP_UART_UCR4_BKEN (2) //!< Bit position for UART_UCR4_BKEN. +#define BM_UART_UCR4_BKEN (0x00000004) //!< Bit mask for UART_UCR4_BKEN. + +//! @brief Get value of UART_UCR4_BKEN from a register value. +#define BG_UART_UCR4_BKEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_BKEN) >> BP_UART_UCR4_BKEN) + +//! @brief Format value for bitfield UART_UCR4_BKEN. +#define BF_UART_UCR4_BKEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_BKEN) & BM_UART_UCR4_BKEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BKEN field to a new value. +#define BW_UART_UCR4_BKEN(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_BKEN) | BF_UART_UCR4_BKEN(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field TCEN[3] (RW) + * + * Transmit Complete Interrupt Enable . Enables/Disables the TXDC bit to generate an interrupt ( + * interrupt_uart = 0) An interrupt will be issued as long as TCEN and TXDC are high even if the + * transmitter is not enabled. In general, user should enable the transmitter before enabling the + * TXDC interrupt. + * + * Values: + * - 0 - Disable TXDC interrupt + * - 1 - Enable TXDC interrupt + */ +//@{ +#define BP_UART_UCR4_TCEN (3) //!< Bit position for UART_UCR4_TCEN. +#define BM_UART_UCR4_TCEN (0x00000008) //!< Bit mask for UART_UCR4_TCEN. + +//! @brief Get value of UART_UCR4_TCEN from a register value. +#define BG_UART_UCR4_TCEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_TCEN) >> BP_UART_UCR4_TCEN) + +//! @brief Format value for bitfield UART_UCR4_TCEN. +#define BF_UART_UCR4_TCEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_TCEN) & BM_UART_UCR4_TCEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TCEN field to a new value. +#define BW_UART_UCR4_TCEN(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_TCEN) | BF_UART_UCR4_TCEN(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field LPBYP[4] (RW) + * + * Low Power Bypass . Allows to bypass the low power new features in UART. To use during debug + * phase. + * + * Values: + * - 0 - Low power features enabled + * - 1 - Low power features disabled + */ +//@{ +#define BP_UART_UCR4_LPBYP (4) //!< Bit position for UART_UCR4_LPBYP. +#define BM_UART_UCR4_LPBYP (0x00000010) //!< Bit mask for UART_UCR4_LPBYP. + +//! @brief Get value of UART_UCR4_LPBYP from a register value. +#define BG_UART_UCR4_LPBYP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_LPBYP) >> BP_UART_UCR4_LPBYP) + +//! @brief Format value for bitfield UART_UCR4_LPBYP. +#define BF_UART_UCR4_LPBYP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_LPBYP) & BM_UART_UCR4_LPBYP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LPBYP field to a new value. +#define BW_UART_UCR4_LPBYP(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_LPBYP) | BF_UART_UCR4_LPBYP(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field IRSC[5] (RW) + * + * IR Special Case . Selects the clock for the vote logic. When set, IRSC switches the vote logic + * clock from the sampling clock to the UART reference clock. The IR pulses are counted a + * predetermined amount of time depending on the reference frequency. See . + * + * Values: + * - 0 - The vote logic uses the sampling clock (16x baud rate) for normal operation + * - 1 - The vote logic uses the UART reference clock + */ +//@{ +#define BP_UART_UCR4_IRSC (5) //!< Bit position for UART_UCR4_IRSC. +#define BM_UART_UCR4_IRSC (0x00000020) //!< Bit mask for UART_UCR4_IRSC. + +//! @brief Get value of UART_UCR4_IRSC from a register value. +#define BG_UART_UCR4_IRSC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_IRSC) >> BP_UART_UCR4_IRSC) + +//! @brief Format value for bitfield UART_UCR4_IRSC. +#define BF_UART_UCR4_IRSC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_IRSC) & BM_UART_UCR4_IRSC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IRSC field to a new value. +#define BW_UART_UCR4_IRSC(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_IRSC) | BF_UART_UCR4_IRSC(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field IDDMAEN[6] (RW) + * + * DMA IDLE Condition Detected Interrupt Enable Enables/Disables the receive DMA request dma_req_rx + * for the IDLE interrupt (triggered with IDLE flag in USR2[12]). + * + * Values: + * - 0 - DMA IDLE interrupt disabled + * - 1 - DMA IDLE interrupt enabled + */ +//@{ +#define BP_UART_UCR4_IDDMAEN (6) //!< Bit position for UART_UCR4_IDDMAEN. +#define BM_UART_UCR4_IDDMAEN (0x00000040) //!< Bit mask for UART_UCR4_IDDMAEN. + +//! @brief Get value of UART_UCR4_IDDMAEN from a register value. +#define BG_UART_UCR4_IDDMAEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_IDDMAEN) >> BP_UART_UCR4_IDDMAEN) + +//! @brief Format value for bitfield UART_UCR4_IDDMAEN. +#define BF_UART_UCR4_IDDMAEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_IDDMAEN) & BM_UART_UCR4_IDDMAEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IDDMAEN field to a new value. +#define BW_UART_UCR4_IDDMAEN(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_IDDMAEN) | BF_UART_UCR4_IDDMAEN(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field WKEN[7] (RW) + * + * WAKE Interrupt Enable . Enables/Disables the WAKE bit to generate an interrupt. The WAKE bit is + * set at the detection of a start bit by the receiver. + * + * Values: + * - 0 - Disable the WAKE interrupt + * - 1 - Enable the WAKE interrupt + */ +//@{ +#define BP_UART_UCR4_WKEN (7) //!< Bit position for UART_UCR4_WKEN. +#define BM_UART_UCR4_WKEN (0x00000080) //!< Bit mask for UART_UCR4_WKEN. + +//! @brief Get value of UART_UCR4_WKEN from a register value. +#define BG_UART_UCR4_WKEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_WKEN) >> BP_UART_UCR4_WKEN) + +//! @brief Format value for bitfield UART_UCR4_WKEN. +#define BF_UART_UCR4_WKEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_WKEN) & BM_UART_UCR4_WKEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WKEN field to a new value. +#define BW_UART_UCR4_WKEN(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_WKEN) | BF_UART_UCR4_WKEN(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field ENIRI[8] (RW) + * + * Serial Infrared Interrupt Enable . Enables/Disables the serial infrared interrupt. + * + * Values: + * - 0 - Serial infrared Interrupt disabled + * - 1 - Serial infrared Interrupt enabled + */ +//@{ +#define BP_UART_UCR4_ENIRI (8) //!< Bit position for UART_UCR4_ENIRI. +#define BM_UART_UCR4_ENIRI (0x00000100) //!< Bit mask for UART_UCR4_ENIRI. + +//! @brief Get value of UART_UCR4_ENIRI from a register value. +#define BG_UART_UCR4_ENIRI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_ENIRI) >> BP_UART_UCR4_ENIRI) + +//! @brief Format value for bitfield UART_UCR4_ENIRI. +#define BF_UART_UCR4_ENIRI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_ENIRI) & BM_UART_UCR4_ENIRI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ENIRI field to a new value. +#define BW_UART_UCR4_ENIRI(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_ENIRI) | BF_UART_UCR4_ENIRI(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field INVR[9] (RW) + * + * Invert RXD input in RS-232/RS-485 Mode, d etermine RXD input logic level being sampled in In IrDA + * mode. In RS232/RS-485 Mode(UMCR[0] = 1), if this bit is set to 1, the RXD input is inverted + * before sampled. In IrDA mode ,when cleared, the infrared logic block expects an active low or + * negative IR 3/16 pulse for 0s and 1s are expected for 1s. When INVR is set (INVR 1), the infrared + * logic block expects an active high or positive IR 3/16 pulse for 0s and 0s are expected for 1s. + * + * Values: + * - 0 - RXD input is not inverted + * - 0 - RXD active low detection + * - 1 - RXD input is inverted + * - 1 - RXD active high detection + */ +//@{ +#define BP_UART_UCR4_INVR (9) //!< Bit position for UART_UCR4_INVR. +#define BM_UART_UCR4_INVR (0x00000200) //!< Bit mask for UART_UCR4_INVR. + +//! @brief Get value of UART_UCR4_INVR from a register value. +#define BG_UART_UCR4_INVR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_INVR) >> BP_UART_UCR4_INVR) + +//! @brief Format value for bitfield UART_UCR4_INVR. +#define BF_UART_UCR4_INVR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_INVR) & BM_UART_UCR4_INVR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the INVR field to a new value. +#define BW_UART_UCR4_INVR(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_INVR) | BF_UART_UCR4_INVR(v))) +#endif +//@} + +/*! @name Register UART_UCR4, field CTSTL[15:10] (RW) + * + * CTS Trigger Level . Controls the threshold at which the CTS pin is deasserted by the RxFIFO. + * After the trigger level is reached and the CTS pin is deasserted, the RxFIFO continues to receive + * data until it is full. The CTSTL bits are encoded as shown in the Settings column. Settings 0 to + * 32 are in use. All other settings are Reserved. + * + * Values: + * - 000000 - 0 characters received + * - ... - + * - ... - + * - 000001 - 1 characters in the RxFIFO + * - 100000 - 32 characters in the RxFIFO (maximum) + */ +//@{ +#define BP_UART_UCR4_CTSTL (10) //!< Bit position for UART_UCR4_CTSTL. +#define BM_UART_UCR4_CTSTL (0x0000fc00) //!< Bit mask for UART_UCR4_CTSTL. + +//! @brief Get value of UART_UCR4_CTSTL from a register value. +#define BG_UART_UCR4_CTSTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UCR4_CTSTL) >> BP_UART_UCR4_CTSTL) + +//! @brief Format value for bitfield UART_UCR4_CTSTL. +#define BF_UART_UCR4_CTSTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UCR4_CTSTL) & BM_UART_UCR4_CTSTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CTSTL field to a new value. +#define BW_UART_UCR4_CTSTL(x, v) (HW_UART_UCR4_WR(x, (HW_UART_UCR4_RD(x) & ~BM_UART_UCR4_CTSTL) | BF_UART_UCR4_CTSTL(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UFCR - UART FIFO Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UFCR - UART FIFO Control Register (RW) + * + * Reset value: 0x00000801 + */ +typedef union _hw_uart_ufcr +{ + reg32_t U; + struct _hw_uart_ufcr_bitfields + { + unsigned RXTL : 6; //!< [5:0] Receiver Trigger Level . + unsigned DCEDTE : 1; //!< [6] DCE/DTE mode select . + unsigned RFDIV : 3; //!< [9:7] Reference Frequency Divider. + unsigned TXTL : 6; //!< [15:10] Transmitter Trigger Level . + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_ufcr_t; +#endif + +/*! + * @name Constants and macros for entire UART_UFCR register + */ +//@{ +#define HW_UART_UFCR_ADDR(x) (REGS_UART_BASE(x) + 0x90) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UFCR(x) (*(volatile hw_uart_ufcr_t *) HW_UART_UFCR_ADDR(x)) +#define HW_UART_UFCR_RD(x) (HW_UART_UFCR(x).U) +#define HW_UART_UFCR_WR(x, v) (HW_UART_UFCR(x).U = (v)) +#define HW_UART_UFCR_SET(x, v) (HW_UART_UFCR_WR(x, HW_UART_UFCR_RD(x) | (v))) +#define HW_UART_UFCR_CLR(x, v) (HW_UART_UFCR_WR(x, HW_UART_UFCR_RD(x) & ~(v))) +#define HW_UART_UFCR_TOG(x, v) (HW_UART_UFCR_WR(x, HW_UART_UFCR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UFCR bitfields + */ + +/*! @name Register UART_UFCR, field RXTL[5:0] (RW) + * + * Receiver Trigger Level . Controls the threshold at which a maskable interrupt is generated by the + * RxFIFO. A maskable interrupt is generated whenever the data level in the RxFIFO reaches the + * selected threshold. The RXTL bits are encoded as shown in the Settings column. Setting 0 to 32 + * are in use. All other settings are Reserved. + * + * Values: + * - 000000 - 0 characters received + * - ... - + * - ... - + * - 000001 - RxFIFO has 1 character + * - 011111 - RxFIFO has 31 characters + * - 100000 - RxFIFO has 32 characters (maximum) + */ +//@{ +#define BP_UART_UFCR_RXTL (0) //!< Bit position for UART_UFCR_RXTL. +#define BM_UART_UFCR_RXTL (0x0000003f) //!< Bit mask for UART_UFCR_RXTL. + +//! @brief Get value of UART_UFCR_RXTL from a register value. +#define BG_UART_UFCR_RXTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UFCR_RXTL) >> BP_UART_UFCR_RXTL) + +//! @brief Format value for bitfield UART_UFCR_RXTL. +#define BF_UART_UFCR_RXTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UFCR_RXTL) & BM_UART_UFCR_RXTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXTL field to a new value. +#define BW_UART_UFCR_RXTL(x, v) (HW_UART_UFCR_WR(x, (HW_UART_UFCR_RD(x) & ~BM_UART_UFCR_RXTL) | BF_UART_UFCR_RXTL(v))) +#endif +//@} + +/*! @name Register UART_UFCR, field DCEDTE[6] (RW) + * + * DCE/DTE mode select . Select UART as data communication equipment (DCE mode) or as data terminal + * equipment (DTE mode). + * + * Values: + * - 0 - DCE mode selected + * - 1 - DTE mode selected + */ +//@{ +#define BP_UART_UFCR_DCEDTE (6) //!< Bit position for UART_UFCR_DCEDTE. +#define BM_UART_UFCR_DCEDTE (0x00000040) //!< Bit mask for UART_UFCR_DCEDTE. + +//! @brief Get value of UART_UFCR_DCEDTE from a register value. +#define BG_UART_UFCR_DCEDTE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UFCR_DCEDTE) >> BP_UART_UFCR_DCEDTE) + +//! @brief Format value for bitfield UART_UFCR_DCEDTE. +#define BF_UART_UFCR_DCEDTE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UFCR_DCEDTE) & BM_UART_UFCR_DCEDTE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DCEDTE field to a new value. +#define BW_UART_UFCR_DCEDTE(x, v) (HW_UART_UFCR_WR(x, (HW_UART_UFCR_RD(x) & ~BM_UART_UFCR_DCEDTE) | BF_UART_UFCR_DCEDTE(v))) +#endif +//@} + +/*! @name Register UART_UFCR, field RFDIV[9:7] (RW) + * + * Reference Frequency Divider. Controls the divide ratio for the reference clock. The input clock + * is module_clock . The output from the divider is ref_clk which is used by BRM to create the 16x + * baud rate oversampling clock ( brm_clk ). + * + * Values: + * - 000 - Divide input clock by 6 + * - 001 - Divide input clock by 5 + * - 010 - Divide input clock by 4 + * - 011 - Divide input clock by 3 + * - 100 - Divide input clock by 2 + * - 101 - Divide input clock by 1 + * - 110 - Divide input clock by 7 + * - 111 - Reserved + */ +//@{ +#define BP_UART_UFCR_RFDIV (7) //!< Bit position for UART_UFCR_RFDIV. +#define BM_UART_UFCR_RFDIV (0x00000380) //!< Bit mask for UART_UFCR_RFDIV. + +//! @brief Get value of UART_UFCR_RFDIV from a register value. +#define BG_UART_UFCR_RFDIV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UFCR_RFDIV) >> BP_UART_UFCR_RFDIV) + +//! @brief Format value for bitfield UART_UFCR_RFDIV. +#define BF_UART_UFCR_RFDIV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UFCR_RFDIV) & BM_UART_UFCR_RFDIV) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RFDIV field to a new value. +#define BW_UART_UFCR_RFDIV(x, v) (HW_UART_UFCR_WR(x, (HW_UART_UFCR_RD(x) & ~BM_UART_UFCR_RFDIV) | BF_UART_UFCR_RFDIV(v))) +#endif +//@} + +/*! @name Register UART_UFCR, field TXTL[15:10] (RW) + * + * Transmitter Trigger Level . Controls the threshold at which a maskable interrupt is generated by + * the TxFIFO. A maskable interrupt is generated whenever the data level in the TxFIFO falls below + * the selected threshold. The bits are encoded as shown in the Settings column. Settings 0 to 32 + * are in use. All other settings are Reserved. + * + * Values: + * - 000000 - Reserved + * - ... - + * - ... - + * - 000001 - Reserved + * - 000010 - TxFIFO has 2 or fewer characters + * - 011111 - TxFIFO has 31 or fewer characters + * - 100000 - TxFIFO has 32 characters (maximum) + */ +//@{ +#define BP_UART_UFCR_TXTL (10) //!< Bit position for UART_UFCR_TXTL. +#define BM_UART_UFCR_TXTL (0x0000fc00) //!< Bit mask for UART_UFCR_TXTL. + +//! @brief Get value of UART_UFCR_TXTL from a register value. +#define BG_UART_UFCR_TXTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UFCR_TXTL) >> BP_UART_UFCR_TXTL) + +//! @brief Format value for bitfield UART_UFCR_TXTL. +#define BF_UART_UFCR_TXTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UFCR_TXTL) & BM_UART_UFCR_TXTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXTL field to a new value. +#define BW_UART_UFCR_TXTL(x, v) (HW_UART_UFCR_WR(x, (HW_UART_UFCR_RD(x) & ~BM_UART_UFCR_TXTL) | BF_UART_UFCR_TXTL(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_USR1 - UART Status Register 1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_USR1 - UART Status Register 1 (RW) + * + * Reset value: 0x00002040 + */ +typedef union _hw_uart_usr1 +{ + reg32_t U; + struct _hw_uart_usr1_bitfields + { + unsigned RESERVED0 : 3; //!< [2:0] Reserved + unsigned SAD : 1; //!< [3] RS-485 Slave Address Detected Interrupt Flag. + unsigned AWAKE : 1; //!< [4] Asynchronous WAKE Interrupt Flag. + unsigned AIRINT : 1; //!< [5] Asynchronous IR WAKE Interrupt Flag. + unsigned RXDS : 1; //!< [6] Receiver IDLE Interrupt Flag. + unsigned DTRD : 1; //!< [7] DTR Delta. + unsigned AGTIM : 1; //!< [8] Ageing Timer Interrupt Flag. + unsigned RRDY : 1; //!< [9] Receiver Ready Interrupt / DMA Flag . + unsigned FRAMERR : 1; //!< [10] Frame Error Interrupt Flag . + unsigned ESCF : 1; //!< [11] Escape Sequence Interrupt Flag . + unsigned RTSD : 1; //!< [12] RTS Delta. + unsigned TRDY : 1; //!< [13] Transmitter Ready Interrupt / DMA Flag . + unsigned RTSS : 1; //!< [14] RTS Pin Status . + unsigned PARITYERR : 1; //!< [15] Parity Error Interrupt Flag . + unsigned RESERVED1 : 16; //!< [31:16] Reserved + } B; +} hw_uart_usr1_t; +#endif + +/*! + * @name Constants and macros for entire UART_USR1 register + */ +//@{ +#define HW_UART_USR1_ADDR(x) (REGS_UART_BASE(x) + 0x94) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_USR1(x) (*(volatile hw_uart_usr1_t *) HW_UART_USR1_ADDR(x)) +#define HW_UART_USR1_RD(x) (HW_UART_USR1(x).U) +#define HW_UART_USR1_WR(x, v) (HW_UART_USR1(x).U = (v)) +#define HW_UART_USR1_SET(x, v) (HW_UART_USR1_WR(x, HW_UART_USR1_RD(x) | (v))) +#define HW_UART_USR1_CLR(x, v) (HW_UART_USR1_WR(x, HW_UART_USR1_RD(x) & ~(v))) +#define HW_UART_USR1_TOG(x, v) (HW_UART_USR1_WR(x, HW_UART_USR1_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_USR1 bitfields + */ + +/*! @name Register UART_USR1, field SAD[3] (W1C) + * + * RS-485 Slave Address Detected Interrupt Flag. Indicates if RS-485 Slave Address was detected . + * SAD was asserted in RS-485 mode when the SADEN bit is set and Slave Address is detected in RxFIFO + * (in Nomal Address Detect Mode, the 9 th data bit = 1; in Automatic Address Detect Mode, the + * received charater matches the programmed SLADDR). + * + * Values: + * - 0 - No slave address detected + * - 1 - Slave address detected + */ +//@{ +#define BP_UART_USR1_SAD (3) //!< Bit position for UART_USR1_SAD. +#define BM_UART_USR1_SAD (0x00000008) //!< Bit mask for UART_USR1_SAD. + +//! @brief Get value of UART_USR1_SAD from a register value. +#define BG_UART_USR1_SAD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_SAD) >> BP_UART_USR1_SAD) + +//! @brief Format value for bitfield UART_USR1_SAD. +#define BF_UART_USR1_SAD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_SAD) & BM_UART_USR1_SAD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SAD field to a new value. +#define BW_UART_USR1_SAD(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_SAD) | BF_UART_USR1_SAD(v))) +#endif +//@} + +/*! @name Register UART_USR1, field AWAKE[4] (W1C) + * + * Asynchronous WAKE Interrupt Flag. Indicates that a falling edge was detected on the RXD pin. + * Clear AWAKE by writing 1 to it. Writing 0 to AWAKE has no effect. + * + * Values: + * - 0 - No falling edge was detected on the RXD Serial pin + * - 1 - A falling edge was detected on the RXD Serial pin + */ +//@{ +#define BP_UART_USR1_AWAKE (4) //!< Bit position for UART_USR1_AWAKE. +#define BM_UART_USR1_AWAKE (0x00000010) //!< Bit mask for UART_USR1_AWAKE. + +//! @brief Get value of UART_USR1_AWAKE from a register value. +#define BG_UART_USR1_AWAKE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_AWAKE) >> BP_UART_USR1_AWAKE) + +//! @brief Format value for bitfield UART_USR1_AWAKE. +#define BF_UART_USR1_AWAKE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_AWAKE) & BM_UART_USR1_AWAKE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AWAKE field to a new value. +#define BW_UART_USR1_AWAKE(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_AWAKE) | BF_UART_USR1_AWAKE(v))) +#endif +//@} + +/*! @name Register UART_USR1, field AIRINT[5] (W1C) + * + * Asynchronous IR WAKE Interrupt Flag. Indicates that the IR WAKE pulse was detected on the RXD + * pin. Clear AIRINT by writing 1 to it. Writing 0 to AIRINT has no effect. + * + * Values: + * - 0 - No pulse was detected on the RXD IrDA pin + * - 1 - A pulse was detected on the RXD IrDA pin + */ +//@{ +#define BP_UART_USR1_AIRINT (5) //!< Bit position for UART_USR1_AIRINT. +#define BM_UART_USR1_AIRINT (0x00000020) //!< Bit mask for UART_USR1_AIRINT. + +//! @brief Get value of UART_USR1_AIRINT from a register value. +#define BG_UART_USR1_AIRINT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_AIRINT) >> BP_UART_USR1_AIRINT) + +//! @brief Format value for bitfield UART_USR1_AIRINT. +#define BF_UART_USR1_AIRINT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_AIRINT) & BM_UART_USR1_AIRINT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AIRINT field to a new value. +#define BW_UART_USR1_AIRINT(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_AIRINT) | BF_UART_USR1_AIRINT(v))) +#endif +//@} + +/*! @name Register UART_USR1, field RXDS[6] (RO) + * + * Receiver IDLE Interrupt Flag. Indicates that the receiver state machine is in an IDLE state, the + * next state is IDLE, and the receive pin is high. RXDS is automatically cleared when a character + * is received. RXDS is active only when the receiver is enabled. + * + * Values: + * - 0 - Receive in progress + * - 1 - Receiver is IDLE + */ +//@{ +#define BP_UART_USR1_RXDS (6) //!< Bit position for UART_USR1_RXDS. +#define BM_UART_USR1_RXDS (0x00000040) //!< Bit mask for UART_USR1_RXDS. + +//! @brief Get value of UART_USR1_RXDS from a register value. +#define BG_UART_USR1_RXDS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_RXDS) >> BP_UART_USR1_RXDS) +//@} + +/*! @name Register UART_USR1, field DTRD[7] (W1C) + * + * DTR Delta. Indicates whether DTR (in DCE mode) or DSR (in DTE mode) pins changed state. DTRD + * generates a maskable interrupt if DTRDEN (UCR3[3]) is set. Clear DTRD by writing 1 to it. Writing + * 0 to DTRD has no effect. + * + * Values: + * - 0 - DTR (DCE) or DSR (DTE) pin did not change state since last cleared + * - 1 - DTR (DCE) or DSR (DTE) pin changed state (write 1 to clear) + */ +//@{ +#define BP_UART_USR1_DTRD (7) //!< Bit position for UART_USR1_DTRD. +#define BM_UART_USR1_DTRD (0x00000080) //!< Bit mask for UART_USR1_DTRD. + +//! @brief Get value of UART_USR1_DTRD from a register value. +#define BG_UART_USR1_DTRD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_DTRD) >> BP_UART_USR1_DTRD) + +//! @brief Format value for bitfield UART_USR1_DTRD. +#define BF_UART_USR1_DTRD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_DTRD) & BM_UART_USR1_DTRD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTRD field to a new value. +#define BW_UART_USR1_DTRD(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_DTRD) | BF_UART_USR1_DTRD(v))) +#endif +//@} + +/*! @name Register UART_USR1, field AGTIM[8] (W1C) + * + * Ageing Timer Interrupt Flag. Indicates that data in the RxFIFO has been idle for a time of 8 + * character lengths (where a character length consists of 7 or 8 bits, depending on the setting of + * the WS bit in UCR2, with the bit time corresponding to the baud rate setting) and FIFO data level + * is less than RxFIFO threshold level (RXTL in the UFCR). Clear by writing a 1 to it. + * + * Values: + * - 0 - AGTIM is not active + * - 1 - AGTIM is active (write 1 to clear) + */ +//@{ +#define BP_UART_USR1_AGTIM (8) //!< Bit position for UART_USR1_AGTIM. +#define BM_UART_USR1_AGTIM (0x00000100) //!< Bit mask for UART_USR1_AGTIM. + +//! @brief Get value of UART_USR1_AGTIM from a register value. +#define BG_UART_USR1_AGTIM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_AGTIM) >> BP_UART_USR1_AGTIM) + +//! @brief Format value for bitfield UART_USR1_AGTIM. +#define BF_UART_USR1_AGTIM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_AGTIM) & BM_UART_USR1_AGTIM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AGTIM field to a new value. +#define BW_UART_USR1_AGTIM(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_AGTIM) | BF_UART_USR1_AGTIM(v))) +#endif +//@} + +/*! @name Register UART_USR1, field RRDY[9] (RO) + * + * Receiver Ready Interrupt / DMA Flag . Indicates that the RxFIFO data level is above the threshold + * set by the RXTL bits. (See the RXTL bits description in for setting the interrupt threshold.) + * When asserted, RRDY generates a maskable interrupt or DMA request. RRDY is automatically cleared + * when data level in the RxFIFO goes below the set threshold level. At reset, RRDY is set to 0. + * + * Values: + * - 0 - No character ready + * - 1 - Character(s) ready (interrupt posted) + */ +//@{ +#define BP_UART_USR1_RRDY (9) //!< Bit position for UART_USR1_RRDY. +#define BM_UART_USR1_RRDY (0x00000200) //!< Bit mask for UART_USR1_RRDY. + +//! @brief Get value of UART_USR1_RRDY from a register value. +#define BG_UART_USR1_RRDY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_RRDY) >> BP_UART_USR1_RRDY) +//@} + +/*! @name Register UART_USR1, field FRAMERR[10] (W1C) + * + * Frame Error Interrupt Flag . Indicates that a frame error is detected. The interrupt_uart + * interrupt will be generated if a frame error is detected and the interrupt is enabled. Clear + * FRAMERR by writing 1 to it. Writing 0 to FRAMERR has no effect. + * + * Values: + * - 0 - No frame error detected + * - 1 - Frame error detected (write 1 to clear) + */ +//@{ +#define BP_UART_USR1_FRAMERR (10) //!< Bit position for UART_USR1_FRAMERR. +#define BM_UART_USR1_FRAMERR (0x00000400) //!< Bit mask for UART_USR1_FRAMERR. + +//! @brief Get value of UART_USR1_FRAMERR from a register value. +#define BG_UART_USR1_FRAMERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_FRAMERR) >> BP_UART_USR1_FRAMERR) + +//! @brief Format value for bitfield UART_USR1_FRAMERR. +#define BF_UART_USR1_FRAMERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_FRAMERR) & BM_UART_USR1_FRAMERR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FRAMERR field to a new value. +#define BW_UART_USR1_FRAMERR(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_FRAMERR) | BF_UART_USR1_FRAMERR(v))) +#endif +//@} + +/*! @name Register UART_USR1, field ESCF[11] (W1C) + * + * Escape Sequence Interrupt Flag . Indicates if an escape sequence was detected. ESCF is asserted + * when the ESCEN bit is set and an escape sequence is detected in the RxFIFO. Clear ESCF by writing + * 1 to it. Writing 0 to ESCF has no effect. + * + * Values: + * - 0 - No escape sequence detected + * - 1 - Escape sequence detected (write 1 to clear). + */ +//@{ +#define BP_UART_USR1_ESCF (11) //!< Bit position for UART_USR1_ESCF. +#define BM_UART_USR1_ESCF (0x00000800) //!< Bit mask for UART_USR1_ESCF. + +//! @brief Get value of UART_USR1_ESCF from a register value. +#define BG_UART_USR1_ESCF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_ESCF) >> BP_UART_USR1_ESCF) + +//! @brief Format value for bitfield UART_USR1_ESCF. +#define BF_UART_USR1_ESCF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_ESCF) & BM_UART_USR1_ESCF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ESCF field to a new value. +#define BW_UART_USR1_ESCF(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_ESCF) | BF_UART_USR1_ESCF(v))) +#endif +//@} + +/*! @name Register UART_USR1, field RTSD[12] (W1C) + * + * RTS Delta. Indicates whether the RTS pin changed state. It (RTSD) generates a maskable interrupt. + * When in STOP mode, RTS assertion sets RTSD and can be used to wake the processor. The current + * state of the RTS pin is available on the RTSS bit. Clear RTSD by writing 1 to it. Writing 0 to + * RTSD has no effect. At reset, RTSD is set to 0. + * + * Values: + * - 0 - RTS pin did not change state since last cleared + * - 1 - RTS pin changed state (write 1 to clear) + */ +//@{ +#define BP_UART_USR1_RTSD (12) //!< Bit position for UART_USR1_RTSD. +#define BM_UART_USR1_RTSD (0x00001000) //!< Bit mask for UART_USR1_RTSD. + +//! @brief Get value of UART_USR1_RTSD from a register value. +#define BG_UART_USR1_RTSD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_RTSD) >> BP_UART_USR1_RTSD) + +//! @brief Format value for bitfield UART_USR1_RTSD. +#define BF_UART_USR1_RTSD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_RTSD) & BM_UART_USR1_RTSD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTSD field to a new value. +#define BW_UART_USR1_RTSD(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_RTSD) | BF_UART_USR1_RTSD(v))) +#endif +//@} + +/*! @name Register UART_USR1, field TRDY[13] (RO) + * + * Transmitter Ready Interrupt / DMA Flag . Indicates that the TxFIFO emptied below its target + * threshold and requires data. TRDY is automatically cleared when the data level in the TxFIFO + * exceeds the threshold set by TXTL bits. At reset, TRDY is set to 1. + * + * Values: + * - 0 - The transmitter does not require data + * - 1 - The transmitter requires data (interrupt posted) + */ +//@{ +#define BP_UART_USR1_TRDY (13) //!< Bit position for UART_USR1_TRDY. +#define BM_UART_USR1_TRDY (0x00002000) //!< Bit mask for UART_USR1_TRDY. + +//! @brief Get value of UART_USR1_TRDY from a register value. +#define BG_UART_USR1_TRDY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_TRDY) >> BP_UART_USR1_TRDY) +//@} + +/*! @name Register UART_USR1, field RTSS[14] (RO) + * + * RTS Pin Status . Indicates the current status of the RTS pin. A "snapshot" of the pin is taken + * immediately before RTSS is presented to the data bus. RTSS cannot be cleared because all writes + * to RTSS are ignored. At reset, RTSS is set to 0. + * + * Values: + * - 0 - The RTS pin is high (inactive) + * - 1 - The RTS pin is low (active) + */ +//@{ +#define BP_UART_USR1_RTSS (14) //!< Bit position for UART_USR1_RTSS. +#define BM_UART_USR1_RTSS (0x00004000) //!< Bit mask for UART_USR1_RTSS. + +//! @brief Get value of UART_USR1_RTSS from a register value. +#define BG_UART_USR1_RTSS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_RTSS) >> BP_UART_USR1_RTSS) +//@} + +/*! @name Register UART_USR1, field PARITYERR[15] (W1C) + * + * Parity Error Interrupt Flag . Indicates a parity error is detected. PARITYERR is cleared by + * writing 1 to it. Writing 0 to PARITYERR has no effect. When parity is disabled, PARITYERR always + * reads 0. At reset, PARITYERR is set to 0. + * + * Values: + * - 0 - No parity error detected + * - 1 - Parity error detected (write 1 to clear) + */ +//@{ +#define BP_UART_USR1_PARITYERR (15) //!< Bit position for UART_USR1_PARITYERR. +#define BM_UART_USR1_PARITYERR (0x00008000) //!< Bit mask for UART_USR1_PARITYERR. + +//! @brief Get value of UART_USR1_PARITYERR from a register value. +#define BG_UART_USR1_PARITYERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR1_PARITYERR) >> BP_UART_USR1_PARITYERR) + +//! @brief Format value for bitfield UART_USR1_PARITYERR. +#define BF_UART_USR1_PARITYERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR1_PARITYERR) & BM_UART_USR1_PARITYERR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PARITYERR field to a new value. +#define BW_UART_USR1_PARITYERR(x, v) (HW_UART_USR1_WR(x, (HW_UART_USR1_RD(x) & ~BM_UART_USR1_PARITYERR) | BF_UART_USR1_PARITYERR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_USR2 - UART Status Register 2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_USR2 - UART Status Register 2 (RW) + * + * Reset value: 0x00004028 + */ +typedef union _hw_uart_usr2 +{ + reg32_t U; + struct _hw_uart_usr2_bitfields + { + unsigned RDR : 1; //!< [0] Receive Data Ready -Indicates that at least 1 character is received and written to the RxFIFO. + unsigned ORE : 1; //!< [1] Overrun Error . + unsigned BRCD : 1; //!< [2] BREAK Condition Detected . + unsigned TXDC : 1; //!< [3] Transmitter Complete . + unsigned RTSF : 1; //!< [4] RTS Edge Triggered Interrupt Flag. + unsigned DCDIN : 1; //!< [5] Data Carrier Detect Input . + unsigned DCDDELT : 1; //!< [6] Data Carrier Detect Delta . + unsigned WAKE : 1; //!< [7] Wake . + unsigned IRINT : 1; //!< [8] Serial Infrared Interrupt Flag. + unsigned RIIN : 1; //!< [9] Ring Indicator Input . + unsigned RIDELT : 1; //!< [10] Ring Indicator Delta . + unsigned ACST : 1; //!< [11] Autobaud Counter Stopped . + unsigned IDLE : 1; //!< [12] Idle Condition . + unsigned DTRF : 1; //!< [13] DTR edge triggered interrupt flag . + unsigned TXFE : 1; //!< [14] Transmit Buffer FIFO Empty . + unsigned ADET : 1; //!< [15] Automatic Baud Rate Detect Complete . + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_usr2_t; +#endif + +/*! + * @name Constants and macros for entire UART_USR2 register + */ +//@{ +#define HW_UART_USR2_ADDR(x) (REGS_UART_BASE(x) + 0x98) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_USR2(x) (*(volatile hw_uart_usr2_t *) HW_UART_USR2_ADDR(x)) +#define HW_UART_USR2_RD(x) (HW_UART_USR2(x).U) +#define HW_UART_USR2_WR(x, v) (HW_UART_USR2(x).U = (v)) +#define HW_UART_USR2_SET(x, v) (HW_UART_USR2_WR(x, HW_UART_USR2_RD(x) | (v))) +#define HW_UART_USR2_CLR(x, v) (HW_UART_USR2_WR(x, HW_UART_USR2_RD(x) & ~(v))) +#define HW_UART_USR2_TOG(x, v) (HW_UART_USR2_WR(x, HW_UART_USR2_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_USR2 bitfields + */ + +/*! @name Register UART_USR2, field RDR[0] (RO) + * + * Receive Data Ready -Indicates that at least 1 character is received and written to the RxFIFO. If + * the URXD register is read and there is only 1 character in the RxFIFO, RDR is automatically + * cleared. + * + * Values: + * - 0 - No receive data ready + * - 1 - Receive data ready + */ +//@{ +#define BP_UART_USR2_RDR (0) //!< Bit position for UART_USR2_RDR. +#define BM_UART_USR2_RDR (0x00000001) //!< Bit mask for UART_USR2_RDR. + +//! @brief Get value of UART_USR2_RDR from a register value. +#define BG_UART_USR2_RDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_RDR) >> BP_UART_USR2_RDR) +//@} + +/*! @name Register UART_USR2, field ORE[1] (W1C) + * + * Overrun Error . When set to 1, ORE indicates that the receive buffer (RxFIFO) was full (32 chars + * inside), and a 33rd character has been fully received. This 33rd character has been discarded. + * Clear ORE by writing 1 to it. Writing 0 to ORE has no effect. + * + * Values: + * - 0 - No overrun error + * - 1 - Overrun error (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_ORE (1) //!< Bit position for UART_USR2_ORE. +#define BM_UART_USR2_ORE (0x00000002) //!< Bit mask for UART_USR2_ORE. + +//! @brief Get value of UART_USR2_ORE from a register value. +#define BG_UART_USR2_ORE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_ORE) >> BP_UART_USR2_ORE) + +//! @brief Format value for bitfield UART_USR2_ORE. +#define BF_UART_USR2_ORE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_ORE) & BM_UART_USR2_ORE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ORE field to a new value. +#define BW_UART_USR2_ORE(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_ORE) | BF_UART_USR2_ORE(v))) +#endif +//@} + +/*! @name Register UART_USR2, field BRCD[2] (W1C) + * + * BREAK Condition Detected . Indicates that a BREAK condition was detected by the receiver. Clear + * BRCD by writing 1 to it. Writing 0 to BRCD has no effect. + * + * Values: + * - 0 - No BREAK condition was detected + * - 1 - A BREAK condition was detected (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_BRCD (2) //!< Bit position for UART_USR2_BRCD. +#define BM_UART_USR2_BRCD (0x00000004) //!< Bit mask for UART_USR2_BRCD. + +//! @brief Get value of UART_USR2_BRCD from a register value. +#define BG_UART_USR2_BRCD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_BRCD) >> BP_UART_USR2_BRCD) + +//! @brief Format value for bitfield UART_USR2_BRCD. +#define BF_UART_USR2_BRCD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_BRCD) & BM_UART_USR2_BRCD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BRCD field to a new value. +#define BW_UART_USR2_BRCD(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_BRCD) | BF_UART_USR2_BRCD(v))) +#endif +//@} + +/*! @name Register UART_USR2, field TXDC[3] (RO) + * + * Transmitter Complete . Indicates that the transmit buffer (TxFIFO) and Shift Register is empty; + * therefore the transmission is complete. TXDC is cleared automatically when data is written to the + * TxFIFO. + * + * Values: + * - 0 - Transmit is incomplete + * - 1 - Transmit is complete + */ +//@{ +#define BP_UART_USR2_TXDC (3) //!< Bit position for UART_USR2_TXDC. +#define BM_UART_USR2_TXDC (0x00000008) //!< Bit mask for UART_USR2_TXDC. + +//! @brief Get value of UART_USR2_TXDC from a register value. +#define BG_UART_USR2_TXDC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_TXDC) >> BP_UART_USR2_TXDC) +//@} + +/*! @name Register UART_USR2, field RTSF[4] (W1C) + * + * RTS Edge Triggered Interrupt Flag. Indicates if a programmed edge is detected on the RTS pin. The + * RTEC bits select the edge that generates an interrupt (see ). RTSF can generate an interrupt that + * can be masked using the RTSEN bit. Clear RTSF by writing 1 to it. Writing 0 to RTSF has no + * effect. + * + * Values: + * - 0 - Programmed edge not detected on RTS + * - 1 - Programmed edge detected on RTS (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_RTSF (4) //!< Bit position for UART_USR2_RTSF. +#define BM_UART_USR2_RTSF (0x00000010) //!< Bit mask for UART_USR2_RTSF. + +//! @brief Get value of UART_USR2_RTSF from a register value. +#define BG_UART_USR2_RTSF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_RTSF) >> BP_UART_USR2_RTSF) + +//! @brief Format value for bitfield UART_USR2_RTSF. +#define BF_UART_USR2_RTSF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_RTSF) & BM_UART_USR2_RTSF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTSF field to a new value. +#define BW_UART_USR2_RTSF(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_RTSF) | BF_UART_USR2_RTSF(v))) +#endif +//@} + +/*! @name Register UART_USR2, field DCDIN[5] (RO) + * + * Data Carrier Detect Input . This bit is used in DTE mode reflect the status of the Data Carrier + * Detect input ( DCD ). The Data Carrier Detect input is used to indicate that a carrier signal has + * been detected. In DCE mode this bit is always zero. + * + * Values: + * - 0 - Carrier signal Detected + * - 1 - No Carrier signal Detected + */ +//@{ +#define BP_UART_USR2_DCDIN (5) //!< Bit position for UART_USR2_DCDIN. +#define BM_UART_USR2_DCDIN (0x00000020) //!< Bit mask for UART_USR2_DCDIN. + +//! @brief Get value of UART_USR2_DCDIN from a register value. +#define BG_UART_USR2_DCDIN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_DCDIN) >> BP_UART_USR2_DCDIN) +//@} + +/*! @name Register UART_USR2, field DCDDELT[6] (W1C) + * + * Data Carrier Detect Delta . This bit is used in DTE mode to indicate that the Data Carrier Detect + * input ( DCD ) has changed state. This flag can cause an interrupt if DCD (UCR3[9]) is enabled. + * When in STOP mode, this bit can be used to wake the processor. In DCE mode this bit is always + * zero. + * + * Values: + * - 0 - Data Carrier Detect input has not changed state + * - 1 - Data Carrier Detect input has changed state (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_DCDDELT (6) //!< Bit position for UART_USR2_DCDDELT. +#define BM_UART_USR2_DCDDELT (0x00000040) //!< Bit mask for UART_USR2_DCDDELT. + +//! @brief Get value of UART_USR2_DCDDELT from a register value. +#define BG_UART_USR2_DCDDELT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_DCDDELT) >> BP_UART_USR2_DCDDELT) + +//! @brief Format value for bitfield UART_USR2_DCDDELT. +#define BF_UART_USR2_DCDDELT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_DCDDELT) & BM_UART_USR2_DCDDELT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DCDDELT field to a new value. +#define BW_UART_USR2_DCDDELT(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_DCDDELT) | BF_UART_USR2_DCDDELT(v))) +#endif +//@} + +/*! @name Register UART_USR2, field WAKE[7] (W1C) + * + * Wake . Indicates the start bit is detected. WAKE can generate an interrupt that can be masked + * using the WKEN bit. Clear WAKE by writing 1 to it. Writing 0 to WAKE has no effect. + * + * Values: + * - 0 - start bit not detected + * - 1 - start bit detected (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_WAKE (7) //!< Bit position for UART_USR2_WAKE. +#define BM_UART_USR2_WAKE (0x00000080) //!< Bit mask for UART_USR2_WAKE. + +//! @brief Get value of UART_USR2_WAKE from a register value. +#define BG_UART_USR2_WAKE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_WAKE) >> BP_UART_USR2_WAKE) + +//! @brief Format value for bitfield UART_USR2_WAKE. +#define BF_UART_USR2_WAKE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_WAKE) & BM_UART_USR2_WAKE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WAKE field to a new value. +#define BW_UART_USR2_WAKE(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_WAKE) | BF_UART_USR2_WAKE(v))) +#endif +//@} + +/*! @name Register UART_USR2, field IRINT[8] (W1C) + * + * Serial Infrared Interrupt Flag. When an edge is detected on the RXD pin during SIR Mode, this + * flag will be asserted. This flag can cause an interrupt which can be masked using the control bit + * ENIRI: UCR4 [8]. + * + * Values: + * - 0 - no edge detected + * - 1 - valid edge detected (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_IRINT (8) //!< Bit position for UART_USR2_IRINT. +#define BM_UART_USR2_IRINT (0x00000100) //!< Bit mask for UART_USR2_IRINT. + +//! @brief Get value of UART_USR2_IRINT from a register value. +#define BG_UART_USR2_IRINT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_IRINT) >> BP_UART_USR2_IRINT) + +//! @brief Format value for bitfield UART_USR2_IRINT. +#define BF_UART_USR2_IRINT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_IRINT) & BM_UART_USR2_IRINT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IRINT field to a new value. +#define BW_UART_USR2_IRINT(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_IRINT) | BF_UART_USR2_IRINT(v))) +#endif +//@} + +/*! @name Register UART_USR2, field RIIN[9] (RO) + * + * Ring Indicator Input . This bit is used in DTE mode to reflect the status if the Ring Indicator + * input ( RI ). The Ring Indicator input is used to indicate that a ring has occurred. In DCE mode + * this bit is always zero. + * + * Values: + * - 0 - Ring Detected + * - 1 - No Ring Detected + */ +//@{ +#define BP_UART_USR2_RIIN (9) //!< Bit position for UART_USR2_RIIN. +#define BM_UART_USR2_RIIN (0x00000200) //!< Bit mask for UART_USR2_RIIN. + +//! @brief Get value of UART_USR2_RIIN from a register value. +#define BG_UART_USR2_RIIN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_RIIN) >> BP_UART_USR2_RIIN) +//@} + +/*! @name Register UART_USR2, field RIDELT[10] (W1C) + * + * Ring Indicator Delta . This bit is used in DTE mode to indicate that the Ring Indicator input ( + * RI ) has changed state. This flag can generate an interrupt if RI (UCR3[8]) is enabled. RIDELT is + * cleared by writing 1 to it. Writing 0 to RIDELT has no effect. + * + * Values: + * - 0 - Ring Indicator input has not changed state + * - 1 - Ring Indicator input has changed state (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_RIDELT (10) //!< Bit position for UART_USR2_RIDELT. +#define BM_UART_USR2_RIDELT (0x00000400) //!< Bit mask for UART_USR2_RIDELT. + +//! @brief Get value of UART_USR2_RIDELT from a register value. +#define BG_UART_USR2_RIDELT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_RIDELT) >> BP_UART_USR2_RIDELT) + +//! @brief Format value for bitfield UART_USR2_RIDELT. +#define BF_UART_USR2_RIDELT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_RIDELT) & BM_UART_USR2_RIDELT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RIDELT field to a new value. +#define BW_UART_USR2_RIDELT(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_RIDELT) | BF_UART_USR2_RIDELT(v))) +#endif +//@} + +/*! @name Register UART_USR2, field ACST[11] (W1C) + * + * Autobaud Counter Stopped . In autobaud detection (ADBR=1), indicates the counter which determines + * the baud rate was running and is now stopped. This means either START bit is finished (if + * ADNIMP=1), or Bit 0 is finished (if ADNIMP=0). See , for more details. An interrupt can be + * flagged on interrupt_uart if ACIEN=1. + * + * Values: + * - 0 - Measurement of bit length not finished (in autobaud) + * - 1 - Measurement of bit length finished (in autobaud). (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_ACST (11) //!< Bit position for UART_USR2_ACST. +#define BM_UART_USR2_ACST (0x00000800) //!< Bit mask for UART_USR2_ACST. + +//! @brief Get value of UART_USR2_ACST from a register value. +#define BG_UART_USR2_ACST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_ACST) >> BP_UART_USR2_ACST) + +//! @brief Format value for bitfield UART_USR2_ACST. +#define BF_UART_USR2_ACST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_ACST) & BM_UART_USR2_ACST) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ACST field to a new value. +#define BW_UART_USR2_ACST(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_ACST) | BF_UART_USR2_ACST(v))) +#endif +//@} + +/*! @name Register UART_USR2, field IDLE[12] (W1C) + * + * Idle Condition . Indicates that an idle condition has existed for more than a programmed amount + * frame (see . An interrupt can be generated by this IDLE bit if IDEN (UCR1[12]) is enabled. IDLE + * is cleared by writing 1 to it. Writing 0 to IDLE has no effect. + * + * Values: + * - 0 - No idle condition detected + * - 1 - Idle condition detected (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_IDLE (12) //!< Bit position for UART_USR2_IDLE. +#define BM_UART_USR2_IDLE (0x00001000) //!< Bit mask for UART_USR2_IDLE. + +//! @brief Get value of UART_USR2_IDLE from a register value. +#define BG_UART_USR2_IDLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_IDLE) >> BP_UART_USR2_IDLE) + +//! @brief Format value for bitfield UART_USR2_IDLE. +#define BF_UART_USR2_IDLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_IDLE) & BM_UART_USR2_IDLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IDLE field to a new value. +#define BW_UART_USR2_IDLE(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_IDLE) | BF_UART_USR2_IDLE(v))) +#endif +//@} + +/*! @name Register UART_USR2, field DTRF[13] (W1C) + * + * DTR edge triggered interrupt flag . This bit is asserted, when the programmed edge is detected on + * the DTR pin (DCE mode) or on DSR (DTE mode). This flag can cause an interrupt if DTREN (UCR3[13]) + * is enabled. + * + * Values: + * - 0 - Programmed edge not detected on DTR/DSR + * - 1 - Programmed edge detected on DTR/DSR (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_DTRF (13) //!< Bit position for UART_USR2_DTRF. +#define BM_UART_USR2_DTRF (0x00002000) //!< Bit mask for UART_USR2_DTRF. + +//! @brief Get value of UART_USR2_DTRF from a register value. +#define BG_UART_USR2_DTRF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_DTRF) >> BP_UART_USR2_DTRF) + +//! @brief Format value for bitfield UART_USR2_DTRF. +#define BF_UART_USR2_DTRF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_DTRF) & BM_UART_USR2_DTRF) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTRF field to a new value. +#define BW_UART_USR2_DTRF(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_DTRF) | BF_UART_USR2_DTRF(v))) +#endif +//@} + +/*! @name Register UART_USR2, field TXFE[14] (RO) + * + * Transmit Buffer FIFO Empty . Indicates that the transmit buffer (TxFIFO) is empty. TXFE is + * cleared automatically when data is written to the TxFIFO. Even though TXFE is high, the + * transmission might still be in progress. + * + * Values: + * - 0 - The transmit buffer (TxFIFO) is not empty + * - 1 - The transmit buffer (TxFIFO) is empty + */ +//@{ +#define BP_UART_USR2_TXFE (14) //!< Bit position for UART_USR2_TXFE. +#define BM_UART_USR2_TXFE (0x00004000) //!< Bit mask for UART_USR2_TXFE. + +//! @brief Get value of UART_USR2_TXFE from a register value. +#define BG_UART_USR2_TXFE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_TXFE) >> BP_UART_USR2_TXFE) +//@} + +/*! @name Register UART_USR2, field ADET[15] (W1C) + * + * Automatic Baud Rate Detect Complete . Indicates that an "A" or "a" was received and that the + * receiver detected and verified the incoming baud rate. Clear ADET by writing 1 to it. Writing 0 + * to ADET has no effect. + * + * Values: + * - 0 - ASCII "A" or "a" was not received + * - 1 - ASCII "A" or "a" was received (write 1 to clear) + */ +//@{ +#define BP_UART_USR2_ADET (15) //!< Bit position for UART_USR2_ADET. +#define BM_UART_USR2_ADET (0x00008000) //!< Bit mask for UART_USR2_ADET. + +//! @brief Get value of UART_USR2_ADET from a register value. +#define BG_UART_USR2_ADET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_USR2_ADET) >> BP_UART_USR2_ADET) + +//! @brief Format value for bitfield UART_USR2_ADET. +#define BF_UART_USR2_ADET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_USR2_ADET) & BM_UART_USR2_ADET) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADET field to a new value. +#define BW_UART_USR2_ADET(x, v) (HW_UART_USR2_WR(x, (HW_UART_USR2_RD(x) & ~BM_UART_USR2_ADET) | BF_UART_USR2_ADET(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UESC - UART Escape Character Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UESC - UART Escape Character Register (RW) + * + * Reset value: 0x0000002b + */ +typedef union _hw_uart_uesc +{ + reg32_t U; + struct _hw_uart_uesc_bitfields + { + unsigned ESC_CHAR : 8; //!< [7:0] UART Escape Character . + unsigned RESERVED0 : 24; //!< [31:8] Reserved + } B; +} hw_uart_uesc_t; +#endif + +/*! + * @name Constants and macros for entire UART_UESC register + */ +//@{ +#define HW_UART_UESC_ADDR(x) (REGS_UART_BASE(x) + 0x9c) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UESC(x) (*(volatile hw_uart_uesc_t *) HW_UART_UESC_ADDR(x)) +#define HW_UART_UESC_RD(x) (HW_UART_UESC(x).U) +#define HW_UART_UESC_WR(x, v) (HW_UART_UESC(x).U = (v)) +#define HW_UART_UESC_SET(x, v) (HW_UART_UESC_WR(x, HW_UART_UESC_RD(x) | (v))) +#define HW_UART_UESC_CLR(x, v) (HW_UART_UESC_WR(x, HW_UART_UESC_RD(x) & ~(v))) +#define HW_UART_UESC_TOG(x, v) (HW_UART_UESC_WR(x, HW_UART_UESC_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UESC bitfields + */ + +/*! @name Register UART_UESC, field ESC_CHAR[7:0] (RW) + * + * UART Escape Character . Holds the selected escape character that all received characters are + * compared against to detect an escape sequence. + */ +//@{ +#define BP_UART_UESC_ESC_CHAR (0) //!< Bit position for UART_UESC_ESC_CHAR. +#define BM_UART_UESC_ESC_CHAR (0x000000ff) //!< Bit mask for UART_UESC_ESC_CHAR. + +//! @brief Get value of UART_UESC_ESC_CHAR from a register value. +#define BG_UART_UESC_ESC_CHAR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UESC_ESC_CHAR) >> BP_UART_UESC_ESC_CHAR) + +//! @brief Format value for bitfield UART_UESC_ESC_CHAR. +#define BF_UART_UESC_ESC_CHAR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UESC_ESC_CHAR) & BM_UART_UESC_ESC_CHAR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ESC_CHAR field to a new value. +#define BW_UART_UESC_ESC_CHAR(x, v) (HW_UART_UESC_WR(x, (HW_UART_UESC_RD(x) & ~BM_UART_UESC_ESC_CHAR) | BF_UART_UESC_ESC_CHAR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UTIM - UART Escape Timer Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UTIM - UART Escape Timer Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_uart_utim +{ + reg32_t U; + struct _hw_uart_utim_bitfields + { + unsigned TIM : 12; //!< [11:0] UART Escape Timer. + unsigned RESERVED0 : 20; //!< [31:12] Reserved + } B; +} hw_uart_utim_t; +#endif + +/*! + * @name Constants and macros for entire UART_UTIM register + */ +//@{ +#define HW_UART_UTIM_ADDR(x) (REGS_UART_BASE(x) + 0xa0) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UTIM(x) (*(volatile hw_uart_utim_t *) HW_UART_UTIM_ADDR(x)) +#define HW_UART_UTIM_RD(x) (HW_UART_UTIM(x).U) +#define HW_UART_UTIM_WR(x, v) (HW_UART_UTIM(x).U = (v)) +#define HW_UART_UTIM_SET(x, v) (HW_UART_UTIM_WR(x, HW_UART_UTIM_RD(x) | (v))) +#define HW_UART_UTIM_CLR(x, v) (HW_UART_UTIM_WR(x, HW_UART_UTIM_RD(x) & ~(v))) +#define HW_UART_UTIM_TOG(x, v) (HW_UART_UTIM_WR(x, HW_UART_UTIM_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UTIM bitfields + */ + +/*! @name Register UART_UTIM, field TIM[11:0] (RW) + * + * UART Escape Timer. Holds the maximum time interval (in ms) allowed between escape characters. The + * escape timer register is programmable in intervals of 2 ms. See and for more information on the + * UART escape sequence detection. Reset value 0x000 = 2 ms up to 0xFFF = 8.192 s. + */ +//@{ +#define BP_UART_UTIM_TIM (0) //!< Bit position for UART_UTIM_TIM. +#define BM_UART_UTIM_TIM (0x00000fff) //!< Bit mask for UART_UTIM_TIM. + +//! @brief Get value of UART_UTIM_TIM from a register value. +#define BG_UART_UTIM_TIM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTIM_TIM) >> BP_UART_UTIM_TIM) + +//! @brief Format value for bitfield UART_UTIM_TIM. +#define BF_UART_UTIM_TIM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTIM_TIM) & BM_UART_UTIM_TIM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TIM field to a new value. +#define BW_UART_UTIM_TIM(x, v) (HW_UART_UTIM_WR(x, (HW_UART_UTIM_RD(x) & ~BM_UART_UTIM_TIM) | BF_UART_UTIM_TIM(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UBIR - UART BRM Incremental Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UBIR - UART BRM Incremental Register (RW) + * + * Reset value: 0x00000000 + * + * This register can be written by both software and hardware. When enabling the automatic baud rate + * detection feature hardware can write 0x000F value into the UBIR after finishing detecting baud + * rate. Hardware has higher priority when both software and hardware try to write it at the same + * cycle Note: The write priority in the new design is not same as the original UART. In the orginal + * design, software has higher priotiry than hardware when writing this register at the same time. . + * Please note software reset will reset the register to its reset value. + */ +typedef union _hw_uart_ubir +{ + reg32_t U; + struct _hw_uart_ubir_bitfields + { + unsigned INC : 16; //!< [15:0] Incremental Numerator. + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_ubir_t; +#endif + +/*! + * @name Constants and macros for entire UART_UBIR register + */ +//@{ +#define HW_UART_UBIR_ADDR(x) (REGS_UART_BASE(x) + 0xa4) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UBIR(x) (*(volatile hw_uart_ubir_t *) HW_UART_UBIR_ADDR(x)) +#define HW_UART_UBIR_RD(x) (HW_UART_UBIR(x).U) +#define HW_UART_UBIR_WR(x, v) (HW_UART_UBIR(x).U = (v)) +#define HW_UART_UBIR_SET(x, v) (HW_UART_UBIR_WR(x, HW_UART_UBIR_RD(x) | (v))) +#define HW_UART_UBIR_CLR(x, v) (HW_UART_UBIR_WR(x, HW_UART_UBIR_RD(x) & ~(v))) +#define HW_UART_UBIR_TOG(x, v) (HW_UART_UBIR_WR(x, HW_UART_UBIR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UBIR bitfields + */ + +/*! @name Register UART_UBIR, field INC[15:0] (RW) + * + * Incremental Numerator. Holds the numerator value minus one of the BRM ratio (see ). The UBIR + * register MUST be updated before the UBMR register for the baud rate to be updated correctly. If + * only one register is written to by software, the BRM will ignore this data until the other + * register is written to by software. Updating this field using byte accesses is not recommended + * and is undefined. + */ +//@{ +#define BP_UART_UBIR_INC (0) //!< Bit position for UART_UBIR_INC. +#define BM_UART_UBIR_INC (0x0000ffff) //!< Bit mask for UART_UBIR_INC. + +//! @brief Get value of UART_UBIR_INC from a register value. +#define BG_UART_UBIR_INC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UBIR_INC) >> BP_UART_UBIR_INC) + +//! @brief Format value for bitfield UART_UBIR_INC. +#define BF_UART_UBIR_INC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UBIR_INC) & BM_UART_UBIR_INC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the INC field to a new value. +#define BW_UART_UBIR_INC(x, v) (HW_UART_UBIR_WR(x, (HW_UART_UBIR_RD(x) & ~BM_UART_UBIR_INC) | BF_UART_UBIR_INC(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UBMR - UART BRM Modulator Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UBMR - UART BRM Modulator Register (RW) + * + * Reset value: 0x00000000 + * + * This register can be written by both software and hardware. When enabling the automatic baud rate + * detection feature hardware can write a proper value into the UBMR based on detected baud rate. + * Hardware has higher priority when both software and hardware try to write it at the same cycle + * Note: The write priority in the new design is not same as the original UART. In the orginal + * design, software has higher priotiry than hardware when writing this register at the same time. . + * Please note software reset will reset the register to its reset value. + */ +typedef union _hw_uart_ubmr +{ + reg32_t U; + struct _hw_uart_ubmr_bitfields + { + unsigned MOD : 16; //!< [15:0] Modulator Denominator. + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_ubmr_t; +#endif + +/*! + * @name Constants and macros for entire UART_UBMR register + */ +//@{ +#define HW_UART_UBMR_ADDR(x) (REGS_UART_BASE(x) + 0xa8) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UBMR(x) (*(volatile hw_uart_ubmr_t *) HW_UART_UBMR_ADDR(x)) +#define HW_UART_UBMR_RD(x) (HW_UART_UBMR(x).U) +#define HW_UART_UBMR_WR(x, v) (HW_UART_UBMR(x).U = (v)) +#define HW_UART_UBMR_SET(x, v) (HW_UART_UBMR_WR(x, HW_UART_UBMR_RD(x) | (v))) +#define HW_UART_UBMR_CLR(x, v) (HW_UART_UBMR_WR(x, HW_UART_UBMR_RD(x) & ~(v))) +#define HW_UART_UBMR_TOG(x, v) (HW_UART_UBMR_WR(x, HW_UART_UBMR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UBMR bitfields + */ + +/*! @name Register UART_UBMR, field MOD[15:0] (RW) + * + * Modulator Denominator. Holds the value of the denominator minus one of the BRM ratio (see ). The + * UBIR register MUST be updated before the UBMR register for the baud rate to be updated correctly. + * If only one register is written to by software, the BRM will ignore this data until the other + * register is written to by software. Updating this register using byte accesses is not recommended + * and undefined. + */ +//@{ +#define BP_UART_UBMR_MOD (0) //!< Bit position for UART_UBMR_MOD. +#define BM_UART_UBMR_MOD (0x0000ffff) //!< Bit mask for UART_UBMR_MOD. + +//! @brief Get value of UART_UBMR_MOD from a register value. +#define BG_UART_UBMR_MOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UBMR_MOD) >> BP_UART_UBMR_MOD) + +//! @brief Format value for bitfield UART_UBMR_MOD. +#define BF_UART_UBMR_MOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UBMR_MOD) & BM_UART_UBMR_MOD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MOD field to a new value. +#define BW_UART_UBMR_MOD(x, v) (HW_UART_UBMR_WR(x, (HW_UART_UBMR_RD(x) & ~BM_UART_UBMR_MOD) | BF_UART_UBMR_MOD(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UBRC - UART Baud Rate Count Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UBRC - UART Baud Rate Count Register (RO) + * + * Reset value: 0x00000004 + */ +typedef union _hw_uart_ubrc +{ + reg32_t U; + struct _hw_uart_ubrc_bitfields + { + unsigned BCNT : 16; //!< [15:0] Baud Rate Count Register. + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_uart_ubrc_t; +#endif + +/*! + * @name Constants and macros for entire UART_UBRC register + */ +//@{ +#define HW_UART_UBRC_ADDR(x) (REGS_UART_BASE(x) + 0xac) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UBRC(x) (*(volatile hw_uart_ubrc_t *) HW_UART_UBRC_ADDR(x)) +#define HW_UART_UBRC_RD(x) (HW_UART_UBRC(x).U) +#endif +//@} + +/* + * constants & macros for individual UART_UBRC bitfields + */ + +/*! @name Register UART_UBRC, field BCNT[15:0] (RO) + * + * Baud Rate Count Register. This read only register is used to count the start bit of the incoming + * baud rate (if ADNIMP=1), or start bit + bit0 (if ADNIMP=0). When the measurement is done, the + * Baud Rate Count Register contains the number of UART internal clock cycles (clock after divider) + * present in an incoming bit. BCNT retains its value until the next Automatic Baud Rate Detection + * sequence has been initiated. The 16 bit Baud Rate Count register is reset to 4 and stays at hex + * FFFF in the case of an overflow. + */ +//@{ +#define BP_UART_UBRC_BCNT (0) //!< Bit position for UART_UBRC_BCNT. +#define BM_UART_UBRC_BCNT (0x0000ffff) //!< Bit mask for UART_UBRC_BCNT. + +//! @brief Get value of UART_UBRC_BCNT from a register value. +#define BG_UART_UBRC_BCNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UBRC_BCNT) >> BP_UART_UBRC_BCNT) +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_ONEMS - UART One Millisecond Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_ONEMS - UART One Millisecond Register (RW) + * + * Reset value: 0x00000000 + * + * This register has been expanded from 16 bits to 24 bits. In previous versions, the 16-bit ONEMS + * can only support the maximum 65.535MHz (0xFFFFx1000) ref_clk . To support 4Mbps Bluetooth + * application with 66.5MHz module_clock , the value 0x103C4 (66.5M/1000) should be written into + * this register. In this case, the 16 bits are not enough to contain the 0x103C4. So this register + * was expanded to 24 bits to support high frequency of the ref_clk . + */ +typedef union _hw_uart_onems +{ + reg32_t U; + struct _hw_uart_onems_bitfields + { + unsigned ONEMS : 24; //!< [23:0] One Millisecond Register. + unsigned RESERVED0 : 8; //!< [31:24] Reserved + } B; +} hw_uart_onems_t; +#endif + +/*! + * @name Constants and macros for entire UART_ONEMS register + */ +//@{ +#define HW_UART_ONEMS_ADDR(x) (REGS_UART_BASE(x) + 0xb0) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_ONEMS(x) (*(volatile hw_uart_onems_t *) HW_UART_ONEMS_ADDR(x)) +#define HW_UART_ONEMS_RD(x) (HW_UART_ONEMS(x).U) +#define HW_UART_ONEMS_WR(x, v) (HW_UART_ONEMS(x).U = (v)) +#define HW_UART_ONEMS_SET(x, v) (HW_UART_ONEMS_WR(x, HW_UART_ONEMS_RD(x) | (v))) +#define HW_UART_ONEMS_CLR(x, v) (HW_UART_ONEMS_WR(x, HW_UART_ONEMS_RD(x) & ~(v))) +#define HW_UART_ONEMS_TOG(x, v) (HW_UART_ONEMS_WR(x, HW_UART_ONEMS_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_ONEMS bitfields + */ + +/*! @name Register UART_ONEMS, field ONEMS[23:0] (RW) + * + * One Millisecond Register. This 24-bit register must contain the value of the UART internal + * frequency ( ref_clk in ) divided by 1000. The internal frequency is obtained after the UART BRM + * internal divider (F ( ref_clk ) = F( module_clock ) / RFDIV). In fact this register contains the + * value corresponding to the number of UART BRM internal clock cycles present in one millisecond. + * The ONEMS (and UTIM) registers value are used in the escape character detection feature ( ) to + * count the number of clock cycles left between two escape characters. The ONEMS register is also + * used in infrared special case mode (IRSC = UCR4[5] = 1'b1), see . + */ +//@{ +#define BP_UART_ONEMS_ONEMS (0) //!< Bit position for UART_ONEMS_ONEMS. +#define BM_UART_ONEMS_ONEMS (0x00ffffff) //!< Bit mask for UART_ONEMS_ONEMS. + +//! @brief Get value of UART_ONEMS_ONEMS from a register value. +#define BG_UART_ONEMS_ONEMS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_ONEMS_ONEMS) >> BP_UART_ONEMS_ONEMS) + +//! @brief Format value for bitfield UART_ONEMS_ONEMS. +#define BF_UART_ONEMS_ONEMS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_ONEMS_ONEMS) & BM_UART_ONEMS_ONEMS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ONEMS field to a new value. +#define BW_UART_ONEMS_ONEMS(x, v) (HW_UART_ONEMS_WR(x, (HW_UART_ONEMS_RD(x) & ~BM_UART_ONEMS_ONEMS) | BF_UART_ONEMS_ONEMS(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UTS - UART Test Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UTS - UART Test Register (RW) + * + * Reset value: 0x00000060 + */ +typedef union _hw_uart_uts +{ + reg32_t U; + struct _hw_uart_uts_bitfields + { + unsigned SOFTRST : 1; //!< [0] Software Reset. + unsigned RESERVED0 : 2; //!< [2:1] Reserved + unsigned RXFULL : 1; //!< [3] RxFIFO FULL. + unsigned TXFULL : 1; //!< [4] TxFIFO FULL. + unsigned RXEMPTY : 1; //!< [5] RxFIFO Empty. + unsigned TXEMPTY : 1; //!< [6] TxFIFO Empty. + unsigned RESERVED1 : 2; //!< [8:7] Reserved + unsigned RXDBG : 1; //!< [9] + unsigned LOOPIR : 1; //!< [10] Loop TX and RX for IR Test (LOOPIR) . + unsigned DBGEN : 1; //!< [11] + unsigned LOOP : 1; //!< [12] Loop TX and RX for Test. + unsigned FRCPERR : 1; //!< [13] Force Parity Error. + unsigned RESERVED2 : 18; //!< [31:14] Reserved + } B; +} hw_uart_uts_t; +#endif + +/*! + * @name Constants and macros for entire UART_UTS register + */ +//@{ +#define HW_UART_UTS_ADDR(x) (REGS_UART_BASE(x) + 0xb4) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UTS(x) (*(volatile hw_uart_uts_t *) HW_UART_UTS_ADDR(x)) +#define HW_UART_UTS_RD(x) (HW_UART_UTS(x).U) +#define HW_UART_UTS_WR(x, v) (HW_UART_UTS(x).U = (v)) +#define HW_UART_UTS_SET(x, v) (HW_UART_UTS_WR(x, HW_UART_UTS_RD(x) | (v))) +#define HW_UART_UTS_CLR(x, v) (HW_UART_UTS_WR(x, HW_UART_UTS_RD(x) & ~(v))) +#define HW_UART_UTS_TOG(x, v) (HW_UART_UTS_WR(x, HW_UART_UTS_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UTS bitfields + */ + +/*! @name Register UART_UTS, field SOFTRST[0] (RW) + * + * Software Reset. Indicates the status of the software reset ( SRST bit of UCR2). + * + * Values: + * - 0 - Software reset inactive + * - 1 - Software reset active + */ +//@{ +#define BP_UART_UTS_SOFTRST (0) //!< Bit position for UART_UTS_SOFTRST. +#define BM_UART_UTS_SOFTRST (0x00000001) //!< Bit mask for UART_UTS_SOFTRST. + +//! @brief Get value of UART_UTS_SOFTRST from a register value. +#define BG_UART_UTS_SOFTRST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_SOFTRST) >> BP_UART_UTS_SOFTRST) + +//! @brief Format value for bitfield UART_UTS_SOFTRST. +#define BF_UART_UTS_SOFTRST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_SOFTRST) & BM_UART_UTS_SOFTRST) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SOFTRST field to a new value. +#define BW_UART_UTS_SOFTRST(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_SOFTRST) | BF_UART_UTS_SOFTRST(v))) +#endif +//@} + +/*! @name Register UART_UTS, field RXFULL[3] (RW) + * + * RxFIFO FULL. Indicates the RxFIFO is full. + * + * Values: + * - 0 - The RxFIFO is not full + * - 1 - The RxFIFO is full + */ +//@{ +#define BP_UART_UTS_RXFULL (3) //!< Bit position for UART_UTS_RXFULL. +#define BM_UART_UTS_RXFULL (0x00000008) //!< Bit mask for UART_UTS_RXFULL. + +//! @brief Get value of UART_UTS_RXFULL from a register value. +#define BG_UART_UTS_RXFULL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_RXFULL) >> BP_UART_UTS_RXFULL) + +//! @brief Format value for bitfield UART_UTS_RXFULL. +#define BF_UART_UTS_RXFULL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_RXFULL) & BM_UART_UTS_RXFULL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXFULL field to a new value. +#define BW_UART_UTS_RXFULL(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_RXFULL) | BF_UART_UTS_RXFULL(v))) +#endif +//@} + +/*! @name Register UART_UTS, field TXFULL[4] (RW) + * + * TxFIFO FULL. Indicates the TxFIFO is full. + * + * Values: + * - 0 - The TxFIFO is not full + * - 1 - The TxFIFO is full + */ +//@{ +#define BP_UART_UTS_TXFULL (4) //!< Bit position for UART_UTS_TXFULL. +#define BM_UART_UTS_TXFULL (0x00000010) //!< Bit mask for UART_UTS_TXFULL. + +//! @brief Get value of UART_UTS_TXFULL from a register value. +#define BG_UART_UTS_TXFULL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_TXFULL) >> BP_UART_UTS_TXFULL) + +//! @brief Format value for bitfield UART_UTS_TXFULL. +#define BF_UART_UTS_TXFULL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_TXFULL) & BM_UART_UTS_TXFULL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXFULL field to a new value. +#define BW_UART_UTS_TXFULL(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_TXFULL) | BF_UART_UTS_TXFULL(v))) +#endif +//@} + +/*! @name Register UART_UTS, field RXEMPTY[5] (RW) + * + * RxFIFO Empty. Indicates the RxFIFO is empty. + * + * Values: + * - 0 - The RxFIFO is not empty + * - 1 - The RxFIFO is empty + */ +//@{ +#define BP_UART_UTS_RXEMPTY (5) //!< Bit position for UART_UTS_RXEMPTY. +#define BM_UART_UTS_RXEMPTY (0x00000020) //!< Bit mask for UART_UTS_RXEMPTY. + +//! @brief Get value of UART_UTS_RXEMPTY from a register value. +#define BG_UART_UTS_RXEMPTY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_RXEMPTY) >> BP_UART_UTS_RXEMPTY) + +//! @brief Format value for bitfield UART_UTS_RXEMPTY. +#define BF_UART_UTS_RXEMPTY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_RXEMPTY) & BM_UART_UTS_RXEMPTY) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXEMPTY field to a new value. +#define BW_UART_UTS_RXEMPTY(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_RXEMPTY) | BF_UART_UTS_RXEMPTY(v))) +#endif +//@} + +/*! @name Register UART_UTS, field TXEMPTY[6] (RW) + * + * TxFIFO Empty. Indicates that the TxFIFO is empty. + * + * Values: + * - 0 - The TxFIFO is not empty + * - 1 - The TxFIFO is empty + */ +//@{ +#define BP_UART_UTS_TXEMPTY (6) //!< Bit position for UART_UTS_TXEMPTY. +#define BM_UART_UTS_TXEMPTY (0x00000040) //!< Bit mask for UART_UTS_TXEMPTY. + +//! @brief Get value of UART_UTS_TXEMPTY from a register value. +#define BG_UART_UTS_TXEMPTY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_TXEMPTY) >> BP_UART_UTS_TXEMPTY) + +//! @brief Format value for bitfield UART_UTS_TXEMPTY. +#define BF_UART_UTS_TXEMPTY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_TXEMPTY) & BM_UART_UTS_TXEMPTY) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXEMPTY field to a new value. +#define BW_UART_UTS_TXEMPTY(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_TXEMPTY) | BF_UART_UTS_TXEMPTY(v))) +#endif +//@} + +/*! @name Register UART_UTS, field RXDBG[9] (RW) + * + * RX_fifo_debug_mode. This bit controls the operation of the RX fifo read counter when in debug + * mode. + * + * Values: + * - 0 - rx fifo read pointer does not increment + * - 1 - rx_fifo read pointer increments as normal + */ +//@{ +#define BP_UART_UTS_RXDBG (9) //!< Bit position for UART_UTS_RXDBG. +#define BM_UART_UTS_RXDBG (0x00000200) //!< Bit mask for UART_UTS_RXDBG. + +//! @brief Get value of UART_UTS_RXDBG from a register value. +#define BG_UART_UTS_RXDBG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_RXDBG) >> BP_UART_UTS_RXDBG) + +//! @brief Format value for bitfield UART_UTS_RXDBG. +#define BF_UART_UTS_RXDBG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_RXDBG) & BM_UART_UTS_RXDBG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RXDBG field to a new value. +#define BW_UART_UTS_RXDBG(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_RXDBG) | BF_UART_UTS_RXDBG(v))) +#endif +//@} + +/*! @name Register UART_UTS, field LOOPIR[10] (RW) + * + * Loop TX and RX for IR Test (LOOPIR) . This bit controls loopback from transmitter to receiver in + * the InfraRed interface. + * + * Values: + * - 0 - No IR loop + * - 1 - Connect IR transmitter to IR receiver + */ +//@{ +#define BP_UART_UTS_LOOPIR (10) //!< Bit position for UART_UTS_LOOPIR. +#define BM_UART_UTS_LOOPIR (0x00000400) //!< Bit mask for UART_UTS_LOOPIR. + +//! @brief Get value of UART_UTS_LOOPIR from a register value. +#define BG_UART_UTS_LOOPIR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_LOOPIR) >> BP_UART_UTS_LOOPIR) + +//! @brief Format value for bitfield UART_UTS_LOOPIR. +#define BF_UART_UTS_LOOPIR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_LOOPIR) & BM_UART_UTS_LOOPIR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LOOPIR field to a new value. +#define BW_UART_UTS_LOOPIR(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_LOOPIR) | BF_UART_UTS_LOOPIR(v))) +#endif +//@} + +/*! @name Register UART_UTS, field DBGEN[11] (RW) + * + * debug_enable . This bit controls whether to respond to the debug_req input signal. + * + * Values: + * - 0 - UART will go into debug mode when debug_req is HIGH + * - 1 - UART will not go into debug mode even if debug_req is HIGH + */ +//@{ +#define BP_UART_UTS_DBGEN (11) //!< Bit position for UART_UTS_DBGEN. +#define BM_UART_UTS_DBGEN (0x00000800) //!< Bit mask for UART_UTS_DBGEN. + +//! @brief Get value of UART_UTS_DBGEN from a register value. +#define BG_UART_UTS_DBGEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_DBGEN) >> BP_UART_UTS_DBGEN) + +//! @brief Format value for bitfield UART_UTS_DBGEN. +#define BF_UART_UTS_DBGEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_DBGEN) & BM_UART_UTS_DBGEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DBGEN field to a new value. +#define BW_UART_UTS_DBGEN(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_DBGEN) | BF_UART_UTS_DBGEN(v))) +#endif +//@} + +/*! @name Register UART_UTS, field LOOP[12] (RW) + * + * Loop TX and RX for Test. Controls loopback for test purposes. When LOOP is high, the receiver + * input is internally connected to the transmitter and ignores the RXD pin. The transmitter is + * unaffected by LOOP. If RXDMUXSEL (UCR3[2]) is set to 1, the loopback is applied on serial and + * IrDA signals. If RXDMUXSEL is set to 0, the loopback is only applied on serial signals. + * + * Values: + * - 0 - Normal receiver operation + * - 1 - Internally connect the transmitter output to the receiver input + */ +//@{ +#define BP_UART_UTS_LOOP (12) //!< Bit position for UART_UTS_LOOP. +#define BM_UART_UTS_LOOP (0x00001000) //!< Bit mask for UART_UTS_LOOP. + +//! @brief Get value of UART_UTS_LOOP from a register value. +#define BG_UART_UTS_LOOP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_LOOP) >> BP_UART_UTS_LOOP) + +//! @brief Format value for bitfield UART_UTS_LOOP. +#define BF_UART_UTS_LOOP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_LOOP) & BM_UART_UTS_LOOP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LOOP field to a new value. +#define BW_UART_UTS_LOOP(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_LOOP) | BF_UART_UTS_LOOP(v))) +#endif +//@} + +/*! @name Register UART_UTS, field FRCPERR[13] (RW) + * + * Force Parity Error. Forces the transmitter to generate a parity error if parity is enabled. + * FRCPERR is provided for system debugging. + * + * Values: + * - 0 - Generate normal parity + * - 1 - Generate inverted parity (error) + */ +//@{ +#define BP_UART_UTS_FRCPERR (13) //!< Bit position for UART_UTS_FRCPERR. +#define BM_UART_UTS_FRCPERR (0x00002000) //!< Bit mask for UART_UTS_FRCPERR. + +//! @brief Get value of UART_UTS_FRCPERR from a register value. +#define BG_UART_UTS_FRCPERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UTS_FRCPERR) >> BP_UART_UTS_FRCPERR) + +//! @brief Format value for bitfield UART_UTS_FRCPERR. +#define BF_UART_UTS_FRCPERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UTS_FRCPERR) & BM_UART_UTS_FRCPERR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FRCPERR field to a new value. +#define BW_UART_UTS_FRCPERR(x, v) (HW_UART_UTS_WR(x, (HW_UART_UTS_RD(x) & ~BM_UART_UTS_FRCPERR) | BF_UART_UTS_FRCPERR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_UART_UMCR - UART RS-485 Mode Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_UART_UMCR - UART RS-485 Mode Control Register (RW) + * + * Reset value: 0x00000000 + */ +typedef union _hw_uart_umcr +{ + reg32_t U; + struct _hw_uart_umcr_bitfields + { + unsigned MDEN : 1; //!< [0] 9-bit data or Multidrop Mode (RS-485) Enable. + unsigned SLAM : 1; //!< [1] RS-485 Slave Address Detect Mode Selection. + unsigned TXB8 : 1; //!< [2] Transmit RS-485 bit 8 (the ninth bit or 9 th bit). + unsigned SADEN : 1; //!< [3] RS-485 Slave Address Detected Interrupt Enable. + unsigned RESERVED0 : 4; //!< [7:4] Reserved + unsigned SLADDR : 8; //!< [15:8] RS-485 Slave Address Character. + unsigned RESERVED1 : 16; //!< [31:16] Reserved + } B; +} hw_uart_umcr_t; +#endif + +/*! + * @name Constants and macros for entire UART_UMCR register + */ +//@{ +#define HW_UART_UMCR_ADDR(x) (REGS_UART_BASE(x) + 0xb8) + +#ifndef __LANGUAGE_ASM__ +#define HW_UART_UMCR(x) (*(volatile hw_uart_umcr_t *) HW_UART_UMCR_ADDR(x)) +#define HW_UART_UMCR_RD(x) (HW_UART_UMCR(x).U) +#define HW_UART_UMCR_WR(x, v) (HW_UART_UMCR(x).U = (v)) +#define HW_UART_UMCR_SET(x, v) (HW_UART_UMCR_WR(x, HW_UART_UMCR_RD(x) | (v))) +#define HW_UART_UMCR_CLR(x, v) (HW_UART_UMCR_WR(x, HW_UART_UMCR_RD(x) & ~(v))) +#define HW_UART_UMCR_TOG(x, v) (HW_UART_UMCR_WR(x, HW_UART_UMCR_RD(x) ^ (v))) +#endif +//@} + +/* + * constants & macros for individual UART_UMCR bitfields + */ + +/*! @name Register UART_UMCR, field MDEN[0] (RW) + * + * 9-bit data or Multidrop Mode (RS-485) Enable. + * + * Values: + * - 0 - Normal RS-232 or IrDA mode, see for detail. + * - 1 - Enable RS-485 mode, see for detail + */ +//@{ +#define BP_UART_UMCR_MDEN (0) //!< Bit position for UART_UMCR_MDEN. +#define BM_UART_UMCR_MDEN (0x00000001) //!< Bit mask for UART_UMCR_MDEN. + +//! @brief Get value of UART_UMCR_MDEN from a register value. +#define BG_UART_UMCR_MDEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UMCR_MDEN) >> BP_UART_UMCR_MDEN) + +//! @brief Format value for bitfield UART_UMCR_MDEN. +#define BF_UART_UMCR_MDEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UMCR_MDEN) & BM_UART_UMCR_MDEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MDEN field to a new value. +#define BW_UART_UMCR_MDEN(x, v) (HW_UART_UMCR_WR(x, (HW_UART_UMCR_RD(x) & ~BM_UART_UMCR_MDEN) | BF_UART_UMCR_MDEN(v))) +#endif +//@} + +/*! @name Register UART_UMCR, field SLAM[1] (RW) + * + * RS-485 Slave Address Detect Mode Selection. + * + * Values: + * - 0 - Select Normal Address Detect mode + * - 1 - Select Automatic Address Detect mode + */ +//@{ +#define BP_UART_UMCR_SLAM (1) //!< Bit position for UART_UMCR_SLAM. +#define BM_UART_UMCR_SLAM (0x00000002) //!< Bit mask for UART_UMCR_SLAM. + +//! @brief Get value of UART_UMCR_SLAM from a register value. +#define BG_UART_UMCR_SLAM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UMCR_SLAM) >> BP_UART_UMCR_SLAM) + +//! @brief Format value for bitfield UART_UMCR_SLAM. +#define BF_UART_UMCR_SLAM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UMCR_SLAM) & BM_UART_UMCR_SLAM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SLAM field to a new value. +#define BW_UART_UMCR_SLAM(x, v) (HW_UART_UMCR_WR(x, (HW_UART_UMCR_RD(x) & ~BM_UART_UMCR_SLAM) | BF_UART_UMCR_SLAM(v))) +#endif +//@} + +/*! @name Register UART_UMCR, field TXB8[2] (RW) + * + * Transmit RS-485 bit 8 (the ninth bit or 9 th bit). In RS-485 mode, software writes TXB8 bit as + * the 9 th data bit to be transmitted. + * + * Values: + * - 0 - 0 will be transmitted as the RS485 9 th data bit + * - 1 - 1 will be transmitted as the RS485 9 th data bit + */ +//@{ +#define BP_UART_UMCR_TXB8 (2) //!< Bit position for UART_UMCR_TXB8. +#define BM_UART_UMCR_TXB8 (0x00000004) //!< Bit mask for UART_UMCR_TXB8. + +//! @brief Get value of UART_UMCR_TXB8 from a register value. +#define BG_UART_UMCR_TXB8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UMCR_TXB8) >> BP_UART_UMCR_TXB8) + +//! @brief Format value for bitfield UART_UMCR_TXB8. +#define BF_UART_UMCR_TXB8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UMCR_TXB8) & BM_UART_UMCR_TXB8) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TXB8 field to a new value. +#define BW_UART_UMCR_TXB8(x, v) (HW_UART_UMCR_WR(x, (HW_UART_UMCR_RD(x) & ~BM_UART_UMCR_TXB8) | BF_UART_UMCR_TXB8(v))) +#endif +//@} + +/*! @name Register UART_UMCR, field SADEN[3] (RW) + * + * RS-485 Slave Address Detected Interrupt Enable. + * + * Values: + * - 0 - Disable RS-485 Slave Address Detected Interrupt + * - 1 - Enable RS-485 Slave Address Detected Interrupt + */ +//@{ +#define BP_UART_UMCR_SADEN (3) //!< Bit position for UART_UMCR_SADEN. +#define BM_UART_UMCR_SADEN (0x00000008) //!< Bit mask for UART_UMCR_SADEN. + +//! @brief Get value of UART_UMCR_SADEN from a register value. +#define BG_UART_UMCR_SADEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UMCR_SADEN) >> BP_UART_UMCR_SADEN) + +//! @brief Format value for bitfield UART_UMCR_SADEN. +#define BF_UART_UMCR_SADEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UMCR_SADEN) & BM_UART_UMCR_SADEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SADEN field to a new value. +#define BW_UART_UMCR_SADEN(x, v) (HW_UART_UMCR_WR(x, (HW_UART_UMCR_RD(x) & ~BM_UART_UMCR_SADEN) | BF_UART_UMCR_SADEN(v))) +#endif +//@} + +/*! @name Register UART_UMCR, field SLADDR[15:8] (RW) + * + * RS-485 Slave Address Character. Holds the selected slave adress character that the receiver wil + * try to detect. + */ +//@{ +#define BP_UART_UMCR_SLADDR (8) //!< Bit position for UART_UMCR_SLADDR. +#define BM_UART_UMCR_SLADDR (0x0000ff00) //!< Bit mask for UART_UMCR_SLADDR. + +//! @brief Get value of UART_UMCR_SLADDR from a register value. +#define BG_UART_UMCR_SLADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_UART_UMCR_SLADDR) >> BP_UART_UMCR_SLADDR) + +//! @brief Format value for bitfield UART_UMCR_SLADDR. +#define BF_UART_UMCR_SLADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_UART_UMCR_SLADDR) & BM_UART_UMCR_SLADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SLADDR field to a new value. +#define BW_UART_UMCR_SLADDR(x, v) (HW_UART_UMCR_WR(x, (HW_UART_UMCR_RD(x) & ~BM_UART_UMCR_SLADDR) | BF_UART_UMCR_SLADDR(v))) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// hw_uart_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All UART module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_uart +{ + volatile hw_uart_urxd_t URXD; //!< UART Receiver Register + reg32_t _reserved0[15]; + volatile hw_uart_utxd_t UTXD; //!< UART Transmitter Register + reg32_t _reserved1[15]; + volatile hw_uart_ucr1_t UCR1; //!< UART Control Register 1 + volatile hw_uart_ucr2_t UCR2; //!< UART Control Register 2 + volatile hw_uart_ucr3_t UCR3; //!< UART Control Register 3 + volatile hw_uart_ucr4_t UCR4; //!< UART Control Register 4 + volatile hw_uart_ufcr_t UFCR; //!< UART FIFO Control Register + volatile hw_uart_usr1_t USR1; //!< UART Status Register 1 + volatile hw_uart_usr2_t USR2; //!< UART Status Register 2 + volatile hw_uart_uesc_t UESC; //!< UART Escape Character Register + volatile hw_uart_utim_t UTIM; //!< UART Escape Timer Register + volatile hw_uart_ubir_t UBIR; //!< UART BRM Incremental Register + volatile hw_uart_ubmr_t UBMR; //!< UART BRM Modulator Register + volatile hw_uart_ubrc_t UBRC; //!< UART Baud Rate Count Register + volatile hw_uart_onems_t ONEMS; //!< UART One Millisecond Register + volatile hw_uart_uts_t UTS; //!< UART Test Register + volatile hw_uart_umcr_t UMCR; //!< UART RS-485 Mode Control Register +} hw_uart_t; +#pragma pack() + +//! @brief Macro to access all UART registers. +//! @param x UART instance number. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_UART(0). +#define HW_UART(x) (*(hw_uart_t *) REGS_UART_BASE(x)) +#endif + +#endif // __HW_UART_REGISTERS_H__ +// v18/121106/1.2.2 +// EOF diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsusbanalog.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsusbanalog.h new file mode 100644 index 0000000000000000000000000000000000000000..4866cec5b08907c8f6a13a266b9e05c58fdef57b --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsusbanalog.h @@ -0,0 +1,1325 @@ +/* + * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. + */ + +#ifndef __HW_USB_ANALOG_REGISTERS_H__ +#define __HW_USB_ANALOG_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL USB_ANALOG registers defined in this header file. + * + * - HW_USB_ANALOG_USB1_VBUS_DETECT - USB VBUS Detect Register + * - HW_USB_ANALOG_USB1_CHRG_DETECT - USB Charger Detect Register + * - HW_USB_ANALOG_USB1_VBUS_DETECT_STAT - USB VBUS Detect Status Register + * - HW_USB_ANALOG_USB1_CHRG_DETECT_STAT - USB Charger Detect Status Register + * - HW_USB_ANALOG_USB1_MISC - USB Misc Register + * - HW_USB_ANALOG_USB2_VBUS_DETECT - USB VBUS Detect Register + * - HW_USB_ANALOG_USB2_CHRG_DETECT - USB Charger Detect Register + * - HW_USB_ANALOG_USB2_VBUS_DETECT_STAT - USB VBUS Detect Status Register + * - HW_USB_ANALOG_USB2_CHRG_DETECT_STAT - USB Charger Detect Status Register + * - HW_USB_ANALOG_USB2_MISC - USB Misc Register + * - HW_USB_ANALOG_DIGPROG - Chip Silicon Version + * + * - hw_usb_analog_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_USB_ANALOG_BASE +#define HW_USB_ANALOG_INSTANCE_COUNT (1) //!< Number of instances of the USB_ANALOG module. +#define REGS_USB_ANALOG_BASE (0x020c8000) //!< Base address for USB_ANALOG. +#endif +//@} + + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB1_VBUS_DETECT - USB VBUS Detect Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB1_VBUS_DETECT - USB VBUS Detect Register (RW) + * + * Reset value: 0x00100004 + * + * This register defines controls for USB VBUS detect. + */ +typedef union _hw_usb_analog_usb1_vbus_detect +{ + reg32_t U; + struct _hw_usb_analog_usb1_vbus_detect_bitfields + { + unsigned VBUSVALID_THRESH : 3; //!< [2:0] Set the threshold for the VBUSVALID comparator. + unsigned RESERVED0 : 17; //!< [19:3] Reserved. + unsigned VBUSVALID_PWRUP_CMPS : 1; //!< [20] Powers up comparators for vbus_valid detector. + unsigned RESERVED1 : 5; //!< [25:21] Reserved. + unsigned DISCHARGE_VBUS : 1; //!< [26] USB OTG discharge VBUS. + unsigned CHARGE_VBUS : 1; //!< [27] USB OTG charge VBUS. + unsigned RESERVED2 : 3; //!< [30:28] Reserved. + unsigned EN_CHARGER_RESISTOR : 1; //!< [31] Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB. + } B; +} hw_usb_analog_usb1_vbus_detect_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB1_VBUS_DETECT register + */ +#define HW_USB_ANALOG_USB1_VBUS_DETECT_ADDR (REGS_USB_ANALOG_BASE + 0x1a0) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_SET_ADDR (HW_USB_ANALOG_USB1_VBUS_DETECT_ADDR + 0x4) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_CLR_ADDR (HW_USB_ANALOG_USB1_VBUS_DETECT_ADDR + 0x8) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_TOG_ADDR (HW_USB_ANALOG_USB1_VBUS_DETECT_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB1_VBUS_DETECT (*(volatile hw_usb_analog_usb1_vbus_detect_t *) HW_USB_ANALOG_USB1_VBUS_DETECT_ADDR) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_RD() (HW_USB_ANALOG_USB1_VBUS_DETECT.U) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_WR(v) (HW_USB_ANALOG_USB1_VBUS_DETECT.U = (v)) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_SET(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_VBUS_DETECT_SET_ADDR) = (v)) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_CLR(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_VBUS_DETECT_CLR_ADDR) = (v)) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_TOG(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_VBUS_DETECT_TOG_ADDR) = (v)) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB1_VBUS_DETECT bitfields + */ + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT, field VBUSVALID_THRESH[2:0] (RW) + * + * Set the threshold for the VBUSVALID comparator. This comparator is the most accurate method to + * determine the presence of 5v, and includes hystersis to minimize the need for software debounce + * of the detection. This comparator has ~50mV of hystersis to prevent chattering at the comparator + * trip point. + * + * Values: + * 4V0 = 000 - 4.0V + * 4V1 = 001 - 4.1V + * 4V2 = 010 - 4.2V + * 4V3 = 011 - 4.3V + * 4V4 = 100 - 4.4V (default) + * 4V5 = 101 - 4.5V + * 4V6 = 110 - 4.6V + * 4V7 = 111 - 4.7V + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH (0) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH (0x00000007) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH) >> BP_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH) + +//! @brief Format value for bitfield USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH. +#define BF_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH) & BM_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VBUSVALID_THRESH field to a new value. +#define BW_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) BF_CS1(USB_ANALOG_USB1_VBUS_DETECT, VBUSVALID_THRESH, v) +#endif + +#define BV_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH__4V0 (0x0) //!< 4.0V +#define BV_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH__4V1 (0x1) //!< 4.1V +#define BV_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH__4V2 (0x2) //!< 4.2V +#define BV_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH__4V3 (0x3) //!< 4.3V +#define BV_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH__4V4 (0x4) //!< 4.4V (default) +#define BV_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH__4V5 (0x5) //!< 4.5V +#define BV_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH__4V6 (0x6) //!< 4.6V +#define BV_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH__4V7 (0x7) //!< 4.7V + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT, field VBUSVALID_PWRUP_CMPS[20] (RW) + * + * Powers up comparators for vbus_valid detector. + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS (20) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS (0x00100000) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS) >> BP_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS) + +//! @brief Format value for bitfield USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS. +#define BF_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS) & BM_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VBUSVALID_PWRUP_CMPS field to a new value. +#define BW_USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(v) BF_CS1(USB_ANALOG_USB1_VBUS_DETECT, VBUSVALID_PWRUP_CMPS, v) +#endif + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT, field DISCHARGE_VBUS[26] (RW) + * + * USB OTG discharge VBUS. + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS (26) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS (0x04000000) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS) >> BP_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS) + +//! @brief Format value for bitfield USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS. +#define BF_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS) & BM_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DISCHARGE_VBUS field to a new value. +#define BW_USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS(v) BF_CS1(USB_ANALOG_USB1_VBUS_DETECT, DISCHARGE_VBUS, v) +#endif + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT, field CHARGE_VBUS[27] (RW) + * + * USB OTG charge VBUS. + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS (27) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS (0x08000000) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS) >> BP_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS) + +//! @brief Format value for bitfield USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS. +#define BF_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS) & BM_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHARGE_VBUS field to a new value. +#define BW_USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS(v) BF_CS1(USB_ANALOG_USB1_VBUS_DETECT, CHARGE_VBUS, v) +#endif + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT, field EN_CHARGER_RESISTOR[31] (RW) + * + * Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB. + * This functionality is a new USB spec and should not be enabled unless recommended by Freescale. + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR (31) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR (0x80000000) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR) >> BP_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR) + +//! @brief Format value for bitfield USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR. +#define BF_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR) & BM_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_CHARGER_RESISTOR field to a new value. +#define BW_USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(v) BF_CS1(USB_ANALOG_USB1_VBUS_DETECT, EN_CHARGER_RESISTOR, v) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB1_CHRG_DETECT - USB Charger Detect Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB1_CHRG_DETECT - USB Charger Detect Register (RW) + * + * Reset value: 0x00000000 + * + * This register defines controls for USB charger detect. + */ +typedef union _hw_usb_analog_usb1_chrg_detect +{ + reg32_t U; + struct _hw_usb_analog_usb1_chrg_detect_bitfields + { + unsigned RESERVED0 : 18; //!< [17:0] Reserved. + unsigned CHK_CONTACT : 1; //!< [18] + unsigned CHK_CHRG_B : 1; //!< [19] + unsigned EN_B : 1; //!< [20] Control the charger detector. + unsigned RESERVED1 : 3; //!< [23:21] Reserved. + unsigned RESERVED2 : 8; //!< [31:24] Reserved. + } B; +} hw_usb_analog_usb1_chrg_detect_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB1_CHRG_DETECT register + */ +#define HW_USB_ANALOG_USB1_CHRG_DETECT_ADDR (REGS_USB_ANALOG_BASE + 0x1b0) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_SET_ADDR (HW_USB_ANALOG_USB1_CHRG_DETECT_ADDR + 0x4) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_CLR_ADDR (HW_USB_ANALOG_USB1_CHRG_DETECT_ADDR + 0x8) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_TOG_ADDR (HW_USB_ANALOG_USB1_CHRG_DETECT_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB1_CHRG_DETECT (*(volatile hw_usb_analog_usb1_chrg_detect_t *) HW_USB_ANALOG_USB1_CHRG_DETECT_ADDR) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_RD() (HW_USB_ANALOG_USB1_CHRG_DETECT.U) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_WR(v) (HW_USB_ANALOG_USB1_CHRG_DETECT.U = (v)) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_SET(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_CHRG_DETECT_SET_ADDR) = (v)) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_CLR(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_CHRG_DETECT_CLR_ADDR) = (v)) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_TOG(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_CHRG_DETECT_TOG_ADDR) = (v)) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB1_CHRG_DETECT bitfields + */ + +/* --- Register HW_USB_ANALOG_USB1_CHRG_DETECT, field CHK_CONTACT[18] (RW) + * + + * + * Values: + * NO_CHECK = 0 - Do not check the contact of USB plug. + * CHECK = 1 - Check whether the USB plug has been in contact with each other + */ + +#define BP_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT (18) //!< Bit position for USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT. +#define BM_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT (0x00040000) //!< Bit mask for USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT. + +//! @brief Get value of USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT from a register value. +#define BG_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT) >> BP_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT) + +//! @brief Format value for bitfield USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT. +#define BF_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT) & BM_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHK_CONTACT field to a new value. +#define BW_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT(v) BF_CS1(USB_ANALOG_USB1_CHRG_DETECT, CHK_CONTACT, v) +#endif + +#define BV_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT__NO_CHECK (0x0) //!< Do not check the contact of USB plug. +#define BV_USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT__CHECK (0x1) //!< Check whether the USB plug has been in contact with each other + +/* --- Register HW_USB_ANALOG_USB1_CHRG_DETECT, field CHK_CHRG_B[19] (RW) + * + + * + * Values: + * CHECK = 0 - Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * NO_CHECK = 1 - Do not check whether a charger is connected to the USB port. + */ + +#define BP_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B (19) //!< Bit position for USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B. +#define BM_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B (0x00080000) //!< Bit mask for USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B. + +//! @brief Get value of USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B from a register value. +#define BG_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B) >> BP_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B) + +//! @brief Format value for bitfield USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B. +#define BF_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B) & BM_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHK_CHRG_B field to a new value. +#define BW_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B(v) BF_CS1(USB_ANALOG_USB1_CHRG_DETECT, CHK_CHRG_B, v) +#endif + +#define BV_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B__CHECK (0x0) //!< Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. +#define BV_USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B__NO_CHECK (0x1) //!< Do not check whether a charger is connected to the USB port. + +/* --- Register HW_USB_ANALOG_USB1_CHRG_DETECT, field EN_B[20] (RW) + * + * Control the charger detector. + * + * Values: + * ENABLE = 0 - Enable the charger detector. + * DISABLE = 1 - Disable the charger detector. + */ + +#define BP_USB_ANALOG_USB1_CHRG_DETECT_EN_B (20) //!< Bit position for USB_ANALOG_USB1_CHRG_DETECT_EN_B. +#define BM_USB_ANALOG_USB1_CHRG_DETECT_EN_B (0x00100000) //!< Bit mask for USB_ANALOG_USB1_CHRG_DETECT_EN_B. + +//! @brief Get value of USB_ANALOG_USB1_CHRG_DETECT_EN_B from a register value. +#define BG_USB_ANALOG_USB1_CHRG_DETECT_EN_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_CHRG_DETECT_EN_B) >> BP_USB_ANALOG_USB1_CHRG_DETECT_EN_B) + +//! @brief Format value for bitfield USB_ANALOG_USB1_CHRG_DETECT_EN_B. +#define BF_USB_ANALOG_USB1_CHRG_DETECT_EN_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_CHRG_DETECT_EN_B) & BM_USB_ANALOG_USB1_CHRG_DETECT_EN_B) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_B field to a new value. +#define BW_USB_ANALOG_USB1_CHRG_DETECT_EN_B(v) BF_CS1(USB_ANALOG_USB1_CHRG_DETECT, EN_B, v) +#endif + +#define BV_USB_ANALOG_USB1_CHRG_DETECT_EN_B__ENABLE (0x0) //!< Enable the charger detector. +#define BV_USB_ANALOG_USB1_CHRG_DETECT_EN_B__DISABLE (0x1) //!< Disable the charger detector. + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB1_VBUS_DETECT_STAT - USB VBUS Detect Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB1_VBUS_DETECT_STAT - USB VBUS Detect Status Register (RO) + * + * Reset value: 0x00000000 + * + * This register defines fields for USB VBUS Detect status. + */ +typedef union _hw_usb_analog_usb1_vbus_detect_stat +{ + reg32_t U; + struct _hw_usb_analog_usb1_vbus_detect_stat_bitfields + { + unsigned SESSEND : 1; //!< [0] Session End for USB OTG. + unsigned BVALID : 1; //!< [1] Indicates VBus is valid for a B-peripheral. + unsigned AVALID : 1; //!< [2] Indicates VBus is valid for a A-peripheral. + unsigned VBUS_VALID : 1; //!< [3] VBus valid for USB OTG. + unsigned RESERVED0 : 28; //!< [31:4] Reserved. + } B; +} hw_usb_analog_usb1_vbus_detect_stat_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB1_VBUS_DETECT_STAT register + */ +#define HW_USB_ANALOG_USB1_VBUS_DETECT_STAT_ADDR (REGS_USB_ANALOG_BASE + 0x1c0) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB1_VBUS_DETECT_STAT (*(volatile hw_usb_analog_usb1_vbus_detect_stat_t *) HW_USB_ANALOG_USB1_VBUS_DETECT_STAT_ADDR) +#define HW_USB_ANALOG_USB1_VBUS_DETECT_STAT_RD() (HW_USB_ANALOG_USB1_VBUS_DETECT_STAT.U) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB1_VBUS_DETECT_STAT bitfields + */ + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT_STAT, field SESSEND[0] (RO) + * + * Session End for USB OTG. This bit is a read only version of the state of the analog signal. It + * can not be overwritten by software like the SESSEND bit below. NOTE: This bit's default value + * depends on whether VDD5V is present, 0 if VDD5V is present, 1 if VDD5V is not present. + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND (0) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND (0x00000001) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND) >> BP_USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND) + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT_STAT, field BVALID[1] (RO) + * + * Indicates VBus is valid for a B-peripheral. This bit is a read only version of the state of the + * analog signal. It can not be overritten by software. + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID (1) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID (0x00000002) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID) >> BP_USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID) + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT_STAT, field AVALID[2] (RO) + * + * Indicates VBus is valid for a A-peripheral. This bit is a read only version of the state of the + * analog signal. It can not be overritten by software. + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID (2) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID (0x00000004) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID) >> BP_USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID) + +/* --- Register HW_USB_ANALOG_USB1_VBUS_DETECT_STAT, field VBUS_VALID[3] (RO) + * + * VBus valid for USB OTG. This bit is a read only version of the state of the analog signal. It can + * not be overwritten by software. + */ + +#define BP_USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID (3) //!< Bit position for USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID. +#define BM_USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID (0x00000008) //!< Bit mask for USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID. + +//! @brief Get value of USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID from a register value. +#define BG_USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID) >> BP_USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID) + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB1_CHRG_DETECT_STAT - USB Charger Detect Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB1_CHRG_DETECT_STAT - USB Charger Detect Status Register (RO) + * + * Reset value: 0x00000000 + * + * This register defines fields for USB charger detect status. + */ +typedef union _hw_usb_analog_usb1_chrg_detect_stat +{ + reg32_t U; + struct _hw_usb_analog_usb1_chrg_detect_stat_bitfields + { + unsigned PLUG_CONTACT : 1; //!< [0] State of the USB plug contact detector. + unsigned CHRG_DETECTED : 1; //!< [1] State of charger detection. + unsigned DM_STATE : 1; //!< [2] DM line state output of the charger detector. + unsigned DP_STATE : 1; //!< [3] DP line state output of the charger detector. + unsigned RESERVED0 : 28; //!< [31:4] Reserved. + } B; +} hw_usb_analog_usb1_chrg_detect_stat_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB1_CHRG_DETECT_STAT register + */ +#define HW_USB_ANALOG_USB1_CHRG_DETECT_STAT_ADDR (REGS_USB_ANALOG_BASE + 0x1d0) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB1_CHRG_DETECT_STAT (*(volatile hw_usb_analog_usb1_chrg_detect_stat_t *) HW_USB_ANALOG_USB1_CHRG_DETECT_STAT_ADDR) +#define HW_USB_ANALOG_USB1_CHRG_DETECT_STAT_RD() (HW_USB_ANALOG_USB1_CHRG_DETECT_STAT.U) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB1_CHRG_DETECT_STAT bitfields + */ + +/* --- Register HW_USB_ANALOG_USB1_CHRG_DETECT_STAT, field PLUG_CONTACT[0] (RO) + * + * State of the USB plug contact detector. + * + * Values: + * NO_CONTACT = 0 - The USB plug has not made contact. + * GOOD_CONTACT = 1 - The USB plug has made good contact. + */ + +#define BP_USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT (0) //!< Bit position for USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT. +#define BM_USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT (0x00000001) //!< Bit mask for USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT. + +//! @brief Get value of USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT from a register value. +#define BG_USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT) >> BP_USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT) + +#define BV_USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT__NO_CONTACT (0x0) //!< The USB plug has not made contact. +#define BV_USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT__GOOD_CONTACT (0x1) //!< The USB plug has made good contact. + +/* --- Register HW_USB_ANALOG_USB1_CHRG_DETECT_STAT, field CHRG_DETECTED[1] (RO) + * + * State of charger detection. This bit is a read only version of the state of the analog signal. + * + * Values: + * CHARGER_NOT_PRESENT = 0 - The USB port is not connected to a charger. + * CHARGER_PRESENT = 1 - A charger (either a dedicated charger or a host charger) is connected to the USB port. + */ + +#define BP_USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED (1) //!< Bit position for USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED. +#define BM_USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED (0x00000002) //!< Bit mask for USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED. + +//! @brief Get value of USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED from a register value. +#define BG_USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED) >> BP_USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED) + +#define BV_USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED__CHARGER_NOT_PRESENT (0x0) //!< The USB port is not connected to a charger. +#define BV_USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED__CHARGER_PRESENT (0x1) //!< A charger (either a dedicated charger or a host charger) is connected to the USB port. + +/* --- Register HW_USB_ANALOG_USB1_CHRG_DETECT_STAT, field DM_STATE[2] (RO) + * + * DM line state output of the charger detector. + */ + +#define BP_USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE (2) //!< Bit position for USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE. +#define BM_USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE (0x00000004) //!< Bit mask for USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE. + +//! @brief Get value of USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE from a register value. +#define BG_USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE) >> BP_USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE) + +/* --- Register HW_USB_ANALOG_USB1_CHRG_DETECT_STAT, field DP_STATE[3] (RO) + * + * DP line state output of the charger detector. + */ + +#define BP_USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE (3) //!< Bit position for USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE. +#define BM_USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE (0x00000008) //!< Bit mask for USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE. + +//! @brief Get value of USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE from a register value. +#define BG_USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE) >> BP_USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE) + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB1_MISC - USB Misc Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB1_MISC - USB Misc Register (RW) + * + * Reset value: 0x00000002 + * + * This register defines controls for USB. + */ +typedef union _hw_usb_analog_usb1_misc +{ + reg32_t U; + struct _hw_usb_analog_usb1_misc_bitfields + { + unsigned HS_USE_EXTERNAL_R : 1; //!< [0] Use external resistor to generate the current bias for the high speed transmitter. + unsigned EN_DEGLITCH : 1; //!< [1] Enable the deglitching circuit of the USB PLL output. + unsigned RESERVED0 : 28; //!< [29:2] Reserved. + unsigned EN_CLK_UTMI : 1; //!< [30] Enables the clk to the UTMI block. + unsigned RESERVED1 : 1; //!< [31] Reserved. + } B; +} hw_usb_analog_usb1_misc_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB1_MISC register + */ +#define HW_USB_ANALOG_USB1_MISC_ADDR (REGS_USB_ANALOG_BASE + 0x1f0) +#define HW_USB_ANALOG_USB1_MISC_SET_ADDR (HW_USB_ANALOG_USB1_MISC_ADDR + 0x4) +#define HW_USB_ANALOG_USB1_MISC_CLR_ADDR (HW_USB_ANALOG_USB1_MISC_ADDR + 0x8) +#define HW_USB_ANALOG_USB1_MISC_TOG_ADDR (HW_USB_ANALOG_USB1_MISC_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB1_MISC (*(volatile hw_usb_analog_usb1_misc_t *) HW_USB_ANALOG_USB1_MISC_ADDR) +#define HW_USB_ANALOG_USB1_MISC_RD() (HW_USB_ANALOG_USB1_MISC.U) +#define HW_USB_ANALOG_USB1_MISC_WR(v) (HW_USB_ANALOG_USB1_MISC.U = (v)) +#define HW_USB_ANALOG_USB1_MISC_SET(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_MISC_SET_ADDR) = (v)) +#define HW_USB_ANALOG_USB1_MISC_CLR(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_MISC_CLR_ADDR) = (v)) +#define HW_USB_ANALOG_USB1_MISC_TOG(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB1_MISC_TOG_ADDR) = (v)) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB1_MISC bitfields + */ + +/* --- Register HW_USB_ANALOG_USB1_MISC, field HS_USE_EXTERNAL_R[0] (RW) + * + * Use external resistor to generate the current bias for the high speed transmitter. This bit + * should not be changed unless recommended by Freescale. + */ + +#define BP_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R (0) //!< Bit position for USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R. +#define BM_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R (0x00000001) //!< Bit mask for USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R. + +//! @brief Get value of USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R from a register value. +#define BG_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R) >> BP_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R) + +//! @brief Format value for bitfield USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R. +#define BF_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R) & BM_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HS_USE_EXTERNAL_R field to a new value. +#define BW_USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R(v) BF_CS1(USB_ANALOG_USB1_MISC, HS_USE_EXTERNAL_R, v) +#endif + +/* --- Register HW_USB_ANALOG_USB1_MISC, field EN_DEGLITCH[1] (RW) + * + * Enable the deglitching circuit of the USB PLL output. + */ + +#define BP_USB_ANALOG_USB1_MISC_EN_DEGLITCH (1) //!< Bit position for USB_ANALOG_USB1_MISC_EN_DEGLITCH. +#define BM_USB_ANALOG_USB1_MISC_EN_DEGLITCH (0x00000002) //!< Bit mask for USB_ANALOG_USB1_MISC_EN_DEGLITCH. + +//! @brief Get value of USB_ANALOG_USB1_MISC_EN_DEGLITCH from a register value. +#define BG_USB_ANALOG_USB1_MISC_EN_DEGLITCH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_MISC_EN_DEGLITCH) >> BP_USB_ANALOG_USB1_MISC_EN_DEGLITCH) + +//! @brief Format value for bitfield USB_ANALOG_USB1_MISC_EN_DEGLITCH. +#define BF_USB_ANALOG_USB1_MISC_EN_DEGLITCH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_MISC_EN_DEGLITCH) & BM_USB_ANALOG_USB1_MISC_EN_DEGLITCH) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_DEGLITCH field to a new value. +#define BW_USB_ANALOG_USB1_MISC_EN_DEGLITCH(v) BF_CS1(USB_ANALOG_USB1_MISC, EN_DEGLITCH, v) +#endif + +/* --- Register HW_USB_ANALOG_USB1_MISC, field EN_CLK_UTMI[30] (RW) + * + * Enables the clk to the UTMI block. + */ + +#define BP_USB_ANALOG_USB1_MISC_EN_CLK_UTMI (30) //!< Bit position for USB_ANALOG_USB1_MISC_EN_CLK_UTMI. +#define BM_USB_ANALOG_USB1_MISC_EN_CLK_UTMI (0x40000000) //!< Bit mask for USB_ANALOG_USB1_MISC_EN_CLK_UTMI. + +//! @brief Get value of USB_ANALOG_USB1_MISC_EN_CLK_UTMI from a register value. +#define BG_USB_ANALOG_USB1_MISC_EN_CLK_UTMI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB1_MISC_EN_CLK_UTMI) >> BP_USB_ANALOG_USB1_MISC_EN_CLK_UTMI) + +//! @brief Format value for bitfield USB_ANALOG_USB1_MISC_EN_CLK_UTMI. +#define BF_USB_ANALOG_USB1_MISC_EN_CLK_UTMI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB1_MISC_EN_CLK_UTMI) & BM_USB_ANALOG_USB1_MISC_EN_CLK_UTMI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_CLK_UTMI field to a new value. +#define BW_USB_ANALOG_USB1_MISC_EN_CLK_UTMI(v) BF_CS1(USB_ANALOG_USB1_MISC, EN_CLK_UTMI, v) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB2_VBUS_DETECT - USB VBUS Detect Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB2_VBUS_DETECT - USB VBUS Detect Register (RW) + * + * Reset value: 0x00100004 + * + * This register defines controls for USB VBUS detect. + */ +typedef union _hw_usb_analog_usb2_vbus_detect +{ + reg32_t U; + struct _hw_usb_analog_usb2_vbus_detect_bitfields + { + unsigned VBUSVALID_THRESH : 3; //!< [2:0] Set the threshold for the VBUSVALID comparator. + unsigned RESERVED0 : 17; //!< [19:3] Reserved. + unsigned VBUSVALID_PWRUP_CMPS : 1; //!< [20] Powers up comparators for vbus_valid detector. + unsigned RESERVED1 : 5; //!< [25:21] Reserved. + unsigned DISCHARGE_VBUS : 1; //!< [26] USB OTG discharge VBUS. + unsigned CHARGE_VBUS : 1; //!< [27] USB OTG charge VBUS. + unsigned RESERVED2 : 3; //!< [30:28] Reserved. + unsigned EN_CHARGER_RESISTOR : 1; //!< [31] Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB. + } B; +} hw_usb_analog_usb2_vbus_detect_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB2_VBUS_DETECT register + */ +#define HW_USB_ANALOG_USB2_VBUS_DETECT_ADDR (REGS_USB_ANALOG_BASE + 0x200) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_SET_ADDR (HW_USB_ANALOG_USB2_VBUS_DETECT_ADDR + 0x4) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_CLR_ADDR (HW_USB_ANALOG_USB2_VBUS_DETECT_ADDR + 0x8) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_TOG_ADDR (HW_USB_ANALOG_USB2_VBUS_DETECT_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB2_VBUS_DETECT (*(volatile hw_usb_analog_usb2_vbus_detect_t *) HW_USB_ANALOG_USB2_VBUS_DETECT_ADDR) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_RD() (HW_USB_ANALOG_USB2_VBUS_DETECT.U) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_WR(v) (HW_USB_ANALOG_USB2_VBUS_DETECT.U = (v)) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_SET(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_VBUS_DETECT_SET_ADDR) = (v)) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_CLR(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_VBUS_DETECT_CLR_ADDR) = (v)) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_TOG(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_VBUS_DETECT_TOG_ADDR) = (v)) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB2_VBUS_DETECT bitfields + */ + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT, field VBUSVALID_THRESH[2:0] (RW) + * + * Set the threshold for the VBUSVALID comparator. This comparator is the most accurate method to + * determine the presence of 5v, and includes hystersis to minimize the need for software debounce + * of the detection. This comparator has ~50mV of hystersis to prevent chattering at the comparator + * trip point. + * + * Values: + * 4V0 = 000 - 4.0V + * 4V1 = 001 - 4.1V + * 4V2 = 010 - 4.2V + * 4V3 = 011 - 4.3V + * 4V4 = 100 - 4.4V (default) + * 4V5 = 101 - 4.5V + * 4V6 = 110 - 4.6V + * 4V7 = 111 - 4.7V + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH (0) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH (0x00000007) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH) >> BP_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH) + +//! @brief Format value for bitfield USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH. +#define BF_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH) & BM_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VBUSVALID_THRESH field to a new value. +#define BW_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) BF_CS1(USB_ANALOG_USB2_VBUS_DETECT, VBUSVALID_THRESH, v) +#endif + +#define BV_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH__4V0 (0x0) //!< 4.0V +#define BV_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH__4V1 (0x1) //!< 4.1V +#define BV_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH__4V2 (0x2) //!< 4.2V +#define BV_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH__4V3 (0x3) //!< 4.3V +#define BV_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH__4V4 (0x4) //!< 4.4V (default) +#define BV_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH__4V5 (0x5) //!< 4.5V +#define BV_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH__4V6 (0x6) //!< 4.6V +#define BV_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH__4V7 (0x7) //!< 4.7V + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT, field VBUSVALID_PWRUP_CMPS[20] (RW) + * + * Powers up comparators for vbus_valid detector. + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS (20) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS (0x00100000) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS) >> BP_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS) + +//! @brief Format value for bitfield USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS. +#define BF_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS) & BM_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VBUSVALID_PWRUP_CMPS field to a new value. +#define BW_USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(v) BF_CS1(USB_ANALOG_USB2_VBUS_DETECT, VBUSVALID_PWRUP_CMPS, v) +#endif + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT, field DISCHARGE_VBUS[26] (RW) + * + * USB OTG discharge VBUS. + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS (26) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS (0x04000000) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS) >> BP_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS) + +//! @brief Format value for bitfield USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS. +#define BF_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS) & BM_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DISCHARGE_VBUS field to a new value. +#define BW_USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS(v) BF_CS1(USB_ANALOG_USB2_VBUS_DETECT, DISCHARGE_VBUS, v) +#endif + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT, field CHARGE_VBUS[27] (RW) + * + * USB OTG charge VBUS. + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS (27) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS (0x08000000) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS) >> BP_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS) + +//! @brief Format value for bitfield USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS. +#define BF_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS) & BM_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHARGE_VBUS field to a new value. +#define BW_USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS(v) BF_CS1(USB_ANALOG_USB2_VBUS_DETECT, CHARGE_VBUS, v) +#endif + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT, field EN_CHARGER_RESISTOR[31] (RW) + * + * Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB. + * This functionality is a new USB spec and should not be enabled unless recommended by Freescale. + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR (31) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR (0x80000000) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR) >> BP_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR) + +//! @brief Format value for bitfield USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR. +#define BF_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR) & BM_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_CHARGER_RESISTOR field to a new value. +#define BW_USB_ANALOG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR(v) BF_CS1(USB_ANALOG_USB2_VBUS_DETECT, EN_CHARGER_RESISTOR, v) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB2_CHRG_DETECT - USB Charger Detect Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB2_CHRG_DETECT - USB Charger Detect Register (RW) + * + * Reset value: 0x00000000 + * + * This register defines controls for USB charger detect. + */ +typedef union _hw_usb_analog_usb2_chrg_detect +{ + reg32_t U; + struct _hw_usb_analog_usb2_chrg_detect_bitfields + { + unsigned RESERVED0 : 18; //!< [17:0] Reserved. + unsigned CHK_CONTACT : 1; //!< [18] + unsigned CHK_CHRG_B : 1; //!< [19] + unsigned EN_B : 1; //!< [20] Control the charger detector. + unsigned RESERVED1 : 3; //!< [23:21] Reserved. + unsigned RESERVED2 : 8; //!< [31:24] Reserved. + } B; +} hw_usb_analog_usb2_chrg_detect_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB2_CHRG_DETECT register + */ +#define HW_USB_ANALOG_USB2_CHRG_DETECT_ADDR (REGS_USB_ANALOG_BASE + 0x210) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_SET_ADDR (HW_USB_ANALOG_USB2_CHRG_DETECT_ADDR + 0x4) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_CLR_ADDR (HW_USB_ANALOG_USB2_CHRG_DETECT_ADDR + 0x8) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_TOG_ADDR (HW_USB_ANALOG_USB2_CHRG_DETECT_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB2_CHRG_DETECT (*(volatile hw_usb_analog_usb2_chrg_detect_t *) HW_USB_ANALOG_USB2_CHRG_DETECT_ADDR) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_RD() (HW_USB_ANALOG_USB2_CHRG_DETECT.U) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_WR(v) (HW_USB_ANALOG_USB2_CHRG_DETECT.U = (v)) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_SET(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_CHRG_DETECT_SET_ADDR) = (v)) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_CLR(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_CHRG_DETECT_CLR_ADDR) = (v)) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_TOG(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_CHRG_DETECT_TOG_ADDR) = (v)) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB2_CHRG_DETECT bitfields + */ + +/* --- Register HW_USB_ANALOG_USB2_CHRG_DETECT, field CHK_CONTACT[18] (RW) + * + + * + * Values: + * NO_CHECK = 0 - Do not check the contact of USB plug. + * CHECK = 1 - Check whether the USB plug has been in contact with each other + */ + +#define BP_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT (18) //!< Bit position for USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT. +#define BM_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT (0x00040000) //!< Bit mask for USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT. + +//! @brief Get value of USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT from a register value. +#define BG_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT) >> BP_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT) + +//! @brief Format value for bitfield USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT. +#define BF_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT) & BM_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHK_CONTACT field to a new value. +#define BW_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT(v) BF_CS1(USB_ANALOG_USB2_CHRG_DETECT, CHK_CONTACT, v) +#endif + +#define BV_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT__NO_CHECK (0x0) //!< Do not check the contact of USB plug. +#define BV_USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT__CHECK (0x1) //!< Check whether the USB plug has been in contact with each other + +/* --- Register HW_USB_ANALOG_USB2_CHRG_DETECT, field CHK_CHRG_B[19] (RW) + * + + * + * Values: + * CHECK = 0 - Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * NO_CHECK = 1 - Do not check whether a charger is connected to the USB port. + */ + +#define BP_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B (19) //!< Bit position for USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B. +#define BM_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B (0x00080000) //!< Bit mask for USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B. + +//! @brief Get value of USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B from a register value. +#define BG_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B) >> BP_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B) + +//! @brief Format value for bitfield USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B. +#define BF_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B) & BM_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CHK_CHRG_B field to a new value. +#define BW_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B(v) BF_CS1(USB_ANALOG_USB2_CHRG_DETECT, CHK_CHRG_B, v) +#endif + +#define BV_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B__CHECK (0x0) //!< Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. +#define BV_USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B__NO_CHECK (0x1) //!< Do not check whether a charger is connected to the USB port. + +/* --- Register HW_USB_ANALOG_USB2_CHRG_DETECT, field EN_B[20] (RW) + * + * Control the charger detector. + * + * Values: + * ENABLE = 0 - Enable the charger detector. + * DISABLE = 1 - Disable the charger detector. + */ + +#define BP_USB_ANALOG_USB2_CHRG_DETECT_EN_B (20) //!< Bit position for USB_ANALOG_USB2_CHRG_DETECT_EN_B. +#define BM_USB_ANALOG_USB2_CHRG_DETECT_EN_B (0x00100000) //!< Bit mask for USB_ANALOG_USB2_CHRG_DETECT_EN_B. + +//! @brief Get value of USB_ANALOG_USB2_CHRG_DETECT_EN_B from a register value. +#define BG_USB_ANALOG_USB2_CHRG_DETECT_EN_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_CHRG_DETECT_EN_B) >> BP_USB_ANALOG_USB2_CHRG_DETECT_EN_B) + +//! @brief Format value for bitfield USB_ANALOG_USB2_CHRG_DETECT_EN_B. +#define BF_USB_ANALOG_USB2_CHRG_DETECT_EN_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_CHRG_DETECT_EN_B) & BM_USB_ANALOG_USB2_CHRG_DETECT_EN_B) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_B field to a new value. +#define BW_USB_ANALOG_USB2_CHRG_DETECT_EN_B(v) BF_CS1(USB_ANALOG_USB2_CHRG_DETECT, EN_B, v) +#endif + +#define BV_USB_ANALOG_USB2_CHRG_DETECT_EN_B__ENABLE (0x0) //!< Enable the charger detector. +#define BV_USB_ANALOG_USB2_CHRG_DETECT_EN_B__DISABLE (0x1) //!< Disable the charger detector. + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB2_VBUS_DETECT_STAT - USB VBUS Detect Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB2_VBUS_DETECT_STAT - USB VBUS Detect Status Register (RO) + * + * Reset value: 0x00000000 + * + * This register defines fields for USB VBUS Detect status. + */ +typedef union _hw_usb_analog_usb2_vbus_detect_stat +{ + reg32_t U; + struct _hw_usb_analog_usb2_vbus_detect_stat_bitfields + { + unsigned SESSEND : 1; //!< [0] Session End for USB OTG. + unsigned BVALID : 1; //!< [1] Indicates VBus is valid for a B-peripheral. + unsigned AVALID : 1; //!< [2] Indicates VBus is valid for a A-peripheral. + unsigned VBUS_VALID : 1; //!< [3] VBus valid for USB OTG. + unsigned RESERVED0 : 28; //!< [31:4] Reserved. + } B; +} hw_usb_analog_usb2_vbus_detect_stat_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB2_VBUS_DETECT_STAT register + */ +#define HW_USB_ANALOG_USB2_VBUS_DETECT_STAT_ADDR (REGS_USB_ANALOG_BASE + 0x220) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB2_VBUS_DETECT_STAT (*(volatile hw_usb_analog_usb2_vbus_detect_stat_t *) HW_USB_ANALOG_USB2_VBUS_DETECT_STAT_ADDR) +#define HW_USB_ANALOG_USB2_VBUS_DETECT_STAT_RD() (HW_USB_ANALOG_USB2_VBUS_DETECT_STAT.U) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB2_VBUS_DETECT_STAT bitfields + */ + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT_STAT, field SESSEND[0] (RO) + * + * Session End for USB OTG. This bit is a read only version of the state of the analog signal. It + * can not be overwritten by software like the SESSEND bit below. NOTE: This bit's default value + * depends on whether VDD5V is present, 0 if VDD5V is present, 1 if VDD5V is not present. + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND (0) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND (0x00000001) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND) >> BP_USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND) + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT_STAT, field BVALID[1] (RO) + * + * Indicates VBus is valid for a B-peripheral. This bit is a read only version of the state of the + * analog signal. It can not be overritten by software. + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID (1) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID (0x00000002) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID) >> BP_USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID) + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT_STAT, field AVALID[2] (RO) + * + * Indicates VBus is valid for a A-peripheral. This bit is a read only version of the state of the + * analog signal. It can not be overritten by software. + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID (2) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID (0x00000004) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID) >> BP_USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID) + +/* --- Register HW_USB_ANALOG_USB2_VBUS_DETECT_STAT, field VBUS_VALID[3] (RO) + * + * VBus valid for USB OTG. This bit is a read only version of the state of the analog signal. It can + * not be overwritten by software. + */ + +#define BP_USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID (3) //!< Bit position for USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID. +#define BM_USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID (0x00000008) //!< Bit mask for USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID. + +//! @brief Get value of USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID from a register value. +#define BG_USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID) >> BP_USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID) + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB2_CHRG_DETECT_STAT - USB Charger Detect Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB2_CHRG_DETECT_STAT - USB Charger Detect Status Register (RO) + * + * Reset value: 0x00000000 + * + * This register defines fields for USB charger detect status. + */ +typedef union _hw_usb_analog_usb2_chrg_detect_stat +{ + reg32_t U; + struct _hw_usb_analog_usb2_chrg_detect_stat_bitfields + { + unsigned PLUG_CONTACT : 1; //!< [0] State of the USB plug contact detector. + unsigned CHRG_DETECTED : 1; //!< [1] State of charger detection. + unsigned DM_STATE : 1; //!< [2] DM line state output of the charger detector. + unsigned DP_STATE : 1; //!< [3] DP line state output of the charger detector. + unsigned RESERVED0 : 28; //!< [31:4] Reserved. + } B; +} hw_usb_analog_usb2_chrg_detect_stat_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB2_CHRG_DETECT_STAT register + */ +#define HW_USB_ANALOG_USB2_CHRG_DETECT_STAT_ADDR (REGS_USB_ANALOG_BASE + 0x230) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB2_CHRG_DETECT_STAT (*(volatile hw_usb_analog_usb2_chrg_detect_stat_t *) HW_USB_ANALOG_USB2_CHRG_DETECT_STAT_ADDR) +#define HW_USB_ANALOG_USB2_CHRG_DETECT_STAT_RD() (HW_USB_ANALOG_USB2_CHRG_DETECT_STAT.U) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB2_CHRG_DETECT_STAT bitfields + */ + +/* --- Register HW_USB_ANALOG_USB2_CHRG_DETECT_STAT, field PLUG_CONTACT[0] (RO) + * + * State of the USB plug contact detector. + * + * Values: + * NO_CONTACT = 0 - The USB plug has not made contact. + * GOOD_CONTACT = 1 - The USB plug has made good contact. + */ + +#define BP_USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT (0) //!< Bit position for USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT. +#define BM_USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT (0x00000001) //!< Bit mask for USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT. + +//! @brief Get value of USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT from a register value. +#define BG_USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT) >> BP_USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT) + +#define BV_USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT__NO_CONTACT (0x0) //!< The USB plug has not made contact. +#define BV_USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT__GOOD_CONTACT (0x1) //!< The USB plug has made good contact. + +/* --- Register HW_USB_ANALOG_USB2_CHRG_DETECT_STAT, field CHRG_DETECTED[1] (RO) + * + * State of charger detection. This bit is a read only version of the state of the analog signal. + * + * Values: + * CHARGER_NOT_PRESENT = 0 - The USB port is not connected to a charger. + * CHARGER_PRESENT = 1 - A charger (either a dedicated charger or a host charger) is connected to the USB port. + */ + +#define BP_USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED (1) //!< Bit position for USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED. +#define BM_USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED (0x00000002) //!< Bit mask for USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED. + +//! @brief Get value of USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED from a register value. +#define BG_USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED) >> BP_USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED) + +#define BV_USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED__CHARGER_NOT_PRESENT (0x0) //!< The USB port is not connected to a charger. +#define BV_USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED__CHARGER_PRESENT (0x1) //!< A charger (either a dedicated charger or a host charger) is connected to the USB port. + +/* --- Register HW_USB_ANALOG_USB2_CHRG_DETECT_STAT, field DM_STATE[2] (RO) + * + * DM line state output of the charger detector. + */ + +#define BP_USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE (2) //!< Bit position for USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE. +#define BM_USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE (0x00000004) //!< Bit mask for USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE. + +//! @brief Get value of USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE from a register value. +#define BG_USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE) >> BP_USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE) + +/* --- Register HW_USB_ANALOG_USB2_CHRG_DETECT_STAT, field DP_STATE[3] (RO) + * + * DP line state output of the charger detector. + */ + +#define BP_USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE (3) //!< Bit position for USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE. +#define BM_USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE (0x00000008) //!< Bit mask for USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE. + +//! @brief Get value of USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE from a register value. +#define BG_USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE) >> BP_USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE) + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_USB2_MISC - USB Misc Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_USB2_MISC - USB Misc Register (RW) + * + * Reset value: 0x00000002 + * + * This register defines controls for USB. + */ +typedef union _hw_usb_analog_usb2_misc +{ + reg32_t U; + struct _hw_usb_analog_usb2_misc_bitfields + { + unsigned HS_USE_EXTERNAL_R : 1; //!< [0] Use external resistor to generate the current bias for the high speed transmitter. + unsigned EN_DEGLITCH : 1; //!< [1] Enable the deglitching circuit of the USB PLL output. + unsigned RESERVED0 : 28; //!< [29:2] Reserved. + unsigned EN_CLK_UTMI : 1; //!< [30] Enables the clk to the UTMI block. + unsigned RESERVED1 : 1; //!< [31] Reserved. + } B; +} hw_usb_analog_usb2_misc_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_USB2_MISC register + */ +#define HW_USB_ANALOG_USB2_MISC_ADDR (REGS_USB_ANALOG_BASE + 0x250) +#define HW_USB_ANALOG_USB2_MISC_SET_ADDR (HW_USB_ANALOG_USB2_MISC_ADDR + 0x4) +#define HW_USB_ANALOG_USB2_MISC_CLR_ADDR (HW_USB_ANALOG_USB2_MISC_ADDR + 0x8) +#define HW_USB_ANALOG_USB2_MISC_TOG_ADDR (HW_USB_ANALOG_USB2_MISC_ADDR + 0xC) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_USB2_MISC (*(volatile hw_usb_analog_usb2_misc_t *) HW_USB_ANALOG_USB2_MISC_ADDR) +#define HW_USB_ANALOG_USB2_MISC_RD() (HW_USB_ANALOG_USB2_MISC.U) +#define HW_USB_ANALOG_USB2_MISC_WR(v) (HW_USB_ANALOG_USB2_MISC.U = (v)) +#define HW_USB_ANALOG_USB2_MISC_SET(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_MISC_SET_ADDR) = (v)) +#define HW_USB_ANALOG_USB2_MISC_CLR(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_MISC_CLR_ADDR) = (v)) +#define HW_USB_ANALOG_USB2_MISC_TOG(v) ((*(volatile reg32_t *) HW_USB_ANALOG_USB2_MISC_TOG_ADDR) = (v)) +#endif + +/* + * constants & macros for individual USB_ANALOG_USB2_MISC bitfields + */ + +/* --- Register HW_USB_ANALOG_USB2_MISC, field HS_USE_EXTERNAL_R[0] (RW) + * + * Use external resistor to generate the current bias for the high speed transmitter. This bit + * should not be changed unless recommended by Freescale. + */ + +#define BP_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R (0) //!< Bit position for USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R. +#define BM_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R (0x00000001) //!< Bit mask for USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R. + +//! @brief Get value of USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R from a register value. +#define BG_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R) >> BP_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R) + +//! @brief Format value for bitfield USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R. +#define BF_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R) & BM_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HS_USE_EXTERNAL_R field to a new value. +#define BW_USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R(v) BF_CS1(USB_ANALOG_USB2_MISC, HS_USE_EXTERNAL_R, v) +#endif + +/* --- Register HW_USB_ANALOG_USB2_MISC, field EN_DEGLITCH[1] (RW) + * + * Enable the deglitching circuit of the USB PLL output. + */ + +#define BP_USB_ANALOG_USB2_MISC_EN_DEGLITCH (1) //!< Bit position for USB_ANALOG_USB2_MISC_EN_DEGLITCH. +#define BM_USB_ANALOG_USB2_MISC_EN_DEGLITCH (0x00000002) //!< Bit mask for USB_ANALOG_USB2_MISC_EN_DEGLITCH. + +//! @brief Get value of USB_ANALOG_USB2_MISC_EN_DEGLITCH from a register value. +#define BG_USB_ANALOG_USB2_MISC_EN_DEGLITCH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_MISC_EN_DEGLITCH) >> BP_USB_ANALOG_USB2_MISC_EN_DEGLITCH) + +//! @brief Format value for bitfield USB_ANALOG_USB2_MISC_EN_DEGLITCH. +#define BF_USB_ANALOG_USB2_MISC_EN_DEGLITCH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_MISC_EN_DEGLITCH) & BM_USB_ANALOG_USB2_MISC_EN_DEGLITCH) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_DEGLITCH field to a new value. +#define BW_USB_ANALOG_USB2_MISC_EN_DEGLITCH(v) BF_CS1(USB_ANALOG_USB2_MISC, EN_DEGLITCH, v) +#endif + +/* --- Register HW_USB_ANALOG_USB2_MISC, field EN_CLK_UTMI[30] (RW) + * + * Enables the clk to the UTMI block. + */ + +#define BP_USB_ANALOG_USB2_MISC_EN_CLK_UTMI (30) //!< Bit position for USB_ANALOG_USB2_MISC_EN_CLK_UTMI. +#define BM_USB_ANALOG_USB2_MISC_EN_CLK_UTMI (0x40000000) //!< Bit mask for USB_ANALOG_USB2_MISC_EN_CLK_UTMI. + +//! @brief Get value of USB_ANALOG_USB2_MISC_EN_CLK_UTMI from a register value. +#define BG_USB_ANALOG_USB2_MISC_EN_CLK_UTMI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_USB2_MISC_EN_CLK_UTMI) >> BP_USB_ANALOG_USB2_MISC_EN_CLK_UTMI) + +//! @brief Format value for bitfield USB_ANALOG_USB2_MISC_EN_CLK_UTMI. +#define BF_USB_ANALOG_USB2_MISC_EN_CLK_UTMI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USB_ANALOG_USB2_MISC_EN_CLK_UTMI) & BM_USB_ANALOG_USB2_MISC_EN_CLK_UTMI) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EN_CLK_UTMI field to a new value. +#define BW_USB_ANALOG_USB2_MISC_EN_CLK_UTMI(v) BF_CS1(USB_ANALOG_USB2_MISC, EN_CLK_UTMI, v) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USB_ANALOG_DIGPROG - Chip Silicon Version +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USB_ANALOG_DIGPROG - Chip Silicon Version (RO) + * + * Reset value: 0x00000000 + * + * The DIGPROG register returns the digital program ID for the silicon. + */ +typedef union _hw_usb_analog_digprog +{ + reg32_t U; + struct _hw_usb_analog_digprog_bitfields + { + unsigned MINOR : 8; //!< [7:0] Fixed read-only value reflecting the MINOR field of the RTL version. + unsigned MAJOR : 16; //!< [23:8] Fixed read-only value reflecting the MAJOR field of the RTL version. + unsigned RESERVED0 : 8; //!< [31:24] Reserved. + } B; +} hw_usb_analog_digprog_t; +#endif + +/* + * constants & macros for entire USB_ANALOG_DIGPROG register + */ +#define HW_USB_ANALOG_DIGPROG_ADDR (REGS_USB_ANALOG_BASE + 0x260) + +#ifndef __LANGUAGE_ASM__ +#define HW_USB_ANALOG_DIGPROG (*(volatile hw_usb_analog_digprog_t *) HW_USB_ANALOG_DIGPROG_ADDR) +#define HW_USB_ANALOG_DIGPROG_RD() (HW_USB_ANALOG_DIGPROG.U) +#endif + +/* + * constants & macros for individual USB_ANALOG_DIGPROG bitfields + */ + +/* --- Register HW_USB_ANALOG_DIGPROG, field MINOR[7:0] (RO) + * + * Fixed read-only value reflecting the MINOR field of the RTL version. + */ + +#define BP_USB_ANALOG_DIGPROG_MINOR (0) //!< Bit position for USB_ANALOG_DIGPROG_MINOR. +#define BM_USB_ANALOG_DIGPROG_MINOR (0x000000ff) //!< Bit mask for USB_ANALOG_DIGPROG_MINOR. + +//! @brief Get value of USB_ANALOG_DIGPROG_MINOR from a register value. +#define BG_USB_ANALOG_DIGPROG_MINOR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_DIGPROG_MINOR) >> BP_USB_ANALOG_DIGPROG_MINOR) + +/* --- Register HW_USB_ANALOG_DIGPROG, field MAJOR[23:8] (RO) + * + * Fixed read-only value reflecting the MAJOR field of the RTL version. + */ + +#define BP_USB_ANALOG_DIGPROG_MAJOR (8) //!< Bit position for USB_ANALOG_DIGPROG_MAJOR. +#define BM_USB_ANALOG_DIGPROG_MAJOR (0x00ffff00) //!< Bit mask for USB_ANALOG_DIGPROG_MAJOR. + +//! @brief Get value of USB_ANALOG_DIGPROG_MAJOR from a register value. +#define BG_USB_ANALOG_DIGPROG_MAJOR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USB_ANALOG_DIGPROG_MAJOR) >> BP_USB_ANALOG_DIGPROG_MAJOR) + + +/*! + * @brief All USB_ANALOG module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_usb_analog +{ + reg32_t _reserved0[104]; + volatile hw_usb_analog_usb1_vbus_detect_t USB1_VBUS_DETECT; //!< USB VBUS Detect Register + volatile reg32_t USB1_VBUS_DETECT_SET; //!< USB VBUS Detect Register Set + volatile reg32_t USB1_VBUS_DETECT_CLR; //!< USB VBUS Detect Register Clear + volatile reg32_t USB1_VBUS_DETECT_TOG; //!< USB VBUS Detect Register Toggle + volatile hw_usb_analog_usb1_chrg_detect_t USB1_CHRG_DETECT; //!< USB Charger Detect Register + volatile reg32_t USB1_CHRG_DETECT_SET; //!< USB Charger Detect Register Set + volatile reg32_t USB1_CHRG_DETECT_CLR; //!< USB Charger Detect Register Clear + volatile reg32_t USB1_CHRG_DETECT_TOG; //!< USB Charger Detect Register Toggle + volatile hw_usb_analog_usb1_vbus_detect_stat_t USB1_VBUS_DETECT_STAT; //!< USB VBUS Detect Status Register + reg32_t _reserved1[3]; + volatile hw_usb_analog_usb1_chrg_detect_stat_t USB1_CHRG_DETECT_STAT; //!< USB Charger Detect Status Register + reg32_t _reserved2[7]; + volatile hw_usb_analog_usb1_misc_t USB1_MISC; //!< USB Misc Register + volatile reg32_t USB1_MISC_SET; //!< USB Misc Register Set + volatile reg32_t USB1_MISC_CLR; //!< USB Misc Register Clear + volatile reg32_t USB1_MISC_TOG; //!< USB Misc Register Toggle + volatile hw_usb_analog_usb2_vbus_detect_t USB2_VBUS_DETECT; //!< USB VBUS Detect Register + volatile reg32_t USB2_VBUS_DETECT_SET; //!< USB VBUS Detect Register Set + volatile reg32_t USB2_VBUS_DETECT_CLR; //!< USB VBUS Detect Register Clear + volatile reg32_t USB2_VBUS_DETECT_TOG; //!< USB VBUS Detect Register Toggle + volatile hw_usb_analog_usb2_chrg_detect_t USB2_CHRG_DETECT; //!< USB Charger Detect Register + volatile reg32_t USB2_CHRG_DETECT_SET; //!< USB Charger Detect Register Set + volatile reg32_t USB2_CHRG_DETECT_CLR; //!< USB Charger Detect Register Clear + volatile reg32_t USB2_CHRG_DETECT_TOG; //!< USB Charger Detect Register Toggle + volatile hw_usb_analog_usb2_vbus_detect_stat_t USB2_VBUS_DETECT_STAT; //!< USB VBUS Detect Status Register + reg32_t _reserved3[3]; + volatile hw_usb_analog_usb2_chrg_detect_stat_t USB2_CHRG_DETECT_STAT; //!< USB Charger Detect Status Register + reg32_t _reserved4[7]; + volatile hw_usb_analog_usb2_misc_t USB2_MISC; //!< USB Misc Register + volatile reg32_t USB2_MISC_SET; //!< USB Misc Register Set + volatile reg32_t USB2_MISC_CLR; //!< USB Misc Register Clear + volatile reg32_t USB2_MISC_TOG; //!< USB Misc Register Toggle + volatile hw_usb_analog_digprog_t DIGPROG; //!< Chip Silicon Version +} hw_usb_analog_t; +#pragma pack() + +//! @brief Macro to access all USB_ANALOG registers. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_USB_ANALOG(0). +#define HW_USB_ANALOG (*(volatile hw_usb_analog_t *) REGS_USB_ANALOG_BASE) + +#endif + + +#endif // __HW_USB_ANALOG_REGISTERS_H__ diff --git a/bsp/imx6ul/platform/include/mx6ul/registers/regsusdhc.h b/bsp/imx6ul/platform/include/mx6ul/registers/regsusdhc.h new file mode 100644 index 0000000000000000000000000000000000000000..210862393bab5036e3939bd8a5d49b64edafcbc3 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/registers/regsusdhc.h @@ -0,0 +1,7074 @@ +/* + * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. + */ + +#ifndef __HW_USDHC_REGISTERS_H__ +#define __HW_USDHC_REGISTERS_H__ + +#include "regs.h" + +/* + * i.MX6UL USDHC registers defined in this header file. + * + * - HW_USDHC_DS_ADDR - DMA System Address + * - HW_USDHC_BLK_ATT - Block Attributes + * - HW_USDHC_CMD_ARG - Command Argument + * - HW_USDHC_CMD_XFR_TYP - Command Transfer Type + * - HW_USDHC_CMD_RSP0 - Command Response0 + * - HW_USDHC_CMD_RSP1 - Command Response1 + * - HW_USDHC_CMD_RSP2 - Command Response2 + * - HW_USDHC_CMD_RSP3 - Command Response3 + * - HW_USDHC_DATA_BUFF_ACC_PORT - Data Buffer Access Port + * - HW_USDHC_PRES_STATE - Present State + * - HW_USDHC_PROT_CTRL - Protocol Control + * - HW_USDHC_SYS_CTRL - System Control + * - HW_USDHC_INT_STATUS - Interrupt Status + * - HW_USDHC_INT_STATUS_EN - Interrupt Status Enable + * - HW_USDHC_INT_SIGNAL_EN - Interrupt Signal Enable + * - HW_USDHC_AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status + * - HW_USDHC_HOST_CTRL_CAP - Host Controller Capabilities + * - HW_USDHC_WTMK_LVL - Watermark Level + * - HW_USDHC_MIX_CTRL - Mixer Control + * - HW_USDHC_FORCE_EVENT - Force Event + * - HW_USDHC_ADMA_ERR_STATUS - ADMA Error Status Register + * - HW_USDHC_ADMA_SYS_ADDR - ADMA System Address + * - HW_USDHC_DLL_CTRL - DLL (Delay Line) Control + * - HW_USDHC_DLL_STATUS - DLL Status + * - HW_USDHC_CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status + * - HW_USDHC_VEND_SPEC - Vendor Specific Register + * - HW_USDHC_MMC_BOOT - MMC Boot Register + * - HW_USDHC_VEND_SPEC2 - Vendor Specific 2 Register + * - HW_USDHC_HOST_CTRL_VER - Host Controller Version + * + * - hw_usdhc_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_USDHC_BASE +#define HW_USDHC_INSTANCE_COUNT (4) //!< Number of instances of the USDHC module. +#define HW_USDHC1 (1) //!< Instance number for USDHC1. +#define HW_USDHC2 (2) //!< Instance number for USDHC2. +#define HW_USDHC3 (3) //!< Instance number for USDHC3. +#define HW_USDHC4 (4) //!< Instance number for USDHC4. + +#define REGS_USDHC1_BASE (0x02190000) //!< Base address for USDHC instance number 1. +#define REGS_USDHC2_BASE (0x02194000) //!< Base address for USDHC instance number 2. +#define REGS_USDHC3_BASE (0x02198000) //!< Base address for USDHC instance number 3. +#define REGS_USDHC4_BASE (0x0219c000) //!< Base address for USDHC instance number 4. + +//! @brief Get the base address of USDHC by instance number. +//! @param x USDHC instance number, from 1 through 4. +#define REGS_USDHC_BASE(x) ( (x) == HW_USDHC1 ? REGS_USDHC1_BASE : (x) == HW_USDHC2 ? REGS_USDHC2_BASE : (x) == HW_USDHC3 ? REGS_USDHC3_BASE : (x) == HW_USDHC4 ? REGS_USDHC4_BASE : 0x00d00000) + +//! @brief Get the instance number given a base address. +//! @param b Base address for an instance of USDHC. +#define REGS_USDHC_INSTANCE(b) ( (b) == REGS_USDHC1_BASE ? HW_USDHC1 : (b) == REGS_USDHC2_BASE ? HW_USDHC2 : (b) == REGS_USDHC3_BASE ? HW_USDHC3 : (b) == REGS_USDHC4_BASE ? HW_USDHC4 : 0) +#endif +//@} + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_DS_ADDR - DMA System Address +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_DS_ADDR - DMA System Address (RW) + * + * Reset value: 0x00000000 + * + * This register contains the physical system memory address used for DMA transfers. + */ +typedef union _hw_usdhc_ds_addr +{ + reg32_t U; + struct _hw_usdhc_ds_addr_bitfields + { + unsigned RESERVED0 : 2; //!< [1:0] Reserved + unsigned DS_ADDR : 30; //!< [31:2] DMA System Address: This register contains the 32-bit system memory address for a DMA transfer. + } B; +} hw_usdhc_ds_addr_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_DS_ADDR register + */ +#define HW_USDHC_DS_ADDR_ADDR(x) (REGS_USDHC_BASE(x) + 0x0) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_DS_ADDR(x) (*(volatile hw_usdhc_ds_addr_t *) HW_USDHC_DS_ADDR_ADDR(x)) +#define HW_USDHC_DS_ADDR_RD(x) (HW_USDHC_DS_ADDR(x).U) +#define HW_USDHC_DS_ADDR_WR(x, v) (HW_USDHC_DS_ADDR(x).U = (v)) +#define HW_USDHC_DS_ADDR_SET(x, v) (HW_USDHC_DS_ADDR_WR(x, HW_USDHC_DS_ADDR_RD(x) | (v))) +#define HW_USDHC_DS_ADDR_CLR(x, v) (HW_USDHC_DS_ADDR_WR(x, HW_USDHC_DS_ADDR_RD(x) & ~(v))) +#define HW_USDHC_DS_ADDR_TOG(x, v) (HW_USDHC_DS_ADDR_WR(x, HW_USDHC_DS_ADDR_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_DS_ADDR bitfields + */ + +/* --- Register HW_USDHC_DS_ADDR, field DS_ADDR[31:2] (RW) + * + * DMA System Address: This register contains the 32-bit system memory address for a DMA transfer. + * Since the address must be word (4 bytes) align, the least 2 bits are reserved, always 0. When the + * uSDHC stops a DMA transfer, this register points to the system address of the next contiguous + * data position. It can be accessed only when no transaction is executing (i.e. after a transaction + * has stopped). Read operation during transfers may return an invalid value. The Host Driver shall + * initialize this register before starting a DMA transaction. After DMA has stopped, the system + * address of the next contiguous data position can be read from this register. This register is + * protected during a data transfer. When data lines are active, write to this register is ignored. + * The Host driver shall wait, until the DLA bit in the Present State register is cleared, before + * writing to this register. The uSDHC internal DMA does not support a virtual memory system. It + * only supports continuous physical memory access. And due to AHB burst limitations, if the burst + * must cross the 1 KB boundary, uSDHC will automatically change SEQ burst type to NSEQ. Since this + * register supports dynamic address reflecting, when TC bit is set, it automatically alters the + * value of internal address counter, so SW cannot change this register when TC bit is set. Such + * restriction is also listed in . + */ + +#define BP_USDHC_DS_ADDR_DS_ADDR (2) //!< Bit position for USDHC_DS_ADDR_DS_ADDR. +#define BM_USDHC_DS_ADDR_DS_ADDR (0xfffffffc) //!< Bit mask for USDHC_DS_ADDR_DS_ADDR. + +//! @brief Get value of USDHC_DS_ADDR_DS_ADDR from a register value. +#define BG_USDHC_DS_ADDR_DS_ADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DS_ADDR_DS_ADDR) >> BP_USDHC_DS_ADDR_DS_ADDR) + +//! @brief Format value for bitfield USDHC_DS_ADDR_DS_ADDR. +#define BF_USDHC_DS_ADDR_DS_ADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DS_ADDR_DS_ADDR) & BM_USDHC_DS_ADDR_DS_ADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DS_ADDR field to a new value. +#define BW_USDHC_DS_ADDR_DS_ADDR(x, v) (HW_USDHC_DS_ADDR_WR(x, (HW_USDHC_DS_ADDR_RD(x) & ~BM_USDHC_DS_ADDR_DS_ADDR) | BF_USDHC_DS_ADDR_DS_ADDR(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_BLK_ATT - Block Attributes +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_BLK_ATT - Block Attributes (RW) + * + * Reset value: 0x00000000 + * + * This register is used to configure the number of data blocks and the number of bytes in each + * block. + */ +typedef union _hw_usdhc_blk_att +{ + reg32_t U; + struct _hw_usdhc_blk_att_bitfields + { + unsigned BLKSIZE : 13; //!< [12:0] Transfer Block Size: This register specifies the block size for block data transfers. + unsigned RESERVED0 : 3; //!< [15:13] Reserved + unsigned BLKCNT : 16; //!< [31:16] Blocks Count For Current Transfer: This register is enabled when the Block Count Enable bit in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. + } B; +} hw_usdhc_blk_att_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_BLK_ATT register + */ +#define HW_USDHC_BLK_ATT_ADDR(x) (REGS_USDHC_BASE(x) + 0x4) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_BLK_ATT(x) (*(volatile hw_usdhc_blk_att_t *) HW_USDHC_BLK_ATT_ADDR(x)) +#define HW_USDHC_BLK_ATT_RD(x) (HW_USDHC_BLK_ATT(x).U) +#define HW_USDHC_BLK_ATT_WR(x, v) (HW_USDHC_BLK_ATT(x).U = (v)) +#define HW_USDHC_BLK_ATT_SET(x, v) (HW_USDHC_BLK_ATT_WR(x, HW_USDHC_BLK_ATT_RD(x) | (v))) +#define HW_USDHC_BLK_ATT_CLR(x, v) (HW_USDHC_BLK_ATT_WR(x, HW_USDHC_BLK_ATT_RD(x) & ~(v))) +#define HW_USDHC_BLK_ATT_TOG(x, v) (HW_USDHC_BLK_ATT_WR(x, HW_USDHC_BLK_ATT_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_BLK_ATT bitfields + */ + +/* --- Register HW_USDHC_BLK_ATT, field BLKSIZE[12:0] (RW) + * + * Transfer Block Size: This register specifies the block size for block data transfers. Values + * ranging from 1 byte up to the maximum buffer size can be set. It can be accessed only when no + * transaction is executing (i.e. after a transaction has stopped). Read operations during transfers + * may return an invalid value, and write operations will be ignored. + * + * Values: + * 000 - No data transfer + * 001 - 1 Byte + * 002 - 2 Bytes + * 003 - 3 Bytes + * 004 - 4 Bytes + * 200 - 512 Bytes + * 1FF - 511 Bytes + * 800 - 2048 Bytes + * 1000 - 4096 Bytes + */ + +#define BP_USDHC_BLK_ATT_BLKSIZE (0) //!< Bit position for USDHC_BLK_ATT_BLKSIZE. +#define BM_USDHC_BLK_ATT_BLKSIZE (0x00001fff) //!< Bit mask for USDHC_BLK_ATT_BLKSIZE. + +//! @brief Get value of USDHC_BLK_ATT_BLKSIZE from a register value. +#define BG_USDHC_BLK_ATT_BLKSIZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_BLK_ATT_BLKSIZE) >> BP_USDHC_BLK_ATT_BLKSIZE) + +//! @brief Format value for bitfield USDHC_BLK_ATT_BLKSIZE. +#define BF_USDHC_BLK_ATT_BLKSIZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_BLK_ATT_BLKSIZE) & BM_USDHC_BLK_ATT_BLKSIZE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BLKSIZE field to a new value. +#define BW_USDHC_BLK_ATT_BLKSIZE(x, v) (HW_USDHC_BLK_ATT_WR(x, (HW_USDHC_BLK_ATT_RD(x) & ~BM_USDHC_BLK_ATT_BLKSIZE) | BF_USDHC_BLK_ATT_BLKSIZE(v))) +#endif + + +/* --- Register HW_USDHC_BLK_ATT, field BLKCNT[31:16] (RW) + * + * Blocks Count For Current Transfer: This register is enabled when the Block Count Enable bit in + * the Transfer Mode register is set to 1 and is valid only for multiple block transfers. For single + * block transfer, this register will always read as 1. The Host Driver shall set this register to a + * value between 1 and the maximum block count. The uSDHC decrements the block count after each + * block transfer and stops when the count reaches zero. Setting the block count to 0 results in no + * data blocks being transferred. This register should be accessed only when no transaction is + * executing (i.e. after transactions are stopped). During data transfer, read operations on this + * register may return an invalid value and write operations are ignored. When saving transfer + * content as a result of a Suspend command, the number of blocks yet to be transferred can be + * determined by reading this register. The reading of this register should be applied after + * transfer is paused by stop at block gap operation and before sending the command marked as + * suspend. This is because when Suspend command is sent out, uSDHC will regard the current transfer + * is aborted and change BLKCNT register back to its original value instead of keeping the dynamical + * indicator of remained block count. When restoring transfer content prior to issuing a Resume + * command, the Host Driver shall restore the previously saved block count. Although the BLKCNT + * field is 0 after reset, the read of reset value is 0x1. This is because when MSBSEL bit is 鈥?鈥? + * indicating a single block transfer, the read value of BLKCNT is always 1. + * + * Values: + * 0000 - Stop Count + * 0001 - 1 block + * 0002 - 2 blocks + * FFFF - 65535 blocks + */ + +#define BP_USDHC_BLK_ATT_BLKCNT (16) //!< Bit position for USDHC_BLK_ATT_BLKCNT. +#define BM_USDHC_BLK_ATT_BLKCNT (0xffff0000) //!< Bit mask for USDHC_BLK_ATT_BLKCNT. + +//! @brief Get value of USDHC_BLK_ATT_BLKCNT from a register value. +#define BG_USDHC_BLK_ATT_BLKCNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_BLK_ATT_BLKCNT) >> BP_USDHC_BLK_ATT_BLKCNT) + +//! @brief Format value for bitfield USDHC_BLK_ATT_BLKCNT. +#define BF_USDHC_BLK_ATT_BLKCNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_BLK_ATT_BLKCNT) & BM_USDHC_BLK_ATT_BLKCNT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BLKCNT field to a new value. +#define BW_USDHC_BLK_ATT_BLKCNT(x, v) (HW_USDHC_BLK_ATT_WR(x, (HW_USDHC_BLK_ATT_RD(x) & ~BM_USDHC_BLK_ATT_BLKCNT) | BF_USDHC_BLK_ATT_BLKCNT(v))) +#endif + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_CMD_ARG - Command Argument +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_CMD_ARG - Command Argument (RW) + * + * Reset value: 0x00000000 + * + * This register contains the SD/MMC Command Argument. . + */ +typedef union _hw_usdhc_cmd_arg +{ + reg32_t U; + struct _hw_usdhc_cmd_arg_bitfields + { + unsigned CMDARG : 32; //!< [31:0] Command Argument: The SD/MMC Command Argument is specified as bits 39-8 of the Command Format in the SD or MMC Specification.This register is write protected when the Command Inhibit (CMD) bit in the Present State register is set. + } B; +} hw_usdhc_cmd_arg_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_CMD_ARG register + */ +#define HW_USDHC_CMD_ARG_ADDR(x) (REGS_USDHC_BASE(x) + 0x8) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_CMD_ARG(x) (*(volatile hw_usdhc_cmd_arg_t *) HW_USDHC_CMD_ARG_ADDR(x)) +#define HW_USDHC_CMD_ARG_RD(x) (HW_USDHC_CMD_ARG(x).U) +#define HW_USDHC_CMD_ARG_WR(x, v) (HW_USDHC_CMD_ARG(x).U = (v)) +#define HW_USDHC_CMD_ARG_SET(x, v) (HW_USDHC_CMD_ARG_WR(x, HW_USDHC_CMD_ARG_RD(x) | (v))) +#define HW_USDHC_CMD_ARG_CLR(x, v) (HW_USDHC_CMD_ARG_WR(x, HW_USDHC_CMD_ARG_RD(x) & ~(v))) +#define HW_USDHC_CMD_ARG_TOG(x, v) (HW_USDHC_CMD_ARG_WR(x, HW_USDHC_CMD_ARG_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_CMD_ARG bitfields + */ + +/* --- Register HW_USDHC_CMD_ARG, field CMDARG[31:0] (RW) + * + * Command Argument: The SD/MMC Command Argument is specified as bits 39-8 of the Command Format in + * the SD or MMC Specification.This register is write protected when the Command Inhibit (CMD) bit + * in the Present State register is set. + */ + +#define BP_USDHC_CMD_ARG_CMDARG (0) //!< Bit position for USDHC_CMD_ARG_CMDARG. +#define BM_USDHC_CMD_ARG_CMDARG (0xffffffff) //!< Bit mask for USDHC_CMD_ARG_CMDARG. + +//! @brief Get value of USDHC_CMD_ARG_CMDARG from a register value. +#define BG_USDHC_CMD_ARG_CMDARG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_ARG_CMDARG) >> BP_USDHC_CMD_ARG_CMDARG) + +//! @brief Format value for bitfield USDHC_CMD_ARG_CMDARG. +#define BF_USDHC_CMD_ARG_CMDARG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CMD_ARG_CMDARG) & BM_USDHC_CMD_ARG_CMDARG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CMDARG field to a new value. +#define BW_USDHC_CMD_ARG_CMDARG(x, v) (HW_USDHC_CMD_ARG_WR(x, (HW_USDHC_CMD_ARG_RD(x) & ~BM_USDHC_CMD_ARG_CMDARG) | BF_USDHC_CMD_ARG_CMDARG(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_CMD_XFR_TYP - Command Transfer Type +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_CMD_XFR_TYP - Command Transfer Type (RW) + * + * Reset value: 0x00000000 + * + * This register is used to control the operation of data transfers. The Host Driver shall set this + * register before issuing a command followed by a data transfer, or before issuing a Resume + * command. To prevent data loss, the uSDHC prevents writing to the bits, that are involved in the + * data transfer of this register, when data transfer is active. These bits are DPSEL, MBSEL, + * DTDSEL, AC12EN, BCEN and DMAEN. The Host Driver shall check the Command Inhibit DAT bit (CDIHB) + * and the Command Inhibit CMD bit (CIHB) in the Present State register before writing to this + * register. When the CDIHB bit in the Present State register is set, any attempt to send a command + * with data by writing to this register is ignored; when the CIHB bit is set, any write to this + * register is ignored. On sending commands with data transfer invovled, it is mandatory that the + * block size is non-zero. Besides, block count must also be non-zero, or indicated as single block + * transfer (bit 5 of this register is '0' when written), or block count is disabled (bit 1 of this + * register is '0' when written), otherwise uSDHC will ignore the sending of this command and do + * nothing. For write command, with all above restrictions, it is also mandatory that the write + * protect switch is not active (WPSPL bit of Present State Register is '1), otherwise uSDHC will + * also ignore the command. If the commands with data transfer does not receive the response in 64 + * clock cycles, i.e., response time-out, uSDHC will regard the external device does not accept the + * command and abort the data transfer. In this scenario, the driver should issue the command again + * to re-try the transfer. It is also possible that for some reason the card responds the command + * but uSDHC does not receive the response, and if it is internal DMA (either simple DMA or ADMA) + * read operation, the external system memory is over-written by the internal DMA with data sent + * back from the card. The table below shows the summary of how register settings determine the + * type of data transfer. Transfer Type Register Setting for Various Transfer Types + * Multi/Single Block Select Block Count Enable Block Count Function 0 Don't Care + * Don't Care Single Transfer 1 0 Don't Care Infinite Transfer 1 1 + * Positive Number Multiple Transfer 1 1 Zero No Data Transfer The table + * belowshows the relationship between the Command Index Check Enable and the Command CRC Check + * Enable, in regards to the Response Type bits as well as the name of the response type. + * Relationship Between Parameters and the Name of the Response Type Response Type Index + * Check Enable CRC Check Enable Name of Response Type 00 0 0 No Response + * 01 0 1 R2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 + * R1b,R5b In the SDIO specification, response type notation for R5b is not defined. R5 + * includes R5b in the SDIO specification. But R5b is defined in this specification to specify that + * the uSDHC will check the busy status after receiving a response. For example, usually CMD52 is + * used with R5, but the I/O abort command shall be used with R5b. The CRC field for R3 and R4 is + * expected to be all 1 bits. The CRC check shall be disabled for these response types. + */ +typedef union _hw_usdhc_cmd_xfr_typ +{ + reg32_t U; + struct _hw_usdhc_cmd_xfr_typ_bitfields + { + unsigned RESERVED0 : 16; //!< [15:0] Reserved + unsigned RSPTYP : 2; //!< [17:16] Response Type Select: + unsigned RESERVED1 : 1; //!< [18] Reserved + unsigned CCCEN : 1; //!< [19] Command CRC Check Enable: If this bit is set to 1, the uSDHC shall check the CRC field in the response. + unsigned CICEN : 1; //!< [20] Command Index Check Enable: If this bit is set to 1, the uSDHC will check the Index field in the response to see if it has the same value as the command index. + unsigned DPSEL : 1; //!< [21] Data Present Select: This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. + unsigned CMDTYP : 2; //!< [23:22] Command Type: There are three types of special commands: Suspend, Resume and Abort. + unsigned CMDINX : 6; //!< [29:24] Command Index: These bits shall be set to the command number that is specified in bits 45-40 of the Command-Format in the SD Memory Card Physical Layer Specification and SDIO Card Specification. + unsigned RESERVED2 : 2; //!< [31:30] Reserved + } B; +} hw_usdhc_cmd_xfr_typ_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_CMD_XFR_TYP register + */ +#define HW_USDHC_CMD_XFR_TYP_ADDR(x) (REGS_USDHC_BASE(x) + 0xc) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_CMD_XFR_TYP(x) (*(volatile hw_usdhc_cmd_xfr_typ_t *) HW_USDHC_CMD_XFR_TYP_ADDR(x)) +#define HW_USDHC_CMD_XFR_TYP_RD(x) (HW_USDHC_CMD_XFR_TYP(x).U) +#define HW_USDHC_CMD_XFR_TYP_WR(x, v) (HW_USDHC_CMD_XFR_TYP(x).U = (v)) +#define HW_USDHC_CMD_XFR_TYP_SET(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, HW_USDHC_CMD_XFR_TYP_RD(x) | (v))) +#define HW_USDHC_CMD_XFR_TYP_CLR(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, HW_USDHC_CMD_XFR_TYP_RD(x) & ~(v))) +#define HW_USDHC_CMD_XFR_TYP_TOG(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, HW_USDHC_CMD_XFR_TYP_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_CMD_XFR_TYP bitfields + */ + +/* --- Register HW_USDHC_CMD_XFR_TYP, field RSPTYP[17:16] (RW) + * + * Response Type Select: + * + * Values: + * 00 - No Response + * 01 - Response Length 136 + * 10 - Response Length 48 + * 11 - Response Length 48, check Busy after response + */ + +#define BP_USDHC_CMD_XFR_TYP_RSPTYP (16) //!< Bit position for USDHC_CMD_XFR_TYP_RSPTYP. +#define BM_USDHC_CMD_XFR_TYP_RSPTYP (0x00030000) //!< Bit mask for USDHC_CMD_XFR_TYP_RSPTYP. + +//! @brief Get value of USDHC_CMD_XFR_TYP_RSPTYP from a register value. +#define BG_USDHC_CMD_XFR_TYP_RSPTYP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_XFR_TYP_RSPTYP) >> BP_USDHC_CMD_XFR_TYP_RSPTYP) + +//! @brief Format value for bitfield USDHC_CMD_XFR_TYP_RSPTYP. +#define BF_USDHC_CMD_XFR_TYP_RSPTYP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CMD_XFR_TYP_RSPTYP) & BM_USDHC_CMD_XFR_TYP_RSPTYP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RSPTYP field to a new value. +#define BW_USDHC_CMD_XFR_TYP_RSPTYP(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, (HW_USDHC_CMD_XFR_TYP_RD(x) & ~BM_USDHC_CMD_XFR_TYP_RSPTYP) | BF_USDHC_CMD_XFR_TYP_RSPTYP(v))) +#endif + + +/* --- Register HW_USDHC_CMD_XFR_TYP, field CCCEN[19] (RW) + * + * Command CRC Check Enable: If this bit is set to 1, the uSDHC shall check the CRC field in the + * response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to + * 0, the CRC field is not checked. The number of bits checked by the CRC field value changes + * according to the length of the response. (Refer to RSPTYP[1:0] and .) + * + * Values: + * 0 - Disable + * 1 - Enable + */ + +#define BP_USDHC_CMD_XFR_TYP_CCCEN (19) //!< Bit position for USDHC_CMD_XFR_TYP_CCCEN. +#define BM_USDHC_CMD_XFR_TYP_CCCEN (0x00080000) //!< Bit mask for USDHC_CMD_XFR_TYP_CCCEN. + +//! @brief Get value of USDHC_CMD_XFR_TYP_CCCEN from a register value. +#define BG_USDHC_CMD_XFR_TYP_CCCEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_XFR_TYP_CCCEN) >> BP_USDHC_CMD_XFR_TYP_CCCEN) + +//! @brief Format value for bitfield USDHC_CMD_XFR_TYP_CCCEN. +#define BF_USDHC_CMD_XFR_TYP_CCCEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CMD_XFR_TYP_CCCEN) & BM_USDHC_CMD_XFR_TYP_CCCEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CCCEN field to a new value. +#define BW_USDHC_CMD_XFR_TYP_CCCEN(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, (HW_USDHC_CMD_XFR_TYP_RD(x) & ~BM_USDHC_CMD_XFR_TYP_CCCEN) | BF_USDHC_CMD_XFR_TYP_CCCEN(v))) +#endif + + +/* --- Register HW_USDHC_CMD_XFR_TYP, field CICEN[20] (RW) + * + * Command Index Check Enable: If this bit is set to 1, the uSDHC will check the Index field in the + * response to see if it has the same value as the command index. If it is not, it is reported as a + * Command Index Error. If this bit is set to 0, the Index field is not checked. + * + * Values: + * 0 - Disable + * 1 - Enable + */ + +#define BP_USDHC_CMD_XFR_TYP_CICEN (20) //!< Bit position for USDHC_CMD_XFR_TYP_CICEN. +#define BM_USDHC_CMD_XFR_TYP_CICEN (0x00100000) //!< Bit mask for USDHC_CMD_XFR_TYP_CICEN. + +//! @brief Get value of USDHC_CMD_XFR_TYP_CICEN from a register value. +#define BG_USDHC_CMD_XFR_TYP_CICEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_XFR_TYP_CICEN) >> BP_USDHC_CMD_XFR_TYP_CICEN) + +//! @brief Format value for bitfield USDHC_CMD_XFR_TYP_CICEN. +#define BF_USDHC_CMD_XFR_TYP_CICEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CMD_XFR_TYP_CICEN) & BM_USDHC_CMD_XFR_TYP_CICEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CICEN field to a new value. +#define BW_USDHC_CMD_XFR_TYP_CICEN(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, (HW_USDHC_CMD_XFR_TYP_RD(x) & ~BM_USDHC_CMD_XFR_TYP_CICEN) | BF_USDHC_CMD_XFR_TYP_CICEN(v))) +#endif + + +/* --- Register HW_USDHC_CMD_XFR_TYP, field DPSEL[21] (RW) + * + * Data Present Select: This bit is set to 1 to indicate that data is present and shall be + * transferred using the DAT line. It is set to 0 for the following: Commands using only the CMD + * line (e.g. CMD52). Commands with no data transfer, but using the busy signal on DAT[0] line (R1b + * or R5b e.g. CMD38) Note: In resume command, this bit shall be set, and other bits in this + * register shall be set the same as when the transfer was initially launched. When the Write + * Protect switch is on, (i.e. the WPSPL bit is active as '0'), any command with a write operation + * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is 0, writes to the + * register Transfer Type are ignored. + * + * Values: + * 0 - No Data Present + * 1 - Data Present + */ + +#define BP_USDHC_CMD_XFR_TYP_DPSEL (21) //!< Bit position for USDHC_CMD_XFR_TYP_DPSEL. +#define BM_USDHC_CMD_XFR_TYP_DPSEL (0x00200000) //!< Bit mask for USDHC_CMD_XFR_TYP_DPSEL. + +//! @brief Get value of USDHC_CMD_XFR_TYP_DPSEL from a register value. +#define BG_USDHC_CMD_XFR_TYP_DPSEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_XFR_TYP_DPSEL) >> BP_USDHC_CMD_XFR_TYP_DPSEL) + +//! @brief Format value for bitfield USDHC_CMD_XFR_TYP_DPSEL. +#define BF_USDHC_CMD_XFR_TYP_DPSEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CMD_XFR_TYP_DPSEL) & BM_USDHC_CMD_XFR_TYP_DPSEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DPSEL field to a new value. +#define BW_USDHC_CMD_XFR_TYP_DPSEL(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, (HW_USDHC_CMD_XFR_TYP_RD(x) & ~BM_USDHC_CMD_XFR_TYP_DPSEL) | BF_USDHC_CMD_XFR_TYP_DPSEL(v))) +#endif + + +/* --- Register HW_USDHC_CMD_XFR_TYP, field CMDTYP[23:22] (RW) + * + * Command Type: There are three types of special commands: Suspend, Resume and Abort. These bits + * shall be set to 00b for all other commands. Suspend Command: If the Suspend command succeeds, the + * uSDHC shall assume that the card bus has been released and that it is possible to issue the next + * command which uses the DAT line. Since the uSDHC does not monitor the content of command + * response, it does not know if the Suspend command succeeded or not. It is the Host Driver's + * responsibility to check the status of the Suspend command and send another command marked as + * Suspend to inform the uSDHC that a Suspend command was successfully issued. Refer to for more + * details. After the end bit of command is sent, the uSDHC de-asserts Read Wait for read + * transactions and stops checking busy for write transactions. In 4-bit mode, the interrupt cycle + * starts. If the Suspend command fails, the uSDHC will maintain its current state, and the Host + * Driver shall restart the transfer by setting the Continue Request bit in the Protocol Control + * register. Resume Command: The Host Driver re-starts the data transfer by restoring the registers + * saved before sending the Suspend Command and then sends the Resume Command. The uSDHC will check + * for a pending busy state before starting write transfers. Abort Command: If this command is set + * when executing a read transfer, the uSDHC will stop reads to the buffer. If this command is set + * when executing a write transfer, the uSDHC will stop driving the DAT line. After issuing the + * Abort command, the Host Driver should issue a software reset (Abort Transaction). + * + * Values: + * 00 - Normal Other commands + * 01 - Suspend CMD52 for writing Bus Suspend in CCCR + * 10 - Resume CMD52 for writing Function Select in CCCR + * 11 - Abort CMD12, CMD52 for writing I/O Abort in CCCR + */ + +#define BP_USDHC_CMD_XFR_TYP_CMDTYP (22) //!< Bit position for USDHC_CMD_XFR_TYP_CMDTYP. +#define BM_USDHC_CMD_XFR_TYP_CMDTYP (0x00c00000) //!< Bit mask for USDHC_CMD_XFR_TYP_CMDTYP. + +//! @brief Get value of USDHC_CMD_XFR_TYP_CMDTYP from a register value. +#define BG_USDHC_CMD_XFR_TYP_CMDTYP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_XFR_TYP_CMDTYP) >> BP_USDHC_CMD_XFR_TYP_CMDTYP) + +//! @brief Format value for bitfield USDHC_CMD_XFR_TYP_CMDTYP. +#define BF_USDHC_CMD_XFR_TYP_CMDTYP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CMD_XFR_TYP_CMDTYP) & BM_USDHC_CMD_XFR_TYP_CMDTYP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CMDTYP field to a new value. +#define BW_USDHC_CMD_XFR_TYP_CMDTYP(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, (HW_USDHC_CMD_XFR_TYP_RD(x) & ~BM_USDHC_CMD_XFR_TYP_CMDTYP) | BF_USDHC_CMD_XFR_TYP_CMDTYP(v))) +#endif + + +/* --- Register HW_USDHC_CMD_XFR_TYP, field CMDINX[29:24] (RW) + * + * Command Index: These bits shall be set to the command number that is specified in bits 45-40 of + * the Command-Format in the SD Memory Card Physical Layer Specification and SDIO Card + * Specification. + */ + +#define BP_USDHC_CMD_XFR_TYP_CMDINX (24) //!< Bit position for USDHC_CMD_XFR_TYP_CMDINX. +#define BM_USDHC_CMD_XFR_TYP_CMDINX (0x3f000000) //!< Bit mask for USDHC_CMD_XFR_TYP_CMDINX. + +//! @brief Get value of USDHC_CMD_XFR_TYP_CMDINX from a register value. +#define BG_USDHC_CMD_XFR_TYP_CMDINX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_XFR_TYP_CMDINX) >> BP_USDHC_CMD_XFR_TYP_CMDINX) + +//! @brief Format value for bitfield USDHC_CMD_XFR_TYP_CMDINX. +#define BF_USDHC_CMD_XFR_TYP_CMDINX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CMD_XFR_TYP_CMDINX) & BM_USDHC_CMD_XFR_TYP_CMDINX) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CMDINX field to a new value. +#define BW_USDHC_CMD_XFR_TYP_CMDINX(x, v) (HW_USDHC_CMD_XFR_TYP_WR(x, (HW_USDHC_CMD_XFR_TYP_RD(x) & ~BM_USDHC_CMD_XFR_TYP_CMDINX) | BF_USDHC_CMD_XFR_TYP_CMDINX(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_CMD_RSP0 - Command Response0 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_CMD_RSP0 - Command Response0 (RO) + * + * Reset value: 0x00000000 + * + * This register is used to store part 0 of the response bits from the card. + */ +typedef union _hw_usdhc_cmd_rsp0 +{ + reg32_t U; + struct _hw_usdhc_cmd_rsp0_bitfields + { + unsigned CMDRSP0 : 32; //!< [31:0] Command Response 0: Refer to for the mapping of command responses from the SD Bus to this register for each response type. + } B; +} hw_usdhc_cmd_rsp0_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_CMD_RSP0 register + */ +#define HW_USDHC_CMD_RSP0_ADDR(x) (REGS_USDHC_BASE(x) + 0x10) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_CMD_RSP0(x) (*(volatile hw_usdhc_cmd_rsp0_t *) HW_USDHC_CMD_RSP0_ADDR(x)) +#define HW_USDHC_CMD_RSP0_RD(x) (HW_USDHC_CMD_RSP0(x).U) +#endif + +/* + * constants & macros for individual USDHC_CMD_RSP0 bitfields + */ + +/* --- Register HW_USDHC_CMD_RSP0, field CMDRSP0[31:0] (RO) + * + * Command Response 0: Refer to for the mapping of command responses from the SD Bus to this + * register for each response type. + */ + +#define BP_USDHC_CMD_RSP0_CMDRSP0 (0) //!< Bit position for USDHC_CMD_RSP0_CMDRSP0. +#define BM_USDHC_CMD_RSP0_CMDRSP0 (0xffffffff) //!< Bit mask for USDHC_CMD_RSP0_CMDRSP0. + +//! @brief Get value of USDHC_CMD_RSP0_CMDRSP0 from a register value. +#define BG_USDHC_CMD_RSP0_CMDRSP0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_RSP0_CMDRSP0) >> BP_USDHC_CMD_RSP0_CMDRSP0) + +//------------------------------------------------------------------------------------------- +// HW_USDHC_CMD_RSP1 - Command Response1 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_CMD_RSP1 - Command Response1 (RO) + * + * Reset value: 0x00000000 + * + * This register is used to store part 1 of the response bits from the card. + */ +typedef union _hw_usdhc_cmd_rsp1 +{ + reg32_t U; + struct _hw_usdhc_cmd_rsp1_bitfields + { + unsigned CMDRSP1 : 32; //!< [31:0] Command Response 1: Refer to for the mapping of command responses from the SD Bus to this register for each response type. + } B; +} hw_usdhc_cmd_rsp1_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_CMD_RSP1 register + */ +#define HW_USDHC_CMD_RSP1_ADDR(x) (REGS_USDHC_BASE(x) + 0x14) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_CMD_RSP1(x) (*(volatile hw_usdhc_cmd_rsp1_t *) HW_USDHC_CMD_RSP1_ADDR(x)) +#define HW_USDHC_CMD_RSP1_RD(x) (HW_USDHC_CMD_RSP1(x).U) +#endif + +/* + * constants & macros for individual USDHC_CMD_RSP1 bitfields + */ + +/* --- Register HW_USDHC_CMD_RSP1, field CMDRSP1[31:0] (RO) + * + * Command Response 1: Refer to for the mapping of command responses from the SD Bus to this + * register for each response type. + */ + +#define BP_USDHC_CMD_RSP1_CMDRSP1 (0) //!< Bit position for USDHC_CMD_RSP1_CMDRSP1. +#define BM_USDHC_CMD_RSP1_CMDRSP1 (0xffffffff) //!< Bit mask for USDHC_CMD_RSP1_CMDRSP1. + +//! @brief Get value of USDHC_CMD_RSP1_CMDRSP1 from a register value. +#define BG_USDHC_CMD_RSP1_CMDRSP1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_RSP1_CMDRSP1) >> BP_USDHC_CMD_RSP1_CMDRSP1) + +//------------------------------------------------------------------------------------------- +// HW_USDHC_CMD_RSP2 - Command Response2 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_CMD_RSP2 - Command Response2 (RO) + * + * Reset value: 0x00000000 + * + * This register is used to store part 2 of the response bits from the card. + */ +typedef union _hw_usdhc_cmd_rsp2 +{ + reg32_t U; + struct _hw_usdhc_cmd_rsp2_bitfields + { + unsigned CMDRSP2 : 32; //!< [31:0] Command Response 2: Refer to for the mapping of command responses from the SD Bus to this register for each response type. + } B; +} hw_usdhc_cmd_rsp2_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_CMD_RSP2 register + */ +#define HW_USDHC_CMD_RSP2_ADDR(x) (REGS_USDHC_BASE(x) + 0x18) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_CMD_RSP2(x) (*(volatile hw_usdhc_cmd_rsp2_t *) HW_USDHC_CMD_RSP2_ADDR(x)) +#define HW_USDHC_CMD_RSP2_RD(x) (HW_USDHC_CMD_RSP2(x).U) +#endif + +/* + * constants & macros for individual USDHC_CMD_RSP2 bitfields + */ + +/* --- Register HW_USDHC_CMD_RSP2, field CMDRSP2[31:0] (RO) + * + * Command Response 2: Refer to for the mapping of command responses from the SD Bus to this + * register for each response type. + */ + +#define BP_USDHC_CMD_RSP2_CMDRSP2 (0) //!< Bit position for USDHC_CMD_RSP2_CMDRSP2. +#define BM_USDHC_CMD_RSP2_CMDRSP2 (0xffffffff) //!< Bit mask for USDHC_CMD_RSP2_CMDRSP2. + +//! @brief Get value of USDHC_CMD_RSP2_CMDRSP2 from a register value. +#define BG_USDHC_CMD_RSP2_CMDRSP2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_RSP2_CMDRSP2) >> BP_USDHC_CMD_RSP2_CMDRSP2) + +//------------------------------------------------------------------------------------------- +// HW_USDHC_CMD_RSP3 - Command Response3 +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_CMD_RSP3 - Command Response3 (RO) + * + * Reset value: 0x00000000 + * + * This register is used to store part 3 of the response bits from the card. The table below + * describes the mapping of command responses from the SD Bus to Command Response registers for each + * response type. In the table, R[ ] refers to a bit range within the response data as transmitted + * on the SD Bus. Response Bit Definition for Each Response Type Response Type Meaning + * of Response Response Field Response Register R1,R1b (normal response) Card Status + * R[39:8] CMDRSP0 R1b (Auto CMD12 response) Card Status for Auto CMD12 R[39:8] + * CMDRSP3 R2 (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], + * CMDRSP2, CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] + * CMDRSP0 R4 (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b + * SDIO response R[39:8] CMDRSP0 R6 (Publish RCA) New Published RCA[31:16] and card + * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48 + * (R[47:0]) have 32-bits of the response data (R[39:8]) stored in the CMDRSP0 register. Responses + * of type R1b (Auto CMD12 responses) have response data bits (R[39:8]) stored in the CMDRSP3 + * register. Responses with length 136 (R[135:0]) have 120-bits of the response data (R[127:8]) + * stored in the CMDRSP0, 1, 2, and 3 registers. To be able to read the response status + * efficiently, the uSDHC only stores part of the response data in the Command Response registers. + * This enables the Host Driver to efficiently read 32-bits of response data in one read cycle on a + * 32-bit bus system. Parts of the response, the Index field and the CRC, are checked by the uSDHC + * (as specified by the Command Index Check Enable and the Command CRC Check Enable bits in the + * Transfer Type register) and generate an error interrupt if any error is detected. The bit range + * for the CRC check depends on the response length. If the response length is 48, the uSDHC will + * check R[47:1], and if the response length is 136 the uSDHC will check R[119:1]. Since the uSDHC + * may have a multiple block data transfer executing concurrently with a CMD_wo_DAT command, the + * uSDHC stores the Auto CMD12 response in the CMDRSP3 register. The CMD_wo_DAT response is stored + * in CMDRSP0. This allows the uSDHC to avoid overwriting the Auto CMD12 response with the + * CMD_wo_DAT and vice versa. When the uSDHC modifies part of the Command Response registers, as + * shown in the table above, it preserves the unmodified bits. + */ +typedef union _hw_usdhc_cmd_rsp3 +{ + reg32_t U; + struct _hw_usdhc_cmd_rsp3_bitfields + { + unsigned CMDRSP3 : 32; //!< [31:0] Command Response 3: Refer to for the mapping of command responses from the SD Bus to this register for each response type. + } B; +} hw_usdhc_cmd_rsp3_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_CMD_RSP3 register + */ +#define HW_USDHC_CMD_RSP3_ADDR(x) (REGS_USDHC_BASE(x) + 0x1c) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_CMD_RSP3(x) (*(volatile hw_usdhc_cmd_rsp3_t *) HW_USDHC_CMD_RSP3_ADDR(x)) +#define HW_USDHC_CMD_RSP3_RD(x) (HW_USDHC_CMD_RSP3(x).U) +#endif + +/* + * constants & macros for individual USDHC_CMD_RSP3 bitfields + */ + +/* --- Register HW_USDHC_CMD_RSP3, field CMDRSP3[31:0] (RO) + * + * Command Response 3: Refer to for the mapping of command responses from the SD Bus to this + * register for each response type. + */ + +#define BP_USDHC_CMD_RSP3_CMDRSP3 (0) //!< Bit position for USDHC_CMD_RSP3_CMDRSP3. +#define BM_USDHC_CMD_RSP3_CMDRSP3 (0xffffffff) //!< Bit mask for USDHC_CMD_RSP3_CMDRSP3. + +//! @brief Get value of USDHC_CMD_RSP3_CMDRSP3 from a register value. +#define BG_USDHC_CMD_RSP3_CMDRSP3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CMD_RSP3_CMDRSP3) >> BP_USDHC_CMD_RSP3_CMDRSP3) + +//------------------------------------------------------------------------------------------- +// HW_USDHC_DATA_BUFF_ACC_PORT - Data Buffer Access Port +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_DATA_BUFF_ACC_PORT - Data Buffer Access Port (RW) + * + * Reset value: 0x00000000 + * + * This is a 32-bit data port register used to access the internal buffer. + */ +typedef union _hw_usdhc_data_buff_acc_port +{ + reg32_t U; + struct _hw_usdhc_data_buff_acc_port_bitfields + { + unsigned DATCONT : 32; //!< [31:0] Data Content: The Buffer Data Port register is for 32-bit data access by the ARM platform or the external DMA. + } B; +} hw_usdhc_data_buff_acc_port_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_DATA_BUFF_ACC_PORT register + */ +#define HW_USDHC_DATA_BUFF_ACC_PORT_ADDR(x) (REGS_USDHC_BASE(x) + 0x20) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_DATA_BUFF_ACC_PORT(x) (*(volatile hw_usdhc_data_buff_acc_port_t *) HW_USDHC_DATA_BUFF_ACC_PORT_ADDR(x)) +#define HW_USDHC_DATA_BUFF_ACC_PORT_RD(x) (HW_USDHC_DATA_BUFF_ACC_PORT(x).U) +#define HW_USDHC_DATA_BUFF_ACC_PORT_WR(x, v) (HW_USDHC_DATA_BUFF_ACC_PORT(x).U = (v)) +#define HW_USDHC_DATA_BUFF_ACC_PORT_SET(x, v) (HW_USDHC_DATA_BUFF_ACC_PORT_WR(x, HW_USDHC_DATA_BUFF_ACC_PORT_RD(x) | (v))) +#define HW_USDHC_DATA_BUFF_ACC_PORT_CLR(x, v) (HW_USDHC_DATA_BUFF_ACC_PORT_WR(x, HW_USDHC_DATA_BUFF_ACC_PORT_RD(x) & ~(v))) +#define HW_USDHC_DATA_BUFF_ACC_PORT_TOG(x, v) (HW_USDHC_DATA_BUFF_ACC_PORT_WR(x, HW_USDHC_DATA_BUFF_ACC_PORT_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_DATA_BUFF_ACC_PORT bitfields + */ + +/* --- Register HW_USDHC_DATA_BUFF_ACC_PORT, field DATCONT[31:0] (RW) + * + * Data Content: The Buffer Data Port register is for 32-bit data access by the ARM platform or the + * external DMA. When the internal DMA is enabled, any write to this register is ignored, and any + * read from this register will always yield 0s. + */ + +#define BP_USDHC_DATA_BUFF_ACC_PORT_DATCONT (0) //!< Bit position for USDHC_DATA_BUFF_ACC_PORT_DATCONT. +#define BM_USDHC_DATA_BUFF_ACC_PORT_DATCONT (0xffffffff) //!< Bit mask for USDHC_DATA_BUFF_ACC_PORT_DATCONT. + +//! @brief Get value of USDHC_DATA_BUFF_ACC_PORT_DATCONT from a register value. +#define BG_USDHC_DATA_BUFF_ACC_PORT_DATCONT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DATA_BUFF_ACC_PORT_DATCONT) >> BP_USDHC_DATA_BUFF_ACC_PORT_DATCONT) + +//! @brief Format value for bitfield USDHC_DATA_BUFF_ACC_PORT_DATCONT. +#define BF_USDHC_DATA_BUFF_ACC_PORT_DATCONT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DATA_BUFF_ACC_PORT_DATCONT) & BM_USDHC_DATA_BUFF_ACC_PORT_DATCONT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DATCONT field to a new value. +#define BW_USDHC_DATA_BUFF_ACC_PORT_DATCONT(x, v) (HW_USDHC_DATA_BUFF_ACC_PORT_WR(x, (HW_USDHC_DATA_BUFF_ACC_PORT_RD(x) & ~BM_USDHC_DATA_BUFF_ACC_PORT_DATCONT) | BF_USDHC_DATA_BUFF_ACC_PORT_DATCONT(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_PRES_STATE - Present State +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_PRES_STATE - Present State (RO) + * + * Reset value: 0x00000000 + * + * The Host Driver can get status of the uSDHC from this 32-bit read only register. The Host + * Driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for SDIO) when the DAT lines are busy + * during a data transfer. These commands can be issued when Command Inhibit (CMD) is set to zero. + * Other commands shall be issued when Command Inhibit (DAT) is set to zero. Possible changes to the + * SD Physical Specification may add other commands to this list in the future. Note: the reset + * value of Present State Register depend on testbench connectivity. + */ +typedef union _hw_usdhc_pres_state +{ + reg32_t U; + struct _hw_usdhc_pres_state_bitfields + { + unsigned CIHB : 1; //!< [0] Command Inhibit (CMD): If this status bit is 0, it indicates that the CMD line is not in use and the uSDHC can issue a SD/MMC Command using the CMD line. + unsigned CDIHB : 1; //!< [1] Command Inhibit (DAT): This status bit is generated if either the DAT Line Active or the Read Transfer Active is set to 1. + unsigned DLA : 1; //!< [2] Data Line Active This status bit indicates whether one of the DAT lines on the SD Bus is in use. + unsigned SDSTB : 1; //!< [3] SD Clock Stable This status bit indicates that the internal card clock is stable. + unsigned IPGOFF : 1; //!< [4] ipg_clk Gated Off Internally: This status bit indicates that the ipg_clk is internally gated off. + unsigned HCKOFF : 1; //!< [5] hclk Gated Off Internally: This status bit indicates that the hclk is internally gated off. + unsigned PEROFF : 1; //!< [6] ipg_perclk Gated Off Internally: This status bit indicates that the ipg_perclk is internally gated off. + unsigned SDOFF : 1; //!< [7] SD Clock Gated Off Internally: This status bit indicates that the SD Clock is internally gated off, because of buffer over/under-run or read pause without read wait assertion, or the driver set FRC_SDCLK_ON bit is 0 to stop the SD clock in idle status. + unsigned WTA : 1; //!< [8] Write Transfer Active: This status bit indicates a write transfer is active. + unsigned RTA : 1; //!< [9] Read Transfer Active: This status bit is used for detecting completion of a read transfer. + unsigned BWEN : 1; //!< [10] Buffer Write Enable: This status bit is used for non-DMA write transfers. + unsigned BREN : 1; //!< [11] Buffer Read Enable: This status bit is used for non-DMA read transfers. + unsigned RTR : 1; //!< [12] Re-Tuning Request: (only for SD3.0 SDR104 mode) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. + unsigned RESERVED0 : 3; //!< [15:13] Reserved + unsigned CINST : 1; //!< [16] Card Inserted: This bit indicates whether a card has been inserted. + unsigned RESERVED1 : 1; //!< [17] Reserved + unsigned CDPL : 1; //!< [18] Card Detect Pin Level: This bit reflects the inverse value of the CD# pin for the card socket. + unsigned WPSPL : 1; //!< [19] Write Protect Switch Pin Level: The Write Protect Switch is supported for memory and combo cards.This bit reflects the inverted value of the WP pin of the card socket. + unsigned RESERVED2 : 3; //!< [22:20] Reserved + unsigned CLSL : 1; //!< [23] CMD Line Signal Level: This status is used to check the CMD line level to recover from errors, and for debugging. + unsigned DLSL : 8; //!< [31:24] DAT[7:0] Line Signal Level: This status is used to check the DAT line level to recover from errors, and for debugging.This is especially useful in detecting the busy signal level from DAT[0]. + } B; +} hw_usdhc_pres_state_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_PRES_STATE register + */ +#define HW_USDHC_PRES_STATE_ADDR(x) (REGS_USDHC_BASE(x) + 0x24) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_PRES_STATE(x) (*(volatile hw_usdhc_pres_state_t *) HW_USDHC_PRES_STATE_ADDR(x)) +#define HW_USDHC_PRES_STATE_RD(x) (HW_USDHC_PRES_STATE(x).U) +#endif + +/* + * constants & macros for individual USDHC_PRES_STATE bitfields + */ + +/* --- Register HW_USDHC_PRES_STATE, field CIHB[0] (RO) + * + * Command Inhibit (CMD): If this status bit is 0, it indicates that the CMD line is not in use and + * the uSDHC can issue a SD/MMC Command using the CMD line. This bit is set also immediately after + * the Transfer Type register is written. This bit is cleared when the command response is received. + * Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if + * this bit is 0. Changing from 1 to 0 generates a Command Complete interrupt in the Interrupt + * Status register. If the uSDHC cannot issue the command because of a command conflict error (Refer + * to Command CRC Error) or because of a Command Not Issued By Auto CMD12 Error, this bit will + * remain 1 and the Command Complete is not set. The Status of issuing an Auto CMD12 does not show + * on this bit. + * + * Values: + * 0 - Can issue command using only CMD line + * 1 - Cannot issue command + */ + +#define BP_USDHC_PRES_STATE_CIHB (0) //!< Bit position for USDHC_PRES_STATE_CIHB. +#define BM_USDHC_PRES_STATE_CIHB (0x00000001) //!< Bit mask for USDHC_PRES_STATE_CIHB. + +//! @brief Get value of USDHC_PRES_STATE_CIHB from a register value. +#define BG_USDHC_PRES_STATE_CIHB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_CIHB) >> BP_USDHC_PRES_STATE_CIHB) + + +/* --- Register HW_USDHC_PRES_STATE, field CDIHB[1] (RO) + * + * Command Inhibit (DAT): This status bit is generated if either the DAT Line Active or the Read + * Transfer Active is set to 1. If this bit is 0, it indicates that the uSDHC can issue the next + * SD/MMC Command. Commands with a busy signal belong to Command Inhibit (DAT) (e.g. R1b, R5b type). + * Except in the case when the command busy is finished, changing from 1 to 0 generates a Transfer + * Complete interrupt in the Interrupt Status register. Note: The SD Host Driver can save registers + * for a suspend transaction after this bit has changed from 1 to 0. + * + * Values: + * 0 - Can issue command which uses the DAT line + * 1 - Cannot issue command which uses the DAT line + */ + +#define BP_USDHC_PRES_STATE_CDIHB (1) //!< Bit position for USDHC_PRES_STATE_CDIHB. +#define BM_USDHC_PRES_STATE_CDIHB (0x00000002) //!< Bit mask for USDHC_PRES_STATE_CDIHB. + +//! @brief Get value of USDHC_PRES_STATE_CDIHB from a register value. +#define BG_USDHC_PRES_STATE_CDIHB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_CDIHB) >> BP_USDHC_PRES_STATE_CDIHB) + + +/* --- Register HW_USDHC_PRES_STATE, field DLA[2] (RO) + * + * Data Line Active This status bit indicates whether one of the DAT lines on the SD Bus is in use. + * In the case of read transactions: This status indicates if a read transfer is executing on the SD + * Bus. Changes in this value from 1 to 0, between data blocks, generates a Block Gap Event + * interrupt in the Interrupt Status register. This bit will be set in either of the following + * cases: After the end bit of the read command. When writing a 1 to the Continue Request bit in the + * Protocol Control register to restart a read transfer. This bit will be cleared in either of the + * following cases: (1) When the end bit of the last data block is sent from the SD Bus to the + * uSDHC. (2) When the Read Wait state is stopped by a Suspend command and the DAT2 line is + * released. The uSDHC will wait at the next block gap by driving Read Wait at the start of the + * interrupt cycle. If the Read Wait signal is already driven (data buffer cannot receive data), the + * uSDHC can wait for a current block gap by continuing to drive the Read Wait signal. It is + * necessary to support Read Wait in order to use the suspend / resume function. This bit will + * remain 1 during Read Wait. In the case of write transactions: This status indicates that a write + * transfer is executing on the SD Bus. Changes in this value from 1 to 0 generate a Transfer + * Complete interrupt in the Interrupt Status register. This bit will be set in either of the + * following cases: After the end bit of the write command. When writing to 1 to the Continue + * Request bit in the Protocol Control register to continue a write transfer. This bit will be + * cleared in either of the following cases: When the SD card releases Write Busy of the last data + * block, the uSDHC will also detect if the output is not busy. If the SD card does not drive the + * busy signal after the CRC status is received, the uSDHC shall assume the card drive "Not Busy". + * When the SD card releases write busy, prior to waiting for write transfer, and as a result of a + * Stop At Block Gap Request. In the case of command with busy pending: This status indicates that a + * busy state follows the command and the data line is in use. This bit will be cleared when the + * DAT0 line is released. + * + * Values: + * 0 - DAT Line Inactive + * 1 - DAT Line Active + */ + +#define BP_USDHC_PRES_STATE_DLA (2) //!< Bit position for USDHC_PRES_STATE_DLA. +#define BM_USDHC_PRES_STATE_DLA (0x00000004) //!< Bit mask for USDHC_PRES_STATE_DLA. + +//! @brief Get value of USDHC_PRES_STATE_DLA from a register value. +#define BG_USDHC_PRES_STATE_DLA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_DLA) >> BP_USDHC_PRES_STATE_DLA) + + +/* --- Register HW_USDHC_PRES_STATE, field SDSTB[3] (RO) + * + * SD Clock Stable This status bit indicates that the internal card clock is stable. This bit is for + * the Host Driver to poll clock status when changing the clock frequency. It is recommended to + * clear FRC_SDCLK_ON bit in System Control register to remove glitch on the card clock when the + * frequency is changing. Before changing clock divisor value(SDCLKFS or DVS), Host Driver should + * make sure the SDSTB bit is high. + * + * Values: + * 0 - clock is changing frequency and not stable + * 1 - clock is stable + */ + +#define BP_USDHC_PRES_STATE_SDSTB (3) //!< Bit position for USDHC_PRES_STATE_SDSTB. +#define BM_USDHC_PRES_STATE_SDSTB (0x00000008) //!< Bit mask for USDHC_PRES_STATE_SDSTB. + +//! @brief Get value of USDHC_PRES_STATE_SDSTB from a register value. +#define BG_USDHC_PRES_STATE_SDSTB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_SDSTB) >> BP_USDHC_PRES_STATE_SDSTB) + + +/* --- Register HW_USDHC_PRES_STATE, field IPGOFF[4] (RO) + * + * ipg_clk Gated Off Internally: This status bit indicates that the ipg_clk is internally gated off. + * This bit is for the Host Driver to debug. + * + * Values: + * 0 - ipg_clk is active + * 1 - ipg_clk is gated off + */ + +#define BP_USDHC_PRES_STATE_IPGOFF (4) //!< Bit position for USDHC_PRES_STATE_IPGOFF. +#define BM_USDHC_PRES_STATE_IPGOFF (0x00000010) //!< Bit mask for USDHC_PRES_STATE_IPGOFF. + +//! @brief Get value of USDHC_PRES_STATE_IPGOFF from a register value. +#define BG_USDHC_PRES_STATE_IPGOFF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_IPGOFF) >> BP_USDHC_PRES_STATE_IPGOFF) + + +/* --- Register HW_USDHC_PRES_STATE, field HCKOFF[5] (RO) + * + * hclk Gated Off Internally: This status bit indicates that the hclk is internally gated off. This + * bit is for the Host Driver to debug during a data transfer. + * + * Values: + * 0 - hclk is active + * 1 - hclk is gated off + */ + +#define BP_USDHC_PRES_STATE_HCKOFF (5) //!< Bit position for USDHC_PRES_STATE_HCKOFF. +#define BM_USDHC_PRES_STATE_HCKOFF (0x00000020) //!< Bit mask for USDHC_PRES_STATE_HCKOFF. + +//! @brief Get value of USDHC_PRES_STATE_HCKOFF from a register value. +#define BG_USDHC_PRES_STATE_HCKOFF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_HCKOFF) >> BP_USDHC_PRES_STATE_HCKOFF) + + +/* --- Register HW_USDHC_PRES_STATE, field PEROFF[6] (RO) + * + * ipg_perclk Gated Off Internally: This status bit indicates that the ipg_perclk is internally + * gated off. This bit is for the Host Driver to debug transaction on the SD bus. When + * IPG_CLK_SOFT_EN is cleared, ipg_perclk will be gated off, otherwise ipg_perclk will be always + * active. + * + * Values: + * 0 - ipg_perclk is active + * 1 - ipg_perclk is gated off + */ + +#define BP_USDHC_PRES_STATE_PEROFF (6) //!< Bit position for USDHC_PRES_STATE_PEROFF. +#define BM_USDHC_PRES_STATE_PEROFF (0x00000040) //!< Bit mask for USDHC_PRES_STATE_PEROFF. + +//! @brief Get value of USDHC_PRES_STATE_PEROFF from a register value. +#define BG_USDHC_PRES_STATE_PEROFF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_PEROFF) >> BP_USDHC_PRES_STATE_PEROFF) + + +/* --- Register HW_USDHC_PRES_STATE, field SDOFF[7] (RO) + * + * SD Clock Gated Off Internally: This status bit indicates that the SD Clock is internally gated + * off, because of buffer over/under-run or read pause without read wait assertion, or the driver + * set FRC_SDCLK_ON bit is 0 to stop the SD clock in idle status. Set IPG_PERCLK_SOFT_EN and + * CARD_CLK_SOFT_EN to 0 also gate off SD clock. This bit is for the Host Driver to debug data + * transaction on the SD bus. + * + * Values: + * 0 - SD Clock is active + * 1 - SD Clock is gated off + */ + +#define BP_USDHC_PRES_STATE_SDOFF (7) //!< Bit position for USDHC_PRES_STATE_SDOFF. +#define BM_USDHC_PRES_STATE_SDOFF (0x00000080) //!< Bit mask for USDHC_PRES_STATE_SDOFF. + +//! @brief Get value of USDHC_PRES_STATE_SDOFF from a register value. +#define BG_USDHC_PRES_STATE_SDOFF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_SDOFF) >> BP_USDHC_PRES_STATE_SDOFF) + + +/* --- Register HW_USDHC_PRES_STATE, field WTA[8] (RO) + * + * Write Transfer Active: This status bit indicates a write transfer is active. If this bit is 0, it + * means no valid write data exists in the uSDHC. This bit is set in either of the following cases: + * After the end bit of the write command. When writing 1 to the Continue Request bit in the + * Protocol Control register to restart a write transfer. This bit is cleared in either of the + * following cases: After getting the CRC status of the last data block as specified by the transfer + * count (Single and Multiple). After getting the CRC status of any block where data transmission is + * about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event + * interrupt is generated when this bit is changed to 0, as result of the Stop At Block Gap Request + * being set. This status is useful for the Host Driver in determining when to issue commands during + * Write Busy state. + * + * Values: + * 0 - No valid data + * 1 - Transferring data + */ + +#define BP_USDHC_PRES_STATE_WTA (8) //!< Bit position for USDHC_PRES_STATE_WTA. +#define BM_USDHC_PRES_STATE_WTA (0x00000100) //!< Bit mask for USDHC_PRES_STATE_WTA. + +//! @brief Get value of USDHC_PRES_STATE_WTA from a register value. +#define BG_USDHC_PRES_STATE_WTA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_WTA) >> BP_USDHC_PRES_STATE_WTA) + + +/* --- Register HW_USDHC_PRES_STATE, field RTA[9] (RO) + * + * Read Transfer Active: This status bit is used for detecting completion of a read transfer. This + * bit is set for either of the following conditions: After the end bit of the read command. When + * writing a 1 to the Continue Request bit in the Protocol Control register to restart a read + * transfer. A Transfer Complete interrupt is generated when this bit changes to 0. This bit is + * cleared for either of the following conditions: When the last data block as specified by block + * length is transferred to the System, i.e. all data are read away from uSDHC internal buffer. When + * all valid data blocks have been transferred from uSDHC internal buffer to the System and no + * current block transfers are being sent as a result of the Stop At Block Gap Request being set to + * 1. + * + * Values: + * 0 - No valid data + * 1 - Transferring data + */ + +#define BP_USDHC_PRES_STATE_RTA (9) //!< Bit position for USDHC_PRES_STATE_RTA. +#define BM_USDHC_PRES_STATE_RTA (0x00000200) //!< Bit mask for USDHC_PRES_STATE_RTA. + +//! @brief Get value of USDHC_PRES_STATE_RTA from a register value. +#define BG_USDHC_PRES_STATE_RTA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_RTA) >> BP_USDHC_PRES_STATE_RTA) + + +/* --- Register HW_USDHC_PRES_STATE, field BWEN[10] (RO) + * + * Buffer Write Enable: This status bit is used for non-DMA write transfers. The uSDHC implements an + * internal buffer to transfer data efficiently. This read only flag indicates if space is available + * for write data. If this bit is 1, valid data greater than the watermark level can be written to + * the buffer. A change of this bit from 1 to 0 occurs when some writes to the buffer(write + * DATPORT(Base + 0x20)) are made and the buffer hasn't valid space greater than the watermake + * level. . A change of this bit from 0 to 1 occurs when the buffer can hold valid data greater than + * the write watermark level and the Buffer Write Ready interrupt is generated and enabled. + * + * Values: + * 0 - Write disable + * 1 - Write enable + */ + +#define BP_USDHC_PRES_STATE_BWEN (10) //!< Bit position for USDHC_PRES_STATE_BWEN. +#define BM_USDHC_PRES_STATE_BWEN (0x00000400) //!< Bit mask for USDHC_PRES_STATE_BWEN. + +//! @brief Get value of USDHC_PRES_STATE_BWEN from a register value. +#define BG_USDHC_PRES_STATE_BWEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_BWEN) >> BP_USDHC_PRES_STATE_BWEN) + + +/* --- Register HW_USDHC_PRES_STATE, field BREN[11] (RO) + * + * Buffer Read Enable: This status bit is used for non-DMA read transfers. The uSDHC implements an + * internal buffer to transfer data efficiently. This read only flag indicates that valid data + * exists in the host side buffer. If this bit is high, valid data greater than the watermark level + * exist in the buffer. A change of this bit from 1 to 0 occurs when some reads from the buffer(read + * DATPORT(Base + 0x20)) are made and the buffer hasn't valid data greater than the watermake level. + * A change of this bit from 0 to1 occurs when there is enough valid data ready in the buffer and + * the Buffer Read Ready interrupt has been generated and enabled. + * + * Values: + * 0 - Read disable + * 1 - Read enable + */ + +#define BP_USDHC_PRES_STATE_BREN (11) //!< Bit position for USDHC_PRES_STATE_BREN. +#define BM_USDHC_PRES_STATE_BREN (0x00000800) //!< Bit mask for USDHC_PRES_STATE_BREN. + +//! @brief Get value of USDHC_PRES_STATE_BREN from a register value. +#define BG_USDHC_PRES_STATE_BREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_BREN) >> BP_USDHC_PRES_STATE_BREN) + + +/* --- Register HW_USDHC_PRES_STATE, field RTR[12] (RO) + * + * Re-Tuning Request: (only for SD3.0 SDR104 mode) Host Controller may request Host Driver to + * execute re-tuning sequence by setting this bit when the data window is shifted by temperature + * drift and a tuned sampling point does not have a good margin to receive correct data. This bit is + * cleared when a command is issued with setting Execute Tuning bit in MIXER_CTRL register. Changing + * of this bit from 0 to 1 generates Re-Tuning Event. Refer to Interrupt status registers for more + * delail. This bit isn't set to 1 if Sampling Clock Select in the MIXER_CTRL register is set to 0 + * (using fixed sampling clock). + * + * Values: + * 0 - Fixed or well tuned sampling clock + * 1 - Sampling clock needs re-tuning + */ + +#define BP_USDHC_PRES_STATE_RTR (12) //!< Bit position for USDHC_PRES_STATE_RTR. +#define BM_USDHC_PRES_STATE_RTR (0x00001000) //!< Bit mask for USDHC_PRES_STATE_RTR. + +//! @brief Get value of USDHC_PRES_STATE_RTR from a register value. +#define BG_USDHC_PRES_STATE_RTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_RTR) >> BP_USDHC_PRES_STATE_RTR) + + +/* --- Register HW_USDHC_PRES_STATE, field CINST[16] (RO) + * + * Card Inserted: This bit indicates whether a card has been inserted. The uSDHC debounces this + * signal so that the Host Driver will not need to wait for it to stabilize. Changing from a 0 to 1 + * generates a Card Insertion interrupt in the Interrupt Status register. Changing from a 1 to 0 + * generates a Card Removal interrupt in the Interrupt Status register. A write to the Force Event + * Register does not effect this bit. The Software Reset For All in the System Control register does + * not effect this bit.A software reset does not effect this bit. + * + * Values: + * 0 - Power on Reset or No Card + * 1 - Card Inserted + */ + +#define BP_USDHC_PRES_STATE_CINST (16) //!< Bit position for USDHC_PRES_STATE_CINST. +#define BM_USDHC_PRES_STATE_CINST (0x00010000) //!< Bit mask for USDHC_PRES_STATE_CINST. + +//! @brief Get value of USDHC_PRES_STATE_CINST from a register value. +#define BG_USDHC_PRES_STATE_CINST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_CINST) >> BP_USDHC_PRES_STATE_CINST) + + +/* --- Register HW_USDHC_PRES_STATE, field CDPL[18] (RO) + * + * Card Detect Pin Level: This bit reflects the inverse value of the CD# pin for the card socket. + * Debouncing is not performed on this bit. This bit may be valid, but is not guaranteed, because of + * propagation delay. Use of this bit is limited to testing since it must be debounced by software. + * A software reset does not effect this bit. A write to the Force Event Register does not effect + * this bit. The reset value is effected by the external card detection pin. This bit shows the + * value on the CD# pin (i.e. when a card is inserted in the socket, it is 0 on the CD# input, and + * consequently the CDPL reads 1.) + * + * Values: + * 0 - No card present (CD#=1) + * 1 - Card present (CD#=0) + */ + +#define BP_USDHC_PRES_STATE_CDPL (18) //!< Bit position for USDHC_PRES_STATE_CDPL. +#define BM_USDHC_PRES_STATE_CDPL (0x00040000) //!< Bit mask for USDHC_PRES_STATE_CDPL. + +//! @brief Get value of USDHC_PRES_STATE_CDPL from a register value. +#define BG_USDHC_PRES_STATE_CDPL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_CDPL) >> BP_USDHC_PRES_STATE_CDPL) + + +/* --- Register HW_USDHC_PRES_STATE, field WPSPL[19] (RO) + * + * Write Protect Switch Pin Level: The Write Protect Switch is supported for memory and combo + * cards.This bit reflects the inverted value of the WP pin of the card socket. A software reset + * does not affect this bit. The reset value is effected by the external write protect switch. If + * the WP pin is not used, it should be tied low, so that the reset value of this bit is high and + * write is enabled. + * + * Values: + * 0 - Write protected (WP=1) + * 1 - Write enabled (WP=0) + */ + +#define BP_USDHC_PRES_STATE_WPSPL (19) //!< Bit position for USDHC_PRES_STATE_WPSPL. +#define BM_USDHC_PRES_STATE_WPSPL (0x00080000) //!< Bit mask for USDHC_PRES_STATE_WPSPL. + +//! @brief Get value of USDHC_PRES_STATE_WPSPL from a register value. +#define BG_USDHC_PRES_STATE_WPSPL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_WPSPL) >> BP_USDHC_PRES_STATE_WPSPL) + + +/* --- Register HW_USDHC_PRES_STATE, field CLSL[23] (RO) + * + * CMD Line Signal Level: This status is used to check the CMD line level to recover from errors, + * and for debugging. The reset value is effected by the external pull-up/pull-down resistor, by + * default, the read value of this bit after reset is 1'b1, when the command line is pulled up. + */ + +#define BP_USDHC_PRES_STATE_CLSL (23) //!< Bit position for USDHC_PRES_STATE_CLSL. +#define BM_USDHC_PRES_STATE_CLSL (0x00800000) //!< Bit mask for USDHC_PRES_STATE_CLSL. + +//! @brief Get value of USDHC_PRES_STATE_CLSL from a register value. +#define BG_USDHC_PRES_STATE_CLSL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_CLSL) >> BP_USDHC_PRES_STATE_CLSL) + +/* --- Register HW_USDHC_PRES_STATE, field DLSL[31:24] (RO) + * + * DAT[7:0] Line Signal Level: This status is used to check the DAT line level to recover from + * errors, and for debugging.This is especially useful in detecting the busy signal level from + * DAT[0]. The reset value is effected by the external pull-up/pull-down resistors. By default, the + * read value of this bit field after reset is 8'b11110111, when DAT[3] is pulled down and the other + * lines are pulled up. DAT[7]: Data 7 line signal level DAT[6]: Data 6 line signal level DAT[5]: + * Data 5 line signal level DAT[4]: Data 4 line signal level DAT[3]: Data 3 line signal level + * DAT[2]: Data 2 line signal level DAT[1]: Data 1 line signal level DAT[0]: Data 0 line signal + * level + */ + +#define BP_USDHC_PRES_STATE_DLSL (24) //!< Bit position for USDHC_PRES_STATE_DLSL. +#define BM_USDHC_PRES_STATE_DLSL (0xff000000) //!< Bit mask for USDHC_PRES_STATE_DLSL. + +//! @brief Get value of USDHC_PRES_STATE_DLSL from a register value. +#define BG_USDHC_PRES_STATE_DLSL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PRES_STATE_DLSL) >> BP_USDHC_PRES_STATE_DLSL) + +//------------------------------------------------------------------------------------------- +// HW_USDHC_PROT_CTRL - Protocol Control +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_PROT_CTRL - Protocol Control (RW) + * + * Reset value: 0x08800020 + * + * There are three cases to restart the transfer after stop at the block gap. Which case is + * appropriate depends on whether the uSDHC issues a Suspend command or the SD card accepts the + * Suspend command. If the Host Driver does not issue a Suspend command, the Continue Request + * shall be used to restart the transfer. If the Host Driver issues a Suspend command and the SD + * card accepts it, a Resume command shall be used to restart the transfer. If the Host Driver + * issues a Suspend command and the SD card does not accept it, the Continue Request shall be used + * to restart the transfer. Any time Stop At Block Gap Request stops the data transfer, the Host + * Driver shall wait for a Transfer Complete (in the Interrupt Status register), before attempting + * to restart the transfer. When restarting the data transfer by Continue Request, the Host Driver + * shall clear the Stop At Block Gap Request before or simultaneously. + */ +typedef union _hw_usdhc_prot_ctrl +{ + reg32_t U; + struct _hw_usdhc_prot_ctrl_bitfields + { + unsigned LCTL : 1; //!< [0] LED Control: This bit, fully controlled by the Host Driver, is used to caution the user not to remove the card while the card is being accessed. + unsigned DTW : 2; //!< [2:1] Data Transfer Width: This bit selects the data width of the SD bus for a data transfer. + unsigned D3CD : 1; //!< [3] DAT3 as Card Detection Pin: If this bit is set, DAT3 should be pulled down to act as a card detection pin. + unsigned EMODE : 2; //!< [5:4] Endian Mode: The uSDHC supports all four endian modes in data transfer. + unsigned CDTL : 1; //!< [6] Card Detect Test Level: This is bit is enabled while the Card Detection Signal Selection is set to 1 and it indicates card insertion. + unsigned CDSS : 1; //!< [7] Card Detect Signal Selection: This bit selects the source for the card detection. + unsigned DMASEL : 2; //!< [9:8] DMA Select: This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA operation. + unsigned RESERVED0 : 6; //!< [15:10] Reserved + unsigned SABGREQ : 1; //!< [16] Stop At Block Gap Request: This bit is used to stop executing a transaction at the next block gap for both DMA and non-DMA transfers. + unsigned CREQ : 1; //!< [17] Continue Request: This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. + unsigned RWCTL : 1; //!< [18] Read Wait Control: The read wait function is optional for SDIO cards. + unsigned IABG : 1; //!< [19] Interrupt At Block Gap: This bit is valid only in 4-bit mode, of the SDIO card, and selects a sample point in the interrupt cycle. + unsigned RD_DONE_NO_8CLK : 1; //!< [20] Read done no 8 clock: According to the SD/MMC spec, for read data transaction, 8 clocks are needed after the end bit of the last data block. + unsigned RD_WAIT_POINT : 3; //!< [23:21] Read wait point : This is only for debug purpose. + unsigned WECINT : 1; //!< [24] Wakeup Event Enable On Card Interrupt: This bit enables a wakeup event, via a Card Interrupt, in the Interrupt Status register. + unsigned WECINS : 1; //!< [25] Wakeup Event Enable On SD Card Insertion: This bit enables a wakeup event, via a Card Insertion, in the Interrupt Status register. + unsigned WECRM : 1; //!< [26] Wakeup Event Enable On SD Card Removal: This bit enables a wakeup event, via a Card Removal, in the Interrupt Status register. + unsigned BURST_LEN_EN : 3; //!< [29:27] BURST length enable for INCR, INCR4/INCR8/INCR16, INCR4-WRAP/INCR8-WRAP/INCR16-WRAP This is used to enable/disable the burst length for the external AHB2AXI bridge. + unsigned NON_EXACT_BLK_RD : 1; //!< [30] Current block read is non-exact block read. + unsigned RD_NO8CLK_EN : 1; //!< [31] Only for debug. + } B; +} hw_usdhc_prot_ctrl_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_PROT_CTRL register + */ +#define HW_USDHC_PROT_CTRL_ADDR(x) (REGS_USDHC_BASE(x) + 0x28) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_PROT_CTRL(x) (*(volatile hw_usdhc_prot_ctrl_t *) HW_USDHC_PROT_CTRL_ADDR(x)) +#define HW_USDHC_PROT_CTRL_RD(x) (HW_USDHC_PROT_CTRL(x).U) +#define HW_USDHC_PROT_CTRL_WR(x, v) (HW_USDHC_PROT_CTRL(x).U = (v)) +#define HW_USDHC_PROT_CTRL_SET(x, v) (HW_USDHC_PROT_CTRL_WR(x, HW_USDHC_PROT_CTRL_RD(x) | (v))) +#define HW_USDHC_PROT_CTRL_CLR(x, v) (HW_USDHC_PROT_CTRL_WR(x, HW_USDHC_PROT_CTRL_RD(x) & ~(v))) +#define HW_USDHC_PROT_CTRL_TOG(x, v) (HW_USDHC_PROT_CTRL_WR(x, HW_USDHC_PROT_CTRL_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_PROT_CTRL bitfields + */ + +/* --- Register HW_USDHC_PROT_CTRL, field LCTL[0] (RW) + * + * LED Control: This bit, fully controlled by the Host Driver, is used to caution the user not to + * remove the card while the card is being accessed. If the software is going to issue multiple SD + * commands, this bit can be set during all these transactions. It is not necessary to change for + * each transaction. When the software issues multiple SD commands, setting the bit once before the + * first command is sufficient: it is not necessary to reset the bit between commands. + * + * Values: + * 0 - LED off + * 1 - LED on + */ + +#define BP_USDHC_PROT_CTRL_LCTL (0) //!< Bit position for USDHC_PROT_CTRL_LCTL. +#define BM_USDHC_PROT_CTRL_LCTL (0x00000001) //!< Bit mask for USDHC_PROT_CTRL_LCTL. + +//! @brief Get value of USDHC_PROT_CTRL_LCTL from a register value. +#define BG_USDHC_PROT_CTRL_LCTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_LCTL) >> BP_USDHC_PROT_CTRL_LCTL) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_LCTL. +#define BF_USDHC_PROT_CTRL_LCTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_LCTL) & BM_USDHC_PROT_CTRL_LCTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the LCTL field to a new value. +#define BW_USDHC_PROT_CTRL_LCTL(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_LCTL) | BF_USDHC_PROT_CTRL_LCTL(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field DTW[2:1] (RW) + * + * Data Transfer Width: This bit selects the data width of the SD bus for a data transfer. The Host + * Driver shall set it to match the data width of the card. Possible Data transfer Width is 1-bit, + * 4-bits or 8-bits. + * + * Values: + * 00 - 1-bit mode + * 01 - 4-bit mode + * 10 - 8-bit mode + * 11 - Reserved + */ + +#define BP_USDHC_PROT_CTRL_DTW (1) //!< Bit position for USDHC_PROT_CTRL_DTW. +#define BM_USDHC_PROT_CTRL_DTW (0x00000006) //!< Bit mask for USDHC_PROT_CTRL_DTW. + +//! @brief Get value of USDHC_PROT_CTRL_DTW from a register value. +#define BG_USDHC_PROT_CTRL_DTW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_DTW) >> BP_USDHC_PROT_CTRL_DTW) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_DTW. +#define BF_USDHC_PROT_CTRL_DTW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_DTW) & BM_USDHC_PROT_CTRL_DTW) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTW field to a new value. +#define BW_USDHC_PROT_CTRL_DTW(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_DTW) | BF_USDHC_PROT_CTRL_DTW(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field D3CD[3] (RW) + * + * DAT3 as Card Detection Pin: If this bit is set, DAT3 should be pulled down to act as a card + * detection pin. Be cautious when using this feature, because DAT3 is also a chip-select for the + * SPI mode. A pull-down on this pin and CMD0 may set the card into the SPI mode, which the uSDHC + * does not support. + * + * Values: + * 0 - DAT3 does not monitor Card Insertion + * 1 - DAT3 as Card Detection Pin + */ + +#define BP_USDHC_PROT_CTRL_D3CD (3) //!< Bit position for USDHC_PROT_CTRL_D3CD. +#define BM_USDHC_PROT_CTRL_D3CD (0x00000008) //!< Bit mask for USDHC_PROT_CTRL_D3CD. + +//! @brief Get value of USDHC_PROT_CTRL_D3CD from a register value. +#define BG_USDHC_PROT_CTRL_D3CD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_D3CD) >> BP_USDHC_PROT_CTRL_D3CD) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_D3CD. +#define BF_USDHC_PROT_CTRL_D3CD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_D3CD) & BM_USDHC_PROT_CTRL_D3CD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the D3CD field to a new value. +#define BW_USDHC_PROT_CTRL_D3CD(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_D3CD) | BF_USDHC_PROT_CTRL_D3CD(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field EMODE[5:4] (RW) + * + * Endian Mode: The uSDHC supports all four endian modes in data transfer. Refer to " for more + * details. + * + * Values: + * 00 - Big Endian Mode + * 01 - Half Word Big Endian Mode + * 10 - Little Endian Mode + * 11 - Reserved + */ + +#define BP_USDHC_PROT_CTRL_EMODE (4) //!< Bit position for USDHC_PROT_CTRL_EMODE. +#define BM_USDHC_PROT_CTRL_EMODE (0x00000030) //!< Bit mask for USDHC_PROT_CTRL_EMODE. + +//! @brief Get value of USDHC_PROT_CTRL_EMODE from a register value. +#define BG_USDHC_PROT_CTRL_EMODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_EMODE) >> BP_USDHC_PROT_CTRL_EMODE) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_EMODE. +#define BF_USDHC_PROT_CTRL_EMODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_EMODE) & BM_USDHC_PROT_CTRL_EMODE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EMODE field to a new value. +#define BW_USDHC_PROT_CTRL_EMODE(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_EMODE) | BF_USDHC_PROT_CTRL_EMODE(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field CDTL[6] (RW) + * + * Card Detect Test Level: This is bit is enabled while the Card Detection Signal Selection is set + * to 1 and it indicates card insertion. + * + * Values: + * 0 - Card Detect Test Level is 0, no card inserted + * 1 - Card Detect Test Level is 1, card inserted + */ + +#define BP_USDHC_PROT_CTRL_CDTL (6) //!< Bit position for USDHC_PROT_CTRL_CDTL. +#define BM_USDHC_PROT_CTRL_CDTL (0x00000040) //!< Bit mask for USDHC_PROT_CTRL_CDTL. + +//! @brief Get value of USDHC_PROT_CTRL_CDTL from a register value. +#define BG_USDHC_PROT_CTRL_CDTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_CDTL) >> BP_USDHC_PROT_CTRL_CDTL) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_CDTL. +#define BF_USDHC_PROT_CTRL_CDTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_CDTL) & BM_USDHC_PROT_CTRL_CDTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CDTL field to a new value. +#define BW_USDHC_PROT_CTRL_CDTL(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_CDTL) | BF_USDHC_PROT_CTRL_CDTL(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field CDSS[7] (RW) + * + * Card Detect Signal Selection: This bit selects the source for the card detection. + * + * Values: + * 0 - Card Detection Level is selected (for normal purpose) + * 1 - Card Detection Test Level is selected (for test purpose) + */ + +#define BP_USDHC_PROT_CTRL_CDSS (7) //!< Bit position for USDHC_PROT_CTRL_CDSS. +#define BM_USDHC_PROT_CTRL_CDSS (0x00000080) //!< Bit mask for USDHC_PROT_CTRL_CDSS. + +//! @brief Get value of USDHC_PROT_CTRL_CDSS from a register value. +#define BG_USDHC_PROT_CTRL_CDSS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_CDSS) >> BP_USDHC_PROT_CTRL_CDSS) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_CDSS. +#define BF_USDHC_PROT_CTRL_CDSS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_CDSS) & BM_USDHC_PROT_CTRL_CDSS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CDSS field to a new value. +#define BW_USDHC_PROT_CTRL_CDSS(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_CDSS) | BF_USDHC_PROT_CTRL_CDSS(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field DMASEL[9:8] (RW) + * + * DMA Select: This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA + * operation. + * + * Values: + * 00 - No DMA or Simple DMA is selected + * 01 - ADMA1 is selected + * 10 - ADMA2 is selected + * 11 - reserved + */ + +#define BP_USDHC_PROT_CTRL_DMASEL (8) //!< Bit position for USDHC_PROT_CTRL_DMASEL. +#define BM_USDHC_PROT_CTRL_DMASEL (0x00000300) //!< Bit mask for USDHC_PROT_CTRL_DMASEL. + +//! @brief Get value of USDHC_PROT_CTRL_DMASEL from a register value. +#define BG_USDHC_PROT_CTRL_DMASEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_DMASEL) >> BP_USDHC_PROT_CTRL_DMASEL) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_DMASEL. +#define BF_USDHC_PROT_CTRL_DMASEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_DMASEL) & BM_USDHC_PROT_CTRL_DMASEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DMASEL field to a new value. +#define BW_USDHC_PROT_CTRL_DMASEL(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_DMASEL) | BF_USDHC_PROT_CTRL_DMASEL(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field SABGREQ[16] (RW) + * + * Stop At Block Gap Request: This bit is used to stop executing a transaction at the next block gap + * for both DMA and non-DMA transfers. Until the Transfer Complete is set to 1, indicating a + * transfer completion, the Host Driver shall leave this bit set to 1. Clearing both the Stop At + * Block Gap Request and Continue Request does not cause the transaction to restart. Read Wait is + * used to stop the read transaction at the block gap. The uSDHC will honor the Stop At Block Gap + * Request for write transfers, but for read transfers it requires that the SDIO card support Read + * Wait. Therefore, the Host Driver shall not set this bit during read transfers unless the SDIO + * card supports Read Wait and has set the Read Wait Control to 1, otherwise the uSDHC will stop the + * SD bus clock to pause the read operation during block gap. In the case of write transfers in + * which the Host Driver writes data to the Data Port register, the Host Driver shall set this bit + * after all block data is written. If this bit is set to 1, the Host Driver shall not write data to + * the Data Port register after a block is sent. Once this bit is set, the Host Driver shall not + * clear this bit before the Transfer Complete bit in Interrupt Status Register is set, otherwise + * the uSDHCs behavior is undefined. This bit effects Read Transfer Active, Write Transfer Active, + * DAT Line Active and Command Inhibit (DAT) in the Present State register. + * + * Values: + * 0 - Transfer + * 1 - Stop + */ + +#define BP_USDHC_PROT_CTRL_SABGREQ (16) //!< Bit position for USDHC_PROT_CTRL_SABGREQ. +#define BM_USDHC_PROT_CTRL_SABGREQ (0x00010000) //!< Bit mask for USDHC_PROT_CTRL_SABGREQ. + +//! @brief Get value of USDHC_PROT_CTRL_SABGREQ from a register value. +#define BG_USDHC_PROT_CTRL_SABGREQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_SABGREQ) >> BP_USDHC_PROT_CTRL_SABGREQ) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_SABGREQ. +#define BF_USDHC_PROT_CTRL_SABGREQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_SABGREQ) & BM_USDHC_PROT_CTRL_SABGREQ) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SABGREQ field to a new value. +#define BW_USDHC_PROT_CTRL_SABGREQ(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_SABGREQ) | BF_USDHC_PROT_CTRL_SABGREQ(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field CREQ[17] (RW) + * + * Continue Request: This bit is used to restart a transaction which was stopped using the Stop At + * Block Gap Request. When a Suspend operation is not accepted by the card, it is also by setting + * this bit to restart the paused transfer. To cancel stop at the block gap, set Stop At Block Gap + * Request to 0 and set this bit to 1 to restart the transfer. The uSDHC automatically clears this + * bit, therefore it is not necessary for the Host Driver to set this bit to 0. If both Stop At + * Block Gap Request and this bit are 1, the continue request is ignored. + * + * Values: + * 0 - No effect + * 1 - Restart + */ + +#define BP_USDHC_PROT_CTRL_CREQ (17) //!< Bit position for USDHC_PROT_CTRL_CREQ. +#define BM_USDHC_PROT_CTRL_CREQ (0x00020000) //!< Bit mask for USDHC_PROT_CTRL_CREQ. + +//! @brief Get value of USDHC_PROT_CTRL_CREQ from a register value. +#define BG_USDHC_PROT_CTRL_CREQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_CREQ) >> BP_USDHC_PROT_CTRL_CREQ) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_CREQ. +#define BF_USDHC_PROT_CTRL_CREQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_CREQ) & BM_USDHC_PROT_CTRL_CREQ) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CREQ field to a new value. +#define BW_USDHC_PROT_CTRL_CREQ(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_CREQ) | BF_USDHC_PROT_CTRL_CREQ(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field RWCTL[18] (RW) + * + * Read Wait Control: The read wait function is optional for SDIO cards. If the card supports read + * wait, set this bit to enable use of the read wait protocol to stop read data using the DAT[2] + * line. Otherwise the uSDHC has to stop the SD Clock to hold read data, which restricts commands + * generation. When the Host Driver detects an SDIO card insertion, it shall set this bit according + * to the CCCR of the card. If the card does not support read wait, this bit shall never be set to + * 1, otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap during read + * operation is also supported, but the uSDHC will stop the SD Clock to pause reading operation. + * + * Values: + * 0 - Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + * 1 - Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ + * bit is set + */ + +#define BP_USDHC_PROT_CTRL_RWCTL (18) //!< Bit position for USDHC_PROT_CTRL_RWCTL. +#define BM_USDHC_PROT_CTRL_RWCTL (0x00040000) //!< Bit mask for USDHC_PROT_CTRL_RWCTL. + +//! @brief Get value of USDHC_PROT_CTRL_RWCTL from a register value. +#define BG_USDHC_PROT_CTRL_RWCTL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_RWCTL) >> BP_USDHC_PROT_CTRL_RWCTL) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_RWCTL. +#define BF_USDHC_PROT_CTRL_RWCTL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_RWCTL) & BM_USDHC_PROT_CTRL_RWCTL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RWCTL field to a new value. +#define BW_USDHC_PROT_CTRL_RWCTL(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_RWCTL) | BF_USDHC_PROT_CTRL_RWCTL(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field IABG[19] (RW) + * + * Interrupt At Block Gap: This bit is valid only in 4-bit mode, of the SDIO card, and selects a + * sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap + * for a multiple block transfer. Setting to 0 disables interrupt detection during a multiple block + * transfer. If the SDIO card can't signal an interrupt during a multiple block transfer, this bit + * should be set to 0 to avoid an inadvertent interrupt. When the Host Driver detects an SDIO card + * insertion, it shall set this bit according to the CCCR of the card. + * + * Values: + * 0 - Disabled + * 1 - Enabled + */ + +#define BP_USDHC_PROT_CTRL_IABG (19) //!< Bit position for USDHC_PROT_CTRL_IABG. +#define BM_USDHC_PROT_CTRL_IABG (0x00080000) //!< Bit mask for USDHC_PROT_CTRL_IABG. + +//! @brief Get value of USDHC_PROT_CTRL_IABG from a register value. +#define BG_USDHC_PROT_CTRL_IABG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_IABG) >> BP_USDHC_PROT_CTRL_IABG) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_IABG. +#define BF_USDHC_PROT_CTRL_IABG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_IABG) & BM_USDHC_PROT_CTRL_IABG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IABG field to a new value. +#define BW_USDHC_PROT_CTRL_IABG(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_IABG) | BF_USDHC_PROT_CTRL_IABG(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field RD_DONE_NO_8CLK[20] (RW) + * + * Read done no 8 clock: According to the SD/MMC spec, for read data transaction, 8 clocks are + * needed after the end bit of the last data block. So, by default(RD_DONE_NO_8CLK=0), 8 clocks will + * be active after the end bit of the last read data transaction. However, this 8 clocks should not + * be active if user wants to use stop at block gap(include the auto stop at block gap in boot mode) + * feature for read and the RWCTL bit(bit18) is not enabled. In this case, software should set + * RD_DONE_NO_8CLK to avoid this 8 clocks. Otherwise, the device may send extra data to uSDHC while + * uSDHC ignores these data. In a summary, this bit should be set only if the use case needs to use + * stop at block gap feature while the device can't support the read wait feature. + */ + +#define BP_USDHC_PROT_CTRL_RD_DONE_NO_8CLK (20) //!< Bit position for USDHC_PROT_CTRL_RD_DONE_NO_8CLK. +#define BM_USDHC_PROT_CTRL_RD_DONE_NO_8CLK (0x00100000) //!< Bit mask for USDHC_PROT_CTRL_RD_DONE_NO_8CLK. + +//! @brief Get value of USDHC_PROT_CTRL_RD_DONE_NO_8CLK from a register value. +#define BG_USDHC_PROT_CTRL_RD_DONE_NO_8CLK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_RD_DONE_NO_8CLK) >> BP_USDHC_PROT_CTRL_RD_DONE_NO_8CLK) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_RD_DONE_NO_8CLK. +#define BF_USDHC_PROT_CTRL_RD_DONE_NO_8CLK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_RD_DONE_NO_8CLK) & BM_USDHC_PROT_CTRL_RD_DONE_NO_8CLK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RD_DONE_NO_8CLK field to a new value. +#define BW_USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_RD_DONE_NO_8CLK) | BF_USDHC_PROT_CTRL_RD_DONE_NO_8CLK(v))) +#endif + +/* --- Register HW_USDHC_PROT_CTRL, field RD_WAIT_POINT[23:21] (RW) + * + * Read wait point : This is only for debug purpose. As a Host controller, uSDHC should pause the + * SDHC_CLK or assert the DAT[2](if read wait feature is supported by the device) to avoid the + * device to send extra data. The SDHC_CLK should be paused or the DAT[2] should be asserted in two + * clock cycles after the end bit of the last transaction. Meanwhile, because the uSDHC controller + * has async FIFO between the card interface and the internal state machine, we need this "Read wait + * point" configuration to overcome the latency which is introduced by this async FIFO. The default + * value is 0x4, which should be accurately overcome the latency. + */ + +#define BP_USDHC_PROT_CTRL_RD_WAIT_POINT (21) //!< Bit position for USDHC_PROT_CTRL_RD_WAIT_POINT. +#define BM_USDHC_PROT_CTRL_RD_WAIT_POINT (0x00e00000) //!< Bit mask for USDHC_PROT_CTRL_RD_WAIT_POINT. + +//! @brief Get value of USDHC_PROT_CTRL_RD_WAIT_POINT from a register value. +#define BG_USDHC_PROT_CTRL_RD_WAIT_POINT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_RD_WAIT_POINT) >> BP_USDHC_PROT_CTRL_RD_WAIT_POINT) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_RD_WAIT_POINT. +#define BF_USDHC_PROT_CTRL_RD_WAIT_POINT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_RD_WAIT_POINT) & BM_USDHC_PROT_CTRL_RD_WAIT_POINT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RD_WAIT_POINT field to a new value. +#define BW_USDHC_PROT_CTRL_RD_WAIT_POINT(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_RD_WAIT_POINT) | BF_USDHC_PROT_CTRL_RD_WAIT_POINT(v))) +#endif + +/* --- Register HW_USDHC_PROT_CTRL, field WECINT[24] (RW) + * + * Wakeup Event Enable On Card Interrupt: This bit enables a wakeup event, via a Card Interrupt, in + * the Interrupt Status register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set + * to 1. When this bit is set, the Card Interrupt Status and the uSDHC interrupt can be asserted + * without CLK toggling. When the wakeup feature is not enabled, the CLK must be active in order to + * assert the Card Interrupt Status and the uSDHC interrupt. + * + * Values: + * 0 - Disable + * 1 - Enable + */ + +#define BP_USDHC_PROT_CTRL_WECINT (24) //!< Bit position for USDHC_PROT_CTRL_WECINT. +#define BM_USDHC_PROT_CTRL_WECINT (0x01000000) //!< Bit mask for USDHC_PROT_CTRL_WECINT. + +//! @brief Get value of USDHC_PROT_CTRL_WECINT from a register value. +#define BG_USDHC_PROT_CTRL_WECINT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_WECINT) >> BP_USDHC_PROT_CTRL_WECINT) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_WECINT. +#define BF_USDHC_PROT_CTRL_WECINT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_WECINT) & BM_USDHC_PROT_CTRL_WECINT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WECINT field to a new value. +#define BW_USDHC_PROT_CTRL_WECINT(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_WECINT) | BF_USDHC_PROT_CTRL_WECINT(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field WECINS[25] (RW) + * + * Wakeup Event Enable On SD Card Insertion: This bit enables a wakeup event, via a Card Insertion, + * in the Interrupt Status register. FN_WUS (Wake Up Support) in CIS does not effect this bit. When + * this bit is set, the Card Insertion Status and the uSDHC interrupt can be asserted without CLK + * toggling. When the wakeup feature is not enabled, the CLK must be active in order to assert the + * Card Insertion Status and the uSDHC interrupt. + * + * Values: + * 0 - Disable + * 1 - Enable + */ + +#define BP_USDHC_PROT_CTRL_WECINS (25) //!< Bit position for USDHC_PROT_CTRL_WECINS. +#define BM_USDHC_PROT_CTRL_WECINS (0x02000000) //!< Bit mask for USDHC_PROT_CTRL_WECINS. + +//! @brief Get value of USDHC_PROT_CTRL_WECINS from a register value. +#define BG_USDHC_PROT_CTRL_WECINS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_WECINS) >> BP_USDHC_PROT_CTRL_WECINS) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_WECINS. +#define BF_USDHC_PROT_CTRL_WECINS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_WECINS) & BM_USDHC_PROT_CTRL_WECINS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WECINS field to a new value. +#define BW_USDHC_PROT_CTRL_WECINS(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_WECINS) | BF_USDHC_PROT_CTRL_WECINS(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field WECRM[26] (RW) + * + * Wakeup Event Enable On SD Card Removal: This bit enables a wakeup event, via a Card Removal, in + * the Interrupt Status register. FN_WUS (Wake Up Support) in CIS does not effect this bit. When + * this bit is set, the Card Removal Status and the uSDHC interrupt can be asserted without CLK + * toggling. When the wakeup feature is not enabled, the CLK must be active in order to assert the + * Card Removal Status and the uSDHC interrupt. + * + * Values: + * 0 - Disable + * 1 - Enable + */ + +#define BP_USDHC_PROT_CTRL_WECRM (26) //!< Bit position for USDHC_PROT_CTRL_WECRM. +#define BM_USDHC_PROT_CTRL_WECRM (0x04000000) //!< Bit mask for USDHC_PROT_CTRL_WECRM. + +//! @brief Get value of USDHC_PROT_CTRL_WECRM from a register value. +#define BG_USDHC_PROT_CTRL_WECRM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_WECRM) >> BP_USDHC_PROT_CTRL_WECRM) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_WECRM. +#define BF_USDHC_PROT_CTRL_WECRM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_WECRM) & BM_USDHC_PROT_CTRL_WECRM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WECRM field to a new value. +#define BW_USDHC_PROT_CTRL_WECRM(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_WECRM) | BF_USDHC_PROT_CTRL_WECRM(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field BURST_LEN_EN[29:27] (RW) + * + * BURST length enable for INCR, INCR4/INCR8/INCR16, INCR4-WRAP/INCR8-WRAP/INCR16-WRAP This is used + * to enable/disable the burst length for the external AHB2AXI bridge. It's useful especially for + * INCR transfer because without burst length indicator, the AHB2AXI bridge doesn't know the burst + * length in advance. Without burst length indicator, AHB INCR transfers can only be converted to + * SINGLEs in AXI side. + * + * Values: + * xx1 - Burst length is enabled for INCR + * x1x - Burst length is enabled for INCR4/INCR8/INCR16 + * 1xx - Burst length is enabled for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP + */ + +#define BP_USDHC_PROT_CTRL_BURST_LEN_EN (27) //!< Bit position for USDHC_PROT_CTRL_BURST_LEN_EN. +#define BM_USDHC_PROT_CTRL_BURST_LEN_EN (0x38000000) //!< Bit mask for USDHC_PROT_CTRL_BURST_LEN_EN. + +//! @brief Get value of USDHC_PROT_CTRL_BURST_LEN_EN from a register value. +#define BG_USDHC_PROT_CTRL_BURST_LEN_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_BURST_LEN_EN) >> BP_USDHC_PROT_CTRL_BURST_LEN_EN) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_BURST_LEN_EN. +#define BF_USDHC_PROT_CTRL_BURST_LEN_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_BURST_LEN_EN) & BM_USDHC_PROT_CTRL_BURST_LEN_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BURST_LEN_EN field to a new value. +#define BW_USDHC_PROT_CTRL_BURST_LEN_EN(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_BURST_LEN_EN) | BF_USDHC_PROT_CTRL_BURST_LEN_EN(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field NON_EXACT_BLK_RD[30] (RW) + * + * Current block read is non-exact block read. It's only used for SDIO. + * + * Values: + * 0 - The block read is exact block read. Host driver doesn't need to issue abort command to terminate + * this multi-block read. + * 1 - The block read is non-exact block read. Host driver needs to issue abort command to terminate this + * multi-block read. + */ + +#define BP_USDHC_PROT_CTRL_NON_EXACT_BLK_RD (30) //!< Bit position for USDHC_PROT_CTRL_NON_EXACT_BLK_RD. +#define BM_USDHC_PROT_CTRL_NON_EXACT_BLK_RD (0x40000000) //!< Bit mask for USDHC_PROT_CTRL_NON_EXACT_BLK_RD. + +//! @brief Get value of USDHC_PROT_CTRL_NON_EXACT_BLK_RD from a register value. +#define BG_USDHC_PROT_CTRL_NON_EXACT_BLK_RD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_NON_EXACT_BLK_RD) >> BP_USDHC_PROT_CTRL_NON_EXACT_BLK_RD) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_NON_EXACT_BLK_RD. +#define BF_USDHC_PROT_CTRL_NON_EXACT_BLK_RD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_NON_EXACT_BLK_RD) & BM_USDHC_PROT_CTRL_NON_EXACT_BLK_RD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NON_EXACT_BLK_RD field to a new value. +#define BW_USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_NON_EXACT_BLK_RD) | BF_USDHC_PROT_CTRL_NON_EXACT_BLK_RD(v))) +#endif + + +/* --- Register HW_USDHC_PROT_CTRL, field RD_NO8CLK_EN[31] (RW) + * + * Only for debug. enable S/W RD_DONE_NO_8CLK bit + * + * Values: + * 0 - Disable S/W RD_DONE_NO_8CLK, uSHDC determines if 8 clocks are needed automatically. + * 1 - S/W RD_DONE_NO_8CLK is enabled + */ + +#define BP_USDHC_PROT_CTRL_RD_NO8CLK_EN (31) //!< Bit position for USDHC_PROT_CTRL_RD_NO8CLK_EN. +#define BM_USDHC_PROT_CTRL_RD_NO8CLK_EN (0x80000000) //!< Bit mask for USDHC_PROT_CTRL_RD_NO8CLK_EN. + +//! @brief Get value of USDHC_PROT_CTRL_RD_NO8CLK_EN from a register value. +#define BG_USDHC_PROT_CTRL_RD_NO8CLK_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_PROT_CTRL_RD_NO8CLK_EN) >> BP_USDHC_PROT_CTRL_RD_NO8CLK_EN) + +//! @brief Format value for bitfield USDHC_PROT_CTRL_RD_NO8CLK_EN. +#define BF_USDHC_PROT_CTRL_RD_NO8CLK_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_PROT_CTRL_RD_NO8CLK_EN) & BM_USDHC_PROT_CTRL_RD_NO8CLK_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RD_NO8CLK_EN field to a new value. +#define BW_USDHC_PROT_CTRL_RD_NO8CLK_EN(x, v) (HW_USDHC_PROT_CTRL_WR(x, (HW_USDHC_PROT_CTRL_RD(x) & ~BM_USDHC_PROT_CTRL_RD_NO8CLK_EN) | BF_USDHC_PROT_CTRL_RD_NO8CLK_EN(v))) +#endif + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_SYS_CTRL - System Control +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_SYS_CTRL - System Control (RW) + * + * Reset value: 0x0080800f + * + + */ +typedef union _hw_usdhc_sys_ctrl +{ + reg32_t U; + struct _hw_usdhc_sys_ctrl_bitfields + { + unsigned IPGEN : 1; //!< [0] IPG Clock Enable: It's not implemented in uSDHC IP. + unsigned HCKEN : 1; //!< [1] HCLK Enable: It's not implemented in uSDHC IP. + unsigned PEREN : 1; //!< [2] Perpherial Clock Enable It's not implemented in uSDHC IP. + unsigned SDCLKEN : 1; //!< [3] SD Clock Enable It's not implemented in uSDHC IP. + unsigned DVS : 4; //!< [7:4] Divisor: This register is used to provide a more exact divisor to generate the desired SD clock frequency. + unsigned SDCLKFS : 8; //!< [15:8] SDCLK Frequency Select: This register is used to select the frequency of the SDCLK pin. + unsigned DTOCV : 4; //!< [19:16] Data Timeout Counter Value: This value determines the interval by which DAT line timeouts are detected. + unsigned RESERVED0 : 2; //!< [21:20] Reserved + unsigned RST_FIFO : 1; //!< [22] Reset the Async FIFO: Reset the Async FIFO between card interface and the internal logic. + unsigned IPP_RST_N : 1; //!< [23] This register's value will be output to CARD from pad directly for hardware reset of the card if card support this feature. + unsigned RSTA : 1; //!< [24] Software Reset For ALL: This reset effects the entire Host Controller except for the card detection circuit. + unsigned RSTC : 1; //!< [25] Software Reset For CMD Line: Only part of the command circuit is reset. + unsigned RSTD : 1; //!< [26] Software Reset For DAT Line: Only part of the data circuit is reset. + unsigned INITA : 1; //!< [27] Initialization Active: When this bit is set, 80 SD-Clocks are sent to the card. + unsigned RESERVED1 : 4; //!< [31:28] Reserved + } B; +} hw_usdhc_sys_ctrl_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_SYS_CTRL register + */ +#define HW_USDHC_SYS_CTRL_ADDR(x) (REGS_USDHC_BASE(x) + 0x2c) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_SYS_CTRL(x) (*(volatile hw_usdhc_sys_ctrl_t *) HW_USDHC_SYS_CTRL_ADDR(x)) +#define HW_USDHC_SYS_CTRL_RD(x) (HW_USDHC_SYS_CTRL(x).U) +#define HW_USDHC_SYS_CTRL_WR(x, v) (HW_USDHC_SYS_CTRL(x).U = (v)) +#define HW_USDHC_SYS_CTRL_SET(x, v) (HW_USDHC_SYS_CTRL_WR(x, HW_USDHC_SYS_CTRL_RD(x) | (v))) +#define HW_USDHC_SYS_CTRL_CLR(x, v) (HW_USDHC_SYS_CTRL_WR(x, HW_USDHC_SYS_CTRL_RD(x) & ~(v))) +#define HW_USDHC_SYS_CTRL_TOG(x, v) (HW_USDHC_SYS_CTRL_WR(x, HW_USDHC_SYS_CTRL_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_SYS_CTRL bitfields + */ + +/* --- Register HW_USDHC_SYS_CTRL, field IPGEN[0] (RW) + * + * IPG Clock Enable: It's not implemented in uSDHC IP. + */ + +#define BP_USDHC_SYS_CTRL_IPGEN (0) //!< Bit position for USDHC_SYS_CTRL_IPGEN. +#define BM_USDHC_SYS_CTRL_IPGEN (0x00000001) //!< Bit mask for USDHC_SYS_CTRL_IPGEN. + +//! @brief Get value of USDHC_SYS_CTRL_IPGEN from a register value. +#define BG_USDHC_SYS_CTRL_IPGEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_IPGEN) >> BP_USDHC_SYS_CTRL_IPGEN) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_IPGEN. +#define BF_USDHC_SYS_CTRL_IPGEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_IPGEN) & BM_USDHC_SYS_CTRL_IPGEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPGEN field to a new value. +#define BW_USDHC_SYS_CTRL_IPGEN(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_IPGEN) | BF_USDHC_SYS_CTRL_IPGEN(v))) +#endif + +/* --- Register HW_USDHC_SYS_CTRL, field HCKEN[1] (RW) + * + * HCLK Enable: It's not implemented in uSDHC IP. + */ + +#define BP_USDHC_SYS_CTRL_HCKEN (1) //!< Bit position for USDHC_SYS_CTRL_HCKEN. +#define BM_USDHC_SYS_CTRL_HCKEN (0x00000002) //!< Bit mask for USDHC_SYS_CTRL_HCKEN. + +//! @brief Get value of USDHC_SYS_CTRL_HCKEN from a register value. +#define BG_USDHC_SYS_CTRL_HCKEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_HCKEN) >> BP_USDHC_SYS_CTRL_HCKEN) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_HCKEN. +#define BF_USDHC_SYS_CTRL_HCKEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_HCKEN) & BM_USDHC_SYS_CTRL_HCKEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HCKEN field to a new value. +#define BW_USDHC_SYS_CTRL_HCKEN(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_HCKEN) | BF_USDHC_SYS_CTRL_HCKEN(v))) +#endif + +/* --- Register HW_USDHC_SYS_CTRL, field PEREN[2] (RW) + * + * Perpherial Clock Enable It's not implemented in uSDHC IP. + */ + +#define BP_USDHC_SYS_CTRL_PEREN (2) //!< Bit position for USDHC_SYS_CTRL_PEREN. +#define BM_USDHC_SYS_CTRL_PEREN (0x00000004) //!< Bit mask for USDHC_SYS_CTRL_PEREN. + +//! @brief Get value of USDHC_SYS_CTRL_PEREN from a register value. +#define BG_USDHC_SYS_CTRL_PEREN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_PEREN) >> BP_USDHC_SYS_CTRL_PEREN) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_PEREN. +#define BF_USDHC_SYS_CTRL_PEREN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_PEREN) & BM_USDHC_SYS_CTRL_PEREN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the PEREN field to a new value. +#define BW_USDHC_SYS_CTRL_PEREN(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_PEREN) | BF_USDHC_SYS_CTRL_PEREN(v))) +#endif + +/* --- Register HW_USDHC_SYS_CTRL, field SDCLKEN[3] (RW) + * + * SD Clock Enable It's not implemented in uSDHC IP. + */ + +#define BP_USDHC_SYS_CTRL_SDCLKEN (3) //!< Bit position for USDHC_SYS_CTRL_SDCLKEN. +#define BM_USDHC_SYS_CTRL_SDCLKEN (0x00000008) //!< Bit mask for USDHC_SYS_CTRL_SDCLKEN. + +//! @brief Get value of USDHC_SYS_CTRL_SDCLKEN from a register value. +#define BG_USDHC_SYS_CTRL_SDCLKEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_SDCLKEN) >> BP_USDHC_SYS_CTRL_SDCLKEN) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_SDCLKEN. +#define BF_USDHC_SYS_CTRL_SDCLKEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_SDCLKEN) & BM_USDHC_SYS_CTRL_SDCLKEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SDCLKEN field to a new value. +#define BW_USDHC_SYS_CTRL_SDCLKEN(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_SDCLKEN) | BF_USDHC_SYS_CTRL_SDCLKEN(v))) +#endif + +/* --- Register HW_USDHC_SYS_CTRL, field DVS[7:4] (RW) + * + * Divisor: This register is used to provide a more exact divisor to generate the desired SD clock + * frequency. Note the divider can even support odd divisor without deterioration of duty cycle. + * Before changing clock divisor value(SDCLKFS or DVS), Host Driver should make sure the SDSTB bit + * is high. The setting are as following: + * + * Values: + * 0 - Divisor by 1 + * 1 - Divisor by 2 + * e - Divisor by 15 + * f - Divisor by 16 + */ + +#define BP_USDHC_SYS_CTRL_DVS (4) //!< Bit position for USDHC_SYS_CTRL_DVS. +#define BM_USDHC_SYS_CTRL_DVS (0x000000f0) //!< Bit mask for USDHC_SYS_CTRL_DVS. + +//! @brief Get value of USDHC_SYS_CTRL_DVS from a register value. +#define BG_USDHC_SYS_CTRL_DVS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_DVS) >> BP_USDHC_SYS_CTRL_DVS) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_DVS. +#define BF_USDHC_SYS_CTRL_DVS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_DVS) & BM_USDHC_SYS_CTRL_DVS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DVS field to a new value. +#define BW_USDHC_SYS_CTRL_DVS(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_DVS) | BF_USDHC_SYS_CTRL_DVS(v))) +#endif + + +/* --- Register HW_USDHC_SYS_CTRL, field SDCLKFS[15:8] (RW) + * + * SDCLK Frequency Select: This register is used to select the frequency of the SDCLK pin. The + * frequency is not programmed directly, rather this register holds the prescaler (this register) + * and divisor (next register) of the Base Clock Frequency register. I n Single Data Rate + * mode(DDR_EN bit of MIXERCTRL is '0') Only the following settings are allowed: 80h) Base clock + * divided by 256 40h) Base clock divided by 128 20h) Base clock divided by 64 10h) Base clock + * divided by 32 08h) Base clock divided by 16 04h) Base clock divided by 8 02h) Base clock divided + * by 4 01h) Base clock divided by 2 00h) Base clock divided by 1 W hile in Dual Data Rate + * mode(DDR_EN bit of MIXERCTRL is '1') Only the following settings are allowed: 80h) Base clock + * divided by 512 40h) Base clock divided by 256 20h) Base clock divided by 128 10h) Base clock + * divided by 64 08h) Base clock divided by 32 04h) Base clock divided by 16 02h) Base clock divided + * by 8 01h) Base clock divided by 4 00h) Base clock divided by 2 W hen S/W changes the DDR_EN bit, + * SDCLKFS may need to be changed also ! In Single Data Rate mode, setting 00h bypasses the + * frequency prescaler of the SD Clock. Multiple bits must not be set, or the behavior of this + * prescaler is undefined. The two default divider values can be calculated by the frequency of + * ipg_perclk and the following Divisor bits. The frequency of SDCLK is set by the following + * formula: Clock Frequency = (Base Clock) / (prescaler x divisor) For example, in Single Data Rate + * mode, if the Base Clock Frequency is 96 MHz, and the target frequency is 25 MHz, then choosing + * the prescaler value of 01h and divisor value of 1h will yield 24 MHz, which is the nearest + * frequency less than or equal to the target. Similarly, to approach a clock value of 400 kHz, the + * prescaler value of 08h and divisor value of eh yields the exact clock value of 400 kHz. The reset + * value of this bit field is 80h, so if the input Base Clock (ipg_perclk) is about 96 MHz, the + * default SD Clock after reset is 375 kHz. According to the SD Physical Specification Version 1.1 + * and the SDIO Card Specification Version 1.2, the maximum SD Clock frequency is 50 MHz and shall + * never exceed this limit. B efore changing clock divisor value(SDCLKFS or DVS), Host Driver should + * make sure the SDSTB bit is high. If setting SDCLKFS and DVS can generate same clock + * frequency,(For example, in SDR mode, SDCLKFS = 01h is same as DVS = 01h.) SDCLKFS is highly + * recommended. + */ + +#define BP_USDHC_SYS_CTRL_SDCLKFS (8) //!< Bit position for USDHC_SYS_CTRL_SDCLKFS. +#define BM_USDHC_SYS_CTRL_SDCLKFS (0x0000ff00) //!< Bit mask for USDHC_SYS_CTRL_SDCLKFS. + +//! @brief Get value of USDHC_SYS_CTRL_SDCLKFS from a register value. +#define BG_USDHC_SYS_CTRL_SDCLKFS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_SDCLKFS) >> BP_USDHC_SYS_CTRL_SDCLKFS) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_SDCLKFS. +#define BF_USDHC_SYS_CTRL_SDCLKFS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_SDCLKFS) & BM_USDHC_SYS_CTRL_SDCLKFS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SDCLKFS field to a new value. +#define BW_USDHC_SYS_CTRL_SDCLKFS(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_SDCLKFS) | BF_USDHC_SYS_CTRL_SDCLKFS(v))) +#endif + +/* --- Register HW_USDHC_SYS_CTRL, field DTOCV[19:16] (RW) + * + * Data Timeout Counter Value: This value determines the interval by which DAT line timeouts are + * detected. Refer to the Data Timeout Error bit in the Interrupt Status register for information on + * factors that dictate time-out generation. Time-out clock frequency will be generated by dividing + * the base clock SDCLK value by this value. The Host Driver can clear the Data Timeout Error Status + * Enable (in the Interrupt Status Enable register) to prevent inadvertent time-out events. + * + * Values: + * 0000 - SDCLK x 2 1 3 + * 0001 - SDCLK x 2 14 + * 1110 - SDCLK x 2 2 7 + * 1111 - SDCLK x 2 28 + */ + +#define BP_USDHC_SYS_CTRL_DTOCV (16) //!< Bit position for USDHC_SYS_CTRL_DTOCV. +#define BM_USDHC_SYS_CTRL_DTOCV (0x000f0000) //!< Bit mask for USDHC_SYS_CTRL_DTOCV. + +//! @brief Get value of USDHC_SYS_CTRL_DTOCV from a register value. +#define BG_USDHC_SYS_CTRL_DTOCV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_DTOCV) >> BP_USDHC_SYS_CTRL_DTOCV) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_DTOCV. +#define BF_USDHC_SYS_CTRL_DTOCV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_DTOCV) & BM_USDHC_SYS_CTRL_DTOCV) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTOCV field to a new value. +#define BW_USDHC_SYS_CTRL_DTOCV(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_DTOCV) | BF_USDHC_SYS_CTRL_DTOCV(v))) +#endif + + +/* --- Register HW_USDHC_SYS_CTRL, field RST_FIFO[22] (WORZ) + * + * Reset the Async FIFO: Reset the Async FIFO between card interface and the internal logic. It's + * only used for debugging. Software should not tough it. + */ + +#define BP_USDHC_SYS_CTRL_RST_FIFO (22) //!< Bit position for USDHC_SYS_CTRL_RST_FIFO. +#define BM_USDHC_SYS_CTRL_RST_FIFO (0x00400000) //!< Bit mask for USDHC_SYS_CTRL_RST_FIFO. + +//! @brief Get value of USDHC_SYS_CTRL_RST_FIFO from a register value. +#define BG_USDHC_SYS_CTRL_RST_FIFO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_RST_FIFO) >> BP_USDHC_SYS_CTRL_RST_FIFO) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_RST_FIFO. +#define BF_USDHC_SYS_CTRL_RST_FIFO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_RST_FIFO) & BM_USDHC_SYS_CTRL_RST_FIFO) + +/* --- Register HW_USDHC_SYS_CTRL, field IPP_RST_N[23] (RW) + * + * This register's value will be output to CARD from pad directly for hardware reset of the card if + * card support this feature. + */ + +#define BP_USDHC_SYS_CTRL_IPP_RST_N (23) //!< Bit position for USDHC_SYS_CTRL_IPP_RST_N. +#define BM_USDHC_SYS_CTRL_IPP_RST_N (0x00800000) //!< Bit mask for USDHC_SYS_CTRL_IPP_RST_N. + +//! @brief Get value of USDHC_SYS_CTRL_IPP_RST_N from a register value. +#define BG_USDHC_SYS_CTRL_IPP_RST_N(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_IPP_RST_N) >> BP_USDHC_SYS_CTRL_IPP_RST_N) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_IPP_RST_N. +#define BF_USDHC_SYS_CTRL_IPP_RST_N(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_IPP_RST_N) & BM_USDHC_SYS_CTRL_IPP_RST_N) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPP_RST_N field to a new value. +#define BW_USDHC_SYS_CTRL_IPP_RST_N(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_IPP_RST_N) | BF_USDHC_SYS_CTRL_IPP_RST_N(v))) +#endif + +/* --- Register HW_USDHC_SYS_CTRL, field RSTA[24] (WORZ) + * + * Software Reset For ALL: This reset effects the entire Host Controller except for the card + * detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared. During its + * initialization, the Host Driver shall set this bit to 1 to reset the uSDHC. The uSDHC shall reset + * this bit to 0 when the capabilities registers are valid and the Host Driver can read them. + * Additional use of Software Reset For All does not affect the value of the Capabilities registers. + * After this bit is set, it is recommended that the Host Driver reset the external card and re- + * initialize it. + * + * Values: + * 0 - No Reset + * 1 - Reset + */ + +#define BP_USDHC_SYS_CTRL_RSTA (24) //!< Bit position for USDHC_SYS_CTRL_RSTA. +#define BM_USDHC_SYS_CTRL_RSTA (0x01000000) //!< Bit mask for USDHC_SYS_CTRL_RSTA. + +//! @brief Get value of USDHC_SYS_CTRL_RSTA from a register value. +#define BG_USDHC_SYS_CTRL_RSTA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_RSTA) >> BP_USDHC_SYS_CTRL_RSTA) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_RSTA. +#define BF_USDHC_SYS_CTRL_RSTA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_RSTA) & BM_USDHC_SYS_CTRL_RSTA) + + +/* --- Register HW_USDHC_SYS_CTRL, field RSTC[25] (WORZ) + * + * Software Reset For CMD Line: Only part of the command circuit is reset. The following registers + * and bits are cleared by this bit: Present State register Command Inhibit (CMD) Interrupt Status + * register Command Complete + * + * Values: + * 0 - No Reset + * 1 - Reset + */ + +#define BP_USDHC_SYS_CTRL_RSTC (25) //!< Bit position for USDHC_SYS_CTRL_RSTC. +#define BM_USDHC_SYS_CTRL_RSTC (0x02000000) //!< Bit mask for USDHC_SYS_CTRL_RSTC. + +//! @brief Get value of USDHC_SYS_CTRL_RSTC from a register value. +#define BG_USDHC_SYS_CTRL_RSTC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_RSTC) >> BP_USDHC_SYS_CTRL_RSTC) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_RSTC. +#define BF_USDHC_SYS_CTRL_RSTC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_RSTC) & BM_USDHC_SYS_CTRL_RSTC) + + +/* --- Register HW_USDHC_SYS_CTRL, field RSTD[26] (WORZ) + * + * Software Reset For DAT Line: Only part of the data circuit is reset. DMA circuit is also reset. + * The following registers and bits are cleared by this bit: Data Port register Buffer is cleared + * and initialized.Present State register Buffer Read Enable Buffer Write Enable Read Transfer + * Active Write Transfer Active DAT Line Active Command Inhibit (DAT) Protocol Control register + * Continue Request Stop At Block Gap Request Interrupt Status register Buffer Read Ready Buffer + * Write Ready DMA Interrupt Block Gap Event Transfer Complete + * + * Values: + * 0 - No Reset + * 1 - Reset + */ + +#define BP_USDHC_SYS_CTRL_RSTD (26) //!< Bit position for USDHC_SYS_CTRL_RSTD. +#define BM_USDHC_SYS_CTRL_RSTD (0x04000000) //!< Bit mask for USDHC_SYS_CTRL_RSTD. + +//! @brief Get value of USDHC_SYS_CTRL_RSTD from a register value. +#define BG_USDHC_SYS_CTRL_RSTD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_RSTD) >> BP_USDHC_SYS_CTRL_RSTD) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_RSTD. +#define BF_USDHC_SYS_CTRL_RSTD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_RSTD) & BM_USDHC_SYS_CTRL_RSTD) + + +/* --- Register HW_USDHC_SYS_CTRL, field INITA[27] (RW) + * + * Initialization Active: When this bit is set, 80 SD-Clocks are sent to the card. After the 80 + * clocks are sent, this bit is self cleared. This bit is very useful during the card power-up + * period when 74 SD-Clocks are needed and the clock auto gating feature is enabled. Writing 1 to + * this bit when this bit is already 1 has no effect. Writing 0 to this bit at any time has no + * effect. When either of the CIHB and CDIHB bits in the Present State Register are set, writing 1 + * to this bit is ignored (i.e. when command line or data lines are active, write to this bit is not + * allowed). On the otherhand, when this bit is set, i.e., during intialization active period, it is + * allowed to issue command, and the command bit stream will appear on the CMD pad after all 80 + * clock cycles are done. So when this command ends, the driver can make sure the 80 clock cycles + * are sent out. This is very useful when the driver needs send 80 cycles to the card and does not + * want to wait till this bit is self cleared. + */ + +#define BP_USDHC_SYS_CTRL_INITA (27) //!< Bit position for USDHC_SYS_CTRL_INITA. +#define BM_USDHC_SYS_CTRL_INITA (0x08000000) //!< Bit mask for USDHC_SYS_CTRL_INITA. + +//! @brief Get value of USDHC_SYS_CTRL_INITA from a register value. +#define BG_USDHC_SYS_CTRL_INITA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_SYS_CTRL_INITA) >> BP_USDHC_SYS_CTRL_INITA) + +//! @brief Format value for bitfield USDHC_SYS_CTRL_INITA. +#define BF_USDHC_SYS_CTRL_INITA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_SYS_CTRL_INITA) & BM_USDHC_SYS_CTRL_INITA) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the INITA field to a new value. +#define BW_USDHC_SYS_CTRL_INITA(x, v) (HW_USDHC_SYS_CTRL_WR(x, (HW_USDHC_SYS_CTRL_RD(x) & ~BM_USDHC_SYS_CTRL_INITA) | BF_USDHC_SYS_CTRL_INITA(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_INT_STATUS - Interrupt Status +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_INT_STATUS - Interrupt Status (W1C) + * + * Reset value: 0x00000000 + * + * An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of + * the status bits is set to 1. For all bits, writing 1 to a bit clears it; writing to 0 keeps the + * bit unchanged. More than one status can be cleared with a single register write. For Card + * Interrupt, before writing 1 to clear, it is required that the card stops asserting the interrupt, + * meaning that when the Card Driver services the interrupt condition, otherwise the CINT bit will + * be asserted again. The table below shows the relationship between the Command Timeout Error and + * the Command Complete. uSDHC Status for Command Timeout Error/Command Complete Bit Combinations + * Command Complete Command Timeout Error Meaning of the Status 0 0 X X 1 + * Response not received within 64 SDCLK cycles 1 0 Response received The table + * below shows the relationship between the Transfer Complete and the Data Timeout Error. uSDHC + * Status for Data Timeout Error/Transfer Complete Bit Combinations Transfer Complete + * Data Timeout Error Meaning of the Status 0 0 X 0 1 Timeout occurred + * during transfer 1 X Data Transfer Complete The table below shows the + * relationship between the Command CRC Error and Command Timeout Error. uSDHC Status for Command + * CRC Error/Command Timeout Error Bit Combinations Command Complete Command Timeout + * Error Meaning of the Status 0 0 No error 0 1 Response Timeout Error + * 1 0 Response CRC Error 1 1 CMD line conflict + */ +typedef union _hw_usdhc_int_status +{ + reg32_t U; + struct _hw_usdhc_int_status_bitfields + { + unsigned CC : 1; //!< [0] Command Complete: This bit is set when you receive the end bit of the command response (except Auto CMD12). + unsigned TC : 1; //!< [1] Transfer Complete: This bit is set when a read or write transfer is completed. + unsigned BGE : 1; //!< [2] Block Gap Event: If the Stop At Block Gap Request bit in the Protocol Control register is set, this bit is set when a read or write transaction is stopped at a block gap. + unsigned DINT : 1; //!< [3] DMA Interrupt: Occurs only when the internal DMA finishes the data transfer successfully. + unsigned BWR : 1; //!< [4] Buffer Write Ready: This status bit is set if the Buffer Write Enable bit, in the Present State register, changes from 0 to 1. + unsigned BRR : 1; //!< [5] Buffer Read Ready: This status bit is set if the Buffer Read Enable bit, in the Present State register, changes from 0 to 1. + unsigned CINS : 1; //!< [6] Card Insertion: This status bit is set if the Card Inserted bit in the Present State register changes from 0 to 1. + unsigned CRM : 1; //!< [7] Card Removal: This status bit is set if the Card Inserted bit in the Present State register changes from 1 to 0. + unsigned CINT : 1; //!< [8] Card Interrupt: This status bit is set when an interrupt signal is detected from the external card. + unsigned RESERVED0 : 3; //!< [11:9] Reserved + unsigned RTE : 1; //!< [12] Re-Tuning Event: (only for SD3.0 SDR104 mode) This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. + unsigned RESERVED1 : 1; //!< [13] Reserved + unsigned TP : 1; //!< [14] Tuning Pass:(only for SD3.0 SDR104 mode) Current CMD19 transfer is done successfully. + unsigned RESERVED2 : 1; //!< [15] Reserved + unsigned CTOE : 1; //!< [16] Command Timeout Error: Occurs only if no response is returned within 64 SDCLK cycles from the end bit of the command. + unsigned CCE : 1; //!< [17] Command CRC Error: Command CRC Error is generated in two cases. + unsigned CEBE : 1; //!< [18] Command End Bit Error: Occurs when detecting that the end bit of a command response is 0. + unsigned CIE : 1; //!< [19] Command Index Error: Occurs if a Command Index error occurs in the command response. + unsigned DTOE : 1; //!< [20] Data Timeout Error: Occurs when detecting one of following time-out conditions. + unsigned DCE : 1; //!< [21] Data CRC Error: Occurs when detecting a CRC error when transferring read data, which uses the DAT line, or when detecting the Write CRC status having a value other than 010. + unsigned DEBE : 1; //!< [22] Data End Bit Error: Occurs either when detecting 0 at the end bit position of read data, which uses the DAT line, or at the end bit position of the CRC. + unsigned RESERVED3 : 1; //!< [23] Reserved + unsigned AC12E : 1; //!< [24] Auto CMD12 Error: Occurs when detecting that one of the bits in the Auto CMD12 Error Status register has changed from 0 to 1. + unsigned RESERVED4 : 1; //!< [25] Reserved + unsigned TNE : 1; //!< [26] Tuning Error: (only for SD3.0 SDR104 mode) This bit is set when an unrecoverable error is detected in a tuning circuit. + unsigned RESERVED5 : 1; //!< [27] Reserved + unsigned DMAE : 1; //!< [28] DMA Error: Occurs when an Internal DMA transfer has failed. + unsigned RESERVED6 : 3; //!< [31:29] Reserved + } B; +} hw_usdhc_int_status_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_INT_STATUS register + */ +#define HW_USDHC_INT_STATUS_ADDR(x) (REGS_USDHC_BASE(x) + 0x30) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_INT_STATUS(x) (*(volatile hw_usdhc_int_status_t *) HW_USDHC_INT_STATUS_ADDR(x)) +#define HW_USDHC_INT_STATUS_RD(x) (HW_USDHC_INT_STATUS(x).U) +#define HW_USDHC_INT_STATUS_WR(x, v) (HW_USDHC_INT_STATUS(x).U = (v)) +#define HW_USDHC_INT_STATUS_SET(x, v) (HW_USDHC_INT_STATUS_WR(x, HW_USDHC_INT_STATUS_RD(x) | (v))) +#define HW_USDHC_INT_STATUS_CLR(x, v) (HW_USDHC_INT_STATUS_WR(x, HW_USDHC_INT_STATUS_RD(x) & ~(v))) +#define HW_USDHC_INT_STATUS_TOG(x, v) (HW_USDHC_INT_STATUS_WR(x, HW_USDHC_INT_STATUS_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_INT_STATUS bitfields + */ + +/* --- Register HW_USDHC_INT_STATUS, field CC[0] (W1C) + * + * Command Complete: This bit is set when you receive the end bit of the command response (except + * Auto CMD12). Refer to the Command Inhibit (CMD) in the Present State register. + * + * Values: + * 0 - Command not complete + * 1 - Command complete + */ + +#define BP_USDHC_INT_STATUS_CC (0) //!< Bit position for USDHC_INT_STATUS_CC. +#define BM_USDHC_INT_STATUS_CC (0x00000001) //!< Bit mask for USDHC_INT_STATUS_CC. + +//! @brief Get value of USDHC_INT_STATUS_CC from a register value. +#define BG_USDHC_INT_STATUS_CC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_CC) >> BP_USDHC_INT_STATUS_CC) + +//! @brief Format value for bitfield USDHC_INT_STATUS_CC. +#define BF_USDHC_INT_STATUS_CC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_CC) & BM_USDHC_INT_STATUS_CC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CC field to a new value. +#define BW_USDHC_INT_STATUS_CC(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_CC) | BF_USDHC_INT_STATUS_CC(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field TC[1] (W1C) + * + * Transfer Complete: This bit is set when a read or write transfer is completed. In the case of a + * Read Transaction: This bit is set at the falling edge of the Read Transfer Active Status. There + * are two cases in which this interrupt is generated. The first is when a data transfer is + * completed as specified by the data length (after the last data has been read to the Host System). + * The second is when data has stopped at the block gap and completed the data transfer by setting + * the Stop At Block Gap Request bit in the Protocol Control register (after valid data has been + * read to the Host System). In the case of a Write Transaction: This bit is set at the falling edge + * of the DAT Line Active Status. There are two cases in which this interrupt is generated. The + * first is when the last data is written to the SD card as specified by the data length and the + * busy signal is released. The second is when data transfers are stopped at the block gap, by + * setting the Stop At Block Gap Request bit in the Protocol Control register, and the data + * transfers are completed. (after valid data is written to the SD card and the busy signal + * released). + * + * Values: + * 0 - Transfer not complete + * 1 - Transfer complete + */ + +#define BP_USDHC_INT_STATUS_TC (1) //!< Bit position for USDHC_INT_STATUS_TC. +#define BM_USDHC_INT_STATUS_TC (0x00000002) //!< Bit mask for USDHC_INT_STATUS_TC. + +//! @brief Get value of USDHC_INT_STATUS_TC from a register value. +#define BG_USDHC_INT_STATUS_TC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_TC) >> BP_USDHC_INT_STATUS_TC) + +//! @brief Format value for bitfield USDHC_INT_STATUS_TC. +#define BF_USDHC_INT_STATUS_TC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_TC) & BM_USDHC_INT_STATUS_TC) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TC field to a new value. +#define BW_USDHC_INT_STATUS_TC(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_TC) | BF_USDHC_INT_STATUS_TC(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field BGE[2] (W1C) + * + * Block Gap Event: If the Stop At Block Gap Request bit in the Protocol Control register is set, + * this bit is set when a read or write transaction is stopped at a block gap. If Stop At Block Gap + * Request is not set to 1, this bit is not set to 1. In the case of a Read Transaction: This bit is + * set at the falling edge of the DAT Line Active Status (When the transaction is stopped at SD Bus + * timing). The Read Wait must be supported in order to use this function. In the case of Write + * Transaction: This bit is set at the falling edge of Write Transfer Active Status (After getting + * CRC status at SD Bus timing). + * + * Values: + * 0 - No block gap event + * 1 - Transaction stopped at block gap + */ + +#define BP_USDHC_INT_STATUS_BGE (2) //!< Bit position for USDHC_INT_STATUS_BGE. +#define BM_USDHC_INT_STATUS_BGE (0x00000004) //!< Bit mask for USDHC_INT_STATUS_BGE. + +//! @brief Get value of USDHC_INT_STATUS_BGE from a register value. +#define BG_USDHC_INT_STATUS_BGE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_BGE) >> BP_USDHC_INT_STATUS_BGE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_BGE. +#define BF_USDHC_INT_STATUS_BGE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_BGE) & BM_USDHC_INT_STATUS_BGE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BGE field to a new value. +#define BW_USDHC_INT_STATUS_BGE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_BGE) | BF_USDHC_INT_STATUS_BGE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field DINT[3] (W1C) + * + * DMA Interrupt: Occurs only when the internal DMA finishes the data transfer successfully. + * Whenever errors occur during data transfer, this bit will not be set. Instead, the DMAE bit will + * be set. Either Simple DMA or ADMA finishes data transferring, this bit will be set. + * + * Values: + * 0 - No DMA Interrupt + * 1 - DMA Interrupt is generated + */ + +#define BP_USDHC_INT_STATUS_DINT (3) //!< Bit position for USDHC_INT_STATUS_DINT. +#define BM_USDHC_INT_STATUS_DINT (0x00000008) //!< Bit mask for USDHC_INT_STATUS_DINT. + +//! @brief Get value of USDHC_INT_STATUS_DINT from a register value. +#define BG_USDHC_INT_STATUS_DINT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_DINT) >> BP_USDHC_INT_STATUS_DINT) + +//! @brief Format value for bitfield USDHC_INT_STATUS_DINT. +#define BF_USDHC_INT_STATUS_DINT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_DINT) & BM_USDHC_INT_STATUS_DINT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DINT field to a new value. +#define BW_USDHC_INT_STATUS_DINT(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_DINT) | BF_USDHC_INT_STATUS_DINT(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field BWR[4] (W1C) + * + * Buffer Write Ready: This status bit is set if the Buffer Write Enable bit, in the Present State + * register, changes from 0 to 1. Refer to the Buffer Write Enable bit in the Present State register + * for additional information. + * + * Values: + * 0 - Not ready to write buffer + * 1 - Ready to write buffer: + */ + +#define BP_USDHC_INT_STATUS_BWR (4) //!< Bit position for USDHC_INT_STATUS_BWR. +#define BM_USDHC_INT_STATUS_BWR (0x00000010) //!< Bit mask for USDHC_INT_STATUS_BWR. + +//! @brief Get value of USDHC_INT_STATUS_BWR from a register value. +#define BG_USDHC_INT_STATUS_BWR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_BWR) >> BP_USDHC_INT_STATUS_BWR) + +//! @brief Format value for bitfield USDHC_INT_STATUS_BWR. +#define BF_USDHC_INT_STATUS_BWR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_BWR) & BM_USDHC_INT_STATUS_BWR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BWR field to a new value. +#define BW_USDHC_INT_STATUS_BWR(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_BWR) | BF_USDHC_INT_STATUS_BWR(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field BRR[5] (W1C) + * + * Buffer Read Ready: This status bit is set if the Buffer Read Enable bit, in the Present State + * register, changes from 0 to 1. Refer to the Buffer Read Enable bit in the Present State register + * for additional information. + * + * Values: + * 0 - Not ready to read buffer + * 1 - Ready to read buffer + */ + +#define BP_USDHC_INT_STATUS_BRR (5) //!< Bit position for USDHC_INT_STATUS_BRR. +#define BM_USDHC_INT_STATUS_BRR (0x00000020) //!< Bit mask for USDHC_INT_STATUS_BRR. + +//! @brief Get value of USDHC_INT_STATUS_BRR from a register value. +#define BG_USDHC_INT_STATUS_BRR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_BRR) >> BP_USDHC_INT_STATUS_BRR) + +//! @brief Format value for bitfield USDHC_INT_STATUS_BRR. +#define BF_USDHC_INT_STATUS_BRR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_BRR) & BM_USDHC_INT_STATUS_BRR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BRR field to a new value. +#define BW_USDHC_INT_STATUS_BRR(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_BRR) | BF_USDHC_INT_STATUS_BRR(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field CINS[6] (W1C) + * + * Card Insertion: This status bit is set if the Card Inserted bit in the Present State register + * changes from 0 to 1. When the Host Driver writes this bit to 1 to clear this status, the status + * of the Card Inserted in the Present State register should be confirmed. Because the card state + * may possibly be changed when the Host Driver clears this bit and the interrupt event may not be + * generated. When this bit is cleared, it will be set again if a card is inserted. In order to + * leave it cleared, clear the Card Inserted Status Enable bit in Interrupt Status Enable register. + * + * Values: + * 0 - Card state unstable or removed + * 1 - Card inserted + */ + +#define BP_USDHC_INT_STATUS_CINS (6) //!< Bit position for USDHC_INT_STATUS_CINS. +#define BM_USDHC_INT_STATUS_CINS (0x00000040) //!< Bit mask for USDHC_INT_STATUS_CINS. + +//! @brief Get value of USDHC_INT_STATUS_CINS from a register value. +#define BG_USDHC_INT_STATUS_CINS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_CINS) >> BP_USDHC_INT_STATUS_CINS) + +//! @brief Format value for bitfield USDHC_INT_STATUS_CINS. +#define BF_USDHC_INT_STATUS_CINS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_CINS) & BM_USDHC_INT_STATUS_CINS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CINS field to a new value. +#define BW_USDHC_INT_STATUS_CINS(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_CINS) | BF_USDHC_INT_STATUS_CINS(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field CRM[7] (W1C) + * + * Card Removal: This status bit is set if the Card Inserted bit in the Present State register + * changes from 1 to 0. When the Host Driver writes this bit to 1 to clear this status, the status + * of the Card Inserted in the Present State register should be confirmed. Because the card state + * may possibly be changed when the Host Driver clears this bit and the interrupt event may not be + * generated. When this bit is cleared, it will be set again if no card is inserted. In order to + * leave it cleared, clear the Card Removal Status Enable bit in Interrupt Status Enable register. + * + * Values: + * 0 - Card state unstable or inserted + * 1 - Card removed + */ + +#define BP_USDHC_INT_STATUS_CRM (7) //!< Bit position for USDHC_INT_STATUS_CRM. +#define BM_USDHC_INT_STATUS_CRM (0x00000080) //!< Bit mask for USDHC_INT_STATUS_CRM. + +//! @brief Get value of USDHC_INT_STATUS_CRM from a register value. +#define BG_USDHC_INT_STATUS_CRM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_CRM) >> BP_USDHC_INT_STATUS_CRM) + +//! @brief Format value for bitfield USDHC_INT_STATUS_CRM. +#define BF_USDHC_INT_STATUS_CRM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_CRM) & BM_USDHC_INT_STATUS_CRM) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRM field to a new value. +#define BW_USDHC_INT_STATUS_CRM(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_CRM) | BF_USDHC_INT_STATUS_CRM(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field CINT[8] (W1C) + * + * Card Interrupt: This status bit is set when an interrupt signal is detected from the external + * card. In 1-bit mode, the uSDHC will detect the Card Interrupt without the SD Clock to support + * wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so the + * interrupt from card can only be sampled during interrupt cycle, introducing some delay between + * the interrupt signal from the SDIO card and the interrupt to the Host System. Writing this bit to + * 1 can clear this bit, but as the interrupt factor from the SDIO card does not clear, this bit is + * set again. In order to clear this bit, it is required to reset the interrupt factor from the + * external card followed by a writing 1 to this bit. When this status has been set, and the Host + * Driver needs to service this interrupt, the Card Interrupt Signal Enable in the Interrupt Signal + * Enable register should be 0 to stop driving the interrupt signal to the Host System. After + * completion of the card interrupt service (It should reset the interrupt factors in the SDIO card + * and the interrupt signal may not be asserted), write 1 to clear this bit, set the Card Interrupt + * Signal Enable to 1, and start sampling the interrupt signal again. + * + * Values: + * 0 - No Card Interrupt + * 1 - Generate Card Interrupt + */ + +#define BP_USDHC_INT_STATUS_CINT (8) //!< Bit position for USDHC_INT_STATUS_CINT. +#define BM_USDHC_INT_STATUS_CINT (0x00000100) //!< Bit mask for USDHC_INT_STATUS_CINT. + +//! @brief Get value of USDHC_INT_STATUS_CINT from a register value. +#define BG_USDHC_INT_STATUS_CINT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_CINT) >> BP_USDHC_INT_STATUS_CINT) + +//! @brief Format value for bitfield USDHC_INT_STATUS_CINT. +#define BF_USDHC_INT_STATUS_CINT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_CINT) & BM_USDHC_INT_STATUS_CINT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CINT field to a new value. +#define BW_USDHC_INT_STATUS_CINT(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_CINT) | BF_USDHC_INT_STATUS_CINT(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field RTE[12] (W1C) + * + * Re-Tuning Event: (only for SD3.0 SDR104 mode) This status is set if Re-Tuning Request in the + * Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re- + * tuning for next data transfer. Current data transfer (not large block count) can be completed + * without re-tuning. + * + * Values: + * 0 - Re-Tuning is not required + * 1 - Re-Tuning should be performed + */ + +#define BP_USDHC_INT_STATUS_RTE (12) //!< Bit position for USDHC_INT_STATUS_RTE. +#define BM_USDHC_INT_STATUS_RTE (0x00001000) //!< Bit mask for USDHC_INT_STATUS_RTE. + +//! @brief Get value of USDHC_INT_STATUS_RTE from a register value. +#define BG_USDHC_INT_STATUS_RTE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_RTE) >> BP_USDHC_INT_STATUS_RTE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_RTE. +#define BF_USDHC_INT_STATUS_RTE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_RTE) & BM_USDHC_INT_STATUS_RTE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTE field to a new value. +#define BW_USDHC_INT_STATUS_RTE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_RTE) | BF_USDHC_INT_STATUS_RTE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field TP[14] (W1C) + * + * Tuning Pass:(only for SD3.0 SDR104 mode) Current CMD19 transfer is done successfully. That is, + * current sampling point is correct. + */ + +#define BP_USDHC_INT_STATUS_TP (14) //!< Bit position for USDHC_INT_STATUS_TP. +#define BM_USDHC_INT_STATUS_TP (0x00004000) //!< Bit mask for USDHC_INT_STATUS_TP. + +//! @brief Get value of USDHC_INT_STATUS_TP from a register value. +#define BG_USDHC_INT_STATUS_TP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_TP) >> BP_USDHC_INT_STATUS_TP) + +//! @brief Format value for bitfield USDHC_INT_STATUS_TP. +#define BF_USDHC_INT_STATUS_TP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_TP) & BM_USDHC_INT_STATUS_TP) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP field to a new value. +#define BW_USDHC_INT_STATUS_TP(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_TP) | BF_USDHC_INT_STATUS_TP(v))) +#endif + +/* --- Register HW_USDHC_INT_STATUS, field CTOE[16] (W1C) + * + * Command Timeout Error: Occurs only if no response is returned within 64 SDCLK cycles from the end + * bit of the command. If the uSDHC detects a CMD line conflict, in which case a Command CRC Error + * shall also be set (as shown in ), this bit shall be set without waiting for 64 SDCLK cycles. This + * is because the command will be aborted by the uSDHC. + * + * Values: + * 0 - No Error + * 1 - Time out + */ + +#define BP_USDHC_INT_STATUS_CTOE (16) //!< Bit position for USDHC_INT_STATUS_CTOE. +#define BM_USDHC_INT_STATUS_CTOE (0x00010000) //!< Bit mask for USDHC_INT_STATUS_CTOE. + +//! @brief Get value of USDHC_INT_STATUS_CTOE from a register value. +#define BG_USDHC_INT_STATUS_CTOE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_CTOE) >> BP_USDHC_INT_STATUS_CTOE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_CTOE. +#define BF_USDHC_INT_STATUS_CTOE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_CTOE) & BM_USDHC_INT_STATUS_CTOE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CTOE field to a new value. +#define BW_USDHC_INT_STATUS_CTOE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_CTOE) | BF_USDHC_INT_STATUS_CTOE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field CCE[17] (W1C) + * + * Command CRC Error: Command CRC Error is generated in two cases. If a response is returned and the + * Command Timeout Error is set to 0 (indicating no time-out), this bit is set when detecting a CRC + * error in the command response. The uSDHC detects a CMD line conflict by monitoring the CMD line + * when a command is issued. If the uSDHC drives the CMD line to 1, but detects 0 on the CMD line at + * the next SDCLK edge, then the uSDHC shall abort the command (Stop driving CMD line) and set this + * bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict. + * + * Values: + * 0 - No Error + * 1 - CRC Error Generated. + */ + +#define BP_USDHC_INT_STATUS_CCE (17) //!< Bit position for USDHC_INT_STATUS_CCE. +#define BM_USDHC_INT_STATUS_CCE (0x00020000) //!< Bit mask for USDHC_INT_STATUS_CCE. + +//! @brief Get value of USDHC_INT_STATUS_CCE from a register value. +#define BG_USDHC_INT_STATUS_CCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_CCE) >> BP_USDHC_INT_STATUS_CCE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_CCE. +#define BF_USDHC_INT_STATUS_CCE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_CCE) & BM_USDHC_INT_STATUS_CCE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CCE field to a new value. +#define BW_USDHC_INT_STATUS_CCE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_CCE) | BF_USDHC_INT_STATUS_CCE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field CEBE[18] (W1C) + * + * Command End Bit Error: Occurs when detecting that the end bit of a command response is 0. + * + * Values: + * 0 - No Error + * 1 - End Bit Error Generated + */ + +#define BP_USDHC_INT_STATUS_CEBE (18) //!< Bit position for USDHC_INT_STATUS_CEBE. +#define BM_USDHC_INT_STATUS_CEBE (0x00040000) //!< Bit mask for USDHC_INT_STATUS_CEBE. + +//! @brief Get value of USDHC_INT_STATUS_CEBE from a register value. +#define BG_USDHC_INT_STATUS_CEBE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_CEBE) >> BP_USDHC_INT_STATUS_CEBE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_CEBE. +#define BF_USDHC_INT_STATUS_CEBE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_CEBE) & BM_USDHC_INT_STATUS_CEBE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CEBE field to a new value. +#define BW_USDHC_INT_STATUS_CEBE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_CEBE) | BF_USDHC_INT_STATUS_CEBE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field CIE[19] (W1C) + * + * Command Index Error: Occurs if a Command Index error occurs in the command response. + * + * Values: + * 0 - No Error + * 1 - Error + */ + +#define BP_USDHC_INT_STATUS_CIE (19) //!< Bit position for USDHC_INT_STATUS_CIE. +#define BM_USDHC_INT_STATUS_CIE (0x00080000) //!< Bit mask for USDHC_INT_STATUS_CIE. + +//! @brief Get value of USDHC_INT_STATUS_CIE from a register value. +#define BG_USDHC_INT_STATUS_CIE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_CIE) >> BP_USDHC_INT_STATUS_CIE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_CIE. +#define BF_USDHC_INT_STATUS_CIE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_CIE) & BM_USDHC_INT_STATUS_CIE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CIE field to a new value. +#define BW_USDHC_INT_STATUS_CIE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_CIE) | BF_USDHC_INT_STATUS_CIE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field DTOE[20] (W1C) + * + * Data Timeout Error: Occurs when detecting one of following time-out conditions. Busy time-out for + * R1b,R5b type Busy time-out after Write CRC status Read Data time-out. + * + * Values: + * 0 - No Error + * 1 - Time out + */ + +#define BP_USDHC_INT_STATUS_DTOE (20) //!< Bit position for USDHC_INT_STATUS_DTOE. +#define BM_USDHC_INT_STATUS_DTOE (0x00100000) //!< Bit mask for USDHC_INT_STATUS_DTOE. + +//! @brief Get value of USDHC_INT_STATUS_DTOE from a register value. +#define BG_USDHC_INT_STATUS_DTOE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_DTOE) >> BP_USDHC_INT_STATUS_DTOE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_DTOE. +#define BF_USDHC_INT_STATUS_DTOE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_DTOE) & BM_USDHC_INT_STATUS_DTOE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTOE field to a new value. +#define BW_USDHC_INT_STATUS_DTOE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_DTOE) | BF_USDHC_INT_STATUS_DTOE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field DCE[21] (W1C) + * + * Data CRC Error: Occurs when detecting a CRC error when transferring read data, which uses the DAT + * line, or when detecting the Write CRC status having a value other than 010. + * + * Values: + * 0 - No Error + * 1 - Error + */ + +#define BP_USDHC_INT_STATUS_DCE (21) //!< Bit position for USDHC_INT_STATUS_DCE. +#define BM_USDHC_INT_STATUS_DCE (0x00200000) //!< Bit mask for USDHC_INT_STATUS_DCE. + +//! @brief Get value of USDHC_INT_STATUS_DCE from a register value. +#define BG_USDHC_INT_STATUS_DCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_DCE) >> BP_USDHC_INT_STATUS_DCE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_DCE. +#define BF_USDHC_INT_STATUS_DCE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_DCE) & BM_USDHC_INT_STATUS_DCE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DCE field to a new value. +#define BW_USDHC_INT_STATUS_DCE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_DCE) | BF_USDHC_INT_STATUS_DCE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field DEBE[22] (W1C) + * + * Data End Bit Error: Occurs either when detecting 0 at the end bit position of read data, which + * uses the DAT line, or at the end bit position of the CRC. + * + * Values: + * 0 - No Error + * 1 - Error + */ + +#define BP_USDHC_INT_STATUS_DEBE (22) //!< Bit position for USDHC_INT_STATUS_DEBE. +#define BM_USDHC_INT_STATUS_DEBE (0x00400000) //!< Bit mask for USDHC_INT_STATUS_DEBE. + +//! @brief Get value of USDHC_INT_STATUS_DEBE from a register value. +#define BG_USDHC_INT_STATUS_DEBE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_DEBE) >> BP_USDHC_INT_STATUS_DEBE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_DEBE. +#define BF_USDHC_INT_STATUS_DEBE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_DEBE) & BM_USDHC_INT_STATUS_DEBE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DEBE field to a new value. +#define BW_USDHC_INT_STATUS_DEBE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_DEBE) | BF_USDHC_INT_STATUS_DEBE(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field AC12E[24] (W1C) + * + * Auto CMD12 Error: Occurs when detecting that one of the bits in the Auto CMD12 Error Status + * register has changed from 0 to 1. This bit is set to 1, not only when the errors in Auto CMD12 + * occur, but also when the Auto CMD12 is not executed due to the previous command error. + * + * Values: + * 0 - No Error + * 1 - Error + */ + +#define BP_USDHC_INT_STATUS_AC12E (24) //!< Bit position for USDHC_INT_STATUS_AC12E. +#define BM_USDHC_INT_STATUS_AC12E (0x01000000) //!< Bit mask for USDHC_INT_STATUS_AC12E. + +//! @brief Get value of USDHC_INT_STATUS_AC12E from a register value. +#define BG_USDHC_INT_STATUS_AC12E(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_AC12E) >> BP_USDHC_INT_STATUS_AC12E) + +//! @brief Format value for bitfield USDHC_INT_STATUS_AC12E. +#define BF_USDHC_INT_STATUS_AC12E(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_AC12E) & BM_USDHC_INT_STATUS_AC12E) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC12E field to a new value. +#define BW_USDHC_INT_STATUS_AC12E(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_AC12E) | BF_USDHC_INT_STATUS_AC12E(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS, field TNE[26] (W1C) + * + * Tuning Error: (only for SD3.0 SDR104 mode) This bit is set when an unrecoverable error is + * detected in a tuning circuit. By detecting Tuning Error, Host Driver needs to abort a command + * executeing and perform tuning. + */ + +#define BP_USDHC_INT_STATUS_TNE (26) //!< Bit position for USDHC_INT_STATUS_TNE. +#define BM_USDHC_INT_STATUS_TNE (0x04000000) //!< Bit mask for USDHC_INT_STATUS_TNE. + +//! @brief Get value of USDHC_INT_STATUS_TNE from a register value. +#define BG_USDHC_INT_STATUS_TNE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_TNE) >> BP_USDHC_INT_STATUS_TNE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_TNE. +#define BF_USDHC_INT_STATUS_TNE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_TNE) & BM_USDHC_INT_STATUS_TNE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TNE field to a new value. +#define BW_USDHC_INT_STATUS_TNE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_TNE) | BF_USDHC_INT_STATUS_TNE(v))) +#endif + +/* --- Register HW_USDHC_INT_STATUS, field DMAE[28] (W1C) + * + * DMA Error: Occurs when an Internal DMA transfer has failed. This bit is set to 1, when some error + * occurs in the data transfer. This error can be caused by either Simple DMA or ADMA, depending on + * which DMA is in use. The value in DMA System Address register is the next fetch address where the + * error occurs. Since any error corrupts the whole data block, the Host Driver shall re-start the + * transfer from the corrupted block boundary. The address of the block boundary can be calculated + * either from the current DS_ADDR value or from the remaining number of blocks and the block size. + * + * Values: + * 0 - No Error + * 1 - Error + */ + +#define BP_USDHC_INT_STATUS_DMAE (28) //!< Bit position for USDHC_INT_STATUS_DMAE. +#define BM_USDHC_INT_STATUS_DMAE (0x10000000) //!< Bit mask for USDHC_INT_STATUS_DMAE. + +//! @brief Get value of USDHC_INT_STATUS_DMAE from a register value. +#define BG_USDHC_INT_STATUS_DMAE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_DMAE) >> BP_USDHC_INT_STATUS_DMAE) + +//! @brief Format value for bitfield USDHC_INT_STATUS_DMAE. +#define BF_USDHC_INT_STATUS_DMAE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_DMAE) & BM_USDHC_INT_STATUS_DMAE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DMAE field to a new value. +#define BW_USDHC_INT_STATUS_DMAE(x, v) (HW_USDHC_INT_STATUS_WR(x, (HW_USDHC_INT_STATUS_RD(x) & ~BM_USDHC_INT_STATUS_DMAE) | BF_USDHC_INT_STATUS_DMAE(v))) +#endif + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_INT_STATUS_EN - Interrupt Status Enable +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_INT_STATUS_EN - Interrupt Status Enable (RW) + * + * Reset value: 0x157f413f + * + * Setting the bits in this register to 1 enables the corresponding Interrupt Status to be set by + * the specified event. If any bit is cleared, the corresponding Interrupt Status bit is also + * cleared (i.e. when the bit in this register is cleared, the corresponding bit in Interrupt Status + * Register is always 0). Depending on IABG bit setting, uSDHC may be programmed to sample the + * card interrupt signal during the interrupt period and hold its value in the flip-flop. There will + * be some delays on the Card Interrupt, asserted from the card, to the time the Host System is + * informed. To detect a CMD line conflict, the Host Driver must set both Command Timeout Error + * Status Enable and Command CRC Error Status Enable to 1. + */ +typedef union _hw_usdhc_int_status_en +{ + reg32_t U; + struct _hw_usdhc_int_status_en_bitfields + { + unsigned CCSEN : 1; //!< [0] Command Complete Status Enable: 1 Enabled 0 Masked + unsigned TCSEN : 1; //!< [1] Transfer Complete Status Enable: + unsigned BGESEN : 1; //!< [2] Block Gap Event Status Enable: + unsigned DINTSEN : 1; //!< [3] DMA Interrupt Status Enable: + unsigned BWRSEN : 1; //!< [4] Buffer Write Ready Status Enable: + unsigned BRRSEN : 1; //!< [5] Buffer Read Ready Status Enable: + unsigned CINSSEN : 1; //!< [6] Card Insertion Status Enable: + unsigned CRMSEN : 1; //!< [7] Card Removal Status Enable: + unsigned CINTSEN : 1; //!< [8] Card Interrupt Status Enable: If this bit is set to 0, the uSDHC will clear the interrupt request to the System. + unsigned RESERVED0 : 3; //!< [11:9] Reserved + unsigned RTESEN : 1; //!< [12] Re-Tuning Event Status Enable + unsigned RESERVED1 : 1; //!< [13] Reserved + unsigned TPSEN : 1; //!< [14] Tuning Pass Status Enable + unsigned RESERVED2 : 1; //!< [15] Reserved + unsigned CTOESEN : 1; //!< [16] Command Timeout Error Status Enable: + unsigned CCESEN : 1; //!< [17] Command CRC Error Status Enable: + unsigned CEBESEN : 1; //!< [18] Command End Bit Error Status Enable: + unsigned CIESEN : 1; //!< [19] Command Index Error Status Enable: + unsigned DTOESEN : 1; //!< [20] Data Timeout Error Status Enable: + unsigned DCESEN : 1; //!< [21] Data CRC Error Status Enable: + unsigned DEBESEN : 1; //!< [22] Data End Bit Error Status Enable: + unsigned RESERVED3 : 1; //!< [23] Reserved + unsigned AC12ESEN : 1; //!< [24] Auto CMD12 Error Status Enable: + unsigned RESERVED4 : 1; //!< [25] Reserved + unsigned TNESEN : 1; //!< [26] Tuning Error Status Enable: + unsigned RESERVED5 : 1; //!< [27] Reserved + unsigned DMAESEN : 1; //!< [28] DMA Error Status Enable: + unsigned RESERVED6 : 3; //!< [31:29] Reserved + } B; +} hw_usdhc_int_status_en_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_INT_STATUS_EN register + */ +#define HW_USDHC_INT_STATUS_EN_ADDR(x) (REGS_USDHC_BASE(x) + 0x34) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_INT_STATUS_EN(x) (*(volatile hw_usdhc_int_status_en_t *) HW_USDHC_INT_STATUS_EN_ADDR(x)) +#define HW_USDHC_INT_STATUS_EN_RD(x) (HW_USDHC_INT_STATUS_EN(x).U) +#define HW_USDHC_INT_STATUS_EN_WR(x, v) (HW_USDHC_INT_STATUS_EN(x).U = (v)) +#define HW_USDHC_INT_STATUS_EN_SET(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, HW_USDHC_INT_STATUS_EN_RD(x) | (v))) +#define HW_USDHC_INT_STATUS_EN_CLR(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, HW_USDHC_INT_STATUS_EN_RD(x) & ~(v))) +#define HW_USDHC_INT_STATUS_EN_TOG(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, HW_USDHC_INT_STATUS_EN_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_INT_STATUS_EN bitfields + */ + +/* --- Register HW_USDHC_INT_STATUS_EN, field CCSEN[0] (RW) + * + * Command Complete Status Enable: 1 Enabled 0 Masked + */ + +#define BP_USDHC_INT_STATUS_EN_CCSEN (0) //!< Bit position for USDHC_INT_STATUS_EN_CCSEN. +#define BM_USDHC_INT_STATUS_EN_CCSEN (0x00000001) //!< Bit mask for USDHC_INT_STATUS_EN_CCSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_CCSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_CCSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_CCSEN) >> BP_USDHC_INT_STATUS_EN_CCSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_CCSEN. +#define BF_USDHC_INT_STATUS_EN_CCSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_CCSEN) & BM_USDHC_INT_STATUS_EN_CCSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CCSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_CCSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_CCSEN) | BF_USDHC_INT_STATUS_EN_CCSEN(v))) +#endif + +/* --- Register HW_USDHC_INT_STATUS_EN, field TCSEN[1] (RW) + * + * Transfer Complete Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_TCSEN (1) //!< Bit position for USDHC_INT_STATUS_EN_TCSEN. +#define BM_USDHC_INT_STATUS_EN_TCSEN (0x00000002) //!< Bit mask for USDHC_INT_STATUS_EN_TCSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_TCSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_TCSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_TCSEN) >> BP_USDHC_INT_STATUS_EN_TCSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_TCSEN. +#define BF_USDHC_INT_STATUS_EN_TCSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_TCSEN) & BM_USDHC_INT_STATUS_EN_TCSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TCSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_TCSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_TCSEN) | BF_USDHC_INT_STATUS_EN_TCSEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field BGESEN[2] (RW) + * + * Block Gap Event Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_BGESEN (2) //!< Bit position for USDHC_INT_STATUS_EN_BGESEN. +#define BM_USDHC_INT_STATUS_EN_BGESEN (0x00000004) //!< Bit mask for USDHC_INT_STATUS_EN_BGESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_BGESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_BGESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_BGESEN) >> BP_USDHC_INT_STATUS_EN_BGESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_BGESEN. +#define BF_USDHC_INT_STATUS_EN_BGESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_BGESEN) & BM_USDHC_INT_STATUS_EN_BGESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BGESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_BGESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_BGESEN) | BF_USDHC_INT_STATUS_EN_BGESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field DINTSEN[3] (RW) + * + * DMA Interrupt Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_DINTSEN (3) //!< Bit position for USDHC_INT_STATUS_EN_DINTSEN. +#define BM_USDHC_INT_STATUS_EN_DINTSEN (0x00000008) //!< Bit mask for USDHC_INT_STATUS_EN_DINTSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_DINTSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_DINTSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_DINTSEN) >> BP_USDHC_INT_STATUS_EN_DINTSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_DINTSEN. +#define BF_USDHC_INT_STATUS_EN_DINTSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_DINTSEN) & BM_USDHC_INT_STATUS_EN_DINTSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DINTSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_DINTSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_DINTSEN) | BF_USDHC_INT_STATUS_EN_DINTSEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field BWRSEN[4] (RW) + * + * Buffer Write Ready Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_BWRSEN (4) //!< Bit position for USDHC_INT_STATUS_EN_BWRSEN. +#define BM_USDHC_INT_STATUS_EN_BWRSEN (0x00000010) //!< Bit mask for USDHC_INT_STATUS_EN_BWRSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_BWRSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_BWRSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_BWRSEN) >> BP_USDHC_INT_STATUS_EN_BWRSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_BWRSEN. +#define BF_USDHC_INT_STATUS_EN_BWRSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_BWRSEN) & BM_USDHC_INT_STATUS_EN_BWRSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BWRSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_BWRSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_BWRSEN) | BF_USDHC_INT_STATUS_EN_BWRSEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field BRRSEN[5] (RW) + * + * Buffer Read Ready Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_BRRSEN (5) //!< Bit position for USDHC_INT_STATUS_EN_BRRSEN. +#define BM_USDHC_INT_STATUS_EN_BRRSEN (0x00000020) //!< Bit mask for USDHC_INT_STATUS_EN_BRRSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_BRRSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_BRRSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_BRRSEN) >> BP_USDHC_INT_STATUS_EN_BRRSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_BRRSEN. +#define BF_USDHC_INT_STATUS_EN_BRRSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_BRRSEN) & BM_USDHC_INT_STATUS_EN_BRRSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BRRSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_BRRSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_BRRSEN) | BF_USDHC_INT_STATUS_EN_BRRSEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field CINSSEN[6] (RW) + * + * Card Insertion Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_CINSSEN (6) //!< Bit position for USDHC_INT_STATUS_EN_CINSSEN. +#define BM_USDHC_INT_STATUS_EN_CINSSEN (0x00000040) //!< Bit mask for USDHC_INT_STATUS_EN_CINSSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_CINSSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_CINSSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_CINSSEN) >> BP_USDHC_INT_STATUS_EN_CINSSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_CINSSEN. +#define BF_USDHC_INT_STATUS_EN_CINSSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_CINSSEN) & BM_USDHC_INT_STATUS_EN_CINSSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CINSSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_CINSSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_CINSSEN) | BF_USDHC_INT_STATUS_EN_CINSSEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field CRMSEN[7] (RW) + * + * Card Removal Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_CRMSEN (7) //!< Bit position for USDHC_INT_STATUS_EN_CRMSEN. +#define BM_USDHC_INT_STATUS_EN_CRMSEN (0x00000080) //!< Bit mask for USDHC_INT_STATUS_EN_CRMSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_CRMSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_CRMSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_CRMSEN) >> BP_USDHC_INT_STATUS_EN_CRMSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_CRMSEN. +#define BF_USDHC_INT_STATUS_EN_CRMSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_CRMSEN) & BM_USDHC_INT_STATUS_EN_CRMSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRMSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_CRMSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_CRMSEN) | BF_USDHC_INT_STATUS_EN_CRMSEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field CINTSEN[8] (RW) + * + * Card Interrupt Status Enable: If this bit is set to 0, the uSDHC will clear the interrupt request + * to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted + * when this bit is set to 1. The Host Driver should clear the Card Interrupt Status Enable before + * servicing the Card Interrupt and should set this bit again after all interrupt requests from the + * card are cleared to prevent inadvertent interrupts. + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_CINTSEN (8) //!< Bit position for USDHC_INT_STATUS_EN_CINTSEN. +#define BM_USDHC_INT_STATUS_EN_CINTSEN (0x00000100) //!< Bit mask for USDHC_INT_STATUS_EN_CINTSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_CINTSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_CINTSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_CINTSEN) >> BP_USDHC_INT_STATUS_EN_CINTSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_CINTSEN. +#define BF_USDHC_INT_STATUS_EN_CINTSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_CINTSEN) & BM_USDHC_INT_STATUS_EN_CINTSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CINTSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_CINTSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_CINTSEN) | BF_USDHC_INT_STATUS_EN_CINTSEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field RTESEN[12] (RW) + * + * Re-Tuning Event Status Enable + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_RTESEN (12) //!< Bit position for USDHC_INT_STATUS_EN_RTESEN. +#define BM_USDHC_INT_STATUS_EN_RTESEN (0x00001000) //!< Bit mask for USDHC_INT_STATUS_EN_RTESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_RTESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_RTESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_RTESEN) >> BP_USDHC_INT_STATUS_EN_RTESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_RTESEN. +#define BF_USDHC_INT_STATUS_EN_RTESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_RTESEN) & BM_USDHC_INT_STATUS_EN_RTESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_RTESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_RTESEN) | BF_USDHC_INT_STATUS_EN_RTESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field TPSEN[14] (RW) + * + * Tuning Pass Status Enable + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_TPSEN (14) //!< Bit position for USDHC_INT_STATUS_EN_TPSEN. +#define BM_USDHC_INT_STATUS_EN_TPSEN (0x00004000) //!< Bit mask for USDHC_INT_STATUS_EN_TPSEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_TPSEN from a register value. +#define BG_USDHC_INT_STATUS_EN_TPSEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_TPSEN) >> BP_USDHC_INT_STATUS_EN_TPSEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_TPSEN. +#define BF_USDHC_INT_STATUS_EN_TPSEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_TPSEN) & BM_USDHC_INT_STATUS_EN_TPSEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TPSEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_TPSEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_TPSEN) | BF_USDHC_INT_STATUS_EN_TPSEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field CTOESEN[16] (RW) + * + * Command Timeout Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_CTOESEN (16) //!< Bit position for USDHC_INT_STATUS_EN_CTOESEN. +#define BM_USDHC_INT_STATUS_EN_CTOESEN (0x00010000) //!< Bit mask for USDHC_INT_STATUS_EN_CTOESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_CTOESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_CTOESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_CTOESEN) >> BP_USDHC_INT_STATUS_EN_CTOESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_CTOESEN. +#define BF_USDHC_INT_STATUS_EN_CTOESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_CTOESEN) & BM_USDHC_INT_STATUS_EN_CTOESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CTOESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_CTOESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_CTOESEN) | BF_USDHC_INT_STATUS_EN_CTOESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field CCESEN[17] (RW) + * + * Command CRC Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_CCESEN (17) //!< Bit position for USDHC_INT_STATUS_EN_CCESEN. +#define BM_USDHC_INT_STATUS_EN_CCESEN (0x00020000) //!< Bit mask for USDHC_INT_STATUS_EN_CCESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_CCESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_CCESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_CCESEN) >> BP_USDHC_INT_STATUS_EN_CCESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_CCESEN. +#define BF_USDHC_INT_STATUS_EN_CCESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_CCESEN) & BM_USDHC_INT_STATUS_EN_CCESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CCESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_CCESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_CCESEN) | BF_USDHC_INT_STATUS_EN_CCESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field CEBESEN[18] (RW) + * + * Command End Bit Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_CEBESEN (18) //!< Bit position for USDHC_INT_STATUS_EN_CEBESEN. +#define BM_USDHC_INT_STATUS_EN_CEBESEN (0x00040000) //!< Bit mask for USDHC_INT_STATUS_EN_CEBESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_CEBESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_CEBESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_CEBESEN) >> BP_USDHC_INT_STATUS_EN_CEBESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_CEBESEN. +#define BF_USDHC_INT_STATUS_EN_CEBESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_CEBESEN) & BM_USDHC_INT_STATUS_EN_CEBESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CEBESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_CEBESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_CEBESEN) | BF_USDHC_INT_STATUS_EN_CEBESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field CIESEN[19] (RW) + * + * Command Index Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_CIESEN (19) //!< Bit position for USDHC_INT_STATUS_EN_CIESEN. +#define BM_USDHC_INT_STATUS_EN_CIESEN (0x00080000) //!< Bit mask for USDHC_INT_STATUS_EN_CIESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_CIESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_CIESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_CIESEN) >> BP_USDHC_INT_STATUS_EN_CIESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_CIESEN. +#define BF_USDHC_INT_STATUS_EN_CIESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_CIESEN) & BM_USDHC_INT_STATUS_EN_CIESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CIESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_CIESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_CIESEN) | BF_USDHC_INT_STATUS_EN_CIESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field DTOESEN[20] (RW) + * + * Data Timeout Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_DTOESEN (20) //!< Bit position for USDHC_INT_STATUS_EN_DTOESEN. +#define BM_USDHC_INT_STATUS_EN_DTOESEN (0x00100000) //!< Bit mask for USDHC_INT_STATUS_EN_DTOESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_DTOESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_DTOESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_DTOESEN) >> BP_USDHC_INT_STATUS_EN_DTOESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_DTOESEN. +#define BF_USDHC_INT_STATUS_EN_DTOESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_DTOESEN) & BM_USDHC_INT_STATUS_EN_DTOESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTOESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_DTOESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_DTOESEN) | BF_USDHC_INT_STATUS_EN_DTOESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field DCESEN[21] (RW) + * + * Data CRC Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_DCESEN (21) //!< Bit position for USDHC_INT_STATUS_EN_DCESEN. +#define BM_USDHC_INT_STATUS_EN_DCESEN (0x00200000) //!< Bit mask for USDHC_INT_STATUS_EN_DCESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_DCESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_DCESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_DCESEN) >> BP_USDHC_INT_STATUS_EN_DCESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_DCESEN. +#define BF_USDHC_INT_STATUS_EN_DCESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_DCESEN) & BM_USDHC_INT_STATUS_EN_DCESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DCESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_DCESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_DCESEN) | BF_USDHC_INT_STATUS_EN_DCESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field DEBESEN[22] (RW) + * + * Data End Bit Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_DEBESEN (22) //!< Bit position for USDHC_INT_STATUS_EN_DEBESEN. +#define BM_USDHC_INT_STATUS_EN_DEBESEN (0x00400000) //!< Bit mask for USDHC_INT_STATUS_EN_DEBESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_DEBESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_DEBESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_DEBESEN) >> BP_USDHC_INT_STATUS_EN_DEBESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_DEBESEN. +#define BF_USDHC_INT_STATUS_EN_DEBESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_DEBESEN) & BM_USDHC_INT_STATUS_EN_DEBESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DEBESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_DEBESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_DEBESEN) | BF_USDHC_INT_STATUS_EN_DEBESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field AC12ESEN[24] (RW) + * + * Auto CMD12 Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_AC12ESEN (24) //!< Bit position for USDHC_INT_STATUS_EN_AC12ESEN. +#define BM_USDHC_INT_STATUS_EN_AC12ESEN (0x01000000) //!< Bit mask for USDHC_INT_STATUS_EN_AC12ESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_AC12ESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_AC12ESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_AC12ESEN) >> BP_USDHC_INT_STATUS_EN_AC12ESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_AC12ESEN. +#define BF_USDHC_INT_STATUS_EN_AC12ESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_AC12ESEN) & BM_USDHC_INT_STATUS_EN_AC12ESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC12ESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_AC12ESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_AC12ESEN) | BF_USDHC_INT_STATUS_EN_AC12ESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field TNESEN[26] (RW) + * + * Tuning Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_TNESEN (26) //!< Bit position for USDHC_INT_STATUS_EN_TNESEN. +#define BM_USDHC_INT_STATUS_EN_TNESEN (0x04000000) //!< Bit mask for USDHC_INT_STATUS_EN_TNESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_TNESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_TNESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_TNESEN) >> BP_USDHC_INT_STATUS_EN_TNESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_TNESEN. +#define BF_USDHC_INT_STATUS_EN_TNESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_TNESEN) & BM_USDHC_INT_STATUS_EN_TNESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TNESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_TNESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_TNESEN) | BF_USDHC_INT_STATUS_EN_TNESEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_STATUS_EN, field DMAESEN[28] (RW) + * + * DMA Error Status Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_STATUS_EN_DMAESEN (28) //!< Bit position for USDHC_INT_STATUS_EN_DMAESEN. +#define BM_USDHC_INT_STATUS_EN_DMAESEN (0x10000000) //!< Bit mask for USDHC_INT_STATUS_EN_DMAESEN. + +//! @brief Get value of USDHC_INT_STATUS_EN_DMAESEN from a register value. +#define BG_USDHC_INT_STATUS_EN_DMAESEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_STATUS_EN_DMAESEN) >> BP_USDHC_INT_STATUS_EN_DMAESEN) + +//! @brief Format value for bitfield USDHC_INT_STATUS_EN_DMAESEN. +#define BF_USDHC_INT_STATUS_EN_DMAESEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_STATUS_EN_DMAESEN) & BM_USDHC_INT_STATUS_EN_DMAESEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DMAESEN field to a new value. +#define BW_USDHC_INT_STATUS_EN_DMAESEN(x, v) (HW_USDHC_INT_STATUS_EN_WR(x, (HW_USDHC_INT_STATUS_EN_RD(x) & ~BM_USDHC_INT_STATUS_EN_DMAESEN) | BF_USDHC_INT_STATUS_EN_DMAESEN(v))) +#endif + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_INT_SIGNAL_EN - Interrupt Signal Enable +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_INT_SIGNAL_EN - Interrupt Signal Enable (RW) + * + * Reset value: 0x00000000 + * + * This register is used to select which interrupt status is indicated to the Host System as the + * interrupt. These status bits all share the same interrupt line. Setting any of these bits to 1 + * enables interrupt generation. The corresponding Status register bit will generate an interrupt + * when the corresponding interrupt signal enable bit is set. + */ +typedef union _hw_usdhc_int_signal_en +{ + reg32_t U; + struct _hw_usdhc_int_signal_en_bitfields + { + unsigned CCIEN : 1; //!< [0] Command Complete Interrupt Enable: + unsigned TCIEN : 1; //!< [1] Transfer Complete Interrupt Enable: + unsigned BGEIEN : 1; //!< [2] Block Gap Event Interrupt Enable: + unsigned DINTIEN : 1; //!< [3] DMA Interrupt Enable: + unsigned BWRIEN : 1; //!< [4] Buffer Write Ready Interrupt Enable: + unsigned BRRIEN : 1; //!< [5] Buffer Read Ready Interrupt Enable: + unsigned CINSIEN : 1; //!< [6] Card Insertion Interrupt Enable: + unsigned CRMIEN : 1; //!< [7] Card Removal Interrupt Enable: + unsigned CINTIEN : 1; //!< [8] Card Interrupt Interrupt Enable: + unsigned RESERVED0 : 3; //!< [11:9] Reserved + unsigned RTEIEN : 1; //!< [12] Re-Tuning Event Interrupt Enable + unsigned RESERVED1 : 1; //!< [13] Reserved + unsigned TPIEN : 1; //!< [14] Tuning Pass Interrupt Enable + unsigned RESERVED2 : 1; //!< [15] Reserved + unsigned CTOEIEN : 1; //!< [16] Command Timeout Error Interrupt Enable + unsigned CCEIEN : 1; //!< [17] Command CRC Error Interrupt Enable: + unsigned CEBEIEN : 1; //!< [18] Command End Bit Error Interrupt Enable: + unsigned CIEIEN : 1; //!< [19] Command Index Error Interrupt Enable: + unsigned DTOEIEN : 1; //!< [20] Data Timeout Error Interrupt Enable: + unsigned DCEIEN : 1; //!< [21] Data CRC Error Interrupt Enable: + unsigned DEBEIEN : 1; //!< [22] Data End Bit Error Interrupt Enable: + unsigned RESERVED3 : 1; //!< [23] Reserved + unsigned AC12EIEN : 1; //!< [24] Auto CMD12 Error Interrupt Enable: + unsigned RESERVED4 : 1; //!< [25] Reserved + unsigned TNEIEN : 1; //!< [26] Tuning Error Interrupt Enable + unsigned RESERVED5 : 1; //!< [27] Reserved + unsigned DMAEIEN : 1; //!< [28] DMA Error Interrupt Enable: + unsigned RESERVED6 : 3; //!< [31:29] Reserved + } B; +} hw_usdhc_int_signal_en_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_INT_SIGNAL_EN register + */ +#define HW_USDHC_INT_SIGNAL_EN_ADDR(x) (REGS_USDHC_BASE(x) + 0x38) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_INT_SIGNAL_EN(x) (*(volatile hw_usdhc_int_signal_en_t *) HW_USDHC_INT_SIGNAL_EN_ADDR(x)) +#define HW_USDHC_INT_SIGNAL_EN_RD(x) (HW_USDHC_INT_SIGNAL_EN(x).U) +#define HW_USDHC_INT_SIGNAL_EN_WR(x, v) (HW_USDHC_INT_SIGNAL_EN(x).U = (v)) +#define HW_USDHC_INT_SIGNAL_EN_SET(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, HW_USDHC_INT_SIGNAL_EN_RD(x) | (v))) +#define HW_USDHC_INT_SIGNAL_EN_CLR(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, HW_USDHC_INT_SIGNAL_EN_RD(x) & ~(v))) +#define HW_USDHC_INT_SIGNAL_EN_TOG(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, HW_USDHC_INT_SIGNAL_EN_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_INT_SIGNAL_EN bitfields + */ + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field CCIEN[0] (RW) + * + * Command Complete Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_CCIEN (0) //!< Bit position for USDHC_INT_SIGNAL_EN_CCIEN. +#define BM_USDHC_INT_SIGNAL_EN_CCIEN (0x00000001) //!< Bit mask for USDHC_INT_SIGNAL_EN_CCIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_CCIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_CCIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_CCIEN) >> BP_USDHC_INT_SIGNAL_EN_CCIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_CCIEN. +#define BF_USDHC_INT_SIGNAL_EN_CCIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_CCIEN) & BM_USDHC_INT_SIGNAL_EN_CCIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CCIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_CCIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_CCIEN) | BF_USDHC_INT_SIGNAL_EN_CCIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field TCIEN[1] (RW) + * + * Transfer Complete Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_TCIEN (1) //!< Bit position for USDHC_INT_SIGNAL_EN_TCIEN. +#define BM_USDHC_INT_SIGNAL_EN_TCIEN (0x00000002) //!< Bit mask for USDHC_INT_SIGNAL_EN_TCIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_TCIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_TCIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_TCIEN) >> BP_USDHC_INT_SIGNAL_EN_TCIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_TCIEN. +#define BF_USDHC_INT_SIGNAL_EN_TCIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_TCIEN) & BM_USDHC_INT_SIGNAL_EN_TCIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TCIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_TCIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_TCIEN) | BF_USDHC_INT_SIGNAL_EN_TCIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field BGEIEN[2] (RW) + * + * Block Gap Event Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_BGEIEN (2) //!< Bit position for USDHC_INT_SIGNAL_EN_BGEIEN. +#define BM_USDHC_INT_SIGNAL_EN_BGEIEN (0x00000004) //!< Bit mask for USDHC_INT_SIGNAL_EN_BGEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_BGEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_BGEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_BGEIEN) >> BP_USDHC_INT_SIGNAL_EN_BGEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_BGEIEN. +#define BF_USDHC_INT_SIGNAL_EN_BGEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_BGEIEN) & BM_USDHC_INT_SIGNAL_EN_BGEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BGEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_BGEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_BGEIEN) | BF_USDHC_INT_SIGNAL_EN_BGEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field DINTIEN[3] (RW) + * + * DMA Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_DINTIEN (3) //!< Bit position for USDHC_INT_SIGNAL_EN_DINTIEN. +#define BM_USDHC_INT_SIGNAL_EN_DINTIEN (0x00000008) //!< Bit mask for USDHC_INT_SIGNAL_EN_DINTIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_DINTIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_DINTIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_DINTIEN) >> BP_USDHC_INT_SIGNAL_EN_DINTIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_DINTIEN. +#define BF_USDHC_INT_SIGNAL_EN_DINTIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_DINTIEN) & BM_USDHC_INT_SIGNAL_EN_DINTIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DINTIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_DINTIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_DINTIEN) | BF_USDHC_INT_SIGNAL_EN_DINTIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field BWRIEN[4] (RW) + * + * Buffer Write Ready Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_BWRIEN (4) //!< Bit position for USDHC_INT_SIGNAL_EN_BWRIEN. +#define BM_USDHC_INT_SIGNAL_EN_BWRIEN (0x00000010) //!< Bit mask for USDHC_INT_SIGNAL_EN_BWRIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_BWRIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_BWRIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_BWRIEN) >> BP_USDHC_INT_SIGNAL_EN_BWRIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_BWRIEN. +#define BF_USDHC_INT_SIGNAL_EN_BWRIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_BWRIEN) & BM_USDHC_INT_SIGNAL_EN_BWRIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BWRIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_BWRIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_BWRIEN) | BF_USDHC_INT_SIGNAL_EN_BWRIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field BRRIEN[5] (RW) + * + * Buffer Read Ready Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_BRRIEN (5) //!< Bit position for USDHC_INT_SIGNAL_EN_BRRIEN. +#define BM_USDHC_INT_SIGNAL_EN_BRRIEN (0x00000020) //!< Bit mask for USDHC_INT_SIGNAL_EN_BRRIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_BRRIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_BRRIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_BRRIEN) >> BP_USDHC_INT_SIGNAL_EN_BRRIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_BRRIEN. +#define BF_USDHC_INT_SIGNAL_EN_BRRIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_BRRIEN) & BM_USDHC_INT_SIGNAL_EN_BRRIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BRRIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_BRRIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_BRRIEN) | BF_USDHC_INT_SIGNAL_EN_BRRIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field CINSIEN[6] (RW) + * + * Card Insertion Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_CINSIEN (6) //!< Bit position for USDHC_INT_SIGNAL_EN_CINSIEN. +#define BM_USDHC_INT_SIGNAL_EN_CINSIEN (0x00000040) //!< Bit mask for USDHC_INT_SIGNAL_EN_CINSIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_CINSIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_CINSIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_CINSIEN) >> BP_USDHC_INT_SIGNAL_EN_CINSIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_CINSIEN. +#define BF_USDHC_INT_SIGNAL_EN_CINSIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_CINSIEN) & BM_USDHC_INT_SIGNAL_EN_CINSIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CINSIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_CINSIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_CINSIEN) | BF_USDHC_INT_SIGNAL_EN_CINSIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field CRMIEN[7] (RW) + * + * Card Removal Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_CRMIEN (7) //!< Bit position for USDHC_INT_SIGNAL_EN_CRMIEN. +#define BM_USDHC_INT_SIGNAL_EN_CRMIEN (0x00000080) //!< Bit mask for USDHC_INT_SIGNAL_EN_CRMIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_CRMIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_CRMIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_CRMIEN) >> BP_USDHC_INT_SIGNAL_EN_CRMIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_CRMIEN. +#define BF_USDHC_INT_SIGNAL_EN_CRMIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_CRMIEN) & BM_USDHC_INT_SIGNAL_EN_CRMIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRMIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_CRMIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_CRMIEN) | BF_USDHC_INT_SIGNAL_EN_CRMIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field CINTIEN[8] (RW) + * + * Card Interrupt Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_CINTIEN (8) //!< Bit position for USDHC_INT_SIGNAL_EN_CINTIEN. +#define BM_USDHC_INT_SIGNAL_EN_CINTIEN (0x00000100) //!< Bit mask for USDHC_INT_SIGNAL_EN_CINTIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_CINTIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_CINTIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_CINTIEN) >> BP_USDHC_INT_SIGNAL_EN_CINTIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_CINTIEN. +#define BF_USDHC_INT_SIGNAL_EN_CINTIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_CINTIEN) & BM_USDHC_INT_SIGNAL_EN_CINTIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CINTIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_CINTIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_CINTIEN) | BF_USDHC_INT_SIGNAL_EN_CINTIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field RTEIEN[12] (RW) + * + * Re-Tuning Event Interrupt Enable + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_RTEIEN (12) //!< Bit position for USDHC_INT_SIGNAL_EN_RTEIEN. +#define BM_USDHC_INT_SIGNAL_EN_RTEIEN (0x00001000) //!< Bit mask for USDHC_INT_SIGNAL_EN_RTEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_RTEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_RTEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_RTEIEN) >> BP_USDHC_INT_SIGNAL_EN_RTEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_RTEIEN. +#define BF_USDHC_INT_SIGNAL_EN_RTEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_RTEIEN) & BM_USDHC_INT_SIGNAL_EN_RTEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RTEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_RTEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_RTEIEN) | BF_USDHC_INT_SIGNAL_EN_RTEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field TPIEN[14] (RW) + * + * Tuning Pass Interrupt Enable + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_TPIEN (14) //!< Bit position for USDHC_INT_SIGNAL_EN_TPIEN. +#define BM_USDHC_INT_SIGNAL_EN_TPIEN (0x00004000) //!< Bit mask for USDHC_INT_SIGNAL_EN_TPIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_TPIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_TPIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_TPIEN) >> BP_USDHC_INT_SIGNAL_EN_TPIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_TPIEN. +#define BF_USDHC_INT_SIGNAL_EN_TPIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_TPIEN) & BM_USDHC_INT_SIGNAL_EN_TPIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TPIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_TPIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_TPIEN) | BF_USDHC_INT_SIGNAL_EN_TPIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field CTOEIEN[16] (RW) + * + * Command Timeout Error Interrupt Enable + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_CTOEIEN (16) //!< Bit position for USDHC_INT_SIGNAL_EN_CTOEIEN. +#define BM_USDHC_INT_SIGNAL_EN_CTOEIEN (0x00010000) //!< Bit mask for USDHC_INT_SIGNAL_EN_CTOEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_CTOEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_CTOEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_CTOEIEN) >> BP_USDHC_INT_SIGNAL_EN_CTOEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_CTOEIEN. +#define BF_USDHC_INT_SIGNAL_EN_CTOEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_CTOEIEN) & BM_USDHC_INT_SIGNAL_EN_CTOEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CTOEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_CTOEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_CTOEIEN) | BF_USDHC_INT_SIGNAL_EN_CTOEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field CCEIEN[17] (RW) + * + * Command CRC Error Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_CCEIEN (17) //!< Bit position for USDHC_INT_SIGNAL_EN_CCEIEN. +#define BM_USDHC_INT_SIGNAL_EN_CCEIEN (0x00020000) //!< Bit mask for USDHC_INT_SIGNAL_EN_CCEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_CCEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_CCEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_CCEIEN) >> BP_USDHC_INT_SIGNAL_EN_CCEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_CCEIEN. +#define BF_USDHC_INT_SIGNAL_EN_CCEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_CCEIEN) & BM_USDHC_INT_SIGNAL_EN_CCEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CCEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_CCEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_CCEIEN) | BF_USDHC_INT_SIGNAL_EN_CCEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field CEBEIEN[18] (RW) + * + * Command End Bit Error Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_CEBEIEN (18) //!< Bit position for USDHC_INT_SIGNAL_EN_CEBEIEN. +#define BM_USDHC_INT_SIGNAL_EN_CEBEIEN (0x00040000) //!< Bit mask for USDHC_INT_SIGNAL_EN_CEBEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_CEBEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_CEBEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_CEBEIEN) >> BP_USDHC_INT_SIGNAL_EN_CEBEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_CEBEIEN. +#define BF_USDHC_INT_SIGNAL_EN_CEBEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_CEBEIEN) & BM_USDHC_INT_SIGNAL_EN_CEBEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CEBEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_CEBEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_CEBEIEN) | BF_USDHC_INT_SIGNAL_EN_CEBEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field CIEIEN[19] (RW) + * + * Command Index Error Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_CIEIEN (19) //!< Bit position for USDHC_INT_SIGNAL_EN_CIEIEN. +#define BM_USDHC_INT_SIGNAL_EN_CIEIEN (0x00080000) //!< Bit mask for USDHC_INT_SIGNAL_EN_CIEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_CIEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_CIEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_CIEIEN) >> BP_USDHC_INT_SIGNAL_EN_CIEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_CIEIEN. +#define BF_USDHC_INT_SIGNAL_EN_CIEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_CIEIEN) & BM_USDHC_INT_SIGNAL_EN_CIEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CIEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_CIEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_CIEIEN) | BF_USDHC_INT_SIGNAL_EN_CIEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field DTOEIEN[20] (RW) + * + * Data Timeout Error Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_DTOEIEN (20) //!< Bit position for USDHC_INT_SIGNAL_EN_DTOEIEN. +#define BM_USDHC_INT_SIGNAL_EN_DTOEIEN (0x00100000) //!< Bit mask for USDHC_INT_SIGNAL_EN_DTOEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_DTOEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_DTOEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_DTOEIEN) >> BP_USDHC_INT_SIGNAL_EN_DTOEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_DTOEIEN. +#define BF_USDHC_INT_SIGNAL_EN_DTOEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_DTOEIEN) & BM_USDHC_INT_SIGNAL_EN_DTOEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTOEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_DTOEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_DTOEIEN) | BF_USDHC_INT_SIGNAL_EN_DTOEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field DCEIEN[21] (RW) + * + * Data CRC Error Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_DCEIEN (21) //!< Bit position for USDHC_INT_SIGNAL_EN_DCEIEN. +#define BM_USDHC_INT_SIGNAL_EN_DCEIEN (0x00200000) //!< Bit mask for USDHC_INT_SIGNAL_EN_DCEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_DCEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_DCEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_DCEIEN) >> BP_USDHC_INT_SIGNAL_EN_DCEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_DCEIEN. +#define BF_USDHC_INT_SIGNAL_EN_DCEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_DCEIEN) & BM_USDHC_INT_SIGNAL_EN_DCEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DCEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_DCEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_DCEIEN) | BF_USDHC_INT_SIGNAL_EN_DCEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field DEBEIEN[22] (RW) + * + * Data End Bit Error Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_DEBEIEN (22) //!< Bit position for USDHC_INT_SIGNAL_EN_DEBEIEN. +#define BM_USDHC_INT_SIGNAL_EN_DEBEIEN (0x00400000) //!< Bit mask for USDHC_INT_SIGNAL_EN_DEBEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_DEBEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_DEBEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_DEBEIEN) >> BP_USDHC_INT_SIGNAL_EN_DEBEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_DEBEIEN. +#define BF_USDHC_INT_SIGNAL_EN_DEBEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_DEBEIEN) & BM_USDHC_INT_SIGNAL_EN_DEBEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DEBEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_DEBEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_DEBEIEN) | BF_USDHC_INT_SIGNAL_EN_DEBEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field AC12EIEN[24] (RW) + * + * Auto CMD12 Error Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_AC12EIEN (24) //!< Bit position for USDHC_INT_SIGNAL_EN_AC12EIEN. +#define BM_USDHC_INT_SIGNAL_EN_AC12EIEN (0x01000000) //!< Bit mask for USDHC_INT_SIGNAL_EN_AC12EIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_AC12EIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_AC12EIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_AC12EIEN) >> BP_USDHC_INT_SIGNAL_EN_AC12EIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_AC12EIEN. +#define BF_USDHC_INT_SIGNAL_EN_AC12EIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_AC12EIEN) & BM_USDHC_INT_SIGNAL_EN_AC12EIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC12EIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_AC12EIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_AC12EIEN) | BF_USDHC_INT_SIGNAL_EN_AC12EIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field TNEIEN[26] (RW) + * + * Tuning Error Interrupt Enable + * + * Values: + * 0 - Masked + * 1 - Enabled + */ + +#define BP_USDHC_INT_SIGNAL_EN_TNEIEN (26) //!< Bit position for USDHC_INT_SIGNAL_EN_TNEIEN. +#define BM_USDHC_INT_SIGNAL_EN_TNEIEN (0x04000000) //!< Bit mask for USDHC_INT_SIGNAL_EN_TNEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_TNEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_TNEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_TNEIEN) >> BP_USDHC_INT_SIGNAL_EN_TNEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_TNEIEN. +#define BF_USDHC_INT_SIGNAL_EN_TNEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_TNEIEN) & BM_USDHC_INT_SIGNAL_EN_TNEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TNEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_TNEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_TNEIEN) | BF_USDHC_INT_SIGNAL_EN_TNEIEN(v))) +#endif + + +/* --- Register HW_USDHC_INT_SIGNAL_EN, field DMAEIEN[28] (RW) + * + * DMA Error Interrupt Enable: + * + * Values: + * 0 - Masked + * 1 - Enable + */ + +#define BP_USDHC_INT_SIGNAL_EN_DMAEIEN (28) //!< Bit position for USDHC_INT_SIGNAL_EN_DMAEIEN. +#define BM_USDHC_INT_SIGNAL_EN_DMAEIEN (0x10000000) //!< Bit mask for USDHC_INT_SIGNAL_EN_DMAEIEN. + +//! @brief Get value of USDHC_INT_SIGNAL_EN_DMAEIEN from a register value. +#define BG_USDHC_INT_SIGNAL_EN_DMAEIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_INT_SIGNAL_EN_DMAEIEN) >> BP_USDHC_INT_SIGNAL_EN_DMAEIEN) + +//! @brief Format value for bitfield USDHC_INT_SIGNAL_EN_DMAEIEN. +#define BF_USDHC_INT_SIGNAL_EN_DMAEIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_INT_SIGNAL_EN_DMAEIEN) & BM_USDHC_INT_SIGNAL_EN_DMAEIEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DMAEIEN field to a new value. +#define BW_USDHC_INT_SIGNAL_EN_DMAEIEN(x, v) (HW_USDHC_INT_SIGNAL_EN_WR(x, (HW_USDHC_INT_SIGNAL_EN_RD(x) & ~BM_USDHC_INT_SIGNAL_EN_DMAEIEN) | BF_USDHC_INT_SIGNAL_EN_DMAEIEN(v))) +#endif + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status (RO) + * + * Reset value: 0x00000000 + * + * When the Auto CMD12 Error Status bit in the Status register is set, the Host Driver shall check + * this register to identify what kind of error the Auto CMD12 indicated. This register is valid + * only when the Auto CMD12 Error status bit is set. The table bwlow shows the relationship between + * the Auto CMGD12 CRC Error and the Auto CMD12 Command Timeout Error. Relationship Between + * Command CRC Error and Command Timeout Error for Auto CMD12 Auto CMD12 CRC Error Auto + * CMD12 Timeout Error Type of Error 0 0 No Error 0 1 Response Timeout + * Error 1 0 Response CRC Error 1 1 CMD line conflict Changes in Auto + * CMD12 Error Status register can be classified in three scenarios: When the uSDHC is going to + * issue an Auto CMD12. Set bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the + * previous command Set bit 0 to 0 if the Auto CMD12 is issued At the end bit of an Auto CMD12 + * response. Check errors correspond to bits 1-4. Set bits 1-4 corresponding to detected errors. + * Clear bits 1-4 corresponding to detected errors Before reading the Auto CMD12 Error Status bit + * 7. Set bit 7 to 1 if there is a command that can't be issued Clear bit 7 if there is no command + * to issue The timing for generating the Auto CMD12 Error and writing to the Command register + * are asynchronous. After that, bit 7 shall be sampled when the driver is not writing to the + * Command register. So it is suggested to read this register only when the AC12E bit in Interrupt + * Status register is set. An Auto CMD12 Error Interrupt is generated when one of the error bits + * (0-4) is set to 1. The Command Not Issued By Auto CMD12 Error does not generate an interrupt. + */ +typedef union _hw_usdhc_autocmd12_err_status +{ + reg32_t U; + struct _hw_usdhc_autocmd12_err_status_bitfields + { + unsigned AC12NE : 1; //!< [0] Auto CMD12 Not Executed: If memory multiple block data transfer is not started, due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. + unsigned AC12TOE : 1; //!< [1] Auto CMD12 Timeout Error: Occurs if no response is returned within 64 SDCLK cycles from the end bit of the command. + unsigned AC12EBE : 1; //!< [2] Auto CMD12 End Bit Error: Occurs when detecting that the end bit of command response is 0 which should be 1. + unsigned AC12CE : 1; //!< [3] Auto CMD12 CRC Error: Occurs when detecting a CRC error in the command response. + unsigned AC12IE : 1; //!< [4] Auto CMD12 Index Error: Occurs if the Command Index error occurs in response to a command. + unsigned RESERVED0 : 2; //!< [6:5] Reserved + unsigned CNIBAC12E : 1; //!< [7] Command Not Issued By Auto CMD12 Error: Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. + unsigned RESERVED1 : 24; //!< [31:8] Reserved + } B; +} hw_usdhc_autocmd12_err_status_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_AUTOCMD12_ERR_STATUS register + */ +#define HW_USDHC_AUTOCMD12_ERR_STATUS_ADDR(x) (REGS_USDHC_BASE(x) + 0x3c) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_AUTOCMD12_ERR_STATUS(x) (*(volatile hw_usdhc_autocmd12_err_status_t *) HW_USDHC_AUTOCMD12_ERR_STATUS_ADDR(x)) +#define HW_USDHC_AUTOCMD12_ERR_STATUS_RD(x) (HW_USDHC_AUTOCMD12_ERR_STATUS(x).U) +#endif + +/* + * constants & macros for individual USDHC_AUTOCMD12_ERR_STATUS bitfields + */ + +/* --- Register HW_USDHC_AUTOCMD12_ERR_STATUS, field AC12NE[0] (RO) + * + * Auto CMD12 Not Executed: If memory multiple block data transfer is not started, due to a command + * error, this bit is not set because it is not necessary to issue an Auto CMD12. Setting this bit + * to 1 means the uSDHC cannot issue the Auto CMD12 to stop a memory multiple block data transfer + * due to some error. If this bit is set to 1, other error status bits (1-4) have no meaning. + * + * Values: + * 0 - Executed + * 1 - Not executed + */ + +#define BP_USDHC_AUTOCMD12_ERR_STATUS_AC12NE (0) //!< Bit position for USDHC_AUTOCMD12_ERR_STATUS_AC12NE. +#define BM_USDHC_AUTOCMD12_ERR_STATUS_AC12NE (0x00000001) //!< Bit mask for USDHC_AUTOCMD12_ERR_STATUS_AC12NE. + +//! @brief Get value of USDHC_AUTOCMD12_ERR_STATUS_AC12NE from a register value. +#define BG_USDHC_AUTOCMD12_ERR_STATUS_AC12NE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_AUTOCMD12_ERR_STATUS_AC12NE) >> BP_USDHC_AUTOCMD12_ERR_STATUS_AC12NE) + + +/* --- Register HW_USDHC_AUTOCMD12_ERR_STATUS, field AC12TOE[1] (RO) + * + * Auto CMD12 Timeout Error: Occurs if no response is returned within 64 SDCLK cycles from the end + * bit of the command. If this bit is set to1, the other error status bits (2-4) have no meaning. + * + * Values: + * 0 - No error + * 1 - Time out + */ + +#define BP_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE (1) //!< Bit position for USDHC_AUTOCMD12_ERR_STATUS_AC12TOE. +#define BM_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE (0x00000002) //!< Bit mask for USDHC_AUTOCMD12_ERR_STATUS_AC12TOE. + +//! @brief Get value of USDHC_AUTOCMD12_ERR_STATUS_AC12TOE from a register value. +#define BG_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE) >> BP_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE) + + +/* --- Register HW_USDHC_AUTOCMD12_ERR_STATUS, field AC12EBE[2] (RO) + * + * Auto CMD12 End Bit Error: Occurs when detecting that the end bit of command response is 0 which + * should be 1. + * + * Values: + * 0 - No error + * 1 - End Bit Error Generated + */ + +#define BP_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE (2) //!< Bit position for USDHC_AUTOCMD12_ERR_STATUS_AC12EBE. +#define BM_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE (0x00000004) //!< Bit mask for USDHC_AUTOCMD12_ERR_STATUS_AC12EBE. + +//! @brief Get value of USDHC_AUTOCMD12_ERR_STATUS_AC12EBE from a register value. +#define BG_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE) >> BP_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE) + + +/* --- Register HW_USDHC_AUTOCMD12_ERR_STATUS, field AC12CE[3] (RO) + * + * Auto CMD12 CRC Error: Occurs when detecting a CRC error in the command response. + * + * Values: + * 0 - No CRC error + * 1 - CRC Error Met in Auto CMD12 Response + */ + +#define BP_USDHC_AUTOCMD12_ERR_STATUS_AC12CE (3) //!< Bit position for USDHC_AUTOCMD12_ERR_STATUS_AC12CE. +#define BM_USDHC_AUTOCMD12_ERR_STATUS_AC12CE (0x00000008) //!< Bit mask for USDHC_AUTOCMD12_ERR_STATUS_AC12CE. + +//! @brief Get value of USDHC_AUTOCMD12_ERR_STATUS_AC12CE from a register value. +#define BG_USDHC_AUTOCMD12_ERR_STATUS_AC12CE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_AUTOCMD12_ERR_STATUS_AC12CE) >> BP_USDHC_AUTOCMD12_ERR_STATUS_AC12CE) + + +/* --- Register HW_USDHC_AUTOCMD12_ERR_STATUS, field AC12IE[4] (RO) + * + * Auto CMD12 Index Error: Occurs if the Command Index error occurs in response to a command. + * + * Values: + * 0 - No error + * 1 - Error, the CMD index in response is not CMD12 + */ + +#define BP_USDHC_AUTOCMD12_ERR_STATUS_AC12IE (4) //!< Bit position for USDHC_AUTOCMD12_ERR_STATUS_AC12IE. +#define BM_USDHC_AUTOCMD12_ERR_STATUS_AC12IE (0x00000010) //!< Bit mask for USDHC_AUTOCMD12_ERR_STATUS_AC12IE. + +//! @brief Get value of USDHC_AUTOCMD12_ERR_STATUS_AC12IE from a register value. +#define BG_USDHC_AUTOCMD12_ERR_STATUS_AC12IE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_AUTOCMD12_ERR_STATUS_AC12IE) >> BP_USDHC_AUTOCMD12_ERR_STATUS_AC12IE) + + +/* --- Register HW_USDHC_AUTOCMD12_ERR_STATUS, field CNIBAC12E[7] (RO) + * + * Command Not Issued By Auto CMD12 Error: Setting this bit to 1 means CMD_wo_DAT is not executed + * due to an Auto CMD12 Error (D04-D01) in this register. + * + * Values: + * 0 - No error + * 1 - Not Issued + */ + +#define BP_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E (7) //!< Bit position for USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E. +#define BM_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E (0x00000080) //!< Bit mask for USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E. + +//! @brief Get value of USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E from a register value. +#define BG_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E) >> BP_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E) + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_HOST_CTRL_CAP - Host Controller Capabilities +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_HOST_CTRL_CAP - Host Controller Capabilities (RO) + * + * Reset value: 0x07f30000 + * + * This register provides the Host Driver with information specific to the uSDHC implementation. The + * value in this register is the power-on-reset value, and does not change with a software reset. + * Any write to this register is ignored. + */ +typedef union _hw_usdhc_host_ctrl_cap +{ + reg32_t U; + struct _hw_usdhc_host_ctrl_cap_bitfields + { + unsigned RESERVED0 : 16; //!< [15:0] Reserved + unsigned MBL : 3; //!< [18:16] Max Block Length: This value indicates the maximum block size that the Host Driver can read and write to the buffer in the uSDHC. + unsigned RESERVED1 : 1; //!< [19] Reserved + unsigned ADMAS : 1; //!< [20] ADMA Support: This bit indicates whether the uSDHC supports the ADMA feature. + unsigned HSS : 1; //!< [21] High Speed Support: This bit indicates whether the uSDHC supports High Speed mode and the Host System can supply a SD Clock frequency from 25 MHz to 50 MHz. + unsigned DMAS : 1; //!< [22] DMA Support: This bit indicates whether the uSDHC is capable of using the internal DMA to transfer data between system memory and the data buffer directly. + unsigned SRS : 1; //!< [23] Suspend / Resume Support: This bit indicates whether the uSDHC supports Suspend / Resume functionality. + unsigned VS33 : 1; //!< [24] Voltage Support 3.3V: This bit shall depend on the Host System ability. + unsigned VS30 : 1; //!< [25] Voltage Support 3.0V: This bit shall depend on the Host System ability. + unsigned VS18 : 1; //!< [26] Voltage Support 1.8V: This bit shall depend on the Host System ability. + unsigned RESERVED2 : 5; //!< [31:27] Reserved + } B; +} hw_usdhc_host_ctrl_cap_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_HOST_CTRL_CAP register + */ +#define HW_USDHC_HOST_CTRL_CAP_ADDR(x) (REGS_USDHC_BASE(x) + 0x40) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_HOST_CTRL_CAP(x) (*(volatile hw_usdhc_host_ctrl_cap_t *) HW_USDHC_HOST_CTRL_CAP_ADDR(x)) +#define HW_USDHC_HOST_CTRL_CAP_RD(x) (HW_USDHC_HOST_CTRL_CAP(x).U) +#endif + +/* + * constants & macros for individual USDHC_HOST_CTRL_CAP bitfields + */ + +/* --- Register HW_USDHC_HOST_CTRL_CAP, field MBL[18:16] (RO) + * + * Max Block Length: This value indicates the maximum block size that the Host Driver can read and + * write to the buffer in the uSDHC. The buffer shall transfer block size without wait cycles. + * + * Values: + * 000 - 512 bytes + * 001 - 1024 bytes + * 010 - 2048 bytes + * 011 - 4096 bytes + */ + +#define BP_USDHC_HOST_CTRL_CAP_MBL (16) //!< Bit position for USDHC_HOST_CTRL_CAP_MBL. +#define BM_USDHC_HOST_CTRL_CAP_MBL (0x00070000) //!< Bit mask for USDHC_HOST_CTRL_CAP_MBL. + +//! @brief Get value of USDHC_HOST_CTRL_CAP_MBL from a register value. +#define BG_USDHC_HOST_CTRL_CAP_MBL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_CAP_MBL) >> BP_USDHC_HOST_CTRL_CAP_MBL) + + +/* --- Register HW_USDHC_HOST_CTRL_CAP, field ADMAS[20] (RO) + * + * ADMA Support: This bit indicates whether the uSDHC supports the ADMA feature. + * + * Values: + * 0 - Advanced DMA Not supported + * 1 - Advanced DMA Supported + */ + +#define BP_USDHC_HOST_CTRL_CAP_ADMAS (20) //!< Bit position for USDHC_HOST_CTRL_CAP_ADMAS. +#define BM_USDHC_HOST_CTRL_CAP_ADMAS (0x00100000) //!< Bit mask for USDHC_HOST_CTRL_CAP_ADMAS. + +//! @brief Get value of USDHC_HOST_CTRL_CAP_ADMAS from a register value. +#define BG_USDHC_HOST_CTRL_CAP_ADMAS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_CAP_ADMAS) >> BP_USDHC_HOST_CTRL_CAP_ADMAS) + + +/* --- Register HW_USDHC_HOST_CTRL_CAP, field HSS[21] (RO) + * + * High Speed Support: This bit indicates whether the uSDHC supports High Speed mode and the Host + * System can supply a SD Clock frequency from 25 MHz to 50 MHz. + * + * Values: + * 0 - High Speed Not Supported + * 1 - High Speed Supported + */ + +#define BP_USDHC_HOST_CTRL_CAP_HSS (21) //!< Bit position for USDHC_HOST_CTRL_CAP_HSS. +#define BM_USDHC_HOST_CTRL_CAP_HSS (0x00200000) //!< Bit mask for USDHC_HOST_CTRL_CAP_HSS. + +//! @brief Get value of USDHC_HOST_CTRL_CAP_HSS from a register value. +#define BG_USDHC_HOST_CTRL_CAP_HSS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_CAP_HSS) >> BP_USDHC_HOST_CTRL_CAP_HSS) + + +/* --- Register HW_USDHC_HOST_CTRL_CAP, field DMAS[22] (RO) + * + * DMA Support: This bit indicates whether the uSDHC is capable of using the internal DMA to + * transfer data between system memory and the data buffer directly. + * + * Values: + * 0 - DMA not supported + * 1 - DMA Supported + */ + +#define BP_USDHC_HOST_CTRL_CAP_DMAS (22) //!< Bit position for USDHC_HOST_CTRL_CAP_DMAS. +#define BM_USDHC_HOST_CTRL_CAP_DMAS (0x00400000) //!< Bit mask for USDHC_HOST_CTRL_CAP_DMAS. + +//! @brief Get value of USDHC_HOST_CTRL_CAP_DMAS from a register value. +#define BG_USDHC_HOST_CTRL_CAP_DMAS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_CAP_DMAS) >> BP_USDHC_HOST_CTRL_CAP_DMAS) + + +/* --- Register HW_USDHC_HOST_CTRL_CAP, field SRS[23] (RO) + * + * Suspend / Resume Support: This bit indicates whether the uSDHC supports Suspend / Resume + * functionality. If this bit is 0, the Suspend and Resume mechanism, as well as the Read Wait, are + * not supported, and the Host Driver shall not issue either Suspend or Resume commands. + * + * Values: + * 0 - Not supported + * 1 - Supported + */ + +#define BP_USDHC_HOST_CTRL_CAP_SRS (23) //!< Bit position for USDHC_HOST_CTRL_CAP_SRS. +#define BM_USDHC_HOST_CTRL_CAP_SRS (0x00800000) //!< Bit mask for USDHC_HOST_CTRL_CAP_SRS. + +//! @brief Get value of USDHC_HOST_CTRL_CAP_SRS from a register value. +#define BG_USDHC_HOST_CTRL_CAP_SRS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_CAP_SRS) >> BP_USDHC_HOST_CTRL_CAP_SRS) + + +/* --- Register HW_USDHC_HOST_CTRL_CAP, field VS33[24] (RO) + * + * Voltage Support 3.3V: This bit shall depend on the Host System ability. + * + * Values: + * 0 - 3.3V not supported + * 1 - 3.3V supported + */ + +#define BP_USDHC_HOST_CTRL_CAP_VS33 (24) //!< Bit position for USDHC_HOST_CTRL_CAP_VS33. +#define BM_USDHC_HOST_CTRL_CAP_VS33 (0x01000000) //!< Bit mask for USDHC_HOST_CTRL_CAP_VS33. + +//! @brief Get value of USDHC_HOST_CTRL_CAP_VS33 from a register value. +#define BG_USDHC_HOST_CTRL_CAP_VS33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_CAP_VS33) >> BP_USDHC_HOST_CTRL_CAP_VS33) + + +/* --- Register HW_USDHC_HOST_CTRL_CAP, field VS30[25] (RO) + * + * Voltage Support 3.0V: This bit shall depend on the Host System ability. + * + * Values: + * 0 - 3.0V not supported + * 1 - 3.0V supported + */ + +#define BP_USDHC_HOST_CTRL_CAP_VS30 (25) //!< Bit position for USDHC_HOST_CTRL_CAP_VS30. +#define BM_USDHC_HOST_CTRL_CAP_VS30 (0x02000000) //!< Bit mask for USDHC_HOST_CTRL_CAP_VS30. + +//! @brief Get value of USDHC_HOST_CTRL_CAP_VS30 from a register value. +#define BG_USDHC_HOST_CTRL_CAP_VS30(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_CAP_VS30) >> BP_USDHC_HOST_CTRL_CAP_VS30) + + +/* --- Register HW_USDHC_HOST_CTRL_CAP, field VS18[26] (RO) + * + * Voltage Support 1.8V: This bit shall depend on the Host System ability. + * + * Values: + * 0 - 1.8V not supported + * 1 - 1.8V supported + */ + +#define BP_USDHC_HOST_CTRL_CAP_VS18 (26) //!< Bit position for USDHC_HOST_CTRL_CAP_VS18. +#define BM_USDHC_HOST_CTRL_CAP_VS18 (0x04000000) //!< Bit mask for USDHC_HOST_CTRL_CAP_VS18. + +//! @brief Get value of USDHC_HOST_CTRL_CAP_VS18 from a register value. +#define BG_USDHC_HOST_CTRL_CAP_VS18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_CAP_VS18) >> BP_USDHC_HOST_CTRL_CAP_VS18) + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_WTMK_LVL - Watermark Level +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_WTMK_LVL - Watermark Level (RW) + * + * Reset value: 0x08100810 + * + * Both write and read watermark levels (FIFO threshold) are configurable. There value can range + * from 1 to 128 words. Both write and read burst lengths are also Configurable. There value can + * range from 1 to 31 words. + */ +typedef union _hw_usdhc_wtmk_lvl +{ + reg32_t U; + struct _hw_usdhc_wtmk_lvl_bitfields + { + unsigned RD_WML : 8; //!< [7:0] Read Watermark Level: The number of words used as the watermark level (FIFO threshold) in a DMA read operation. + unsigned RD_BRST_LEN : 5; //!< [12:8] Read Burst Length: Due to system restriction, the actual burst length may not exceed 16. + unsigned RESERVED0 : 3; //!< [15:13] Reserved + unsigned WR_WML : 8; //!< [23:16] Write Watermark Level: The number of words used as the watermark level (FIFO threshold) in a DMA write operation. + unsigned WR_BRST_LEN : 5; //!< [28:24] Write Burst Length: Due to system restriction, the actual burst length may not exceed 16. + unsigned RESERVED1 : 3; //!< [31:29] Reserved + } B; +} hw_usdhc_wtmk_lvl_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_WTMK_LVL register + */ +#define HW_USDHC_WTMK_LVL_ADDR(x) (REGS_USDHC_BASE(x) + 0x44) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_WTMK_LVL(x) (*(volatile hw_usdhc_wtmk_lvl_t *) HW_USDHC_WTMK_LVL_ADDR(x)) +#define HW_USDHC_WTMK_LVL_RD(x) (HW_USDHC_WTMK_LVL(x).U) +#define HW_USDHC_WTMK_LVL_WR(x, v) (HW_USDHC_WTMK_LVL(x).U = (v)) +#define HW_USDHC_WTMK_LVL_SET(x, v) (HW_USDHC_WTMK_LVL_WR(x, HW_USDHC_WTMK_LVL_RD(x) | (v))) +#define HW_USDHC_WTMK_LVL_CLR(x, v) (HW_USDHC_WTMK_LVL_WR(x, HW_USDHC_WTMK_LVL_RD(x) & ~(v))) +#define HW_USDHC_WTMK_LVL_TOG(x, v) (HW_USDHC_WTMK_LVL_WR(x, HW_USDHC_WTMK_LVL_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_WTMK_LVL bitfields + */ + +/* --- Register HW_USDHC_WTMK_LVL, field RD_WML[7:0] (RW) + * + * Read Watermark Level: The number of words used as the watermark level (FIFO threshold) in a DMA + * read operation. Also the number of words as a sequence of read bursts in back-to-back mode. The + * maximum legal value for the read water mark level is 128. + */ + +#define BP_USDHC_WTMK_LVL_RD_WML (0) //!< Bit position for USDHC_WTMK_LVL_RD_WML. +#define BM_USDHC_WTMK_LVL_RD_WML (0x000000ff) //!< Bit mask for USDHC_WTMK_LVL_RD_WML. + +//! @brief Get value of USDHC_WTMK_LVL_RD_WML from a register value. +#define BG_USDHC_WTMK_LVL_RD_WML(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_WTMK_LVL_RD_WML) >> BP_USDHC_WTMK_LVL_RD_WML) + +//! @brief Format value for bitfield USDHC_WTMK_LVL_RD_WML. +#define BF_USDHC_WTMK_LVL_RD_WML(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_WTMK_LVL_RD_WML) & BM_USDHC_WTMK_LVL_RD_WML) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RD_WML field to a new value. +#define BW_USDHC_WTMK_LVL_RD_WML(x, v) (HW_USDHC_WTMK_LVL_WR(x, (HW_USDHC_WTMK_LVL_RD(x) & ~BM_USDHC_WTMK_LVL_RD_WML) | BF_USDHC_WTMK_LVL_RD_WML(v))) +#endif + +/* --- Register HW_USDHC_WTMK_LVL, field RD_BRST_LEN[12:8] (RW) + * + * Read Burst Length: Due to system restriction, the actual burst length may not exceed 16. The + * number of words the uSDHC reads in a single burst. The read burst length must be less than or + * equal to the read watermark level, and all bursts within a watermark level transfer will be in + * back-to-back mode. On reset, this field will be 8. Writing 0 to this field will result in '01000' + * (i.e. it is not able to clear this field). + */ + +#define BP_USDHC_WTMK_LVL_RD_BRST_LEN (8) //!< Bit position for USDHC_WTMK_LVL_RD_BRST_LEN. +#define BM_USDHC_WTMK_LVL_RD_BRST_LEN (0x00001f00) //!< Bit mask for USDHC_WTMK_LVL_RD_BRST_LEN. + +//! @brief Get value of USDHC_WTMK_LVL_RD_BRST_LEN from a register value. +#define BG_USDHC_WTMK_LVL_RD_BRST_LEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_WTMK_LVL_RD_BRST_LEN) >> BP_USDHC_WTMK_LVL_RD_BRST_LEN) + +//! @brief Format value for bitfield USDHC_WTMK_LVL_RD_BRST_LEN. +#define BF_USDHC_WTMK_LVL_RD_BRST_LEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_WTMK_LVL_RD_BRST_LEN) & BM_USDHC_WTMK_LVL_RD_BRST_LEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the RD_BRST_LEN field to a new value. +#define BW_USDHC_WTMK_LVL_RD_BRST_LEN(x, v) (HW_USDHC_WTMK_LVL_WR(x, (HW_USDHC_WTMK_LVL_RD(x) & ~BM_USDHC_WTMK_LVL_RD_BRST_LEN) | BF_USDHC_WTMK_LVL_RD_BRST_LEN(v))) +#endif + +/* --- Register HW_USDHC_WTMK_LVL, field WR_WML[23:16] (RW) + * + * Write Watermark Level: The number of words used as the watermark level (FIFO threshold) in a DMA + * write operation. Also the number of words as a sequence of write bursts in back-to-back mode. The + * maximum legal value for the write watermark level is 128. + */ + +#define BP_USDHC_WTMK_LVL_WR_WML (16) //!< Bit position for USDHC_WTMK_LVL_WR_WML. +#define BM_USDHC_WTMK_LVL_WR_WML (0x00ff0000) //!< Bit mask for USDHC_WTMK_LVL_WR_WML. + +//! @brief Get value of USDHC_WTMK_LVL_WR_WML from a register value. +#define BG_USDHC_WTMK_LVL_WR_WML(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_WTMK_LVL_WR_WML) >> BP_USDHC_WTMK_LVL_WR_WML) + +//! @brief Format value for bitfield USDHC_WTMK_LVL_WR_WML. +#define BF_USDHC_WTMK_LVL_WR_WML(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_WTMK_LVL_WR_WML) & BM_USDHC_WTMK_LVL_WR_WML) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WR_WML field to a new value. +#define BW_USDHC_WTMK_LVL_WR_WML(x, v) (HW_USDHC_WTMK_LVL_WR(x, (HW_USDHC_WTMK_LVL_RD(x) & ~BM_USDHC_WTMK_LVL_WR_WML) | BF_USDHC_WTMK_LVL_WR_WML(v))) +#endif + +/* --- Register HW_USDHC_WTMK_LVL, field WR_BRST_LEN[28:24] (RW) + * + * Write Burst Length: Due to system restriction, the actual burst length may not exceed 16. The + * number of words the uSDHC writes in a single burst. The write burst length must be less than or + * equal to the write watermark level, and all bursts within a watermark level transfer will be in + * back-to-back mode. On reset, this field will be 8. Writing 0 to this field will result in '01000' + * (i.e. it is not able to clear this field). + */ + +#define BP_USDHC_WTMK_LVL_WR_BRST_LEN (24) //!< Bit position for USDHC_WTMK_LVL_WR_BRST_LEN. +#define BM_USDHC_WTMK_LVL_WR_BRST_LEN (0x1f000000) //!< Bit mask for USDHC_WTMK_LVL_WR_BRST_LEN. + +//! @brief Get value of USDHC_WTMK_LVL_WR_BRST_LEN from a register value. +#define BG_USDHC_WTMK_LVL_WR_BRST_LEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_WTMK_LVL_WR_BRST_LEN) >> BP_USDHC_WTMK_LVL_WR_BRST_LEN) + +//! @brief Format value for bitfield USDHC_WTMK_LVL_WR_BRST_LEN. +#define BF_USDHC_WTMK_LVL_WR_BRST_LEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_WTMK_LVL_WR_BRST_LEN) & BM_USDHC_WTMK_LVL_WR_BRST_LEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WR_BRST_LEN field to a new value. +#define BW_USDHC_WTMK_LVL_WR_BRST_LEN(x, v) (HW_USDHC_WTMK_LVL_WR(x, (HW_USDHC_WTMK_LVL_RD(x) & ~BM_USDHC_WTMK_LVL_WR_BRST_LEN) | BF_USDHC_WTMK_LVL_WR_BRST_LEN(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_MIX_CTRL - Mixer Control +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_MIX_CTRL - Mixer Control (RW) + * + * Reset value: 0x80000000 + * + * This register is used to DMA and data transfer. To prevent data loss, The software should be + * check if data transfer is active before write this register. Olny data transfer is invalid there + * can be write. These bits are DPSEL, MBSEL, DTDSEL, AC12EN, BCEN and DMAEN. Transfer Type + * Register Setting for Various Transfer Types Multi/Single Block Select Block Count + * Enable Block Count Function 0 Don't Care Don't Care Single Transfer 1 + * 0 Don't Care Infinite Transfer 1 1 Positive Number Multiple Transfer 1 + * 1 Zero No Data Transfer + */ +typedef union _hw_usdhc_mix_ctrl +{ + reg32_t U; + struct _hw_usdhc_mix_ctrl_bitfields + { + unsigned DMAEN : 1; //!< [0] DMA Enable: This bit enables DMA functionality. + unsigned BCEN : 1; //!< [1] Block Count Enable: This bit is used to enable the Block Count register, which is only relevant for multiple block transfers. + unsigned AC12EN : 1; //!< [2] Auto CMD12 Enable: Multiple block transfers for memory require a CMD12 to stop the transaction. + unsigned DDR_EN : 1; //!< [3] Dual Data Rate mode selection + unsigned DTDSEL : 1; //!< [4] Data Transfer Direction Select: This bit defines the direction of DAT line data transfers. + unsigned MSBSEL : 1; //!< [5] Multi / Single Block Select: This bit enables multiple block DAT line data transfers. + unsigned NIBBLE_POS : 1; //!< [6] In DDR 4 bit mode nibble position indictation. + unsigned AC23EN : 1; //!< [7] Auto CMD23 Enable When this bit is set to 1, the Host Controller issues a CMD23 automatically before issuing a command specified in the Command Register. + unsigned RESERVED0 : 14; //!< [21:8] Reserved + unsigned EXE_TUNE : 1; //!< [22] Execute Tuning: (Only used for SD3.0, SDR104 mode) This bit is set to 1 to indicate the Host Driver is starting tuning procedure. + unsigned SMP_CLK_SEL : 1; //!< [23] Tuned clock or Fixed clock is used to sample data/cmd (Only used for SD3.0, SDR104 mode) + unsigned AUTO_TUNE_EN : 1; //!< [24] Auto tuning enable (Only used for SD3.0, SDR104 mode) + unsigned FBCLK_SEL : 1; //!< [25] Feedback clock source selection (Only used for SD3.0, SDR104 mode) + unsigned RESERVED1 : 3; //!< [28:26] Reserved + unsigned AC12_RD_POINT : 1; //!< [29] Only for debug. + unsigned CMD_DMY_WAIT_CFG : 1; //!< [30] Only for debug. + unsigned CMD_DMY_EN : 1; //!< [31] Only for debug. + } B; +} hw_usdhc_mix_ctrl_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_MIX_CTRL register + */ +#define HW_USDHC_MIX_CTRL_ADDR(x) (REGS_USDHC_BASE(x) + 0x48) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_MIX_CTRL(x) (*(volatile hw_usdhc_mix_ctrl_t *) HW_USDHC_MIX_CTRL_ADDR(x)) +#define HW_USDHC_MIX_CTRL_RD(x) (HW_USDHC_MIX_CTRL(x).U) +#define HW_USDHC_MIX_CTRL_WR(x, v) (HW_USDHC_MIX_CTRL(x).U = (v)) +#define HW_USDHC_MIX_CTRL_SET(x, v) (HW_USDHC_MIX_CTRL_WR(x, HW_USDHC_MIX_CTRL_RD(x) | (v))) +#define HW_USDHC_MIX_CTRL_CLR(x, v) (HW_USDHC_MIX_CTRL_WR(x, HW_USDHC_MIX_CTRL_RD(x) & ~(v))) +#define HW_USDHC_MIX_CTRL_TOG(x, v) (HW_USDHC_MIX_CTRL_WR(x, HW_USDHC_MIX_CTRL_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_MIX_CTRL bitfields + */ + +/* --- Register HW_USDHC_MIX_CTRL, field DMAEN[0] (RW) + * + * DMA Enable: This bit enables DMA functionality. If this bit is set to 1, a DMA operation shall + * begin when the Host Driver sets the DPSEL bit of this register. Whether the Simple DMA, or the + * Advanced DMA, is active depends on the DMA Select field of the Protocol Control register. + * + * Values: + * 0 - Disable + * 1 - Enable + */ + +#define BP_USDHC_MIX_CTRL_DMAEN (0) //!< Bit position for USDHC_MIX_CTRL_DMAEN. +#define BM_USDHC_MIX_CTRL_DMAEN (0x00000001) //!< Bit mask for USDHC_MIX_CTRL_DMAEN. + +//! @brief Get value of USDHC_MIX_CTRL_DMAEN from a register value. +#define BG_USDHC_MIX_CTRL_DMAEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_DMAEN) >> BP_USDHC_MIX_CTRL_DMAEN) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_DMAEN. +#define BF_USDHC_MIX_CTRL_DMAEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_DMAEN) & BM_USDHC_MIX_CTRL_DMAEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DMAEN field to a new value. +#define BW_USDHC_MIX_CTRL_DMAEN(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_DMAEN) | BF_USDHC_MIX_CTRL_DMAEN(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field BCEN[1] (RW) + * + * Block Count Enable: This bit is used to enable the Block Count register, which is only relevant + * for multiple block transfers. When this bit is 0, the internal counter for block is disabled, + * which is useful in executing an infinite transfer. + * + * Values: + * 0 - Disable + * 1 - Enable + */ + +#define BP_USDHC_MIX_CTRL_BCEN (1) //!< Bit position for USDHC_MIX_CTRL_BCEN. +#define BM_USDHC_MIX_CTRL_BCEN (0x00000002) //!< Bit mask for USDHC_MIX_CTRL_BCEN. + +//! @brief Get value of USDHC_MIX_CTRL_BCEN from a register value. +#define BG_USDHC_MIX_CTRL_BCEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_BCEN) >> BP_USDHC_MIX_CTRL_BCEN) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_BCEN. +#define BF_USDHC_MIX_CTRL_BCEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_BCEN) & BM_USDHC_MIX_CTRL_BCEN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BCEN field to a new value. +#define BW_USDHC_MIX_CTRL_BCEN(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_BCEN) | BF_USDHC_MIX_CTRL_BCEN(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field AC12EN[2] (RW) + * + * Auto CMD12 Enable: Multiple block transfers for memory require a CMD12 to stop the transaction. + * When this bit is set to 1, the uSDHC will issue a CMD12 automatically when the last block + * transfer has completed. The Host Driver shall not set this bit to issue commands that do not + * require CMD12 to stop a multiple block data transfer. In particular, secure commands defined in + * File Security Specification (see reference list) do not require CMD12. In single block transfer, + * the uSDHC will ignore this bit no matter if it is set or not. + * + * Values: + * 0 - Disable + * 1 - Enable + */ + +#define BP_USDHC_MIX_CTRL_AC12EN (2) //!< Bit position for USDHC_MIX_CTRL_AC12EN. +#define BM_USDHC_MIX_CTRL_AC12EN (0x00000004) //!< Bit mask for USDHC_MIX_CTRL_AC12EN. + +//! @brief Get value of USDHC_MIX_CTRL_AC12EN from a register value. +#define BG_USDHC_MIX_CTRL_AC12EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_AC12EN) >> BP_USDHC_MIX_CTRL_AC12EN) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_AC12EN. +#define BF_USDHC_MIX_CTRL_AC12EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_AC12EN) & BM_USDHC_MIX_CTRL_AC12EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC12EN field to a new value. +#define BW_USDHC_MIX_CTRL_AC12EN(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_AC12EN) | BF_USDHC_MIX_CTRL_AC12EN(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field DDR_EN[3] (RW) + * + * Dual Data Rate mode selection + */ + +#define BP_USDHC_MIX_CTRL_DDR_EN (3) //!< Bit position for USDHC_MIX_CTRL_DDR_EN. +#define BM_USDHC_MIX_CTRL_DDR_EN (0x00000008) //!< Bit mask for USDHC_MIX_CTRL_DDR_EN. + +//! @brief Get value of USDHC_MIX_CTRL_DDR_EN from a register value. +#define BG_USDHC_MIX_CTRL_DDR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_DDR_EN) >> BP_USDHC_MIX_CTRL_DDR_EN) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_DDR_EN. +#define BF_USDHC_MIX_CTRL_DDR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_DDR_EN) & BM_USDHC_MIX_CTRL_DDR_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DDR_EN field to a new value. +#define BW_USDHC_MIX_CTRL_DDR_EN(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_DDR_EN) | BF_USDHC_MIX_CTRL_DDR_EN(v))) +#endif + +/* --- Register HW_USDHC_MIX_CTRL, field DTDSEL[4] (RW) + * + * Data Transfer Direction Select: This bit defines the direction of DAT line data transfers. The + * bit is set to 1 by the Host Driver to transfer data from the SD card to the uSDHC and is set to 0 + * for all other commands. + * + * Values: + * 0 - Write (Host to Card) + * 1 - Read (Card to Host) + */ + +#define BP_USDHC_MIX_CTRL_DTDSEL (4) //!< Bit position for USDHC_MIX_CTRL_DTDSEL. +#define BM_USDHC_MIX_CTRL_DTDSEL (0x00000010) //!< Bit mask for USDHC_MIX_CTRL_DTDSEL. + +//! @brief Get value of USDHC_MIX_CTRL_DTDSEL from a register value. +#define BG_USDHC_MIX_CTRL_DTDSEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_DTDSEL) >> BP_USDHC_MIX_CTRL_DTDSEL) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_DTDSEL. +#define BF_USDHC_MIX_CTRL_DTDSEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_DTDSEL) & BM_USDHC_MIX_CTRL_DTDSEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTDSEL field to a new value. +#define BW_USDHC_MIX_CTRL_DTDSEL(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_DTDSEL) | BF_USDHC_MIX_CTRL_DTDSEL(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field MSBSEL[5] (RW) + * + * Multi / Single Block Select: This bit enables multiple block DAT line data transfers. For any + * other commands, this bit shall be set to 0. If this bit is 0, it is not necessary to set the + * Block Count register. (Refer to ). + * + * Values: + * 0 - Single Block + * 1 - Multiple Blocks + */ + +#define BP_USDHC_MIX_CTRL_MSBSEL (5) //!< Bit position for USDHC_MIX_CTRL_MSBSEL. +#define BM_USDHC_MIX_CTRL_MSBSEL (0x00000020) //!< Bit mask for USDHC_MIX_CTRL_MSBSEL. + +//! @brief Get value of USDHC_MIX_CTRL_MSBSEL from a register value. +#define BG_USDHC_MIX_CTRL_MSBSEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_MSBSEL) >> BP_USDHC_MIX_CTRL_MSBSEL) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_MSBSEL. +#define BF_USDHC_MIX_CTRL_MSBSEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_MSBSEL) & BM_USDHC_MIX_CTRL_MSBSEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the MSBSEL field to a new value. +#define BW_USDHC_MIX_CTRL_MSBSEL(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_MSBSEL) | BF_USDHC_MIX_CTRL_MSBSEL(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field NIBBLE_POS[6] (RW) + * + * In DDR 4 bit mode nibble position indictation. 0- the sequence is 'odd high nibble -> even high + * nibble -> odd low nibble -> even low nibble'; 1- the sequence is 'odd high nibble -> odd low + * nibble -> even high nibble -> even low nibble'. + */ + +#define BP_USDHC_MIX_CTRL_NIBBLE_POS (6) //!< Bit position for USDHC_MIX_CTRL_NIBBLE_POS. +#define BM_USDHC_MIX_CTRL_NIBBLE_POS (0x00000040) //!< Bit mask for USDHC_MIX_CTRL_NIBBLE_POS. + +//! @brief Get value of USDHC_MIX_CTRL_NIBBLE_POS from a register value. +#define BG_USDHC_MIX_CTRL_NIBBLE_POS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_NIBBLE_POS) >> BP_USDHC_MIX_CTRL_NIBBLE_POS) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_NIBBLE_POS. +#define BF_USDHC_MIX_CTRL_NIBBLE_POS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_NIBBLE_POS) & BM_USDHC_MIX_CTRL_NIBBLE_POS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the NIBBLE_POS field to a new value. +#define BW_USDHC_MIX_CTRL_NIBBLE_POS(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_NIBBLE_POS) | BF_USDHC_MIX_CTRL_NIBBLE_POS(v))) +#endif + +/* --- Register HW_USDHC_MIX_CTRL, field AC23EN[7] (RW) + * + * Auto CMD23 Enable When this bit is set to 1, the Host Controller issues a CMD23 automatically + * before issuing a command specified in the Command Register. + */ + +#define BP_USDHC_MIX_CTRL_AC23EN (7) //!< Bit position for USDHC_MIX_CTRL_AC23EN. +#define BM_USDHC_MIX_CTRL_AC23EN (0x00000080) //!< Bit mask for USDHC_MIX_CTRL_AC23EN. + +//! @brief Get value of USDHC_MIX_CTRL_AC23EN from a register value. +#define BG_USDHC_MIX_CTRL_AC23EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_AC23EN) >> BP_USDHC_MIX_CTRL_AC23EN) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_AC23EN. +#define BF_USDHC_MIX_CTRL_AC23EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_AC23EN) & BM_USDHC_MIX_CTRL_AC23EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC23EN field to a new value. +#define BW_USDHC_MIX_CTRL_AC23EN(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_AC23EN) | BF_USDHC_MIX_CTRL_AC23EN(v))) +#endif + +/* --- Register HW_USDHC_MIX_CTRL, field EXE_TUNE[22] (RW) + * + * Execute Tuning: (Only used for SD3.0, SDR104 mode) This bit is set to 1 to indicate the Host + * Driver is starting tuning procedure. Tuning procedure is aborted by writing 0. + * + * Values: + * 0 - Not Tuned or Tuning Completed + * 1 - Execute Tuning + */ + +#define BP_USDHC_MIX_CTRL_EXE_TUNE (22) //!< Bit position for USDHC_MIX_CTRL_EXE_TUNE. +#define BM_USDHC_MIX_CTRL_EXE_TUNE (0x00400000) //!< Bit mask for USDHC_MIX_CTRL_EXE_TUNE. + +//! @brief Get value of USDHC_MIX_CTRL_EXE_TUNE from a register value. +#define BG_USDHC_MIX_CTRL_EXE_TUNE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_EXE_TUNE) >> BP_USDHC_MIX_CTRL_EXE_TUNE) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_EXE_TUNE. +#define BF_USDHC_MIX_CTRL_EXE_TUNE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_EXE_TUNE) & BM_USDHC_MIX_CTRL_EXE_TUNE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EXE_TUNE field to a new value. +#define BW_USDHC_MIX_CTRL_EXE_TUNE(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_EXE_TUNE) | BF_USDHC_MIX_CTRL_EXE_TUNE(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field SMP_CLK_SEL[23] (RW) + * + * Tuned clock or Fixed clock is used to sample data/cmd (Only used for SD3.0, SDR104 mode) + * + * Values: + * 0 - Fixed clock is used to sample data/cmd + * 1 - Tuned clock is used to sample data/cmd + */ + +#define BP_USDHC_MIX_CTRL_SMP_CLK_SEL (23) //!< Bit position for USDHC_MIX_CTRL_SMP_CLK_SEL. +#define BM_USDHC_MIX_CTRL_SMP_CLK_SEL (0x00800000) //!< Bit mask for USDHC_MIX_CTRL_SMP_CLK_SEL. + +//! @brief Get value of USDHC_MIX_CTRL_SMP_CLK_SEL from a register value. +#define BG_USDHC_MIX_CTRL_SMP_CLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_SMP_CLK_SEL) >> BP_USDHC_MIX_CTRL_SMP_CLK_SEL) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_SMP_CLK_SEL. +#define BF_USDHC_MIX_CTRL_SMP_CLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_SMP_CLK_SEL) & BM_USDHC_MIX_CTRL_SMP_CLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SMP_CLK_SEL field to a new value. +#define BW_USDHC_MIX_CTRL_SMP_CLK_SEL(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_SMP_CLK_SEL) | BF_USDHC_MIX_CTRL_SMP_CLK_SEL(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field AUTO_TUNE_EN[24] (RW) + * + * Auto tuning enable (Only used for SD3.0, SDR104 mode) + * + * Values: + * 0 - disable auto tuning + * 1 - enable auto tuning + */ + +#define BP_USDHC_MIX_CTRL_AUTO_TUNE_EN (24) //!< Bit position for USDHC_MIX_CTRL_AUTO_TUNE_EN. +#define BM_USDHC_MIX_CTRL_AUTO_TUNE_EN (0x01000000) //!< Bit mask for USDHC_MIX_CTRL_AUTO_TUNE_EN. + +//! @brief Get value of USDHC_MIX_CTRL_AUTO_TUNE_EN from a register value. +#define BG_USDHC_MIX_CTRL_AUTO_TUNE_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_AUTO_TUNE_EN) >> BP_USDHC_MIX_CTRL_AUTO_TUNE_EN) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_AUTO_TUNE_EN. +#define BF_USDHC_MIX_CTRL_AUTO_TUNE_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_AUTO_TUNE_EN) & BM_USDHC_MIX_CTRL_AUTO_TUNE_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AUTO_TUNE_EN field to a new value. +#define BW_USDHC_MIX_CTRL_AUTO_TUNE_EN(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_AUTO_TUNE_EN) | BF_USDHC_MIX_CTRL_AUTO_TUNE_EN(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field FBCLK_SEL[25] (RW) + * + * Feedback clock source selection (Only used for SD3.0, SDR104 mode) + * + * Values: + * 0 - feedback clock comes from the loopback CLK + * 1 - feedback clock comes from the ipp_card_clk_out + */ + +#define BP_USDHC_MIX_CTRL_FBCLK_SEL (25) //!< Bit position for USDHC_MIX_CTRL_FBCLK_SEL. +#define BM_USDHC_MIX_CTRL_FBCLK_SEL (0x02000000) //!< Bit mask for USDHC_MIX_CTRL_FBCLK_SEL. + +//! @brief Get value of USDHC_MIX_CTRL_FBCLK_SEL from a register value. +#define BG_USDHC_MIX_CTRL_FBCLK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_FBCLK_SEL) >> BP_USDHC_MIX_CTRL_FBCLK_SEL) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_FBCLK_SEL. +#define BF_USDHC_MIX_CTRL_FBCLK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_FBCLK_SEL) & BM_USDHC_MIX_CTRL_FBCLK_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FBCLK_SEL field to a new value. +#define BW_USDHC_MIX_CTRL_FBCLK_SEL(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_FBCLK_SEL) | BF_USDHC_MIX_CTRL_FBCLK_SEL(v))) +#endif + + +/* --- Register HW_USDHC_MIX_CTRL, field AC12_RD_POINT[29] (RW) + * + * Only for debug. It's used to control when to send Auto CMD12 after multi-block read. 1 send Auto + * CMD12 8 cycles after CRC is checked successfully 0 send Auto CMD12 right after CRC is checked + * successfully + */ + +#define BP_USDHC_MIX_CTRL_AC12_RD_POINT (29) //!< Bit position for USDHC_MIX_CTRL_AC12_RD_POINT. +#define BM_USDHC_MIX_CTRL_AC12_RD_POINT (0x20000000) //!< Bit mask for USDHC_MIX_CTRL_AC12_RD_POINT. + +//! @brief Get value of USDHC_MIX_CTRL_AC12_RD_POINT from a register value. +#define BG_USDHC_MIX_CTRL_AC12_RD_POINT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_AC12_RD_POINT) >> BP_USDHC_MIX_CTRL_AC12_RD_POINT) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_AC12_RD_POINT. +#define BF_USDHC_MIX_CTRL_AC12_RD_POINT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_AC12_RD_POINT) & BM_USDHC_MIX_CTRL_AC12_RD_POINT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC12_RD_POINT field to a new value. +#define BW_USDHC_MIX_CTRL_AC12_RD_POINT(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_AC12_RD_POINT) | BF_USDHC_MIX_CTRL_AC12_RD_POINT(v))) +#endif + +/* --- Register HW_USDHC_MIX_CTRL, field CMD_DMY_WAIT_CFG[30] (RW) + * + * Only for debug. It's also used to control the number of dummy clock cycles after each command + * when CMD_DMY_EN bit is enabled. CMD_DMY_EN = 0, CMD_DMY_WAIT_CFG = x : 12 dummy clocks after each + * command CMD_DMY_EN = 1, CMD_DMY_WAIT_CFG = 0: 20 dummy clocks after each command CMD_DMY_EN = 1, + * CMD_DMY_WAIT_CFG = 1: 31 dummy clocks after each command + */ + +#define BP_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG (30) //!< Bit position for USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG. +#define BM_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG (0x40000000) //!< Bit mask for USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG. + +//! @brief Get value of USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG from a register value. +#define BG_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG) >> BP_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG. +#define BF_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG) & BM_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CMD_DMY_WAIT_CFG field to a new value. +#define BW_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG) | BF_USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG(v))) +#endif + +/* --- Register HW_USDHC_MIX_CTRL, field CMD_DMY_EN[31] (RW) + * + * Only for debug. It's used to control the number of dummy clock cycles after each command. + */ + +#define BP_USDHC_MIX_CTRL_CMD_DMY_EN (31) //!< Bit position for USDHC_MIX_CTRL_CMD_DMY_EN. +#define BM_USDHC_MIX_CTRL_CMD_DMY_EN (0x80000000) //!< Bit mask for USDHC_MIX_CTRL_CMD_DMY_EN. + +//! @brief Get value of USDHC_MIX_CTRL_CMD_DMY_EN from a register value. +#define BG_USDHC_MIX_CTRL_CMD_DMY_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MIX_CTRL_CMD_DMY_EN) >> BP_USDHC_MIX_CTRL_CMD_DMY_EN) + +//! @brief Format value for bitfield USDHC_MIX_CTRL_CMD_DMY_EN. +#define BF_USDHC_MIX_CTRL_CMD_DMY_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MIX_CTRL_CMD_DMY_EN) & BM_USDHC_MIX_CTRL_CMD_DMY_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CMD_DMY_EN field to a new value. +#define BW_USDHC_MIX_CTRL_CMD_DMY_EN(x, v) (HW_USDHC_MIX_CTRL_WR(x, (HW_USDHC_MIX_CTRL_RD(x) & ~BM_USDHC_MIX_CTRL_CMD_DMY_EN) | BF_USDHC_MIX_CTRL_CMD_DMY_EN(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_FORCE_EVENT - Force Event +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_FORCE_EVENT - Force Event (WORZ) + * + * Reset value: 0x00000000 + * + * The Force Event Register is not a physically implemented register. Rather, it is an address at + * which the Interrupt Status Register can be written if the corresponding bit of the Interrupt + * Status Enable Register is set. This register is a write only register and writing 0 to it has no + * effect. Writing 1 to this register actually sets the corresponding bit of Interrupt Status + * Register. A read from this register always results in 0's. In order to change the corresponding + * status bits in the Interrupt Status Register, make sure to set IPGEN bit in System Control + * Register so that ipg_clk is always active. Forcing a card interrupt will generate a short pulse + * on the DAT[1] line, and the driver may treat this interrupt as a normal interrupt. The interrupt + * service routine may skip polling the card interrupt factor as the interrupt is self cleared. + */ +typedef union _hw_usdhc_force_event +{ + reg32_t U; + struct _hw_usdhc_force_event_bitfields + { + unsigned FEVTAC12NE : 1; //!< [0] Force Event Auto Command 12 Not Executed: Forces the AC12NE bit in the Auto Command12 Error Status Register to be set + unsigned FEVTAC12TOE : 1; //!< [1] Force Event Auto Command 12 Time Out Error: Forces the AC12TOE bit in the Auto Command12 Error Status Register to be set + unsigned FEVTAC12CE : 1; //!< [2] Force Event Auto Command 12 CRC Error: Forces the AC12CE bit in the Auto Command12 Error Status Register to be set + unsigned FEVTAC12EBE : 1; //!< [3] Force Event Auto Command 12 End Bit Error: Forces the AC12EBE bit in the Auto Command12 Error Status Register to be set + unsigned FEVTAC12IE : 1; //!< [4] Force Event Auto Command 12 Index Error: Forces the AC12IE bit in the Auto Command12 Error Status Register to be set + unsigned RESERVED0 : 2; //!< [6:5] Reserved + unsigned FEVTCNIBAC12E : 1; //!< [7] Force Event Command Not Executed By Auto Command 12 Error: Forces the CNIBAC12E bit in the Auto Command12 Error Status Register to be set + unsigned RESERVED1 : 8; //!< [15:8] Reserved + unsigned FEVTCCE : 1; //!< [16] Force Event Command Time Out Error: Forces the CTOE bit of Interrupt Status Register to be set + unsigned FEVTCCE1 : 1; //!< [17] Force Event Command CRC Error: Forces the CCE bit of Interrupt Status Register to be set + unsigned FEVTCEBE : 1; //!< [18] Force Event Command End Bit Error: Forces the CEBE bit of Interrupt Status Register to be set + unsigned FEVTCIE : 1; //!< [19] Force Event Command Index Error: Forces the CCE bit of Interrupt Status Register to be set + unsigned FEVTDTOE : 1; //!< [20] Force Event Data Time Out Error: Force the DTOE bit of Interrupt Status Register to be set + unsigned FEVTDCE : 1; //!< [21] Force Event Data CRC Error: Forces the DCE bit of Interrupt Status Register to be set + unsigned FEVTDEBE : 1; //!< [22] Force Event Data End Bit Error: Forces the DEBE bit of Interrupt Status Register to be set + unsigned RESERVED2 : 1; //!< [23] Reserved + unsigned FEVTAC12E : 1; //!< [24] Force Event Auto Command 12 Error: Forces the AC12E bit of Interrupt Status Register to be set + unsigned RESERVED3 : 1; //!< [25] Reserved + unsigned FEVTTNE : 1; //!< [26] Force Tuning Error: Forces the TNE bit of Interrupt Status Register to be set + unsigned RESERVED4 : 1; //!< [27] Reserved + unsigned FEVTDMAE : 1; //!< [28] Force Event DMA Error: Forces the DMAE bit of Interrupt Status Register to be set + unsigned RESERVED5 : 2; //!< [30:29] Reserved + unsigned FEVTCINT : 1; //!< [31] Force Event Card Interrupt: Writing 1 to this bit generates a short low-level pulse on the internal DAT[1] line, as if a self clearing interrupt was received from the external card. + } B; +} hw_usdhc_force_event_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_FORCE_EVENT register + */ +#define HW_USDHC_FORCE_EVENT_ADDR(x) (REGS_USDHC_BASE(x) + 0x50) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_FORCE_EVENT(x) (*(volatile hw_usdhc_force_event_t *) HW_USDHC_FORCE_EVENT_ADDR(x)) +#define HW_USDHC_FORCE_EVENT_WR(x, v) (HW_USDHC_FORCE_EVENT(x).U = (v)) +#endif + +/* + * constants & macros for individual USDHC_FORCE_EVENT bitfields + */ + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTAC12NE[0] (WORZ) + * + * Force Event Auto Command 12 Not Executed: Forces the AC12NE bit in the Auto Command12 Error + * Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTAC12NE (0) //!< Bit position for USDHC_FORCE_EVENT_FEVTAC12NE. +#define BM_USDHC_FORCE_EVENT_FEVTAC12NE (0x00000001) //!< Bit mask for USDHC_FORCE_EVENT_FEVTAC12NE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTAC12NE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTAC12NE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTAC12NE) >> BP_USDHC_FORCE_EVENT_FEVTAC12NE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTAC12NE. +#define BF_USDHC_FORCE_EVENT_FEVTAC12NE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTAC12NE) & BM_USDHC_FORCE_EVENT_FEVTAC12NE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTAC12TOE[1] (WORZ) + * + * Force Event Auto Command 12 Time Out Error: Forces the AC12TOE bit in the Auto Command12 Error + * Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTAC12TOE (1) //!< Bit position for USDHC_FORCE_EVENT_FEVTAC12TOE. +#define BM_USDHC_FORCE_EVENT_FEVTAC12TOE (0x00000002) //!< Bit mask for USDHC_FORCE_EVENT_FEVTAC12TOE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTAC12TOE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTAC12TOE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTAC12TOE) >> BP_USDHC_FORCE_EVENT_FEVTAC12TOE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTAC12TOE. +#define BF_USDHC_FORCE_EVENT_FEVTAC12TOE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTAC12TOE) & BM_USDHC_FORCE_EVENT_FEVTAC12TOE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTAC12CE[2] (WORZ) + * + * Force Event Auto Command 12 CRC Error: Forces the AC12CE bit in the Auto Command12 Error Status + * Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTAC12CE (2) //!< Bit position for USDHC_FORCE_EVENT_FEVTAC12CE. +#define BM_USDHC_FORCE_EVENT_FEVTAC12CE (0x00000004) //!< Bit mask for USDHC_FORCE_EVENT_FEVTAC12CE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTAC12CE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTAC12CE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTAC12CE) >> BP_USDHC_FORCE_EVENT_FEVTAC12CE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTAC12CE. +#define BF_USDHC_FORCE_EVENT_FEVTAC12CE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTAC12CE) & BM_USDHC_FORCE_EVENT_FEVTAC12CE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTAC12EBE[3] (WORZ) + * + * Force Event Auto Command 12 End Bit Error: Forces the AC12EBE bit in the Auto Command12 Error + * Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTAC12EBE (3) //!< Bit position for USDHC_FORCE_EVENT_FEVTAC12EBE. +#define BM_USDHC_FORCE_EVENT_FEVTAC12EBE (0x00000008) //!< Bit mask for USDHC_FORCE_EVENT_FEVTAC12EBE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTAC12EBE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTAC12EBE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTAC12EBE) >> BP_USDHC_FORCE_EVENT_FEVTAC12EBE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTAC12EBE. +#define BF_USDHC_FORCE_EVENT_FEVTAC12EBE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTAC12EBE) & BM_USDHC_FORCE_EVENT_FEVTAC12EBE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTAC12IE[4] (WORZ) + * + * Force Event Auto Command 12 Index Error: Forces the AC12IE bit in the Auto Command12 Error Status + * Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTAC12IE (4) //!< Bit position for USDHC_FORCE_EVENT_FEVTAC12IE. +#define BM_USDHC_FORCE_EVENT_FEVTAC12IE (0x00000010) //!< Bit mask for USDHC_FORCE_EVENT_FEVTAC12IE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTAC12IE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTAC12IE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTAC12IE) >> BP_USDHC_FORCE_EVENT_FEVTAC12IE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTAC12IE. +#define BF_USDHC_FORCE_EVENT_FEVTAC12IE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTAC12IE) & BM_USDHC_FORCE_EVENT_FEVTAC12IE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTCNIBAC12E[7] (WORZ) + * + * Force Event Command Not Executed By Auto Command 12 Error: Forces the CNIBAC12E bit in the Auto + * Command12 Error Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTCNIBAC12E (7) //!< Bit position for USDHC_FORCE_EVENT_FEVTCNIBAC12E. +#define BM_USDHC_FORCE_EVENT_FEVTCNIBAC12E (0x00000080) //!< Bit mask for USDHC_FORCE_EVENT_FEVTCNIBAC12E. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTCNIBAC12E from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTCNIBAC12E(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTCNIBAC12E) >> BP_USDHC_FORCE_EVENT_FEVTCNIBAC12E) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTCNIBAC12E. +#define BF_USDHC_FORCE_EVENT_FEVTCNIBAC12E(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTCNIBAC12E) & BM_USDHC_FORCE_EVENT_FEVTCNIBAC12E) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTCCE[16] (WORZ) + * + * Force Event Command Time Out Error: Forces the CTOE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTCCE (16) //!< Bit position for USDHC_FORCE_EVENT_FEVTCCE. +#define BM_USDHC_FORCE_EVENT_FEVTCCE (0x00010000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTCCE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTCCE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTCCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTCCE) >> BP_USDHC_FORCE_EVENT_FEVTCCE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTCCE. +#define BF_USDHC_FORCE_EVENT_FEVTCCE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTCCE) & BM_USDHC_FORCE_EVENT_FEVTCCE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTCCE1[17] (WORZ) + * + * Force Event Command CRC Error: Forces the CCE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTCCE1 (17) //!< Bit position for USDHC_FORCE_EVENT_FEVTCCE1. +#define BM_USDHC_FORCE_EVENT_FEVTCCE1 (0x00020000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTCCE1. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTCCE1 from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTCCE1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTCCE1) >> BP_USDHC_FORCE_EVENT_FEVTCCE1) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTCCE1. +#define BF_USDHC_FORCE_EVENT_FEVTCCE1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTCCE1) & BM_USDHC_FORCE_EVENT_FEVTCCE1) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTCEBE[18] (WORZ) + * + * Force Event Command End Bit Error: Forces the CEBE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTCEBE (18) //!< Bit position for USDHC_FORCE_EVENT_FEVTCEBE. +#define BM_USDHC_FORCE_EVENT_FEVTCEBE (0x00040000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTCEBE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTCEBE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTCEBE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTCEBE) >> BP_USDHC_FORCE_EVENT_FEVTCEBE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTCEBE. +#define BF_USDHC_FORCE_EVENT_FEVTCEBE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTCEBE) & BM_USDHC_FORCE_EVENT_FEVTCEBE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTCIE[19] (WORZ) + * + * Force Event Command Index Error: Forces the CCE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTCIE (19) //!< Bit position for USDHC_FORCE_EVENT_FEVTCIE. +#define BM_USDHC_FORCE_EVENT_FEVTCIE (0x00080000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTCIE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTCIE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTCIE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTCIE) >> BP_USDHC_FORCE_EVENT_FEVTCIE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTCIE. +#define BF_USDHC_FORCE_EVENT_FEVTCIE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTCIE) & BM_USDHC_FORCE_EVENT_FEVTCIE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTDTOE[20] (WORZ) + * + * Force Event Data Time Out Error: Force the DTOE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTDTOE (20) //!< Bit position for USDHC_FORCE_EVENT_FEVTDTOE. +#define BM_USDHC_FORCE_EVENT_FEVTDTOE (0x00100000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTDTOE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTDTOE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTDTOE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTDTOE) >> BP_USDHC_FORCE_EVENT_FEVTDTOE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTDTOE. +#define BF_USDHC_FORCE_EVENT_FEVTDTOE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTDTOE) & BM_USDHC_FORCE_EVENT_FEVTDTOE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTDCE[21] (WORZ) + * + * Force Event Data CRC Error: Forces the DCE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTDCE (21) //!< Bit position for USDHC_FORCE_EVENT_FEVTDCE. +#define BM_USDHC_FORCE_EVENT_FEVTDCE (0x00200000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTDCE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTDCE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTDCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTDCE) >> BP_USDHC_FORCE_EVENT_FEVTDCE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTDCE. +#define BF_USDHC_FORCE_EVENT_FEVTDCE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTDCE) & BM_USDHC_FORCE_EVENT_FEVTDCE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTDEBE[22] (WORZ) + * + * Force Event Data End Bit Error: Forces the DEBE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTDEBE (22) //!< Bit position for USDHC_FORCE_EVENT_FEVTDEBE. +#define BM_USDHC_FORCE_EVENT_FEVTDEBE (0x00400000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTDEBE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTDEBE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTDEBE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTDEBE) >> BP_USDHC_FORCE_EVENT_FEVTDEBE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTDEBE. +#define BF_USDHC_FORCE_EVENT_FEVTDEBE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTDEBE) & BM_USDHC_FORCE_EVENT_FEVTDEBE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTAC12E[24] (WORZ) + * + * Force Event Auto Command 12 Error: Forces the AC12E bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTAC12E (24) //!< Bit position for USDHC_FORCE_EVENT_FEVTAC12E. +#define BM_USDHC_FORCE_EVENT_FEVTAC12E (0x01000000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTAC12E. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTAC12E from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTAC12E(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTAC12E) >> BP_USDHC_FORCE_EVENT_FEVTAC12E) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTAC12E. +#define BF_USDHC_FORCE_EVENT_FEVTAC12E(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTAC12E) & BM_USDHC_FORCE_EVENT_FEVTAC12E) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTTNE[26] (WORZ) + * + * Force Tuning Error: Forces the TNE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTTNE (26) //!< Bit position for USDHC_FORCE_EVENT_FEVTTNE. +#define BM_USDHC_FORCE_EVENT_FEVTTNE (0x04000000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTTNE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTTNE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTTNE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTTNE) >> BP_USDHC_FORCE_EVENT_FEVTTNE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTTNE. +#define BF_USDHC_FORCE_EVENT_FEVTTNE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTTNE) & BM_USDHC_FORCE_EVENT_FEVTTNE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTDMAE[28] (WORZ) + * + * Force Event DMA Error: Forces the DMAE bit of Interrupt Status Register to be set + */ + +#define BP_USDHC_FORCE_EVENT_FEVTDMAE (28) //!< Bit position for USDHC_FORCE_EVENT_FEVTDMAE. +#define BM_USDHC_FORCE_EVENT_FEVTDMAE (0x10000000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTDMAE. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTDMAE from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTDMAE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTDMAE) >> BP_USDHC_FORCE_EVENT_FEVTDMAE) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTDMAE. +#define BF_USDHC_FORCE_EVENT_FEVTDMAE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTDMAE) & BM_USDHC_FORCE_EVENT_FEVTDMAE) + +/* --- Register HW_USDHC_FORCE_EVENT, field FEVTCINT[31] (WORZ) + * + * Force Event Card Interrupt: Writing 1 to this bit generates a short low-level pulse on the + * internal DAT[1] line, as if a self clearing interrupt was received from the external card. If + * enabled, the CINT bit will be set and the interrupt service routine may treat this interrupt as a + * normal interrupt from the external card. + */ + +#define BP_USDHC_FORCE_EVENT_FEVTCINT (31) //!< Bit position for USDHC_FORCE_EVENT_FEVTCINT. +#define BM_USDHC_FORCE_EVENT_FEVTCINT (0x80000000) //!< Bit mask for USDHC_FORCE_EVENT_FEVTCINT. + +//! @brief Get value of USDHC_FORCE_EVENT_FEVTCINT from a register value. +#define BG_USDHC_FORCE_EVENT_FEVTCINT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_FORCE_EVENT_FEVTCINT) >> BP_USDHC_FORCE_EVENT_FEVTCINT) + +//! @brief Format value for bitfield USDHC_FORCE_EVENT_FEVTCINT. +#define BF_USDHC_FORCE_EVENT_FEVTCINT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_FORCE_EVENT_FEVTCINT) & BM_USDHC_FORCE_EVENT_FEVTCINT) + +//------------------------------------------------------------------------------------------- +// HW_USDHC_ADMA_ERR_STATUS - ADMA Error Status Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_ADMA_ERR_STATUS - ADMA Error Status Register (RO) + * + * Reset value: 0x00000000 + * + * When an ADMA Error Interrupt has occurred, the ADMA Error States field in this register holds the + * ADMA state and the ADMA System Address register holds the address around the error descriptor. + * For recovering from this error, the Host Driver requires the ADMA state to identify the error + * descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address + * register is the error descriptor address ST_FDS: Current location set in the ADMA System Address + * register is the error descriptor address ST_CADR: This state is never set because it only + * increments the descriptor pointer and doesn't generate an ADMA error ST_TFR: Previous location + * set in the ADMA System Address register is the error descriptor address In case of a write + * operation, the Host Driver should use the ACMD22 to get the number of the written block, rather + * than using this information, since unwritten data may exist in the Host Controller. The Host + * Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid=0) + * in the ST_FDS state. The Host Driver can distinguish this error by reading the Valid bit of the + * error descriptor. ADMA Error State Coding D01-D00 ADMA Error State (when error has + * occurred) Contents of ADMA System Address Register 00 ST_STOP (Stop DMA) Holds + * the address of the next executable Descriptor command 01 ST_FDS (Fetch Descriptor) + * Holds the valid Descriptor address 10 ST_CADR (Change Address) No ADMA Error is + * generated 11 ST_TFR (Transfer Data) Holds the address of the next executable + * Descriptor command + */ +typedef union _hw_usdhc_adma_err_status +{ + reg32_t U; + struct _hw_usdhc_adma_err_status_bitfields + { + unsigned ADMAES : 2; //!< [1:0] ADMA Error State (when ADMA Error is occurred.): This field indicates the state of the ADMA when an error has occurred during an ADMA data transfer. + unsigned ADMALME : 1; //!< [2] ADMA Length Mismatch Error: This error occurs in the following 2 cases: While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length Total data length can not be divided by the block length + unsigned ADMADCE : 1; //!< [3] ADMA Descritor Error: This error occurs when invalid descriptor fetched by ADMA: + unsigned RESERVED0 : 28; //!< [31:4] Reserved + } B; +} hw_usdhc_adma_err_status_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_ADMA_ERR_STATUS register + */ +#define HW_USDHC_ADMA_ERR_STATUS_ADDR(x) (REGS_USDHC_BASE(x) + 0x54) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_ADMA_ERR_STATUS(x) (*(volatile hw_usdhc_adma_err_status_t *) HW_USDHC_ADMA_ERR_STATUS_ADDR(x)) +#define HW_USDHC_ADMA_ERR_STATUS_RD(x) (HW_USDHC_ADMA_ERR_STATUS(x).U) +#endif + +/* + * constants & macros for individual USDHC_ADMA_ERR_STATUS bitfields + */ + +/* --- Register HW_USDHC_ADMA_ERR_STATUS, field ADMAES[1:0] (RO) + * + * ADMA Error State (when ADMA Error is occurred.): This field indicates the state of the ADMA when + * an error has occurred during an ADMA data transfer. Refer to for more details. + */ + +#define BP_USDHC_ADMA_ERR_STATUS_ADMAES (0) //!< Bit position for USDHC_ADMA_ERR_STATUS_ADMAES. +#define BM_USDHC_ADMA_ERR_STATUS_ADMAES (0x00000003) //!< Bit mask for USDHC_ADMA_ERR_STATUS_ADMAES. + +//! @brief Get value of USDHC_ADMA_ERR_STATUS_ADMAES from a register value. +#define BG_USDHC_ADMA_ERR_STATUS_ADMAES(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_ADMA_ERR_STATUS_ADMAES) >> BP_USDHC_ADMA_ERR_STATUS_ADMAES) + +/* --- Register HW_USDHC_ADMA_ERR_STATUS, field ADMALME[2] (RO) + * + * ADMA Length Mismatch Error: This error occurs in the following 2 cases: While the Block Count + * Enable is being set, the total data length specified by the Descriptor table is different from + * that specified by the Block Count and Block Length Total data length can not be divided by the + * block length + * + * Values: + * 0 - No Error + * 1 - Error + */ + +#define BP_USDHC_ADMA_ERR_STATUS_ADMALME (2) //!< Bit position for USDHC_ADMA_ERR_STATUS_ADMALME. +#define BM_USDHC_ADMA_ERR_STATUS_ADMALME (0x00000004) //!< Bit mask for USDHC_ADMA_ERR_STATUS_ADMALME. + +//! @brief Get value of USDHC_ADMA_ERR_STATUS_ADMALME from a register value. +#define BG_USDHC_ADMA_ERR_STATUS_ADMALME(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_ADMA_ERR_STATUS_ADMALME) >> BP_USDHC_ADMA_ERR_STATUS_ADMALME) + + +/* --- Register HW_USDHC_ADMA_ERR_STATUS, field ADMADCE[3] (RO) + * + * ADMA Descritor Error: This error occurs when invalid descriptor fetched by ADMA: + * + * Values: + * 0 - No Error + * 1 - Error + */ + +#define BP_USDHC_ADMA_ERR_STATUS_ADMADCE (3) //!< Bit position for USDHC_ADMA_ERR_STATUS_ADMADCE. +#define BM_USDHC_ADMA_ERR_STATUS_ADMADCE (0x00000008) //!< Bit mask for USDHC_ADMA_ERR_STATUS_ADMADCE. + +//! @brief Get value of USDHC_ADMA_ERR_STATUS_ADMADCE from a register value. +#define BG_USDHC_ADMA_ERR_STATUS_ADMADCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_ADMA_ERR_STATUS_ADMADCE) >> BP_USDHC_ADMA_ERR_STATUS_ADMADCE) + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_ADMA_SYS_ADDR - ADMA System Address +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_ADMA_SYS_ADDR - ADMA System Address (RW) + * + * Reset value: 0x00000000 + * + * This register contains the physical system memory address used for ADMA transfers. + */ +typedef union _hw_usdhc_adma_sys_addr +{ + reg32_t U; + struct _hw_usdhc_adma_sys_addr_bitfields + { + unsigned RESERVED0 : 2; //!< [1:0] Reserved + unsigned ADS_ADDR : 30; //!< [31:2] ADMA System Address: This register holds the word address of the executing command in the Descriptor table. + } B; +} hw_usdhc_adma_sys_addr_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_ADMA_SYS_ADDR register + */ +#define HW_USDHC_ADMA_SYS_ADDR_ADDR(x) (REGS_USDHC_BASE(x) + 0x58) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_ADMA_SYS_ADDR(x) (*(volatile hw_usdhc_adma_sys_addr_t *) HW_USDHC_ADMA_SYS_ADDR_ADDR(x)) +#define HW_USDHC_ADMA_SYS_ADDR_RD(x) (HW_USDHC_ADMA_SYS_ADDR(x).U) +#define HW_USDHC_ADMA_SYS_ADDR_WR(x, v) (HW_USDHC_ADMA_SYS_ADDR(x).U = (v)) +#define HW_USDHC_ADMA_SYS_ADDR_SET(x, v) (HW_USDHC_ADMA_SYS_ADDR_WR(x, HW_USDHC_ADMA_SYS_ADDR_RD(x) | (v))) +#define HW_USDHC_ADMA_SYS_ADDR_CLR(x, v) (HW_USDHC_ADMA_SYS_ADDR_WR(x, HW_USDHC_ADMA_SYS_ADDR_RD(x) & ~(v))) +#define HW_USDHC_ADMA_SYS_ADDR_TOG(x, v) (HW_USDHC_ADMA_SYS_ADDR_WR(x, HW_USDHC_ADMA_SYS_ADDR_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_ADMA_SYS_ADDR bitfields + */ + +/* --- Register HW_USDHC_ADMA_SYS_ADDR, field ADS_ADDR[31:2] (RW) + * + * ADMA System Address: This register holds the word address of the executing command in the + * Descriptor table. At the start of ADMA, the Host Driver shall set the start address of the + * Descriptor table. The ADMA engine increments this register address whenever fetching a Descriptor + * command. When the ADMA is stopped at the Block Gap, this register indicates the address of the + * next executable Descriptor command. When the ADMA Error Interrupt is generated, this register + * shall hold the valid Descriptor address depending on the ADMA state. The lower 2 bits of this + * register is tied to '0' so the ADMA address is always word aligned. Since this register supports + * dynamic address reflecting, when TC bit is set, it automatically alters the value of internal + * address counter, so SW cannot change this register when TC bit is set. Such restriction is also + * listed in . + */ + +#define BP_USDHC_ADMA_SYS_ADDR_ADS_ADDR (2) //!< Bit position for USDHC_ADMA_SYS_ADDR_ADS_ADDR. +#define BM_USDHC_ADMA_SYS_ADDR_ADS_ADDR (0xfffffffc) //!< Bit mask for USDHC_ADMA_SYS_ADDR_ADS_ADDR. + +//! @brief Get value of USDHC_ADMA_SYS_ADDR_ADS_ADDR from a register value. +#define BG_USDHC_ADMA_SYS_ADDR_ADS_ADDR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_ADMA_SYS_ADDR_ADS_ADDR) >> BP_USDHC_ADMA_SYS_ADDR_ADS_ADDR) + +//! @brief Format value for bitfield USDHC_ADMA_SYS_ADDR_ADS_ADDR. +#define BF_USDHC_ADMA_SYS_ADDR_ADS_ADDR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_ADMA_SYS_ADDR_ADS_ADDR) & BM_USDHC_ADMA_SYS_ADDR_ADS_ADDR) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the ADS_ADDR field to a new value. +#define BW_USDHC_ADMA_SYS_ADDR_ADS_ADDR(x, v) (HW_USDHC_ADMA_SYS_ADDR_WR(x, (HW_USDHC_ADMA_SYS_ADDR_RD(x) & ~BM_USDHC_ADMA_SYS_ADDR_ADS_ADDR) | BF_USDHC_ADMA_SYS_ADDR_ADS_ADDR(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_DLL_CTRL - DLL (Delay Line) Control +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_DLL_CTRL - DLL (Delay Line) Control (RW) + * + * Reset value: 0x00000000 + * + * This register contains control bits for DLL. + */ +typedef union _hw_usdhc_dll_ctrl +{ + reg32_t U; + struct _hw_usdhc_dll_ctrl_bitfields + { + unsigned DLL_CTRL_ENABLE : 1; //!< [0] Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL. + unsigned DLL_CTRL_RESET : 1; //!< [1] Setting this bit to 1 force a reset on DLL. + unsigned DLL_CTRL_SLV_FORCE_UPD : 1; //!< [2] Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately. + unsigned DLL_CTRL_SLV_DLY_TARGET : 4; //!< [6:3] The delay target for the uSDHC loopback read clock can be programmed in 1/16th increments of an ref_clock half-period. + unsigned DLL_CTRL_GATE_UPDATE : 1; //!< [7] Set this bit to 1 to force DLL not update from now on.Since when clock_in exists, glitches might appear during update. + unsigned DLL_CTRL_SLV_OVERRIDE : 1; //!< [8] Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override. + unsigned DLL_CTRL_SLV_OVERRIDE_VAL : 7; //!< [15:9] When SLV_OVERRIDE=1 This field is used to select 1 of 128 physical taps manually. + unsigned DLL_CTRL_SLV_DLY_TARGET1 : 3; //!< [18:16] Refer to DLL_CTRL_SLV_DLY_TARGET[3:0] below. + unsigned RESERVED0 : 1; //!< [19] Reserved + unsigned DLL_CTRL_SLV_UPDATE_INT : 8; //!< [27:20] slave delay line update interval. + unsigned DLL_CTRL_REF_UPDATE_INT : 4; //!< [31:28] DLL control loop update interval. + } B; +} hw_usdhc_dll_ctrl_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_DLL_CTRL register + */ +#define HW_USDHC_DLL_CTRL_ADDR(x) (REGS_USDHC_BASE(x) + 0x60) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_DLL_CTRL(x) (*(volatile hw_usdhc_dll_ctrl_t *) HW_USDHC_DLL_CTRL_ADDR(x)) +#define HW_USDHC_DLL_CTRL_RD(x) (HW_USDHC_DLL_CTRL(x).U) +#define HW_USDHC_DLL_CTRL_WR(x, v) (HW_USDHC_DLL_CTRL(x).U = (v)) +#define HW_USDHC_DLL_CTRL_SET(x, v) (HW_USDHC_DLL_CTRL_WR(x, HW_USDHC_DLL_CTRL_RD(x) | (v))) +#define HW_USDHC_DLL_CTRL_CLR(x, v) (HW_USDHC_DLL_CTRL_WR(x, HW_USDHC_DLL_CTRL_RD(x) & ~(v))) +#define HW_USDHC_DLL_CTRL_TOG(x, v) (HW_USDHC_DLL_CTRL_WR(x, HW_USDHC_DLL_CTRL_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_DLL_CTRL bitfields + */ + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_ENABLE[0] (RW) + * + * Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL. Note + * that using the slave delay line override feature with SLV_OVERRIDE and SLV_OVERRIDE VAL, the DLL + * does not need to be enabled + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_ENABLE (0) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_ENABLE. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_ENABLE (0x00000001) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_ENABLE. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_ENABLE from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_ENABLE) >> BP_USDHC_DLL_CTRL_DLL_CTRL_ENABLE) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_ENABLE. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_ENABLE) & BM_USDHC_DLL_CTRL_DLL_CTRL_ENABLE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_ENABLE field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_ENABLE) | BF_USDHC_DLL_CTRL_DLL_CTRL_ENABLE(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_RESET[1] (RW) + * + * Setting this bit to 1 force a reset on DLL. This will cause the DLL to lose lock and re-calibrate + * to detect an ref_clock half period phase shift. This signal is used by the DLL as edge-sensitive, + * so in order to create a subsequent reset, RESET must be taken low and then asserted again + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_RESET (1) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_RESET. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_RESET (0x00000002) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_RESET. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_RESET from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_RESET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_RESET) >> BP_USDHC_DLL_CTRL_DLL_CTRL_RESET) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_RESET. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_RESET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_RESET) & BM_USDHC_DLL_CTRL_DLL_CTRL_RESET) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_RESET field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_RESET(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_RESET) | BF_USDHC_DLL_CTRL_DLL_CTRL_RESET(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_SLV_FORCE_UPD[2] (RW) + * + * Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value + * immediately. The slave delay line shall update automatically based on the SLV_UPDATE_INT interval + * or when a DLL lock condition is sensed. Subsequent forcing of the slave-line update can only + * occur if SLV_FORCE_UP is set back to 0 and then asserted again (edge triggered). Be sure to use + * it when uSDHC is idle. This function may not work when uSDHC is working on data/cmd/response. + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD (2) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD (0x00000004) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD) >> BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_SLV_FORCE_UPD field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD) | BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_SLV_DLY_TARGET[6:3] (RW) + * + * The delay target for the uSDHC loopback read clock can be programmed in 1/16th increments of an + * ref_clock half-period. The delay is ((DLL_CTRL_SLV_DLY_TARGET[6:0] +1)* ref_clock/2)/16 So the + * input read-clock can be delayed relative input data from (ref_clock/2)/16 to ref_clock*4 + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET (3) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET (0x00000078) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET) >> BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_SLV_DLY_TARGET field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET) | BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_GATE_UPDATE[7] (RW) + * + * Set this bit to 1 to force DLL not update from now on.Since when clock_in exists, glitches might + * appear during update. This bit is used by software if we met such kind of condition. Set it to 0 + * to let DLL update automatically + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE (7) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE (0x00000080) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE) >> BP_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE) & BM_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_GATE_UPDATE field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE) | BF_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_SLV_OVERRIDE[8] (RW) + * + * Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set + * 0 to disable manual override. This feature does not require the DLL to tbe enabled using the + * ENABLE bit. In fact to reduce power, if SLV_OVERRIDE is used, it is recommended to disable the + * DLL with ENABLE=0 + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE (8) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE (0x00000100) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE) >> BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_SLV_OVERRIDE field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE) | BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_SLV_OVERRIDE_VAL[15:9] (RW) + * + * When SLV_OVERRIDE=1 This field is used to select 1 of 128 physical taps manually. A value of 0 + * selects tap 1, and a value of 0x7f selects tap 128. + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL (9) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL (0x0000fe00) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL) >> BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_SLV_OVERRIDE_VAL field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL) | BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_SLV_DLY_TARGET1[18:16] (RW) + * + * Refer to DLL_CTRL_SLV_DLY_TARGET[3:0] below. + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 (16) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 (0x00070000) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1) >> BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_SLV_DLY_TARGET1 field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1) | BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_SLV_UPDATE_INT[27:20] (RW) + * + * slave delay line update interval. If default 0 is used, it means 256 cycles of ref_clock. A value + * of 0x0f results in 15 cycles and so on. Note that software can always cause an update of the + * slave-delay line using the SLV_FORCE_UPDATE register. Note that the slave delay line will also + * update automatically when the reference DLL transitions to a locked state (from an un-locked + * state). + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT (20) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT (0x0ff00000) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT) >> BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT) & BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_SLV_UPDATE_INT field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT) | BF_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(v))) +#endif + +/* --- Register HW_USDHC_DLL_CTRL, field DLL_CTRL_REF_UPDATE_INT[31:28] (RW) + * + * DLL control loop update interval. The interval cycle is (2 + REF_UPDATE_INT) * ref_clock. By + * default, the DLL control loop shall update every two ref_clock cycles. It should be noted that + * increasing the reference delay-line update interval reduces the ability of the DLL to adjust to + * fast changes in conditions that may effect the delay (such as voltage and temperature) + */ + +#define BP_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT (28) //!< Bit position for USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT. +#define BM_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT (0xf0000000) //!< Bit mask for USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT. + +//! @brief Get value of USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT from a register value. +#define BG_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT) >> BP_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT) + +//! @brief Format value for bitfield USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT. +#define BF_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT) & BM_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLL_CTRL_REF_UPDATE_INT field to a new value. +#define BW_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x, v) (HW_USDHC_DLL_CTRL_WR(x, (HW_USDHC_DLL_CTRL_RD(x) & ~BM_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT) | BF_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_DLL_STATUS - DLL Status +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_DLL_STATUS - DLL Status (RO) + * + * Reset value: 0x00000000 + * + * This register contains the DLL status information. All bits are read only and will read the same + * as the power-reset value. + */ +typedef union _hw_usdhc_dll_status +{ + reg32_t U; + struct _hw_usdhc_dll_status_bitfields + { + unsigned DLL_STS_SLV_LOCK : 1; //!< [0] Slave delay-line lock status. + unsigned DLL_STS_REF_LOCK : 1; //!< [1] Reference DLL lock status. + unsigned DLL_STS_SLV_SEL : 7; //!< [8:2] Slave delay line select status. + unsigned DLL_STS_REF_SEL : 7; //!< [15:9] Reference delay line select taps. + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_usdhc_dll_status_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_DLL_STATUS register + */ +#define HW_USDHC_DLL_STATUS_ADDR(x) (REGS_USDHC_BASE(x) + 0x64) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_DLL_STATUS(x) (*(volatile hw_usdhc_dll_status_t *) HW_USDHC_DLL_STATUS_ADDR(x)) +#define HW_USDHC_DLL_STATUS_RD(x) (HW_USDHC_DLL_STATUS(x).U) +#endif + +/* + * constants & macros for individual USDHC_DLL_STATUS bitfields + */ + +/* --- Register HW_USDHC_DLL_STATUS, field DLL_STS_SLV_LOCK[0] (RO) + * + * Slave delay-line lock status. This signifies that a valid calibration has been set to the slave- + * delay line and that the slave-delay line is implementing the programmed delay value + */ + +#define BP_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK (0) //!< Bit position for USDHC_DLL_STATUS_DLL_STS_SLV_LOCK. +#define BM_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK (0x00000001) //!< Bit mask for USDHC_DLL_STATUS_DLL_STS_SLV_LOCK. + +//! @brief Get value of USDHC_DLL_STATUS_DLL_STS_SLV_LOCK from a register value. +#define BG_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK) >> BP_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK) + +/* --- Register HW_USDHC_DLL_STATUS, field DLL_STS_REF_LOCK[1] (RO) + * + * Reference DLL lock status. This signifies that the DLL has detected and locked to a half-phase + * ref_clock shift, allowing the slave delay-line to perform programmed clock delays + */ + +#define BP_USDHC_DLL_STATUS_DLL_STS_REF_LOCK (1) //!< Bit position for USDHC_DLL_STATUS_DLL_STS_REF_LOCK. +#define BM_USDHC_DLL_STATUS_DLL_STS_REF_LOCK (0x00000002) //!< Bit mask for USDHC_DLL_STATUS_DLL_STS_REF_LOCK. + +//! @brief Get value of USDHC_DLL_STATUS_DLL_STS_REF_LOCK from a register value. +#define BG_USDHC_DLL_STATUS_DLL_STS_REF_LOCK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_STATUS_DLL_STS_REF_LOCK) >> BP_USDHC_DLL_STATUS_DLL_STS_REF_LOCK) + +/* --- Register HW_USDHC_DLL_STATUS, field DLL_STS_SLV_SEL[8:2] (RO) + * + * Slave delay line select status. This is the instant value generated from reference chain. Since + * only when ref_lock is detected can the reference chain get updated, this value should be the + * right value next be update to the slave line when reference is locked. + */ + +#define BP_USDHC_DLL_STATUS_DLL_STS_SLV_SEL (2) //!< Bit position for USDHC_DLL_STATUS_DLL_STS_SLV_SEL. +#define BM_USDHC_DLL_STATUS_DLL_STS_SLV_SEL (0x000001fc) //!< Bit mask for USDHC_DLL_STATUS_DLL_STS_SLV_SEL. + +//! @brief Get value of USDHC_DLL_STATUS_DLL_STS_SLV_SEL from a register value. +#define BG_USDHC_DLL_STATUS_DLL_STS_SLV_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_STATUS_DLL_STS_SLV_SEL) >> BP_USDHC_DLL_STATUS_DLL_STS_SLV_SEL) + +/* --- Register HW_USDHC_DLL_STATUS, field DLL_STS_REF_SEL[15:9] (RO) + * + * Reference delay line select taps. Be noted this is encoded by 7 bits for 127taps. + */ + +#define BP_USDHC_DLL_STATUS_DLL_STS_REF_SEL (9) //!< Bit position for USDHC_DLL_STATUS_DLL_STS_REF_SEL. +#define BM_USDHC_DLL_STATUS_DLL_STS_REF_SEL (0x0000fe00) //!< Bit mask for USDHC_DLL_STATUS_DLL_STS_REF_SEL. + +//! @brief Get value of USDHC_DLL_STATUS_DLL_STS_REF_SEL from a register value. +#define BG_USDHC_DLL_STATUS_DLL_STS_REF_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_DLL_STATUS_DLL_STS_REF_SEL) >> BP_USDHC_DLL_STATUS_DLL_STS_REF_SEL) + +//------------------------------------------------------------------------------------------- +// HW_USDHC_CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status (RW) + * + * Reset value: 0x00000000 + * + * This register contains the Clock Tuning Control status information. All bits are read only and + * will read the same as the power-reset value. This register is added to support SD3.0 UHS-I SDR104 + * mode. + */ +typedef union _hw_usdhc_clk_tune_ctrl_status +{ + reg32_t U; + struct _hw_usdhc_clk_tune_ctrl_status_bitfields + { + unsigned DLY_CELL_SET_POST : 4; //!< [3:0] Set the number of delay cells on the feedback clock between CLK_OUT and CLK_POST. + unsigned DLY_CELL_SET_OUT : 4; //!< [7:4] Set the number of delay cells on the feedback clock between CLK_PRE and CLK_OUT. + unsigned DLY_CELL_SET_PRE : 7; //!< [14:8] Set the number of delay cells on the feedback clock between the feedback clock and CLK_PRE. + unsigned NXT_ERR : 1; //!< [15] NXT error which means the number of delay cells added on the feedback clock is too large. + unsigned TAP_SEL_POST : 4; //!< [19:16] Reflect the number of delay cells added on the feedback clock between CLK_OUT and CLK_POST. + unsigned TAP_SEL_OUT : 4; //!< [23:20] Reflect the number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT. + unsigned TAP_SEL_PRE : 7; //!< [30:24] Reflect the number of delay cells added on the feedback clock between the feedback clock and CLK_PRE. + unsigned PRE_ERR : 1; //!< [31] PRE error which means the number of delay cells added on the feedback clock is too small. + } B; +} hw_usdhc_clk_tune_ctrl_status_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_CLK_TUNE_CTRL_STATUS register + */ +#define HW_USDHC_CLK_TUNE_CTRL_STATUS_ADDR(x) (REGS_USDHC_BASE(x) + 0x68) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_CLK_TUNE_CTRL_STATUS(x) (*(volatile hw_usdhc_clk_tune_ctrl_status_t *) HW_USDHC_CLK_TUNE_CTRL_STATUS_ADDR(x)) +#define HW_USDHC_CLK_TUNE_CTRL_STATUS_RD(x) (HW_USDHC_CLK_TUNE_CTRL_STATUS(x).U) +#define HW_USDHC_CLK_TUNE_CTRL_STATUS_WR(x, v) (HW_USDHC_CLK_TUNE_CTRL_STATUS(x).U = (v)) +#define HW_USDHC_CLK_TUNE_CTRL_STATUS_SET(x, v) (HW_USDHC_CLK_TUNE_CTRL_STATUS_WR(x, HW_USDHC_CLK_TUNE_CTRL_STATUS_RD(x) | (v))) +#define HW_USDHC_CLK_TUNE_CTRL_STATUS_CLR(x, v) (HW_USDHC_CLK_TUNE_CTRL_STATUS_WR(x, HW_USDHC_CLK_TUNE_CTRL_STATUS_RD(x) & ~(v))) +#define HW_USDHC_CLK_TUNE_CTRL_STATUS_TOG(x, v) (HW_USDHC_CLK_TUNE_CTRL_STATUS_WR(x, HW_USDHC_CLK_TUNE_CTRL_STATUS_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_CLK_TUNE_CTRL_STATUS bitfields + */ + +/* --- Register HW_USDHC_CLK_TUNE_CTRL_STATUS, field DLY_CELL_SET_POST[3:0] (RW) + * + * Set the number of delay cells on the feedback clock between CLK_OUT and CLK_POST. + */ + +#define BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST (0) //!< Bit position for USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST. +#define BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST (0x0000000f) //!< Bit mask for USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST. + +//! @brief Get value of USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST from a register value. +#define BG_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST) >> BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST) + +//! @brief Format value for bitfield USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST. +#define BF_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST) & BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLY_CELL_SET_POST field to a new value. +#define BW_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x, v) (HW_USDHC_CLK_TUNE_CTRL_STATUS_WR(x, (HW_USDHC_CLK_TUNE_CTRL_STATUS_RD(x) & ~BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST) | BF_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(v))) +#endif + +/* --- Register HW_USDHC_CLK_TUNE_CTRL_STATUS, field DLY_CELL_SET_OUT[7:4] (RW) + * + * Set the number of delay cells on the feedback clock between CLK_PRE and CLK_OUT. + */ + +#define BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT (4) //!< Bit position for USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT. +#define BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT (0x000000f0) //!< Bit mask for USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT. + +//! @brief Get value of USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT from a register value. +#define BG_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT) >> BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT) + +//! @brief Format value for bitfield USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT. +#define BF_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT) & BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLY_CELL_SET_OUT field to a new value. +#define BW_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x, v) (HW_USDHC_CLK_TUNE_CTRL_STATUS_WR(x, (HW_USDHC_CLK_TUNE_CTRL_STATUS_RD(x) & ~BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT) | BF_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(v))) +#endif + +/* --- Register HW_USDHC_CLK_TUNE_CTRL_STATUS, field DLY_CELL_SET_PRE[14:8] (RW) + * + * Set the number of delay cells on the feedback clock between the feedback clock and CLK_PRE. + */ + +#define BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE (8) //!< Bit position for USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE. +#define BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE (0x00007f00) //!< Bit mask for USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE. + +//! @brief Get value of USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE from a register value. +#define BG_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE) >> BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE) + +//! @brief Format value for bitfield USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE. +#define BF_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE) & BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DLY_CELL_SET_PRE field to a new value. +#define BW_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x, v) (HW_USDHC_CLK_TUNE_CTRL_STATUS_WR(x, (HW_USDHC_CLK_TUNE_CTRL_STATUS_RD(x) & ~BM_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE) | BF_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(v))) +#endif + +/* --- Register HW_USDHC_CLK_TUNE_CTRL_STATUS, field NXT_ERR[15] (RO) + * + * NXT error which means the number of delay cells added on the feedback clock is too large. It's + * valid only when SMP_CLK_SEL of Mix control register(bit23 of 0x48) is enabled. + */ + +#define BP_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR (15) //!< Bit position for USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR. +#define BM_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR (0x00008000) //!< Bit mask for USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR. + +//! @brief Get value of USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR from a register value. +#define BG_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR) >> BP_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR) + +/* --- Register HW_USDHC_CLK_TUNE_CTRL_STATUS, field TAP_SEL_POST[19:16] (RO) + * + * Reflect the number of delay cells added on the feedback clock between CLK_OUT and CLK_POST. + */ + +#define BP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST (16) //!< Bit position for USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST. +#define BM_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST (0x000f0000) //!< Bit mask for USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST. + +//! @brief Get value of USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST from a register value. +#define BG_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST) >> BP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST) + +/* --- Register HW_USDHC_CLK_TUNE_CTRL_STATUS, field TAP_SEL_OUT[23:20] (RO) + * + * Reflect the number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT. + */ + +#define BP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT (20) //!< Bit position for USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT. +#define BM_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT (0x00f00000) //!< Bit mask for USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT. + +//! @brief Get value of USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT from a register value. +#define BG_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT) >> BP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT) + +/* --- Register HW_USDHC_CLK_TUNE_CTRL_STATUS, field TAP_SEL_PRE[30:24] (RO) + * + * Reflect the number of delay cells added on the feedback clock between the feedback clock and + * CLK_PRE. When AUTO_TUNE_EN(bit24 of 0x48) is disabled, TAP_SEL_PRE is always equal to + * DLY_CELL_SET_PRE. When AUTO_TUNE_EN(bit24 of 0x48) is enabled, TAP_SEL_PRE will be updated + * automatically according to the status of the auto tuning circuit to adjust the sample clock + * phase. + */ + +#define BP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE (24) //!< Bit position for USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE. +#define BM_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE (0x7f000000) //!< Bit mask for USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE. + +//! @brief Get value of USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE from a register value. +#define BG_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE) >> BP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE) + +/* --- Register HW_USDHC_CLK_TUNE_CTRL_STATUS, field PRE_ERR[31] (RO) + * + * PRE error which means the number of delay cells added on the feedback clock is too small. It's + * valid only when SMP_CLK_SEL of Mix control register(bit23 of 0x48) is enabled. + */ + +#define BP_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR (31) //!< Bit position for USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR. +#define BM_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR (0x80000000) //!< Bit mask for USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR. + +//! @brief Get value of USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR from a register value. +#define BG_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR) >> BP_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR) + +//------------------------------------------------------------------------------------------- +// HW_USDHC_VEND_SPEC - Vendor Specific Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_VEND_SPEC - Vendor Specific Register (RW) + * + * Reset value: 0x20007809 + * + * This register contains the vendor specific control/status register. + */ +typedef union _hw_usdhc_vend_spec +{ + reg32_t U; + struct _hw_usdhc_vend_spec_bitfields + { + unsigned EXT_DMA_EN : 1; //!< [0] External DMA Request Enable Enable the request to external DMA. + unsigned VSELECT : 1; //!< [1] Voltage Selection Change the value of output signal VSELECT, to control the voltage on pads for external card. + unsigned CONFLICT_CHK_EN : 1; //!< [2] It's not implemented in uSDHC IP. + unsigned AC12_WR_CHKBUSY_EN : 1; //!< [3] Check busy enable after auto CMD12 for write data packet + unsigned DAT3_CD_POL : 1; //!< [4] This bit only uses for debugging. + unsigned CD_POL : 1; //!< [5] This bit only uses for debugging. + unsigned WP_POL : 1; //!< [6] This bit only uses for debugging. + unsigned CLKONJ_IN_ABORT : 1; //!< [7] This bit only uses for debugging. + unsigned FRC_SDCLK_ON : 1; //!< [8] Force CLK output active: + unsigned AC12_ISNOT_ABORT : 1; //!< [9] This bit only uses for debugging. + unsigned DDREN_ACT_ATONCE : 1; //!< [10] This bit only uses for debugging. + unsigned IPG_CLK_SOFT_EN : 1; //!< [11] IPG_CLK software enable + unsigned HCLK_SOFT_EN : 1; //!< [12] Please note, hardware auto-enables the AHB clock when the internal DMA is enabled even if HCLK_SOFT_EN is 0. + unsigned IPG_PERCLK_SOFT_EN : 1; //!< [13] ipg_perclk software enable + unsigned CARD_CLK_SOFT_EN : 1; //!< [14] card clock software enable + unsigned CRC_CHK_DIS : 1; //!< [15] CRC check disable + unsigned INT_ST_VAL : 8; //!< [23:16] Internal State Value Internal state value, reflecting the corresponding state value selected by Debug Select field. + unsigned DBG_SEL : 4; //!< [27:24] Debug Select Select the internal sub-module to show its internal state value. + unsigned CMD_OE_PRE_EN : 1; //!< [28] Only for debug. + unsigned AC12_RD_CHKBUSY_EN : 1; //!< [29] Only for debug. + unsigned CARD_DET_IN_IDLE_ENJ : 1; //!< [30] Only for debug. + unsigned RESERVED0 : 1; //!< [31] Reserved + } B; +} hw_usdhc_vend_spec_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_VEND_SPEC register + */ +#define HW_USDHC_VEND_SPEC_ADDR(x) (REGS_USDHC_BASE(x) + 0xc0) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_VEND_SPEC(x) (*(volatile hw_usdhc_vend_spec_t *) HW_USDHC_VEND_SPEC_ADDR(x)) +#define HW_USDHC_VEND_SPEC_RD(x) (HW_USDHC_VEND_SPEC(x).U) +#define HW_USDHC_VEND_SPEC_WR(x, v) (HW_USDHC_VEND_SPEC(x).U = (v)) +#define HW_USDHC_VEND_SPEC_SET(x, v) (HW_USDHC_VEND_SPEC_WR(x, HW_USDHC_VEND_SPEC_RD(x) | (v))) +#define HW_USDHC_VEND_SPEC_CLR(x, v) (HW_USDHC_VEND_SPEC_WR(x, HW_USDHC_VEND_SPEC_RD(x) & ~(v))) +#define HW_USDHC_VEND_SPEC_TOG(x, v) (HW_USDHC_VEND_SPEC_WR(x, HW_USDHC_VEND_SPEC_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_VEND_SPEC bitfields + */ + +/* --- Register HW_USDHC_VEND_SPEC, field EXT_DMA_EN[0] (RW) + * + * External DMA Request Enable Enable the request to external DMA. When the internal DMA (either + * Simple DMA or Advanced DMA) is not in use, and this bit is set, uSDHC will send out DMA request + * when the internal buffer is ready. This bit is particularly useful when transferring data by ARM + * platform polling mode, and it is not allowed to send out the external DMA request. By default, + * this bit is set. + * + * Values: + * 0 - In any scenario, uSDHC does not send out external DMA request + * 1 - When internal DMA is not active, the external DMA request will be sent out + */ + +#define BP_USDHC_VEND_SPEC_EXT_DMA_EN (0) //!< Bit position for USDHC_VEND_SPEC_EXT_DMA_EN. +#define BM_USDHC_VEND_SPEC_EXT_DMA_EN (0x00000001) //!< Bit mask for USDHC_VEND_SPEC_EXT_DMA_EN. + +//! @brief Get value of USDHC_VEND_SPEC_EXT_DMA_EN from a register value. +#define BG_USDHC_VEND_SPEC_EXT_DMA_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_EXT_DMA_EN) >> BP_USDHC_VEND_SPEC_EXT_DMA_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_EXT_DMA_EN. +#define BF_USDHC_VEND_SPEC_EXT_DMA_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_EXT_DMA_EN) & BM_USDHC_VEND_SPEC_EXT_DMA_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the EXT_DMA_EN field to a new value. +#define BW_USDHC_VEND_SPEC_EXT_DMA_EN(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_EXT_DMA_EN) | BF_USDHC_VEND_SPEC_EXT_DMA_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field VSELECT[1] (RW) + * + * Voltage Selection Change the value of output signal VSELECT, to control the voltage on pads for + * external card. There must be a control circuit out of uSDHC to change the voltage on pads. + * + * Values: + * 0 - Change the voltage to high voltage range, around 3.0V + * 1 - Change the voltage to low voltage range, around 1.8V + */ + +#define BP_USDHC_VEND_SPEC_VSELECT (1) //!< Bit position for USDHC_VEND_SPEC_VSELECT. +#define BM_USDHC_VEND_SPEC_VSELECT (0x00000002) //!< Bit mask for USDHC_VEND_SPEC_VSELECT. + +//! @brief Get value of USDHC_VEND_SPEC_VSELECT from a register value. +#define BG_USDHC_VEND_SPEC_VSELECT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_VSELECT) >> BP_USDHC_VEND_SPEC_VSELECT) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_VSELECT. +#define BF_USDHC_VEND_SPEC_VSELECT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_VSELECT) & BM_USDHC_VEND_SPEC_VSELECT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the VSELECT field to a new value. +#define BW_USDHC_VEND_SPEC_VSELECT(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_VSELECT) | BF_USDHC_VEND_SPEC_VSELECT(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field CONFLICT_CHK_EN[2] (RW) + * + * It's not implemented in uSDHC IP. Conflict check enable. + * + * Values: + * 0 - conflict check disable + * 1 - conflict check enable + */ + +#define BP_USDHC_VEND_SPEC_CONFLICT_CHK_EN (2) //!< Bit position for USDHC_VEND_SPEC_CONFLICT_CHK_EN. +#define BM_USDHC_VEND_SPEC_CONFLICT_CHK_EN (0x00000004) //!< Bit mask for USDHC_VEND_SPEC_CONFLICT_CHK_EN. + +//! @brief Get value of USDHC_VEND_SPEC_CONFLICT_CHK_EN from a register value. +#define BG_USDHC_VEND_SPEC_CONFLICT_CHK_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_CONFLICT_CHK_EN) >> BP_USDHC_VEND_SPEC_CONFLICT_CHK_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_CONFLICT_CHK_EN. +#define BF_USDHC_VEND_SPEC_CONFLICT_CHK_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_CONFLICT_CHK_EN) & BM_USDHC_VEND_SPEC_CONFLICT_CHK_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CONFLICT_CHK_EN field to a new value. +#define BW_USDHC_VEND_SPEC_CONFLICT_CHK_EN(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_CONFLICT_CHK_EN) | BF_USDHC_VEND_SPEC_CONFLICT_CHK_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field AC12_WR_CHKBUSY_EN[3] (RW) + * + * Check busy enable after auto CMD12 for write data packet + * + * Values: + * 0 - Not check busy after auto CMD12 for write data packet + * 1 - Check busy after auto CMD12 for write data packet + */ + +#define BP_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN (3) //!< Bit position for USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN. +#define BM_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN (0x00000008) //!< Bit mask for USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN. + +//! @brief Get value of USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN from a register value. +#define BG_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN) >> BP_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN. +#define BF_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN) & BM_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC12_WR_CHKBUSY_EN field to a new value. +#define BW_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN) | BF_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field DAT3_CD_POL[4] (RW) + * + * This bit only uses for debugging. Polarity of Dat3 pin when it's used as card detection: + * + * Values: + * 0 - card detected when DAT3 is high + * 1 - card detected when DAT3 is low + */ + +#define BP_USDHC_VEND_SPEC_DAT3_CD_POL (4) //!< Bit position for USDHC_VEND_SPEC_DAT3_CD_POL. +#define BM_USDHC_VEND_SPEC_DAT3_CD_POL (0x00000010) //!< Bit mask for USDHC_VEND_SPEC_DAT3_CD_POL. + +//! @brief Get value of USDHC_VEND_SPEC_DAT3_CD_POL from a register value. +#define BG_USDHC_VEND_SPEC_DAT3_CD_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_DAT3_CD_POL) >> BP_USDHC_VEND_SPEC_DAT3_CD_POL) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_DAT3_CD_POL. +#define BF_USDHC_VEND_SPEC_DAT3_CD_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_DAT3_CD_POL) & BM_USDHC_VEND_SPEC_DAT3_CD_POL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DAT3_CD_POL field to a new value. +#define BW_USDHC_VEND_SPEC_DAT3_CD_POL(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_DAT3_CD_POL) | BF_USDHC_VEND_SPEC_DAT3_CD_POL(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field CD_POL[5] (RW) + * + * This bit only uses for debugging. Polarity of the CD pin: + * + * Values: + * 0 - CD pin is low active + * 1 - CD pin is high active + */ + +#define BP_USDHC_VEND_SPEC_CD_POL (5) //!< Bit position for USDHC_VEND_SPEC_CD_POL. +#define BM_USDHC_VEND_SPEC_CD_POL (0x00000020) //!< Bit mask for USDHC_VEND_SPEC_CD_POL. + +//! @brief Get value of USDHC_VEND_SPEC_CD_POL from a register value. +#define BG_USDHC_VEND_SPEC_CD_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_CD_POL) >> BP_USDHC_VEND_SPEC_CD_POL) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_CD_POL. +#define BF_USDHC_VEND_SPEC_CD_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_CD_POL) & BM_USDHC_VEND_SPEC_CD_POL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CD_POL field to a new value. +#define BW_USDHC_VEND_SPEC_CD_POL(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_CD_POL) | BF_USDHC_VEND_SPEC_CD_POL(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field WP_POL[6] (RW) + * + * This bit only uses for debugging. Polarity of the WP pin: + * + * Values: + * 0 - WP pin is high active + * 1 - WP pin is low active + */ + +#define BP_USDHC_VEND_SPEC_WP_POL (6) //!< Bit position for USDHC_VEND_SPEC_WP_POL. +#define BM_USDHC_VEND_SPEC_WP_POL (0x00000040) //!< Bit mask for USDHC_VEND_SPEC_WP_POL. + +//! @brief Get value of USDHC_VEND_SPEC_WP_POL from a register value. +#define BG_USDHC_VEND_SPEC_WP_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_WP_POL) >> BP_USDHC_VEND_SPEC_WP_POL) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_WP_POL. +#define BF_USDHC_VEND_SPEC_WP_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_WP_POL) & BM_USDHC_VEND_SPEC_WP_POL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP_POL field to a new value. +#define BW_USDHC_VEND_SPEC_WP_POL(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_WP_POL) | BF_USDHC_VEND_SPEC_WP_POL(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field CLKONJ_IN_ABORT[7] (RW) + * + * This bit only uses for debugging. Force CLK output active when sending Abort command: + * + * Values: + * 0 - the CLK output is active when sending abort command while data is transmitting even if the internal + * FIFO is full(for read) or empty(for write) + * 1 - the CLK output is inactive when sending abort command while data is transmitting if the internal + * FIFO is full(for read) or empty(for write) + */ + +#define BP_USDHC_VEND_SPEC_CLKONJ_IN_ABORT (7) //!< Bit position for USDHC_VEND_SPEC_CLKONJ_IN_ABORT. +#define BM_USDHC_VEND_SPEC_CLKONJ_IN_ABORT (0x00000080) //!< Bit mask for USDHC_VEND_SPEC_CLKONJ_IN_ABORT. + +//! @brief Get value of USDHC_VEND_SPEC_CLKONJ_IN_ABORT from a register value. +#define BG_USDHC_VEND_SPEC_CLKONJ_IN_ABORT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_CLKONJ_IN_ABORT) >> BP_USDHC_VEND_SPEC_CLKONJ_IN_ABORT) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_CLKONJ_IN_ABORT. +#define BF_USDHC_VEND_SPEC_CLKONJ_IN_ABORT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_CLKONJ_IN_ABORT) & BM_USDHC_VEND_SPEC_CLKONJ_IN_ABORT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CLKONJ_IN_ABORT field to a new value. +#define BW_USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_CLKONJ_IN_ABORT) | BF_USDHC_VEND_SPEC_CLKONJ_IN_ABORT(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field FRC_SDCLK_ON[8] (RW) + * + * Force CLK output active: + * + * Values: + * 0 - CLK active or inactive is fully controlled by the hardware + * 1 - force CLK active + */ + +#define BP_USDHC_VEND_SPEC_FRC_SDCLK_ON (8) //!< Bit position for USDHC_VEND_SPEC_FRC_SDCLK_ON. +#define BM_USDHC_VEND_SPEC_FRC_SDCLK_ON (0x00000100) //!< Bit mask for USDHC_VEND_SPEC_FRC_SDCLK_ON. + +//! @brief Get value of USDHC_VEND_SPEC_FRC_SDCLK_ON from a register value. +#define BG_USDHC_VEND_SPEC_FRC_SDCLK_ON(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_FRC_SDCLK_ON) >> BP_USDHC_VEND_SPEC_FRC_SDCLK_ON) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_FRC_SDCLK_ON. +#define BF_USDHC_VEND_SPEC_FRC_SDCLK_ON(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_FRC_SDCLK_ON) & BM_USDHC_VEND_SPEC_FRC_SDCLK_ON) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the FRC_SDCLK_ON field to a new value. +#define BW_USDHC_VEND_SPEC_FRC_SDCLK_ON(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_FRC_SDCLK_ON) | BF_USDHC_VEND_SPEC_FRC_SDCLK_ON(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field AC12_ISNOT_ABORT[9] (RW) + * + * This bit only uses for debugging. Auto CMD12 is not a abort command: + * + * Values: + * 0 - Hardware treats the Auto CMD12 as abort command + * 1 - Hardwae doesn't treat the Auto CMD12 as abort comman + */ + +#define BP_USDHC_VEND_SPEC_AC12_ISNOT_ABORT (9) //!< Bit position for USDHC_VEND_SPEC_AC12_ISNOT_ABORT. +#define BM_USDHC_VEND_SPEC_AC12_ISNOT_ABORT (0x00000200) //!< Bit mask for USDHC_VEND_SPEC_AC12_ISNOT_ABORT. + +//! @brief Get value of USDHC_VEND_SPEC_AC12_ISNOT_ABORT from a register value. +#define BG_USDHC_VEND_SPEC_AC12_ISNOT_ABORT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_AC12_ISNOT_ABORT) >> BP_USDHC_VEND_SPEC_AC12_ISNOT_ABORT) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_AC12_ISNOT_ABORT. +#define BF_USDHC_VEND_SPEC_AC12_ISNOT_ABORT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_AC12_ISNOT_ABORT) & BM_USDHC_VEND_SPEC_AC12_ISNOT_ABORT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC12_ISNOT_ABORT field to a new value. +#define BW_USDHC_VEND_SPEC_AC12_ISNOT_ABORT(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_AC12_ISNOT_ABORT) | BF_USDHC_VEND_SPEC_AC12_ISNOT_ABORT(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field DDREN_ACT_ATONCE[10] (RW) + * + * This bit only uses for debugging. DDR_EN setting take active at once: + * + * Values: + * 0 - DDR_EN setting takes active only when the data and cmd line are idle. + * 1 - DDR_EN setting takes active at once no matter what the state of the data and cmd line are. + */ + +#define BP_USDHC_VEND_SPEC_DDREN_ACT_ATONCE (10) //!< Bit position for USDHC_VEND_SPEC_DDREN_ACT_ATONCE. +#define BM_USDHC_VEND_SPEC_DDREN_ACT_ATONCE (0x00000400) //!< Bit mask for USDHC_VEND_SPEC_DDREN_ACT_ATONCE. + +//! @brief Get value of USDHC_VEND_SPEC_DDREN_ACT_ATONCE from a register value. +#define BG_USDHC_VEND_SPEC_DDREN_ACT_ATONCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_DDREN_ACT_ATONCE) >> BP_USDHC_VEND_SPEC_DDREN_ACT_ATONCE) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_DDREN_ACT_ATONCE. +#define BF_USDHC_VEND_SPEC_DDREN_ACT_ATONCE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_DDREN_ACT_ATONCE) & BM_USDHC_VEND_SPEC_DDREN_ACT_ATONCE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DDREN_ACT_ATONCE field to a new value. +#define BW_USDHC_VEND_SPEC_DDREN_ACT_ATONCE(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_DDREN_ACT_ATONCE) | BF_USDHC_VEND_SPEC_DDREN_ACT_ATONCE(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field IPG_CLK_SOFT_EN[11] (RW) + * + * IPG_CLK software enable + * + * Values: + * 0 - gate off the IPG_CLK + * 1 - enable the IPG_CLK + */ + +#define BP_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN (11) //!< Bit position for USDHC_VEND_SPEC_IPG_CLK_SOFT_EN. +#define BM_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN (0x00000800) //!< Bit mask for USDHC_VEND_SPEC_IPG_CLK_SOFT_EN. + +//! @brief Get value of USDHC_VEND_SPEC_IPG_CLK_SOFT_EN from a register value. +#define BG_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN) >> BP_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_IPG_CLK_SOFT_EN. +#define BF_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN) & BM_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPG_CLK_SOFT_EN field to a new value. +#define BW_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN) | BF_USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field HCLK_SOFT_EN[12] (RW) + * + * Please note, hardware auto-enables the AHB clock when the internal DMA is enabled even if + * HCLK_SOFT_EN is 0. AHB clock software enable + * + * Values: + * 0 - gate off the AHB clock. + * 1 - enable the AHB clock. + */ + +#define BP_USDHC_VEND_SPEC_HCLK_SOFT_EN (12) //!< Bit position for USDHC_VEND_SPEC_HCLK_SOFT_EN. +#define BM_USDHC_VEND_SPEC_HCLK_SOFT_EN (0x00001000) //!< Bit mask for USDHC_VEND_SPEC_HCLK_SOFT_EN. + +//! @brief Get value of USDHC_VEND_SPEC_HCLK_SOFT_EN from a register value. +#define BG_USDHC_VEND_SPEC_HCLK_SOFT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_HCLK_SOFT_EN) >> BP_USDHC_VEND_SPEC_HCLK_SOFT_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_HCLK_SOFT_EN. +#define BF_USDHC_VEND_SPEC_HCLK_SOFT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_HCLK_SOFT_EN) & BM_USDHC_VEND_SPEC_HCLK_SOFT_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the HCLK_SOFT_EN field to a new value. +#define BW_USDHC_VEND_SPEC_HCLK_SOFT_EN(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_HCLK_SOFT_EN) | BF_USDHC_VEND_SPEC_HCLK_SOFT_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field IPG_PERCLK_SOFT_EN[13] (RW) + * + * ipg_perclk software enable + * + * Values: + * 0 - gate off the ipg_perclk + * 1 - enable the ipg_perclk + */ + +#define BP_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN (13) //!< Bit position for USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN. +#define BM_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN (0x00002000) //!< Bit mask for USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN. + +//! @brief Get value of USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN from a register value. +#define BG_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN) >> BP_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN. +#define BF_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN) & BM_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the IPG_PERCLK_SOFT_EN field to a new value. +#define BW_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN) | BF_USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field CARD_CLK_SOFT_EN[14] (ROO) + * + * card clock software enable + * + * Values: + * 0 - gate off the sd_clk + * 1 - enable the sd_clk + */ + +#define BP_USDHC_VEND_SPEC_CARD_CLK_SOFT_EN (14) //!< Bit position for USDHC_VEND_SPEC_CARD_CLK_SOFT_EN. +#define BM_USDHC_VEND_SPEC_CARD_CLK_SOFT_EN (0x00004000) //!< Bit mask for USDHC_VEND_SPEC_CARD_CLK_SOFT_EN. + +//! @brief Get value of USDHC_VEND_SPEC_CARD_CLK_SOFT_EN from a register value. +#define BG_USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_CARD_CLK_SOFT_EN) >> BP_USDHC_VEND_SPEC_CARD_CLK_SOFT_EN) + + +/* --- Register HW_USDHC_VEND_SPEC, field CRC_CHK_DIS[15] (RW) + * + * CRC check disable + * + * Values: + * 0 - check CRC16 for every read data packet and check CRC bits for every write data packet + * 1 - ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + */ + +#define BP_USDHC_VEND_SPEC_CRC_CHK_DIS (15) //!< Bit position for USDHC_VEND_SPEC_CRC_CHK_DIS. +#define BM_USDHC_VEND_SPEC_CRC_CHK_DIS (0x00008000) //!< Bit mask for USDHC_VEND_SPEC_CRC_CHK_DIS. + +//! @brief Get value of USDHC_VEND_SPEC_CRC_CHK_DIS from a register value. +#define BG_USDHC_VEND_SPEC_CRC_CHK_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_CRC_CHK_DIS) >> BP_USDHC_VEND_SPEC_CRC_CHK_DIS) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_CRC_CHK_DIS. +#define BF_USDHC_VEND_SPEC_CRC_CHK_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_CRC_CHK_DIS) & BM_USDHC_VEND_SPEC_CRC_CHK_DIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CRC_CHK_DIS field to a new value. +#define BW_USDHC_VEND_SPEC_CRC_CHK_DIS(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_CRC_CHK_DIS) | BF_USDHC_VEND_SPEC_CRC_CHK_DIS(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field INT_ST_VAL[23:16] (RO) + * + * Internal State Value Internal state value, reflecting the corresponding state value selected by + * Debug Select field. This field is read-only and write to this field does not have effect. + */ + +#define BP_USDHC_VEND_SPEC_INT_ST_VAL (16) //!< Bit position for USDHC_VEND_SPEC_INT_ST_VAL. +#define BM_USDHC_VEND_SPEC_INT_ST_VAL (0x00ff0000) //!< Bit mask for USDHC_VEND_SPEC_INT_ST_VAL. + +//! @brief Get value of USDHC_VEND_SPEC_INT_ST_VAL from a register value. +#define BG_USDHC_VEND_SPEC_INT_ST_VAL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_INT_ST_VAL) >> BP_USDHC_VEND_SPEC_INT_ST_VAL) + +/* --- Register HW_USDHC_VEND_SPEC, field DBG_SEL[27:24] (RW) + * + * Debug Select Select the internal sub-module to show its internal state value. + */ + +#define BP_USDHC_VEND_SPEC_DBG_SEL (24) //!< Bit position for USDHC_VEND_SPEC_DBG_SEL. +#define BM_USDHC_VEND_SPEC_DBG_SEL (0x0f000000) //!< Bit mask for USDHC_VEND_SPEC_DBG_SEL. + +//! @brief Get value of USDHC_VEND_SPEC_DBG_SEL from a register value. +#define BG_USDHC_VEND_SPEC_DBG_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_DBG_SEL) >> BP_USDHC_VEND_SPEC_DBG_SEL) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_DBG_SEL. +#define BF_USDHC_VEND_SPEC_DBG_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_DBG_SEL) & BM_USDHC_VEND_SPEC_DBG_SEL) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DBG_SEL field to a new value. +#define BW_USDHC_VEND_SPEC_DBG_SEL(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_DBG_SEL) | BF_USDHC_VEND_SPEC_DBG_SEL(v))) +#endif + +/* --- Register HW_USDHC_VEND_SPEC, field CMD_OE_PRE_EN[28] (RW) + * + * Only for debug. Control the assert point of CMD_OE signal + * + * Values: + * 0 - CMD_OE and CMD_O assert at the same time + * 1 - CMD_OE asserts one clock cycle before CMD_O + */ + +#define BP_USDHC_VEND_SPEC_CMD_OE_PRE_EN (28) //!< Bit position for USDHC_VEND_SPEC_CMD_OE_PRE_EN. +#define BM_USDHC_VEND_SPEC_CMD_OE_PRE_EN (0x10000000) //!< Bit mask for USDHC_VEND_SPEC_CMD_OE_PRE_EN. + +//! @brief Get value of USDHC_VEND_SPEC_CMD_OE_PRE_EN from a register value. +#define BG_USDHC_VEND_SPEC_CMD_OE_PRE_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_CMD_OE_PRE_EN) >> BP_USDHC_VEND_SPEC_CMD_OE_PRE_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_CMD_OE_PRE_EN. +#define BF_USDHC_VEND_SPEC_CMD_OE_PRE_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_CMD_OE_PRE_EN) & BM_USDHC_VEND_SPEC_CMD_OE_PRE_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CMD_OE_PRE_EN field to a new value. +#define BW_USDHC_VEND_SPEC_CMD_OE_PRE_EN(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_CMD_OE_PRE_EN) | BF_USDHC_VEND_SPEC_CMD_OE_PRE_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field AC12_RD_CHKBUSY_EN[29] (RW) + * + * Only for debug. Auto CMD12 to terminate multi-block read needs to check busy or not + * + * Values: + * 0 - Auto CMD12 to terminate multi-block read doesn't need to check busy + * 1 - Auto CMD12 to terminate multi-block read needs to check busy + */ + +#define BP_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN (29) //!< Bit position for USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN. +#define BM_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN (0x20000000) //!< Bit mask for USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN. + +//! @brief Get value of USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN from a register value. +#define BG_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN) >> BP_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN. +#define BF_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN) & BM_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AC12_RD_CHKBUSY_EN field to a new value. +#define BW_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN) | BF_USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC, field CARD_DET_IN_IDLE_ENJ[30] (RW) + * + * Only for debug. Card detection is only detected during data line idle. + * + * Values: + * 1b - + */ + +#define BP_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ (30) //!< Bit position for USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ. +#define BM_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ (0x40000000) //!< Bit mask for USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ. + +//! @brief Get value of USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ from a register value. +#define BG_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ) >> BP_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ) + +//! @brief Format value for bitfield USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ. +#define BF_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ) & BM_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CARD_DET_IN_IDLE_ENJ field to a new value. +#define BW_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ(x, v) (HW_USDHC_VEND_SPEC_WR(x, (HW_USDHC_VEND_SPEC_RD(x) & ~BM_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ) | BF_USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ(v))) +#endif + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_MMC_BOOT - MMC Boot Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_MMC_BOOT - MMC Boot Register (RW) + * + * Reset value: 0x00000000 + * + * This register contains the MMC Fast Boot control register. + */ +typedef union _hw_usdhc_mmc_boot +{ + reg32_t U; + struct _hw_usdhc_mmc_boot_bitfields + { + unsigned DTOCV_ACK : 4; //!< [3:0] Boot ACK time out counter value. + unsigned BOOT_ACK : 1; //!< [4] Boot ack mode select 0: no ack 1: ack + unsigned BOOT_MODE : 1; //!< [5] Boot mode select 0: normal boot 1: alternative boot + unsigned BOOT_EN : 1; //!< [6] Boot mode enable 0: fast boot disable 1: fast boot enable + unsigned AUTO_SABG_EN : 1; //!< [7] When boot, enable auto stop at block gap function. + unsigned DISABLE_TIME_OUT : 1; //!< [8] Please note, when this bit is set, there is no timeout check no matter boot_en is set or not. + unsigned RESERVED0 : 7; //!< [15:9] Reserved + unsigned BOOT_BLK_CNT : 16; //!< [31:16] The value defines the Stop At Block Gap value of automatic mode. + } B; +} hw_usdhc_mmc_boot_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_MMC_BOOT register + */ +#define HW_USDHC_MMC_BOOT_ADDR(x) (REGS_USDHC_BASE(x) + 0xc4) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_MMC_BOOT(x) (*(volatile hw_usdhc_mmc_boot_t *) HW_USDHC_MMC_BOOT_ADDR(x)) +#define HW_USDHC_MMC_BOOT_RD(x) (HW_USDHC_MMC_BOOT(x).U) +#define HW_USDHC_MMC_BOOT_WR(x, v) (HW_USDHC_MMC_BOOT(x).U = (v)) +#define HW_USDHC_MMC_BOOT_SET(x, v) (HW_USDHC_MMC_BOOT_WR(x, HW_USDHC_MMC_BOOT_RD(x) | (v))) +#define HW_USDHC_MMC_BOOT_CLR(x, v) (HW_USDHC_MMC_BOOT_WR(x, HW_USDHC_MMC_BOOT_RD(x) & ~(v))) +#define HW_USDHC_MMC_BOOT_TOG(x, v) (HW_USDHC_MMC_BOOT_WR(x, HW_USDHC_MMC_BOOT_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_MMC_BOOT bitfields + */ + +/* --- Register HW_USDHC_MMC_BOOT, field DTOCV_ACK[3:0] (RW) + * + * Boot ACK time out counter value. + * + * Values: + * 0000 - SDCLK x 2^13 + * 0001 - SDCLK x 2^14 + * 0010 - SDCLK x 2^15 + * 0011 - SDCLK x 2^16 + * 0100 - SDCLK x 2^17 + * 0101 - SDCLK x 2^18 + * 0110 - SDCLK x 2^19 + * 0111 - SDCLK x 2^20 + * 1110 - SDCLK x 2^27 + * 1111 - SDCLK x 2^28 + */ + +#define BP_USDHC_MMC_BOOT_DTOCV_ACK (0) //!< Bit position for USDHC_MMC_BOOT_DTOCV_ACK. +#define BM_USDHC_MMC_BOOT_DTOCV_ACK (0x0000000f) //!< Bit mask for USDHC_MMC_BOOT_DTOCV_ACK. + +//! @brief Get value of USDHC_MMC_BOOT_DTOCV_ACK from a register value. +#define BG_USDHC_MMC_BOOT_DTOCV_ACK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MMC_BOOT_DTOCV_ACK) >> BP_USDHC_MMC_BOOT_DTOCV_ACK) + +//! @brief Format value for bitfield USDHC_MMC_BOOT_DTOCV_ACK. +#define BF_USDHC_MMC_BOOT_DTOCV_ACK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MMC_BOOT_DTOCV_ACK) & BM_USDHC_MMC_BOOT_DTOCV_ACK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DTOCV_ACK field to a new value. +#define BW_USDHC_MMC_BOOT_DTOCV_ACK(x, v) (HW_USDHC_MMC_BOOT_WR(x, (HW_USDHC_MMC_BOOT_RD(x) & ~BM_USDHC_MMC_BOOT_DTOCV_ACK) | BF_USDHC_MMC_BOOT_DTOCV_ACK(v))) +#endif + + +/* --- Register HW_USDHC_MMC_BOOT, field BOOT_ACK[4] (RW) + * + * Boot ack mode select 0: no ack 1: ack + */ + +#define BP_USDHC_MMC_BOOT_BOOT_ACK (4) //!< Bit position for USDHC_MMC_BOOT_BOOT_ACK. +#define BM_USDHC_MMC_BOOT_BOOT_ACK (0x00000010) //!< Bit mask for USDHC_MMC_BOOT_BOOT_ACK. + +//! @brief Get value of USDHC_MMC_BOOT_BOOT_ACK from a register value. +#define BG_USDHC_MMC_BOOT_BOOT_ACK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MMC_BOOT_BOOT_ACK) >> BP_USDHC_MMC_BOOT_BOOT_ACK) + +//! @brief Format value for bitfield USDHC_MMC_BOOT_BOOT_ACK. +#define BF_USDHC_MMC_BOOT_BOOT_ACK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MMC_BOOT_BOOT_ACK) & BM_USDHC_MMC_BOOT_BOOT_ACK) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BOOT_ACK field to a new value. +#define BW_USDHC_MMC_BOOT_BOOT_ACK(x, v) (HW_USDHC_MMC_BOOT_WR(x, (HW_USDHC_MMC_BOOT_RD(x) & ~BM_USDHC_MMC_BOOT_BOOT_ACK) | BF_USDHC_MMC_BOOT_BOOT_ACK(v))) +#endif + +/* --- Register HW_USDHC_MMC_BOOT, field BOOT_MODE[5] (RW) + * + * Boot mode select 0: normal boot 1: alternative boot + */ + +#define BP_USDHC_MMC_BOOT_BOOT_MODE (5) //!< Bit position for USDHC_MMC_BOOT_BOOT_MODE. +#define BM_USDHC_MMC_BOOT_BOOT_MODE (0x00000020) //!< Bit mask for USDHC_MMC_BOOT_BOOT_MODE. + +//! @brief Get value of USDHC_MMC_BOOT_BOOT_MODE from a register value. +#define BG_USDHC_MMC_BOOT_BOOT_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MMC_BOOT_BOOT_MODE) >> BP_USDHC_MMC_BOOT_BOOT_MODE) + +//! @brief Format value for bitfield USDHC_MMC_BOOT_BOOT_MODE. +#define BF_USDHC_MMC_BOOT_BOOT_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MMC_BOOT_BOOT_MODE) & BM_USDHC_MMC_BOOT_BOOT_MODE) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BOOT_MODE field to a new value. +#define BW_USDHC_MMC_BOOT_BOOT_MODE(x, v) (HW_USDHC_MMC_BOOT_WR(x, (HW_USDHC_MMC_BOOT_RD(x) & ~BM_USDHC_MMC_BOOT_BOOT_MODE) | BF_USDHC_MMC_BOOT_BOOT_MODE(v))) +#endif + +/* --- Register HW_USDHC_MMC_BOOT, field BOOT_EN[6] (RW) + * + * Boot mode enable 0: fast boot disable 1: fast boot enable + */ + +#define BP_USDHC_MMC_BOOT_BOOT_EN (6) //!< Bit position for USDHC_MMC_BOOT_BOOT_EN. +#define BM_USDHC_MMC_BOOT_BOOT_EN (0x00000040) //!< Bit mask for USDHC_MMC_BOOT_BOOT_EN. + +//! @brief Get value of USDHC_MMC_BOOT_BOOT_EN from a register value. +#define BG_USDHC_MMC_BOOT_BOOT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MMC_BOOT_BOOT_EN) >> BP_USDHC_MMC_BOOT_BOOT_EN) + +//! @brief Format value for bitfield USDHC_MMC_BOOT_BOOT_EN. +#define BF_USDHC_MMC_BOOT_BOOT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MMC_BOOT_BOOT_EN) & BM_USDHC_MMC_BOOT_BOOT_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BOOT_EN field to a new value. +#define BW_USDHC_MMC_BOOT_BOOT_EN(x, v) (HW_USDHC_MMC_BOOT_WR(x, (HW_USDHC_MMC_BOOT_RD(x) & ~BM_USDHC_MMC_BOOT_BOOT_EN) | BF_USDHC_MMC_BOOT_BOOT_EN(v))) +#endif + +/* --- Register HW_USDHC_MMC_BOOT, field AUTO_SABG_EN[7] (RW) + * + * When boot, enable auto stop at block gap function. This function will be triggered, and host will + * stop at block gap when received card block cnt is equal to (BLK_CNT - BOOT_BLK_CNT). + */ + +#define BP_USDHC_MMC_BOOT_AUTO_SABG_EN (7) //!< Bit position for USDHC_MMC_BOOT_AUTO_SABG_EN. +#define BM_USDHC_MMC_BOOT_AUTO_SABG_EN (0x00000080) //!< Bit mask for USDHC_MMC_BOOT_AUTO_SABG_EN. + +//! @brief Get value of USDHC_MMC_BOOT_AUTO_SABG_EN from a register value. +#define BG_USDHC_MMC_BOOT_AUTO_SABG_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MMC_BOOT_AUTO_SABG_EN) >> BP_USDHC_MMC_BOOT_AUTO_SABG_EN) + +//! @brief Format value for bitfield USDHC_MMC_BOOT_AUTO_SABG_EN. +#define BF_USDHC_MMC_BOOT_AUTO_SABG_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MMC_BOOT_AUTO_SABG_EN) & BM_USDHC_MMC_BOOT_AUTO_SABG_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the AUTO_SABG_EN field to a new value. +#define BW_USDHC_MMC_BOOT_AUTO_SABG_EN(x, v) (HW_USDHC_MMC_BOOT_WR(x, (HW_USDHC_MMC_BOOT_RD(x) & ~BM_USDHC_MMC_BOOT_AUTO_SABG_EN) | BF_USDHC_MMC_BOOT_AUTO_SABG_EN(v))) +#endif + +/* --- Register HW_USDHC_MMC_BOOT, field DISABLE_TIME_OUT[8] (RW) + * + * Please note, when this bit is set, there is no timeout check no matter boot_en is set or not. + * Disable time out. + * + * Values: + * 0 - enable time out + * 1 - Disable time out + */ + +#define BP_USDHC_MMC_BOOT_DISABLE_TIME_OUT (8) //!< Bit position for USDHC_MMC_BOOT_DISABLE_TIME_OUT. +#define BM_USDHC_MMC_BOOT_DISABLE_TIME_OUT (0x00000100) //!< Bit mask for USDHC_MMC_BOOT_DISABLE_TIME_OUT. + +//! @brief Get value of USDHC_MMC_BOOT_DISABLE_TIME_OUT from a register value. +#define BG_USDHC_MMC_BOOT_DISABLE_TIME_OUT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MMC_BOOT_DISABLE_TIME_OUT) >> BP_USDHC_MMC_BOOT_DISABLE_TIME_OUT) + +//! @brief Format value for bitfield USDHC_MMC_BOOT_DISABLE_TIME_OUT. +#define BF_USDHC_MMC_BOOT_DISABLE_TIME_OUT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MMC_BOOT_DISABLE_TIME_OUT) & BM_USDHC_MMC_BOOT_DISABLE_TIME_OUT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the DISABLE_TIME_OUT field to a new value. +#define BW_USDHC_MMC_BOOT_DISABLE_TIME_OUT(x, v) (HW_USDHC_MMC_BOOT_WR(x, (HW_USDHC_MMC_BOOT_RD(x) & ~BM_USDHC_MMC_BOOT_DISABLE_TIME_OUT) | BF_USDHC_MMC_BOOT_DISABLE_TIME_OUT(v))) +#endif + + +/* --- Register HW_USDHC_MMC_BOOT, field BOOT_BLK_CNT[31:16] (RW) + * + * The value defines the Stop At Block Gap value of automatic mode. When received card block cnt is + * equal to (BLK_CNT - BOOT_BLK_CNT) and AUTO_SABG_EN is 1, then Stop At Block Gap. Here, BLK_CNT is + * defined in the Block Atrributes Register, bit31-16 of 0x04. + */ + +#define BP_USDHC_MMC_BOOT_BOOT_BLK_CNT (16) //!< Bit position for USDHC_MMC_BOOT_BOOT_BLK_CNT. +#define BM_USDHC_MMC_BOOT_BOOT_BLK_CNT (0xffff0000) //!< Bit mask for USDHC_MMC_BOOT_BOOT_BLK_CNT. + +//! @brief Get value of USDHC_MMC_BOOT_BOOT_BLK_CNT from a register value. +#define BG_USDHC_MMC_BOOT_BOOT_BLK_CNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_MMC_BOOT_BOOT_BLK_CNT) >> BP_USDHC_MMC_BOOT_BOOT_BLK_CNT) + +//! @brief Format value for bitfield USDHC_MMC_BOOT_BOOT_BLK_CNT. +#define BF_USDHC_MMC_BOOT_BOOT_BLK_CNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_MMC_BOOT_BOOT_BLK_CNT) & BM_USDHC_MMC_BOOT_BOOT_BLK_CNT) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the BOOT_BLK_CNT field to a new value. +#define BW_USDHC_MMC_BOOT_BOOT_BLK_CNT(x, v) (HW_USDHC_MMC_BOOT_WR(x, (HW_USDHC_MMC_BOOT_RD(x) & ~BM_USDHC_MMC_BOOT_BOOT_BLK_CNT) | BF_USDHC_MMC_BOOT_BOOT_BLK_CNT(v))) +#endif + +//------------------------------------------------------------------------------------------- +// HW_USDHC_VEND_SPEC2 - Vendor Specific 2 Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_VEND_SPEC2 - Vendor Specific 2 Register (RW) + * + * Reset value: 0x00000006 + * + * This register contains the vendor specific control 2 register. + */ +typedef union _hw_usdhc_vend_spec2 +{ + reg32_t U; + struct _hw_usdhc_vend_spec2_bitfields + { + unsigned SDR104_TIMING_DIS : 1; //!< [0] Timeout counter test. + unsigned SDR104_OE_DIS : 1; //!< [1] CMD_OE/DAT_OE logic generation test. + unsigned SDR104_NSD_DIS : 1; //!< [2] Interrupt window after abort command is sent. + unsigned CARD_INT_D3_TEST : 1; //!< [3] Card interrupt detection test. + unsigned TUNING_8BIT_EN : 1; //!< [4] Enable the auto tuning circuit to check the DAT[7:0]. + unsigned TUNING_1BIT_EN : 1; //!< [5] Enable the auto tuning circuit to check the DAT0 only. + unsigned TUNING_CMD_EN : 1; //!< [6] Enable the auto tuning circuit to check the CMD line. + unsigned CARD_INT_AUTO_CLR_DIS : 1; //!< [7] Disable the feature to clear the Card interrupt status bit when Card Interrupt status enable bit is cleared. + unsigned RESERVED0 : 24; //!< [31:8] Reserved + } B; +} hw_usdhc_vend_spec2_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_VEND_SPEC2 register + */ +#define HW_USDHC_VEND_SPEC2_ADDR(x) (REGS_USDHC_BASE(x) + 0xc8) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_VEND_SPEC2(x) (*(volatile hw_usdhc_vend_spec2_t *) HW_USDHC_VEND_SPEC2_ADDR(x)) +#define HW_USDHC_VEND_SPEC2_RD(x) (HW_USDHC_VEND_SPEC2(x).U) +#define HW_USDHC_VEND_SPEC2_WR(x, v) (HW_USDHC_VEND_SPEC2(x).U = (v)) +#define HW_USDHC_VEND_SPEC2_SET(x, v) (HW_USDHC_VEND_SPEC2_WR(x, HW_USDHC_VEND_SPEC2_RD(x) | (v))) +#define HW_USDHC_VEND_SPEC2_CLR(x, v) (HW_USDHC_VEND_SPEC2_WR(x, HW_USDHC_VEND_SPEC2_RD(x) & ~(v))) +#define HW_USDHC_VEND_SPEC2_TOG(x, v) (HW_USDHC_VEND_SPEC2_WR(x, HW_USDHC_VEND_SPEC2_RD(x) ^ (v))) +#endif + +/* + * constants & macros for individual USDHC_VEND_SPEC2 bitfields + */ + +/* --- Register HW_USDHC_VEND_SPEC2, field SDR104_TIMING_DIS[0] (RW) + * + * Timeout counter test. This bit only uses for debugging. + * + * Values: + * 0 - The timeout counter for Ncr changes to 80, Ncrc changes to 21. + * 1 - The timeout counter for Ncr changes to 72, Ncrc changes to 15. + */ + +#define BP_USDHC_VEND_SPEC2_SDR104_TIMING_DIS (0) //!< Bit position for USDHC_VEND_SPEC2_SDR104_TIMING_DIS. +#define BM_USDHC_VEND_SPEC2_SDR104_TIMING_DIS (0x00000001) //!< Bit mask for USDHC_VEND_SPEC2_SDR104_TIMING_DIS. + +//! @brief Get value of USDHC_VEND_SPEC2_SDR104_TIMING_DIS from a register value. +#define BG_USDHC_VEND_SPEC2_SDR104_TIMING_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC2_SDR104_TIMING_DIS) >> BP_USDHC_VEND_SPEC2_SDR104_TIMING_DIS) + +//! @brief Format value for bitfield USDHC_VEND_SPEC2_SDR104_TIMING_DIS. +#define BF_USDHC_VEND_SPEC2_SDR104_TIMING_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC2_SDR104_TIMING_DIS) & BM_USDHC_VEND_SPEC2_SDR104_TIMING_DIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SDR104_TIMING_DIS field to a new value. +#define BW_USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x, v) (HW_USDHC_VEND_SPEC2_WR(x, (HW_USDHC_VEND_SPEC2_RD(x) & ~BM_USDHC_VEND_SPEC2_SDR104_TIMING_DIS) | BF_USDHC_VEND_SPEC2_SDR104_TIMING_DIS(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC2, field SDR104_OE_DIS[1] (RW) + * + * CMD_OE/DAT_OE logic generation test. This bit only uses for debugging. + * + * Values: + * 0 - Drive the CMD_OE/DAT_OE for one more clock cycle after the end bit. + * 1 - Stop to drive the CMD_OE/DAT_OE at once after driving the end bit. + */ + +#define BP_USDHC_VEND_SPEC2_SDR104_OE_DIS (1) //!< Bit position for USDHC_VEND_SPEC2_SDR104_OE_DIS. +#define BM_USDHC_VEND_SPEC2_SDR104_OE_DIS (0x00000002) //!< Bit mask for USDHC_VEND_SPEC2_SDR104_OE_DIS. + +//! @brief Get value of USDHC_VEND_SPEC2_SDR104_OE_DIS from a register value. +#define BG_USDHC_VEND_SPEC2_SDR104_OE_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC2_SDR104_OE_DIS) >> BP_USDHC_VEND_SPEC2_SDR104_OE_DIS) + +//! @brief Format value for bitfield USDHC_VEND_SPEC2_SDR104_OE_DIS. +#define BF_USDHC_VEND_SPEC2_SDR104_OE_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC2_SDR104_OE_DIS) & BM_USDHC_VEND_SPEC2_SDR104_OE_DIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SDR104_OE_DIS field to a new value. +#define BW_USDHC_VEND_SPEC2_SDR104_OE_DIS(x, v) (HW_USDHC_VEND_SPEC2_WR(x, (HW_USDHC_VEND_SPEC2_RD(x) & ~BM_USDHC_VEND_SPEC2_SDR104_OE_DIS) | BF_USDHC_VEND_SPEC2_SDR104_OE_DIS(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC2, field SDR104_NSD_DIS[2] (RW) + * + * Interrupt window after abort command is sent. This bit only uses for debugging. + * + * Values: + * 0 - Enable the interrupt window 9 cycles later after the end of the I/O abort command(or CMD12) is sent. + * 1 - Enable the interrupt window 5 cycles later after the end of the I/O abort command(or CMD12) is sent. + */ + +#define BP_USDHC_VEND_SPEC2_SDR104_NSD_DIS (2) //!< Bit position for USDHC_VEND_SPEC2_SDR104_NSD_DIS. +#define BM_USDHC_VEND_SPEC2_SDR104_NSD_DIS (0x00000004) //!< Bit mask for USDHC_VEND_SPEC2_SDR104_NSD_DIS. + +//! @brief Get value of USDHC_VEND_SPEC2_SDR104_NSD_DIS from a register value. +#define BG_USDHC_VEND_SPEC2_SDR104_NSD_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC2_SDR104_NSD_DIS) >> BP_USDHC_VEND_SPEC2_SDR104_NSD_DIS) + +//! @brief Format value for bitfield USDHC_VEND_SPEC2_SDR104_NSD_DIS. +#define BF_USDHC_VEND_SPEC2_SDR104_NSD_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC2_SDR104_NSD_DIS) & BM_USDHC_VEND_SPEC2_SDR104_NSD_DIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SDR104_NSD_DIS field to a new value. +#define BW_USDHC_VEND_SPEC2_SDR104_NSD_DIS(x, v) (HW_USDHC_VEND_SPEC2_WR(x, (HW_USDHC_VEND_SPEC2_RD(x) & ~BM_USDHC_VEND_SPEC2_SDR104_NSD_DIS) | BF_USDHC_VEND_SPEC2_SDR104_NSD_DIS(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC2, field CARD_INT_D3_TEST[3] (RW) + * + * Card interrupt detection test. This bit only uses for debugging. + * + * Values: + * 0 - Check the card interrupt only when DAT[3] is high. + * 1 - Check the card interrupt by ignoring the status of DAT[3]. + */ + +#define BP_USDHC_VEND_SPEC2_CARD_INT_D3_TEST (3) //!< Bit position for USDHC_VEND_SPEC2_CARD_INT_D3_TEST. +#define BM_USDHC_VEND_SPEC2_CARD_INT_D3_TEST (0x00000008) //!< Bit mask for USDHC_VEND_SPEC2_CARD_INT_D3_TEST. + +//! @brief Get value of USDHC_VEND_SPEC2_CARD_INT_D3_TEST from a register value. +#define BG_USDHC_VEND_SPEC2_CARD_INT_D3_TEST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC2_CARD_INT_D3_TEST) >> BP_USDHC_VEND_SPEC2_CARD_INT_D3_TEST) + +//! @brief Format value for bitfield USDHC_VEND_SPEC2_CARD_INT_D3_TEST. +#define BF_USDHC_VEND_SPEC2_CARD_INT_D3_TEST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC2_CARD_INT_D3_TEST) & BM_USDHC_VEND_SPEC2_CARD_INT_D3_TEST) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CARD_INT_D3_TEST field to a new value. +#define BW_USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x, v) (HW_USDHC_VEND_SPEC2_WR(x, (HW_USDHC_VEND_SPEC2_RD(x) & ~BM_USDHC_VEND_SPEC2_CARD_INT_D3_TEST) | BF_USDHC_VEND_SPEC2_CARD_INT_D3_TEST(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC2, field TUNING_8BIT_EN[4] (RW) + * + * Enable the auto tuning circuit to check the DAT[7:0]. It's used with the TUNING_1bit_EN together. + * + * Values: + * 00 - Tuning circuit only checks the DAT[3:0]. + * 01 - Tuning circuit only checks the DAT[0]. + * 10 - Tuning circuit checks the whole DAT[7:0]. + * 11 - Invalid. + */ + +#define BP_USDHC_VEND_SPEC2_TUNING_8BIT_EN (4) //!< Bit position for USDHC_VEND_SPEC2_TUNING_8BIT_EN. +#define BM_USDHC_VEND_SPEC2_TUNING_8BIT_EN (0x00000010) //!< Bit mask for USDHC_VEND_SPEC2_TUNING_8BIT_EN. + +//! @brief Get value of USDHC_VEND_SPEC2_TUNING_8BIT_EN from a register value. +#define BG_USDHC_VEND_SPEC2_TUNING_8BIT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC2_TUNING_8BIT_EN) >> BP_USDHC_VEND_SPEC2_TUNING_8BIT_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC2_TUNING_8BIT_EN. +#define BF_USDHC_VEND_SPEC2_TUNING_8BIT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC2_TUNING_8BIT_EN) & BM_USDHC_VEND_SPEC2_TUNING_8BIT_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TUNING_8BIT_EN field to a new value. +#define BW_USDHC_VEND_SPEC2_TUNING_8BIT_EN(x, v) (HW_USDHC_VEND_SPEC2_WR(x, (HW_USDHC_VEND_SPEC2_RD(x) & ~BM_USDHC_VEND_SPEC2_TUNING_8BIT_EN) | BF_USDHC_VEND_SPEC2_TUNING_8BIT_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC2, field TUNING_1BIT_EN[5] (RW) + * + * Enable the auto tuning circuit to check the DAT0 only. It's used with the TUNING_8bit_EN + * together. + */ + +#define BP_USDHC_VEND_SPEC2_TUNING_1BIT_EN (5) //!< Bit position for USDHC_VEND_SPEC2_TUNING_1BIT_EN. +#define BM_USDHC_VEND_SPEC2_TUNING_1BIT_EN (0x00000020) //!< Bit mask for USDHC_VEND_SPEC2_TUNING_1BIT_EN. + +//! @brief Get value of USDHC_VEND_SPEC2_TUNING_1BIT_EN from a register value. +#define BG_USDHC_VEND_SPEC2_TUNING_1BIT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC2_TUNING_1BIT_EN) >> BP_USDHC_VEND_SPEC2_TUNING_1BIT_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC2_TUNING_1BIT_EN. +#define BF_USDHC_VEND_SPEC2_TUNING_1BIT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC2_TUNING_1BIT_EN) & BM_USDHC_VEND_SPEC2_TUNING_1BIT_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TUNING_1BIT_EN field to a new value. +#define BW_USDHC_VEND_SPEC2_TUNING_1BIT_EN(x, v) (HW_USDHC_VEND_SPEC2_WR(x, (HW_USDHC_VEND_SPEC2_RD(x) & ~BM_USDHC_VEND_SPEC2_TUNING_1BIT_EN) | BF_USDHC_VEND_SPEC2_TUNING_1BIT_EN(v))) +#endif + +/* --- Register HW_USDHC_VEND_SPEC2, field TUNING_CMD_EN[6] (RW) + * + * Enable the auto tuning circuit to check the CMD line. + * + * Values: + * 0 - Auto tuning circuit doesn't check the CMD line. + * 1 - Auto tuning circuit checks the CMD line. + */ + +#define BP_USDHC_VEND_SPEC2_TUNING_CMD_EN (6) //!< Bit position for USDHC_VEND_SPEC2_TUNING_CMD_EN. +#define BM_USDHC_VEND_SPEC2_TUNING_CMD_EN (0x00000040) //!< Bit mask for USDHC_VEND_SPEC2_TUNING_CMD_EN. + +//! @brief Get value of USDHC_VEND_SPEC2_TUNING_CMD_EN from a register value. +#define BG_USDHC_VEND_SPEC2_TUNING_CMD_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC2_TUNING_CMD_EN) >> BP_USDHC_VEND_SPEC2_TUNING_CMD_EN) + +//! @brief Format value for bitfield USDHC_VEND_SPEC2_TUNING_CMD_EN. +#define BF_USDHC_VEND_SPEC2_TUNING_CMD_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC2_TUNING_CMD_EN) & BM_USDHC_VEND_SPEC2_TUNING_CMD_EN) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TUNING_CMD_EN field to a new value. +#define BW_USDHC_VEND_SPEC2_TUNING_CMD_EN(x, v) (HW_USDHC_VEND_SPEC2_WR(x, (HW_USDHC_VEND_SPEC2_RD(x) & ~BM_USDHC_VEND_SPEC2_TUNING_CMD_EN) | BF_USDHC_VEND_SPEC2_TUNING_CMD_EN(v))) +#endif + + +/* --- Register HW_USDHC_VEND_SPEC2, field CARD_INT_AUTO_CLR_DIS[7] (RW) + * + * Disable the feature to clear the Card interrupt status bit when Card Interrupt status enable bit + * is cleared. This bit only uses for debugging. + * + * Values: + * 0 - Card interrupt status bit(CINT) can be cleared when Card Interrupt status enable bit is 0. + * 1 - Card interrupt status bit(CINT) can only be cleared by written-1 to CINT bit. + */ + +#define BP_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS (7) //!< Bit position for USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS. +#define BM_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS (0x00000080) //!< Bit mask for USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS. + +//! @brief Get value of USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS from a register value. +#define BG_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS) >> BP_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS) + +//! @brief Format value for bitfield USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS. +#define BF_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS) & BM_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the CARD_INT_AUTO_CLR_DIS field to a new value. +#define BW_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x, v) (HW_USDHC_VEND_SPEC2_WR(x, (HW_USDHC_VEND_SPEC2_RD(x) & ~BM_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS) | BF_USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(v))) +#endif + + +//------------------------------------------------------------------------------------------- +// HW_USDHC_HOST_CTRL_VER - Host Controller Version +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_USDHC_HOST_CTRL_VER - Host Controller Version (RO) + * + * Reset value: 0x00000003 + * + * This register contains the vendor Host Controller version information. All bits are read only and + * will read the same as the power-reset value. + */ +typedef union _hw_usdhc_host_ctrl_ver +{ + reg32_t U; + struct _hw_usdhc_host_ctrl_ver_bitfields + { + unsigned SVN : 8; //!< [7:0] Specification Version Number: These status bits indicate the Host Controller Specification Version. + unsigned VVN : 8; //!< [15:8] Vendor Version Number: These status bits are reserved for the vendor version number. + unsigned RESERVED0 : 16; //!< [31:16] Reserved + } B; +} hw_usdhc_host_ctrl_ver_t; +#endif + +/* + * constants & macros for entire multi-block USDHC_HOST_CTRL_VER register + */ +#define HW_USDHC_HOST_CTRL_VER_ADDR(x) (REGS_USDHC_BASE(x) + 0xfc) + +#ifndef __LANGUAGE_ASM__ +#define HW_USDHC_HOST_CTRL_VER(x) (*(volatile hw_usdhc_host_ctrl_ver_t *) HW_USDHC_HOST_CTRL_VER_ADDR(x)) +#define HW_USDHC_HOST_CTRL_VER_RD(x) (HW_USDHC_HOST_CTRL_VER(x).U) +#endif + +/* + * constants & macros for individual USDHC_HOST_CTRL_VER bitfields + */ + +/* --- Register HW_USDHC_HOST_CTRL_VER, field SVN[7:0] (RO) + * + * Specification Version Number: These status bits indicate the Host Controller Specification + * Version. 00 SD Host Specification Version 1.0 03 SD Host Specification Version 3.0, supports Test + * Event Register and ADMA. All others) Reserved + */ + +#define BP_USDHC_HOST_CTRL_VER_SVN (0) //!< Bit position for USDHC_HOST_CTRL_VER_SVN. +#define BM_USDHC_HOST_CTRL_VER_SVN (0x000000ff) //!< Bit mask for USDHC_HOST_CTRL_VER_SVN. + +//! @brief Get value of USDHC_HOST_CTRL_VER_SVN from a register value. +#define BG_USDHC_HOST_CTRL_VER_SVN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_VER_SVN) >> BP_USDHC_HOST_CTRL_VER_SVN) + +/* --- Register HW_USDHC_HOST_CTRL_VER, field VVN[15:8] (RO) + * + * Vendor Version Number: These status bits are reserved for the vendor version number. The Host + * Driver shall not use this status. 01 Freescale uSDHC Version 1.1 others) Reserved + */ + +#define BP_USDHC_HOST_CTRL_VER_VVN (8) //!< Bit position for USDHC_HOST_CTRL_VER_VVN. +#define BM_USDHC_HOST_CTRL_VER_VVN (0x0000ff00) //!< Bit mask for USDHC_HOST_CTRL_VER_VVN. + +//! @brief Get value of USDHC_HOST_CTRL_VER_VVN from a register value. +#define BG_USDHC_HOST_CTRL_VER_VVN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_USDHC_HOST_CTRL_VER_VVN) >> BP_USDHC_HOST_CTRL_VER_VVN) + + +/*! + * @brief All USDHC module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_usdhc +{ + volatile hw_usdhc_ds_addr_t DS_ADDR; //!< DMA System Address + volatile hw_usdhc_blk_att_t BLK_ATT; //!< Block Attributes + volatile hw_usdhc_cmd_arg_t CMD_ARG; //!< Command Argument + volatile hw_usdhc_cmd_xfr_typ_t CMD_XFR_TYP; //!< Command Transfer Type + volatile hw_usdhc_cmd_rsp0_t CMD_RSP0; //!< Command Response0 + volatile hw_usdhc_cmd_rsp1_t CMD_RSP1; //!< Command Response1 + volatile hw_usdhc_cmd_rsp2_t CMD_RSP2; //!< Command Response2 + volatile hw_usdhc_cmd_rsp3_t CMD_RSP3; //!< Command Response3 + volatile hw_usdhc_data_buff_acc_port_t DATA_BUFF_ACC_PORT; //!< Data Buffer Access Port + volatile hw_usdhc_pres_state_t PRES_STATE; //!< Present State + volatile hw_usdhc_prot_ctrl_t PROT_CTRL; //!< Protocol Control + volatile hw_usdhc_sys_ctrl_t SYS_CTRL; //!< System Control + volatile hw_usdhc_int_status_t INT_STATUS; //!< Interrupt Status + volatile hw_usdhc_int_status_en_t INT_STATUS_EN; //!< Interrupt Status Enable + volatile hw_usdhc_int_signal_en_t INT_SIGNAL_EN; //!< Interrupt Signal Enable + volatile hw_usdhc_autocmd12_err_status_t AUTOCMD12_ERR_STATUS; //!< Auto CMD12 Error Status + volatile hw_usdhc_host_ctrl_cap_t HOST_CTRL_CAP; //!< Host Controller Capabilities + volatile hw_usdhc_wtmk_lvl_t WTMK_LVL; //!< Watermark Level + volatile hw_usdhc_mix_ctrl_t MIX_CTRL; //!< Mixer Control + reg32_t _reserved0; + volatile hw_usdhc_force_event_t FORCE_EVENT; //!< Force Event + volatile hw_usdhc_adma_err_status_t ADMA_ERR_STATUS; //!< ADMA Error Status Register + volatile hw_usdhc_adma_sys_addr_t ADMA_SYS_ADDR; //!< ADMA System Address + reg32_t _reserved1; + volatile hw_usdhc_dll_ctrl_t DLL_CTRL; //!< DLL (Delay Line) Control + volatile hw_usdhc_dll_status_t DLL_STATUS; //!< DLL Status + volatile hw_usdhc_clk_tune_ctrl_status_t CLK_TUNE_CTRL_STATUS; //!< CLK Tuning Control and Status + reg32_t _reserved2[21]; + volatile hw_usdhc_vend_spec_t VEND_SPEC; //!< Vendor Specific Register + volatile hw_usdhc_mmc_boot_t MMC_BOOT; //!< MMC Boot Register + volatile hw_usdhc_vend_spec2_t VEND_SPEC2; //!< Vendor Specific 2 Register + reg32_t _reserved3[12]; + volatile hw_usdhc_host_ctrl_ver_t HOST_CTRL_VER; //!< Host Controller Version +} hw_usdhc_t; +#pragma pack() + +//! @brief Macro to access all USDHC registers. +//! @param x USDHC instance number. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_USDHC(0). +#define HW_USDHC(x) (*(volatile hw_usdhc_t *) REGS_USDHC_BASE(x)) + +#endif + + +#endif // __HW_USDHC_REGISTERS_H__ diff --git a/bsp/imx6ul/platform/include/mx6ul/regs.h b/bsp/imx6ul/platform/include/mx6ul/regs.h new file mode 100644 index 0000000000000000000000000000000000000000..ed11722e8580d805ef054fa7eeaa046433ec2483 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/regs.h @@ -0,0 +1,470 @@ +/* + * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. + */ + +#ifndef _REGS_H +#define _REGS_H 1 + +// +// define base address of the register block only if it is not already +// defined, which allows the compiler to override at build time for +// users who've mapped their registers to locations other than the +// physical location +// + +#ifndef REGS_BASE +#define REGS_BASE 0x00000000 +#endif + +// +// common register types +// + +#ifndef __LANGUAGE_ASM__ +typedef unsigned char reg8_t; +typedef unsigned short reg16_t; +typedef unsigned int reg32_t; +#endif + +// +// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is +// used to simplify macro definitions in the module register headers. +// +#ifndef __REG_VALUE_TYPE + #ifndef __LANGUAGE_ASM__ + #define __REG_VALUE_TYPE(v, t) ((t)(v)) + #else + #define __REG_VALUE_TYPE(v, t) (v) + #endif +#endif + +// +// macros for single instance registers +// + +#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) +#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) +#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) + +#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) +#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) +#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) + +#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BF_RD(reg, field) HW_##reg.B.field +#define BF_WR(reg, field, v) BW_##reg##_##field(v) + +#define BF_CS1(reg, f1, v1) \ + (HW_##reg##_CLR(BM_##reg##_##f1), \ + HW_##reg##_SET(BF_##reg##_##f1(v1))) + +#define BF_CS2(reg, f1, v1, f2, v2) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +// +// macros for multiple instance registers +// + +#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) +#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) +#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) + +#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) +#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) +#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) + +#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym + +#define BF_RDn(reg, n, field) HW_##reg(n).B.field +#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) + +#define BF_CS1n(reg, n, f1, v1) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) + +#define BF_CS2n(reg, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +// +// macros for single instance MULTI-BLOCK registers +// + +#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) +#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) +#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) + +#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) +#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) +#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) + +#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field +#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) + +#define BFn_CS1(reg, blk, f1, v1) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) + +#define BFn_CS2(reg, blk, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +// +// macros for MULTI-BLOCK multiple instance registers +// + +#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) +#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) +#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) + +#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) +#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) +#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) + +#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field +#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) + +#define BFn_CS1n(reg, blk, n, f1, v1) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) + +#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +#endif // _REGS_H + +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/mx6ul/regsapbh.h b/bsp/imx6ul/platform/include/mx6ul/regsapbh.h new file mode 100644 index 0000000000000000000000000000000000000000..be19ed6989f04c55deebdf53034116d25003ac12 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/regsapbh.h @@ -0,0 +1,1963 @@ +/* + * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. + */ + +#ifndef _APBH_H +#define _APBH_H 1 + +#include "regs.h" +//#include "registers.h" + +#ifndef REGS_APBH_BASE +#define REGS_APBH_BASE (REGS_BASE + 0x110000) +#endif + +/* + * HW_APBH_CTRL0 - AHB to APBH Bridge Control and Status Register 0 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CLKGATE_CHANNEL:16; + unsigned RSVD0:12; + unsigned APB_BURST_EN:1; + unsigned AHB_BURST8_EN:1; + unsigned CLKGATE:1; + unsigned SFTRST:1; + } B; +} hw_apbh_ctrl0_t; +#endif + +/* + * constants & macros for entire HW_APBH_CTRL0 register + */ +#define HW_APBH_CTRL0_ADDR (0x00110000) +#define HW_APBH_CTRL0_SET_ADDR (0x00110004) +#define HW_APBH_CTRL0_CLR_ADDR (0x00110008) +#define HW_APBH_CTRL0_TOG_ADDR (0x0011000c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_APBH_CTRL0 (*(volatile hw_apbh_ctrl0_t *) HW_APBH_CTRL0_ADDR) +#define HW_APBH_CTRL0_RD() (HW_APBH_CTRL0.U) +#define HW_APBH_CTRL0_WR(v) (HW_APBH_CTRL0.U = (v)) +#define HW_APBH_CTRL0_SET(v) ((*(volatile reg32_t *) HW_APBH_CTRL0_SET_ADDR) = (v)) +#define HW_APBH_CTRL0_CLR(v) ((*(volatile reg32_t *) HW_APBH_CTRL0_CLR_ADDR) = (v)) +#define HW_APBH_CTRL0_TOG(v) ((*(volatile reg32_t *) HW_APBH_CTRL0_TOG_ADDR) = (v)) +#else +#define HW_APBH_CTRL0_RD() (_rbase->mem32_read(HW_APBH_CTRL0_ADDR)) +#define HW_APBH_CTRL0_WR(v) (_rbase->mem32_write(HW_APBH_CTRL0_ADDR,(v))) +#define HW_APBH_CTRL0_SET(v) (_rbase->mem32_write(HW_APBH_CTRL0_SET_ADDR,(v))) +#define HW_APBH_CTRL0_CLR(v) (_rbase->mem32_write(HW_APBH_CTRL0_CLR_ADDR,(v))) +#define HW_APBH_CTRL0_TOG(v) (_rbase->mem32_write(HW_APBH_CTRL0_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_APBH_CTRL0 bitfields + */ +/* --- Register HW_APBH_CTRL0, field SFTRST */ + +#define BP_APBH_CTRL0_SFTRST 31 +#define BM_APBH_CTRL0_SFTRST 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CTRL0_SFTRST(v) ((((reg32_t) v) << 31) & BM_APBH_CTRL0_SFTRST) +#else +#define BF_APBH_CTRL0_SFTRST(v) (((v) << 31) & BM_APBH_CTRL0_SFTRST) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL0_SFTRST(v) BF_CS1(APBH_CTRL0, SFTRST, v) +#endif + +/* --- Register HW_APBH_CTRL0, field CLKGATE */ + +#define BP_APBH_CTRL0_CLKGATE 30 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 + +#define BF_APBH_CTRL0_CLKGATE(v) (((v) << 30) & BM_APBH_CTRL0_CLKGATE) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL0_CLKGATE(v) BF_CS1(APBH_CTRL0, CLKGATE, v) +#endif + +/* --- Register HW_APBH_CTRL0, field AHB_BURST8_EN */ + +#define BP_APBH_CTRL0_AHB_BURST8_EN 29 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 + +#define BF_APBH_CTRL0_AHB_BURST8_EN(v) (((v) << 29) & BM_APBH_CTRL0_AHB_BURST8_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL0_AHB_BURST8_EN(v) BF_CS1(APBH_CTRL0, AHB_BURST8_EN, v) +#endif + +/* --- Register HW_APBH_CTRL0, field APB_BURST_EN */ + +#define BP_APBH_CTRL0_APB_BURST_EN 28 +#define BM_APBH_CTRL0_APB_BURST_EN 0x10000000 + +#define BF_APBH_CTRL0_APB_BURST_EN(v) (((v) << 28) & BM_APBH_CTRL0_APB_BURST_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL0_APB_BURST_EN(v) BF_CS1(APBH_CTRL0, APB_BURST_EN, v) +#endif + +/* --- Register HW_APBH_CTRL0, field RSVD0 */ + +#define BP_APBH_CTRL0_RSVD0 16 +#define BM_APBH_CTRL0_RSVD0 0x0FFF0000 + +#define BF_APBH_CTRL0_RSVD0(v) (((v) << 16) & BM_APBH_CTRL0_RSVD0) +/* --- Register HW_APBH_CTRL0, field CLKGATE_CHANNEL */ + +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 0 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FFFF + +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) (((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL0_CLKGATE_CHANNEL(v) (HW_APBH_CTRL0.B.CLKGATE_CHANNEL = (v)) +#endif + +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0001 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0002 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0004 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0008 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0010 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0020 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0040 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0080 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP 0x0100 +#define NAND_CHANNEL 0 + +/* + * HW_APBH_CTRL1 - AHB to APBH Bridge Control and Status Register 1 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CH0_CMDCMPLT_IRQ:1; + unsigned CH1_CMDCMPLT_IRQ:1; + unsigned CH2_CMDCMPLT_IRQ:1; + unsigned CH3_CMDCMPLT_IRQ:1; + unsigned CH4_CMDCMPLT_IRQ:1; + unsigned CH5_CMDCMPLT_IRQ:1; + unsigned CH6_CMDCMPLT_IRQ:1; + unsigned CH7_CMDCMPLT_IRQ:1; + unsigned CH8_CMDCMPLT_IRQ:1; + unsigned CH9_CMDCMPLT_IRQ:1; + unsigned CH10_CMDCMPLT_IRQ:1; + unsigned CH11_CMDCMPLT_IRQ:1; + unsigned CH12_CMDCMPLT_IRQ:1; + unsigned CH13_CMDCMPLT_IRQ:1; + unsigned CH14_CMDCMPLT_IRQ:1; + unsigned CH15_CMDCMPLT_IRQ:1; + unsigned CH0_CMDCMPLT_IRQ_EN:1; + unsigned CH1_CMDCMPLT_IRQ_EN:1; + unsigned CH2_CMDCMPLT_IRQ_EN:1; + unsigned CH3_CMDCMPLT_IRQ_EN:1; + unsigned CH4_CMDCMPLT_IRQ_EN:1; + unsigned CH5_CMDCMPLT_IRQ_EN:1; + unsigned CH6_CMDCMPLT_IRQ_EN:1; + unsigned CH7_CMDCMPLT_IRQ_EN:1; + unsigned CH8_CMDCMPLT_IRQ_EN:1; + unsigned CH9_CMDCMPLT_IRQ_EN:1; + unsigned CH10_CMDCMPLT_IRQ_EN:1; + unsigned CH11_CMDCMPLT_IRQ_EN:1; + unsigned CH12_CMDCMPLT_IRQ_EN:1; + unsigned CH13_CMDCMPLT_IRQ_EN:1; + unsigned CH14_CMDCMPLT_IRQ_EN:1; + unsigned CH15_CMDCMPLT_IRQ_EN:1; + } B; +} hw_apbh_ctrl1_t; +#endif + +/* + * constants & macros for entire HW_APBH_CTRL1 register + */ +#define HW_APBH_CTRL1_ADDR (0x00110010) +#define HW_APBH_CTRL1_SET_ADDR (0x00110014) +#define HW_APBH_CTRL1_CLR_ADDR (0x00110018) +#define HW_APBH_CTRL1_TOG_ADDR (0x0011001c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_APBH_CTRL1 (*(volatile hw_apbh_ctrl1_t *) HW_APBH_CTRL1_ADDR) +#define HW_APBH_CTRL1_RD() (HW_APBH_CTRL1.U) +#define HW_APBH_CTRL1_WR(v) (HW_APBH_CTRL1.U = (v)) +#define HW_APBH_CTRL1_SET(v) ((*(volatile reg32_t *) HW_APBH_CTRL1_SET_ADDR) = (v)) +#define HW_APBH_CTRL1_CLR(v) ((*(volatile reg32_t *) HW_APBH_CTRL1_CLR_ADDR) = (v)) +#define HW_APBH_CTRL1_TOG(v) ((*(volatile reg32_t *) HW_APBH_CTRL1_TOG_ADDR) = (v)) +#else +#define HW_APBH_CTRL1_RD() (_rbase->mem32_read(HW_APBH_CTRL1_ADDR)) +#define HW_APBH_CTRL1_WR(v) (_rbase->mem32_write(HW_APBH_CTRL1_ADDR,(v))) +#define HW_APBH_CTRL1_SET(v) (_rbase->mem32_write(HW_APBH_CTRL1_SET_ADDR,(v))) +#define HW_APBH_CTRL1_CLR(v) (_rbase->mem32_write(HW_APBH_CTRL1_CLR_ADDR,(v))) +#define HW_APBH_CTRL1_TOG(v) (_rbase->mem32_write(HW_APBH_CTRL1_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_APBH_CTRL1 bitfields + */ +/* --- Register HW_APBH_CTRL1, field CH15_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN 31 +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(v) ((((reg32_t) v) << 31) & BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN) +#else +#define BF_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(v) (((v) << 31) & BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH15_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH14_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN 30 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 + +#define BF_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(v) (((v) << 30) & BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH14_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH13_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN 29 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 + +#define BF_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(v) (((v) << 29) & BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH13_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH12_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN 28 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 + +#define BF_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(v) (((v) << 28) & BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH12_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH11_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN 27 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 + +#define BF_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(v) (((v) << 27) & BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH11_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH10_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN 26 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 + +#define BF_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(v) (((v) << 26) & BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH10_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH9_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN 25 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 + +#define BF_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(v) (((v) << 25) & BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH9_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH8_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN 24 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 + +#define BF_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(v) (((v) << 24) & BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH8_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH7_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 23 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 + +#define BF_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(v) (((v) << 23) & BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH7_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH6_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 22 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 + +#define BF_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(v) (((v) << 22) & BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH6_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH5_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 21 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 + +#define BF_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(v) (((v) << 21) & BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH5_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH4_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 20 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 + +#define BF_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(v) (((v) << 20) & BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH4_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH3_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 19 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 + +#define BF_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(v) (((v) << 19) & BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH3_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH2_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 18 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 + +#define BF_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(v) (((v) << 18) & BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH2_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH1_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 17 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 + +#define BF_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(v) (((v) << 17) & BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH1_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH0_CMDCMPLT_IRQ_EN */ + +#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 16 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 + +#define BF_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(v) (((v) << 16) & BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(v) BF_CS1(APBH_CTRL1, CH0_CMDCMPLT_IRQ_EN, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH15_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH15_CMDCMPLT_IRQ 15 +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 + +#define BF_APBH_CTRL1_CH15_CMDCMPLT_IRQ(v) (((v) << 15) & BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH15_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH15_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH14_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH14_CMDCMPLT_IRQ 14 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 + +#define BF_APBH_CTRL1_CH14_CMDCMPLT_IRQ(v) (((v) << 14) & BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH14_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH14_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH13_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH13_CMDCMPLT_IRQ 13 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 + +#define BF_APBH_CTRL1_CH13_CMDCMPLT_IRQ(v) (((v) << 13) & BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH13_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH13_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH12_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH12_CMDCMPLT_IRQ 12 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 + +#define BF_APBH_CTRL1_CH12_CMDCMPLT_IRQ(v) (((v) << 12) & BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH12_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH12_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH11_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH11_CMDCMPLT_IRQ 11 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 + +#define BF_APBH_CTRL1_CH11_CMDCMPLT_IRQ(v) (((v) << 11) & BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH11_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH11_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH10_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH10_CMDCMPLT_IRQ 10 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 + +#define BF_APBH_CTRL1_CH10_CMDCMPLT_IRQ(v) (((v) << 10) & BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH10_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH10_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH9_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH9_CMDCMPLT_IRQ 9 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 + +#define BF_APBH_CTRL1_CH9_CMDCMPLT_IRQ(v) (((v) << 9) & BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH9_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH9_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH8_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH8_CMDCMPLT_IRQ 8 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 + +#define BF_APBH_CTRL1_CH8_CMDCMPLT_IRQ(v) (((v) << 8) & BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH8_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH8_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH7_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ 7 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 + +#define BF_APBH_CTRL1_CH7_CMDCMPLT_IRQ(v) (((v) << 7) & BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH7_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH7_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH6_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH6_CMDCMPLT_IRQ 6 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 + +#define BF_APBH_CTRL1_CH6_CMDCMPLT_IRQ(v) (((v) << 6) & BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH6_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH6_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH5_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH5_CMDCMPLT_IRQ 5 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 + +#define BF_APBH_CTRL1_CH5_CMDCMPLT_IRQ(v) (((v) << 5) & BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH5_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH5_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH4_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH4_CMDCMPLT_IRQ 4 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 + +#define BF_APBH_CTRL1_CH4_CMDCMPLT_IRQ(v) (((v) << 4) & BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH4_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH4_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH3_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH3_CMDCMPLT_IRQ 3 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 + +#define BF_APBH_CTRL1_CH3_CMDCMPLT_IRQ(v) (((v) << 3) & BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH3_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH3_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH2_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH2_CMDCMPLT_IRQ 2 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 + +#define BF_APBH_CTRL1_CH2_CMDCMPLT_IRQ(v) (((v) << 2) & BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH2_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH2_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH1_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ 1 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 + +#define BF_APBH_CTRL1_CH1_CMDCMPLT_IRQ(v) (((v) << 1) & BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH1_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH1_CMDCMPLT_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL1, field CH0_CMDCMPLT_IRQ */ + +#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define BF_APBH_CTRL1_CH0_CMDCMPLT_IRQ(v) (((v) << 0) & BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL1_CH0_CMDCMPLT_IRQ(v) BF_CS1(APBH_CTRL1, CH0_CMDCMPLT_IRQ, v) +#endif + +/* + * HW_APBH_CTRL2 - AHB to APBH Bridge Control and Status Register 2 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CH0_ERROR_IRQ:1; + unsigned CH1_ERROR_IRQ:1; + unsigned CH2_ERROR_IRQ:1; + unsigned CH3_ERROR_IRQ:1; + unsigned CH4_ERROR_IRQ:1; + unsigned CH5_ERROR_IRQ:1; + unsigned CH6_ERROR_IRQ:1; + unsigned CH7_ERROR_IRQ:1; + unsigned CH8_ERROR_IRQ:1; + unsigned CH9_ERROR_IRQ:1; + unsigned CH10_ERROR_IRQ:1; + unsigned CH11_ERROR_IRQ:1; + unsigned CH12_ERROR_IRQ:1; + unsigned CH13_ERROR_IRQ:1; + unsigned CH14_ERROR_IRQ:1; + unsigned CH15_ERROR_IRQ:1; + unsigned CH0_ERROR_STATUS:1; + unsigned CH1_ERROR_STATUS:1; + unsigned CH2_ERROR_STATUS:1; + unsigned CH3_ERROR_STATUS:1; + unsigned CH4_ERROR_STATUS:1; + unsigned CH5_ERROR_STATUS:1; + unsigned CH6_ERROR_STATUS:1; + unsigned CH7_ERROR_STATUS:1; + unsigned CH8_ERROR_STATUS:1; + unsigned CH9_ERROR_STATUS:1; + unsigned CH10_ERROR_STATUS:1; + unsigned CH11_ERROR_STATUS:1; + unsigned CH12_ERROR_STATUS:1; + unsigned CH13_ERROR_STATUS:1; + unsigned CH14_ERROR_STATUS:1; + unsigned CH15_ERROR_STATUS:1; + } B; +} hw_apbh_ctrl2_t; +#endif + +/* + * constants & macros for entire HW_APBH_CTRL2 register + */ +#define HW_APBH_CTRL2_ADDR (0x00110020) +#define HW_APBH_CTRL2_SET_ADDR (0x00110024) +#define HW_APBH_CTRL2_CLR_ADDR (0x00110028) +#define HW_APBH_CTRL2_TOG_ADDR (0x0011002c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_APBH_CTRL2 (*(volatile hw_apbh_ctrl2_t *) HW_APBH_CTRL2_ADDR) +#define HW_APBH_CTRL2_RD() (HW_APBH_CTRL2.U) +#define HW_APBH_CTRL2_WR(v) (HW_APBH_CTRL2.U = (v)) +#define HW_APBH_CTRL2_SET(v) ((*(volatile reg32_t *) HW_APBH_CTRL2_SET_ADDR) = (v)) +#define HW_APBH_CTRL2_CLR(v) ((*(volatile reg32_t *) HW_APBH_CTRL2_CLR_ADDR) = (v)) +#define HW_APBH_CTRL2_TOG(v) ((*(volatile reg32_t *) HW_APBH_CTRL2_TOG_ADDR) = (v)) +#else +#define HW_APBH_CTRL2_RD() (_rbase->mem32_read(HW_APBH_CTRL2_ADDR)) +#define HW_APBH_CTRL2_WR(v) (_rbase->mem32_write(HW_APBH_CTRL2_ADDR,(v))) +#define HW_APBH_CTRL2_SET(v) (_rbase->mem32_write(HW_APBH_CTRL2_SET_ADDR,(v))) +#define HW_APBH_CTRL2_CLR(v) (_rbase->mem32_write(HW_APBH_CTRL2_CLR_ADDR,(v))) +#define HW_APBH_CTRL2_TOG(v) (_rbase->mem32_write(HW_APBH_CTRL2_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_APBH_CTRL2 bitfields + */ +/* --- Register HW_APBH_CTRL2, field CH15_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH15_ERROR_STATUS 31 +#define BM_APBH_CTRL2_CH15_ERROR_STATUS 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CTRL2_CH15_ERROR_STATUS(v) ((((reg32_t) v) << 31) & BM_APBH_CTRL2_CH15_ERROR_STATUS) +#else +#define BF_APBH_CTRL2_CH15_ERROR_STATUS(v) (((v) << 31) & BM_APBH_CTRL2_CH15_ERROR_STATUS) +#endif +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH14_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH14_ERROR_STATUS 30 +#define BM_APBH_CTRL2_CH14_ERROR_STATUS 0x40000000 + +#define BF_APBH_CTRL2_CH14_ERROR_STATUS(v) (((v) << 30) & BM_APBH_CTRL2_CH14_ERROR_STATUS) +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH13_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH13_ERROR_STATUS 29 +#define BM_APBH_CTRL2_CH13_ERROR_STATUS 0x20000000 + +#define BF_APBH_CTRL2_CH13_ERROR_STATUS(v) (((v) << 29) & BM_APBH_CTRL2_CH13_ERROR_STATUS) +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH12_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH12_ERROR_STATUS 28 +#define BM_APBH_CTRL2_CH12_ERROR_STATUS 0x10000000 + +#define BF_APBH_CTRL2_CH12_ERROR_STATUS(v) (((v) << 28) & BM_APBH_CTRL2_CH12_ERROR_STATUS) +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH11_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH11_ERROR_STATUS 27 +#define BM_APBH_CTRL2_CH11_ERROR_STATUS 0x08000000 + +#define BF_APBH_CTRL2_CH11_ERROR_STATUS(v) (((v) << 27) & BM_APBH_CTRL2_CH11_ERROR_STATUS) +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH10_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH10_ERROR_STATUS 26 +#define BM_APBH_CTRL2_CH10_ERROR_STATUS 0x04000000 + +#define BF_APBH_CTRL2_CH10_ERROR_STATUS(v) (((v) << 26) & BM_APBH_CTRL2_CH10_ERROR_STATUS) +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH9_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH9_ERROR_STATUS 25 +#define BM_APBH_CTRL2_CH9_ERROR_STATUS 0x02000000 + +#define BF_APBH_CTRL2_CH9_ERROR_STATUS(v) (((v) << 25) & BM_APBH_CTRL2_CH9_ERROR_STATUS) +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH8_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH8_ERROR_STATUS 24 +#define BM_APBH_CTRL2_CH8_ERROR_STATUS 0x01000000 + +#define BF_APBH_CTRL2_CH8_ERROR_STATUS(v) (((v) << 24) & BM_APBH_CTRL2_CH8_ERROR_STATUS) +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH7_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH7_ERROR_STATUS 23 +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 + +#define BF_APBH_CTRL2_CH7_ERROR_STATUS(v) (((v) << 23) & BM_APBH_CTRL2_CH7_ERROR_STATUS) +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH6_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH6_ERROR_STATUS 22 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 + +#define BF_APBH_CTRL2_CH6_ERROR_STATUS(v) (((v) << 22) & BM_APBH_CTRL2_CH6_ERROR_STATUS) +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH5_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH5_ERROR_STATUS 21 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 + +#define BF_APBH_CTRL2_CH5_ERROR_STATUS(v) (((v) << 21) & BM_APBH_CTRL2_CH5_ERROR_STATUS) +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH4_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH4_ERROR_STATUS 20 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 + +#define BF_APBH_CTRL2_CH4_ERROR_STATUS(v) (((v) << 20) & BM_APBH_CTRL2_CH4_ERROR_STATUS) +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH3_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH3_ERROR_STATUS 19 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 + +#define BF_APBH_CTRL2_CH3_ERROR_STATUS(v) (((v) << 19) & BM_APBH_CTRL2_CH3_ERROR_STATUS) +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH2_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH2_ERROR_STATUS 18 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 + +#define BF_APBH_CTRL2_CH2_ERROR_STATUS(v) (((v) << 18) & BM_APBH_CTRL2_CH2_ERROR_STATUS) +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH1_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH1_ERROR_STATUS 17 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 + +#define BF_APBH_CTRL2_CH1_ERROR_STATUS(v) (((v) << 17) & BM_APBH_CTRL2_CH1_ERROR_STATUS) +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH0_ERROR_STATUS */ + +#define BP_APBH_CTRL2_CH0_ERROR_STATUS 16 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 + +#define BF_APBH_CTRL2_CH0_ERROR_STATUS(v) (((v) << 16) & BM_APBH_CTRL2_CH0_ERROR_STATUS) +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 + +/* --- Register HW_APBH_CTRL2, field CH15_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH15_ERROR_IRQ 15 +#define BM_APBH_CTRL2_CH15_ERROR_IRQ 0x00008000 + +#define BF_APBH_CTRL2_CH15_ERROR_IRQ(v) (((v) << 15) & BM_APBH_CTRL2_CH15_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH15_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH15_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH14_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH14_ERROR_IRQ 14 +#define BM_APBH_CTRL2_CH14_ERROR_IRQ 0x00004000 + +#define BF_APBH_CTRL2_CH14_ERROR_IRQ(v) (((v) << 14) & BM_APBH_CTRL2_CH14_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH14_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH14_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH13_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH13_ERROR_IRQ 13 +#define BM_APBH_CTRL2_CH13_ERROR_IRQ 0x00002000 + +#define BF_APBH_CTRL2_CH13_ERROR_IRQ(v) (((v) << 13) & BM_APBH_CTRL2_CH13_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH13_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH13_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH12_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH12_ERROR_IRQ 12 +#define BM_APBH_CTRL2_CH12_ERROR_IRQ 0x00001000 + +#define BF_APBH_CTRL2_CH12_ERROR_IRQ(v) (((v) << 12) & BM_APBH_CTRL2_CH12_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH12_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH12_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH11_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH11_ERROR_IRQ 11 +#define BM_APBH_CTRL2_CH11_ERROR_IRQ 0x00000800 + +#define BF_APBH_CTRL2_CH11_ERROR_IRQ(v) (((v) << 11) & BM_APBH_CTRL2_CH11_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH11_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH11_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH10_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH10_ERROR_IRQ 10 +#define BM_APBH_CTRL2_CH10_ERROR_IRQ 0x00000400 + +#define BF_APBH_CTRL2_CH10_ERROR_IRQ(v) (((v) << 10) & BM_APBH_CTRL2_CH10_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH10_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH10_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH9_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH9_ERROR_IRQ 9 +#define BM_APBH_CTRL2_CH9_ERROR_IRQ 0x00000200 + +#define BF_APBH_CTRL2_CH9_ERROR_IRQ(v) (((v) << 9) & BM_APBH_CTRL2_CH9_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH9_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH9_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH8_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH8_ERROR_IRQ 8 +#define BM_APBH_CTRL2_CH8_ERROR_IRQ 0x00000100 + +#define BF_APBH_CTRL2_CH8_ERROR_IRQ(v) (((v) << 8) & BM_APBH_CTRL2_CH8_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH8_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH8_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH7_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH7_ERROR_IRQ 7 +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 + +#define BF_APBH_CTRL2_CH7_ERROR_IRQ(v) (((v) << 7) & BM_APBH_CTRL2_CH7_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH7_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH7_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH6_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH6_ERROR_IRQ 6 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 + +#define BF_APBH_CTRL2_CH6_ERROR_IRQ(v) (((v) << 6) & BM_APBH_CTRL2_CH6_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH6_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH6_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH5_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH5_ERROR_IRQ 5 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 + +#define BF_APBH_CTRL2_CH5_ERROR_IRQ(v) (((v) << 5) & BM_APBH_CTRL2_CH5_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH5_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH5_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH4_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH4_ERROR_IRQ 4 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 + +#define BF_APBH_CTRL2_CH4_ERROR_IRQ(v) (((v) << 4) & BM_APBH_CTRL2_CH4_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH4_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH4_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH3_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH3_ERROR_IRQ 3 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 + +#define BF_APBH_CTRL2_CH3_ERROR_IRQ(v) (((v) << 3) & BM_APBH_CTRL2_CH3_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH3_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH3_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH2_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH2_ERROR_IRQ 2 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 + +#define BF_APBH_CTRL2_CH2_ERROR_IRQ(v) (((v) << 2) & BM_APBH_CTRL2_CH2_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH2_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH2_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH1_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH1_ERROR_IRQ 1 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 + +#define BF_APBH_CTRL2_CH1_ERROR_IRQ(v) (((v) << 1) & BM_APBH_CTRL2_CH1_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH1_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH1_ERROR_IRQ, v) +#endif + +/* --- Register HW_APBH_CTRL2, field CH0_ERROR_IRQ */ + +#define BP_APBH_CTRL2_CH0_ERROR_IRQ 0 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define BF_APBH_CTRL2_CH0_ERROR_IRQ(v) (((v) << 0) & BM_APBH_CTRL2_CH0_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CTRL2_CH0_ERROR_IRQ(v) BF_CS1(APBH_CTRL2, CH0_ERROR_IRQ, v) +#endif + +/* + * HW_APBH_CHANNEL_CTRL - AHB to APBH Bridge Channel Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned FREEZE_CHANNEL:16; + unsigned RESET_CHANNEL:16; + } B; +} hw_apbh_channel_ctrl_t; +#endif + +/* + * constants & macros for entire HW_APBH_CHANNEL_CTRL register + */ +#define HW_APBH_CHANNEL_CTRL_ADDR (0x00110030) +#define HW_APBH_CHANNEL_CTRL_SET_ADDR (0x00110034) +#define HW_APBH_CHANNEL_CTRL_CLR_ADDR (0x00110038) +#define HW_APBH_CHANNEL_CTRL_TOG_ADDR (0x0011003c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_APBH_CHANNEL_CTRL (*(volatile hw_apbh_channel_ctrl_t *) HW_APBH_CHANNEL_CTRL_ADDR) +#define HW_APBH_CHANNEL_CTRL_RD() (HW_APBH_CHANNEL_CTRL.U) +#define HW_APBH_CHANNEL_CTRL_WR(v) (HW_APBH_CHANNEL_CTRL.U = (v)) +#define HW_APBH_CHANNEL_CTRL_SET(v) ((*(volatile reg32_t *) HW_APBH_CHANNEL_CTRL_SET_ADDR) = (v)) +#define HW_APBH_CHANNEL_CTRL_CLR(v) ((*(volatile reg32_t *) HW_APBH_CHANNEL_CTRL_CLR_ADDR) = (v)) +#define HW_APBH_CHANNEL_CTRL_TOG(v) ((*(volatile reg32_t *) HW_APBH_CHANNEL_CTRL_TOG_ADDR) = (v)) +#else +#define HW_APBH_CHANNEL_CTRL_RD() (_rbase->mem32_read(HW_APBH_CHANNEL_CTRL_ADDR)) +#define HW_APBH_CHANNEL_CTRL_WR(v) (_rbase->mem32_write(HW_APBH_CHANNEL_CTRL_ADDR,(v))) +#define HW_APBH_CHANNEL_CTRL_SET(v) (_rbase->mem32_write(HW_APBH_CHANNEL_CTRL_SET_ADDR,(v))) +#define HW_APBH_CHANNEL_CTRL_CLR(v) (_rbase->mem32_write(HW_APBH_CHANNEL_CTRL_CLR_ADDR,(v))) +#define HW_APBH_CHANNEL_CTRL_TOG(v) (_rbase->mem32_write(HW_APBH_CHANNEL_CTRL_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_APBH_CHANNEL_CTRL bitfields + */ +/* --- Register HW_APBH_CHANNEL_CTRL, field RESET_CHANNEL */ + +#define BP_APBH_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) ((((reg32_t) v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) +#else +#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) (((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) (HW_APBH_CHANNEL_CTRL.B.RESET_CHANNEL = (v)) +#endif + +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0001 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0002 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0004 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0008 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0010 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0020 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0040 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0080 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP 0x0100 + +/* --- Register HW_APBH_CHANNEL_CTRL, field FREEZE_CHANNEL */ + +#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF + +#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) (((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) (HW_APBH_CHANNEL_CTRL.B.FREEZE_CHANNEL = (v)) +#endif + +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0001 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0002 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0004 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0008 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0010 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0020 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0040 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0080 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP 0x0100 + +/* + * HW_APBH_DEVSEL - AHB to APBH DMA Device Assignment Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CH0:2; + unsigned CH1:2; + unsigned CH2:2; + unsigned CH3:2; + unsigned CH4:2; + unsigned CH5:2; + unsigned CH6:2; + unsigned CH7:2; + unsigned CH8:2; + unsigned CH9:2; + unsigned CH10:2; + unsigned CH11:2; + unsigned CH12:2; + unsigned CH13:2; + unsigned CH14:2; + unsigned CH15:2; + } B; +} hw_apbh_devsel_t; +#endif + +/* + * constants & macros for entire HW_APBH_DEVSEL register + */ +#define HW_APBH_DEVSEL_ADDR (0x00110040) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_APBH_DEVSEL (*(volatile hw_apbh_devsel_t *) HW_APBH_DEVSEL_ADDR) +#define HW_APBH_DEVSEL_RD() (HW_APBH_DEVSEL.U) +#else +#define HW_APBH_DEVSEL_RD() (_rbase->mem32_read(HW_APBH_DEVSEL_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_APBH_DEVSEL bitfields + */ +/* --- Register HW_APBH_DEVSEL, field CH15 */ + +#define BP_APBH_DEVSEL_CH15 30 +#define BM_APBH_DEVSEL_CH15 0xC0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_DEVSEL_CH15(v) ((((reg32_t) v) << 30) & BM_APBH_DEVSEL_CH15) +#else +#define BF_APBH_DEVSEL_CH15(v) (((v) << 30) & BM_APBH_DEVSEL_CH15) +#endif +/* --- Register HW_APBH_DEVSEL, field CH14 */ + +#define BP_APBH_DEVSEL_CH14 28 +#define BM_APBH_DEVSEL_CH14 0x30000000 + +#define BF_APBH_DEVSEL_CH14(v) (((v) << 28) & BM_APBH_DEVSEL_CH14) +/* --- Register HW_APBH_DEVSEL, field CH13 */ + +#define BP_APBH_DEVSEL_CH13 26 +#define BM_APBH_DEVSEL_CH13 0x0C000000 + +#define BF_APBH_DEVSEL_CH13(v) (((v) << 26) & BM_APBH_DEVSEL_CH13) +/* --- Register HW_APBH_DEVSEL, field CH12 */ + +#define BP_APBH_DEVSEL_CH12 24 +#define BM_APBH_DEVSEL_CH12 0x03000000 + +#define BF_APBH_DEVSEL_CH12(v) (((v) << 24) & BM_APBH_DEVSEL_CH12) +/* --- Register HW_APBH_DEVSEL, field CH11 */ + +#define BP_APBH_DEVSEL_CH11 22 +#define BM_APBH_DEVSEL_CH11 0x00C00000 + +#define BF_APBH_DEVSEL_CH11(v) (((v) << 22) & BM_APBH_DEVSEL_CH11) +/* --- Register HW_APBH_DEVSEL, field CH10 */ + +#define BP_APBH_DEVSEL_CH10 20 +#define BM_APBH_DEVSEL_CH10 0x00300000 + +#define BF_APBH_DEVSEL_CH10(v) (((v) << 20) & BM_APBH_DEVSEL_CH10) +/* --- Register HW_APBH_DEVSEL, field CH9 */ + +#define BP_APBH_DEVSEL_CH9 18 +#define BM_APBH_DEVSEL_CH9 0x000C0000 + +#define BF_APBH_DEVSEL_CH9(v) (((v) << 18) & BM_APBH_DEVSEL_CH9) +/* --- Register HW_APBH_DEVSEL, field CH8 */ + +#define BP_APBH_DEVSEL_CH8 16 +#define BM_APBH_DEVSEL_CH8 0x00030000 + +#define BF_APBH_DEVSEL_CH8(v) (((v) << 16) & BM_APBH_DEVSEL_CH8) +/* --- Register HW_APBH_DEVSEL, field CH7 */ + +#define BP_APBH_DEVSEL_CH7 14 +#define BM_APBH_DEVSEL_CH7 0x0000C000 + +#define BF_APBH_DEVSEL_CH7(v) (((v) << 14) & BM_APBH_DEVSEL_CH7) +/* --- Register HW_APBH_DEVSEL, field CH6 */ + +#define BP_APBH_DEVSEL_CH6 12 +#define BM_APBH_DEVSEL_CH6 0x00003000 + +#define BF_APBH_DEVSEL_CH6(v) (((v) << 12) & BM_APBH_DEVSEL_CH6) +/* --- Register HW_APBH_DEVSEL, field CH5 */ + +#define BP_APBH_DEVSEL_CH5 10 +#define BM_APBH_DEVSEL_CH5 0x00000C00 + +#define BF_APBH_DEVSEL_CH5(v) (((v) << 10) & BM_APBH_DEVSEL_CH5) +/* --- Register HW_APBH_DEVSEL, field CH4 */ + +#define BP_APBH_DEVSEL_CH4 8 +#define BM_APBH_DEVSEL_CH4 0x00000300 + +#define BF_APBH_DEVSEL_CH4(v) (((v) << 8) & BM_APBH_DEVSEL_CH4) +/* --- Register HW_APBH_DEVSEL, field CH3 */ + +#define BP_APBH_DEVSEL_CH3 6 +#define BM_APBH_DEVSEL_CH3 0x000000C0 + +#define BF_APBH_DEVSEL_CH3(v) (((v) << 6) & BM_APBH_DEVSEL_CH3) +/* --- Register HW_APBH_DEVSEL, field CH2 */ + +#define BP_APBH_DEVSEL_CH2 4 +#define BM_APBH_DEVSEL_CH2 0x00000030 + +#define BF_APBH_DEVSEL_CH2(v) (((v) << 4) & BM_APBH_DEVSEL_CH2) +/* --- Register HW_APBH_DEVSEL, field CH1 */ + +#define BP_APBH_DEVSEL_CH1 2 +#define BM_APBH_DEVSEL_CH1 0x0000000C + +#define BF_APBH_DEVSEL_CH1(v) (((v) << 2) & BM_APBH_DEVSEL_CH1) +/* --- Register HW_APBH_DEVSEL, field CH0 */ + +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x00000003 + +#define BF_APBH_DEVSEL_CH0(v) (((v) << 0) & BM_APBH_DEVSEL_CH0) + +/* + * HW_APBH_DMA_BURST_SIZE - AHB to APBH DMA burst size + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CH0:2; + unsigned CH1:2; + unsigned CH2:2; + unsigned CH3:2; + unsigned CH4:2; + unsigned CH5:2; + unsigned CH6:2; + unsigned CH7:2; + unsigned CH8:2; + unsigned CH9:2; + unsigned CH10:2; + unsigned CH11:2; + unsigned CH12:2; + unsigned CH13:2; + unsigned CH14:2; + unsigned CH15:2; + } B; +} hw_apbh_dma_burst_size_t; +#endif + +/* + * constants & macros for entire HW_APBH_DMA_BURST_SIZE register + */ +#define HW_APBH_DMA_BURST_SIZE_ADDR (0x00110050) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_APBH_DMA_BURST_SIZE (*(volatile hw_apbh_dma_burst_size_t *) HW_APBH_DMA_BURST_SIZE_ADDR) +#define HW_APBH_DMA_BURST_SIZE_RD() (HW_APBH_DMA_BURST_SIZE.U) +#define HW_APBH_DMA_BURST_SIZE_WR(v) (HW_APBH_DMA_BURST_SIZE.U = (v)) +#define HW_APBH_DMA_BURST_SIZE_SET(v) (HW_APBH_DMA_BURST_SIZE_WR(HW_APBH_DMA_BURST_SIZE_RD() | (v))) +#define HW_APBH_DMA_BURST_SIZE_CLR(v) (HW_APBH_DMA_BURST_SIZE_WR(HW_APBH_DMA_BURST_SIZE_RD() & ~(v))) +#define HW_APBH_DMA_BURST_SIZE_TOG(v) (HW_APBH_DMA_BURST_SIZE_WR(HW_APBH_DMA_BURST_SIZE_RD() ^ (v))) +#else +#define HW_APBH_DMA_BURST_SIZE_RD() (_rbase->mem32_read(HW_APBH_DMA_BURST_SIZE_ADDR)) +#define HW_APBH_DMA_BURST_SIZE_WR(v) (_rbase->mem32_write(HW_APBH_DMA_BURST_SIZE_ADDR,(v))) +#define HW_APBH_DMA_BURST_SIZE_SET(v) (HW_APBH_DMA_BURST_SIZE_WR(HW_APBH_DMA_BURST_SIZE_RD() | (v))) +#define HW_APBH_DMA_BURST_SIZE_CLR(v) (HW_APBH_DMA_BURST_SIZE_WR(HW_APBH_DMA_BURST_SIZE_RD() & ~(v))) +#define HW_APBH_DMA_BURST_SIZE_TOG(v) (HW_APBH_DMA_BURST_SIZE_WR(HW_APBH_DMA_BURST_SIZE_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_APBH_DMA_BURST_SIZE bitfields + */ +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH15 */ + +#define BP_APBH_DMA_BURST_SIZE_CH15 30 +#define BM_APBH_DMA_BURST_SIZE_CH15 0xC0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_DMA_BURST_SIZE_CH15(v) ((((reg32_t) v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15) +#else +#define BF_APBH_DMA_BURST_SIZE_CH15(v) (((v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15) +#endif +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH14 */ + +#define BP_APBH_DMA_BURST_SIZE_CH14 28 +#define BM_APBH_DMA_BURST_SIZE_CH14 0x30000000 + +#define BF_APBH_DMA_BURST_SIZE_CH14(v) (((v) << 28) & BM_APBH_DMA_BURST_SIZE_CH14) +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH13 */ + +#define BP_APBH_DMA_BURST_SIZE_CH13 26 +#define BM_APBH_DMA_BURST_SIZE_CH13 0x0C000000 + +#define BF_APBH_DMA_BURST_SIZE_CH13(v) (((v) << 26) & BM_APBH_DMA_BURST_SIZE_CH13) +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH12 */ + +#define BP_APBH_DMA_BURST_SIZE_CH12 24 +#define BM_APBH_DMA_BURST_SIZE_CH12 0x03000000 + +#define BF_APBH_DMA_BURST_SIZE_CH12(v) (((v) << 24) & BM_APBH_DMA_BURST_SIZE_CH12) +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH11 */ + +#define BP_APBH_DMA_BURST_SIZE_CH11 22 +#define BM_APBH_DMA_BURST_SIZE_CH11 0x00C00000 + +#define BF_APBH_DMA_BURST_SIZE_CH11(v) (((v) << 22) & BM_APBH_DMA_BURST_SIZE_CH11) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH11(v) BF_CS1(APBH_DMA_BURST_SIZE, CH11, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH10 */ + +#define BP_APBH_DMA_BURST_SIZE_CH10 20 +#define BM_APBH_DMA_BURST_SIZE_CH10 0x00300000 + +#define BF_APBH_DMA_BURST_SIZE_CH10(v) (((v) << 20) & BM_APBH_DMA_BURST_SIZE_CH10) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH10(v) BF_CS1(APBH_DMA_BURST_SIZE, CH10, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH9 */ + +#define BP_APBH_DMA_BURST_SIZE_CH9 18 +#define BM_APBH_DMA_BURST_SIZE_CH9 0x000C0000 + +#define BF_APBH_DMA_BURST_SIZE_CH9(v) (((v) << 18) & BM_APBH_DMA_BURST_SIZE_CH9) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH9(v) BF_CS1(APBH_DMA_BURST_SIZE, CH9, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH8 */ + +#define BP_APBH_DMA_BURST_SIZE_CH8 16 +#define BM_APBH_DMA_BURST_SIZE_CH8 0x00030000 + +#define BF_APBH_DMA_BURST_SIZE_CH8(v) (((v) << 16) & BM_APBH_DMA_BURST_SIZE_CH8) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH8(v) BF_CS1(APBH_DMA_BURST_SIZE, CH8, v) +#endif + +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST8 0x2 + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH7 */ + +#define BP_APBH_DMA_BURST_SIZE_CH7 14 +#define BM_APBH_DMA_BURST_SIZE_CH7 0x0000C000 + +#define BF_APBH_DMA_BURST_SIZE_CH7(v) (((v) << 14) & BM_APBH_DMA_BURST_SIZE_CH7) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH7(v) BF_CS1(APBH_DMA_BURST_SIZE, CH7, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH6 */ + +#define BP_APBH_DMA_BURST_SIZE_CH6 12 +#define BM_APBH_DMA_BURST_SIZE_CH6 0x00003000 + +#define BF_APBH_DMA_BURST_SIZE_CH6(v) (((v) << 12) & BM_APBH_DMA_BURST_SIZE_CH6) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH6(v) BF_CS1(APBH_DMA_BURST_SIZE, CH6, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH5 */ + +#define BP_APBH_DMA_BURST_SIZE_CH5 10 +#define BM_APBH_DMA_BURST_SIZE_CH5 0x00000C00 + +#define BF_APBH_DMA_BURST_SIZE_CH5(v) (((v) << 10) & BM_APBH_DMA_BURST_SIZE_CH5) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH5(v) BF_CS1(APBH_DMA_BURST_SIZE, CH5, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH4 */ + +#define BP_APBH_DMA_BURST_SIZE_CH4 8 +#define BM_APBH_DMA_BURST_SIZE_CH4 0x00000300 + +#define BF_APBH_DMA_BURST_SIZE_CH4(v) (((v) << 8) & BM_APBH_DMA_BURST_SIZE_CH4) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH4(v) BF_CS1(APBH_DMA_BURST_SIZE, CH4, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH3 */ + +#define BP_APBH_DMA_BURST_SIZE_CH3 6 +#define BM_APBH_DMA_BURST_SIZE_CH3 0x000000C0 + +#define BF_APBH_DMA_BURST_SIZE_CH3(v) (((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH3(v) BF_CS1(APBH_DMA_BURST_SIZE, CH3, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH2 */ + +#define BP_APBH_DMA_BURST_SIZE_CH2 4 +#define BM_APBH_DMA_BURST_SIZE_CH2 0x00000030 + +#define BF_APBH_DMA_BURST_SIZE_CH2(v) (((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH2(v) BF_CS1(APBH_DMA_BURST_SIZE, CH2, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH1 */ + +#define BP_APBH_DMA_BURST_SIZE_CH1 2 +#define BM_APBH_DMA_BURST_SIZE_CH1 0x0000000C + +#define BF_APBH_DMA_BURST_SIZE_CH1(v) (((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH1(v) BF_CS1(APBH_DMA_BURST_SIZE, CH1, v) +#endif + +/* --- Register HW_APBH_DMA_BURST_SIZE, field CH0 */ + +#define BP_APBH_DMA_BURST_SIZE_CH0 0 +#define BM_APBH_DMA_BURST_SIZE_CH0 0x00000003 + +#define BF_APBH_DMA_BURST_SIZE_CH0(v) (((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DMA_BURST_SIZE_CH0(v) BF_CS1(APBH_DMA_BURST_SIZE, CH0, v) +#endif + +/* + * HW_APBH_DEBUG - AHB to APBH DMA Debug Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned GPMI_ONE_FIFO:1; + unsigned RSVD:31; + } B; +} hw_apbh_debug_t; +#endif + +/* + * constants & macros for entire HW_APBH_DEBUG register + */ +#define HW_APBH_DEBUG_ADDR (0x00110060) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_APBH_DEBUG (*(volatile hw_apbh_debug_t *) HW_APBH_DEBUG_ADDR) +#define HW_APBH_DEBUG_RD() (HW_APBH_DEBUG.U) +#define HW_APBH_DEBUG_WR(v) (HW_APBH_DEBUG.U = (v)) +#define HW_APBH_DEBUG_SET(v) (HW_APBH_DEBUG_WR(HW_APBH_DEBUG_RD() | (v))) +#define HW_APBH_DEBUG_CLR(v) (HW_APBH_DEBUG_WR(HW_APBH_DEBUG_RD() & ~(v))) +#define HW_APBH_DEBUG_TOG(v) (HW_APBH_DEBUG_WR(HW_APBH_DEBUG_RD() ^ (v))) +#else +#define HW_APBH_DEBUG_RD() (_rbase->mem32_read(HW_APBH_DEBUG_ADDR)) +#define HW_APBH_DEBUG_WR(v) (_rbase->mem32_write(HW_APBH_DEBUG_ADDR,(v))) +#define HW_APBH_DEBUG_SET(v) (HW_APBH_DEBUG_WR(HW_APBH_DEBUG_RD() | (v))) +#define HW_APBH_DEBUG_CLR(v) (HW_APBH_DEBUG_WR(HW_APBH_DEBUG_RD() & ~(v))) +#define HW_APBH_DEBUG_TOG(v) (HW_APBH_DEBUG_WR(HW_APBH_DEBUG_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_APBH_DEBUG bitfields + */ +/* --- Register HW_APBH_DEBUG, field RSVD */ + +#define BP_APBH_DEBUG_RSVD 1 +#define BM_APBH_DEBUG_RSVD 0xFFFFFFFE + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_DEBUG_RSVD(v) ((((reg32_t) v) << 1) & BM_APBH_DEBUG_RSVD) +#else +#define BF_APBH_DEBUG_RSVD(v) (((v) << 1) & BM_APBH_DEBUG_RSVD) +#endif +/* --- Register HW_APBH_DEBUG, field GPMI_ONE_FIFO */ + +#define BP_APBH_DEBUG_GPMI_ONE_FIFO 0 +#define BM_APBH_DEBUG_GPMI_ONE_FIFO 0x00000001 + +#define BF_APBH_DEBUG_GPMI_ONE_FIFO(v) (((v) << 0) & BM_APBH_DEBUG_GPMI_ONE_FIFO) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_DEBUG_GPMI_ONE_FIFO(v) BF_CS1(APBH_DEBUG, GPMI_ONE_FIFO, v) +#endif + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CMD_ADDR:32; + } B; +} hw_apbh_chn_curcmdar_t; +#endif + +/* + * constants & macros for entire HW_APBH_CHn_CURCMDAR multi-register + */ +#define HW_APBH_CHn_CURCMDAR_COUNT 16 +#define HW_APBH_CHn_CURCMDAR_ADDR(n) (0x110100 + ((n) * 0x70)) + +#ifndef __LANGUAGE_ASM__ +#define HW_APBH_CHn_CURCMDAR(n) (*(volatile hw_apbh_chn_curcmdar_t *) HW_APBH_CHn_CURCMDAR_ADDR(n)) +#define HW_APBH_CHn_CURCMDAR_RD(n) (HW_APBH_CHn_CURCMDAR(n).U) +#endif + +/* + * constants & macros for individual HW_APBH_CHn_CURCMDAR multi-register bitfields + */ +/* --- Register HW_APBH_CHn_CURCMDAR, field CMD_ADDR */ + +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) ((reg32_t) v) +#else +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) +#endif + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CMD_ADDR:32; + } B; +} hw_apbh_chn_nxtcmdar_t; +#endif + +/* + * constants & macros for entire HW_APBH_CHn_NXTCMDAR multi-register + */ +#define HW_APBH_CHn_NXTCMDAR_COUNT 16 +#define HW_APBH_CHn_NXTCMDAR_ADDR(n) (0x110110 + ((n) * 0x70)) + +#ifndef __LANGUAGE_ASM__ +#define HW_APBH_CHn_NXTCMDAR(n) (*(volatile hw_apbh_chn_nxtcmdar_t *) HW_APBH_CHn_NXTCMDAR_ADDR(n)) +#define HW_APBH_CHn_NXTCMDAR_RD(n) (HW_APBH_CHn_NXTCMDAR(n).U) +#define HW_APBH_CHn_NXTCMDAR_WR(n, v) (HW_APBH_CHn_NXTCMDAR(n).U = (v)) +#define HW_APBH_CHn_NXTCMDAR_SET(n, v) (HW_APBH_CHn_NXTCMDAR_WR(n, HW_APBH_CHn_NXTCMDAR_RD(n) | (v))) +#define HW_APBH_CHn_NXTCMDAR_CLR(n, v) (HW_APBH_CHn_NXTCMDAR_WR(n, HW_APBH_CHn_NXTCMDAR_RD(n) & ~(v))) +#define HW_APBH_CHn_NXTCMDAR_TOG(n, v) (HW_APBH_CHn_NXTCMDAR_WR(n, HW_APBH_CHn_NXTCMDAR_RD(n) ^ (v))) +#endif + +/* + * constants & macros for individual HW_APBH_CHn_NXTCMDAR multi-register bitfields + */ +/* --- Register HW_APBH_CHn_NXTCMDAR, field CMD_ADDR */ + +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) ((reg32_t) v) +#else +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CHn_NXTCMDAR_CMD_ADDR(n, v) (HW_APBH_CHn_NXTCMDAR(n).B.CMD_ADDR = (v)) +#endif + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned COMMAND:2; + unsigned CHAIN:1; + unsigned IRQONCMPLT:1; + unsigned NANDLOCK:1; + unsigned NANDWAIT4READY:1; + unsigned SEMAPHORE:1; + unsigned WAIT4ENDCMD:1; + unsigned HALTONTERMINATE:1; + unsigned RSVD1:3; + unsigned CMDWORDS:4; + unsigned XFER_COUNT:16; + } B; +} hw_apbh_chn_cmd_t; +#endif + +/* + * constants & macros for entire HW_APBH_CHn_CMD multi-register + */ +#define HW_APBH_CHn_CMD_COUNT 16 +#define HW_APBH_CHn_CMD_ADDR(n) (0x110120 + ((n) * 0x70)) + +#ifndef __LANGUAGE_ASM__ +#define HW_APBH_CHn_CMD(n) (*(volatile hw_apbh_chn_cmd_t *) HW_APBH_CHn_CMD_ADDR(n)) +#define HW_APBH_CHn_CMD_RD(n) (HW_APBH_CHn_CMD(n).U) +#endif + +/* + * constants & macros for individual HW_APBH_CHn_CMD multi-register bitfields + */ +/* --- Register HW_APBH_CHn_CMD, field XFER_COUNT */ + +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CHn_CMD_XFER_COUNT(v) ((((reg32_t) v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#else +#define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#endif +/* --- Register HW_APBH_CHn_CMD, field CMDWORDS */ + +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 + +#define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +/* --- Register HW_APBH_CHn_CMD, field RSVD1 */ + +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 + +#define BF_APBH_CHn_CMD_RSVD1(v) (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +/* --- Register HW_APBH_CHn_CMD, field HALTONTERMINATE */ + +#define BP_APBH_CHn_CMD_HALTONTERMINATE 8 +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 + +#define BF_APBH_CHn_CMD_HALTONTERMINATE(v) (((v) << 8) & BM_APBH_CHn_CMD_HALTONTERMINATE) +/* --- Register HW_APBH_CHn_CMD, field WAIT4ENDCMD */ + +#define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 + +#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & BM_APBH_CHn_CMD_WAIT4ENDCMD) +/* --- Register HW_APBH_CHn_CMD, field SEMAPHORE */ + +#define BP_APBH_CHn_CMD_SEMAPHORE 6 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 + +#define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) << 6) & BM_APBH_CHn_CMD_SEMAPHORE) +/* --- Register HW_APBH_CHn_CMD, field NANDWAIT4READY */ + +#define BP_APBH_CHn_CMD_NANDWAIT4READY 5 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 + +#define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) << 5) & BM_APBH_CHn_CMD_NANDWAIT4READY) +/* --- Register HW_APBH_CHn_CMD, field NANDLOCK */ + +#define BP_APBH_CHn_CMD_NANDLOCK 4 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 + +#define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) << 4) & BM_APBH_CHn_CMD_NANDLOCK) +/* --- Register HW_APBH_CHn_CMD, field IRQONCMPLT */ + +#define BP_APBH_CHn_CMD_IRQONCMPLT 3 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 + +#define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & BM_APBH_CHn_CMD_IRQONCMPLT) +/* --- Register HW_APBH_CHn_CMD, field CHAIN */ + +#define BP_APBH_CHn_CMD_CHAIN 2 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 + +#define BF_APBH_CHn_CMD_CHAIN(v) (((v) << 2) & BM_APBH_CHn_CMD_CHAIN) +/* --- Register HW_APBH_CHn_CMD, field COMMAND */ + +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 + +#define BF_APBH_CHn_CMD_COMMAND(v) (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 + +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ADDRESS:32; + } B; +} hw_apbh_chn_bar_t; +#endif + +/* + * constants & macros for entire HW_APBH_CHn_BAR multi-register + */ +#define HW_APBH_CHn_BAR_COUNT 16 +#define HW_APBH_CHn_BAR_ADDR(n) (0x110130 + ((n) * 0x70)) + +#ifndef __LANGUAGE_ASM__ +#define HW_APBH_CHn_BAR(n) (*(volatile hw_apbh_chn_bar_t *) HW_APBH_CHn_BAR_ADDR(n)) +#define HW_APBH_CHn_BAR_RD(n) (HW_APBH_CHn_BAR(n).U) +#endif + +/* + * constants & macros for individual HW_APBH_CHn_BAR multi-register bitfields + */ +/* --- Register HW_APBH_CHn_BAR, field ADDRESS */ + +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CHn_BAR_ADDRESS(v) ((reg32_t) v) +#else +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) +#endif + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned INCREMENT_SEMA:8; + unsigned RSVD1:8; + unsigned PHORE:8; + unsigned RSVD2:8; + } B; +} hw_apbh_chn_sema_t; +#endif + +/* + * constants & macros for entire HW_APBH_CHn_SEMA multi-register + */ +#define HW_APBH_CHn_SEMA_COUNT 16 +#define HW_APBH_CHn_SEMA_ADDR(n) (0x110140 + ((n) * 0x70)) + +#ifndef __LANGUAGE_ASM__ +#define HW_APBH_CHn_SEMA(n) (*(volatile hw_apbh_chn_sema_t *) HW_APBH_CHn_SEMA_ADDR(n)) +#define HW_APBH_CHn_SEMA_RD(n) (HW_APBH_CHn_SEMA(n).U) +#define HW_APBH_CHn_SEMA_WR(n, v) (HW_APBH_CHn_SEMA(n).U = (v)) +#define HW_APBH_CHn_SEMA_SET(n, v) (HW_APBH_CHn_SEMA_WR(n, HW_APBH_CHn_SEMA_RD(n) | (v))) +#define HW_APBH_CHn_SEMA_CLR(n, v) (HW_APBH_CHn_SEMA_WR(n, HW_APBH_CHn_SEMA_RD(n) & ~(v))) +#define HW_APBH_CHn_SEMA_TOG(n, v) (HW_APBH_CHn_SEMA_WR(n, HW_APBH_CHn_SEMA_RD(n) ^ (v))) +#endif + +/* + * constants & macros for individual HW_APBH_CHn_SEMA multi-register bitfields + */ +/* --- Register HW_APBH_CHn_SEMA, field RSVD2 */ + +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CHn_SEMA_RSVD2(v) ((((reg32_t) v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#else +#define BF_APBH_CHn_SEMA_RSVD2(v) (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#endif +/* --- Register HW_APBH_CHn_SEMA, field PHORE */ + +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 + +#define BF_APBH_CHn_SEMA_PHORE(v) (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +/* --- Register HW_APBH_CHn_SEMA, field RSVD1 */ + +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 + +#define BF_APBH_CHn_SEMA_RSVD1(v) (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +/* --- Register HW_APBH_CHn_SEMA, field INCREMENT_SEMA */ + +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF + +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) +#ifndef __LANGUAGE_ASM__ +#define BW_APBH_CHn_SEMA_INCREMENT_SEMA(n, v) (HW_APBH_CHn_SEMA(n).B.INCREMENT_SEMA = (v)) +#endif + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned STATEMACHINE:5; + unsigned RSVD1:15; + unsigned WR_FIFO_FULL:1; + unsigned WR_FIFO_EMPTY:1; + unsigned RD_FIFO_FULL:1; + unsigned RD_FIFO_EMPTY:1; + unsigned NEXTCMDADDRVALID:1; + unsigned LOCK:1; + unsigned READY:1; + unsigned SENSE:1; + unsigned END:1; + unsigned KICK:1; + unsigned BURST:1; + unsigned REQ:1; + } B; +} hw_apbh_chn_debug1_t; +#endif + +/* + * constants & macros for entire HW_APBH_CHn_DEBUG1 multi-register + */ +#define HW_APBH_CHn_DEBUG1_COUNT 16 +#define HW_APBH_CHn_DEBUG1_ADDR(n) (0x110150 + ((n) * 0x70)) + +#ifndef __LANGUAGE_ASM__ +#define HW_APBH_CHn_DEBUG1(n) (*(volatile hw_apbh_chn_debug1_t *) HW_APBH_CHn_DEBUG1_ADDR(n)) +#define HW_APBH_CHn_DEBUG1_RD(n) (HW_APBH_CHn_DEBUG1(n).U) +#endif + +/* + * constants & macros for individual HW_APBH_CHn_DEBUG1 multi-register bitfields + */ +/* --- Register HW_APBH_CHn_DEBUG1, field REQ */ + +#define BP_APBH_CHn_DEBUG1_REQ 31 +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CHn_DEBUG1_REQ(v) ((((reg32_t) v) << 31) & BM_APBH_CHn_DEBUG1_REQ) +#else +#define BF_APBH_CHn_DEBUG1_REQ(v) (((v) << 31) & BM_APBH_CHn_DEBUG1_REQ) +#endif +/* --- Register HW_APBH_CHn_DEBUG1, field BURST */ + +#define BP_APBH_CHn_DEBUG1_BURST 30 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 + +#define BF_APBH_CHn_DEBUG1_BURST(v) (((v) << 30) & BM_APBH_CHn_DEBUG1_BURST) +/* --- Register HW_APBH_CHn_DEBUG1, field KICK */ + +#define BP_APBH_CHn_DEBUG1_KICK 29 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 + +#define BF_APBH_CHn_DEBUG1_KICK(v) (((v) << 29) & BM_APBH_CHn_DEBUG1_KICK) +/* --- Register HW_APBH_CHn_DEBUG1, field END */ + +#define BP_APBH_CHn_DEBUG1_END 28 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 + +#define BF_APBH_CHn_DEBUG1_END(v) (((v) << 28) & BM_APBH_CHn_DEBUG1_END) +/* --- Register HW_APBH_CHn_DEBUG1, field SENSE */ + +#define BP_APBH_CHn_DEBUG1_SENSE 27 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 + +#define BF_APBH_CHn_DEBUG1_SENSE(v) (((v) << 27) & BM_APBH_CHn_DEBUG1_SENSE) +/* --- Register HW_APBH_CHn_DEBUG1, field READY */ + +#define BP_APBH_CHn_DEBUG1_READY 26 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 + +#define BF_APBH_CHn_DEBUG1_READY(v) (((v) << 26) & BM_APBH_CHn_DEBUG1_READY) +/* --- Register HW_APBH_CHn_DEBUG1, field LOCK */ + +#define BP_APBH_CHn_DEBUG1_LOCK 25 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 + +#define BF_APBH_CHn_DEBUG1_LOCK(v) (((v) << 25) & BM_APBH_CHn_DEBUG1_LOCK) +/* --- Register HW_APBH_CHn_DEBUG1, field NEXTCMDADDRVALID */ + +#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 24 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 + +#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID) +/* --- Register HW_APBH_CHn_DEBUG1, field RD_FIFO_EMPTY */ + +#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 23 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 + +#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY) +/* --- Register HW_APBH_CHn_DEBUG1, field RD_FIFO_FULL */ + +#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL 22 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 + +#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & BM_APBH_CHn_DEBUG1_RD_FIFO_FULL) +/* --- Register HW_APBH_CHn_DEBUG1, field WR_FIFO_EMPTY */ + +#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 21 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 + +#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY) +/* --- Register HW_APBH_CHn_DEBUG1, field WR_FIFO_FULL */ + +#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL 20 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 + +#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & BM_APBH_CHn_DEBUG1_WR_FIFO_FULL) +/* --- Register HW_APBH_CHn_DEBUG1, field RSVD1 */ + +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 + +#define BF_APBH_CHn_DEBUG1_RSVD1(v) (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +/* --- Register HW_APBH_CHn_DEBUG1, field STATEMACHINE */ + +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F + +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_READY 0x1F + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned AHB_BYTES:16; + unsigned APB_BYTES:16; + } B; +} hw_apbh_chn_debug2_t; +#endif + +/* + * constants & macros for entire HW_APBH_CHn_DEBUG2 multi-register + */ +#define HW_APBH_CHn_DEBUG2_COUNT 16 +#define HW_APBH_CHn_DEBUG2_ADDR(n) (0x110160 + ((n) * 0x70)) + +#ifndef __LANGUAGE_ASM__ +#define HW_APBH_CHn_DEBUG2(n) (*(volatile hw_apbh_chn_debug2_t *) HW_APBH_CHn_DEBUG2_ADDR(n)) +#define HW_APBH_CHn_DEBUG2_RD(n) (HW_APBH_CHn_DEBUG2(n).U) +#endif + +/* + * constants & macros for individual HW_APBH_CHn_DEBUG2 multi-register bitfields + */ +/* --- Register HW_APBH_CHn_DEBUG2, field APB_BYTES */ + +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) ((((reg32_t) v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#else +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#endif +/* --- Register HW_APBH_CHn_DEBUG2, field AHB_BYTES */ + +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF + +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +/* + * HW_APBH_VERSION - APBH Bridge Version Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned STEP:16; + unsigned MINOR:8; + unsigned MAJOR:8; + } B; +} hw_apbh_version_t; +#endif + +/* + * constants & macros for entire HW_APBH_VERSION register + */ +#define HW_APBH_VERSION_ADDR (0x00110800) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_APBH_VERSION (*(volatile hw_apbh_version_t *) HW_APBH_VERSION_ADDR) +#define HW_APBH_VERSION_RD() (HW_APBH_VERSION.U) +#else +#define HW_APBH_VERSION_RD() (_rbase->mem32_read(HW_APBH_VERSION_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_APBH_VERSION bitfields + */ +/* --- Register HW_APBH_VERSION, field MAJOR */ + +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_APBH_VERSION_MAJOR(v) ((((reg32_t) v) << 24) & BM_APBH_VERSION_MAJOR) +#else +#define BF_APBH_VERSION_MAJOR(v) (((v) << 24) & BM_APBH_VERSION_MAJOR) +#endif +/* --- Register HW_APBH_VERSION, field MINOR */ + +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 + +#define BF_APBH_VERSION_MINOR(v) (((v) << 16) & BM_APBH_VERSION_MINOR) +/* --- Register HW_APBH_VERSION, field STEP */ + +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF + +#define BF_APBH_VERSION_STEP(v) (((v) << 0) & BM_APBH_VERSION_STEP) + +#endif /* _APBH_H */ + +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/mx6ul/regsbch.h b/bsp/imx6ul/platform/include/mx6ul/regsbch.h new file mode 100644 index 0000000000000000000000000000000000000000..1aef875d3759368b8ff44df5cb00adb635315ef6 --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/regsbch.h @@ -0,0 +1,2087 @@ +/* + * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. + */ + +#ifndef _BCH_H +#define _BCH_H 1 + +#include "regs.h" +//#include "registers.h" + +#ifndef REGS_BCH_BASE +#define REGS_BCH_BASE (REGS_BASE + 0x114000) +#endif + +/* + * HW_BCH_CTRL - Hardware BCH ECC Accelerator Control Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned COMPLETE_IRQ:1; + unsigned RSVD0:1; + unsigned DEBUG_STALL_IRQ:1; + unsigned BM_ERROR_IRQ:1; + unsigned RSVD1:4; + unsigned COMPLETE_IRQ_EN:1; + unsigned RSVD2:1; + unsigned DEBUG_STALL_IRQ_EN:1; + unsigned RSVD3:5; + unsigned M2M_ENABLE:1; + unsigned M2M_ENCODE:1; + unsigned M2M_LAYOUT:2; + unsigned RSVD4:2; + unsigned DEBUGSYNDROME:1; + unsigned RSVD5:7; + unsigned CLKGATE:1; + unsigned SFTRST:1; + } B; +} hw_bch_ctrl_t; +#endif + +/* + * constants & macros for entire HW_BCH_CTRL register + */ +#define HW_BCH_CTRL_ADDR (0x00114000) +#define HW_BCH_CTRL_SET_ADDR (0x00114004) +#define HW_BCH_CTRL_CLR_ADDR (0x00114008) +#define HW_BCH_CTRL_TOG_ADDR (0x0011400c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_CTRL (*(volatile hw_bch_ctrl_t *) HW_BCH_CTRL_ADDR) +#define HW_BCH_CTRL_RD() (HW_BCH_CTRL.U) +#define HW_BCH_CTRL_WR(v) (HW_BCH_CTRL.U = (v)) +#define HW_BCH_CTRL_SET(v) ((*(volatile reg32_t *) HW_BCH_CTRL_SET_ADDR) = (v)) +#define HW_BCH_CTRL_CLR(v) ((*(volatile reg32_t *) HW_BCH_CTRL_CLR_ADDR) = (v)) +#define HW_BCH_CTRL_TOG(v) ((*(volatile reg32_t *) HW_BCH_CTRL_TOG_ADDR) = (v)) +#else +#define HW_BCH_CTRL_RD() (_rbase->mem32_read(HW_BCH_CTRL_ADDR)) +#define HW_BCH_CTRL_WR(v) (_rbase->mem32_write(HW_BCH_CTRL_ADDR,(v))) +#define HW_BCH_CTRL_SET(v) (_rbase->mem32_write(HW_BCH_CTRL_SET_ADDR,(v))) +#define HW_BCH_CTRL_CLR(v) (_rbase->mem32_write(HW_BCH_CTRL_CLR_ADDR,(v))) +#define HW_BCH_CTRL_TOG(v) (_rbase->mem32_write(HW_BCH_CTRL_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_CTRL bitfields + */ +/* --- Register HW_BCH_CTRL, field SFTRST */ + +#define BP_BCH_CTRL_SFTRST 31 +#define BM_BCH_CTRL_SFTRST 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_CTRL_SFTRST(v) ((((reg32_t) v) << 31) & BM_BCH_CTRL_SFTRST) +#else +#define BF_BCH_CTRL_SFTRST(v) (((v) << 31) & BM_BCH_CTRL_SFTRST) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_SFTRST(v) BF_CS1(BCH_CTRL, SFTRST, v) +#endif + +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 + +/* --- Register HW_BCH_CTRL, field CLKGATE */ + +#define BP_BCH_CTRL_CLKGATE 30 +#define BM_BCH_CTRL_CLKGATE 0x40000000 + +#define BF_BCH_CTRL_CLKGATE(v) (((v) << 30) & BM_BCH_CTRL_CLKGATE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_CLKGATE(v) BF_CS1(BCH_CTRL, CLKGATE, v) +#endif + +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 + +/* --- Register HW_BCH_CTRL, field RSVD5 */ + +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3F800000 + +#define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & BM_BCH_CTRL_RSVD5) +/* --- Register HW_BCH_CTRL, field DEBUGSYNDROME */ + +#define BP_BCH_CTRL_DEBUGSYNDROME 22 +#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 + +#define BF_BCH_CTRL_DEBUGSYNDROME(v) (((v) << 22) & BM_BCH_CTRL_DEBUGSYNDROME) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_DEBUGSYNDROME(v) BF_CS1(BCH_CTRL, DEBUGSYNDROME, v) +#endif + +/* --- Register HW_BCH_CTRL, field RSVD4 */ + +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x00300000 + +#define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & BM_BCH_CTRL_RSVD4) +/* --- Register HW_BCH_CTRL, field M2M_LAYOUT */ + +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 + +#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_M2M_LAYOUT(v) BF_CS1(BCH_CTRL, M2M_LAYOUT, v) +#endif + +/* --- Register HW_BCH_CTRL, field M2M_ENCODE */ + +#define BP_BCH_CTRL_M2M_ENCODE 17 +#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 + +#define BF_BCH_CTRL_M2M_ENCODE(v) (((v) << 17) & BM_BCH_CTRL_M2M_ENCODE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_M2M_ENCODE(v) BF_CS1(BCH_CTRL, M2M_ENCODE, v) +#endif + +/* --- Register HW_BCH_CTRL, field M2M_ENABLE */ + +#define BP_BCH_CTRL_M2M_ENABLE 16 +#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 + +#define BF_BCH_CTRL_M2M_ENABLE(v) (((v) << 16) & BM_BCH_CTRL_M2M_ENABLE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_M2M_ENABLE(v) BF_CS1(BCH_CTRL, M2M_ENABLE, v) +#endif + +/* --- Register HW_BCH_CTRL, field RSVD3 */ + +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0x0000F800 + +#define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & BM_BCH_CTRL_RSVD3) +/* --- Register HW_BCH_CTRL, field DEBUG_STALL_IRQ_EN */ + +#define BP_BCH_CTRL_DEBUG_STALL_IRQ_EN 10 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 + +#define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(v) (((v) << 10) & BM_BCH_CTRL_DEBUG_STALL_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_DEBUG_STALL_IRQ_EN(v) BF_CS1(BCH_CTRL, DEBUG_STALL_IRQ_EN, v) +#endif + +/* --- Register HW_BCH_CTRL, field RSVD2 */ + +#define BP_BCH_CTRL_RSVD2 9 +#define BM_BCH_CTRL_RSVD2 0x00000200 + +#define BF_BCH_CTRL_RSVD2(v) (((v) << 9) & BM_BCH_CTRL_RSVD2) +/* --- Register HW_BCH_CTRL, field COMPLETE_IRQ_EN */ + +#define BP_BCH_CTRL_COMPLETE_IRQ_EN 8 +#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 + +#define BF_BCH_CTRL_COMPLETE_IRQ_EN(v) (((v) << 8) & BM_BCH_CTRL_COMPLETE_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_COMPLETE_IRQ_EN(v) BF_CS1(BCH_CTRL, COMPLETE_IRQ_EN, v) +#endif + +/* --- Register HW_BCH_CTRL, field RSVD1 */ + +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0x000000F0 + +#define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & BM_BCH_CTRL_RSVD1) +/* --- Register HW_BCH_CTRL, field BM_ERROR_IRQ */ + +#define BP_BCH_CTRL_BM_ERROR_IRQ 3 +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 + +#define BF_BCH_CTRL_BM_ERROR_IRQ(v) (((v) << 3) & BM_BCH_CTRL_BM_ERROR_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_BM_ERROR_IRQ(v) BF_CS1(BCH_CTRL, BM_ERROR_IRQ, v) +#endif + +/* --- Register HW_BCH_CTRL, field DEBUG_STALL_IRQ */ + +#define BP_BCH_CTRL_DEBUG_STALL_IRQ 2 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 + +#define BF_BCH_CTRL_DEBUG_STALL_IRQ(v) (((v) << 2) & BM_BCH_CTRL_DEBUG_STALL_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_DEBUG_STALL_IRQ(v) BF_CS1(BCH_CTRL, DEBUG_STALL_IRQ, v) +#endif + +/* --- Register HW_BCH_CTRL, field RSVD0 */ + +#define BP_BCH_CTRL_RSVD0 1 +#define BM_BCH_CTRL_RSVD0 0x00000002 + +#define BF_BCH_CTRL_RSVD0(v) (((v) << 1) & BM_BCH_CTRL_RSVD0) +/* --- Register HW_BCH_CTRL, field COMPLETE_IRQ */ + +#define BP_BCH_CTRL_COMPLETE_IRQ 0 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 + +#define BF_BCH_CTRL_COMPLETE_IRQ(v) (((v) << 0) & BM_BCH_CTRL_COMPLETE_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_CTRL_COMPLETE_IRQ(v) BF_CS1(BCH_CTRL, COMPLETE_IRQ, v) +#endif + +/* + * HW_BCH_STATUS0 - Hardware ECC Accelerator Status Register 0 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RSVD0:2; + unsigned UNCORRECTABLE:1; + unsigned CORRECTED:1; + unsigned ALLONES:1; + unsigned RSVD1:3; + unsigned STATUS_BLK0:8; + unsigned COMPLETED_CE:4; + unsigned HANDLE:12; + } B; +} hw_bch_status0_t; +#endif + +/* + * constants & macros for entire HW_BCH_STATUS0 register + */ +#define HW_BCH_STATUS0_ADDR (0x00114010) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_STATUS0 (*(volatile hw_bch_status0_t *) HW_BCH_STATUS0_ADDR) +#define HW_BCH_STATUS0_RD() (HW_BCH_STATUS0.U) +#else +#define HW_BCH_STATUS0_RD() (_rbase->mem32_read(HW_BCH_STATUS0_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_STATUS0 bitfields + */ +/* --- Register HW_BCH_STATUS0, field HANDLE */ + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xFFF00000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_STATUS0_HANDLE(v) ((((reg32_t) v) << 20) & BM_BCH_STATUS0_HANDLE) +#else +#define BF_BCH_STATUS0_HANDLE(v) (((v) << 20) & BM_BCH_STATUS0_HANDLE) +#endif +/* --- Register HW_BCH_STATUS0, field COMPLETED_CE */ + +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 + +#define BF_BCH_STATUS0_COMPLETED_CE(v) (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) +/* --- Register HW_BCH_STATUS0, field STATUS_BLK0 */ + +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 + +#define BF_BCH_STATUS0_STATUS_BLK0(v) (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF + +/* --- Register HW_BCH_STATUS0, field RSVD1 */ + +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0x000000E0 + +#define BF_BCH_STATUS0_RSVD1(v) (((v) << 5) & BM_BCH_STATUS0_RSVD1) +/* --- Register HW_BCH_STATUS0, field ALLONES */ + +#define BP_BCH_STATUS0_ALLONES 4 +#define BM_BCH_STATUS0_ALLONES 0x00000010 + +#define BF_BCH_STATUS0_ALLONES(v) (((v) << 4) & BM_BCH_STATUS0_ALLONES) +/* --- Register HW_BCH_STATUS0, field CORRECTED */ + +#define BP_BCH_STATUS0_CORRECTED 3 +#define BM_BCH_STATUS0_CORRECTED 0x00000008 + +#define BF_BCH_STATUS0_CORRECTED(v) (((v) << 3) & BM_BCH_STATUS0_CORRECTED) +/* --- Register HW_BCH_STATUS0, field UNCORRECTABLE */ + +#define BP_BCH_STATUS0_UNCORRECTABLE 2 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 + +#define BF_BCH_STATUS0_UNCORRECTABLE(v) (((v) << 2) & BM_BCH_STATUS0_UNCORRECTABLE) +/* --- Register HW_BCH_STATUS0, field RSVD0 */ + +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x00000003 + +#define BF_BCH_STATUS0_RSVD0(v) (((v) << 0) & BM_BCH_STATUS0_RSVD0) + +/* + * HW_BCH_MODE - Hardware ECC Accelerator Mode Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ERASE_THRESHOLD:8; + unsigned RSVD:24; + } B; +} hw_bch_mode_t; +#endif + +/* + * constants & macros for entire HW_BCH_MODE register + */ +#define HW_BCH_MODE_ADDR (0x00114020) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_MODE (*(volatile hw_bch_mode_t *) HW_BCH_MODE_ADDR) +#define HW_BCH_MODE_RD() (HW_BCH_MODE.U) +#define HW_BCH_MODE_WR(v) (HW_BCH_MODE.U = (v)) +#define HW_BCH_MODE_SET(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() | (v))) +#define HW_BCH_MODE_CLR(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() & ~(v))) +#define HW_BCH_MODE_TOG(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() ^ (v))) +#else +#define HW_BCH_MODE_RD() (_rbase->mem32_read(HW_BCH_MODE_ADDR)) +#define HW_BCH_MODE_WR(v) (_rbase->mem32_write(HW_BCH_MODE_ADDR,(v))) +#define HW_BCH_MODE_SET(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() | (v))) +#define HW_BCH_MODE_CLR(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() & ~(v))) +#define HW_BCH_MODE_TOG(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_MODE bitfields + */ +/* --- Register HW_BCH_MODE, field RSVD */ + +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xFFFFFF00 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_MODE_RSVD(v) ((((reg32_t) v) << 8) & BM_BCH_MODE_RSVD) +#else +#define BF_BCH_MODE_RSVD(v) (((v) << 8) & BM_BCH_MODE_RSVD) +#endif +/* --- Register HW_BCH_MODE, field ERASE_THRESHOLD */ + +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF + +#define BF_BCH_MODE_ERASE_THRESHOLD(v) (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_MODE_ERASE_THRESHOLD(v) (HW_BCH_MODE.B.ERASE_THRESHOLD = (v)) +#endif + +/* + * HW_BCH_ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ADDR:32; + } B; +} hw_bch_encodeptr_t; +#endif + +/* + * constants & macros for entire HW_BCH_ENCODEPTR register + */ +#define HW_BCH_ENCODEPTR_ADDR (0x00114030) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_ENCODEPTR (*(volatile hw_bch_encodeptr_t *) HW_BCH_ENCODEPTR_ADDR) +#define HW_BCH_ENCODEPTR_RD() (HW_BCH_ENCODEPTR.U) +#define HW_BCH_ENCODEPTR_WR(v) (HW_BCH_ENCODEPTR.U = (v)) +#define HW_BCH_ENCODEPTR_SET(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() | (v))) +#define HW_BCH_ENCODEPTR_CLR(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() & ~(v))) +#define HW_BCH_ENCODEPTR_TOG(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() ^ (v))) +#else +#define HW_BCH_ENCODEPTR_RD() (_rbase->mem32_read(HW_BCH_ENCODEPTR_ADDR)) +#define HW_BCH_ENCODEPTR_WR(v) (_rbase->mem32_write(HW_BCH_ENCODEPTR_ADDR,(v))) +#define HW_BCH_ENCODEPTR_SET(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() | (v))) +#define HW_BCH_ENCODEPTR_CLR(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() & ~(v))) +#define HW_BCH_ENCODEPTR_TOG(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_ENCODEPTR bitfields + */ +/* --- Register HW_BCH_ENCODEPTR, field ADDR */ + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_ENCODEPTR_ADDR(v) ((reg32_t) v) +#else +#define BF_BCH_ENCODEPTR_ADDR(v) (v) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_ENCODEPTR_ADDR(v) (HW_BCH_ENCODEPTR.B.ADDR = (v)) +#endif + +/* + * HW_BCH_DATAPTR - Hardware BCH ECC Loopback Data Buffer Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ADDR:32; + } B; +} hw_bch_dataptr_t; +#endif + +/* + * constants & macros for entire HW_BCH_DATAPTR register + */ +#define HW_BCH_DATAPTR_ADDR (0x00114040) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_DATAPTR (*(volatile hw_bch_dataptr_t *) HW_BCH_DATAPTR_ADDR) +#define HW_BCH_DATAPTR_RD() (HW_BCH_DATAPTR.U) +#define HW_BCH_DATAPTR_WR(v) (HW_BCH_DATAPTR.U = (v)) +#define HW_BCH_DATAPTR_SET(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() | (v))) +#define HW_BCH_DATAPTR_CLR(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() & ~(v))) +#define HW_BCH_DATAPTR_TOG(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() ^ (v))) +#else +#define HW_BCH_DATAPTR_RD() (_rbase->mem32_read(HW_BCH_DATAPTR_ADDR)) +#define HW_BCH_DATAPTR_WR(v) (_rbase->mem32_write(HW_BCH_DATAPTR_ADDR,(v))) +#define HW_BCH_DATAPTR_SET(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() | (v))) +#define HW_BCH_DATAPTR_CLR(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() & ~(v))) +#define HW_BCH_DATAPTR_TOG(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_DATAPTR bitfields + */ +/* --- Register HW_BCH_DATAPTR, field ADDR */ + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_DATAPTR_ADDR(v) ((reg32_t) v) +#else +#define BF_BCH_DATAPTR_ADDR(v) (v) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DATAPTR_ADDR(v) (HW_BCH_DATAPTR.B.ADDR = (v)) +#endif + +/* + * HW_BCH_METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ADDR:32; + } B; +} hw_bch_metaptr_t; +#endif + +/* + * constants & macros for entire HW_BCH_METAPTR register + */ +#define HW_BCH_METAPTR_ADDR (0x00114050) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_METAPTR (*(volatile hw_bch_metaptr_t *) HW_BCH_METAPTR_ADDR) +#define HW_BCH_METAPTR_RD() (HW_BCH_METAPTR.U) +#define HW_BCH_METAPTR_WR(v) (HW_BCH_METAPTR.U = (v)) +#define HW_BCH_METAPTR_SET(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() | (v))) +#define HW_BCH_METAPTR_CLR(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() & ~(v))) +#define HW_BCH_METAPTR_TOG(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() ^ (v))) +#else +#define HW_BCH_METAPTR_RD() (_rbase->mem32_read(HW_BCH_METAPTR_ADDR)) +#define HW_BCH_METAPTR_WR(v) (_rbase->mem32_write(HW_BCH_METAPTR_ADDR,(v))) +#define HW_BCH_METAPTR_SET(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() | (v))) +#define HW_BCH_METAPTR_CLR(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() & ~(v))) +#define HW_BCH_METAPTR_TOG(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_METAPTR bitfields + */ +/* --- Register HW_BCH_METAPTR, field ADDR */ + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_METAPTR_ADDR(v) ((reg32_t) v) +#else +#define BF_BCH_METAPTR_ADDR(v) (v) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_METAPTR_ADDR(v) (HW_BCH_METAPTR.B.ADDR = (v)) +#endif + +/* + * HW_BCH_LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CS0_SELECT:2; + unsigned CS1_SELECT:2; + unsigned CS2_SELECT:2; + unsigned CS3_SELECT:2; + unsigned CS4_SELECT:2; + unsigned CS5_SELECT:2; + unsigned CS6_SELECT:2; + unsigned CS7_SELECT:2; + unsigned CS8_SELECT:2; + unsigned CS9_SELECT:2; + unsigned CS10_SELECT:2; + unsigned CS11_SELECT:2; + unsigned CS12_SELECT:2; + unsigned CS13_SELECT:2; + unsigned CS14_SELECT:2; + unsigned CS15_SELECT:2; + } B; +} hw_bch_layoutselect_t; +#endif + +/* + * constants & macros for entire HW_BCH_LAYOUTSELECT register + */ +#define HW_BCH_LAYOUTSELECT_ADDR (0x00114070) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_LAYOUTSELECT (*(volatile hw_bch_layoutselect_t *) HW_BCH_LAYOUTSELECT_ADDR) +#define HW_BCH_LAYOUTSELECT_RD() (HW_BCH_LAYOUTSELECT.U) +#define HW_BCH_LAYOUTSELECT_WR(v) (HW_BCH_LAYOUTSELECT.U = (v)) +#define HW_BCH_LAYOUTSELECT_SET(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() | (v))) +#define HW_BCH_LAYOUTSELECT_CLR(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() & ~(v))) +#define HW_BCH_LAYOUTSELECT_TOG(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() ^ (v))) +#else +#define HW_BCH_LAYOUTSELECT_RD() (_rbase->mem32_read(HW_BCH_LAYOUTSELECT_ADDR)) +#define HW_BCH_LAYOUTSELECT_WR(v) (_rbase->mem32_write(HW_BCH_LAYOUTSELECT_ADDR,(v))) +#define HW_BCH_LAYOUTSELECT_SET(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() | (v))) +#define HW_BCH_LAYOUTSELECT_CLR(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() & ~(v))) +#define HW_BCH_LAYOUTSELECT_TOG(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_LAYOUTSELECT bitfields + */ +/* --- Register HW_BCH_LAYOUTSELECT, field CS15_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) ((((reg32_t) v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#else +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS15_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS15_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS14_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 + +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS14_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS14_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS13_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 + +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS13_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS13_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS12_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 + +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS12_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS12_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS11_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 + +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS11_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS11_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS10_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 + +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS10_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS10_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS9_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 + +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS9_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS9_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS8_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 + +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS8_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS8_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS7_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 + +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS7_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS7_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS6_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 + +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS6_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS6_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS5_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 + +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS5_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS5_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS4_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 + +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS4_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS4_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS3_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 + +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS3_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS3_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS2_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 + +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS2_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS2_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS1_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C + +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS1_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS1_SELECT, v) +#endif + +/* --- Register HW_BCH_LAYOUTSELECT, field CS0_SELECT */ + +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 + +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_LAYOUTSELECT_CS0_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS0_SELECT, v) +#endif + +/* + * HW_BCH_FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA0_SIZE:10; + unsigned GF13_0_GF14_1:1; + unsigned ECC0:5; + unsigned META_SIZE:8; + unsigned NBLOCKS:8; + } B; +} hw_bch_flash0layout0_t; +#endif + +/* + * constants & macros for entire HW_BCH_FLASH0LAYOUT0 register + */ +#define HW_BCH_FLASH0LAYOUT0_ADDR (0x00114080) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_FLASH0LAYOUT0 (*(volatile hw_bch_flash0layout0_t *) HW_BCH_FLASH0LAYOUT0_ADDR) +#define HW_BCH_FLASH0LAYOUT0_RD() (HW_BCH_FLASH0LAYOUT0.U) +#define HW_BCH_FLASH0LAYOUT0_WR(v) (HW_BCH_FLASH0LAYOUT0.U = (v)) +#define HW_BCH_FLASH0LAYOUT0_SET(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() | (v))) +#define HW_BCH_FLASH0LAYOUT0_CLR(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() & ~(v))) +#define HW_BCH_FLASH0LAYOUT0_TOG(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() ^ (v))) +#else +#define HW_BCH_FLASH0LAYOUT0_RD() (_rbase->mem32_read(HW_BCH_FLASH0LAYOUT0_ADDR)) +#define HW_BCH_FLASH0LAYOUT0_WR(v) (_rbase->mem32_write(HW_BCH_FLASH0LAYOUT0_ADDR,(v))) +#define HW_BCH_FLASH0LAYOUT0_SET(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() | (v))) +#define HW_BCH_FLASH0LAYOUT0_CLR(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() & ~(v))) +#define HW_BCH_FLASH0LAYOUT0_TOG(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_FLASH0LAYOUT0 bitfields + */ +/* --- Register HW_BCH_FLASH0LAYOUT0, field NBLOCKS */ + +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) ((((reg32_t) v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#else +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT0_NBLOCKS(v) (HW_BCH_FLASH0LAYOUT0.B.NBLOCKS = (v)) +#endif + +/* --- Register HW_BCH_FLASH0LAYOUT0, field META_SIZE */ + +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 + +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT0_META_SIZE(v) (HW_BCH_FLASH0LAYOUT0.B.META_SIZE = (v)) +#endif + +/* --- Register HW_BCH_FLASH0LAYOUT0, field ECC0 */ + +#define BP_BCH_FLASH0LAYOUT0_ECC0 11 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F800 + +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) (((v) << 11) & BM_BCH_FLASH0LAYOUT0_ECC0) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT0_ECC0(v) BF_CS1(BCH_FLASH0LAYOUT0, ECC0, v) +#endif + +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC32 0x10 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC34 0x11 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC36 0x12 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC38 0x13 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC40 0x14 + +/* --- Register HW_BCH_FLASH0LAYOUT0, field GF13_0_GF14_1 */ + +#define BP_BCH_FLASH0LAYOUT0_GF13_0_GF14_1 10 +#define BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1 0x00000400 + +#define BF_BCH_FLASH0LAYOUT0_GF13_0_GF14_1(v) (((v) << 10) & BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT0_GF13_0_GF14_1(v) BF_CS1(BCH_FLASH0LAYOUT0, GF13_0_GF14_1, v) +#endif + +/* --- Register HW_BCH_FLASH0LAYOUT0, field DATA0_SIZE */ + +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x000003FF + +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) BF_CS1(BCH_FLASH0LAYOUT0, DATA0_SIZE, v) +#endif + +/* + * HW_BCH_FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATAN_SIZE:10; + unsigned GF13_0_GF14_1:1; + unsigned ECCN:5; + unsigned PAGE_SIZE:16; + } B; +} hw_bch_flash0layout1_t; +#endif + +/* + * constants & macros for entire HW_BCH_FLASH0LAYOUT1 register + */ +#define HW_BCH_FLASH0LAYOUT1_ADDR (0x00114090) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_FLASH0LAYOUT1 (*(volatile hw_bch_flash0layout1_t *) HW_BCH_FLASH0LAYOUT1_ADDR) +#define HW_BCH_FLASH0LAYOUT1_RD() (HW_BCH_FLASH0LAYOUT1.U) +#define HW_BCH_FLASH0LAYOUT1_WR(v) (HW_BCH_FLASH0LAYOUT1.U = (v)) +#define HW_BCH_FLASH0LAYOUT1_SET(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() | (v))) +#define HW_BCH_FLASH0LAYOUT1_CLR(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() & ~(v))) +#define HW_BCH_FLASH0LAYOUT1_TOG(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() ^ (v))) +#else +#define HW_BCH_FLASH0LAYOUT1_RD() (_rbase->mem32_read(HW_BCH_FLASH0LAYOUT1_ADDR)) +#define HW_BCH_FLASH0LAYOUT1_WR(v) (_rbase->mem32_write(HW_BCH_FLASH0LAYOUT1_ADDR,(v))) +#define HW_BCH_FLASH0LAYOUT1_SET(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() | (v))) +#define HW_BCH_FLASH0LAYOUT1_CLR(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() & ~(v))) +#define HW_BCH_FLASH0LAYOUT1_TOG(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_FLASH0LAYOUT1 bitfields + */ +/* --- Register HW_BCH_FLASH0LAYOUT1, field PAGE_SIZE */ + +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) ((((reg32_t) v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#else +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) (HW_BCH_FLASH0LAYOUT1.B.PAGE_SIZE = (v)) +#endif + +/* --- Register HW_BCH_FLASH0LAYOUT1, field ECCN */ + +#define BP_BCH_FLASH0LAYOUT1_ECCN 11 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F800 + +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) (((v) << 11) & BM_BCH_FLASH0LAYOUT1_ECCN) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT1_ECCN(v) BF_CS1(BCH_FLASH0LAYOUT1, ECCN, v) +#endif + +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC32 0x10 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC34 0x11 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC36 0x12 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC38 0x13 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC40 0x14 + +/* --- Register HW_BCH_FLASH0LAYOUT1, field GF13_0_GF14_1 */ + +#define BP_BCH_FLASH0LAYOUT1_GF13_0_GF14_1 10 +#define BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1 0x00000400 + +#define BF_BCH_FLASH0LAYOUT1_GF13_0_GF14_1(v) (((v) << 10) & BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT1_GF13_0_GF14_1(v) BF_CS1(BCH_FLASH0LAYOUT1, GF13_0_GF14_1, v) +#endif + +/* --- Register HW_BCH_FLASH0LAYOUT1, field DATAN_SIZE */ + +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x000003FF + +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) BF_CS1(BCH_FLASH0LAYOUT1, DATAN_SIZE, v) +#endif + +/* + * HW_BCH_FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA0_SIZE:10; + unsigned GF13_0_GF14_1:1; + unsigned ECC0:5; + unsigned META_SIZE:8; + unsigned NBLOCKS:8; + } B; +} hw_bch_flash1layout0_t; +#endif + +/* + * constants & macros for entire HW_BCH_FLASH1LAYOUT0 register + */ +#define HW_BCH_FLASH1LAYOUT0_ADDR (0x001140a0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_FLASH1LAYOUT0 (*(volatile hw_bch_flash1layout0_t *) HW_BCH_FLASH1LAYOUT0_ADDR) +#define HW_BCH_FLASH1LAYOUT0_RD() (HW_BCH_FLASH1LAYOUT0.U) +#define HW_BCH_FLASH1LAYOUT0_WR(v) (HW_BCH_FLASH1LAYOUT0.U = (v)) +#define HW_BCH_FLASH1LAYOUT0_SET(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() | (v))) +#define HW_BCH_FLASH1LAYOUT0_CLR(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() & ~(v))) +#define HW_BCH_FLASH1LAYOUT0_TOG(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() ^ (v))) +#else +#define HW_BCH_FLASH1LAYOUT0_RD() (_rbase->mem32_read(HW_BCH_FLASH1LAYOUT0_ADDR)) +#define HW_BCH_FLASH1LAYOUT0_WR(v) (_rbase->mem32_write(HW_BCH_FLASH1LAYOUT0_ADDR,(v))) +#define HW_BCH_FLASH1LAYOUT0_SET(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() | (v))) +#define HW_BCH_FLASH1LAYOUT0_CLR(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() & ~(v))) +#define HW_BCH_FLASH1LAYOUT0_TOG(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_FLASH1LAYOUT0 bitfields + */ +/* --- Register HW_BCH_FLASH1LAYOUT0, field NBLOCKS */ + +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) ((((reg32_t) v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#else +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT0_NBLOCKS(v) (HW_BCH_FLASH1LAYOUT0.B.NBLOCKS = (v)) +#endif + +/* --- Register HW_BCH_FLASH1LAYOUT0, field META_SIZE */ + +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 + +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT0_META_SIZE(v) (HW_BCH_FLASH1LAYOUT0.B.META_SIZE = (v)) +#endif + +/* --- Register HW_BCH_FLASH1LAYOUT0, field ECC0 */ + +#define BP_BCH_FLASH1LAYOUT0_ECC0 11 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F800 + +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) (((v) << 11) & BM_BCH_FLASH1LAYOUT0_ECC0) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT0_ECC0(v) BF_CS1(BCH_FLASH1LAYOUT0, ECC0, v) +#endif + +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC32 0x10 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC34 0x11 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC36 0x12 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC38 0x13 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC40 0x14 + +/* --- Register HW_BCH_FLASH1LAYOUT0, field GF13_0_GF14_1 */ + +#define BP_BCH_FLASH1LAYOUT0_GF13_0_GF14_1 10 +#define BM_BCH_FLASH1LAYOUT0_GF13_0_GF14_1 0x00000400 + +#define BF_BCH_FLASH1LAYOUT0_GF13_0_GF14_1(v) (((v) << 10) & BM_BCH_FLASH1LAYOUT0_GF13_0_GF14_1) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT0_GF13_0_GF14_1(v) BF_CS1(BCH_FLASH1LAYOUT0, GF13_0_GF14_1, v) +#endif + +/* --- Register HW_BCH_FLASH1LAYOUT0, field DATA0_SIZE */ + +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x000003FF + +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) BF_CS1(BCH_FLASH1LAYOUT0, DATA0_SIZE, v) +#endif + +/* + * HW_BCH_FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATAN_SIZE:10; + unsigned GF13_0_GF14_1:1; + unsigned ECCN:5; + unsigned PAGE_SIZE:16; + } B; +} hw_bch_flash1layout1_t; +#endif + +/* + * constants & macros for entire HW_BCH_FLASH1LAYOUT1 register + */ +#define HW_BCH_FLASH1LAYOUT1_ADDR (0x001140b0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_FLASH1LAYOUT1 (*(volatile hw_bch_flash1layout1_t *) HW_BCH_FLASH1LAYOUT1_ADDR) +#define HW_BCH_FLASH1LAYOUT1_RD() (HW_BCH_FLASH1LAYOUT1.U) +#define HW_BCH_FLASH1LAYOUT1_WR(v) (HW_BCH_FLASH1LAYOUT1.U = (v)) +#define HW_BCH_FLASH1LAYOUT1_SET(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() | (v))) +#define HW_BCH_FLASH1LAYOUT1_CLR(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() & ~(v))) +#define HW_BCH_FLASH1LAYOUT1_TOG(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() ^ (v))) +#else +#define HW_BCH_FLASH1LAYOUT1_RD() (_rbase->mem32_read(HW_BCH_FLASH1LAYOUT1_ADDR)) +#define HW_BCH_FLASH1LAYOUT1_WR(v) (_rbase->mem32_write(HW_BCH_FLASH1LAYOUT1_ADDR,(v))) +#define HW_BCH_FLASH1LAYOUT1_SET(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() | (v))) +#define HW_BCH_FLASH1LAYOUT1_CLR(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() & ~(v))) +#define HW_BCH_FLASH1LAYOUT1_TOG(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_FLASH1LAYOUT1 bitfields + */ +/* --- Register HW_BCH_FLASH1LAYOUT1, field PAGE_SIZE */ + +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) ((((reg32_t) v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#else +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) (HW_BCH_FLASH1LAYOUT1.B.PAGE_SIZE = (v)) +#endif + +/* --- Register HW_BCH_FLASH1LAYOUT1, field ECCN */ + +#define BP_BCH_FLASH1LAYOUT1_ECCN 11 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F800 + +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) (((v) << 11) & BM_BCH_FLASH1LAYOUT1_ECCN) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT1_ECCN(v) BF_CS1(BCH_FLASH1LAYOUT1, ECCN, v) +#endif + +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC32 0x10 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC34 0x11 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC36 0x12 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC38 0x13 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC40 0x14 + +/* --- Register HW_BCH_FLASH1LAYOUT1, field GF13_0_GF14_1 */ + +#define BP_BCH_FLASH1LAYOUT1_GF13_0_GF14_1 10 +#define BM_BCH_FLASH1LAYOUT1_GF13_0_GF14_1 0x00000400 + +#define BF_BCH_FLASH1LAYOUT1_GF13_0_GF14_1(v) (((v) << 10) & BM_BCH_FLASH1LAYOUT1_GF13_0_GF14_1) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT1_GF13_0_GF14_1(v) BF_CS1(BCH_FLASH1LAYOUT1, GF13_0_GF14_1, v) +#endif + +/* --- Register HW_BCH_FLASH1LAYOUT1, field DATAN_SIZE */ + +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x000003FF + +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) BF_CS1(BCH_FLASH1LAYOUT1, DATAN_SIZE, v) +#endif + +/* + * HW_BCH_FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA0_SIZE:10; + unsigned GF13_0_GF14_1:1; + unsigned ECC0:5; + unsigned META_SIZE:8; + unsigned NBLOCKS:8; + } B; +} hw_bch_flash2layout0_t; +#endif + +/* + * constants & macros for entire HW_BCH_FLASH2LAYOUT0 register + */ +#define HW_BCH_FLASH2LAYOUT0_ADDR (0x001140c0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_FLASH2LAYOUT0 (*(volatile hw_bch_flash2layout0_t *) HW_BCH_FLASH2LAYOUT0_ADDR) +#define HW_BCH_FLASH2LAYOUT0_RD() (HW_BCH_FLASH2LAYOUT0.U) +#define HW_BCH_FLASH2LAYOUT0_WR(v) (HW_BCH_FLASH2LAYOUT0.U = (v)) +#define HW_BCH_FLASH2LAYOUT0_SET(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() | (v))) +#define HW_BCH_FLASH2LAYOUT0_CLR(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() & ~(v))) +#define HW_BCH_FLASH2LAYOUT0_TOG(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() ^ (v))) +#else +#define HW_BCH_FLASH2LAYOUT0_RD() (_rbase->mem32_read(HW_BCH_FLASH2LAYOUT0_ADDR)) +#define HW_BCH_FLASH2LAYOUT0_WR(v) (_rbase->mem32_write(HW_BCH_FLASH2LAYOUT0_ADDR,(v))) +#define HW_BCH_FLASH2LAYOUT0_SET(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() | (v))) +#define HW_BCH_FLASH2LAYOUT0_CLR(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() & ~(v))) +#define HW_BCH_FLASH2LAYOUT0_TOG(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_FLASH2LAYOUT0 bitfields + */ +/* --- Register HW_BCH_FLASH2LAYOUT0, field NBLOCKS */ + +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) ((((reg32_t) v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#else +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT0_NBLOCKS(v) (HW_BCH_FLASH2LAYOUT0.B.NBLOCKS = (v)) +#endif + +/* --- Register HW_BCH_FLASH2LAYOUT0, field META_SIZE */ + +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 + +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT0_META_SIZE(v) (HW_BCH_FLASH2LAYOUT0.B.META_SIZE = (v)) +#endif + +/* --- Register HW_BCH_FLASH2LAYOUT0, field ECC0 */ + +#define BP_BCH_FLASH2LAYOUT0_ECC0 11 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F800 + +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) (((v) << 11) & BM_BCH_FLASH2LAYOUT0_ECC0) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT0_ECC0(v) BF_CS1(BCH_FLASH2LAYOUT0, ECC0, v) +#endif + +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC32 0x10 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC34 0x11 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC36 0x12 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC38 0x13 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC40 0x14 + +/* --- Register HW_BCH_FLASH2LAYOUT0, field GF13_0_GF14_1 */ + +#define BP_BCH_FLASH2LAYOUT0_GF13_0_GF14_1 10 +#define BM_BCH_FLASH2LAYOUT0_GF13_0_GF14_1 0x00000400 + +#define BF_BCH_FLASH2LAYOUT0_GF13_0_GF14_1(v) (((v) << 10) & BM_BCH_FLASH2LAYOUT0_GF13_0_GF14_1) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT0_GF13_0_GF14_1(v) BF_CS1(BCH_FLASH2LAYOUT0, GF13_0_GF14_1, v) +#endif + +/* --- Register HW_BCH_FLASH2LAYOUT0, field DATA0_SIZE */ + +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x000003FF + +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) BF_CS1(BCH_FLASH2LAYOUT0, DATA0_SIZE, v) +#endif + +/* + * HW_BCH_FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATAN_SIZE:10; + unsigned GF13_0_GF14_1:1; + unsigned ECCN:5; + unsigned PAGE_SIZE:16; + } B; +} hw_bch_flash2layout1_t; +#endif + +/* + * constants & macros for entire HW_BCH_FLASH2LAYOUT1 register + */ +#define HW_BCH_FLASH2LAYOUT1_ADDR (0x001140d0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_FLASH2LAYOUT1 (*(volatile hw_bch_flash2layout1_t *) HW_BCH_FLASH2LAYOUT1_ADDR) +#define HW_BCH_FLASH2LAYOUT1_RD() (HW_BCH_FLASH2LAYOUT1.U) +#define HW_BCH_FLASH2LAYOUT1_WR(v) (HW_BCH_FLASH2LAYOUT1.U = (v)) +#define HW_BCH_FLASH2LAYOUT1_SET(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() | (v))) +#define HW_BCH_FLASH2LAYOUT1_CLR(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() & ~(v))) +#define HW_BCH_FLASH2LAYOUT1_TOG(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() ^ (v))) +#else +#define HW_BCH_FLASH2LAYOUT1_RD() (_rbase->mem32_read(HW_BCH_FLASH2LAYOUT1_ADDR)) +#define HW_BCH_FLASH2LAYOUT1_WR(v) (_rbase->mem32_write(HW_BCH_FLASH2LAYOUT1_ADDR,(v))) +#define HW_BCH_FLASH2LAYOUT1_SET(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() | (v))) +#define HW_BCH_FLASH2LAYOUT1_CLR(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() & ~(v))) +#define HW_BCH_FLASH2LAYOUT1_TOG(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_FLASH2LAYOUT1 bitfields + */ +/* --- Register HW_BCH_FLASH2LAYOUT1, field PAGE_SIZE */ + +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) ((((reg32_t) v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#else +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) (HW_BCH_FLASH2LAYOUT1.B.PAGE_SIZE = (v)) +#endif + +/* --- Register HW_BCH_FLASH2LAYOUT1, field ECCN */ + +#define BP_BCH_FLASH2LAYOUT1_ECCN 11 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F800 + +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) (((v) << 11) & BM_BCH_FLASH2LAYOUT1_ECCN) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT1_ECCN(v) BF_CS1(BCH_FLASH2LAYOUT1, ECCN, v) +#endif + +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC32 0x10 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC34 0x11 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC36 0x12 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC38 0x13 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC40 0x14 + +/* --- Register HW_BCH_FLASH2LAYOUT1, field GF13_0_GF14_1 */ + +#define BP_BCH_FLASH2LAYOUT1_GF13_0_GF14_1 10 +#define BM_BCH_FLASH2LAYOUT1_GF13_0_GF14_1 0x00000400 + +#define BF_BCH_FLASH2LAYOUT1_GF13_0_GF14_1(v) (((v) << 10) & BM_BCH_FLASH2LAYOUT1_GF13_0_GF14_1) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT1_GF13_0_GF14_1(v) BF_CS1(BCH_FLASH2LAYOUT1, GF13_0_GF14_1, v) +#endif + +/* --- Register HW_BCH_FLASH2LAYOUT1, field DATAN_SIZE */ + +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x000003FF + +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) BF_CS1(BCH_FLASH2LAYOUT1, DATAN_SIZE, v) +#endif + +/* + * HW_BCH_FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA0_SIZE:10; + unsigned GF13_0_GF14_1:1; + unsigned ECC0:5; + unsigned META_SIZE:8; + unsigned NBLOCKS:8; + } B; +} hw_bch_flash3layout0_t; +#endif + +/* + * constants & macros for entire HW_BCH_FLASH3LAYOUT0 register + */ +#define HW_BCH_FLASH3LAYOUT0_ADDR (0x001140e0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_FLASH3LAYOUT0 (*(volatile hw_bch_flash3layout0_t *) HW_BCH_FLASH3LAYOUT0_ADDR) +#define HW_BCH_FLASH3LAYOUT0_RD() (HW_BCH_FLASH3LAYOUT0.U) +#define HW_BCH_FLASH3LAYOUT0_WR(v) (HW_BCH_FLASH3LAYOUT0.U = (v)) +#define HW_BCH_FLASH3LAYOUT0_SET(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() | (v))) +#define HW_BCH_FLASH3LAYOUT0_CLR(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() & ~(v))) +#define HW_BCH_FLASH3LAYOUT0_TOG(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() ^ (v))) +#else +#define HW_BCH_FLASH3LAYOUT0_RD() (_rbase->mem32_read(HW_BCH_FLASH3LAYOUT0_ADDR)) +#define HW_BCH_FLASH3LAYOUT0_WR(v) (_rbase->mem32_write(HW_BCH_FLASH3LAYOUT0_ADDR,(v))) +#define HW_BCH_FLASH3LAYOUT0_SET(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() | (v))) +#define HW_BCH_FLASH3LAYOUT0_CLR(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() & ~(v))) +#define HW_BCH_FLASH3LAYOUT0_TOG(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_FLASH3LAYOUT0 bitfields + */ +/* --- Register HW_BCH_FLASH3LAYOUT0, field NBLOCKS */ + +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) ((((reg32_t) v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#else +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT0_NBLOCKS(v) (HW_BCH_FLASH3LAYOUT0.B.NBLOCKS = (v)) +#endif + +/* --- Register HW_BCH_FLASH3LAYOUT0, field META_SIZE */ + +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 + +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT0_META_SIZE(v) (HW_BCH_FLASH3LAYOUT0.B.META_SIZE = (v)) +#endif + +/* --- Register HW_BCH_FLASH3LAYOUT0, field ECC0 */ + +#define BP_BCH_FLASH3LAYOUT0_ECC0 11 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F800 + +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) (((v) << 11) & BM_BCH_FLASH3LAYOUT0_ECC0) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT0_ECC0(v) BF_CS1(BCH_FLASH3LAYOUT0, ECC0, v) +#endif + +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC32 0x10 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC34 0x11 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC36 0x12 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC38 0x13 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC40 0x14 + +/* --- Register HW_BCH_FLASH3LAYOUT0, field GF13_0_GF14_1 */ + +#define BP_BCH_FLASH3LAYOUT0_GF13_0_GF14_1 10 +#define BM_BCH_FLASH3LAYOUT0_GF13_0_GF14_1 0x00000400 + +#define BF_BCH_FLASH3LAYOUT0_GF13_0_GF14_1(v) (((v) << 10) & BM_BCH_FLASH3LAYOUT0_GF13_0_GF14_1) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT0_GF13_0_GF14_1(v) BF_CS1(BCH_FLASH3LAYOUT0, GF13_0_GF14_1, v) +#endif + +/* --- Register HW_BCH_FLASH3LAYOUT0, field DATA0_SIZE */ + +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x000003FF + +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) BF_CS1(BCH_FLASH3LAYOUT0, DATA0_SIZE, v) +#endif + +/* + * HW_BCH_FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATAN_SIZE:10; + unsigned GF13_0_GF14_1:1; + unsigned ECCN:5; + unsigned PAGE_SIZE:16; + } B; +} hw_bch_flash3layout1_t; +#endif + +/* + * constants & macros for entire HW_BCH_FLASH3LAYOUT1 register + */ +#define HW_BCH_FLASH3LAYOUT1_ADDR (0x001140f0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_FLASH3LAYOUT1 (*(volatile hw_bch_flash3layout1_t *) HW_BCH_FLASH3LAYOUT1_ADDR) +#define HW_BCH_FLASH3LAYOUT1_RD() (HW_BCH_FLASH3LAYOUT1.U) +#define HW_BCH_FLASH3LAYOUT1_WR(v) (HW_BCH_FLASH3LAYOUT1.U = (v)) +#define HW_BCH_FLASH3LAYOUT1_SET(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() | (v))) +#define HW_BCH_FLASH3LAYOUT1_CLR(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() & ~(v))) +#define HW_BCH_FLASH3LAYOUT1_TOG(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() ^ (v))) +#else +#define HW_BCH_FLASH3LAYOUT1_RD() (_rbase->mem32_read(HW_BCH_FLASH3LAYOUT1_ADDR)) +#define HW_BCH_FLASH3LAYOUT1_WR(v) (_rbase->mem32_write(HW_BCH_FLASH3LAYOUT1_ADDR,(v))) +#define HW_BCH_FLASH3LAYOUT1_SET(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() | (v))) +#define HW_BCH_FLASH3LAYOUT1_CLR(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() & ~(v))) +#define HW_BCH_FLASH3LAYOUT1_TOG(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_FLASH3LAYOUT1 bitfields + */ +/* --- Register HW_BCH_FLASH3LAYOUT1, field PAGE_SIZE */ + +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) ((((reg32_t) v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#else +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) (HW_BCH_FLASH3LAYOUT1.B.PAGE_SIZE = (v)) +#endif + +/* --- Register HW_BCH_FLASH3LAYOUT1, field ECCN */ + +#define BP_BCH_FLASH3LAYOUT1_ECCN 11 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F800 + +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) (((v) << 11) & BM_BCH_FLASH3LAYOUT1_ECCN) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT1_ECCN(v) BF_CS1(BCH_FLASH3LAYOUT1, ECCN, v) +#endif + +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC32 0x10 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC34 0x11 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC36 0x12 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC38 0x13 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC40 0x14 + +/* --- Register HW_BCH_FLASH3LAYOUT1, field GF13_0_GF14_1 */ + +#define BP_BCH_FLASH3LAYOUT1_GF13_0_GF14_1 10 +#define BM_BCH_FLASH3LAYOUT1_GF13_0_GF14_1 0x00000400 + +#define BF_BCH_FLASH3LAYOUT1_GF13_0_GF14_1(v) (((v) << 10) & BM_BCH_FLASH3LAYOUT1_GF13_0_GF14_1) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT1_GF13_0_GF14_1(v) BF_CS1(BCH_FLASH3LAYOUT1, GF13_0_GF14_1, v) +#endif + +/* --- Register HW_BCH_FLASH3LAYOUT1, field DATAN_SIZE */ + +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x000003FF + +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) BF_CS1(BCH_FLASH3LAYOUT1, DATAN_SIZE, v) +#endif + +/* + * HW_BCH_DEBUG0 - Hardware BCH ECC Debug Register0 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DEBUG_REG_SELECT:6; + unsigned RSVD0:2; + unsigned BM_KES_TEST_BYPASS:1; + unsigned KES_DEBUG_STALL:1; + unsigned KES_DEBUG_STEP:1; + unsigned KES_STANDALONE:1; + unsigned KES_DEBUG_KICK:1; + unsigned KES_DEBUG_MODE4K:1; + unsigned KES_DEBUG_PAYLOAD_FLAG:1; + unsigned KES_DEBUG_SHIFT_SYND:1; + unsigned KES_DEBUG_SYNDROME_SYMBOL:9; + unsigned RSVD1:7; + } B; +} hw_bch_debug0_t; +#endif + +/* + * constants & macros for entire HW_BCH_DEBUG0 register + */ +#define HW_BCH_DEBUG0_ADDR (0x00114100) +#define HW_BCH_DEBUG0_SET_ADDR (0x00114104) +#define HW_BCH_DEBUG0_CLR_ADDR (0x00114108) +#define HW_BCH_DEBUG0_TOG_ADDR (0x0011410c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_DEBUG0 (*(volatile hw_bch_debug0_t *) HW_BCH_DEBUG0_ADDR) +#define HW_BCH_DEBUG0_RD() (HW_BCH_DEBUG0.U) +#define HW_BCH_DEBUG0_WR(v) (HW_BCH_DEBUG0.U = (v)) +#define HW_BCH_DEBUG0_SET(v) ((*(volatile reg32_t *) HW_BCH_DEBUG0_SET_ADDR) = (v)) +#define HW_BCH_DEBUG0_CLR(v) ((*(volatile reg32_t *) HW_BCH_DEBUG0_CLR_ADDR) = (v)) +#define HW_BCH_DEBUG0_TOG(v) ((*(volatile reg32_t *) HW_BCH_DEBUG0_TOG_ADDR) = (v)) +#else +#define HW_BCH_DEBUG0_RD() (_rbase->mem32_read(HW_BCH_DEBUG0_ADDR)) +#define HW_BCH_DEBUG0_WR(v) (_rbase->mem32_write(HW_BCH_DEBUG0_ADDR,(v))) +#define HW_BCH_DEBUG0_SET(v) (_rbase->mem32_write(HW_BCH_DEBUG0_SET_ADDR,(v))) +#define HW_BCH_DEBUG0_CLR(v) (_rbase->mem32_write(HW_BCH_DEBUG0_CLR_ADDR,(v))) +#define HW_BCH_DEBUG0_TOG(v) (_rbase->mem32_write(HW_BCH_DEBUG0_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_DEBUG0 bitfields + */ +/* --- Register HW_BCH_DEBUG0, field RSVD1 */ + +#define BP_BCH_DEBUG0_RSVD1 25 +#define BM_BCH_DEBUG0_RSVD1 0xFE000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_DEBUG0_RSVD1(v) ((((reg32_t) v) << 25) & BM_BCH_DEBUG0_RSVD1) +#else +#define BF_BCH_DEBUG0_RSVD1(v) (((v) << 25) & BM_BCH_DEBUG0_RSVD1) +#endif +/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_SYNDROME_SYMBOL */ + +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 + +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_SYNDROME_SYMBOL, v) +#endif + +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 + +/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_SHIFT_SYND */ + +#define BP_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 15 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 + +#define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v) (((v) << 15) & BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_SHIFT_SYND, v) +#endif + +/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_PAYLOAD_FLAG */ + +#define BP_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 14 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 + +#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) (((v) << 14) & BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_PAYLOAD_FLAG, v) +#endif + +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 + +/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_MODE4K */ + +#define BP_BCH_DEBUG0_KES_DEBUG_MODE4K 13 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 + +#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K(v) (((v) << 13) & BM_BCH_DEBUG0_KES_DEBUG_MODE4K) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_KES_DEBUG_MODE4K(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_MODE4K, v) +#endif + +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 + +/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_KICK */ + +#define BP_BCH_DEBUG0_KES_DEBUG_KICK 12 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 + +#define BF_BCH_DEBUG0_KES_DEBUG_KICK(v) (((v) << 12) & BM_BCH_DEBUG0_KES_DEBUG_KICK) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_KES_DEBUG_KICK(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_KICK, v) +#endif + +/* --- Register HW_BCH_DEBUG0, field KES_STANDALONE */ + +#define BP_BCH_DEBUG0_KES_STANDALONE 11 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 + +#define BF_BCH_DEBUG0_KES_STANDALONE(v) (((v) << 11) & BM_BCH_DEBUG0_KES_STANDALONE) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_KES_STANDALONE(v) BF_CS1(BCH_DEBUG0, KES_STANDALONE, v) +#endif + +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 + +/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_STEP */ + +#define BP_BCH_DEBUG0_KES_DEBUG_STEP 10 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 + +#define BF_BCH_DEBUG0_KES_DEBUG_STEP(v) (((v) << 10) & BM_BCH_DEBUG0_KES_DEBUG_STEP) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_KES_DEBUG_STEP(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_STEP, v) +#endif + +/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_STALL */ + +#define BP_BCH_DEBUG0_KES_DEBUG_STALL 9 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 + +#define BF_BCH_DEBUG0_KES_DEBUG_STALL(v) (((v) << 9) & BM_BCH_DEBUG0_KES_DEBUG_STALL) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_KES_DEBUG_STALL(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_STALL, v) +#endif + +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 + +/* --- Register HW_BCH_DEBUG0, field BM_KES_TEST_BYPASS */ + +#define BP_BCH_DEBUG0_BM_KES_TEST_BYPASS 8 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 + +#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(v) (((v) << 8) & BM_BCH_DEBUG0_BM_KES_TEST_BYPASS) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_BM_KES_TEST_BYPASS(v) BF_CS1(BCH_DEBUG0, BM_KES_TEST_BYPASS, v) +#endif + +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 + +/* --- Register HW_BCH_DEBUG0, field RSVD0 */ + +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0x000000C0 + +#define BF_BCH_DEBUG0_RSVD0(v) (((v) << 6) & BM_BCH_DEBUG0_RSVD0) +/* --- Register HW_BCH_DEBUG0, field DEBUG_REG_SELECT */ + +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F + +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) +#ifndef __LANGUAGE_ASM__ +#define BW_BCH_DEBUG0_DEBUG_REG_SELECT(v) BF_CS1(BCH_DEBUG0, DEBUG_REG_SELECT, v) +#endif + +/* + * HW_BCH_DBGKESREAD - KES Debug Read Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned VALUES:32; + } B; +} hw_bch_dbgkesread_t; +#endif + +/* + * constants & macros for entire HW_BCH_DBGKESREAD register + */ +#define HW_BCH_DBGKESREAD_ADDR (0x00114110) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_DBGKESREAD (*(volatile hw_bch_dbgkesread_t *) HW_BCH_DBGKESREAD_ADDR) +#define HW_BCH_DBGKESREAD_RD() (HW_BCH_DBGKESREAD.U) +#else +#define HW_BCH_DBGKESREAD_RD() (_rbase->mem32_read(HW_BCH_DBGKESREAD_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_DBGKESREAD bitfields + */ +/* --- Register HW_BCH_DBGKESREAD, field VALUES */ + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_DBGKESREAD_VALUES(v) ((reg32_t) v) +#else +#define BF_BCH_DBGKESREAD_VALUES(v) (v) +#endif + +/* + * HW_BCH_DBGCSFEREAD - Chien Search Debug Read Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned VALUES:32; + } B; +} hw_bch_dbgcsferead_t; +#endif + +/* + * constants & macros for entire HW_BCH_DBGCSFEREAD register + */ +#define HW_BCH_DBGCSFEREAD_ADDR (0x00114120) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_DBGCSFEREAD (*(volatile hw_bch_dbgcsferead_t *) HW_BCH_DBGCSFEREAD_ADDR) +#define HW_BCH_DBGCSFEREAD_RD() (HW_BCH_DBGCSFEREAD.U) +#else +#define HW_BCH_DBGCSFEREAD_RD() (_rbase->mem32_read(HW_BCH_DBGCSFEREAD_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_DBGCSFEREAD bitfields + */ +/* --- Register HW_BCH_DBGCSFEREAD, field VALUES */ + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_DBGCSFEREAD_VALUES(v) ((reg32_t) v) +#else +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) +#endif + +/* + * HW_BCH_DBGSYNDGENREAD - Syndrome Generator Debug Read Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned VALUES:32; + } B; +} hw_bch_dbgsyndgenread_t; +#endif + +/* + * constants & macros for entire HW_BCH_DBGSYNDGENREAD register + */ +#define HW_BCH_DBGSYNDGENREAD_ADDR (0x00114130) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_DBGSYNDGENREAD (*(volatile hw_bch_dbgsyndgenread_t *) HW_BCH_DBGSYNDGENREAD_ADDR) +#define HW_BCH_DBGSYNDGENREAD_RD() (HW_BCH_DBGSYNDGENREAD.U) +#else +#define HW_BCH_DBGSYNDGENREAD_RD() (_rbase->mem32_read(HW_BCH_DBGSYNDGENREAD_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_DBGSYNDGENREAD bitfields + */ +/* --- Register HW_BCH_DBGSYNDGENREAD, field VALUES */ + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) ((reg32_t) v) +#else +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) +#endif + +/* + * HW_BCH_DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned VALUES:32; + } B; +} hw_bch_dbgahbmread_t; +#endif + +/* + * constants & macros for entire HW_BCH_DBGAHBMREAD register + */ +#define HW_BCH_DBGAHBMREAD_ADDR (0x00114140) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_DBGAHBMREAD (*(volatile hw_bch_dbgahbmread_t *) HW_BCH_DBGAHBMREAD_ADDR) +#define HW_BCH_DBGAHBMREAD_RD() (HW_BCH_DBGAHBMREAD.U) +#else +#define HW_BCH_DBGAHBMREAD_RD() (_rbase->mem32_read(HW_BCH_DBGAHBMREAD_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_DBGAHBMREAD bitfields + */ +/* --- Register HW_BCH_DBGAHBMREAD, field VALUES */ + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_DBGAHBMREAD_VALUES(v) ((reg32_t) v) +#else +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) +#endif + +/* + * HW_BCH_BLOCKNAME - Block Name Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned NAME:32; + } B; +} hw_bch_blockname_t; +#endif + +/* + * constants & macros for entire HW_BCH_BLOCKNAME register + */ +#define HW_BCH_BLOCKNAME_ADDR (0x00114150) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_BLOCKNAME (*(volatile hw_bch_blockname_t *) HW_BCH_BLOCKNAME_ADDR) +#define HW_BCH_BLOCKNAME_RD() (HW_BCH_BLOCKNAME.U) +#else +#define HW_BCH_BLOCKNAME_RD() (_rbase->mem32_read(HW_BCH_BLOCKNAME_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_BLOCKNAME bitfields + */ +/* --- Register HW_BCH_BLOCKNAME, field NAME */ + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_BLOCKNAME_NAME(v) ((reg32_t) v) +#else +#define BF_BCH_BLOCKNAME_NAME(v) (v) +#endif + +/* + * HW_BCH_VERSION - BCH Version Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned STEP:16; + unsigned MINOR:8; + unsigned MAJOR:8; + } B; +} hw_bch_version_t; +#endif + +/* + * constants & macros for entire HW_BCH_VERSION register + */ +#define HW_BCH_VERSION_ADDR (0x00114160) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_BCH_VERSION (*(volatile hw_bch_version_t *) HW_BCH_VERSION_ADDR) +#define HW_BCH_VERSION_RD() (HW_BCH_VERSION.U) +#else +#define HW_BCH_VERSION_RD() (_rbase->mem32_read(HW_BCH_VERSION_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_BCH_VERSION bitfields + */ +/* --- Register HW_BCH_VERSION, field MAJOR */ + +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_BCH_VERSION_MAJOR(v) ((((reg32_t) v) << 24) & BM_BCH_VERSION_MAJOR) +#else +#define BF_BCH_VERSION_MAJOR(v) (((v) << 24) & BM_BCH_VERSION_MAJOR) +#endif +/* --- Register HW_BCH_VERSION, field MINOR */ + +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0x00FF0000 + +#define BF_BCH_VERSION_MINOR(v) (((v) << 16) & BM_BCH_VERSION_MINOR) +/* --- Register HW_BCH_VERSION, field STEP */ + +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0x0000FFFF + +#define BF_BCH_VERSION_STEP(v) (((v) << 0) & BM_BCH_VERSION_STEP) + +#endif /* _BCH_H */ + +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/mx6ul/regsgpmi.h b/bsp/imx6ul/platform/include/mx6ul/regsgpmi.h new file mode 100644 index 0000000000000000000000000000000000000000..60b8cda3b700a1e8c2a39c0f32bfd31fe6fbb50e --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/regsgpmi.h @@ -0,0 +1,2161 @@ +/* + * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved + * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT + * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF + * Freescale Semiconductor, Inc. + */ + +#ifndef _GPMI_H +#define _GPMI_H 1 + +#include "regs.h" +//#include "registers.h" + +#ifndef REGS_GPMI_BASE +#define REGS_GPMI_BASE (REGS_BASE + 0x112000) +#endif + +/* + * HW_GPMI_CTRL0 - GPMI Control Register 0 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned XFER_COUNT:16; + unsigned ADDRESS_INCREMENT:1; + unsigned ADDRESS:3; + unsigned CS:3; + unsigned WORD_LENGTH:1; + unsigned COMMAND_MODE:2; + unsigned UDMA:1; + unsigned LOCK_CS:1; + unsigned DEV_IRQ_EN:1; + unsigned RUN:1; + unsigned CLKGATE:1; + unsigned SFTRST:1; + } B; +} hw_gpmi_ctrl0_t; +#endif + +/* + * constants & macros for entire HW_GPMI_CTRL0 register + */ +#define HW_GPMI_CTRL0_ADDR (0x00112000) +#define HW_GPMI_CTRL0_SET_ADDR (0x00112004) +#define HW_GPMI_CTRL0_CLR_ADDR (0x00112008) +#define HW_GPMI_CTRL0_TOG_ADDR (0x0011200c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_CTRL0 (*(volatile hw_gpmi_ctrl0_t *) HW_GPMI_CTRL0_ADDR) +#define HW_GPMI_CTRL0_RD() (HW_GPMI_CTRL0.U) +#define HW_GPMI_CTRL0_WR(v) (HW_GPMI_CTRL0.U = (v)) +#define HW_GPMI_CTRL0_SET(v) ((*(volatile reg32_t *) HW_GPMI_CTRL0_SET_ADDR) = (v)) +#define HW_GPMI_CTRL0_CLR(v) ((*(volatile reg32_t *) HW_GPMI_CTRL0_CLR_ADDR) = (v)) +#define HW_GPMI_CTRL0_TOG(v) ((*(volatile reg32_t *) HW_GPMI_CTRL0_TOG_ADDR) = (v)) +#else +#define HW_GPMI_CTRL0_RD() (_rbase->mem32_read(HW_GPMI_CTRL0_ADDR)) +#define HW_GPMI_CTRL0_WR(v) (_rbase->mem32_write(HW_GPMI_CTRL0_ADDR,(v))) +#define HW_GPMI_CTRL0_SET(v) (_rbase->mem32_write(HW_GPMI_CTRL0_SET_ADDR,(v))) +#define HW_GPMI_CTRL0_CLR(v) (_rbase->mem32_write(HW_GPMI_CTRL0_CLR_ADDR,(v))) +#define HW_GPMI_CTRL0_TOG(v) (_rbase->mem32_write(HW_GPMI_CTRL0_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_CTRL0 bitfields + */ +/* --- Register HW_GPMI_CTRL0, field SFTRST */ + +#define BP_GPMI_CTRL0_SFTRST 31 +#define BM_GPMI_CTRL0_SFTRST 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_CTRL0_SFTRST(v) ((((reg32_t) v) << 31) & BM_GPMI_CTRL0_SFTRST) +#else +#define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & BM_GPMI_CTRL0_SFTRST) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_SFTRST(v) BF_CS1(GPMI_CTRL0, SFTRST, v) +#endif + +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 + +/* --- Register HW_GPMI_CTRL0, field CLKGATE */ + +#define BP_GPMI_CTRL0_CLKGATE 30 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 + +#define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & BM_GPMI_CTRL0_CLKGATE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_CLKGATE(v) BF_CS1(GPMI_CTRL0, CLKGATE, v) +#endif + +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 + +/* --- Register HW_GPMI_CTRL0, field RUN */ + +#define BP_GPMI_CTRL0_RUN 29 +#define BM_GPMI_CTRL0_RUN 0x20000000 + +#define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & BM_GPMI_CTRL0_RUN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_RUN(v) BF_CS1(GPMI_CTRL0, RUN, v) +#endif + +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 + +/* --- Register HW_GPMI_CTRL0, field DEV_IRQ_EN */ + +#define BP_GPMI_CTRL0_DEV_IRQ_EN 28 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 + +#define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & BM_GPMI_CTRL0_DEV_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_DEV_IRQ_EN(v) BF_CS1(GPMI_CTRL0, DEV_IRQ_EN, v) +#endif + +/* --- Register HW_GPMI_CTRL0, field LOCK_CS */ + +#define BP_GPMI_CTRL0_LOCK_CS 27 +#define BM_GPMI_CTRL0_LOCK_CS 0x08000000 + +#define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 27) & BM_GPMI_CTRL0_LOCK_CS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_LOCK_CS(v) BF_CS1(GPMI_CTRL0, LOCK_CS, v) +#endif + +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 + +/* --- Register HW_GPMI_CTRL0, field UDMA */ + +#define BP_GPMI_CTRL0_UDMA 26 +#define BM_GPMI_CTRL0_UDMA 0x04000000 + +#define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & BM_GPMI_CTRL0_UDMA) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_UDMA(v) BF_CS1(GPMI_CTRL0, UDMA, v) +#endif + +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 + +/* --- Register HW_GPMI_CTRL0, field COMMAND_MODE */ + +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 + +#define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_COMMAND_MODE(v) BF_CS1(GPMI_CTRL0, COMMAND_MODE, v) +#endif + +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 + +/* --- Register HW_GPMI_CTRL0, field WORD_LENGTH */ + +#define BP_GPMI_CTRL0_WORD_LENGTH 23 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 + +#define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & BM_GPMI_CTRL0_WORD_LENGTH) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_WORD_LENGTH(v) BF_CS1(GPMI_CTRL0, WORD_LENGTH, v) +#endif + +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 + +/* --- Register HW_GPMI_CTRL0, field CS */ + +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00700000 + +#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & BM_GPMI_CTRL0_CS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_CS(v) BF_CS1(GPMI_CTRL0, CS, v) +#endif + +/* --- Register HW_GPMI_CTRL0, field ADDRESS */ + +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 + +#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_ADDRESS(v) BF_CS1(GPMI_CTRL0, ADDRESS, v) +#endif + +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 + +/* --- Register HW_GPMI_CTRL0, field ADDRESS_INCREMENT */ + +#define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 + +#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & BM_GPMI_CTRL0_ADDRESS_INCREMENT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_ADDRESS_INCREMENT(v) BF_CS1(GPMI_CTRL0, ADDRESS_INCREMENT, v) +#endif + +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 + +/* --- Register HW_GPMI_CTRL0, field XFER_COUNT */ + +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF + +#define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL0_XFER_COUNT(v) (HW_GPMI_CTRL0.B.XFER_COUNT = (v)) +#endif + +/* + * HW_GPMI_COMPARE - GPMI Compare Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned REFERENCE:16; + unsigned MASK:16; + } B; +} hw_gpmi_compare_t; +#endif + +/* + * constants & macros for entire HW_GPMI_COMPARE register + */ +#define HW_GPMI_COMPARE_ADDR (0x00112010) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_COMPARE (*(volatile hw_gpmi_compare_t *) HW_GPMI_COMPARE_ADDR) +#define HW_GPMI_COMPARE_RD() (HW_GPMI_COMPARE.U) +#define HW_GPMI_COMPARE_WR(v) (HW_GPMI_COMPARE.U = (v)) +#define HW_GPMI_COMPARE_SET(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() | (v))) +#define HW_GPMI_COMPARE_CLR(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() & ~(v))) +#define HW_GPMI_COMPARE_TOG(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() ^ (v))) +#else +#define HW_GPMI_COMPARE_RD() (_rbase->mem32_read(HW_GPMI_COMPARE_ADDR)) +#define HW_GPMI_COMPARE_WR(v) (_rbase->mem32_write(HW_GPMI_COMPARE_ADDR,(v))) +#define HW_GPMI_COMPARE_SET(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() | (v))) +#define HW_GPMI_COMPARE_CLR(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() & ~(v))) +#define HW_GPMI_COMPARE_TOG(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_COMPARE bitfields + */ +/* --- Register HW_GPMI_COMPARE, field MASK */ + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_COMPARE_MASK(v) ((((reg32_t) v) << 16) & BM_GPMI_COMPARE_MASK) +#else +#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_COMPARE_MASK(v) (HW_GPMI_COMPARE.B.MASK = (v)) +#endif + +/* --- Register HW_GPMI_COMPARE, field REFERENCE */ + +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF + +#define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_COMPARE_REFERENCE(v) (HW_GPMI_COMPARE.B.REFERENCE = (v)) +#endif + +/* + * HW_GPMI_ECCCTRL - GPMI Integrated ECC Control Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned BUFFER_MASK:9; + unsigned RSVD1:3; + unsigned ENABLE_ECC:1; + unsigned ECC_CMD:2; + unsigned RSVD2:1; + unsigned HANDLE:16; + } B; +} hw_gpmi_eccctrl_t; +#endif + +/* + * constants & macros for entire HW_GPMI_ECCCTRL register + */ +#define HW_GPMI_ECCCTRL_ADDR (0x00112020) +#define HW_GPMI_ECCCTRL_SET_ADDR (0x00112024) +#define HW_GPMI_ECCCTRL_CLR_ADDR (0x00112028) +#define HW_GPMI_ECCCTRL_TOG_ADDR (0x0011202c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_ECCCTRL (*(volatile hw_gpmi_eccctrl_t *) HW_GPMI_ECCCTRL_ADDR) +#define HW_GPMI_ECCCTRL_RD() (HW_GPMI_ECCCTRL.U) +#define HW_GPMI_ECCCTRL_WR(v) (HW_GPMI_ECCCTRL.U = (v)) +#define HW_GPMI_ECCCTRL_SET(v) ((*(volatile reg32_t *) HW_GPMI_ECCCTRL_SET_ADDR) = (v)) +#define HW_GPMI_ECCCTRL_CLR(v) ((*(volatile reg32_t *) HW_GPMI_ECCCTRL_CLR_ADDR) = (v)) +#define HW_GPMI_ECCCTRL_TOG(v) ((*(volatile reg32_t *) HW_GPMI_ECCCTRL_TOG_ADDR) = (v)) +#else +#define HW_GPMI_ECCCTRL_RD() (_rbase->mem32_read(HW_GPMI_ECCCTRL_ADDR)) +#define HW_GPMI_ECCCTRL_WR(v) (_rbase->mem32_write(HW_GPMI_ECCCTRL_ADDR,(v))) +#define HW_GPMI_ECCCTRL_SET(v) (_rbase->mem32_write(HW_GPMI_ECCCTRL_SET_ADDR,(v))) +#define HW_GPMI_ECCCTRL_CLR(v) (_rbase->mem32_write(HW_GPMI_ECCCTRL_CLR_ADDR,(v))) +#define HW_GPMI_ECCCTRL_TOG(v) (_rbase->mem32_write(HW_GPMI_ECCCTRL_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_ECCCTRL bitfields + */ +/* --- Register HW_GPMI_ECCCTRL, field HANDLE */ + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_ECCCTRL_HANDLE(v) ((((reg32_t) v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#else +#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCTRL_HANDLE(v) (HW_GPMI_ECCCTRL.B.HANDLE = (v)) +#endif + +/* --- Register HW_GPMI_ECCCTRL, field RSVD2 */ + +#define BP_GPMI_ECCCTRL_RSVD2 15 +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 + +#define BF_GPMI_ECCCTRL_RSVD2(v) (((v) << 15) & BM_GPMI_ECCCTRL_RSVD2) +/* --- Register HW_GPMI_ECCCTRL, field ECC_CMD */ + +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 + +#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCTRL_ECC_CMD(v) BF_CS1(GPMI_ECCCTRL, ECC_CMD, v) +#endif + +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3 + +/* --- Register HW_GPMI_ECCCTRL, field ENABLE_ECC */ + +#define BP_GPMI_ECCCTRL_ENABLE_ECC 12 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 + +#define BF_GPMI_ECCCTRL_ENABLE_ECC(v) (((v) << 12) & BM_GPMI_ECCCTRL_ENABLE_ECC) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCTRL_ENABLE_ECC(v) BF_CS1(GPMI_ECCCTRL, ENABLE_ECC, v) +#endif + +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 + +/* --- Register HW_GPMI_ECCCTRL, field RSVD1 */ + +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 + +#define BF_GPMI_ECCCTRL_RSVD1(v) (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +/* --- Register HW_GPMI_ECCCTRL, field BUFFER_MASK */ + +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF + +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCTRL_BUFFER_MASK(v) BF_CS1(GPMI_ECCCTRL, BUFFER_MASK, v) +#endif + +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF + +/* + * HW_GPMI_ECCCOUNT - GPMI Integrated ECC Transfer Count Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned COUNT:16; + unsigned RSVD2:16; + } B; +} hw_gpmi_ecccount_t; +#endif + +/* + * constants & macros for entire HW_GPMI_ECCCOUNT register + */ +#define HW_GPMI_ECCCOUNT_ADDR (0x00112030) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_ECCCOUNT (*(volatile hw_gpmi_ecccount_t *) HW_GPMI_ECCCOUNT_ADDR) +#define HW_GPMI_ECCCOUNT_RD() (HW_GPMI_ECCCOUNT.U) +#define HW_GPMI_ECCCOUNT_WR(v) (HW_GPMI_ECCCOUNT.U = (v)) +#define HW_GPMI_ECCCOUNT_SET(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() | (v))) +#define HW_GPMI_ECCCOUNT_CLR(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() & ~(v))) +#define HW_GPMI_ECCCOUNT_TOG(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() ^ (v))) +#else +#define HW_GPMI_ECCCOUNT_RD() (_rbase->mem32_read(HW_GPMI_ECCCOUNT_ADDR)) +#define HW_GPMI_ECCCOUNT_WR(v) (_rbase->mem32_write(HW_GPMI_ECCCOUNT_ADDR,(v))) +#define HW_GPMI_ECCCOUNT_SET(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() | (v))) +#define HW_GPMI_ECCCOUNT_CLR(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() & ~(v))) +#define HW_GPMI_ECCCOUNT_TOG(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_ECCCOUNT bitfields + */ +/* --- Register HW_GPMI_ECCCOUNT, field RSVD2 */ + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_ECCCOUNT_RSVD2(v) ((((reg32_t) v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#else +#define BF_GPMI_ECCCOUNT_RSVD2(v) (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#endif +/* --- Register HW_GPMI_ECCCOUNT, field COUNT */ + +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF + +#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_ECCCOUNT_COUNT(v) (HW_GPMI_ECCCOUNT.B.COUNT = (v)) +#endif + +/* + * HW_GPMI_PAYLOAD - GPMI Payload Address Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RSVD0:2; + unsigned ADDRESS:30; + } B; +} hw_gpmi_payload_t; +#endif + +/* + * constants & macros for entire HW_GPMI_PAYLOAD register + */ +#define HW_GPMI_PAYLOAD_ADDR (0x00112040) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_PAYLOAD (*(volatile hw_gpmi_payload_t *) HW_GPMI_PAYLOAD_ADDR) +#define HW_GPMI_PAYLOAD_RD() (HW_GPMI_PAYLOAD.U) +#define HW_GPMI_PAYLOAD_WR(v) (HW_GPMI_PAYLOAD.U = (v)) +#define HW_GPMI_PAYLOAD_SET(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() | (v))) +#define HW_GPMI_PAYLOAD_CLR(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() & ~(v))) +#define HW_GPMI_PAYLOAD_TOG(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() ^ (v))) +#else +#define HW_GPMI_PAYLOAD_RD() (_rbase->mem32_read(HW_GPMI_PAYLOAD_ADDR)) +#define HW_GPMI_PAYLOAD_WR(v) (_rbase->mem32_write(HW_GPMI_PAYLOAD_ADDR,(v))) +#define HW_GPMI_PAYLOAD_SET(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() | (v))) +#define HW_GPMI_PAYLOAD_CLR(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() & ~(v))) +#define HW_GPMI_PAYLOAD_TOG(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_PAYLOAD bitfields + */ +/* --- Register HW_GPMI_PAYLOAD, field ADDRESS */ + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_PAYLOAD_ADDRESS(v) ((((reg32_t) v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#else +#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_PAYLOAD_ADDRESS(v) BF_CS1(GPMI_PAYLOAD, ADDRESS, v) +#endif + +/* --- Register HW_GPMI_PAYLOAD, field RSVD0 */ + +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 + +#define BF_GPMI_PAYLOAD_RSVD0(v) (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +/* + * HW_GPMI_AUXILIARY - GPMI Auxiliary Address Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RSVD0:2; + unsigned ADDRESS:30; + } B; +} hw_gpmi_auxiliary_t; +#endif + +/* + * constants & macros for entire HW_GPMI_AUXILIARY register + */ +#define HW_GPMI_AUXILIARY_ADDR (0x00112050) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_AUXILIARY (*(volatile hw_gpmi_auxiliary_t *) HW_GPMI_AUXILIARY_ADDR) +#define HW_GPMI_AUXILIARY_RD() (HW_GPMI_AUXILIARY.U) +#define HW_GPMI_AUXILIARY_WR(v) (HW_GPMI_AUXILIARY.U = (v)) +#define HW_GPMI_AUXILIARY_SET(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() | (v))) +#define HW_GPMI_AUXILIARY_CLR(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() & ~(v))) +#define HW_GPMI_AUXILIARY_TOG(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() ^ (v))) +#else +#define HW_GPMI_AUXILIARY_RD() (_rbase->mem32_read(HW_GPMI_AUXILIARY_ADDR)) +#define HW_GPMI_AUXILIARY_WR(v) (_rbase->mem32_write(HW_GPMI_AUXILIARY_ADDR,(v))) +#define HW_GPMI_AUXILIARY_SET(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() | (v))) +#define HW_GPMI_AUXILIARY_CLR(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() & ~(v))) +#define HW_GPMI_AUXILIARY_TOG(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_AUXILIARY bitfields + */ +/* --- Register HW_GPMI_AUXILIARY, field ADDRESS */ + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_AUXILIARY_ADDRESS(v) ((((reg32_t) v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#else +#define BF_GPMI_AUXILIARY_ADDRESS(v) (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_AUXILIARY_ADDRESS(v) BF_CS1(GPMI_AUXILIARY, ADDRESS, v) +#endif + +/* --- Register HW_GPMI_AUXILIARY, field RSVD0 */ + +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 + +#define BF_GPMI_AUXILIARY_RSVD0(v) (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +/* + * HW_GPMI_CTRL1 - GPMI Control Register 1 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned GPMI_MODE:1; + unsigned CAMERA_MODE:1; + unsigned ATA_IRQRDY_POLARITY:1; + unsigned DEV_RESET:1; + unsigned ABORT_WAIT_FOR_READY_CHANNEL:3; + unsigned ABORT_WAIT_REQUEST:1; + unsigned BURST_EN:1; + unsigned TIMEOUT_IRQ:1; + unsigned DEV_IRQ:1; + unsigned DMA2ECC_MODE:1; + unsigned RDN_DELAY:4; + unsigned HALF_PERIOD:1; + unsigned DLL_ENABLE:1; + unsigned BCH_MODE:1; + unsigned GANGED_RDYBUSY:1; + unsigned TIMEOUT_IRQ_EN:1; + unsigned RSVD1:1; + unsigned WRN_DLY_SEL:2; + unsigned DECOUPLE_CS:1; + unsigned SSYNCMODE:1; + unsigned UPDATE_CS:1; + unsigned GPMI_CLK_DIV2_EN:1; + unsigned TOGGLE_MODE:1; + unsigned WRITE_CLK_STOP:1; + unsigned SSYNC_CLK_STOP:1; + unsigned DEV_CLK_STOP:1; + } B; +} hw_gpmi_ctrl1_t; +#endif + +/* + * constants & macros for entire HW_GPMI_CTRL1 register + */ +#define HW_GPMI_CTRL1_ADDR (0x00112060) +#define HW_GPMI_CTRL1_SET_ADDR (0x00112064) +#define HW_GPMI_CTRL1_CLR_ADDR (0x00112068) +#define HW_GPMI_CTRL1_TOG_ADDR (0x0011206c) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_CTRL1 (*(volatile hw_gpmi_ctrl1_t *) HW_GPMI_CTRL1_ADDR) +#define HW_GPMI_CTRL1_RD() (HW_GPMI_CTRL1.U) +#define HW_GPMI_CTRL1_WR(v) (HW_GPMI_CTRL1.U = (v)) +#define HW_GPMI_CTRL1_SET(v) ((*(volatile reg32_t *) HW_GPMI_CTRL1_SET_ADDR) = (v)) +#define HW_GPMI_CTRL1_CLR(v) ((*(volatile reg32_t *) HW_GPMI_CTRL1_CLR_ADDR) = (v)) +#define HW_GPMI_CTRL1_TOG(v) ((*(volatile reg32_t *) HW_GPMI_CTRL1_TOG_ADDR) = (v)) +#else +#define HW_GPMI_CTRL1_RD() (_rbase->mem32_read(HW_GPMI_CTRL1_ADDR)) +#define HW_GPMI_CTRL1_WR(v) (_rbase->mem32_write(HW_GPMI_CTRL1_ADDR,(v))) +#define HW_GPMI_CTRL1_SET(v) (_rbase->mem32_write(HW_GPMI_CTRL1_SET_ADDR,(v))) +#define HW_GPMI_CTRL1_CLR(v) (_rbase->mem32_write(HW_GPMI_CTRL1_CLR_ADDR,(v))) +#define HW_GPMI_CTRL1_TOG(v) (_rbase->mem32_write(HW_GPMI_CTRL1_TOG_ADDR,(v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_CTRL1 bitfields + */ +/* --- Register HW_GPMI_CTRL1, field DEV_CLK_STOP */ + +#define BP_GPMI_CTRL1_DEV_CLK_STOP 31 +#define BM_GPMI_CTRL1_DEV_CLK_STOP 0x80000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_CTRL1_DEV_CLK_STOP(v) ((((reg32_t) v) << 31) & BM_GPMI_CTRL1_DEV_CLK_STOP) +#else +#define BF_GPMI_CTRL1_DEV_CLK_STOP(v) (((v) << 31) & BM_GPMI_CTRL1_DEV_CLK_STOP) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DEV_CLK_STOP(v) BF_CS1(GPMI_CTRL1, DEV_CLK_STOP, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field SSYNC_CLK_STOP */ + +#define BP_GPMI_CTRL1_SSYNC_CLK_STOP 30 +#define BM_GPMI_CTRL1_SSYNC_CLK_STOP 0x40000000 + +#define BF_GPMI_CTRL1_SSYNC_CLK_STOP(v) (((v) << 30) & BM_GPMI_CTRL1_SSYNC_CLK_STOP) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_SSYNC_CLK_STOP(v) BF_CS1(GPMI_CTRL1, SSYNC_CLK_STOP, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field WRITE_CLK_STOP */ + +#define BP_GPMI_CTRL1_WRITE_CLK_STOP 29 +#define BM_GPMI_CTRL1_WRITE_CLK_STOP 0x20000000 + +#define BF_GPMI_CTRL1_WRITE_CLK_STOP(v) (((v) << 29) & BM_GPMI_CTRL1_WRITE_CLK_STOP) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_WRITE_CLK_STOP(v) BF_CS1(GPMI_CTRL1, WRITE_CLK_STOP, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field TOGGLE_MODE */ + +#define BP_GPMI_CTRL1_TOGGLE_MODE 28 +#define BM_GPMI_CTRL1_TOGGLE_MODE 0x10000000 + +#define BF_GPMI_CTRL1_TOGGLE_MODE(v) (((v) << 28) & BM_GPMI_CTRL1_TOGGLE_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_TOGGLE_MODE(v) BF_CS1(GPMI_CTRL1, TOGGLE_MODE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field GPMI_CLK_DIV2_EN */ + +#define BP_GPMI_CTRL1_GPMI_CLK_DIV2_EN 27 +#define BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN 0x08000000 + +#define BF_GPMI_CTRL1_GPMI_CLK_DIV2_EN(v) (((v) << 27) & BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_GPMI_CLK_DIV2_EN(v) BF_CS1(GPMI_CTRL1, GPMI_CLK_DIV2_EN, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field UPDATE_CS */ + +#define BP_GPMI_CTRL1_UPDATE_CS 26 +#define BM_GPMI_CTRL1_UPDATE_CS 0x04000000 + +#define BF_GPMI_CTRL1_UPDATE_CS(v) (((v) << 26) & BM_GPMI_CTRL1_UPDATE_CS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_UPDATE_CS(v) BF_CS1(GPMI_CTRL1, UPDATE_CS, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field SSYNCMODE */ + +#define BP_GPMI_CTRL1_SSYNCMODE 25 +#define BM_GPMI_CTRL1_SSYNCMODE 0x02000000 + +#define BF_GPMI_CTRL1_SSYNCMODE(v) (((v) << 25) & BM_GPMI_CTRL1_SSYNCMODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_SSYNCMODE(v) BF_CS1(GPMI_CTRL1, SSYNCMODE, v) +#endif + +#define BV_GPMI_CTRL1_SSYNCMODE__ASYNC 0x0 +#define BV_GPMI_CTRL1_SSYNCMODE__SSYNC 0x1 + +/* --- Register HW_GPMI_CTRL1, field DECOUPLE_CS */ + +#define BP_GPMI_CTRL1_DECOUPLE_CS 24 +#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000 + +#define BF_GPMI_CTRL1_DECOUPLE_CS(v) (((v) << 24) & BM_GPMI_CTRL1_DECOUPLE_CS) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DECOUPLE_CS(v) BF_CS1(GPMI_CTRL1, DECOUPLE_CS, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field WRN_DLY_SEL */ + +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 +#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000 + +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) (((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_WRN_DLY_SEL(v) BF_CS1(GPMI_CTRL1, WRN_DLY_SEL, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field RSVD1 */ + +#define BP_GPMI_CTRL1_RSVD1 21 +#define BM_GPMI_CTRL1_RSVD1 0x00200000 + +#define BF_GPMI_CTRL1_RSVD1(v) (((v) << 21) & BM_GPMI_CTRL1_RSVD1) +/* --- Register HW_GPMI_CTRL1, field TIMEOUT_IRQ_EN */ + +#define BP_GPMI_CTRL1_TIMEOUT_IRQ_EN 20 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000 + +#define BF_GPMI_CTRL1_TIMEOUT_IRQ_EN(v) (((v) << 20) & BM_GPMI_CTRL1_TIMEOUT_IRQ_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_TIMEOUT_IRQ_EN(v) BF_CS1(GPMI_CTRL1, TIMEOUT_IRQ_EN, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field GANGED_RDYBUSY */ + +#define BP_GPMI_CTRL1_GANGED_RDYBUSY 19 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 + +#define BF_GPMI_CTRL1_GANGED_RDYBUSY(v) (((v) << 19) & BM_GPMI_CTRL1_GANGED_RDYBUSY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_GANGED_RDYBUSY(v) BF_CS1(GPMI_CTRL1, GANGED_RDYBUSY, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field BCH_MODE */ + +#define BP_GPMI_CTRL1_BCH_MODE 18 +#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 + +#define BF_GPMI_CTRL1_BCH_MODE(v) (((v) << 18) & BM_GPMI_CTRL1_BCH_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_BCH_MODE(v) BF_CS1(GPMI_CTRL1, BCH_MODE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field DLL_ENABLE */ + +#define BP_GPMI_CTRL1_DLL_ENABLE 17 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 + +#define BF_GPMI_CTRL1_DLL_ENABLE(v) (((v) << 17) & BM_GPMI_CTRL1_DLL_ENABLE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DLL_ENABLE(v) BF_CS1(GPMI_CTRL1, DLL_ENABLE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field HALF_PERIOD */ + +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 + +#define BF_GPMI_CTRL1_HALF_PERIOD(v) (((v) << 16) & BM_GPMI_CTRL1_HALF_PERIOD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_HALF_PERIOD(v) BF_CS1(GPMI_CTRL1, HALF_PERIOD, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field RDN_DELAY */ + +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 + +#define BF_GPMI_CTRL1_RDN_DELAY(v) (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_RDN_DELAY(v) BF_CS1(GPMI_CTRL1, RDN_DELAY, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field DMA2ECC_MODE */ + +#define BP_GPMI_CTRL1_DMA2ECC_MODE 11 +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 + +#define BF_GPMI_CTRL1_DMA2ECC_MODE(v) (((v) << 11) & BM_GPMI_CTRL1_DMA2ECC_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DMA2ECC_MODE(v) BF_CS1(GPMI_CTRL1, DMA2ECC_MODE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field DEV_IRQ */ + +#define BP_GPMI_CTRL1_DEV_IRQ 10 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 + +#define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & BM_GPMI_CTRL1_DEV_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DEV_IRQ(v) BF_CS1(GPMI_CTRL1, DEV_IRQ, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field TIMEOUT_IRQ */ + +#define BP_GPMI_CTRL1_TIMEOUT_IRQ 9 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 + +#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & BM_GPMI_CTRL1_TIMEOUT_IRQ) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_TIMEOUT_IRQ(v) BF_CS1(GPMI_CTRL1, TIMEOUT_IRQ, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field BURST_EN */ + +#define BP_GPMI_CTRL1_BURST_EN 8 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 + +#define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & BM_GPMI_CTRL1_BURST_EN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_BURST_EN(v) BF_CS1(GPMI_CTRL1, BURST_EN, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field ABORT_WAIT_REQUEST */ + +#define BP_GPMI_CTRL1_ABORT_WAIT_REQUEST 7 +#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080 + +#define BF_GPMI_CTRL1_ABORT_WAIT_REQUEST(v) (((v) << 7) & BM_GPMI_CTRL1_ABORT_WAIT_REQUEST) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_ABORT_WAIT_REQUEST(v) BF_CS1(GPMI_CTRL1, ABORT_WAIT_REQUEST, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field ABORT_WAIT_FOR_READY_CHANNEL */ + +#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070 + +#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) BF_CS1(GPMI_CTRL1, ABORT_WAIT_FOR_READY_CHANNEL, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field DEV_RESET */ + +#define BP_GPMI_CTRL1_DEV_RESET 3 +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 + +#define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & BM_GPMI_CTRL1_DEV_RESET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_DEV_RESET(v) BF_CS1(GPMI_CTRL1, DEV_RESET, v) +#endif + +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 + +/* --- Register HW_GPMI_CTRL1, field ATA_IRQRDY_POLARITY */ + +#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 + +#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) BF_CS1(GPMI_CTRL1, ATA_IRQRDY_POLARITY, v) +#endif + +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 + +/* --- Register HW_GPMI_CTRL1, field CAMERA_MODE */ + +#define BP_GPMI_CTRL1_CAMERA_MODE 1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 + +#define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & BM_GPMI_CTRL1_CAMERA_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_CAMERA_MODE(v) BF_CS1(GPMI_CTRL1, CAMERA_MODE, v) +#endif + +/* --- Register HW_GPMI_CTRL1, field GPMI_MODE */ + +#define BP_GPMI_CTRL1_GPMI_MODE 0 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 + +#define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & BM_GPMI_CTRL1_GPMI_MODE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_CTRL1_GPMI_MODE(v) BF_CS1(GPMI_CTRL1, GPMI_MODE, v) +#endif + +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 + +/* + * HW_GPMI_TIMING0 - GPMI Timing Register 0 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA_SETUP:8; + unsigned DATA_HOLD:8; + unsigned ADDRESS_SETUP:8; + unsigned RSVD1:8; + } B; +} hw_gpmi_timing0_t; +#endif + +/* + * constants & macros for entire HW_GPMI_TIMING0 register + */ +#define HW_GPMI_TIMING0_ADDR (0x00112070) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_TIMING0 (*(volatile hw_gpmi_timing0_t *) HW_GPMI_TIMING0_ADDR) +#define HW_GPMI_TIMING0_RD() (HW_GPMI_TIMING0.U) +#define HW_GPMI_TIMING0_WR(v) (HW_GPMI_TIMING0.U = (v)) +#define HW_GPMI_TIMING0_SET(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() | (v))) +#define HW_GPMI_TIMING0_CLR(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() & ~(v))) +#define HW_GPMI_TIMING0_TOG(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() ^ (v))) +#else +#define HW_GPMI_TIMING0_RD() (_rbase->mem32_read(HW_GPMI_TIMING0_ADDR)) +#define HW_GPMI_TIMING0_WR(v) (_rbase->mem32_write(HW_GPMI_TIMING0_ADDR,(v))) +#define HW_GPMI_TIMING0_SET(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() | (v))) +#define HW_GPMI_TIMING0_CLR(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() & ~(v))) +#define HW_GPMI_TIMING0_TOG(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_TIMING0 bitfields + */ +/* --- Register HW_GPMI_TIMING0, field RSVD1 */ + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_TIMING0_RSVD1(v) ((((reg32_t) v) << 24) & BM_GPMI_TIMING0_RSVD1) +#else +#define BF_GPMI_TIMING0_RSVD1(v) (((v) << 24) & BM_GPMI_TIMING0_RSVD1) +#endif +/* --- Register HW_GPMI_TIMING0, field ADDRESS_SETUP */ + +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 + +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING0_ADDRESS_SETUP(v) (HW_GPMI_TIMING0.B.ADDRESS_SETUP = (v)) +#endif + +/* --- Register HW_GPMI_TIMING0, field DATA_HOLD */ + +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 + +#define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING0_DATA_HOLD(v) (HW_GPMI_TIMING0.B.DATA_HOLD = (v)) +#endif + +/* --- Register HW_GPMI_TIMING0, field DATA_SETUP */ + +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF + +#define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING0_DATA_SETUP(v) (HW_GPMI_TIMING0.B.DATA_SETUP = (v)) +#endif + +/* + * HW_GPMI_TIMING1 - GPMI Timing Register 1 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RSVD1:16; + unsigned DEVICE_BUSY_TIMEOUT:16; + } B; +} hw_gpmi_timing1_t; +#endif + +/* + * constants & macros for entire HW_GPMI_TIMING1 register + */ +#define HW_GPMI_TIMING1_ADDR (0x00112080) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_TIMING1 (*(volatile hw_gpmi_timing1_t *) HW_GPMI_TIMING1_ADDR) +#define HW_GPMI_TIMING1_RD() (HW_GPMI_TIMING1.U) +#define HW_GPMI_TIMING1_WR(v) (HW_GPMI_TIMING1.U = (v)) +#define HW_GPMI_TIMING1_SET(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() | (v))) +#define HW_GPMI_TIMING1_CLR(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() & ~(v))) +#define HW_GPMI_TIMING1_TOG(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() ^ (v))) +#else +#define HW_GPMI_TIMING1_RD() (_rbase->mem32_read(HW_GPMI_TIMING1_ADDR)) +#define HW_GPMI_TIMING1_WR(v) (_rbase->mem32_write(HW_GPMI_TIMING1_ADDR,(v))) +#define HW_GPMI_TIMING1_SET(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() | (v))) +#define HW_GPMI_TIMING1_CLR(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() & ~(v))) +#define HW_GPMI_TIMING1_TOG(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_TIMING1 bitfields + */ +/* --- Register HW_GPMI_TIMING1, field DEVICE_BUSY_TIMEOUT */ + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) ((((reg32_t) v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#else +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (HW_GPMI_TIMING1.B.DEVICE_BUSY_TIMEOUT = (v)) +#endif + +/* --- Register HW_GPMI_TIMING1, field RSVD1 */ + +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF + +#define BF_GPMI_TIMING1_RSVD1(v) (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +/* + * HW_GPMI_TIMING2 - GPMI Timing Register 2 + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA_PAUSE:4; + unsigned CMDADD_PAUSE:4; + unsigned POSTAMBLE_DELAY:4; + unsigned PREAMBLE_DELAY:4; + unsigned CE_DELAY:5; + unsigned RSVD0:3; + unsigned READ_LATENCY:3; + unsigned RSVD1:5; + } B; +} hw_gpmi_timing2_t; +#endif + +/* + * constants & macros for entire HW_GPMI_TIMING2 register + */ +#define HW_GPMI_TIMING2_ADDR (0x00112090) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_TIMING2 (*(volatile hw_gpmi_timing2_t *) HW_GPMI_TIMING2_ADDR) +#define HW_GPMI_TIMING2_RD() (HW_GPMI_TIMING2.U) +#define HW_GPMI_TIMING2_WR(v) (HW_GPMI_TIMING2.U = (v)) +#define HW_GPMI_TIMING2_SET(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() | (v))) +#define HW_GPMI_TIMING2_CLR(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() & ~(v))) +#define HW_GPMI_TIMING2_TOG(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() ^ (v))) +#else +#define HW_GPMI_TIMING2_RD() (_rbase->mem32_read(HW_GPMI_TIMING2_ADDR)) +#define HW_GPMI_TIMING2_WR(v) (_rbase->mem32_write(HW_GPMI_TIMING2_ADDR,(v))) +#define HW_GPMI_TIMING2_SET(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() | (v))) +#define HW_GPMI_TIMING2_CLR(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() & ~(v))) +#define HW_GPMI_TIMING2_TOG(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_TIMING2 bitfields + */ +/* --- Register HW_GPMI_TIMING2, field RSVD1 */ + +#define BP_GPMI_TIMING2_RSVD1 27 +#define BM_GPMI_TIMING2_RSVD1 0xF8000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_TIMING2_RSVD1(v) ((((reg32_t) v) << 27) & BM_GPMI_TIMING2_RSVD1) +#else +#define BF_GPMI_TIMING2_RSVD1(v) (((v) << 27) & BM_GPMI_TIMING2_RSVD1) +#endif +/* --- Register HW_GPMI_TIMING2, field READ_LATENCY */ + +#define BP_GPMI_TIMING2_READ_LATENCY 24 +#define BM_GPMI_TIMING2_READ_LATENCY 0x07000000 + +#define BF_GPMI_TIMING2_READ_LATENCY(v) (((v) << 24) & BM_GPMI_TIMING2_READ_LATENCY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_READ_LATENCY(v) BF_CS1(GPMI_TIMING2, READ_LATENCY, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field RSVD0 */ + +#define BP_GPMI_TIMING2_RSVD0 21 +#define BM_GPMI_TIMING2_RSVD0 0x00E00000 + +#define BF_GPMI_TIMING2_RSVD0(v) (((v) << 21) & BM_GPMI_TIMING2_RSVD0) +/* --- Register HW_GPMI_TIMING2, field CE_DELAY */ + +#define BP_GPMI_TIMING2_CE_DELAY 16 +#define BM_GPMI_TIMING2_CE_DELAY 0x001F0000 + +#define BF_GPMI_TIMING2_CE_DELAY(v) (((v) << 16) & BM_GPMI_TIMING2_CE_DELAY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_CE_DELAY(v) BF_CS1(GPMI_TIMING2, CE_DELAY, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field PREAMBLE_DELAY */ + +#define BP_GPMI_TIMING2_PREAMBLE_DELAY 12 +#define BM_GPMI_TIMING2_PREAMBLE_DELAY 0x0000F000 + +#define BF_GPMI_TIMING2_PREAMBLE_DELAY(v) (((v) << 12) & BM_GPMI_TIMING2_PREAMBLE_DELAY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_PREAMBLE_DELAY(v) BF_CS1(GPMI_TIMING2, PREAMBLE_DELAY, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field POSTAMBLE_DELAY */ + +#define BP_GPMI_TIMING2_POSTAMBLE_DELAY 8 +#define BM_GPMI_TIMING2_POSTAMBLE_DELAY 0x00000F00 + +#define BF_GPMI_TIMING2_POSTAMBLE_DELAY(v) (((v) << 8) & BM_GPMI_TIMING2_POSTAMBLE_DELAY) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_POSTAMBLE_DELAY(v) BF_CS1(GPMI_TIMING2, POSTAMBLE_DELAY, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field CMDADD_PAUSE */ + +#define BP_GPMI_TIMING2_CMDADD_PAUSE 4 +#define BM_GPMI_TIMING2_CMDADD_PAUSE 0x000000F0 + +#define BF_GPMI_TIMING2_CMDADD_PAUSE(v) (((v) << 4) & BM_GPMI_TIMING2_CMDADD_PAUSE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_CMDADD_PAUSE(v) BF_CS1(GPMI_TIMING2, CMDADD_PAUSE, v) +#endif + +/* --- Register HW_GPMI_TIMING2, field DATA_PAUSE */ + +#define BP_GPMI_TIMING2_DATA_PAUSE 0 +#define BM_GPMI_TIMING2_DATA_PAUSE 0x0000000F + +#define BF_GPMI_TIMING2_DATA_PAUSE(v) (((v) << 0) & BM_GPMI_TIMING2_DATA_PAUSE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_TIMING2_DATA_PAUSE(v) BF_CS1(GPMI_TIMING2, DATA_PAUSE, v) +#endif + +/* + * HW_GPMI_DATA - GPMI DMA Data Transfer Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DATA:32; + } B; +} hw_gpmi_data_t; +#endif + +/* + * constants & macros for entire HW_GPMI_DATA register + */ +#define HW_GPMI_DATA_ADDR (0x001120a0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_DATA (*(volatile hw_gpmi_data_t *) HW_GPMI_DATA_ADDR) +#define HW_GPMI_DATA_RD() (HW_GPMI_DATA.U) +#define HW_GPMI_DATA_WR(v) (HW_GPMI_DATA.U = (v)) +#define HW_GPMI_DATA_SET(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() | (v))) +#define HW_GPMI_DATA_CLR(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() & ~(v))) +#define HW_GPMI_DATA_TOG(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() ^ (v))) +#else +#define HW_GPMI_DATA_RD() (_rbase->mem32_read(HW_GPMI_DATA_ADDR)) +#define HW_GPMI_DATA_WR(v) (_rbase->mem32_write(HW_GPMI_DATA_ADDR,(v))) +#define HW_GPMI_DATA_SET(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() | (v))) +#define HW_GPMI_DATA_CLR(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() & ~(v))) +#define HW_GPMI_DATA_TOG(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_DATA bitfields + */ +/* --- Register HW_GPMI_DATA, field DATA */ + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_DATA_DATA(v) ((reg32_t) v) +#else +#define BF_GPMI_DATA_DATA(v) (v) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_DATA_DATA(v) (HW_GPMI_DATA.B.DATA = (v)) +#endif + +/* + * HW_GPMI_STAT - GPMI Status Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned PRESENT:1; + unsigned FIFO_FULL:1; + unsigned FIFO_EMPTY:1; + unsigned INVALID_BUFFER_MASK:1; + unsigned ATA_IRQ:1; + unsigned RSVD1:3; + unsigned DEV0_ERROR:1; + unsigned DEV1_ERROR:1; + unsigned DEV2_ERROR:1; + unsigned DEV3_ERROR:1; + unsigned DEV4_ERROR:1; + unsigned DEV5_ERROR:1; + unsigned DEV6_ERROR:1; + unsigned DEV7_ERROR:1; + unsigned RDY_TIMEOUT:8; + unsigned READY_BUSY:8; + } B; +} hw_gpmi_stat_t; +#endif + +/* + * constants & macros for entire HW_GPMI_STAT register + */ +#define HW_GPMI_STAT_ADDR (0x001120b0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_STAT (*(volatile hw_gpmi_stat_t *) HW_GPMI_STAT_ADDR) +#define HW_GPMI_STAT_RD() (HW_GPMI_STAT.U) +#else +#define HW_GPMI_STAT_RD() (_rbase->mem32_read(HW_GPMI_STAT_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_STAT bitfields + */ +/* --- Register HW_GPMI_STAT, field READY_BUSY */ + +#define BP_GPMI_STAT_READY_BUSY 24 +#define BM_GPMI_STAT_READY_BUSY 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_STAT_READY_BUSY(v) ((((reg32_t) v) << 24) & BM_GPMI_STAT_READY_BUSY) +#else +#define BF_GPMI_STAT_READY_BUSY(v) (((v) << 24) & BM_GPMI_STAT_READY_BUSY) +#endif +/* --- Register HW_GPMI_STAT, field RDY_TIMEOUT */ + +#define BP_GPMI_STAT_RDY_TIMEOUT 16 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000 + +#define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT) +/* --- Register HW_GPMI_STAT, field DEV7_ERROR */ + +#define BP_GPMI_STAT_DEV7_ERROR 15 +#define BM_GPMI_STAT_DEV7_ERROR 0x00008000 + +#define BF_GPMI_STAT_DEV7_ERROR(v) (((v) << 15) & BM_GPMI_STAT_DEV7_ERROR) +/* --- Register HW_GPMI_STAT, field DEV6_ERROR */ + +#define BP_GPMI_STAT_DEV6_ERROR 14 +#define BM_GPMI_STAT_DEV6_ERROR 0x00004000 + +#define BF_GPMI_STAT_DEV6_ERROR(v) (((v) << 14) & BM_GPMI_STAT_DEV6_ERROR) +/* --- Register HW_GPMI_STAT, field DEV5_ERROR */ + +#define BP_GPMI_STAT_DEV5_ERROR 13 +#define BM_GPMI_STAT_DEV5_ERROR 0x00002000 + +#define BF_GPMI_STAT_DEV5_ERROR(v) (((v) << 13) & BM_GPMI_STAT_DEV5_ERROR) +/* --- Register HW_GPMI_STAT, field DEV4_ERROR */ + +#define BP_GPMI_STAT_DEV4_ERROR 12 +#define BM_GPMI_STAT_DEV4_ERROR 0x00001000 + +#define BF_GPMI_STAT_DEV4_ERROR(v) (((v) << 12) & BM_GPMI_STAT_DEV4_ERROR) +/* --- Register HW_GPMI_STAT, field DEV3_ERROR */ + +#define BP_GPMI_STAT_DEV3_ERROR 11 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000800 + +#define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 11) & BM_GPMI_STAT_DEV3_ERROR) +/* --- Register HW_GPMI_STAT, field DEV2_ERROR */ + +#define BP_GPMI_STAT_DEV2_ERROR 10 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000400 + +#define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 10) & BM_GPMI_STAT_DEV2_ERROR) +/* --- Register HW_GPMI_STAT, field DEV1_ERROR */ + +#define BP_GPMI_STAT_DEV1_ERROR 9 +#define BM_GPMI_STAT_DEV1_ERROR 0x00000200 + +#define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 9) & BM_GPMI_STAT_DEV1_ERROR) +/* --- Register HW_GPMI_STAT, field DEV0_ERROR */ + +#define BP_GPMI_STAT_DEV0_ERROR 8 +#define BM_GPMI_STAT_DEV0_ERROR 0x00000100 + +#define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 8) & BM_GPMI_STAT_DEV0_ERROR) +/* --- Register HW_GPMI_STAT, field RSVD1 */ + +#define BP_GPMI_STAT_RSVD1 5 +#define BM_GPMI_STAT_RSVD1 0x000000E0 + +#define BF_GPMI_STAT_RSVD1(v) (((v) << 5) & BM_GPMI_STAT_RSVD1) +/* --- Register HW_GPMI_STAT, field ATA_IRQ */ + +#define BP_GPMI_STAT_ATA_IRQ 4 +#define BM_GPMI_STAT_ATA_IRQ 0x00000010 + +#define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 4) & BM_GPMI_STAT_ATA_IRQ) +/* --- Register HW_GPMI_STAT, field INVALID_BUFFER_MASK */ + +#define BP_GPMI_STAT_INVALID_BUFFER_MASK 3 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008 + +#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 3) & BM_GPMI_STAT_INVALID_BUFFER_MASK) +/* --- Register HW_GPMI_STAT, field FIFO_EMPTY */ + +#define BP_GPMI_STAT_FIFO_EMPTY 2 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004 + +#define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 2) & BM_GPMI_STAT_FIFO_EMPTY) +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 + +/* --- Register HW_GPMI_STAT, field FIFO_FULL */ + +#define BP_GPMI_STAT_FIFO_FULL 1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000002 + +#define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 1) & BM_GPMI_STAT_FIFO_FULL) +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 + +/* --- Register HW_GPMI_STAT, field PRESENT */ + +#define BP_GPMI_STAT_PRESENT 0 +#define BM_GPMI_STAT_PRESENT 0x00000001 + +#define BF_GPMI_STAT_PRESENT(v) (((v) << 0) & BM_GPMI_STAT_PRESENT) +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 + +/* + * HW_GPMI_DEBUG - GPMI Debug Information Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned CMD_END:8; + unsigned DMAREQ:8; + unsigned DMA_SENSE:8; + unsigned WAIT_FOR_READY_END:8; + } B; +} hw_gpmi_debug_t; +#endif + +/* + * constants & macros for entire HW_GPMI_DEBUG register + */ +#define HW_GPMI_DEBUG_ADDR (0x001120c0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_DEBUG (*(volatile hw_gpmi_debug_t *) HW_GPMI_DEBUG_ADDR) +#define HW_GPMI_DEBUG_RD() (HW_GPMI_DEBUG.U) +#else +#define HW_GPMI_DEBUG_RD() (_rbase->mem32_read(HW_GPMI_DEBUG_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_DEBUG bitfields + */ +/* --- Register HW_GPMI_DEBUG, field WAIT_FOR_READY_END */ + +#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) ((((reg32_t) v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#else +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#endif +/* --- Register HW_GPMI_DEBUG, field DMA_SENSE */ + +#define BP_GPMI_DEBUG_DMA_SENSE 16 +#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000 + +#define BF_GPMI_DEBUG_DMA_SENSE(v) (((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE) +/* --- Register HW_GPMI_DEBUG, field DMAREQ */ + +#define BP_GPMI_DEBUG_DMAREQ 8 +#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00 + +#define BF_GPMI_DEBUG_DMAREQ(v) (((v) << 8) & BM_GPMI_DEBUG_DMAREQ) +/* --- Register HW_GPMI_DEBUG, field CMD_END */ + +#define BP_GPMI_DEBUG_CMD_END 0 +#define BM_GPMI_DEBUG_CMD_END 0x000000FF + +#define BF_GPMI_DEBUG_CMD_END(v) (((v) << 0) & BM_GPMI_DEBUG_CMD_END) + +/* + * HW_GPMI_VERSION - GPMI Version Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned STEP:16; + unsigned MINOR:8; + unsigned MAJOR:8; + } B; +} hw_gpmi_version_t; +#endif + +/* + * constants & macros for entire HW_GPMI_VERSION register + */ +#define HW_GPMI_VERSION_ADDR (0x001120d0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_VERSION (*(volatile hw_gpmi_version_t *) HW_GPMI_VERSION_ADDR) +#define HW_GPMI_VERSION_RD() (HW_GPMI_VERSION.U) +#else +#define HW_GPMI_VERSION_RD() (_rbase->mem32_read(HW_GPMI_VERSION_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_VERSION bitfields + */ +/* --- Register HW_GPMI_VERSION, field MAJOR */ + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_VERSION_MAJOR(v) ((((reg32_t) v) << 24) & BM_GPMI_VERSION_MAJOR) +#else +#define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#endif +/* --- Register HW_GPMI_VERSION, field MINOR */ + +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 + +#define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & BM_GPMI_VERSION_MINOR) +/* --- Register HW_GPMI_VERSION, field STEP */ + +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF + +#define BF_GPMI_VERSION_STEP(v) (((v) << 0) & BM_GPMI_VERSION_STEP) + +/* + * HW_GPMI_DEBUG2 - GPMI Debug2 Information Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned RDN_TAP:6; + unsigned UPDATE_WINDOW:1; + unsigned VIEW_DELAYED_RDN:1; + unsigned SYND2GPMI_READY:1; + unsigned SYND2GPMI_VALID:1; + unsigned GPMI2SYND_READY:1; + unsigned GPMI2SYND_VALID:1; + unsigned SYND2GPMI_BE:4; + unsigned MAIN_STATE:4; + unsigned PIN_STATE:3; + unsigned BUSY:1; + unsigned UDMA_STATE:4; + unsigned RSVD1:4; + } B; +} hw_gpmi_debug2_t; +#endif + +/* + * constants & macros for entire HW_GPMI_DEBUG2 register + */ +#define HW_GPMI_DEBUG2_ADDR (0x001120e0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_DEBUG2 (*(volatile hw_gpmi_debug2_t *) HW_GPMI_DEBUG2_ADDR) +#define HW_GPMI_DEBUG2_RD() (HW_GPMI_DEBUG2.U) +#define HW_GPMI_DEBUG2_WR(v) (HW_GPMI_DEBUG2.U = (v)) +#define HW_GPMI_DEBUG2_SET(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() | (v))) +#define HW_GPMI_DEBUG2_CLR(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() & ~(v))) +#define HW_GPMI_DEBUG2_TOG(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() ^ (v))) +#else +#define HW_GPMI_DEBUG2_RD() (_rbase->mem32_read(HW_GPMI_DEBUG2_ADDR)) +#define HW_GPMI_DEBUG2_WR(v) (_rbase->mem32_write(HW_GPMI_DEBUG2_ADDR,(v))) +#define HW_GPMI_DEBUG2_SET(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() | (v))) +#define HW_GPMI_DEBUG2_CLR(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() & ~(v))) +#define HW_GPMI_DEBUG2_TOG(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_DEBUG2 bitfields + */ +/* --- Register HW_GPMI_DEBUG2, field RSVD1 */ + +#define BP_GPMI_DEBUG2_RSVD1 28 +#define BM_GPMI_DEBUG2_RSVD1 0xF0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_DEBUG2_RSVD1(v) ((((reg32_t) v) << 28) & BM_GPMI_DEBUG2_RSVD1) +#else +#define BF_GPMI_DEBUG2_RSVD1(v) (((v) << 28) & BM_GPMI_DEBUG2_RSVD1) +#endif +/* --- Register HW_GPMI_DEBUG2, field UDMA_STATE */ + +#define BP_GPMI_DEBUG2_UDMA_STATE 24 +#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000 + +#define BF_GPMI_DEBUG2_UDMA_STATE(v) (((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE) +/* --- Register HW_GPMI_DEBUG2, field BUSY */ + +#define BP_GPMI_DEBUG2_BUSY 23 +#define BM_GPMI_DEBUG2_BUSY 0x00800000 + +#define BF_GPMI_DEBUG2_BUSY(v) (((v) << 23) & BM_GPMI_DEBUG2_BUSY) +#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG2_BUSY__ENABLED 0x1 + +/* --- Register HW_GPMI_DEBUG2, field PIN_STATE */ + +#define BP_GPMI_DEBUG2_PIN_STATE 20 +#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000 + +#define BF_GPMI_DEBUG2_PIN_STATE(v) (((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE) +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7 + +/* --- Register HW_GPMI_DEBUG2, field MAIN_STATE */ + +#define BP_GPMI_DEBUG2_MAIN_STATE 16 +#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000 + +#define BF_GPMI_DEBUG2_MAIN_STATE(v) (((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE) +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA + +/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_BE */ + +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 + +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +/* --- Register HW_GPMI_DEBUG2, field GPMI2SYND_VALID */ + +#define BP_GPMI_DEBUG2_GPMI2SYND_VALID 11 +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 + +#define BF_GPMI_DEBUG2_GPMI2SYND_VALID(v) (((v) << 11) & BM_GPMI_DEBUG2_GPMI2SYND_VALID) +/* --- Register HW_GPMI_DEBUG2, field GPMI2SYND_READY */ + +#define BP_GPMI_DEBUG2_GPMI2SYND_READY 10 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 + +#define BF_GPMI_DEBUG2_GPMI2SYND_READY(v) (((v) << 10) & BM_GPMI_DEBUG2_GPMI2SYND_READY) +/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_VALID */ + +#define BP_GPMI_DEBUG2_SYND2GPMI_VALID 9 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 + +#define BF_GPMI_DEBUG2_SYND2GPMI_VALID(v) (((v) << 9) & BM_GPMI_DEBUG2_SYND2GPMI_VALID) +/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_READY */ + +#define BP_GPMI_DEBUG2_SYND2GPMI_READY 8 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 + +#define BF_GPMI_DEBUG2_SYND2GPMI_READY(v) (((v) << 8) & BM_GPMI_DEBUG2_SYND2GPMI_READY) +/* --- Register HW_GPMI_DEBUG2, field VIEW_DELAYED_RDN */ + +#define BP_GPMI_DEBUG2_VIEW_DELAYED_RDN 7 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 + +#define BF_GPMI_DEBUG2_VIEW_DELAYED_RDN(v) (((v) << 7) & BM_GPMI_DEBUG2_VIEW_DELAYED_RDN) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_DEBUG2_VIEW_DELAYED_RDN(v) BF_CS1(GPMI_DEBUG2, VIEW_DELAYED_RDN, v) +#endif + +/* --- Register HW_GPMI_DEBUG2, field UPDATE_WINDOW */ + +#define BP_GPMI_DEBUG2_UPDATE_WINDOW 6 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 + +#define BF_GPMI_DEBUG2_UPDATE_WINDOW(v) (((v) << 6) & BM_GPMI_DEBUG2_UPDATE_WINDOW) +/* --- Register HW_GPMI_DEBUG2, field RDN_TAP */ + +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F + +#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +/* + * HW_GPMI_DEBUG3 - GPMI Debug3 Information Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned DEV_WORD_CNTR:16; + unsigned APB_WORD_CNTR:16; + } B; +} hw_gpmi_debug3_t; +#endif + +/* + * constants & macros for entire HW_GPMI_DEBUG3 register + */ +#define HW_GPMI_DEBUG3_ADDR (0x001120f0) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_DEBUG3 (*(volatile hw_gpmi_debug3_t *) HW_GPMI_DEBUG3_ADDR) +#define HW_GPMI_DEBUG3_RD() (HW_GPMI_DEBUG3.U) +#else +#define HW_GPMI_DEBUG3_RD() (_rbase->mem32_read(HW_GPMI_DEBUG3_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_DEBUG3 bitfields + */ +/* --- Register HW_GPMI_DEBUG3, field APB_WORD_CNTR */ + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) ((((reg32_t) v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#else +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#endif +/* --- Register HW_GPMI_DEBUG3, field DEV_WORD_CNTR */ + +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF + +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +/* + * HW_GPMI_READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ENABLE:1; + unsigned RESET:1; + unsigned SLV_FORCE_UPD:1; + unsigned SLV_DLY_TARGET:4; + unsigned GATE_UPDATE:1; + unsigned REFCLK_ON:1; + unsigned SLV_OVERRIDE:1; + unsigned SLV_OVERRIDE_VAL:8; + unsigned RSVD1:2; + unsigned SLV_UPDATE_INT:8; + unsigned REF_UPDATE_INT:4; + } B; +} hw_gpmi_read_ddr_dll_ctrl_t; +#endif + +/* + * constants & macros for entire HW_GPMI_READ_DDR_DLL_CTRL register + */ +#define HW_GPMI_READ_DDR_DLL_CTRL_ADDR (0x00112100) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_READ_DDR_DLL_CTRL (*(volatile hw_gpmi_read_ddr_dll_ctrl_t *) HW_GPMI_READ_DDR_DLL_CTRL_ADDR) +#define HW_GPMI_READ_DDR_DLL_CTRL_RD() (HW_GPMI_READ_DDR_DLL_CTRL.U) +#define HW_GPMI_READ_DDR_DLL_CTRL_WR(v) (HW_GPMI_READ_DDR_DLL_CTRL.U = (v)) +#define HW_GPMI_READ_DDR_DLL_CTRL_SET(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() | (v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_CLR(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() & ~(v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_TOG(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() ^ (v))) +#else +#define HW_GPMI_READ_DDR_DLL_CTRL_RD() (_rbase->mem32_read(HW_GPMI_READ_DDR_DLL_CTRL_ADDR)) +#define HW_GPMI_READ_DDR_DLL_CTRL_WR(v) (_rbase->mem32_write(HW_GPMI_READ_DDR_DLL_CTRL_ADDR,(v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_SET(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() | (v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_CLR(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() & ~(v))) +#define HW_GPMI_READ_DDR_DLL_CTRL_TOG(v) (HW_GPMI_READ_DDR_DLL_CTRL_WR(HW_GPMI_READ_DDR_DLL_CTRL_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_READ_DDR_DLL_CTRL bitfields + */ +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field REF_UPDATE_INT */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) ((((reg32_t) v) << 28) & BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT) +#else +#define BF_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) (((v) << 28) & BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, REF_UPDATE_INT, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_UPDATE_INT */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(v) (((v) << 20) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_UPDATE_INT, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field RSVD1 */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_RSVD1 18 +#define BM_GPMI_READ_DDR_DLL_CTRL_RSVD1 0x000C0000 + +#define BF_GPMI_READ_DDR_DLL_CTRL_RSVD1(v) (((v) << 18) & BM_GPMI_READ_DDR_DLL_CTRL_RSVD1) +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_OVERRIDE_VAL */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) (((v) << 10) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_OVERRIDE_VAL, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_OVERRIDE */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE 9 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(v) (((v) << 9) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_OVERRIDE, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field REFCLK_ON */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON 8 +#define BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON 0x00000100 + +#define BF_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(v) (((v) << 8) & BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, REFCLK_ON, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field GATE_UPDATE */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE 7 +#define BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE 0x00000080 + +#define BF_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(v) (((v) << 7) & BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, GATE_UPDATE, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_DLY_TARGET */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(v) (((v) << 3) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_DLY_TARGET, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field SLV_FORCE_UPD */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD 2 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004 + +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(v) (((v) << 2) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, SLV_FORCE_UPD, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field RESET */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_RESET 1 +#define BM_GPMI_READ_DDR_DLL_CTRL_RESET 0x00000002 + +#define BF_GPMI_READ_DDR_DLL_CTRL_RESET(v) (((v) << 1) & BM_GPMI_READ_DDR_DLL_CTRL_RESET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_RESET(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, RESET, v) +#endif + +/* --- Register HW_GPMI_READ_DDR_DLL_CTRL, field ENABLE */ + +#define BP_GPMI_READ_DDR_DLL_CTRL_ENABLE 0 +#define BM_GPMI_READ_DDR_DLL_CTRL_ENABLE 0x00000001 + +#define BF_GPMI_READ_DDR_DLL_CTRL_ENABLE(v) (((v) << 0) & BM_GPMI_READ_DDR_DLL_CTRL_ENABLE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_READ_DDR_DLL_CTRL_ENABLE(v) BF_CS1(GPMI_READ_DDR_DLL_CTRL, ENABLE, v) +#endif + +/* + * HW_GPMI_WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned ENABLE:1; + unsigned RESET:1; + unsigned SLV_FORCE_UPD:1; + unsigned SLV_DLY_TARGET:4; + unsigned GATE_UPDATE:1; + unsigned REFCLK_ON:1; + unsigned SLV_OVERRIDE:1; + unsigned SLV_OVERRIDE_VAL:8; + unsigned RSVD1:2; + unsigned SLV_UPDATE_INT:8; + unsigned REF_UPDATE_INT:4; + } B; +} hw_gpmi_write_ddr_dll_ctrl_t; +#endif + +/* + * constants & macros for entire HW_GPMI_WRITE_DDR_DLL_CTRL register + */ +#define HW_GPMI_WRITE_DDR_DLL_CTRL_ADDR (0x00112110) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_WRITE_DDR_DLL_CTRL (*(volatile hw_gpmi_write_ddr_dll_ctrl_t *) HW_GPMI_WRITE_DDR_DLL_CTRL_ADDR) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_RD() (HW_GPMI_WRITE_DDR_DLL_CTRL.U) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_WR(v) (HW_GPMI_WRITE_DDR_DLL_CTRL.U = (v)) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_SET(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() | (v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_CLR(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() & ~(v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_TOG(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() ^ (v))) +#else +#define HW_GPMI_WRITE_DDR_DLL_CTRL_RD() (_rbase->mem32_read(HW_GPMI_WRITE_DDR_DLL_CTRL_ADDR)) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_WR(v) (_rbase->mem32_write(HW_GPMI_WRITE_DDR_DLL_CTRL_ADDR,(v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_SET(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() | (v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_CLR(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() & ~(v))) +#define HW_GPMI_WRITE_DDR_DLL_CTRL_TOG(v) (HW_GPMI_WRITE_DDR_DLL_CTRL_WR(HW_GPMI_WRITE_DDR_DLL_CTRL_RD() ^ (v))) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_WRITE_DDR_DLL_CTRL bitfields + */ +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field REF_UPDATE_INT */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) ((((reg32_t) v) << 28) & BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT) +#else +#define BF_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) (((v) << 28) & BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT) +#endif +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, REF_UPDATE_INT, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_UPDATE_INT */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(v) (((v) << 20) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_UPDATE_INT, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field RSVD1 */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 18 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 0x000C0000 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_RSVD1(v) (((v) << 18) & BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1) +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_OVERRIDE_VAL */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) (((v) << 10) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_OVERRIDE_VAL, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_OVERRIDE */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE 9 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(v) (((v) << 9) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_OVERRIDE, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field REFCLK_ON */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON 8 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON 0x00000100 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(v) (((v) << 8) & BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, REFCLK_ON, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field GATE_UPDATE */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE 7 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE 0x00000080 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(v) (((v) << 7) & BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, GATE_UPDATE, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_DLY_TARGET */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(v) (((v) << 3) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_DLY_TARGET, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field SLV_FORCE_UPD */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD 2 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(v) (((v) << 2) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, SLV_FORCE_UPD, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field RESET */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_RESET 1 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_RESET 0x00000002 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_RESET(v) (((v) << 1) & BM_GPMI_WRITE_DDR_DLL_CTRL_RESET) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_RESET(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, RESET, v) +#endif + +/* --- Register HW_GPMI_WRITE_DDR_DLL_CTRL, field ENABLE */ + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_ENABLE 0 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE 0x00000001 + +#define BF_GPMI_WRITE_DDR_DLL_CTRL_ENABLE(v) (((v) << 0) & BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE) +#ifndef __LANGUAGE_ASM__ +#define BW_GPMI_WRITE_DDR_DLL_CTRL_ENABLE(v) BF_CS1(GPMI_WRITE_DDR_DLL_CTRL, ENABLE, v) +#endif + +/* + * HW_GPMI_READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned SLV_LOCK:1; + unsigned SLV_SEL:8; + unsigned RSVD0:7; + unsigned REF_LOCK:1; + unsigned REF_SEL:8; + unsigned RSVD1:7; + } B; +} hw_gpmi_read_ddr_dll_sts_t; +#endif + +/* + * constants & macros for entire HW_GPMI_READ_DDR_DLL_STS register + */ +#define HW_GPMI_READ_DDR_DLL_STS_ADDR (0x00112120) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_READ_DDR_DLL_STS (*(volatile hw_gpmi_read_ddr_dll_sts_t *) HW_GPMI_READ_DDR_DLL_STS_ADDR) +#define HW_GPMI_READ_DDR_DLL_STS_RD() (HW_GPMI_READ_DDR_DLL_STS.U) +#else +#define HW_GPMI_READ_DDR_DLL_STS_RD() (_rbase->mem32_read(HW_GPMI_READ_DDR_DLL_STS_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_READ_DDR_DLL_STS bitfields + */ +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field RSVD1 */ + +#define BP_GPMI_READ_DDR_DLL_STS_RSVD1 25 +#define BM_GPMI_READ_DDR_DLL_STS_RSVD1 0xFE000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_READ_DDR_DLL_STS_RSVD1(v) ((((reg32_t) v) << 25) & BM_GPMI_READ_DDR_DLL_STS_RSVD1) +#else +#define BF_GPMI_READ_DDR_DLL_STS_RSVD1(v) (((v) << 25) & BM_GPMI_READ_DDR_DLL_STS_RSVD1) +#endif +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field REF_SEL */ + +#define BP_GPMI_READ_DDR_DLL_STS_REF_SEL 17 +#define BM_GPMI_READ_DDR_DLL_STS_REF_SEL 0x01FE0000 + +#define BF_GPMI_READ_DDR_DLL_STS_REF_SEL(v) (((v) << 17) & BM_GPMI_READ_DDR_DLL_STS_REF_SEL) +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field REF_LOCK */ + +#define BP_GPMI_READ_DDR_DLL_STS_REF_LOCK 16 +#define BM_GPMI_READ_DDR_DLL_STS_REF_LOCK 0x00010000 + +#define BF_GPMI_READ_DDR_DLL_STS_REF_LOCK(v) (((v) << 16) & BM_GPMI_READ_DDR_DLL_STS_REF_LOCK) +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field RSVD0 */ + +#define BP_GPMI_READ_DDR_DLL_STS_RSVD0 9 +#define BM_GPMI_READ_DDR_DLL_STS_RSVD0 0x0000FE00 + +#define BF_GPMI_READ_DDR_DLL_STS_RSVD0(v) (((v) << 9) & BM_GPMI_READ_DDR_DLL_STS_RSVD0) +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field SLV_SEL */ + +#define BP_GPMI_READ_DDR_DLL_STS_SLV_SEL 1 +#define BM_GPMI_READ_DDR_DLL_STS_SLV_SEL 0x000001FE + +#define BF_GPMI_READ_DDR_DLL_STS_SLV_SEL(v) (((v) << 1) & BM_GPMI_READ_DDR_DLL_STS_SLV_SEL) +/* --- Register HW_GPMI_READ_DDR_DLL_STS, field SLV_LOCK */ + +#define BP_GPMI_READ_DDR_DLL_STS_SLV_LOCK 0 +#define BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK 0x00000001 + +#define BF_GPMI_READ_DDR_DLL_STS_SLV_LOCK(v) (((v) << 0) & BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK) + +/* + * HW_GPMI_WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register + */ +#ifndef __LANGUAGE_ASM__ +typedef union { + reg32_t U; + struct { + unsigned SLV_LOCK:1; + unsigned SLV_SEL:8; + unsigned RSVD0:7; + unsigned REF_LOCK:1; + unsigned REF_SEL:8; + unsigned RSVD1:7; + } B; +} hw_gpmi_write_ddr_dll_sts_t; +#endif + +/* + * constants & macros for entire HW_GPMI_WRITE_DDR_DLL_STS register + */ +#define HW_GPMI_WRITE_DDR_DLL_STS_ADDR (0x00112130) + +#ifndef __LANGUAGE_ASM__ +#ifndef ROCOO_TEST +#define HW_GPMI_WRITE_DDR_DLL_STS (*(volatile hw_gpmi_write_ddr_dll_sts_t *) HW_GPMI_WRITE_DDR_DLL_STS_ADDR) +#define HW_GPMI_WRITE_DDR_DLL_STS_RD() (HW_GPMI_WRITE_DDR_DLL_STS.U) +#else +#define HW_GPMI_WRITE_DDR_DLL_STS_RD() (_rbase->mem32_read(HW_GPMI_WRITE_DDR_DLL_STS_ADDR)) +#endif +#endif + +/* + * constants & macros for individual HW_GPMI_WRITE_DDR_DLL_STS bitfields + */ +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field RSVD1 */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD1 25 +#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD1 0xFE000000 + +#ifndef __LANGUAGE_ASM__ +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD1(v) ((((reg32_t) v) << 25) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD1) +#else +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD1(v) (((v) << 25) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD1) +#endif +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field REF_SEL */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_REF_SEL 17 +#define BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL 0x01FE0000 + +#define BF_GPMI_WRITE_DDR_DLL_STS_REF_SEL(v) (((v) << 17) & BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL) +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field REF_LOCK */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_REF_LOCK 16 +#define BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK 0x00010000 + +#define BF_GPMI_WRITE_DDR_DLL_STS_REF_LOCK(v) (((v) << 16) & BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK) +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field RSVD0 */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD0 9 +#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD0 0x0000FE00 + +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD0(v) (((v) << 9) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD0) +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field SLV_SEL */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 1 +#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 0x000001FE + +#define BF_GPMI_WRITE_DDR_DLL_STS_SLV_SEL(v) (((v) << 1) & BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL) +/* --- Register HW_GPMI_WRITE_DDR_DLL_STS, field SLV_LOCK */ + +#define BP_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK 0 +#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK 0x00000001 + +#define BF_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(v) (((v) << 0) & BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK) + +#endif /* _GPMI_H */ + +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/mx6ul/soc_memory_map.h b/bsp/imx6ul/platform/include/mx6ul/soc_memory_map.h new file mode 100644 index 0000000000000000000000000000000000000000..7c126b2384cb0a4487a81361566de1a49976533d --- /dev/null +++ b/bsp/imx6ul/platform/include/mx6ul/soc_memory_map.h @@ -0,0 +1,103 @@ +#ifndef _SOC_MEMORY_MAP_H +#define _SOC_MEMORY_MAP_H + +#define ANATOP_IPS_BASE_ADDR 0x020c8000 + +#define ADC1_BASE_ADDR 0x02198000 +#define ADC2_BASE_ADDR 0x0219c000 +#define APBH_BASE_ADDR 0x01804000 +#define ASRC_BASE_ADDR 0x02034000 +#define BCH_BASE_ADDR 0x01808000 +#define CCM_BASE_ADDR 0x020c4000 +#define CCM_ANALOG_BASE_ADDR 0x020c8000 +#define CSI_BASE_ADDR 0x021c4000 +#define ECSPI1_BASE_ADDR 0x02008000 +#define ECSPI2_BASE_ADDR 0x0200c000 +#define ECSPI3_BASE_ADDR 0x02010000 +#define ECSPI4_BASE_ADDR 0x02014000 +#define EIM_BASE_ADDR 0x021b8000 +#define EMVSIM1_BASE_ADDR 0x0218c000 +#define EMVSIM2_BASE_ADDR 0x021b4000 +#define ENET1_BASE_ADDR 0x02188000 +#define ENET2_BASE_ADDR 0x020b4000 +#define EPIT1_BASE_ADDR 0x020d0000 +#define EPIT2_BASE_ADDR 0x020d4000 +#define FLEXCAN1_BASE_ADDR 0x02090000 +#define FLEXCAN2_BASE_ADDR 0x02094000 +#define GPC_BASE_ADDR 0x020dc000 +#define GPIO1_BASE_ADDR 0x0209c000 +#define GPIO2_BASE_ADDR 0x020a0000 +#define GPIO3_BASE_ADDR 0x020a4000 +#define GPIO4_BASE_ADDR 0x020a8000 +#define GPIO5_BASE_ADDR 0x020ac000 +#define GPMI_BASE_ADDR 0x01806000 +#define GPT1_BASE_ADDR 0x02098000 +#define GPT2_BASE_ADDR 0x020e8000 +#define I2C1_BASE_ADDR 0x021a0000 +#define I2C2_BASE_ADDR 0x021a4000 +#define I2C3_BASE_ADDR 0x021a8000 +#define I2C4_BASE_ADDR 0x021f8000 +#define I2S1_BASE_ADDR 0x02028000 +#define I2S2_BASE_ADDR 0x0202c000 +#define I2S3_BASE_ADDR 0x02030000 +#define IOMUXC_BASE_ADDR 0x020e0000 +#define IOMUXC_GPR_BASE_ADDR 0x020e4000 +#define KPP_BASE_ADDR 0x020b8000 +#define LCDIF1_BASE_ADDR 0x02220000 +#define LCDIF2_BASE_ADDR 0x02224000 +#define MMDC_BASE_ADDR 0x021b0000 +#define OCOTP_BASE_ADDR 0x021bc000 +#define PMU_BASE_ADDR 0x020c8000 +#define PWM1_BASE_ADDR 0x02080000 +#define PWM2_BASE_ADDR 0x02084000 +#define PWM3_BASE_ADDR 0x02088000 +#define PWM4_BASE_ADDR 0x0208c000 +#define PWM5_BASE_ADDR 0x020f0000 +#define PWM6_BASE_ADDR 0x020f4000 +#define PWM7_BASE_ADDR 0x020f8000 +#define PWM8_BASE_ADDR 0x020fc000 +#define PXP_BASE_ADDR 0x021cc000 +#define QUADSPI_BASE_ADDR 0x021e0000 +#define ROMC_BASE_ADDR 0x021ac000 +#define SDMAARM_BASE_ADDR 0x020ec000 +#define SDMABP_BASE_ADDR 0x020ec000 +#define SDMACORE_BASE_ADDR 0x020ec000 +#define SJC_BASE_ADDR 0x00000000 +#define SNVS_BASE_ADDR 0x020cc000 +#define SPBA_BASE_ADDR 0x0203c000 +#define SPDIF_BASE_ADDR 0x02004000 +#define SRC_BASE_ADDR 0x020d8000 +#define TEMPMON_BASE_ADDR 0x020c8000 +#define UART1_BASE_ADDR 0x02020000 +#define UART2_BASE_ADDR 0x021e8000 +#define UART3_BASE_ADDR 0x021ec000 +#define UART4_BASE_ADDR 0x021f0000 +#define UART5_BASE_ADDR 0x021f4000 +#define UART6_BASE_ADDR 0x021fc000 +#define UART7_BASE_ADDR 0x02018000 +#define UART8_BASE_ADDR 0x02024000 +#define USB_BASE_ADDR 0x02184000 +#define USBNC_BASE_ADDR 0x02184000 +#define USBPHY1_BASE_ADDR 0x020c9000 +#define USBPHY2_BASE_ADDR 0x020ca000 +#define USDHC1_BASE_ADDR 0x02190000 +#define USDHC2_BASE_ADDR 0x02194000 +#define WDOG1_BASE_ADDR 0x020bc000 +#define WDOG2_BASE_ADDR 0x020c0000 +#define WDOG3_BASE_ADDR 0x021e4000 +#define XTALOSC24M_BASE_ADDR 0x020c8000 + +#define USB_UOG1_BASE_ADDR USB_BASE_ADDR +#define USB_UOG2_BASE_ADDR (USB_BASE_ADDR+0x200) + +#define CCM_ANALOG_PLL_USB1n (CCM_ANALOG_BASE_ADDR+0x10) +#define CCM_ANALOG_PFD_528n (CCM_ANALOG_BASE_ADDR+0x100) + +#define CAN0_BASE_ADDR FLEXCAN1_BASE_ADDR +#define CAN1_BASE_ADDR FLEXCAN2_BASE_ADDR +#define CSD0_BASE_ADDR 0x80000000 + +#define MMDC_P0_BASE_ADDR MMDC_BASE_ADDR + + +#endif //_SOC_MEMORY_MAP_H diff --git a/bsp/imx6ul/platform/include/sdk.h b/bsp/imx6ul/platform/include/sdk.h new file mode 100644 index 0000000000000000000000000000000000000000..eeea34c7bf01697af13a027216b3b2c92b397040 --- /dev/null +++ b/bsp/imx6ul/platform/include/sdk.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file sdk.h + * @brief Basic defines + * + * @ingroup diag_init + */ +#ifndef __SDK_H__ +#define __SDK_H__ + +#include +#include +#include +#include + +#include "sdk_types.h" +#include "sdk_version.h" +#include "io.h" + +#include "soc_memory_map.h" +#include "registers.h" +#include "iomux_define.h" +#include "iomux_register.h" +#include "interrupt.h" + +#include "gic.h" +#include "ccm_pll.h" +#include "imx_i2c.h" +#include "imx_timer.h" +#include "imx_uart.h" + +#endif // __SDK_H__ diff --git a/bsp/imx6ul/platform/include/sdk_types.h b/bsp/imx6ul/platform/include/sdk_types.h new file mode 100644 index 0000000000000000000000000000000000000000..0b7bc4b7677cc59835911032ce4f61a53df308dd --- /dev/null +++ b/bsp/imx6ul/platform/include/sdk_types.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SDK_TYPES_H__ +#define __SDK_TYPES_H__ + +//! @addtogroup sdk_common +//! @{ + +/*! + * @file sdk_types.h + * @brief Basic types used throughout the SDK. + */ + +#include +#include +#include +#include + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @name Alternate Boolean constants +//@{ +#define TRUE 1 +#define FALSE 0 +//@} + +//! @brief +#define NONE_CHAR (0xFF) + +//! @brief A parameter was out of range or otherwise invalid. +#define INVALID_PARAMETER (-1) + +//! @name Min/max macros +//@{ +#if !defined(MIN) + #define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) + #define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +//@} + +//! @brief Computes the number of elements in an array. +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +//! @brief Debug print utility. +//! +//! This print function will only output text when the @a DEBUG macro is defined. +static inline void debug_printf(const char * format, ...) +{ +#if defined(DEBUG) + va_list args; + va_start(args, format); + vprintf(format, args); + va_end(args); +#endif +} + +//! @name Test results +typedef enum _test_return +{ + TEST_NOT_STARTED = -3, // present in the menu, but not run + TEST_NOT_IMPLEMENTED = -2, // present in the menu, but not functional + TEST_FAILED = -1, + TEST_PASSED = 0, + TEST_BYPASSED = 2, // user elected to exit the test before it was run + TEST_NOT_PRESENT = 3, // not present in the menu. + TEST_CONTINUE = 4 // proceed with the test. opposite of TEST_BYPASSED +} test_return_t; + +//! @name Return codes +//@{ +#define SUCCESS (0) +#define FAIL (1) +#define ERROR_GENERIC (-1) +#define ERROR_OUT_OF_MEMORY (-2) +//@} + +//! @brief Possible types of displays. +enum display_type { + DISP_DEV_NULL = 0, + DISP_DEV_TFTLCD, + DISP_DEV_LVDS, + DISP_DEV_VGA, + DISP_DEV_HDMI, + DISP_DEV_TV, + DISP_DEV_MIPI, +}; + +//! @} + +#endif // __SDK_TYPES_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/platform/include/sdk_version.h b/bsp/imx6ul/platform/include/sdk_version.h new file mode 100644 index 0000000000000000000000000000000000000000..e6917f9a432dc4f683b0a9bd35002e1d17281073 --- /dev/null +++ b/bsp/imx6ul/platform/include/sdk_version.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2008-2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file sdk_version.h + * @brief SDK release version defines. + * + * @ingroup diag_util + */ + +#if !defined(__SDK_VERSION_H__) +#define __SDK_VERSION_H__ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Current version of the SDK. +#define SDK_VERSION_STRING "1.2" + +//! @name SDK version number components +//@{ +#define SDK_VERSION_MAJOR 1 +#define SDK_VERSION_MINOR 1 +#define SDK_VERSION_BUGFIX 0 +//@} + +//! @brief Current version of the SDK. +extern const char k_sdk_version[]; + +//! @brief Copyright string for the SDK. +extern const char k_sdk_copyright[]; + +#endif // __SDK_VERSION_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/imx6ul/rtconfig.h b/bsp/imx6ul/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..f37f620a9c5fa510b5f3fe6be2897a769a16248c --- /dev/null +++ b/bsp/imx6ul/rtconfig.h @@ -0,0 +1,194 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// + +// +#define RT_NAME_MAX 6 +// +#define RT_ALIGN_SIZE 4 +// +// 8 +// 32 +// 256 +// +#define RT_THREAD_PRIORITY_MAX 32 +// +#define RT_TICK_PER_SECOND 1000 +// +#define IDLE_THREAD_STACK_SIZE 512 +//
+#define RT_DEBUG +// +// #define RT_DEBUG_SCHEDULER 1 +// +#define RT_USING_OVERFLOW_CHECK +//
+ +// +#define RT_USING_HOOK +//
+// #define RT_USING_TIMER_SOFT +// +#define RT_TIMER_THREAD_PRIO 4 +// +#define RT_TIMER_THREAD_STACK_SIZE 512 +// +#define RT_TIMER_TICK_PER_SECOND 10 +//
+ +//
+// +#define RT_USING_SEMAPHORE +// +#define RT_USING_MUTEX +// +#define RT_USING_EVENT +// +#define RT_USING_MAILBOX +// +#define RT_USING_MESSAGEQUEUE +//
+ +//
+// +#define RT_USING_MEMPOOL +// +// #define RT_USING_MEMHEAP +// +#define RT_USING_HEAP +// +// #define RT_USING_MEMHEAP_AS_HEAP +// +#define RT_USING_SMALL_MEM +// +// #define RT_USING_SLAB +//
+ +//
+#define RT_USING_DEVICE +// +#define RT_USING_DEVICE_IPC +// +#define RT_USING_SERIAL +// +#define RT_UART_RX_BUFFER_SIZE 64 +// +#define RT_USING_INTERRUPT_INFO +// +// #define RT_USING_UART0 +// +#define RT_USING_UART1 +//
+ +//
+#define RT_USING_CONSOLE +// +#define RT_CONSOLEBUF_SIZE 128 +// +#define RT_CONSOLE_DEVICE_NAME "uart1" +//
+ +// +#define RT_USING_COMPONENTS_INIT +//
+#define RT_USING_FINSH +// +#define FINSH_USING_MSH +// +#define FINSH_USING_MSH_DEFAULT +// +#define FINSH_USING_SYMTAB +// +#define FINSH_USING_DESCRIPTION +// +#define FINSH_THREAD_STACK_SIZE 4096 +//
+ +//
+// +#define RT_USING_LIBC +// +#define RT_USING_PTHREADS +//
+ +//
+// #define RT_USING_DFS +// +#define DFS_USING_WORKDIR +// +#define DFS_FILESYSTEMS_MAX 2 +// +#define DFS_FD_MAX 4 +// +// #define RT_USING_DFS_ELMFAT +// +// 1 +// 2 +// +#define RT_DFS_ELM_USE_LFN 1 +// +#define RT_DFS_ELM_MAX_LFN 64 +// +// #define RT_USING_DFS_YAFFS2 +// +// #define RT_USING_DFS_UFFS +// +#define RT_USING_DFS_DEVFS +// +// #define RT_USING_DFS_NFS +// +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +//
+ +//
+// #define RT_USING_LWIP +// +#define RT_LWIP_ICMP +// +// #define RT_LWIP_IGMP +// +#define RT_LWIP_UDP +// +#define RT_LWIP_TCP +// +#define RT_LWIP_DNS +// +// #define RT_LWIP_SNMP +// +#define RT_LWIP_DHCP +// +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +// +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +// +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +// +#define RT_LWIP_ETHTHREAD_PRIORITY 14 +// +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +// +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +// +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 +// +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 +// +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 +//
+ +#define RT_USING_LOGTRACE + +// + +#endif diff --git a/bsp/imx6ul/rtconfig.py b/bsp/imx6ul/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..3dcd1ca04cf01aef50c23b7b36758241ee559ed9 --- /dev/null +++ b/bsp/imx6ul/rtconfig.py @@ -0,0 +1,101 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-a' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp' + CFLAGS = DEVICE + ' -Wall' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LINK_SCRIPT = 'imx6.lds' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-imx6.map,-cref,-u,system_vectors'+\ + ' -T %s' % LINK_SCRIPT + + CPATH = '' + LPATH = '' + + # generate debug info in all cases + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -g -gdwarf-2' + + if BUILD == 'debug': + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMP' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imx6.map --scatter imx6.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' --cpu DARMP' + + CFLAGS = '' + AFLAGS = '' + LFLAGS = ' --config imx6.icf' + + EXEC_PATH += '/arm/bin/' + RT_USING_MINILIBC = False + POST_ACTION = '' diff --git a/libcpu/Kconfig b/libcpu/Kconfig index 0358141576833bdcfedf694936a758ba510bc467..0279ca1bcfc3bee76074cee8cb032311ecf8e22c 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -33,21 +33,25 @@ config ARCH_ARM_MMU bool depends on ARCH_ARM -config ARCH_ARM_CORTEX_A5 +config ARCH_ARM_CORTEX_A bool select ARCH_ARM +config ARCH_ARM_CORTEX_A5 + bool + select ARCH_ARM_CORTEX_A + config ARCH_ARM_CORTEX_A7 bool - select ARCH_ARM + select ARCH_ARM_CORTEX_A config ARCH_ARM_CORTEX_A8 bool - select ARCH_ARM + select ARCH_ARM_CORTEX_A config ARCH_ARM_CORTEX_A9 bool - select ARCH_ARM + select ARCH_ARM_CORTEX_A config ARCH_MIPS bool diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..69c556eb3c7eba4d87df16249afb218db576dfb2 --- /dev/null +++ b/libcpu/arm/cortex-a/armv7.h @@ -0,0 +1,64 @@ +#ifndef __ARMV7_H__ +#define __ARMV7_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +struct rt_hw_stack +{ + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +#endif diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..01593a7c0aa40e88c83b69324369ca1a274d0505 --- /dev/null +++ b/libcpu/arm/cortex-a/context_gcc.S @@ -0,0 +1,105 @@ +/* + * File : context.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .text, "ax" +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mrs r0, cpsr + cpsid i + bx lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + msr cpsr, r0 + bx lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + ldr sp, [r0] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc + +.section .bss.share.isr +_guest_switch_lvl: + .word 0 + +.globl vmm_virq_update + +.section .text.isr, "ax" +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file + + mrs r4, cpsr + tst lr, #0x01 + orrne r4, r4, #0x20 @ it's thumb code + + stmfd sp!, {r4} @ push cpsr + + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task cpsr to spsr + msr spsr_cxsf, r4 + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r0, [ip] + str r3, [r2] +_reswitch: + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + bx lr diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h new file mode 100644 index 0000000000000000000000000000000000000000..ebea3f0fe307d44979db5b895e8d71d30926c17d --- /dev/null +++ b/libcpu/arm/cortex-a/cp15.h @@ -0,0 +1,12 @@ +#ifndef __CP15_H__ +#define __CP15_H__ + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_vector_set_base(unsigned int addr); + +#endif diff --git a/libcpu/arm/cortex-a/cp15_gcc.S b/libcpu/arm/cortex-a/cp15_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..f1ed6492aad55f8f0deb769583e738dc79a8a6f2 --- /dev/null +++ b/libcpu/arm/cortex-a/cp15_gcc.S @@ -0,0 +1,140 @@ +/* + * File : cp15_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * http://www.rt-thread.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.globl rt_cpu_get_smp_id +rt_cpu_get_smp_id: + mrc p15, #0, r0, c0, c0, #5 + bx lr + +.globl rt_cpu_vector_set_base +rt_cpu_vector_set_base: + mcr p15, #0, r0, c12, c0, #0 + dsb + bx lr + +.globl rt_hw_cpu_dcache_enable +rt_hw_cpu_dcache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_hw_cpu_icache_enable +rt_hw_cpu_icache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +_FLD_MAX_WAY: + .word 0x3ff +_FLD_MAX_IDX: + .word 0x7ff + +.globl rt_cpu_dcache_clean_flush +rt_cpu_dcache_clean_flush: + push {r4-r11} + dmb + mrc p15, #1, r0, c0, c0, #1 @ read clid register + ands r3, r0, #0x7000000 @ get level of coherency + mov r3, r3, lsr #23 + beq finished + mov r10, #0 +loop1: + add r2, r10, r10, lsr #1 + mov r1, r0, lsr r2 + and r1, r1, #7 + cmp r1, #2 + blt skip + mcr p15, #2, r10, c0, c0, #0 + isb + mrc p15, #1, r1, c0, c0, #0 + and r2, r1, #7 + add r2, r2, #4 + ldr r4, _FLD_MAX_WAY + ands r4, r4, r1, lsr #3 + clz r5, r4 + ldr r7, _FLD_MAX_IDX + ands r7, r7, r1, lsr #13 +loop2: + mov r9, r4 +loop3: + orr r11, r10, r9, lsl r5 + orr r11, r11, r7, lsl r2 + mcr p15, #0, r11, c7, c14, #2 + subs r9, r9, #1 + bge loop3 + subs r7, r7, #1 + bge loop2 +skip: + add r10, r10, #2 + cmp r3, r10 + bgt loop1 + +finished: + dsb + isb + pop {r4-r11} + bx lr + +.globl rt_hw_cpu_dcache_disable +rt_hw_cpu_dcache_disable: + push {r4-r11, lr} + bl rt_cpu_dcache_clean_flush + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + pop {r4-r11, lr} + bx lr + +.globl rt_hw_cpu_icache_disable +rt_hw_cpu_icache_disable: + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_cpu_mmu_disable +rt_cpu_mmu_disable: + mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit + dsb + bx lr + +.globl rt_cpu_mmu_enable +rt_cpu_mmu_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x001 + mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit + dsb + bx lr + +.globl rt_cpu_tlb_set +rt_cpu_tlb_set: + mcr p15, #0, r0, c2, c0, #0 + dmb + bx lr diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..7dd426e4dd97b49a18ebc3616b6db2e06fea89d4 --- /dev/null +++ b/libcpu/arm/cortex-a/cpu.c @@ -0,0 +1,37 @@ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#include +#include +#include + +/** + * @addtogroup AM33xx + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..942c074721984dc6d154a0a10ef4e7bb620628e3 --- /dev/null +++ b/libcpu/arm/cortex-a/interrupt.c @@ -0,0 +1,152 @@ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + * 2014-04-03 Grissiom port to VMM + */ + +#include +#include + +#include +#include + +#include +#include "cp15.h" + +#define MAX_HANDLERS IMX_INTERRUPT_COUNT + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +extern void rt_cpu_vector_set_base(unsigned int addr); +extern int system_vectors; + +/* keep compatible with platform SDK */ +void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr) +{ + rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown"); +} + +void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority) +{ + gic_set_irq_priority(irq_id, priority); + gic_set_irq_security(irq_id, false); // set IRQ as non-secure + gic_set_cpu_target(irq_id, cpu_id, true); + gic_enable_irq(irq_id, true); +} + +void disable_interrupt(uint32_t irq_id, uint32_t cpu_id) +{ + gic_enable_irq(irq_id, false); + gic_set_cpu_target(irq_id, cpu_id, false); +} + +static void rt_hw_vector_init(void) +{ + int sctrl; + unsigned int *src = (unsigned int *)&system_vectors; + + /* C12-C0 is only active when SCTLR.V = 0 */ + asm volatile ("mrc p15, #0, %0, c1, c0, #0" + :"=r" (sctrl)); + sctrl &= ~(1 << 13); + asm volatile ("mcr p15, #0, %0, c1, c0, #0" + : + :"r" (sctrl)); + + asm volatile ("mcr p15, #0, %0, c12, c0, #0" + : + :"r" (src)); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_hw_vector_init(); + gic_init(); + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + disable_interrupt(vector, 0); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + enable_interrupt(vector, 0, 0); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + // arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); + } + + return old_handler; +} + +/** + * Trigger a software IRQ + * + * Since we are running in single core, the target CPU are always CPU0. + */ +void rt_hw_interrupt_trigger(int vector) +{ + // arm_gic_trigger(0, 1, vector); +} + +void rt_hw_interrupt_clear(int vector) +{ + gic_write_end_of_irq(vector); +} diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..b2503e4260c77ece6e044a68d5ea6d2802a793f2 --- /dev/null +++ b/libcpu/arm/cortex-a/mmu.c @@ -0,0 +1,207 @@ +/* + * File : mmu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + */ + +#include +#include +#include + +#include "cp15.h" + +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO +#define XN (1<<4) // eXecute Never + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* Read/Write, cache, write back */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +/* Read/Write, cache, write through */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +/* Read/Write without cache and write buffer */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +/* Read/Write without cache and write buffer, no execute */ +#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) +/* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_mmu_init(void) +{ + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /* set page table */ + /* 4G 1:1 memory */ + rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB); + /* IO memory region */ + rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c new file mode 100644 index 0000000000000000000000000000000000000000..07911a2db721bd1c82cffbb2d8f4816393663b91 --- /dev/null +++ b/libcpu/arm/cortex-a/pmu.c @@ -0,0 +1,12 @@ +#include +#include "pmu.h" + +void rt_hw_pmu_dump_feature(void) +{ + unsigned long reg; + + reg = rt_hw_pmu_get_control(); + rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", + reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); + RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); +} diff --git a/libcpu/arm/cortex-a/pmu.h b/libcpu/arm/cortex-a/pmu.h new file mode 100644 index 0000000000000000000000000000000000000000..05c1420dd8fbf7a7177ea1bd4699750690c3b720 --- /dev/null +++ b/libcpu/arm/cortex-a/pmu.h @@ -0,0 +1,151 @@ +#ifndef __PMU_H__ +#define __PMU_H__ + +#include "board.h" + +/* Number of counters */ +#define ARM_PMU_CNTER_NR 4 + +enum rt_hw_pmu_event_type { + ARM_PMU_EVENT_PMNC_SW_INCR = 0x00, + ARM_PMU_EVENT_L1_ICACHE_REFILL = 0x01, + ARM_PMU_EVENT_ITLB_REFILL = 0x02, + ARM_PMU_EVENT_L1_DCACHE_REFILL = 0x03, + ARM_PMU_EVENT_L1_DCACHE_ACCESS = 0x04, + ARM_PMU_EVENT_DTLB_REFILL = 0x05, + ARM_PMU_EVENT_MEM_READ = 0x06, + ARM_PMU_EVENT_MEM_WRITE = 0x07, + ARM_PMU_EVENT_INSTR_EXECUTED = 0x08, + ARM_PMU_EVENT_EXC_TAKEN = 0x09, + ARM_PMU_EVENT_EXC_EXECUTED = 0x0A, + ARM_PMU_EVENT_CID_WRITE = 0x0B, +}; + +/* Enable bit */ +#define ARM_PMU_PMCR_E (0x01 << 0) +/* Event counter reset */ +#define ARM_PMU_PMCR_P (0x01 << 1) +/* Cycle counter reset */ +#define ARM_PMU_PMCR_C (0x01 << 2) +/* Cycle counter divider */ +#define ARM_PMU_PMCR_D (0x01 << 3) + +#ifdef __GNUC__ +rt_inline void rt_hw_pmu_enable_cnt(int divide64) +{ + unsigned long pmcr; + unsigned long pmcntenset; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C; + if (divide64) + pmcr |= ARM_PMU_PMCR_D; + else + pmcr &= ~ARM_PMU_PMCR_D; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + + /* enable all the counters */ + pmcntenset = ~0; + asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset)); + /* clear overflows(just in case) */ + asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset)); +} + +rt_inline unsigned long rt_hw_pmu_get_control(void) +{ + unsigned long pmcr; + asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + return pmcr; +} + +rt_inline unsigned long rt_hw_pmu_get_ceid(void) +{ + unsigned long reg; + /* only PMCEID0 is supported, PMCEID1 is RAZ. */ + asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg)); + return reg; +} + +rt_inline unsigned long rt_hw_pmu_get_cnten(void) +{ + unsigned long pmcnt; + asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt)); + return pmcnt; +} + +rt_inline void rt_hw_pmu_reset_cycle(void) +{ + unsigned long pmcr; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_C; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + asm volatile ("isb"); +} + +rt_inline void rt_hw_pmu_reset_event(void) +{ + unsigned long pmcr; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_P; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + asm volatile ("isb"); +} + +rt_inline unsigned long rt_hw_pmu_get_cycle(void) +{ + unsigned long cyc; + asm volatile ("isb"); + asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r"(cyc)); + return cyc; +} + +rt_inline void rt_hw_pmu_select_counter(int idx) +{ + RT_ASSERT(idx < ARM_PMU_CNTER_NR); + + asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx)); + /* Linux add an isb here, don't know why here. */ + asm volatile ("isb"); +} + +rt_inline void rt_hw_pmu_select_event(int idx, + enum rt_hw_pmu_event_type eve) +{ + RT_ASSERT(idx < ARM_PMU_CNTER_NR); + + rt_hw_pmu_select_counter(idx); + asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve)); +} + +rt_inline unsigned long rt_hw_pmu_read_counter(int idx) +{ + unsigned long reg; + + rt_hw_pmu_select_counter(idx); + asm volatile ("isb"); + asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg)); + return reg; +} + +rt_inline unsigned long rt_hw_pmu_get_ovsr(void) +{ + unsigned long reg; + asm volatile ("isb"); + asm ("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg)); + return reg; +} + +rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) +{ + asm ("mcr p15, 0, %0, c9, c12, 3" : : "r"(reg)); + asm volatile ("isb"); +} + +#endif + +void rt_hw_pmu_dump_feature(void); + +#endif /* end of include guard: __PMU_H__ */ + diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c new file mode 100644 index 0000000000000000000000000000000000000000..e653c5d11177ad62544837626bc51e25fd37ce74 --- /dev/null +++ b/libcpu/arm/cortex-a/stack.c @@ -0,0 +1,66 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include +#include +#include + +/** + * @addtogroup AM33xx + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stk = (rt_uint32_t*)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..ca8c1f930f0507dc16b43d97fcf70d84471e27e2 --- /dev/null +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -0,0 +1,249 @@ +/* + * File : start_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000100 +.equ ABT_Stack_Size, 0x00000000 +.equ RT_FIQ_STACK_PGSZ, 0x00000000 +.equ RT_IRQ_STACK_PGSZ, 0x00000100 +.equ USR_Stack_Size, 0x00000100 + +#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) + +.section .data.share.isr +/* stack */ +.globl stack_start +.globl stack_top + +stack_start: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top: + +.text +/* reset entry */ +.globl _reset +_reset: + bl rt_cpu_mmu_disable + /* set the cpu to SVC32 mode and disable interrupt */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0x13 + msr cpsr_c, r0 + + /* setup stack */ + bl stack_setup + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + + /* start RT-Thread Kernel */ + ldr pc, _rtthread_startup +_rtthread_startup: + .word rtthread_startup + +stack_setup: + ldr r0, =stack_top + + @ Set the startup stack for svc + mov sp, r0 + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_FIQ_STACK_PGSZ + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_IRQ_STACK_PGSZ + + /* come back to SVC mode */ + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + bx lr + +/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ +.section .text.isr, "ax" + .align 5 +.globl vector_fiq +vector_fiq: + stmfd sp!,{r0-r7,lr} + bl rt_hw_trap_fiq + ldmfd sp!,{r0-r7,lr} + subs pc, lr, #4 + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + +.globl rt_current_thread +.globl vmm_thread +.globl vmm_virq_check + + .align 5 +.globl vector_irq +vector_irq: + stmfd sp!, {r0-r12,lr} + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do + + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 + +rt_hw_context_switch_interrupt_do: + mov r1, #0 @ clear flag + str r1, [r0] + + mov r1, sp @ r1 point to {r0-r3} in stack + add sp, sp, #4*4 + ldmfd sp!, {r4-r12,lr}@ reload saved registers + mrs r0, spsr @ get cpsr of interrupt thread + sub r2, lr, #4 @ save old task's pc to r2 + + @ Switch to SVC mode with no interrupt. If the usr mode guest is + @ interrupted, this will just switch to the stack of kernel space. + @ save the registers in kernel space won't trigger data abort. + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + + stmfd sp!, {r2} @ push old task's pc + stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 + ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread + stmfd sp!, {r1-r4} @ push old task's r0-r3 + stmfd sp!, {r0} @ push old task's cpsr + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] @ store sp in preempted tasks's TCB + + ldr r6, =rt_interrupt_to_thread + ldr r6, [r6] + ldr sp, [r6] @ get new task's stack pointer + + ldmfd sp!, {r4} @ pop new task's cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + +.macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ +.endm + + .align 5 + .globl vector_swi +vector_swi: + push_svc_reg + bl rt_hw_trap_swi + b . + + .align 5 + .globl vector_undef +vector_undef: + push_svc_reg + bl rt_hw_trap_undef + b . + + .align 5 + .globl vector_pabt +vector_pabt: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .align 5 + .globl vector_dabt +vector_dabt: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .align 5 + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c new file mode 100644 index 0000000000000000000000000000000000000000..515f7cb54427b4f3591848ccd08bb8dee23e85ea --- /dev/null +++ b/libcpu/arm/cortex-a/trap.c @@ -0,0 +1,181 @@ +/* + * File : trap.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#include +#include +#include + +#include "armv7.h" + +#include "gic.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("data abort:"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +void rt_hw_trap_irq(void) +{ + void *param; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + // vectNum = RESERVED[31:13] | CPUID[12:10] | INTERRUPT_ID[9:0] + // send ack and get ID source + uint32_t vectNum = gic_read_irq_ack(); + + // Check that INT_ID isn't 1023 or 1022 (spurious interrupt) + if (vectNum & 0x0200) + { + gic_write_end_of_irq(vectNum); // send end of irq + } + else + { + // copy the local value to the global image of CPUID + unsigned cpu = (vectNum >> 10) & 0x7; + unsigned irq = vectNum & 0x1FF; + + /* skip warning */ + cpu = cpu; + + // Call the service routine stored in the handlers array. If there isn't + // one for this IRQ, then call the default handler. + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + + // Signal the end of the irq. + gic_write_end_of_irq(vectNum); + } +} + +void rt_hw_trap_fiq(void) +{ + /* TODO */ +} diff --git a/libcpu/arm/cortex-a/vector_gcc.S b/libcpu/arm/cortex-a/vector_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..4a44a7395cbbf15e4fe45d39183c3bdc1fe3b072 --- /dev/null +++ b/libcpu/arm/cortex-a/vector_gcc.S @@ -0,0 +1,65 @@ +/* + * File : vector_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .vectors, "ax" +.code 32 + +.globl system_vectors +system_vectors: + ldr pc, _vector_reset + ldr pc, _vector_undef + ldr pc, _vector_swi + ldr pc, _vector_pabt + ldr pc, _vector_dabt + ldr pc, _vector_resv + ldr pc, _vector_irq + ldr pc, _vector_fiq + +.globl _reset +.globl vector_undef +.globl vector_swi +.globl vector_pabt +.globl vector_dabt +.globl vector_resv +.globl vector_irq +.globl vector_fiq + +_vector_reset: + .word _reset +_vector_undef: + .word vector_undef +_vector_swi: + .word vector_swi +_vector_pabt: + .word vector_pabt +_vector_dabt: + .word vector_dabt +_vector_resv: + .word vector_resv +_vector_irq: + .word vector_irq +_vector_fiq: + .word vector_fiq + +.balignl 16,0xdeadbeef