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提交 dee31a71 编写于 作者: B Bernard Xiong
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Merge pull request #517 from aozima/pulls 

Pulls
上级 2fffc07d 7254c412
隐藏空白更改
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Showing with 957 addition and 839 deletion
bsp/lpc408x/drivers/drv_lpccan.c
浏览文件 @ dee31a71
...@@ -27,698 +27,781 @@ ...@@ -27,698 +27,781 @@
#include "lpc_exti.h" #include "lpc_exti.h"
#include "lpc_clkpwr.h" #include "lpc_clkpwr.h"
struct lpccandata { struct lpccandata
en_CAN_unitId id; {
}; en_CAN_unitId id;
static const rt_uint32_t LPCBAUDTAB[] = {
1000000,
800000,
500000,
250000,
125000,
100000,
50000,
20000,
10000,
}; };
static LPC_CAN_TypeDef* lcpcan_get_reg_base(rt_uint32_t id) static LPC_CAN_TypeDef* lcpcan_get_reg_base(rt_uint32_t id)
{ {
LPC_CAN_TypeDef* pCan; LPC_CAN_TypeDef* pCan;
switch (id) { switch (id)
case CAN_ID_1: {
pCan = LPC_CAN1; case CAN_ID_1:
break; pCan = LPC_CAN1;
break;
case CAN_ID_2:
pCan = LPC_CAN2; case CAN_ID_2:
break; pCan = LPC_CAN2;
default: break;
pCan = NULL; default:
} pCan = NULL;
return pCan; }
return pCan;
} }
static void lpccan_irqstate_init(rt_uint32_t id) static void lpccan_irqstate_init(rt_uint32_t id)
{ {
LPC_CAN_TypeDef* pCan = lcpcan_get_reg_base(id); LPC_CAN_TypeDef* pCan = lcpcan_get_reg_base(id);
volatile rt_int32_t i;
pCan->MOD = 1; // Enter Reset Mode pCan->MOD = 1; // Enter Reset Mode
pCan->IER = 0; // Disable All CAN Interrupts pCan->IER = 0; // Disable All CAN Interrupts
pCan->GSR = 0; pCan->GSR = 0;
/* Request command to release Rx, Tx buffer and clear data overrun */ /* Request command to release Rx, Tx buffer and clear data overrun */
//pCan->CMR = CAN_CMR_AT | CAN_CMR_RRB | CAN_CMR_CDO; //pCan->CMR = CAN_CMR_AT | CAN_CMR_RRB | CAN_CMR_CDO;
pCan->CMR = (1 << 1) | (1 << 2) | (1 << 3); pCan->CMR = (1 << 1) | (1 << 2) | (1 << 3);
/* Read to clear interrupt pending in interrupt capture register */ /* Read to clear interrupt pending in interrupt capture register */
rt_int32_t i = pCan->ICR; i = pCan->ICR;
pCan->MOD = 0;// Return Normal operating i = i;
pCan->MOD = 0;// Return Normal operating
} }
static void lpccan_baud_set(rt_uint32_t id, rt_uint32_t baud)
static rt_err_t lpccan_baud_set(rt_uint32_t id, rt_uint32_t baud)
{ {
uint32_t result = 0; uint32_t result = 0;
uint8_t NT, TSEG1, TSEG2; uint8_t NT, TSEG1, TSEG2;
uint32_t CANPclk = 0; uint32_t CANPclk = 0;
uint32_t BRP; uint32_t BRP;
LPC_CAN_TypeDef* pCan = lcpcan_get_reg_base(id); LPC_CAN_TypeDef* pCan = lcpcan_get_reg_base(id);
CANPclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); CANPclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
result = CANPclk / LPCBAUDTAB[baud]; result = CANPclk / baud;
/* Calculate suitable nominal time value
* NT (nominal time) = (TSEG1 + TSEG2 + 3) /* Calculate suitable nominal time value
* NT <= 24 * NT (nominal time) = (TSEG1 + TSEG2 + 3)
* TSEG1 >= 2*TSEG2 * NT <= 24
*/ * TSEG1 >= 2*TSEG2
for(NT = 24; NT > 0; NT = NT-2) */
{ for(NT = 24; NT > 0; NT = NT-2)
if ((result%NT) == 0) {
{ if ((result % NT) == 0)
BRP = result / NT - 1; {
NT--; BRP = result / NT - 1;
TSEG2 = (NT/3) - 1; NT--;
TSEG1 = NT -(NT/3) - 1; TSEG2 = (NT/3) - 1;
break; TSEG1 = NT -(NT/3) - 1;
} break;
} }
/* Enter reset mode */ }
pCan->MOD = 0x01;
/* Set bit timing /* Enter reset mode */
* Default: SAM = 0x00; pCan->MOD = 0x01;
* SJW = 0x03; /* Set bit timing
*/ * Default: SAM = 0x00;
pCan->BTR = (TSEG2 << 20) | (TSEG1 << 16) | (3 << 14) | BRP; * SJW = 0x03;
/* Return to normal operating */ */
pCan->MOD = 0; pCan->BTR = (TSEG2 << 20) | (TSEG1 << 16) | (3 << 14) | BRP;
/* Return to normal operating */
pCan->MOD = 0;
return RT_EOK;
} }
static void lpccan_init_alut_ram(void) static void lpccan_init_alut_ram(void)
{ {
//Reset CANAF value //Reset CANAF value
LPC_CANAF->AFMR = 0x01; LPC_CANAF->AFMR = 0x01;
//clear ALUT RAM //clear ALUT RAM
rt_memset((void *)LPC_CANAF_RAM->mask, 0, 2048); rt_memset((void *)LPC_CANAF_RAM->mask, 0, 2048);
LPC_CANAF->SFF_sa = 0; LPC_CANAF->SFF_sa = 0;
LPC_CANAF->SFF_GRP_sa = 0; LPC_CANAF->SFF_GRP_sa = 0;
LPC_CANAF->EFF_sa = 0; LPC_CANAF->EFF_sa = 0;
LPC_CANAF->EFF_GRP_sa = 0; LPC_CANAF->EFF_GRP_sa = 0;
LPC_CANAF->ENDofTable = 0; LPC_CANAF->ENDofTable = 0;
LPC_CANAF->AFMR = 0x00; LPC_CANAF->AFMR = 0x00;
// Set AF Mode // Set AF Mode
CAN_SetAFMode(CAN_NORMAL); CAN_SetAFMode(CAN_NORMAL);
} }
#ifdef RT_USING_LPCCAN1 #ifdef RT_USING_LPCCAN1
static void lpccan1_turnon_clk(void) static void lpccan1_turnon_clk(void)
{ {
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN1, ENABLE); CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN1, ENABLE);
} }
static void lpccan1_filter_init(struct rt_can_device *can) static void lpccan1_filter_init(struct rt_can_device *can)
{ {
} }
static void lpccan1_hw_init(enum CANBAUD baud, CAN_MODE_Type mode)
static void lpccan1_hw_init(uint32_t baud, CAN_MODE_Type mode)
{ {
if(mode != CAN_SELFTEST_MODE) { if(mode != CAN_SELFTEST_MODE)
{
#ifndef LPCCAN1_USEING_GPIO_SECOND #ifndef LPCCAN1_USEING_GPIO_SECOND
PINSEL_ConfigPin (0, 0, 1); PINSEL_ConfigPin (0, 0, 1);
PINSEL_ConfigPin (0, 1, 1); PINSEL_ConfigPin (0, 1, 1);
#else #else
PINSEL_ConfigPin (0, 21, 4); PINSEL_ConfigPin (0, 21, 4);
PINSEL_ConfigPin (0, 22, 4); PINSEL_ConfigPin (0, 22, 4);
#endif #endif
} }
lpccan1_turnon_clk(); lpccan1_turnon_clk();
lpccan_irqstate_init(CAN_1); lpccan_irqstate_init(CAN_1);
lpccan_init_alut_ram(); lpccan_init_alut_ram();
lpccan1_turnon_clk(); lpccan1_turnon_clk();
lpccan_baud_set(CAN_1, baud); lpccan_baud_set(CAN_1, baud);
CAN_ModeConfig(CAN_1, mode, ENABLE); CAN_ModeConfig(CAN_1, mode, ENABLE);
if(mode == CAN_SELFTEST_MODE) { if(mode == CAN_SELFTEST_MODE)
//CAN_ModeConfig(CAN_1, CAN_TEST_MODE, ENABLE); {
CAN_SetAFMode(CAN_ACC_BP); //CAN_ModeConfig(CAN_1, CAN_TEST_MODE, ENABLE);
} CAN_SetAFMode(CAN_ACC_BP);
}
} }
#endif /*RT_USING_LPCCAN1*/ #endif /*RT_USING_LPCCAN1*/
#ifdef RT_USING_LPCCAN2 #ifdef RT_USING_LPCCAN2
static void lpccan2_turnon_clk(void) static void lpccan2_turnon_clk(void)
{ {
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN2, ENABLE); CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN2, ENABLE);
} }
static void lpccan2_filter_init(struct rt_can_device *can) static void lpccan2_filter_init(struct rt_can_device *can)
{ {
} }
static void lpccan2_hw_init(enum CANBAUD baud, CAN_MODE_Type mode)
static void lpccan2_hw_init(uint32_t baud, CAN_MODE_Type mode)
{ {
if(mode != CAN_SELFTEST_MODE) { if(mode != CAN_SELFTEST_MODE)
{
#ifndef LPCCAN2_USEING_GPIO_SECOND #ifndef LPCCAN2_USEING_GPIO_SECOND
PINSEL_ConfigPin (0, 4, 2); PINSEL_ConfigPin (0, 4, 2);
PINSEL_ConfigPin (0, 5, 2); PINSEL_ConfigPin (0, 5, 2);
#else #else
PINSEL_ConfigPin (2, 7, 1); PINSEL_ConfigPin (2, 7, 1);
PINSEL_ConfigPin (2, 8, 1); PINSEL_ConfigPin (2, 8, 1);
#endif #endif
} }
lpccan2_turnon_clk(); lpccan2_turnon_clk();
lpccan_irqstate_init(CAN_2); lpccan_irqstate_init(CAN_2);
#ifndef RT_USING_LPCCAN1 #ifndef RT_USING_LPCCAN1
lpccan_init_alut_ram(); lpccan_init_alut_ram();
#endif /*RT_USING_LPCCAN1*/ #endif /*RT_USING_LPCCAN1*/
lpccan_baud_set(CAN_2, baud); lpccan_baud_set(CAN_2, baud);
CAN_ModeConfig(CAN_2, mode, ENABLE); CAN_ModeConfig(CAN_2, mode, ENABLE);
if(mode == CAN_SELFTEST_MODE) { if(mode == CAN_SELFTEST_MODE)
CAN_SetAFMode(CAN_ACC_BP); {
} CAN_SetAFMode(CAN_ACC_BP);
}
} }
#endif /*RT_USING_LPCCAN2*/ #endif /*RT_USING_LPCCAN2*/
static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg) static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg)
{ {
CAN_MODE_Type mode; CAN_MODE_Type mode;
switch(cfg->mode) { rt_uint32_t canid;
case RT_CAN_MODE_NORMAL:
mode = CAN_OPERATING_MODE; switch(cfg->mode)
break; {
case RT_CAN_MODE_LISEN: case RT_CAN_MODE_NORMAL:
mode = CAN_LISTENONLY_MODE; mode = CAN_OPERATING_MODE;
break; break;
case RT_CAN_MODE_LOOPBACKANLISEN: case RT_CAN_MODE_LISEN:
mode = CAN_SELFTEST_MODE; mode = CAN_LISTENONLY_MODE;
break; break;
default: case RT_CAN_MODE_LOOPBACKANLISEN:
return RT_EIO; mode = CAN_SELFTEST_MODE;
} break;
rt_uint32_t canid; default:
canid = ((struct lpccandata *) can->parent.user_data)->id; return RT_EIO;
#ifdef RT_USING_LPCCAN1 }
if(canid == CAN_1)
{ canid = ((struct lpccandata *) can->parent.user_data)->id;
lpccan1_hw_init(cfg->baud_rate, mode); #ifdef RT_USING_LPCCAN1
lpccan1_filter_init(can); if(canid == CAN_1)
} {
lpccan1_hw_init(cfg->baud_rate, mode);
lpccan1_filter_init(can);
}
#endif /*RT_USING_LPCCAN1*/ #endif /*RT_USING_LPCCAN1*/
#ifdef RT_USING_LPCCAN2 #ifdef RT_USING_LPCCAN2
#ifdef RT_USING_LPCCAN1 #ifdef RT_USING_LPCCAN1
else else
#endif /*RT_USING_LPCCAN1*/ #endif /*RT_USING_LPCCAN1*/
{ {
lpccan2_hw_init(cfg->baud_rate, mode); lpccan2_hw_init(cfg->baud_rate, mode);
lpccan2_filter_init(can); lpccan2_filter_init(can);
} }
#endif /*RT_USING_LPCCAN2*/ #endif /*RT_USING_LPCCAN2*/
return RT_EOK; return RT_EOK;
} }
static CAN_ERROR findfilter(struct lpccandata* plpccan, struct rt_can_filter_item* pitem, rt_int32_t* pos) static CAN_ERROR findfilter(struct lpccandata* plpccan, struct rt_can_filter_item* pitem, rt_int32_t* pos)
{ {
extern uint16_t CANAF_FullCAN_cnt; extern uint16_t CANAF_FullCAN_cnt;
extern uint16_t CANAF_std_cnt; extern uint16_t CANAF_std_cnt;
extern uint16_t CANAF_gstd_cnt; extern uint16_t CANAF_gstd_cnt;
extern uint16_t CANAF_ext_cnt; extern uint16_t CANAF_ext_cnt;
extern uint16_t CANAF_gext_cnt; extern uint16_t CANAF_gext_cnt;
rt_uint32_t buf0 = 0, buf1 = 0; rt_uint32_t buf0 = 0, buf1 = 0;
rt_int16_t cnt1 = 0, cnt2 = 0, bound1 = 0; rt_int16_t cnt1 = 0, cnt2 = 0, bound1 = 0;
CAN_ID_FORMAT_Type format; CAN_ID_FORMAT_Type format;
*pos = -1; *pos = -1;
if(pitem->ide) { if(pitem->ide)
format = EXT_ID_FORMAT; {
} else { format = EXT_ID_FORMAT;
format = STD_ID_FORMAT; }
} else
if(pitem->mode) { {
rt_uint32_t id = pitem->id; format = STD_ID_FORMAT;
if(format == STD_ID_FORMAT) }
{ if(pitem->mode)
id &= 0x07FF; {
rt_uint32_t id = pitem->id;
id |= plpccan->id << 13;/* Add controller number */ if(format == STD_ID_FORMAT)
{
if (CANAF_std_cnt == 0) id &= 0x07FF;
{
return CAN_ENTRY_NOT_EXIT_ERROR; id |= plpccan->id << 13;/* Add controller number */
}
else if (CANAF_std_cnt == 1) if (CANAF_std_cnt == 0)
{ {
cnt2 = (CANAF_FullCAN_cnt + 1) >> 1; return CAN_ENTRY_NOT_EXIT_ERROR;
if(id != LPC_CANAF_RAM->mask[cnt2] >> 16) { }
return CAN_ENTRY_NOT_EXIT_ERROR; else if (CANAF_std_cnt == 1)
} {
} cnt2 = (CANAF_FullCAN_cnt + 1) >> 1;
else if(id != LPC_CANAF_RAM->mask[cnt2] >> 16)
{ {
cnt1 = (CANAF_FullCAN_cnt+1)>>1; return CAN_ENTRY_NOT_EXIT_ERROR;
}
bound1 = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1); }
else
while (cnt1 < bound1) {
{ cnt1 = (CANAF_FullCAN_cnt+1)>>1;
/* Loop through standard existing IDs */
if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) == id) bound1 = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1);
{
*pos = cnt1 * 2; while (cnt1 < bound1)
return CAN_OK; {
} /* Loop through standard existing IDs */
if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) == id)
if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) == id) {
{ *pos = cnt1 * 2;
*pos = cnt1 * 2 + 1; return CAN_OK;
return CAN_OK; }
}
if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) > id) if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) == id)
{ {
return CAN_ENTRY_NOT_EXIT_ERROR; *pos = cnt1 * 2 + 1;
} return CAN_OK;
}
if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) > id) if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) > id)
{ {
return CAN_ENTRY_NOT_EXIT_ERROR; return CAN_ENTRY_NOT_EXIT_ERROR;
} }
cnt1++;
} if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) > id)
return CAN_ENTRY_NOT_EXIT_ERROR; {
} return CAN_ENTRY_NOT_EXIT_ERROR;
} }
/*********** Add Explicit Extended Identifier Frame Format entry *********/ cnt1++;
else }
{ return CAN_ENTRY_NOT_EXIT_ERROR;
/* Add controller number */ }
id |= plpccan->id << 29; }
/*********** Add Explicit Extended Identifier Frame Format entry *********/
cnt1 = ((CANAF_FullCAN_cnt+1) >> 1) + (((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt); else
{
cnt2 = 0; /* Add controller number */
id |= plpccan->id << 29;
while (cnt2 < CANAF_ext_cnt)
{ cnt1 = ((CANAF_FullCAN_cnt+1) >> 1) + (((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt);
/* Loop through extended existing masks*/
if (LPC_CANAF_RAM->mask[cnt1] == id) cnt2 = 0;
{
*pos = cnt2; while (cnt2 < CANAF_ext_cnt)
return CAN_OK; {
} /* Loop through extended existing masks*/
if (LPC_CANAF_RAM->mask[cnt1] > id) if (LPC_CANAF_RAM->mask[cnt1] == id)
{ {
return CAN_ENTRY_NOT_EXIT_ERROR; *pos = cnt2;
} return CAN_OK;
cnt1++; }
cnt2++; if (LPC_CANAF_RAM->mask[cnt1] > id)
} {
} return CAN_ENTRY_NOT_EXIT_ERROR;
} else { }
rt_uint32_t lowerID = pitem->id; cnt1++;
rt_uint32_t upperID = pitem->mask; cnt2++;
rt_uint32_t LID,UID; }
if(lowerID > upperID) }
return CAN_CONFLICT_ID_ERROR; }
if(format == STD_ID_FORMAT) else
{ {
lowerID &=0x7FF; //mask ID rt_uint32_t lowerID = pitem->id;
upperID &=0x7FF; rt_uint32_t upperID = pitem->mask;
cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1); rt_uint32_t LID,UID;
if(CANAF_gstd_cnt == 0) if(lowerID > upperID)
{ return CAN_CONFLICT_ID_ERROR;
return CAN_ENTRY_NOT_EXIT_ERROR; if(format == STD_ID_FORMAT)
} {
else lowerID &=0x7FF; //mask ID
{ upperID &=0x7FF;
bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt; cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1);
while(cnt1 < bound1) if(CANAF_gstd_cnt == 0)
{ //compare controller first {
while((LPC_CANAF_RAM->mask[cnt1] >> 29) < (plpccan->id))//increase until meet greater or equal controller return CAN_ENTRY_NOT_EXIT_ERROR;
cnt1++; }
buf0 = LPC_CANAF_RAM->mask[cnt1]; else
if((LPC_CANAF_RAM->mask[cnt1] >> 29) > (plpccan->id)) //meet greater controller {
{ bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt;
return CAN_ENTRY_NOT_EXIT_ERROR; while(cnt1 < bound1)
} {
else //meet equal controller //compare controller first
{ while((LPC_CANAF_RAM->mask[cnt1] >> 29) < (plpccan->id))//increase until meet greater or equal controller
LID = (buf0 >> 16)&0x7FF; cnt1++;
UID = buf0 & 0x7FF; buf0 = LPC_CANAF_RAM->mask[cnt1];
if (upperID == LID && lowerID == UID) if((LPC_CANAF_RAM->mask[cnt1] >> 29) > (plpccan->id)) //meet greater controller
{ {
*pos = cnt1; return CAN_ENTRY_NOT_EXIT_ERROR;
return CAN_OK; }
} else //meet equal controller
if (upperID < LID) {
{ LID = (buf0 >> 16)&0x7FF;
return CAN_ENTRY_NOT_EXIT_ERROR; UID = buf0 & 0x7FF;
} if (upperID == LID && lowerID == UID)
else if (lowerID >= UID) {
{ *pos = cnt1;
cnt1 ++; return CAN_OK;
} }
else if (upperID < LID)
return CAN_CONFLICT_ID_ERROR; {
} return CAN_ENTRY_NOT_EXIT_ERROR;
} }
if(cnt1 >= bound1) else if (lowerID >= UID)
{ {
return CAN_ENTRY_NOT_EXIT_ERROR; cnt1 ++;
} }
} else
} return CAN_CONFLICT_ID_ERROR;
/*********Add Group of Extended Identifier Frame Format************/ }
else }
{ if(cnt1 >= bound1)
lowerID &= 0x1FFFFFFF; //mask ID {
upperID &= 0x1FFFFFFF; return CAN_ENTRY_NOT_EXIT_ERROR;
cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt + CANAF_ext_cnt; }
//if this is the first Group standard ID entry }
if(CANAF_gext_cnt == 0) }
{ /*********Add Group of Extended Identifier Frame Format************/
return CAN_ENTRY_NOT_EXIT_ERROR; else
} {
else lowerID &= 0x1FFFFFFF; //mask ID
{ upperID &= 0x1FFFFFFF;
bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt \ cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt + CANAF_ext_cnt;
+ CANAF_ext_cnt + (CANAF_gext_cnt<<1); //if this is the first Group standard ID entry
while(cnt1 < bound1) if(CANAF_gext_cnt == 0)
{ {
while((LPC_CANAF_RAM->mask[cnt1] >>29)< plpccan->id ) //increase until meet greater or equal controller return CAN_ENTRY_NOT_EXIT_ERROR;
cnt1++; }
buf0 = LPC_CANAF_RAM->mask[cnt1]; else
buf1 = LPC_CANAF_RAM->mask[cnt1+1]; {
if((LPC_CANAF_RAM->mask[cnt1] >> 29) > plpccan->id ) //meet greater controller bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt \
{ + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
return CAN_ENTRY_NOT_EXIT_ERROR; while(cnt1 < bound1)
} {
else //meet equal controller while((LPC_CANAF_RAM->mask[cnt1] >>29)< plpccan->id ) //increase until meet greater or equal controller
{ cnt1++;
LID = buf0 & 0x1FFFFFFF; //mask ID buf0 = LPC_CANAF_RAM->mask[cnt1];
UID = buf1 & 0x1FFFFFFF; buf1 = LPC_CANAF_RAM->mask[cnt1+1];
if (upperID == LID && lowerID == UID) if((LPC_CANAF_RAM->mask[cnt1] >> 29) > plpccan->id ) //meet greater controller
{ {
*pos = cnt1; return CAN_ENTRY_NOT_EXIT_ERROR;
return CAN_OK; }
} else //meet equal controller
if (upperID < LID) {
{ LID = buf0 & 0x1FFFFFFF; //mask ID
return CAN_ENTRY_NOT_EXIT_ERROR; UID = buf1 & 0x1FFFFFFF;
} if (upperID == LID && lowerID == UID)
else if (lowerID >= UID) {
{ *pos = cnt1;
//load next entry to compare return CAN_OK;
cnt1 +=2; }
} if (upperID < LID)
else {
return CAN_CONFLICT_ID_ERROR; return CAN_ENTRY_NOT_EXIT_ERROR;
} }
} else if (lowerID >= UID)
if(cnt1 >= bound1) {
{ //load next entry to compare
return CAN_ENTRY_NOT_EXIT_ERROR; cnt1 +=2;
} }
} else
} return CAN_CONFLICT_ID_ERROR;
} }
return CAN_ENTRY_NOT_EXIT_ERROR; }
if(cnt1 >= bound1)
{
return CAN_ENTRY_NOT_EXIT_ERROR;
}
}
}
}
return CAN_ENTRY_NOT_EXIT_ERROR;
} }
static rt_err_t setfilter(struct lpccandata* plpccan,struct rt_can_filter_config *pconfig) static rt_err_t setfilter(struct lpccandata* plpccan,struct rt_can_filter_config *pconfig)
{ {
struct rt_can_filter_item* pitem = pconfig->items; struct rt_can_filter_item* pitem = pconfig->items;
rt_uint32_t count = pconfig->count; rt_uint32_t count = pconfig->count;
rt_int32_t pos; rt_int32_t pos;
CAN_ID_FORMAT_Type format; CAN_ID_FORMAT_Type format;
CAN_ERROR lpccanres; CAN_ERROR lpccanres;
while(count) { while(count)
if(pitem->ide) { {
format = EXT_ID_FORMAT; if(pitem->ide)
} else { {
format = STD_ID_FORMAT; format = EXT_ID_FORMAT;
} }
lpccanres = findfilter(plpccan, pitem, &pos); else
if(pconfig->actived && lpccanres != CAN_OK) { {
if(pitem->mode) { format = STD_ID_FORMAT;
lpccanres = CAN_LoadGroupEntry(plpccan->id, pitem->id, pitem->mask, format); }
} else { lpccanres = findfilter(plpccan, pitem, &pos);
lpccanres = CAN_LoadExplicitEntry(plpccan->id, pitem->id, format); if(pconfig->actived && lpccanres != CAN_OK)
} {
} else if(!pconfig->actived && lpccanres == CAN_OK) { if(pitem->mode)
AFLUT_ENTRY_Type type; {
if(pitem->mode) { lpccanres = CAN_LoadGroupEntry(plpccan->id, pitem->id, pitem->mask, format);
if(format == EXT_ID_FORMAT) { }
type = GROUP_EXTEND_ENTRY; else
} else { {
type = GROUP_STANDARD_ENTRY; lpccanres = CAN_LoadExplicitEntry(plpccan->id, pitem->id, format);
} }
} else { }
if(format == EXT_ID_FORMAT) { else if(!pconfig->actived && lpccanres == CAN_OK)
type = EXPLICIT_EXTEND_ENTRY; {
} else { AFLUT_ENTRY_Type type;
type = EXPLICIT_STANDARD_ENTRY; if(pitem->mode)
} {
} if(format == EXT_ID_FORMAT)
lpccanres = CAN_RemoveEntry(type, (rt_uint16_t)(pos)); {
} else if(!pconfig->actived && lpccanres != CAN_OK) { type = GROUP_EXTEND_ENTRY;
lpccanres = CAN_OK; }
} else
if(lpccanres != CAN_OK) { {
return RT_EIO; type = GROUP_STANDARD_ENTRY;
} }
pitem++; }
count--; else
} {
return RT_EOK; if(format == EXT_ID_FORMAT)
{
type = EXPLICIT_EXTEND_ENTRY;
}
else
{
type = EXPLICIT_STANDARD_ENTRY;
}
}
lpccanres = CAN_RemoveEntry(type, (rt_uint16_t)(pos));
}
else if(!pconfig->actived && lpccanres != CAN_OK)
{
lpccanres = CAN_OK;
}
if(lpccanres != CAN_OK)
{
return RT_EIO;
}
pitem++;
count--;
}
return RT_EOK;
} }
static rt_err_t control(struct rt_can_device *can, int cmd, void *arg) static rt_err_t control(struct rt_can_device *can, int cmd, void *arg)
{ {
struct lpccandata* plpccan; struct lpccandata* plpccan;
rt_uint32_t argval; rt_uint32_t argval;
CAN_MODE_Type mode; CAN_MODE_Type mode;
plpccan = (struct lpccandata* ) can->parent.user_data;
RT_ASSERT(plpccan != RT_NULL); plpccan = (struct lpccandata* ) can->parent.user_data;
switch (cmd) RT_ASSERT(plpccan != RT_NULL);
{
case RT_DEVICE_CTRL_CLR_INT: switch (cmd)
argval = (rt_uint32_t) arg; {
if(argval == RT_DEVICE_FLAG_INT_RX) case RT_DEVICE_CTRL_CLR_INT:
{ argval = (rt_uint32_t) arg;
CAN_IRQCmd(plpccan->id, CANINT_RIE, DISABLE); if(argval == RT_DEVICE_FLAG_INT_RX)
CAN_IRQCmd(plpccan->id, CANINT_DOIE, DISABLE); {
} else if(argval == RT_DEVICE_FLAG_INT_TX) { CAN_IRQCmd(plpccan->id, CANINT_RIE, DISABLE);
CAN_IRQCmd(plpccan->id, CANINT_TIE1, DISABLE); CAN_IRQCmd(plpccan->id, CANINT_DOIE, DISABLE);
CAN_IRQCmd(plpccan->id, CANINT_TIE2, DISABLE); }
CAN_IRQCmd(plpccan->id, CANINT_TIE3, DISABLE); else if(argval == RT_DEVICE_FLAG_INT_TX)
} else if(argval == RT_DEVICE_CAN_INT_ERR) { {
CAN_IRQCmd(plpccan->id, CANINT_EIE, DISABLE); CAN_IRQCmd(plpccan->id, CANINT_TIE1, DISABLE);
} CAN_IRQCmd(plpccan->id, CANINT_TIE2, DISABLE);
break; CAN_IRQCmd(plpccan->id, CANINT_TIE3, DISABLE);
case RT_DEVICE_CTRL_SET_INT: }
argval = (rt_uint32_t) arg; else if(argval == RT_DEVICE_CAN_INT_ERR)
if(argval == RT_DEVICE_FLAG_INT_RX) {
{ CAN_IRQCmd(plpccan->id, CANINT_EIE, DISABLE);
CAN_IRQCmd(plpccan->id, CANINT_RIE, ENABLE); }
CAN_IRQCmd(plpccan->id, CANINT_DOIE, ENABLE); break;
} else if(argval == RT_DEVICE_FLAG_INT_TX) {
CAN_IRQCmd(plpccan->id, CANINT_TIE1, ENABLE); case RT_DEVICE_CTRL_SET_INT:
CAN_IRQCmd(plpccan->id, CANINT_TIE2, ENABLE); argval = (rt_uint32_t) arg;
CAN_IRQCmd(plpccan->id, CANINT_TIE3, ENABLE); if(argval == RT_DEVICE_FLAG_INT_RX)
} else if(argval == RT_DEVICE_CAN_INT_ERR) { {
CAN_IRQCmd(plpccan->id, CANINT_EIE, ENABLE); CAN_IRQCmd(plpccan->id, CANINT_RIE, ENABLE);
} CAN_IRQCmd(plpccan->id, CANINT_DOIE, ENABLE);
break; }
case RT_CAN_CMD_SET_FILTER: else if(argval == RT_DEVICE_FLAG_INT_TX)
return setfilter(plpccan, (struct rt_can_filter_config*) arg); {
case RT_CAN_CMD_SET_MODE: CAN_IRQCmd(plpccan->id, CANINT_TIE1, ENABLE);
argval = (rt_uint32_t) arg; CAN_IRQCmd(plpccan->id, CANINT_TIE2, ENABLE);
if(argval != RT_CAN_MODE_NORMAL || CAN_IRQCmd(plpccan->id, CANINT_TIE3, ENABLE);
argval != RT_CAN_MODE_LISEN) { }
return RT_ERROR; else if(argval == RT_DEVICE_CAN_INT_ERR)
} {
if(argval != can->config.mode) CAN_IRQCmd(plpccan->id, CANINT_EIE, ENABLE);
{ }
can->config.mode = argval; break;
switch(argval) {
case RT_CAN_MODE_NORMAL: case RT_CAN_CMD_SET_FILTER:
mode = CAN_OPERATING_MODE; return setfilter(plpccan, (struct rt_can_filter_config*) arg);
break;
case RT_CAN_MODE_LISEN: case RT_CAN_CMD_SET_MODE:
mode = CAN_LISTENONLY_MODE; argval = (rt_uint32_t) arg;
break; if(argval != RT_CAN_MODE_NORMAL ||
case RT_CAN_MODE_LOOPBACKANLISEN: argval != RT_CAN_MODE_LISEN)
mode = CAN_SELFTEST_MODE; {
break; return RT_ERROR;
default: }
return RT_EIO; if(argval != can->config.mode)
} {
CAN_ModeConfig(plpccan->id, mode, ENABLE); can->config.mode = argval;
if(mode == CAN_SELFTEST_MODE) { switch(argval)
//CAN_ModeConfig(CAN_1, CAN_TEST_MODE, ENABLE); {
CAN_SetAFMode(CAN_ACC_BP); case RT_CAN_MODE_NORMAL:
} mode = CAN_OPERATING_MODE;
} break;
break; case RT_CAN_MODE_LISEN:
case RT_CAN_CMD_SET_BAUD: mode = CAN_LISTENONLY_MODE;
argval = (rt_uint32_t) arg; break;
if(argval != CAN1MBaud && case RT_CAN_MODE_LOOPBACKANLISEN:
argval != CAN800kBaud && mode = CAN_SELFTEST_MODE;
argval != CAN500kBaud && break;
argval != CAN250kBaud && default:
argval != CAN125kBaud && return RT_EIO;
argval != CAN100kBaud && }
argval != CAN50kBaud && CAN_ModeConfig(plpccan->id, mode, ENABLE);
argval != CAN20kBaud && if(mode == CAN_SELFTEST_MODE)
argval != CAN10kBaud ) { {
return RT_ERROR; //CAN_ModeConfig(CAN_1, CAN_TEST_MODE, ENABLE);
} CAN_SetAFMode(CAN_ACC_BP);
if(argval != can->config.baud_rate) }
{ }
can->config.baud_rate = argval; break;
lpccan_baud_set(plpccan->id, (rt_uint32_t) arg);
} case RT_CAN_CMD_SET_BAUD:
break; argval = (rt_uint32_t) arg;
case RT_CAN_CMD_SET_PRIV: if(argval != can->config.baud_rate)
argval = (rt_uint32_t) arg; {
if(argval != RT_CAN_MODE_PRIV || can->config.baud_rate = argval;
argval != RT_CAN_MODE_NOPRIV) { return lpccan_baud_set(plpccan->id, (rt_uint32_t) arg);
return RT_ERROR; }
} break;
if(argval != can->config.privmode)
{ case RT_CAN_CMD_SET_PRIV:
can->config.privmode = argval; argval = (rt_uint32_t) arg;
CAN_ModeConfig(plpccan->id, CAN_TXPRIORITY_MODE, ENABLE); if(argval != RT_CAN_MODE_PRIV ||
} argval != RT_CAN_MODE_NOPRIV)
break; {
case RT_CAN_CMD_GET_STATUS: return RT_ERROR;
{ }
rt_uint32_t errtype; if(argval != can->config.privmode)
can->status.rcverrcnt = 0; {
can->status.snderrcnt = 0; can->config.privmode = argval;
can->status.errcode = 0; CAN_ModeConfig(plpccan->id, CAN_TXPRIORITY_MODE, ENABLE);
if(arg != &can->status) { }
rt_memcpy(arg,&can->status,sizeof(can->status)); break;
}
} case RT_CAN_CMD_GET_STATUS:
break; {
} can->status.rcverrcnt = 0;
return RT_EOK; can->status.snderrcnt = 0;
can->status.errcode = 0;
if(arg != &can->status)
{
rt_memcpy(arg,&can->status,sizeof(can->status));
}
}
break;
}
return RT_EOK;
} }
static int sendmsg(struct rt_can_device *can, const void* buf, rt_uint32_t boxno) static int sendmsg(struct rt_can_device *can, const void* buf, rt_uint32_t boxno)
{ {
struct lpccandata* plpccan; struct lpccandata* plpccan;
plpccan = (struct lpccandata* ) can->parent.user_data; LPC_CAN_TypeDef* pCan;
RT_ASSERT(plpccan != RT_NULL); struct rt_can_msg* pmsg;
LPC_CAN_TypeDef* pCan = lcpcan_get_reg_base(plpccan->id); rt_uint32_t SR_Mask;
RT_ASSERT(pCan != RT_NULL); rt_uint32_t CMRMsk;
struct rt_can_msg* pmsg = (struct rt_can_msg*) buf;
rt_uint32_t SR_Mask; plpccan = (struct lpccandata* ) can->parent.user_data;
if(boxno > 2) { RT_ASSERT(plpccan != RT_NULL);
return RT_ERROR;
} pCan = lcpcan_get_reg_base(plpccan->id);
rt_uint32_t CMRMsk = 0x01 | (0x01 << (boxno + 5)); RT_ASSERT(pCan != RT_NULL);
SR_Mask = 0x01 <<(boxno * 8 + 2);
volatile unsigned int *pTFI = (&pCan->TFI1 + 0 + 4 * boxno); pmsg = (struct rt_can_msg*) buf;
volatile unsigned int *pTID = (&pCan->TFI1 + 1 + 4 * boxno);
volatile unsigned int *pTDA = (&pCan->TFI1 + 2 + 4 * boxno); if(boxno > 2)
volatile unsigned int *pTDB = (&pCan->TFI1 + 3 + 4 * boxno); {
rt_uint32_t data; return RT_ERROR;
if(pCan->SR & SR_Mask) { }
/* Transmit Channel 1 is available */
/* Write frame informations and frame data into its CANxTFI1, CMRMsk = 0x01 | (0x01 << (boxno + 5));
* CANxTID1, CANxTDA1, CANxTDB1 register */ SR_Mask = 0x01 <<(boxno * 8 + 2);
*pTFI &= ~ 0x000F0000;
*pTFI |= (pmsg->len) << 16; if(pCan->SR & SR_Mask)
if(pmsg->rtr == REMOTE_FRAME) {
{ volatile unsigned int *pTFI = (&pCan->TFI1 + 0 + 4 * boxno);
*pTFI |= (1 << 30); //set bit RTR volatile unsigned int *pTID = (&pCan->TFI1 + 1 + 4 * boxno);
} volatile unsigned int *pTDA = (&pCan->TFI1 + 2 + 4 * boxno);
else volatile unsigned int *pTDB = (&pCan->TFI1 + 3 + 4 * boxno);
{ rt_uint32_t data;
*pTFI &= ~(1 << 30);
} /* Transmit Channel 1 is available */
/* Write frame informations and frame data into its CANxTFI1,
if(pmsg->ide == EXT_ID_FORMAT) * CANxTID1, CANxTDA1, CANxTDB1 register */
{ *pTFI &= ~ 0x000F0000;
*pTFI |= (((uint32_t)1) << 31); //set bit FF *pTFI |= (pmsg->len) << 16;
} if(pmsg->rtr == REMOTE_FRAME)
else {
{ *pTFI |= (1 << 30); //set bit RTR
*pTFI &= ~(((uint32_t)1) << 31); }
} else
if(can->config.privmode) { {
*pTFI &= ~0x000000FF; *pTFI &= ~(1 << 30);
*pTFI |= pmsg->priv; }
}
/* Write CAN ID*/ if(pmsg->ide == EXT_ID_FORMAT)
*pTID = pmsg->id; {
/*Write first 4 data bytes*/ *pTFI |= (((uint32_t)1) << 31); //set bit FF
data = (pmsg->data[0]) | (((pmsg->data[1]))<< 8) | ((pmsg->data[2]) << 16) | ((pmsg->data[3]) << 24); }
*pTDA = data; else
/*Write second 4 data bytes*/ {
data = (pmsg->data[4]) | (((pmsg->data[5])) << 8) | ((pmsg->data[6]) << 16) | ((pmsg->data[7]) << 24); *pTFI &= ~(((uint32_t)1) << 31);
*pTDB = data; }
/*Write transmission request*/ if(can->config.privmode)
pCan->CMR = CMRMsk; {
return RT_EOK; *pTFI &= ~0x000000FF;
} else { *pTFI |= pmsg->priv;
return RT_ERROR; }
} /* Write CAN ID*/
*pTID = pmsg->id;
/*Write first 4 data bytes*/
data = (pmsg->data[0]) | (((pmsg->data[1]))<< 8) | ((pmsg->data[2]) << 16) | ((pmsg->data[3]) << 24);
*pTDA = data;
/*Write second 4 data bytes*/
data = (pmsg->data[4]) | (((pmsg->data[5])) << 8) | ((pmsg->data[6]) << 16) | ((pmsg->data[7]) << 24);
*pTDB = data;
/*Write transmission request*/
pCan->CMR = CMRMsk;
return RT_EOK;
}
else
{
return RT_ERROR;
}
} }
static int recvmsg(struct rt_can_device *can, void* buf, rt_uint32_t boxno) static int recvmsg(struct rt_can_device *can, void* buf, rt_uint32_t boxno)
{ {
struct lpccandata* plpccan; struct lpccandata* plpccan;
plpccan = (struct lpccandata* ) can->parent.user_data; LPC_CAN_TypeDef* pCan;
RT_ASSERT(plpccan != RT_NULL);
LPC_CAN_TypeDef* pCan = lcpcan_get_reg_base(plpccan->id); plpccan = (struct lpccandata* ) can->parent.user_data;
RT_ASSERT(pCan != RT_NULL); RT_ASSERT(plpccan != RT_NULL);
//CAN_ReceiveMsg pCan = lcpcan_get_reg_base(plpccan->id);
uint32_t data; RT_ASSERT(pCan != RT_NULL);
struct rt_can_msg* pmsg = (struct rt_can_msg*) buf;
//check status of Receive Buffer //CAN_ReceiveMsg
if((pCan->SR &0x00000001)) //check status of Receive Buffer
{ if((pCan->SR &0x00000001))
/* Receive message is available */ {
/* Read frame informations */ uint32_t data;
pmsg->ide = (uint8_t)(((pCan->RFS) & 0x80000000) >> 31); struct rt_can_msg* pmsg = (struct rt_can_msg*) buf;
pmsg->rtr = (uint8_t)(((pCan->RFS) & 0x40000000) >> 30);
pmsg->len = (uint8_t)(((pCan->RFS) & 0x000F0000) >> 16); /* Receive message is available */
/* Read CAN message identifier */ /* Read frame informations */
pmsg->id = pCan->RID; pmsg->ide = (uint8_t)(((pCan->RFS) & 0x80000000) >> 31);
/* Read the data if received message was DATA FRAME */ pmsg->rtr = (uint8_t)(((pCan->RFS) & 0x40000000) >> 30);
if (!pmsg->rtr) pmsg->len = (uint8_t)(((pCan->RFS) & 0x000F0000) >> 16);
{ /* Read CAN message identifier */
/* Read first 4 data bytes */ pmsg->id = pCan->RID;
data = pCan->RDA; /* Read the data if received message was DATA FRAME */
pmsg->data[0] = data & 0x000000FF; if (!pmsg->rtr)
pmsg->data[1] = (data & 0x0000FF00) >> 8; {
pmsg->data[2] = (data & 0x00FF0000) >> 16; /* Read first 4 data bytes */
pmsg->data[3] = (data & 0xFF000000) >> 24; data = pCan->RDA;
/* Read second 4 data bytes */ pmsg->data[0] = data & 0x000000FF;
if(pmsg->len > 4) { pmsg->data[1] = (data & 0x0000FF00) >> 8;
data = pCan->RDB; pmsg->data[2] = (data & 0x00FF0000) >> 16;
pmsg->data[4] = data & 0x000000FF; pmsg->data[3] = (data & 0xFF000000) >> 24;
pmsg->data[5] = (data & 0x0000FF00) >> 8; /* Read second 4 data bytes */
pmsg->data[6] = (data & 0x00FF0000) >> 16; if(pmsg->len > 4)
pmsg->data[7] = (data & 0xFF000000) >> 24; {
} data = pCan->RDB;
pmsg->hdr = 0; pmsg->data[4] = data & 0x000000FF;
/*release receive buffer*/ pmsg->data[5] = (data & 0x0000FF00) >> 8;
pCan->CMR = 0x04; pmsg->data[6] = (data & 0x00FF0000) >> 16;
} pmsg->data[7] = (data & 0xFF000000) >> 24;
else }
{ pmsg->hdr = 0;
/* Received Frame is a Remote Frame, not have data, we just receive /*release receive buffer*/
* message information only */ pCan->CMR = 0x04;
pCan->CMR = 0x04; /*release receive buffer*/ }
return SUCCESS; else
} {
} /* Received Frame is a Remote Frame, not have data, we just receive
else * message information only */
{ pCan->CMR = 0x04; /*release receive buffer*/
// no receive message available return SUCCESS;
return ERROR; }
} }
return RT_EOK; else
{
// no receive message available
return ERROR;
}
return RT_EOK;
} }
static const struct rt_can_ops canops = static const struct rt_can_ops canops =
{ {
configure, configure,
control, control,
sendmsg, sendmsg,
recvmsg, recvmsg,
}; };
#ifdef RT_USING_LPCCAN1 #ifdef RT_USING_LPCCAN1
#ifdef RT_CAN_USING_LED #ifdef RT_CAN_USING_LED
#endif #endif
static struct lpccandata lpccandata1 = { static struct lpccandata lpccandata1 =
CAN_1, {
CAN_ID_1,
}; };
static struct rt_can_device lpccan1; static struct rt_can_device lpccan1;
#endif /*RT_USINGLPCCAN1*/ #endif /*RT_USINGLPCCAN1*/
...@@ -726,11 +809,13 @@ static struct rt_can_device lpccan1; ...@@ -726,11 +809,13 @@ static struct rt_can_device lpccan1;
#ifdef RT_USING_LPCCAN2 #ifdef RT_USING_LPCCAN2
#ifdef RT_CAN_USING_LED #ifdef RT_CAN_USING_LED
#endif #endif
static struct lpccandata lpccandata2 = { static struct lpccandata lpccandata2 =
CAN_2, {
CAN_ID_2,
}; };
static struct rt_can_device lpccan2; static struct rt_can_device lpccan2;
#endif /*RT_USINGLPCCAN2*/ #endif /*RT_USINGLPCCAN2*/
/*----------------- INTERRUPT SERVICE ROUTINES --------------------------*/ /*----------------- INTERRUPT SERVICE ROUTINES --------------------------*/
/*********************************************************************//** /*********************************************************************//**
* @brief Event Router IRQ Handler * @brief Event Router IRQ Handler
...@@ -739,234 +824,267 @@ static struct rt_can_device lpccan2; ...@@ -739,234 +824,267 @@ static struct rt_can_device lpccan2;
**********************************************************************/ **********************************************************************/
void CAN_IRQHandler(void) void CAN_IRQHandler(void)
{ {
rt_uint32_t IntStatus; rt_uint32_t IntStatus;
#ifdef RT_USING_LPCCAN1 #ifdef RT_USING_LPCCAN1
IntStatus = CAN_IntGetStatus(CAN_1); IntStatus = CAN_IntGetStatus(CAN_1);
//check receive interrupt //check receive interrupt
if((IntStatus >> 0) & 0x01) if((IntStatus >> 0) & 0x01)
{ {
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_RX_IND | 0<<8); rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_RX_IND | 0<<8);
} }
//check Transmit Interrupt interrupt1 //check Transmit Interrupt interrupt1
if((IntStatus >> 1) & 0x01) if((IntStatus >> 1) & 0x01)
{ {
rt_uint32_t state = 0; rt_uint32_t state = 0;
state = CAN_GetCTRLStatus(CAN_1, CANCTRL_STS); state = CAN_GetCTRLStatus(CAN_1, CANCTRL_STS);
if(state & (0x01 << 3)) if(state & (0x01 << 3))
{ {
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 0<<8); rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 0<<8);
} else { }
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 0<<8); else
} {
} rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 0<<8);
//check Error Warning Interrupt }
if((IntStatus >> 2) & 0x01) }
{ //check Error Warning Interrupt
rt_uint32_t errtype; if((IntStatus >> 2) & 0x01)
errtype = (IntStatus >> 16); {
if(errtype & 0x1F && lpccan1.status.lasterrtype == (errtype & 0x1F)) { rt_uint32_t errtype;
switch((errtype & 0x1F)) { rt_uint32_t state;
case 00011: // Start of Frame
case 00010: // ID28 ... ID21 errtype = (IntStatus >> 16);
case 00110: //ID20 ... ID18 if(errtype & 0x1F && lpccan1.status.lasterrtype == (errtype & 0x1F))
case 00100: // SRTR Bit {
case 00101: // IDE bit switch((errtype & 0x1F))
case 00111: // ID17 ... 13 {
case 01111: // ID12 ... ID5 case 00011: // Start of Frame
case 01110: // ID4 ... ID0 case 00010: // ID28 ... ID21
case 01100: // RTR Bit case 00110: //ID20 ... ID18
case 01011: // Data Length Code case 00100: // SRTR Bit
case 01010: // Data Field case 00101: // IDE bit
lpccan1.status.formaterrcnt++; case 00111: // ID17 ... 13
break; case 01111: // ID12 ... ID5
case 01101: // Reserved Bit 1 case 01110: // ID4 ... ID0
case 01001: // Reserved Bit 0 case 01100: // RTR Bit
lpccan1.status.bitpaderrcnt++; case 01011: // Data Length Code
break; case 01010: // Data Field
case 01000: // CRC Sequence lpccan1.status.formaterrcnt++;
case 11000: // CRC Delimiter break;
lpccan1.status.crcerrcnt++; case 01101: // Reserved Bit 1
break; case 01001: // Reserved Bit 0
case 11001: // Acknowledge Slot lpccan1.status.bitpaderrcnt++;
case 11011: // Acknowledge Delimiter break;
lpccan1.status.ackerrcnt++; case 01000: // CRC Sequence
break; case 11000: // CRC Delimiter
case 11010: // End of Frame lpccan1.status.crcerrcnt++;
case 10010: // Intermission break;
lpccan1.status.formaterrcnt++; case 11001: // Acknowledge Slot
break; case 11011: // Acknowledge Delimiter
} lpccan1.status.ackerrcnt++;
lpccan1.status.lasterrtype = errtype & 0x1F; break;
} case 11010: // End of Frame
rt_uint32_t state = 0; case 10010: // Intermission
state = CAN_GetCTRLStatus(CAN_1, CANCTRL_GLOBAL_STS); lpccan1.status.formaterrcnt++;
lpccan1.status.rcverrcnt = (state >> 16) & 0xFF; break;
lpccan1.status.snderrcnt = (state >> 24) & 0xFF; }
lpccan1.status.errcode = (state >> 5) & 0x06; lpccan1.status.lasterrtype = errtype & 0x1F;
} }
//check Data Overrun Interrupt Interrupt
if((IntStatus >> 3) & 0x01) state = CAN_GetCTRLStatus(CAN_1, CANCTRL_GLOBAL_STS);
{ lpccan1.status.rcverrcnt = (state >> 16) & 0xFF;
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_RXOF_IND | 0<<8); lpccan1.status.snderrcnt = (state >> 24) & 0xFF;
} lpccan1.status.errcode = (state >> 5) & 0x06;
//check Transmit Interrupt interrupt2 }
if((IntStatus >> 9) & 0x01) //check Data Overrun Interrupt Interrupt
{ if((IntStatus >> 3) & 0x01)
rt_uint32_t state = 0; {
state = CAN_GetCTRLStatus(CAN_1, CANCTRL_STS); rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_RXOF_IND | 0<<8);
if(state & (0x01 << 11)) }
{ //check Transmit Interrupt interrupt2
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 1<<8); if((IntStatus >> 9) & 0x01)
} else { {
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 1<<8); rt_uint32_t state = 0;
} state = CAN_GetCTRLStatus(CAN_1, CANCTRL_STS);
} if(state & (0x01 << 11))
//check Transmit Interrupt interrupt3 {
if((IntStatus >> 10) & 0x01) rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 1<<8);
{ }
rt_uint32_t state = 0; else
state = CAN_GetCTRLStatus(CAN_1, CANCTRL_STS); {
if(state & (0x01 << 19)) rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 1<<8);
{ }
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 2<<8); }
} else { //check Transmit Interrupt interrupt3
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 2<<8); if((IntStatus >> 10) & 0x01)
} {
} rt_uint32_t state = 0;
state = CAN_GetCTRLStatus(CAN_1, CANCTRL_STS);
if(state & (0x01 << 19))
{
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 2<<8);
}
else
{
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 2<<8);
}
}
#endif /*RT_USING_LPCCAN1*/ #endif /*RT_USING_LPCCAN1*/
#ifdef RT_USING_LPCCAN2 #ifdef RT_USING_LPCCAN2
IntStatus = CAN_IntGetStatus(CAN_2); IntStatus = CAN_IntGetStatus(CAN_2);
//check receive interrupt //check receive interrupt
if((IntStatus >> 0) & 0x01) if((IntStatus >> 0) & 0x01)
{ {
rt_hw_can_isr(&lpccan2,RT_CAN_EVENT_RX_IND | 0<<8); rt_hw_can_isr(&lpccan2,RT_CAN_EVENT_RX_IND | 0<<8);
} }
//check Transmit Interrupt interrupt1 //check Transmit Interrupt interrupt1
if((IntStatus >> 1) & 0x01) if((IntStatus >> 1) & 0x01)
{ {
rt_uint32_t state = 0; rt_uint32_t state = 0;
state = CAN_GetCTRLStatus(CAN_2, CANCTRL_STS); state = CAN_GetCTRLStatus(CAN_2, CANCTRL_STS);
if(state & (0x01 << 3)) if(state & (0x01 << 3))
{ {
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 0<<8); rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 0<<8);
} else { }
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 0<<8); else
} {
} rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 0<<8);
//check Error Warning Interrupt }
if((IntStatus >> 2) & 0x01) }
{
rt_uint32_t errtype; //check Error Warning Interrupt
errtype = (IntStatus >> 16); if((IntStatus >> 2) & 0x01)
if(errtype & 0x1F && lpccan2.status.lasterrtype == (errtype & 0x1F)) { {
switch((errtype & 0x1F)) { rt_uint32_t errtype;
case 00011: // Start of Frame errtype = (IntStatus >> 16);
case 00010: // ID28 ... ID21 if(errtype & 0x1F && lpccan2.status.lasterrtype == (errtype & 0x1F))
case 00110: //ID20 ... ID18 {
case 00100: // SRTR Bit switch((errtype & 0x1F))
case 00101: // IDE bit {
case 00111: // ID17 ... 13 case 00011: // Start of Frame
case 01111: // ID12 ... ID5 case 00010: // ID28 ... ID21
case 01110: // ID4 ... ID0 case 00110: //ID20 ... ID18
case 01100: // RTR Bit case 00100: // SRTR Bit
case 01011: // Data Length Code case 00101: // IDE bit
case 01010: // Data Field case 00111: // ID17 ... 13
lpccan2.status.formaterrcnt++; case 01111: // ID12 ... ID5
break; case 01110: // ID4 ... ID0
case 01101: // Reserved Bit 1 case 01100: // RTR Bit
case 01001: // Reserved Bit 0 case 01011: // Data Length Code
lpccan2.status.bitpaderrcnt++; case 01010: // Data Field
break; lpccan2.status.formaterrcnt++;
case 01000: // CRC Sequence break;
case 11000: // CRC Delimiter case 01101: // Reserved Bit 1
lpccan2.status.crcerrcnt++; case 01001: // Reserved Bit 0
break; lpccan2.status.bitpaderrcnt++;
case 11001: // Acknowledge Slot break;
case 11011: // Acknowledge Delimiter case 01000: // CRC Sequence
lpccan2.status.ackerrcnt++; case 11000: // CRC Delimiter
break; lpccan2.status.crcerrcnt++;
case 11010: // End of Frame break;
case 10010: // Intermission case 11001: // Acknowledge Slot
lpccan2.status.formaterrcnt++; case 11011: // Acknowledge Delimiter
break; lpccan2.status.ackerrcnt++;
} break;
lpccan2.status.lasterrtype = errtype & 0x1F; case 11010: // End of Frame
} case 10010: // Intermission
rt_uint32_t state = 0; lpccan2.status.formaterrcnt++;
state = CAN_GetCTRLStatus(CAN_2, CANCTRL_GLOBAL_STS); break;
lpccan2.status.rcverrcnt = (state >> 16) & 0xFF; }
lpccan2.status.snderrcnt = (state >> 24) & 0xFF; lpccan2.status.lasterrtype = errtype & 0x1F;
lpccan2.status.errcode = (state >> 5) & 0x06; }
} rt_uint32_t state = 0;
//check Data Overrun Interrupt Interrupt state = CAN_GetCTRLStatus(CAN_2, CANCTRL_GLOBAL_STS);
if((IntStatus >> 3) & 0x01) lpccan2.status.rcverrcnt = (state >> 16) & 0xFF;
{ lpccan2.status.snderrcnt = (state >> 24) & 0xFF;
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_RXOF_IND | 0<<8); lpccan2.status.errcode = (state >> 5) & 0x06;
} }
//check Transmit Interrupt interrupt2
if((IntStatus >> 9) & 0x01) //check Data Overrun Interrupt Interrupt
{ if((IntStatus >> 3) & 0x01)
rt_uint32_t state = 0; {
state = CAN_GetCTRLStatus(CAN_2, CANCTRL_STS); rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_RXOF_IND | 0<<8);
if(state & (0x01 << 11)) }
{
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 1<<8); //check Transmit Interrupt interrupt2
} else { if((IntStatus >> 9) & 0x01)
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 1<<8); {
} rt_uint32_t state = 0;
} state = CAN_GetCTRLStatus(CAN_2, CANCTRL_STS);
//check Transmit Interrupt interrupt3 if(state & (0x01 << 11))
if((IntStatus >> 10) & 0x01) {
{ rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 1<<8);
rt_uint32_t state = 0; }
state = CAN_GetCTRLStatus(CAN_2, CANCTRL_STS); else
if(state & (0x01 << 19)) {
{ rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 1<<8);
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 2<<8); }
} else { }
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 2<<8);
} //check Transmit Interrupt interrupt3
} if((IntStatus >> 10) & 0x01)
{
rt_uint32_t state = 0;
state = CAN_GetCTRLStatus(CAN_2, CANCTRL_STS);
if(state & (0x01 << 19))
{
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_DONE | 2<<8);
}
else
{
rt_hw_can_isr(&lpccan1,RT_CAN_EVENT_TX_FAIL | 2<<8);
}
}
#endif /*RT_USING_LPCCAN2*/ #endif /*RT_USING_LPCCAN2*/
} }
int lpc_can_init(void) int lpc_can_init(void)
{ {
#ifdef RT_USING_LPCCAN1 #ifdef RT_USING_LPCCAN1
lpccan1.config.baud_rate=CAN1MBaud; lpccan1.config.baud_rate=CAN1MBaud;
lpccan1.config.msgboxsz=16; lpccan1.config.msgboxsz=16;
lpccan1.config.sndboxnumber=3; lpccan1.config.sndboxnumber=3;
lpccan1.config.mode=RT_CAN_MODE_NORMAL; lpccan1.config.mode=RT_CAN_MODE_NORMAL;
lpccan1.config.privmode=0; lpccan1.config.privmode=0;
#ifdef RT_CAN_USING_LED #ifdef RT_CAN_USING_LED
#endif #endif
lpccan1.config.ticks = 50;
lpccan1.config.ticks = 50;
#ifdef RT_CAN_USING_HDR #ifdef RT_CAN_USING_HDR
#endif
//Enable CAN Interrupt
NVIC_EnableIRQ(CAN_IRQn);
rt_hw_can_register(&lpccan1, "lpccan1", &canops, &lpccandata1);
#endif #endif
//Enable CAN Interrupt
NVIC_EnableIRQ(CAN_IRQn);
rt_hw_can_register(&lpccan1, "lpccan1", &canops, &lpccandata1);
#endif /*RT_USING_LPCCAN1*/
#ifdef RT_USING_LPCCAN2 #ifdef RT_USING_LPCCAN2
lpccan2.config.baud_rate=CAN1MBaud; lpccan2.config.baud_rate=CAN1MBaud;
lpccan2.config.msgboxsz=16; lpccan2.config.msgboxsz=16;
lpccan2.config.sndboxnumber=3; lpccan2.config.sndboxnumber=3;
lpccan2.config.mode=RT_CAN_MODE_NORMAL; lpccan2.config.mode=RT_CAN_MODE_NORMAL;
lpccan2.config.privmode=0; lpccan2.config.privmode=0;
#ifdef RT_CAN_USING_LED #ifdef RT_CAN_USING_LED
#endif
lpccan2.config.ticks = 50;
#ifdef RT_CAN_USING_HDR
#endif
#ifndef RT_USING_LPCCAN1
//Enable CAN Interrupt
NVIC_EnableIRQ(CAN_IRQn);
#endif #endif
lpccan2.config.ticks = 50;
#ifdef RT_CAN_USING_HDR #ifdef RT_CAN_USING_HDR
#endif #endif
rt_hw_can_register(&lpccan2, "lpccan2", &canops, &lpccandata2);
//Enable CAN Interrupt
NVIC_EnableIRQ(CAN_IRQn);
#ifdef RT_CAN_USING_HDR
#endif #endif
return RT_EOK;
rt_hw_can_register(&lpccan2, "lpccan2", &canops, &lpccandata2);
#endif /*RT_USING_LPCCAN2*/
return RT_EOK;
} }
INIT_BOARD_EXPORT(lpc_can_init); INIT_BOARD_EXPORT(lpc_can_init);
......
components/drivers/include/drivers/can.h
浏览文件 @ dee31a71
...@@ -37,15 +37,15 @@ ...@@ -37,15 +37,15 @@
enum CANBAUD enum CANBAUD
{ {
CAN1MBaud = 0, /* 1 MBit/sec */ CAN1MBaud = 1000UL * 1000,/* 1 MBit/sec */
CAN800kBaud, /* 800 kBit/sec */ CAN800kBaud = 1000UL * 800, /* 800 kBit/sec */
CAN500kBaud, /* 500 kBit/sec */ CAN500kBaud = 1000UL * 500, /* 500 kBit/sec */
CAN250kBaud, /* 250 kBit/sec */ CAN250kBaud = 1000UL * 250, /* 250 kBit/sec */
CAN125kBaud, /* 125 kBit/sec */ CAN125kBaud = 1000UL * 125, /* 125 kBit/sec */
CAN100kBaud, /* 100 kBit/sec */ CAN100kBaud = 1000UL * 100, /* 100 kBit/sec */
CAN50kBaud, /* 50 kBit/sec */ CAN50kBaud = 1000UL * 50, /* 50 kBit/sec */
CAN20kBaud, /* 20 kBit/sec */ CAN20kBaud = 1000UL * 20, /* 20 kBit/sec */
CAN10kBaud /* 10 kBit/sec */ CAN10kBaud = 1000UL * 10 /* 10 kBit/sec */
}; };
#define RT_CAN_MODE_NORMAL 0 #define RT_CAN_MODE_NORMAL 0
......
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