diff --git a/bsp/pic32ethernet/board.c b/bsp/pic32ethernet/board.c
index ba16e5cbc60b0dd76a291f6a978e10300fb6ce37..b5bc301aeaa662e557db63a5f3fe9108490d1bad 100644
--- a/bsp/pic32ethernet/board.c
+++ b/bsp/pic32ethernet/board.c
@@ -63,7 +63,7 @@ static void rt_hw_timer_handler(void)
}
/**
-* This function will initial FM3 Easy Kit board.
+* This function will initial board.
*/
void rt_hw_board_init()
{
@@ -73,7 +73,11 @@ void rt_hw_board_init()
// The PBDIV value is already set via the pragma FPBDIV option above.
SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
- rt_hw_console_init();
+ /* use DBPRINTF */
+ /* rt_hw_console_init(); */
+
+ rt_hw_usart_init();
+ rt_console_set_device("uart1");
rt_hw_show_info();
@@ -94,9 +98,6 @@ void rt_hw_board_init()
/* Setup the software interrupt. */
mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
-
- // configure PORTD.RD0 = output,Toggle in CoreSW0Handler.
- mPORTDSetPinsDigitalOut(BIT_0);
}
void __ISR(_TIMER_1_VECTOR, ipl2) Timer1Handler(void)
@@ -106,9 +107,6 @@ void __ISR(_TIMER_1_VECTOR, ipl2) Timer1Handler(void)
// .. things to do
rt_hw_timer_handler();
-
-// // .. in this case, toggle the LED
-// mPORTDToggleBits(BIT_1);
}
//void __ISR(_CORE_TIMER_VECTOR, ipl2) CoreTimerHandler(void)
@@ -121,9 +119,6 @@ void __ISR(_TIMER_1_VECTOR, ipl2) Timer1Handler(void)
//
// // update the period
// UpdateCoreTimer(CORE_TICK_RATE);
-//
-// // .. Toggle the LED
-// mPORTDToggleBits(BIT_1);
//}
diff --git a/bsp/pic32ethernet/procdefs.ld b/bsp/pic32ethernet/procdefs.ld
new file mode 100644
index 0000000000000000000000000000000000000000..bbd87402fbe61818c1a5b17a9fc53c037a8255e6
--- /dev/null
+++ b/bsp/pic32ethernet/procdefs.ld
@@ -0,0 +1,66 @@
+/*************************************************************************
+ * Processor-specific object file. Contains SFR definitions.
+ *************************************************************************/
+INPUT("processor.o")
+
+/*************************************************************************
+ * For interrupt vector handling
+ *************************************************************************/
+PROVIDE(_vector_spacing = 0x00000001);
+_ebase_address = 0x9FC01000;
+
+/*************************************************************************
+ * Memory Address Equates
+ *************************************************************************/
+_RESET_ADDR = 0xBFC00000;
+_BEV_EXCPT_ADDR = 0xBFC00380;
+_DBG_EXCPT_ADDR = 0xBFC00480;
+_DBG_CODE_ADDR = 0xBFC02000;
+_GEN_EXCPT_ADDR = _ebase_address + 0x180;
+
+/*************************************************************************
+ * Memory Regions
+ *
+ * Memory regions without attributes cannot be used for orphaned sections.
+ * Only sections specifically assigned to these regions can be allocated
+ * into these regions.
+ *************************************************************************/
+MEMORY
+{
+ kseg0_program_mem (rx) : ORIGIN = 0x9D000000, LENGTH = 0x80000
+ kseg0_boot_mem : ORIGIN = 0x9FC00490, LENGTH = 0x970
+ exception_mem : ORIGIN = 0x9FC01000, LENGTH = 0x1000
+ kseg1_boot_mem : ORIGIN = 0xBFC00000, LENGTH = 0x490
+ debug_exec_mem : ORIGIN = 0xBFC02000, LENGTH = 0xFF0
+ config3 : ORIGIN = 0xBFC02FF0, LENGTH = 0x4
+ config2 : ORIGIN = 0xBFC02FF4, LENGTH = 0x4
+ config1 : ORIGIN = 0xBFC02FF8, LENGTH = 0x4
+ config0 : ORIGIN = 0xBFC02FFC, LENGTH = 0x4
+ kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000
+ sfrs : ORIGIN = 0xBF800000, LENGTH = 0x100000
+ configsfrs : ORIGIN = 0xBFC02FF0, LENGTH = 0x10
+}
+SECTIONS
+{
+ .config_BFC02FF0 : {
+ KEEP(*(.config_BFC02FF0))
+ } > config3
+ .config_BFC02FF4 : {
+ KEEP(*(.config_BFC02FF4))
+ } > config2
+ .config_BFC02FF8 : {
+ KEEP(*(.config_BFC02FF8))
+ } > config1
+ .config_BFC02FFC : {
+ KEEP(*(.config_BFC02FFC))
+ } > config0
+ .text :
+ {
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ } > kseg0_program_mem
+}
\ No newline at end of file
diff --git a/bsp/pic32ethernet/project.cbp b/bsp/pic32ethernet/project.cbp
index 28543d7b5994c07837b4b376157933565a9ed96b..912c26fd867216e4e219d64a1d874aa9e4a1c8cc 100644
--- a/bsp/pic32ethernet/project.cbp
+++ b/bsp/pic32ethernet/project.cbp
@@ -28,10 +28,343 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/bsp/pic32ethernet/project.mcp b/bsp/pic32ethernet/project.mcp
index 8bb29c4bee85c83d44c322afbb88cb6c3d2d52db..5649b16d2c70ffb699ddf414ec41434d31ef0f7b 100644
--- a/bsp/pic32ethernet/project.mcp
+++ b/bsp/pic32ethernet/project.mcp
@@ -8,7 +8,7 @@ dir_src=
dir_bin=./obj
dir_tmp=./obj
dir_sin=
-dir_inc=.;../../include
+dir_inc=.;../../include;../../components/finsh
dir_lib=C:\Program Files\Microchip\MPLAB C32 Suite\lib;C:\Program Files\Microchip\MPLAB C32 Suite\pic32mx\lib
dir_lkr=
[CAT_FILTERS]
@@ -18,7 +18,7 @@ filter_obj=*.o
filter_lib=*.a
filter_lkr=*.ld
[CAT_SUBFOLDERS]
-subfolder_src=kernel;pic32
+subfolder_src=finsh;kernel;pic32
subfolder_inc=
subfolder_obj=
subfolder_lib=
@@ -46,7 +46,21 @@ file_018=pic32
file_019=pic32
file_020=.
file_021=pic32
-file_022=.
+file_022=finsh
+file_023=finsh
+file_024=finsh
+file_025=finsh
+file_026=finsh
+file_027=finsh
+file_028=finsh
+file_029=finsh
+file_030=finsh
+file_031=finsh
+file_032=finsh
+file_033=finsh
+file_034=finsh
+file_035=.
+file_036=.
[GENERATED_FILES]
file_000=no
file_001=no
@@ -71,6 +85,20 @@ file_019=no
file_020=no
file_021=no
file_022=no
+file_023=no
+file_024=no
+file_025=no
+file_026=no
+file_027=no
+file_028=no
+file_029=no
+file_030=no
+file_031=no
+file_032=no
+file_033=no
+file_034=no
+file_035=no
+file_036=no
[OTHER_FILES]
file_000=no
file_001=no
@@ -95,6 +123,20 @@ file_019=no
file_020=no
file_021=no
file_022=no
+file_023=no
+file_024=no
+file_025=no
+file_026=no
+file_027=no
+file_028=no
+file_029=no
+file_030=no
+file_031=no
+file_032=no
+file_033=no
+file_034=no
+file_035=no
+file_036=no
[FILE_INFO]
file_000=board.c
file_001=application.c
@@ -118,13 +160,28 @@ file_018=..\..\libcpu\mips\pic32\context_gcc.S
file_019=..\..\libcpu\mips\pic32\stack.c
file_020=console.c
file_021=..\..\libcpu\mips\pic32\interrupt.c
-file_022=rtconfig.h
+file_022=..\..\components\finsh\finsh_node.c
+file_023=..\..\components\finsh\finsh_ops.c
+file_024=..\..\components\finsh\finsh_parser.c
+file_025=..\..\components\finsh\finsh_token.c
+file_026=..\..\components\finsh\finsh_var.c
+file_027=..\..\components\finsh\finsh_vm.c
+file_028=..\..\components\finsh\shell.c
+file_029=..\..\components\finsh\symbol.c
+file_030=..\..\components\finsh\cmd.c
+file_031=..\..\components\finsh\finsh_compiler.c
+file_032=..\..\components\finsh\finsh_error.c
+file_033=..\..\components\finsh\finsh_heap.c
+file_034=..\..\components\finsh\finsh_init.c
+file_035=uart.c
+file_036=rtconfig.h
[SUITE_INFO]
suite_guid={14495C23-81F8-43F3-8A44-859C583D7760}
suite_state=
[TOOL_SETTINGS]
TS{CB0AF4B8-4022-429D-8F99-8A56782B2C6D}=--gdwarf-2
-TS{9C698E0A-CBC9-4EFF-AE7D-B569F93E7322}=-g -DPIC32_STARTER_KIT
+TS{9C698E0A-CBC9-4EFF-AE7D-B569F93E7322}=-g -DPIC32_STARTER_KIT -G0
+TS{9C698E0A-CBC9-4EFF-AE7D-B569F93E7322}_alt=yes
TS{77F59DA1-3C53-4677-AC5F-A03EB0125170}=-Map="$(BINDIR_)$(TARGETBASE).map" -o"$(BINDIR_)$(TARGETBASE).$(TARGETSUFFIX)"
TS{0396C0A1-9052-4E4F-8B84-EF0162B1B4E9}=
[INSTRUMENTED_TRACE]
diff --git a/bsp/pic32ethernet/project.mcw b/bsp/pic32ethernet/project.mcw
index 6473508f56f33a31c93f4f9d7f9267a1fc3583f2..56e9837cae52e2030093748395068a2105546d28 100644
Binary files a/bsp/pic32ethernet/project.mcw and b/bsp/pic32ethernet/project.mcw differ
diff --git a/bsp/pic32ethernet/rtconfig.h b/bsp/pic32ethernet/rtconfig.h
index de33c2e4bb0853454c15d25d51133e96fbf1a8d0..9ea423c79bbd110ae6c5103613ec4bcd9abb7349 100644
--- a/bsp/pic32ethernet/rtconfig.h
+++ b/bsp/pic32ethernet/rtconfig.h
@@ -70,17 +70,13 @@
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
-#define RT_USING_NEWLIB
+//#define RT_USING_NEWLIB
/* SECTION: finsh, a C-Express shell */
-//#define RT_USING_FINSH
+#define RT_USING_FINSH
/* Using symbol table */
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
-#define __fsymtab_start _alt_partition_FSymTab_start
-#define __fsymtab_end _alt_partition_FSymTab_end
-#define __vsymtab_start _alt_partition_VSymTab_start
-#define __vsymtab_end _alt_partition_VSymTab_end
/* SECTION: device filesystem */
//#define RT_USING_DFS
diff --git a/bsp/pic32ethernet/startup.c b/bsp/pic32ethernet/startup.c
index e26bd5885d3088d9a4ee0e68163f3e2d47b32bec..641c8cd7dc902cb934842bd03168eb34f991f73b 100644
--- a/bsp/pic32ethernet/startup.c
+++ b/bsp/pic32ethernet/startup.c
@@ -19,6 +19,11 @@
extern int _ramfunc_end;
#define PIC32_SRAM_END (0xA0000000+0x8000) //795F512L 512KB
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
/**
* This function will startup RT-Thread RTOS.
*/
@@ -71,13 +76,13 @@ void rtthread_startup(void)
/* init application */
rt_application_init();
-//#ifdef RT_USING_FINSH
-// /* init finsh */
-// finsh_system_init();
-//#ifdef RT_USING_DEVICE
-// finsh_set_device("uart2");
-//#endif
-//#endif
+#ifdef RT_USING_FINSH
+ /* init finsh */
+ finsh_system_init();
+#ifdef RT_USING_DEVICE
+ finsh_set_device("uart1");
+#endif
+#endif
/* init timer thread */
rt_system_timer_thread_init();
diff --git a/bsp/pic32ethernet/uart.c b/bsp/pic32ethernet/uart.c
new file mode 100644
index 0000000000000000000000000000000000000000..dcc1d3b45035b44fedc413f344f3f6893c67deac
--- /dev/null
+++ b/bsp/pic32ethernet/uart.c
@@ -0,0 +1,277 @@
+#include
+#include
+
+#include
+
+#include "uart.h"
+
+#define GetSystemClock() (80000000ul)
+#define GetPeripheralClock() (GetSystemClock()/(1 << OSCCONbits.PBDIV))
+#define GetInstructionClock() (GetSystemClock())
+
+struct rt_uart_pic32
+{
+ struct rt_device parent;
+
+ int uart; /* UART Module ID. */
+
+ /* buffer for reception */
+ rt_uint8_t read_index, save_index;
+ rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+};
+
+#ifdef RT_USING_UART1
+static struct rt_uart_pic32 uart1_device;
+#endif
+
+#ifdef RT_USING_UART2
+static struct rt_uart_pic32 uart2_device;
+#endif
+
+static rt_err_t rt_uart_init (rt_device_t dev)
+{
+ struct rt_uart_pic32 *uart_device = (struct rt_uart_pic32*)dev;
+
+ UARTConfigure(uart_device->uart, UART_ENABLE_PINS_TX_RX_ONLY);
+ UARTSetFifoMode(uart_device->uart, UART_INTERRUPT_ON_TX_NOT_FULL | UART_INTERRUPT_ON_RX_NOT_EMPTY);
+ UARTSetLineControl(uart_device->uart, UART_DATA_SIZE_8_BITS | UART_PARITY_NONE | UART_STOP_BITS_1);
+ UARTSetDataRate(uart_device->uart, GetPeripheralClock(), 115200);
+ UARTEnable(uart_device->uart, UART_ENABLE_FLAGS(UART_PERIPHERAL | UART_RX | UART_TX));
+
+ // Configure UART RX Interrupt
+ INTEnable(INT_SOURCE_UART_RX(uart_device->uart), INT_ENABLED);
+ INTSetVectorPriority(INT_VECTOR_UART(uart_device->uart), INT_PRIORITY_LEVEL_2);
+ INTSetVectorSubPriority(INT_VECTOR_UART(uart_device->uart), INT_SUB_PRIORITY_LEVEL_0);
+
+ return RT_EOK;
+}
+
+static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_uart_close(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ struct rt_uart_pic32 *uart_device = (struct rt_uart_pic32*)dev;
+ RT_ASSERT(uart_device != RT_NULL);
+
+ /* point to buffer */
+ ptr = (rt_uint8_t*) buffer;
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ while (size)
+ {
+ /* interrupt receive */
+ rt_base_t level;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+ if (uart_device->read_index != uart_device->save_index)
+ {
+ *ptr = uart_device->rx_buffer[uart_device->read_index];
+
+ uart_device->read_index ++;
+ if (uart_device->read_index >= RT_UART_RX_BUFFER_SIZE)
+ uart_device->read_index = 0;
+ }
+ else
+ {
+ /* no data in rx buffer */
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ break;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+
+ ptr ++;
+ size --;
+ }
+
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+ }
+
+ return 0;
+}
+
+static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+ struct rt_uart_pic32 *uart_device = (struct rt_uart_pic32*)dev;
+ char *ptr;
+ ptr = (char*)buffer;
+
+ if (dev->flag & RT_DEVICE_FLAG_STREAM)
+ {
+ /* stream mode */
+ while (size)
+ {
+ if (*ptr == '\n')
+ {
+ while(!UARTTransmitterIsReady(uart_device->uart));
+ UARTSendDataByte(uart_device->uart,'\r' );
+ while(!UARTTransmissionHasCompleted(uart_device->uart));
+ }
+ while(!UARTTransmitterIsReady(uart_device->uart));
+ UARTSendDataByte(uart_device->uart, *ptr);
+ while(!UARTTransmissionHasCompleted(uart_device->uart));
+
+ ptr ++;
+ size --;
+ }
+ }
+ else
+ {
+ while ( size != 0 )
+ {
+ while(!UARTTransmitterIsReady(uart_device->uart));
+ UARTSendDataByte(uart_device->uart, *ptr);
+ while(!UARTTransmissionHasCompleted(uart_device->uart));
+
+ ptr++;
+ size--;
+ }
+ }
+
+ return (rt_size_t) ptr - (rt_size_t) buffer;
+}
+
+
+#ifdef RT_USING_UART1
+// UART 1 interrupt handler
+// it is set at priority level 2
+void __ISR(_UART1_VECTOR, ipl2) IntUART1Handler(void)
+{
+ struct rt_uart_pic32 *uart_device = &uart1_device;
+
+ // Is this an RX interrupt?
+ if(INTGetFlag(INT_SOURCE_UART_RX(uart_device->uart)))
+ {
+ // Clear the RX interrupt Flag
+ INTClearFlag(INT_SOURCE_UART_RX(uart_device->uart));
+
+ /* Receive Data Available */
+ uart_device->rx_buffer[uart_device->save_index] = UARTGetDataByte(uart_device->uart);//UARTGetDataByte(UART1);
+ uart_device->save_index ++;
+ if (uart_device->save_index >= RT_UART_RX_BUFFER_SIZE)
+ uart_device->save_index = 0;
+
+ /* invoke callback */
+ if(uart_device->parent.rx_indicate != RT_NULL)
+ {
+ rt_size_t length;
+ if (uart_device->read_index > uart_device->save_index)
+ length = RT_UART_RX_BUFFER_SIZE - uart_device->read_index + uart_device->save_index;
+ else
+ length = uart_device->save_index - uart_device->read_index;
+
+ uart_device->parent.rx_indicate(&uart_device->parent, length);
+ }
+
+ // Clear the RX interrupt Flag
+ INTClearFlag(INT_SOURCE_UART_RX(uart_device->uart));
+ } // Is this an RX interrupt?
+
+ // We don't care about TX interrupt
+ if ( INTGetFlag(INT_SOURCE_UART_TX(uart_device->uart)) )
+ {
+ INTClearFlag(INT_SOURCE_UART_TX(uart_device->uart));
+ }
+}
+#endif
+
+#ifdef RT_USING_UART2
+// UART 2 interrupt handler
+// it is set at priority level 2
+void __ISR(_UART2_VECTOR, ipl2) IntUART2Handler(void)
+{
+ struct rt_uart_pic32 *uart_device = &uart2_device;
+
+ // Is this an RX interrupt?
+ if(INTGetFlag(INT_SOURCE_UART_RX(uart_device->uart)))
+ {
+ // Clear the RX interrupt Flag
+ INTClearFlag(INT_SOURCE_UART_RX(uart_device->uart));
+
+ /* Receive Data Available */
+ uart_device->rx_buffer[uart_device->save_index] = UARTGetDataByte(uart_device->uart);//UARTGetDataByte(UART1);
+ uart_device->save_index ++;
+ if (uart_device->save_index >= RT_UART_RX_BUFFER_SIZE)
+ uart_device->save_index = 0;
+
+ /* invoke callback */
+ if(uart_device->parent.rx_indicate != RT_NULL)
+ {
+ rt_size_t length;
+ if (uart_device->read_index > uart_device->save_index)
+ length = RT_UART_RX_BUFFER_SIZE - uart_device->read_index + uart_device->save_index;
+ else
+ length = uart_device->save_index - uart_device->read_index;
+
+ uart_device->parent.rx_indicate(&uart_device->parent, length);
+ }
+
+ // Clear the RX interrupt Flag
+ INTClearFlag(INT_SOURCE_UART_RX(uart_device->uart));
+ } // Is this an RX interrupt?
+
+ // We don't care about TX interrupt
+ if ( INTGetFlag(INT_SOURCE_UART_TX(uart_device->uart)) )
+ {
+ INTClearFlag(INT_SOURCE_UART_TX(uart_device->uart));
+ }
+}
+#endif
+
+void rt_hw_usart_init(void)
+{
+ struct rt_uart_pic32 *uart_device;
+
+#ifdef RT_USING_UART1
+ /* device initialization */
+ uart_device = &uart1_device;
+ rt_memset(uart_device,0,sizeof(struct rt_uart_pic32));
+ uart_device->uart = UART1;
+ uart_device->parent.type = RT_Device_Class_Char;
+
+ /* device interface */
+ uart_device->parent.init = rt_uart_init;
+ uart_device->parent.open = rt_uart_open;
+ uart_device->parent.close = rt_uart_close;
+ uart_device->parent.read = rt_uart_read;
+ uart_device->parent.write = rt_uart_write;
+ uart_device->parent.control = RT_NULL;
+ uart_device->parent.user_data = RT_NULL;
+
+ rt_device_register(&uart_device->parent,
+ "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+#endif
+
+#ifdef RT_USING_UART2
+ /* device initialization */
+ uart_device = &uart2_device;
+ rt_memset(uart_device,0,sizeof(struct rt_uart_pic32));
+ uart_device->uart = UART2;
+ uart_device->parent.type = RT_Device_Class_Char;
+
+ /* device interface */
+ uart_device->parent.init = rt_uart_init;
+ uart_device->parent.open = rt_uart_open;
+ uart_device->parent.close = rt_uart_close;
+ uart_device->parent.read = rt_uart_read;
+ uart_device->parent.write = rt_uart_write;
+ uart_device->parent.control = RT_NULL;
+ uart_device->parent.user_data = RT_NULL;
+
+ rt_device_register(&uart_device->parent,
+ "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+#endif
+}
diff --git a/bsp/pic32ethernet/uart.h b/bsp/pic32ethernet/uart.h
new file mode 100644
index 0000000000000000000000000000000000000000..1a96d622b426248c9958ff4f02b024672e242626
--- /dev/null
+++ b/bsp/pic32ethernet/uart.h
@@ -0,0 +1,10 @@
+#ifndef UART_H_INCLUDED
+#define UART_H_INCLUDED
+
+#define RT_UART_RX_BUFFER_SIZE 64
+
+#define RT_USING_UART1
+#define RT_USING_UART2
+
+
+#endif // UART_H_INCLUDED