diff --git a/bsp/simulator/drivers/dfs_win32.c b/bsp/simulator/drivers/dfs_win32.c
index 51f0d295daadcf19d099ab305d22518229256dd5..32e09f03f793d6cfe41641bba7b6d9ae44e26197 100644
--- a/bsp/simulator/drivers/dfs_win32.c
+++ b/bsp/simulator/drivers/dfs_win32.c
@@ -1,4 +1,3 @@
-
 /*
  * File      : rtthread.h
  * This file is part of RT-Thread RTOS
@@ -11,6 +10,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2012-11-27     prife        the first version
+ * 2013-03-03     aozima       add dfs_win32_stat st_mtime support.
  */
 #include <rtthread.h>
 
@@ -473,7 +473,21 @@ static int dfs_win32_stat(struct dfs_filesystem *fs, const char *path, struct st
 
     st->st_dev  = 0;
     st->st_size = fileInfo.nFileSizeLow;
-    st->st_mtime = 0;
+
+    /* get st_mtime. */
+    {
+        LARGE_INTEGER time_tmp;
+        time_tmp.LowPart = fileInfo.ftLastWriteTime.dwLowDateTime;
+        time_tmp.HighPart = fileInfo.ftLastWriteTime.dwHighDateTime;
+
+        /* removes the diff between 1970 and 1601. */
+        time_tmp.QuadPart -= 11644473600000 * 10000;
+        /* converts back from 100-nanoseconds to seconds. */
+        time_tmp.QuadPart /= 10UL * 1000 * 1000;
+
+        st->st_mtime = time_tmp.QuadPart;
+    }
+
     st->st_blksize = 0;
 
     FindClose(hFind);
diff --git a/libcpu/mips/jz47xx/start_gcc.S b/libcpu/mips/jz47xx/start_gcc.S
index 162c491b1d311f397425090618b4de7741703d22..418a68d0f8bbeb0802a392cb22bec68d6b7579c7 100644
--- a/libcpu/mips/jz47xx/start_gcc.S
+++ b/libcpu/mips/jz47xx/start_gcc.S
@@ -19,24 +19,24 @@ _start:
     .set    noreorder
     la      ra, _start
 
+    li	    t1, 0x00800000
+    mtc0    t1, CP0_CAUSE
+
     /* init cp0 registers. */
     li	    t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
     mtc0    t0, CP0_STATUS
 
-    li	    t1, 0x00800000
-    mtc0    t1, CP0_CAUSE
-
     /* setup stack pointer */
     li      sp, SYSTEM_STACK
     la      gp, _gp
 
     /* init caches, assumes a 4way * 128set * 32byte I/D cache */
+    mtc0    zero, CP0_TAGLO  /* TAGLO reg */
+    mtc0    zero, CP0_TAGHI  /* TAGHI reg */
     li      t0, 3            /* enable cache for kseg0 accesses */
     mtc0    t0, CP0_CONFIG    /* CONFIG reg */
     la      t0, 0x80000000   /* an idx op should use an unmappable address */
     ori     t1, t0, 0x4000   /* 16kB cache */
-    mtc0    zero, CP0_TAGLO  /* TAGLO reg */
-    mtc0    zero, CP0_TAGHI  /* TAGHI reg */
 
 _cache_loop:
     cache   0x8, 0(t0)       /* index store icache tag */