From a97b0a0d3972ad332a6afb2b7472163ff7f57ac0 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Fri, 11 Sep 2020 11:44:49 +0800 Subject: [PATCH] code format --- bsp/ls2kdev/drivers/board.h | 2 +- bsp/ls2kdev/drivers/clk.c | 1 - bsp/ls2kdev/drivers/drv_gpio.c | 4 +- bsp/ls2kdev/drivers/drv_gpio.h | 3 +- bsp/ls2kdev/drivers/drv_uart.h | 149 +- bsp/ls2kdev/drivers/interrupt.h | 26 +- bsp/ls2kdev/drivers/ls2k1000.h | 16 +- bsp/ls2kdev/drivers/net/mii.c | 2 +- bsp/ls2kdev/drivers/net/mii.h | 34 +- bsp/ls2kdev/drivers/net/synopGMAC.c | 4 - bsp/ls2kdev/drivers/net/synopGMAC_Dev.c | 172 +-- bsp/ls2kdev/drivers/net/synopGMAC_Dev.h | 1694 +++++++++++----------- bsp/ls2kdev/drivers/net/synopGMAC_plat.h | 2 +- libcpu/mips/gs264/cache.c | 2 +- libcpu/mips/gs264/cpuinit_gcc.S | 8 +- libcpu/mips/gs264/mips_mmu.c | 32 +- libcpu/mips/gs264/mips_mmu.h | 155 +- libcpu/mips/gs264/mipscfg.c | 14 +- libcpu/mips/gs264/mmu.c | 8 +- libcpu/mips/gs264/mmu.h | 24 +- 20 files changed, 1140 insertions(+), 1212 deletions(-) diff --git a/bsp/ls2kdev/drivers/board.h b/bsp/ls2kdev/drivers/board.h index 927a789af0..ca57ebf3f2 100644 --- a/bsp/ls2kdev/drivers/board.h +++ b/bsp/ls2kdev/drivers/board.h @@ -15,7 +15,7 @@ extern unsigned char __bss_end; -#define CPU_HZ (1000 * 1000 * 1000) //QEMU 200*1000*1000 +#define CPU_HZ (1000 * 1000 * 1000) //QEMU 200*1000*1000 #define RT_HW_HEAP_BEGIN (void*)&__bss_end #define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024) diff --git a/bsp/ls2kdev/drivers/clk.c b/bsp/ls2kdev/drivers/clk.c index aba08bd87a..7a043e9ff4 100644 --- a/bsp/ls2kdev/drivers/clk.c +++ b/bsp/ls2kdev/drivers/clk.c @@ -14,7 +14,6 @@ #include #include "ls2k1000.h" - struct loongson_pll { rt_uint64_t PLL_SYS_0; rt_uint64_t PLL_SYS_1; diff --git a/bsp/ls2kdev/drivers/drv_gpio.c b/bsp/ls2kdev/drivers/drv_gpio.c index 155807461f..abf9fdc8af 100644 --- a/bsp/ls2kdev/drivers/drv_gpio.c +++ b/bsp/ls2kdev/drivers/drv_gpio.c @@ -5,8 +5,8 @@ * Change Logs: * Date Author Notes * 2015-01-20 Bernard the first version - * 2017-10-20 ZYH add mode open drain and input pull down - * 2020-06-01 Du Huanpeng GPIO driver based on + * 2017-10-20 ZYH add mode open drain and input pull down + * 2020-06-01 Du Huanpeng GPIO driver based on */ #include #include diff --git a/bsp/ls2kdev/drivers/drv_gpio.h b/bsp/ls2kdev/drivers/drv_gpio.h index 51a75c306e..4bf1ba80f5 100644 --- a/bsp/ls2kdev/drivers/drv_gpio.h +++ b/bsp/ls2kdev/drivers/drv_gpio.h @@ -6,7 +6,7 @@ * * Change Logs: * Date Author Notes - * 2017-11-24 勤为本 first version + * 2017-11-24 勤为本 first version * 2018-05-11 zhuangwei add gpio interrupt ops */ @@ -36,6 +36,5 @@ struct loongson_gpio { int loongson_pin_init(void); - #endif diff --git a/bsp/ls2kdev/drivers/drv_uart.h b/bsp/ls2kdev/drivers/drv_uart.h index 4d17b99b35..ca3e856d06 100644 --- a/bsp/ls2kdev/drivers/drv_uart.h +++ b/bsp/ls2kdev/drivers/drv_uart.h @@ -15,100 +15,99 @@ #include /* UART registers */ -#define UART_DAT(base) HWREG8(base + 0x00) -#define UART_IER(base) HWREG8(base + 0x01) -#define UART_IIR(base) HWREG8(base + 0x02) -#define UART_FCR(base) HWREG8(base + 0x02) -#define UART_LCR(base) HWREG8(base + 0x03) -#define UART_MCR(base) HWREG8(base + 0x04) -#define UART_LSR(base) HWREG8(base + 0x05) -#define UART_MSR(base) HWREG8(base + 0x06) +#define UART_DAT(base) HWREG8(base + 0x00) +#define UART_IER(base) HWREG8(base + 0x01) +#define UART_IIR(base) HWREG8(base + 0x02) +#define UART_FCR(base) HWREG8(base + 0x02) +#define UART_LCR(base) HWREG8(base + 0x03) +#define UART_MCR(base) HWREG8(base + 0x04) +#define UART_LSR(base) HWREG8(base + 0x05) +#define UART_MSR(base) HWREG8(base + 0x06) -#define UART_LSB(base) HWREG8(base + 0x00) -#define UART_MSB(base) HWREG8(base + 0x01) +#define UART_LSB(base) HWREG8(base + 0x00) +#define UART_MSB(base) HWREG8(base + 0x01) /* interrupt enable register */ -#define IER_IRxE 0x1 -#define IER_ITxE 0x2 -#define IER_ILE 0x4 -#define IER_IME 0x8 +#define IER_IRxE 0x1 +#define IER_ITxE 0x2 +#define IER_ILE 0x4 +#define IER_IME 0x8 /* interrupt identification register */ -#define IIR_IMASK 0xf /* mask */ -#define IIR_RXTOUT 0xc /* receive timeout */ -#define IIR_RLS 0x6 /* receive line status */ -#define IIR_RXRDY 0x4 /* receive ready */ -#define IIR_TXRDY 0x2 /* transmit ready */ -#define IIR_NOPEND 0x1 /* nothing */ -#define IIR_MLSC 0x0 /* modem status */ -#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ +#define IIR_IMASK 0xf /* mask */ +#define IIR_RXTOUT 0xc /* receive timeout */ +#define IIR_RLS 0x6 /* receive line status */ +#define IIR_RXRDY 0x4 /* receive ready */ +#define IIR_TXRDY 0x2 /* transmit ready */ +#define IIR_NOPEND 0x1 /* nothing */ +#define IIR_MLSC 0x0 /* modem status */ +#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ /* fifo control register */ -#define FIFO_ENABLE 0x01 /* enable fifo */ -#define FIFO_RCV_RST 0x02 /* reset receive fifo */ -#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ -#define FIFO_DMA_MODE 0x08 /* enable dma mode */ -#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ -#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ -#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ -#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ +#define FIFO_ENABLE 0x01 /* enable fifo */ +#define FIFO_RCV_RST 0x02 /* reset receive fifo */ +#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ +#define FIFO_DMA_MODE 0x08 /* enable dma mode */ +#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ +#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ +#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ +#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ -// 线路控制寄存器 /* character format control register */ -#define CFCR_DLAB 0x80 /* divisor latch */ -#define CFCR_SBREAK 0x40 /* send break */ -#define CFCR_PZERO 0x30 /* zero parity */ -#define CFCR_PONE 0x20 /* one parity */ -#define CFCR_PEVEN 0x10 /* even parity */ -#define CFCR_PODD 0x00 /* odd parity */ -#define CFCR_PENAB 0x08 /* parity enable */ -#define CFCR_STOPB 0x04 /* 2 stop bits */ -#define CFCR_8BITS 0x03 /* 8 data bits */ -#define CFCR_7BITS 0x02 /* 7 data bits */ -#define CFCR_6BITS 0x01 /* 6 data bits */ -#define CFCR_5BITS 0x00 /* 5 data bits */ +#define CFCR_DLAB 0x80 /* divisor latch */ +#define CFCR_SBREAK 0x40 /* send break */ +#define CFCR_PZERO 0x30 /* zero parity */ +#define CFCR_PONE 0x20 /* one parity */ +#define CFCR_PEVEN 0x10 /* even parity */ +#define CFCR_PODD 0x00 /* odd parity */ +#define CFCR_PENAB 0x08 /* parity enable */ +#define CFCR_STOPB 0x04 /* 2 stop bits */ +#define CFCR_8BITS 0x03 /* 8 data bits */ +#define CFCR_7BITS 0x02 /* 7 data bits */ +#define CFCR_6BITS 0x01 /* 6 data bits */ +#define CFCR_5BITS 0x00 /* 5 data bits */ /* modem control register */ -#define MCR_LOOPBACK 0x10 /* loopback */ -#define MCR_IENABLE 0x08 /* output 2 = int enable */ -#define MCR_DRS 0x04 /* output 1 = xxx */ -#define MCR_RTS 0x02 /* enable RTS */ -#define MCR_DTR 0x01 /* enable DTR */ +#define MCR_LOOPBACK 0x10 /* loopback */ +#define MCR_IENABLE 0x08 /* output 2 = int enable */ +#define MCR_DRS 0x04 /* output 1 = xxx */ +#define MCR_RTS 0x02 /* enable RTS */ +#define MCR_DTR 0x01 /* enable DTR */ /* line status register */ -#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ -#define LSR_TSRE 0x40 /* transmitter empty */ -#define LSR_TXRDY 0x20 /* transmitter ready */ -#define LSR_BI 0x10 /* break detected */ -#define LSR_FE 0x08 /* framing error */ -#define LSR_PE 0x04 /* parity error */ -#define LSR_OE 0x02 /* overrun error */ -#define LSR_RXRDY 0x01 /* receiver ready */ -#define LSR_RCV_MASK 0x1f +#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ +#define LSR_TSRE 0x40 /* transmitter empty */ +#define LSR_TXRDY 0x20 /* transmitter ready */ +#define LSR_BI 0x10 /* break detected */ +#define LSR_FE 0x08 /* framing error */ +#define LSR_PE 0x04 /* parity error */ +#define LSR_OE 0x02 /* overrun error */ +#define LSR_RXRDY 0x01 /* receiver ready */ +#define LSR_RCV_MASK 0x1f /* UART interrupt enable register value */ -#define UARTIER_IME (1 << 3) -#define UARTIER_ILE (1 << 2) -#define UARTIER_ITXE (1 << 1) -#define UARTIER_IRXE (1 << 0) +#define UARTIER_IME (1 << 3) +#define UARTIER_ILE (1 << 2) +#define UARTIER_ITXE (1 << 1) +#define UARTIER_IRXE (1 << 0) /* UART line control register value */ -#define UARTLCR_DLAB (1 << 7) -#define UARTLCR_BCB (1 << 6) -#define UARTLCR_SPB (1 << 5) -#define UARTLCR_EPS (1 << 4) -#define UARTLCR_PE (1 << 3) -#define UARTLCR_SB (1 << 2) +#define UARTLCR_DLAB (1 << 7) +#define UARTLCR_BCB (1 << 6) +#define UARTLCR_SPB (1 << 5) +#define UARTLCR_EPS (1 << 4) +#define UARTLCR_PE (1 << 3) +#define UARTLCR_SB (1 << 2) /* UART line status register value */ -#define UARTLSR_ERROR (1 << 7) -#define UARTLSR_TE (1 << 6) -#define UARTLSR_TFE (1 << 5) -#define UARTLSR_BI (1 << 4) -#define UARTLSR_FE (1 << 3) -#define UARTLSR_PE (1 << 2) -#define UARTLSR_OE (1 << 1) -#define UARTLSR_DR (1 << 0) +#define UARTLSR_ERROR (1 << 7) +#define UARTLSR_TE (1 << 6) +#define UARTLSR_TFE (1 << 5) +#define UARTLSR_BI (1 << 4) +#define UARTLSR_FE (1 << 3) +#define UARTLSR_PE (1 << 2) +#define UARTLSR_OE (1 << 1) +#define UARTLSR_DR (1 << 0) #endif diff --git a/bsp/ls2kdev/drivers/interrupt.h b/bsp/ls2kdev/drivers/interrupt.h index 18707f7321..df55437cf9 100644 --- a/bsp/ls2kdev/drivers/interrupt.h +++ b/bsp/ls2kdev/drivers/interrupt.h @@ -64,22 +64,22 @@ #define LS2K_GPIO2_INT_IRQ (62) #define LS2K_GPIO3_INT_IRQ (63) -#define MAX_INTR 64 -#define LIOINTC0_IRQBASE 0 -#define LIOINTC1_IRQBASE 32 +#define MAX_INTR (64) +#define LIOINTC0_IRQBASE (0) +#define LIOINTC1_IRQBASE (32) -#define LIOINTC_SHIFT_INTx 4 -#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx))) +#define LIOINTC_SHIFT_INTx (4) +#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx))) -#define LIOINTC_INTC_CHIP_START 0x20 +#define LIOINTC_INTC_CHIP_START 0x20 -#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00) -#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) -#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) -#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) -#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) -#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00) +#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) +#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) +#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) +#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) +#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) void liointc_set_irq_mode(int irq, int mode); -#endif \ No newline at end of file +#endif diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h index 24396e7d3b..38e83875fb 100644 --- a/bsp/ls2kdev/drivers/ls2k1000.h +++ b/bsp/ls2kdev/drivers/ls2k1000.h @@ -6,11 +6,11 @@ #define APB_BASE CKSEG1ADDR(0xbfe00000) -#define UART0_BASE_ADDR 0xbfe00000 -#define UART0_OFF 0x0 -#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF) +#define UART0_BASE_ADDR (0xbfe00000) +#define UART0_OFF (0x0) +#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF) -#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8))) +#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8))) #define LIOINTC0_BASE CKSEG1ADDR(0x1fe11400) #define CORE0_INTISR0 CKSEG1ADDR(0x1fe11040) @@ -18,11 +18,11 @@ #define LIOINTC1_BASE CKSEG1ADDR(0x1fe11440) #define CORE0_INTISR1 CKSEG1ADDR(0x1fe11048) -#define GPIO_BASE 0xFFFFFFFFBFE10500 -#define PLL_SYS_BASE 0xFFFFFFFFBFE10480 -#define RTC_BASE 0xFFFFFFFFBFE07820 +#define GPIO_BASE (0xFFFFFFFFBFE10500) +#define PLL_SYS_BASE (0xFFFFFFFFBFE10480) +#define RTC_BASE (0xFFFFFFFFBFE07820) -#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420 +#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420) void rt_hw_timer_handler(void); void rt_hw_uart_init(void); diff --git a/bsp/ls2kdev/drivers/net/mii.c b/bsp/ls2kdev/drivers/net/mii.c index b06475df12..a0b3a7adce 100644 --- a/bsp/ls2kdev/drivers/net/mii.c +++ b/bsp/ls2kdev/drivers/net/mii.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls2kdev/drivers/net/mii.h b/bsp/ls2kdev/drivers/net/mii.h index 994d560c50..bc6d6c7a0c 100644 --- a/bsp/ls2kdev/drivers/net/mii.h +++ b/bsp/ls2kdev/drivers/net/mii.h @@ -37,7 +37,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -135,8 +135,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -170,11 +170,11 @@ /* Which connector port. */ -#define PORT_TP 0x00 -#define PORT_AUI 0x01 -#define PORT_MII 0x02 -#define PORT_FIBRE 0x03 -#define PORT_BNC 0x04 +#define PORT_TP 0x00 +#define PORT_AUI 0x01 +#define PORT_MII 0x02 +#define PORT_FIBRE 0x03 +#define PORT_BNC 0x04 /* Which transceiver to use. */ #define XCVR_INTERNAL 0x00 @@ -183,18 +183,18 @@ #define XCVR_DUMMY2 0x03 #define XCVR_DUMMY3 0x04 -#define AUTONEG_DISABLE 0x00 -#define AUTONEG_ENABLE 0x01 +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 -#define SPEED_2500 2500 -#define SPEED_10000 10000 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 struct ethtool_cmd { u32 cmd; diff --git a/bsp/ls2kdev/drivers/net/synopGMAC.c b/bsp/ls2kdev/drivers/net/synopGMAC.c index 38a6345236..f58f67ff5f 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC.c +++ b/bsp/ls2kdev/drivers/net/synopGMAC.c @@ -260,7 +260,6 @@ s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter) return gmacdev->Speed | (gmacdev->DuplexMode << 4); } - static int Mac_change_check(u8 *macaddr0, u8 *macaddr1) { int i; @@ -894,7 +893,6 @@ int rt_hw_eth_init(void) struct synopGMACNetworkAdapter *synopGMACadapter; static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS; int index; - //rt_kprintf("rt_hw_eth_init 1\n"); rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); @@ -958,8 +956,6 @@ int rt_hw_eth_init(void) eth_device_init(&(eth_dev.parent), "e0"); eth_device_linkchange(ð_dev.parent, RT_TRUE); //linkup the e0 for lwip to check - //rt_kprintf("rt_hw_eth_init 2\n"); return 0; } - INIT_COMPONENT_EXPORT(rt_hw_eth_init); diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c index ade261563d..cdd4585670 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c +++ b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c @@ -860,7 +860,6 @@ void synopGMAC_promisc_disable(synopGMACdevice *gmacdev) return; } - /** * Enables unicast hash filtering. * When enabled GMAC performs the destination address filtering of unicast frames according to the hash table. @@ -1032,7 +1031,6 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev) synopGMACWriteReg(gmacdev -> MacBase,GmacFlowControl,mac_flow_control_reg); return; - } /** @@ -1352,10 +1350,9 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) desc -> length = 0; #else desc -> length = last_ring_desc ? TxDescEndOfRing : 0; - desc -> status = 0; + desc -> status = 0; #endif //sw - desc -> buffer1 = 0; desc -> buffer2 = 0; desc -> data1 = 0; @@ -1365,8 +1362,6 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) return; } - - /** * Initialize the rx descriptors for chain mode of operation. * - Status field is initialized to 0. @@ -1409,7 +1404,6 @@ void synopGMAC_tx_desc_init_chain(DmaDesc * desc) return; } - s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev) { s32 i; @@ -1817,7 +1811,6 @@ void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1 } return; - } #ifdef ENH_DESC_8W @@ -1912,10 +1905,7 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 u32 txover = gmacdev->TxBusy; DmaDesc * txdesc = gmacdev->TxBusyDesc; int i; - //sw: dbg - - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R); //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG @@ -1954,12 +1944,12 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; if(synopGMAC_is_tx_desc_chained(txdesc)) - { - gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; + { + gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; synopGMAC_tx_desc_init_chain(txdesc); } else - { + { gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); } @@ -2008,37 +1998,40 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now - if(synopGMAC_is_tx_desc_chained(txdesc)){ - txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC - #else - txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor - #endif - - txdesc->buffer1 = Buffer1; - txdesc->data1 = Data1; - - if(offload_needed){ - /* - Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, - before calling any of the functions given below. - */ - synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); - synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); + if(synopGMAC_is_tx_desc_chained(txdesc)) + { + txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC + #else + txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor + #endif + + txdesc->buffer1 = Buffer1; + txdesc->data1 = Data1; + + if(offload_needed) + { + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); // synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } + #ifdef ENH_DESC + txdesc->status |= DescOwnByDma;//ENH_DESC + #else + txdesc->status = DescOwnByDma; + #endif + + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; } - #ifdef ENH_DESC - txdesc->status |= DescOwnByDma;//ENH_DESC - #else - txdesc->status = DescOwnByDma; - #endif - - gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; - gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; - } - else{ -// printf("synopGMAC_set_tx_qptr:in ring mode\n"); + else + { +// printf("synopGMAC_set_tx_qptr:in ring mode\n"); txdesc->length |= (((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC @@ -2046,13 +2039,14 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor #endif - txdesc->buffer1 = Buffer1; + txdesc->buffer1 = Buffer1; txdesc->data1 = Data1; - txdesc->buffer2 = Buffer2; + txdesc->buffer2 = Buffer2; txdesc->data2 = Data2; - if(offload_needed){ + if(offload_needed) + { /* Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, before calling any of the functions given below. @@ -2638,8 +2632,7 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) else{ synopGMAC_take_desc_ownership(desc + i); } - } - + } } /** @@ -2668,15 +2661,8 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); data &= (~DmaRxStart); synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); -} - - - +} /*******************PMT APIs***************************************/ - - - - /** * Enables the assertion of PMT interrupt. * This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame @@ -2835,9 +2821,9 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte } #endif + /*******************PMT APIs***************************************/ /*******************MMC APIs***************************************/ - /** * Freezes the MMC counters. * This function call freezes the MMC counters. None of the MMC counters are updated @@ -3081,7 +3067,6 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) * \return returns TRUE or FALSE */ #ifdef ENH_DESC_8W - /** * This function indicates whether extended status is available in the RDES0. * Any function which accesses the fields of extended status register must ensure a check on this has been made @@ -3132,8 +3117,6 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) } #endif - - /** * Decodes the Rx Descriptor status to various checksum error conditions. * @param[in] pointer to synopGMACdevice. @@ -3172,7 +3155,6 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); } - /** * Checks if any payload checksum error in the frame just transmitted. * This serves as indication that error occureed in the payload checksum insertion. @@ -3199,7 +3181,6 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des #else desc->length = (desc->length & (~DescTxCisMask)); #endif - } /** * The check summ offload engine is enabled to do only IPV4 header checksum. @@ -3215,7 +3196,6 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de #else desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs); #endif - } /** @@ -3233,7 +3213,6 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de #else desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs); #endif - } /** * The check summ offload engine is enabled to do complete checksum computation. @@ -3254,14 +3233,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc } /*******************Ip checksum offloading APIs***************************************/ - - - - - /*******************IEEE 1588 Timestamping API***************************************/ - - /* * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled. * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced @@ -3295,7 +3267,6 @@ void synopGMAC_TS_disable(synopGMACdevice *gmacdev) return; } - /** * Enable the interrupt to get timestamping interrupt. * This enables the host to get the interrupt when (1) system time is greater or equal to the @@ -3344,7 +3315,6 @@ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev) return; } - /** * Selet the type of clock mode for PTP. * Please note to use one of the follwoing as the clk_type argument. @@ -3493,7 +3463,6 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev) return; } - /** * Snoop PTP packet for version 2 format * When set the PTP packets are snooped using the version 2 format. @@ -3584,11 +3553,10 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value) if(loop_variable < DEFAULT_LOOP_VARIABLE) synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSADDREG); else{ - TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; } -return -ESYNOPGMACNOERR; - + return -ESYNOPGMACNOERR; } /** * time stamp Update @@ -3602,21 +3570,21 @@ return -ESYNOPGMACNOERR; s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { u32 loop_variable; - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register - synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time + synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register + synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break - break; + break; } plat_delay(DEFAULT_DELAY_VARIABLE); - } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT); - else{ + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT); + else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; - } -return -ESYNOPGMACNOERR; + return -ESYNOPGMACPHYERR; + } + return -ESYNOPGMACNOERR; } /** @@ -3631,21 +3599,21 @@ return -ESYNOPGMACNOERR; s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { u32 loop_variable; - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register - synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time + synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register + synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break - break; + break; } plat_delay(DEFAULT_DELAY_VARIABLE); - } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT); - else{ + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT); + else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; - } -return -ESYNOPGMACNOERR; + return -ESYNOPGMACPHYERR; + } + return -ESYNOPGMACNOERR; } /** @@ -3696,8 +3664,8 @@ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val) { * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); - * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh); - * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSLow); + * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh); + * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSLow); return; } /** diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h index fceb7af1fb..f47046d5ba 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h +++ b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h @@ -15,17 +15,17 @@ #define SYNOP_GMAC_DEV_H 1 /*******************************************************************/ -#define SYNOP_LOOPBACK_MODE 0 -#define SYNOP_LOOPBACK_DEBUG 0 -#define SYNOP_PHY_LOOPBACK 0 +#define SYNOP_LOOPBACK_MODE (0) +#define SYNOP_LOOPBACK_DEBUG (0) +#define SYNOP_PHY_LOOPBACK (0) -#define SYNOP_TX_TEST 0 -#define SYNOP_RX_TEST 0 +#define SYNOP_TX_TEST (0) +#define SYNOP_RX_TEST (0) -#define SYNOP_TOP_DEBUG 0 -#define SYNOP_REG_DEBUG 0 -#define SYNOP_RX_DEBUG 0 -#define SYNOP_TX_DEBUG 0 +#define SYNOP_TOP_DEBUG (0) +#define SYNOP_REG_DEBUG (0) +#define SYNOP_RX_DEBUG (0) +#define SYNOP_TX_DEBUG (0) #define ENH_DESC /*******************************************************************/ @@ -49,35 +49,35 @@ enum GMACPhyBase { - PHY0 = 0, //The device can support 32 phys, but we use first phy only + PHY0 = 0, //The device can support 32 phys, but we use first phy only PHY1 = 1, PHY16 = 16, PHY31 = 31, }; -//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue -//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue -//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue -#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue -#define RECEIVE_DESC_SIZE 36 //96 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue +//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue +#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue +#define RECEIVE_DESC_SIZE 36 //96 //Rx Descriptors needed in the Descriptor pool/queue -#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type -#define ETHERNET_CRC 4 //Ethernet CRC -#define ETHERNET_EXTRA 2 //Only God knows about this????? -#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb -#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA -#define VLAN_TAG 4 //optional 802.1q VLAN Tag -#define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size -#define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size -#define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size +#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type +#define ETHERNET_CRC 4 //Ethernet CRC +#define ETHERNET_EXTRA 2 //Only God knows about this????? +#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb +#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA +#define VLAN_TAG 4 //optional 802.1q VLAN Tag +#define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size +#define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size +#define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size -#define TX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000 -#define RX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000 +#define TX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000 +#define RX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000 // This is the IP's phy address. This is unique address for every MAC in the universe -#define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7} +#define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7} /* DMA Descriptor Structure @@ -98,31 +98,31 @@ In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DES #ifdef ENH_DESC_8W typedef struct DmaDescStruct { - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ /* This data below is used only by driver */ - u32 extstatus; /* Extended status of a Rx Descriptor */ - u32 reserved1; /* Reserved word */ - u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ - u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ - u64 data1; /* This holds virtual address of buffer1, not used by DMA */ - u64 data2; /* This holds virtual address of buffer2, not used by DMA */ + u32 extstatus; /* Extended status of a Rx Descriptor */ + u32 reserved1; /* Reserved word */ + u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ + u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ + u64 data1; /* This holds virtual address of buffer1, not used by DMA */ + u64 data2; /* This holds virtual address of buffer2, not used by DMA */ } DmaDesc; #else typedef struct DmaDescStruct { - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ - /* This data below is used only by driver */ - u64 data1; /* This holds virtual address of buffer1, not used by DMA */ - u64 data2; /* This holds virtual address of buffer2, not used by DMA */ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ + u64 data1; /* This holds virtual address of buffer1, not used by DMA */ + u64 data2; /* This holds virtual address of buffer2, not used by DMA */ - //u32 dummy1; //sw: for addr align - //u32 dummy2; // + //u32 dummy1; //sw: for addr align + //u32 dummy2; // } DmaDesc; #endif @@ -130,137 +130,130 @@ typedef struct DmaDescStruct enum DescMode { RINGMODE = 0x00000001, - CHAINMODE = 0x00000002, + CHAINMODE = 0x00000002, }; enum BufferMode { - SINGLEBUF = 0x00000001, - DUALBUF = 0x00000002, + SINGLEBUF = 0x00000001, + DUALBUF = 0x00000002, }; /* synopGMAC device data */ typedef struct synopGMACDeviceStruct { - u64 MacBase; /* base address of MAC registers */ - u64 DmaBase; /* base address of DMA registers */ - u64 PhyBase; /* PHY device address on MII interface */ - u32 Version; /* Gmac Revision version */ + u64 MacBase; /* base address of MAC registers */ + u64 DmaBase; /* base address of DMA registers */ + u64 PhyBase; /* PHY device address on MII interface */ + u32 Version; /* Gmac Revision version */ + dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ + dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ + DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ + DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ - dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ - dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ - DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ - DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ - - u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ - u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ - - u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ - u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ + u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ + u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ - u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ - u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ - u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ - u32 RxNext; /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */ - - DmaDesc * TxBusyDesc; /* Tx Descriptor address corresponding to the index TxBusy */ - DmaDesc * TxNextDesc; /* Tx Descriptor address corresponding to the index TxNext */ - DmaDesc * RxBusyDesc; /* Rx Descriptor address corresponding to the index TxBusy */ - DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ - - /*Phy related stuff*/ - u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ - /* The status of the link */ - u32 LinkState0; /* Link status as reported by the Marvel Phy */ - u32 LinkState; /* Link status as reported by the Marvel Phy */ - u32 DuplexMode; /* Duplex mode of the Phy */ - u32 Speed; /* Speed of the Phy */ - u32 LoopBackMode; /* Loopback status of the Phy */ + u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ + u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ + u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ + u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ + u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ + u32 RxNext; /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */ + + DmaDesc * TxBusyDesc; /* Tx Descriptor address corresponding to the index TxBusy */ + DmaDesc * TxNextDesc; /* Tx Descriptor address corresponding to the index TxNext */ + DmaDesc * RxBusyDesc; /* Rx Descriptor address corresponding to the index TxBusy */ + DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ + + /*Phy related stuff*/ + u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ + /* The status of the link */ + u32 LinkState0; /* Link status as reported by the Marvel Phy */ + u32 LinkState; /* Link status as reported by the Marvel Phy */ + u32 DuplexMode; /* Duplex mode of the Phy */ + u32 Speed; /* Speed of the Phy */ + u32 LoopBackMode; /* Loopback status of the Phy */ // void * FirstTxDesc; // void * FirstRxDesc; // u32 skb_array[RECEIVE_DESC_SIZE]; } synopGMACdevice; - - /* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter. * Since the Phy register map is standard, this map hardly changes to a different Ppy */ - enum MiiRegisters { - PHY_CONTROL_REG = 0x0000, /*Control Register*/ - PHY_STATUS_REG = 0x0001, /*Status Register */ - PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ - PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ - PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ - PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ - PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ - PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ - PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ - PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ - PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ - PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ - PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ - PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ - PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ - PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ - PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ - PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ - PHY_LED_CONTROL = 0x0018, /*LED Control*/ - PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ - PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ - PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ - PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ + PHY_CONTROL_REG = 0x0000, /*Control Register*/ + PHY_STATUS_REG = 0x0001, /*Status Register */ + PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ + PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ + PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ + PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ + PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ + PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ + PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ + PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ + PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ + PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ + PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ + PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ + PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ + PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ + PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ + PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ + PHY_LED_CONTROL = 0x0018, /*LED Control*/ + PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ + PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ + PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ + PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ }; - /* This is Control register layout. Control register is of 16 bit wide. */ - enum Mii_GEN_CTRL -{ /* Description bits R/W default value */ - Mii_reset = 0x8000, - Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ - Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ - Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ +{ /* Description bits R/W default value */ + Mii_reset = 0x8000, + Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ + Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ + Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ - Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ + Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ - Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ + Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ - Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ - Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ + Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ + Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ }; enum Mii_Phy_Status { Mii_phy_status_speed_10 = 0x0000, - Mii_phy_status_speed_100 = 0x4000, - Mii_phy_status_speed_1000 = 0x8000, + Mii_phy_status_speed_100 = 0x4000, + Mii_phy_status_speed_1000 = 0x8000, - Mii_phy_status_full_duplex = 0x2000, - Mii_phy_status_half_duplex = 0x0000, + Mii_phy_status_full_duplex = 0x2000, + Mii_phy_status_half_duplex = 0x0000, - Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy + Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy // Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY }; /* This is Status register layout. Status register is of 16 bit wide. */ enum Mii_GEN_STATUS { - Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ - Mii_Link = 0x0004, /* Link status 2 RW */ + Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ + Mii_Link = 0x0004, /* Link status 2 RW */ }; enum Mii_Link_Status { - LINKDOWN = 0, - LINKUP = 1, + LINKDOWN = 0, + LINKUP = 1, }; enum Mii_Duplex_Mode @@ -281,8 +274,6 @@ enum Mii_Loop_Back LOOPBACK = 1, }; - - /********************************************************** * GMAC registers Map * For Pci based system address is BARx + GmacRegisterBase @@ -290,76 +281,76 @@ enum Mii_Loop_Back **********************************************************/ enum GmacRegisters { - GmacConfig = 0x0000, /* Mac config Register */ - GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ - GmacHashHigh = 0x0008, /* Multi-cast hash table high */ - GmacHashLow = 0x000C, /* Multi-cast hash table low */ - GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ - GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ - GmacFlowControl = 0x0018, /* Flow control Register */ - GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ + GmacConfig = 0x0000, /* Mac config Register */ + GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ + GmacHashHigh = 0x0008, /* Multi-cast hash table high */ + GmacHashLow = 0x000C, /* Multi-cast hash table low */ + GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ + GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ + GmacFlowControl = 0x0018, /* Flow control Register */ + GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ - GmacVersion = 0x0020, /* GMAC Core Version Register */ - GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ - GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ + GmacVersion = 0x0020, /* GMAC Core Version Register */ + GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ + GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ - GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ - GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ + GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ + GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ - GmacAddr0High = 0x0040, /* Mac address0 high Register */ - GmacAddr0Low = 0x0044, /* Mac address0 low Register */ - GmacAddr1High = 0x0048, /* Mac address1 high Register */ - GmacAddr1Low = 0x004C, /* Mac address1 low Register */ - GmacAddr2High = 0x0050, /* Mac address2 high Register */ - GmacAddr2Low = 0x0054, /* Mac address2 low Register */ - GmacAddr3High = 0x0058, /* Mac address3 high Register */ - GmacAddr3Low = 0x005C, /* Mac address3 low Register */ - GmacAddr4High = 0x0060, /* Mac address4 high Register */ - GmacAddr4Low = 0x0064, /* Mac address4 low Register */ - GmacAddr5High = 0x0068, /* Mac address5 high Register */ - GmacAddr5Low = 0x006C, /* Mac address5 low Register */ - GmacAddr6High = 0x0070, /* Mac address6 high Register */ - GmacAddr6Low = 0x0074, /* Mac address6 low Register */ - GmacAddr7High = 0x0078, /* Mac address7 high Register */ - GmacAddr7Low = 0x007C, /* Mac address7 low Register */ - GmacAddr8High = 0x0080, /* Mac address8 high Register */ - GmacAddr8Low = 0x0084, /* Mac address8 low Register */ - GmacAddr9High = 0x0088, /* Mac address9 high Register */ - GmacAddr9Low = 0x008C, /* Mac address9 low Register */ - GmacAddr10High = 0x0090, /* Mac address10 high Register */ - GmacAddr10Low = 0x0094, /* Mac address10 low Register */ - GmacAddr11High = 0x0098, /* Mac address11 high Register */ - GmacAddr11Low = 0x009C, /* Mac address11 low Register */ - GmacAddr12High = 0x00A0, /* Mac address12 high Register */ - GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ - GmacAddr13High = 0x00A8, /* Mac address13 high Register */ - GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ - GmacAddr14High = 0x00B0, /* Mac address14 high Register */ - GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ - GmacAddr15High = 0x00B8, /* Mac address15 high Register */ - GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ - GmacStatus = 0x00d8, /*MAC status*/ + GmacAddr0High = 0x0040, /* Mac address0 high Register */ + GmacAddr0Low = 0x0044, /* Mac address0 low Register */ + GmacAddr1High = 0x0048, /* Mac address1 high Register */ + GmacAddr1Low = 0x004C, /* Mac address1 low Register */ + GmacAddr2High = 0x0050, /* Mac address2 high Register */ + GmacAddr2Low = 0x0054, /* Mac address2 low Register */ + GmacAddr3High = 0x0058, /* Mac address3 high Register */ + GmacAddr3Low = 0x005C, /* Mac address3 low Register */ + GmacAddr4High = 0x0060, /* Mac address4 high Register */ + GmacAddr4Low = 0x0064, /* Mac address4 low Register */ + GmacAddr5High = 0x0068, /* Mac address5 high Register */ + GmacAddr5Low = 0x006C, /* Mac address5 low Register */ + GmacAddr6High = 0x0070, /* Mac address6 high Register */ + GmacAddr6Low = 0x0074, /* Mac address6 low Register */ + GmacAddr7High = 0x0078, /* Mac address7 high Register */ + GmacAddr7Low = 0x007C, /* Mac address7 low Register */ + GmacAddr8High = 0x0080, /* Mac address8 high Register */ + GmacAddr8Low = 0x0084, /* Mac address8 low Register */ + GmacAddr9High = 0x0088, /* Mac address9 high Register */ + GmacAddr9Low = 0x008C, /* Mac address9 low Register */ + GmacAddr10High = 0x0090, /* Mac address10 high Register */ + GmacAddr10Low = 0x0094, /* Mac address10 low Register */ + GmacAddr11High = 0x0098, /* Mac address11 high Register */ + GmacAddr11Low = 0x009C, /* Mac address11 low Register */ + GmacAddr12High = 0x00A0, /* Mac address12 high Register */ + GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ + GmacAddr13High = 0x00A8, /* Mac address13 high Register */ + GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ + GmacAddr14High = 0x00B0, /* Mac address14 high Register */ + GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ + GmacAddr15High = 0x00B8, /* Mac address15 high Register */ + GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ + GmacStatus = 0x00d8, /* MAC status */ /*Time Stamp Register Map*/ - GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ + GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ - GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ - //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ + GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ +//GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ - GmacTSStatus = 0x0728, /* Time Stamp Status Register */ + GmacTSStatus = 0x0728, /* Time Stamp Status Register */ }; /********************************************************** @@ -376,214 +367,211 @@ enum GmacRegisters /* GmacConfig = 0x0000, Mac config Register Layout */ enum GmacConfigReg { - /* Bit description Bits R/W Reset value */ - GmacWatchdog = 0x00800000, - GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ - GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ - - GmacJabber = 0x00400000, - GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ - GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ - - GmacFrameBurst = 0x00200000, - GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ - GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ + /* Bit description Bits R/W Reset value */ + GmacWatchdog = 0x00800000, + GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ + GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ + + GmacJabber = 0x00400000, + GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ + GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ + + GmacFrameBurst = 0x00200000, + GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ + GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ - GmacJumboFrame = 0x00100000, - GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ - GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ - - GmacInterFrameGap7 = 0x000E0000, /* (IFG) Config7 - 40 bit times 19:17 RW */ - GmacInterFrameGap6 = 0x000C0000, /* (IFG) Config6 - 48 bit times */ - GmacInterFrameGap5 = 0x000A0000, /* (IFG) Config5 - 56 bit times */ - GmacInterFrameGap4 = 0x00080000, /* (IFG) Config4 - 64 bit times */ - GmacInterFrameGap3 = 0x00040000, /* (IFG) Config3 - 72 bit times */ - GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ - GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ - GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ + GmacJumboFrame = 0x00100000, + GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ + GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ + + GmacInterFrameGap7 = 0x000E0000, /* (IFG) Config7 - 40 bit times 19:17 RW */ + GmacInterFrameGap6 = 0x000C0000, /* (IFG) Config6 - 48 bit times */ + GmacInterFrameGap5 = 0x000A0000, /* (IFG) Config5 - 56 bit times */ + GmacInterFrameGap4 = 0x00080000, /* (IFG) Config4 - 64 bit times */ + GmacInterFrameGap3 = 0x00040000, /* (IFG) Config3 - 72 bit times */ + GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ + GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ + GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ - GmacDisableCrs = 0x00010000, - GmacMiiGmii = 0x00008000, - GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ - GmacSelectGmii = 0x00000000, /* GMII mode 0 */ + GmacDisableCrs = 0x00010000, + GmacMiiGmii = 0x00008000, + GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ + GmacSelectGmii = 0x00000000, /* GMII mode 0 */ - GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ - GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ + GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ + GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ - GmacRxOwn = 0x00002000, - GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ - GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ + GmacRxOwn = 0x00002000, + GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ + GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ - GmacLoopback = 0x00001000, - GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ - GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ + GmacLoopback = 0x00001000, + GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ + GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ - GmacDuplex = 0x00000800, - GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ - GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ + GmacDuplex = 0x00000800, + GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ + GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ - GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ + GmacRxIpcOffload = 0x00000400, /* IPC checksum offload 10 RW 0 */ - GmacRetry = 0x00000200, - GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ - GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ + GmacRetry = 0x00000200, + GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ + GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ - GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ - GmacLinkDown = 0x00000100, /* Link Down 0 */ + GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ + GmacLinkDown = 0x00000100, /* Link Down 0 */ - GmacPadCrcStrip = 0x00000080, - GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ - GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ + GmacPadCrcStrip = 0x00000080, + GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ + GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ - GmacBackoffLimit = 0x00000060, - GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ - GmacBackoffLimit2 = 0x00000040, /* */ - GmacBackoffLimit1 = 0x00000020, /* */ - GmacBackoffLimit0 = 0x00000000, /* 00 */ - - GmacDeferralCheck = 0x00000010, - GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ - GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ + GmacBackoffLimit = 0x00000060, + GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ + GmacBackoffLimit2 = 0x00000040, /* */ + GmacBackoffLimit1 = 0x00000020, /* */ + GmacBackoffLimit0 = 0x00000000, /* 00 */ + + GmacDeferralCheck = 0x00000010, + GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ + GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ - GmacTx = 0x00000008, - GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ - GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ + GmacTx = 0x00000008, + GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ + GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ - GmacRx = 0x00000004, - GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ - GmacRxDisable = 0x00000000, /* Receiver disable 0 */ + GmacRx = 0x00000004, + GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ + GmacRxDisable = 0x00000000, /* Receiver disable 0 */ }; /* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/ enum GmacFrameFilterReg { - GmacFilter = 0x80000000, - GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ - GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ + GmacFilter = 0x80000000, + GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ + GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ - GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ + GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ - GmacSrcAddrFilter = 0x00000200, - GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ - GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ + GmacSrcAddrFilter = 0x00000200, + GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ + GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ - GmacSrcInvaAddrFilter = 0x00000100, - GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ - GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ + GmacSrcInvaAddrFilter = 0x00000100, + GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ + GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ - GmacPassControl = 0x000000C0, - GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ - GmacPassControl2 = 0x00000080, /* Forwards all control frames */ - GmacPassControl1 = 0x00000040, /* Does not pass control frames */ - GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ + GmacPassControl = 0x000000C0, + GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ + GmacPassControl2 = 0x00000080, /* Forwards all control frames */ + GmacPassControl1 = 0x00000040, /* Does not pass control frames */ + GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ - GmacBroadcast = 0x00000020, - GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ - GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ + GmacBroadcast = 0x00000020, + GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ + GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ - GmacMulticastFilter = 0x00000010, - GmacMulticastFilterOff = 0x00000010, /* (PM) Pass all multicast packets 4 RW */ - GmacMulticastFilterOn = 0x00000000, /* Pass filtered multicast packets 0 */ + GmacMulticastFilter = 0x00000010, + GmacMulticastFilterOff = 0x00000010, /* (PM) Pass all multicast packets 4 RW */ + GmacMulticastFilterOn = 0x00000000, /* Pass filtered multicast packets 0 */ - GmacDestAddrFilter = 0x00000008, - GmacDestAddrFilterInv = 0x00000008, /* (DAIF)Inverse filtering for DA 3 RW */ - GmacDestAddrFilterNor = 0x00000000, /* Normal filtering for DA 0 */ + GmacDestAddrFilter = 0x00000008, + GmacDestAddrFilterInv = 0x00000008, /* (DAIF)Inverse filtering for DA 3 RW */ + GmacDestAddrFilterNor = 0x00000000, /* Normal filtering for DA 0 */ - GmacMcastHashFilter = 0x00000004, - GmacMcastHashFilterOn = 0x00000004, /* (HMC)perfom multicast hash filtering 2 RW */ - GmacMcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ + GmacMcastHashFilter = 0x00000004, + GmacMcastHashFilterOn = 0x00000004, /* (HMC)perfom multicast hash filtering 2 RW */ + GmacMcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ - GmacUcastHashFilter = 0x00000002, - GmacUcastHashFilterOn = 0x00000002, /* (HUC)Unicast Hash filtering only 1 RW */ - GmacUcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ + GmacUcastHashFilter = 0x00000002, + GmacUcastHashFilterOn = 0x00000002, /* (HUC)Unicast Hash filtering only 1 RW */ + GmacUcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ - GmacPromiscuousMode = 0x00000001, - GmacPromiscuousModeOn = 0x00000001, /* Receive all frames 0 RW */ - GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ + GmacPromiscuousMode = 0x00000001, + GmacPromiscuousModeOn = 0x00000001, /* Receive all frames 0 RW */ + GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ }; - /*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */ enum GmacGmiiAddrReg { - GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ - GmiiDevShift = 11, + GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ + GmiiDevShift = 11, - GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ - GmiiRegShift = 6, + GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ + GmiiRegShift = 6, - GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ - GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ - GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ - GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ - GmiiCsrClk2 = 0x00000008, /* 20-35 MHz */ - GmiiCsrClk1 = 0x00000004, /* 100-150 MHz */ - GmiiCsrClk0 = 0x00000000, /* 60-100 MHz */ - - GmiiWrite = 0x00000002, /* (GW)Write to register 1 RW */ - GmiiRead = 0x00000000, /* Read from register 0 */ - - GmiiBusy = 0x00000001, /* (GB)GMII interface is busy 0 RW 0 */ + GmiiCsrClkMask = 0x0000001C, /* CSR Clock bit Mask 4:2 */ + GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ + GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ + GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ + GmiiCsrClk2 = 0x00000008, /* 20-35 MHz */ + GmiiCsrClk1 = 0x00000004, /* 100-150 MHz */ + GmiiCsrClk0 = 0x00000000, /* 60-100 MHz */ + + GmiiWrite = 0x00000002, /* (GW)Write to register 1 RW */ + GmiiRead = 0x00000000, /* Read from register 0 */ + + GmiiBusy = 0x00000001, /* (GB)GMII interface is busy 0 RW 0 */ }; /* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */ enum GmacGmiiDataReg { - GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ + GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ }; - /*GmacFlowControl = 0x0018, Flow control Register Layout */ enum GmacFlowControlReg { - GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ - GmacPauseTimeShift = 16, + GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ + GmacPauseTimeShift = 16, - GmacPauseLowThresh = 0x00000030, - GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ - GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ - GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ - GmacPauseLowThresh0 = 0x00000000, /* 4 slot time 000 */ - - GmacUnicastPauseFrame = 0x00000008, - GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ - GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ - - GmacRxFlowControl = 0x00000004, - GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ - GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ - - GmacTxFlowControl = 0x00000002, - GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ - GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ - - GmacFlowControlBackPressure= 0x00000001, - GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ + GmacPauseLowThresh = 0x00000030, + GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ + GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ + GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ + GmacPauseLowThresh0 = 0x00000000, /* 4 slot time 000 */ + + GmacUnicastPauseFrame = 0x00000008, + GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ + GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ + + GmacRxFlowControl = 0x00000004, + GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ + GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ + + GmacTxFlowControl = 0x00000002, + GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ + GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ + + GmacFlowControlBackPressure= 0x00000001, + GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ }; /* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ enum GmacInterruptStatusBitDefinition { - GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ - GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ - GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ - GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ - GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ - GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ - GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ - GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ - GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ - + GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ + GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ + GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ + GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ + GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ + GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ + GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ + GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ }; /* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ enum GmacInterruptMaskBitDefinition { - GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ - GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ - GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ - GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ - GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ + GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ + GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ + GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ + GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ + GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ }; /********************************************************** @@ -591,22 +579,21 @@ enum GmacInterruptMaskBitDefinition * For Pci based system address is BARx + GmaDmaBase * For any other system translation is done accordingly **********************************************************/ - enum DmaRegisters { - DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ - DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ - DmaRxPollDemand = 0x0008, /* CSR2 - Receive Poll Demand Register */ - DmaRxBaseAddr = 0x000C, /* CSR3 - Receive Descriptor list base address */ - DmaTxBaseAddr = 0x0010, /* CSR4 - Transmit Descriptor list base address */ - DmaStatus = 0x0014, /* CSR5 - Dma status Register */ - DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ - DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ - DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ - DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ - DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ - DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ - DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ + DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ + DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ + DmaRxPollDemand = 0x0008, /* CSR2 - Receive Poll Demand Register */ + DmaRxBaseAddr = 0x000C, /* CSR3 - Receive Descriptor list base address */ + DmaTxBaseAddr = 0x0010, /* CSR4 - Transmit Descriptor list base address */ + DmaStatus = 0x0014, /* CSR5 - Dma status Register */ + DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ + DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ + DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ + DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ + DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ + DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ + DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ }; /********************************************************** @@ -616,165 +603,164 @@ enum DmaRegisters /*DmaBusMode = 0x0000, CSR0 - Bus Mode */ enum DmaBusModeReg { /* Bit description Bits R/W Reset value */ - DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ - DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ + DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ + DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ - DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ - DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ - DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ - DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ + DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ + DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ + DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ + DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ - DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ + DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ - DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ - DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ - DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ - DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ - DmaBurstLength16 = 0x00001000, /* Dma burst length = 16 */ - DmaBurstLength8 = 0x00000800, /* Dma burst length = 8 */ - DmaBurstLength4 = 0x00000400, /* Dma burst length = 4 */ - DmaBurstLength2 = 0x00000200, /* Dma burst length = 2 */ - DmaBurstLength1 = 0x00000100, /* Dma burst length = 1 */ - DmaBurstLength0 = 0x00000000, /* Dma burst length = 0 0x00 */ - - DmaDescriptor8Words = 0x00000080, /* Enh Descriptor works 1=> 8 word descriptor 7 0 */ - DmaDescriptor4Words = 0x00000000, /* Enh Descriptor works 0=> 4 word descriptor 7 0 */ - - DmaDescriptorSkip16 = 0x00000040, /* (DSL)Descriptor skip length (no.of dwords) 6:2 RW */ - DmaDescriptorSkip8 = 0x00000020, /* between two unchained descriptors */ - DmaDescriptorSkip4 = 0x00000010, /* */ - DmaDescriptorSkip2 = 0x00000008, /* */ - DmaDescriptorSkip1 = 0x00000004, /* */ - DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ - - DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ - DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ + DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ + DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ + DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ + DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ + DmaBurstLength16 = 0x00001000, /* Dma burst length = 16 */ + DmaBurstLength8 = 0x00000800, /* Dma burst length = 8 */ + DmaBurstLength4 = 0x00000400, /* Dma burst length = 4 */ + DmaBurstLength2 = 0x00000200, /* Dma burst length = 2 */ + DmaBurstLength1 = 0x00000100, /* Dma burst length = 1 */ + DmaBurstLength0 = 0x00000000, /* Dma burst length = 0 0x00 */ + + DmaDescriptor8Words = 0x00000080, /* Enh Descriptor works 1=> 8 word descriptor 7 0 */ + DmaDescriptor4Words = 0x00000000, /* Enh Descriptor works 0=> 4 word descriptor 7 0 */ + + DmaDescriptorSkip16 = 0x00000040, /* (DSL)Descriptor skip length (no.of dwords) 6:2 RW */ + DmaDescriptorSkip8 = 0x00000020, /* between two unchained descriptors */ + DmaDescriptorSkip4 = 0x00000010, /* */ + DmaDescriptorSkip2 = 0x00000008, /* */ + DmaDescriptorSkip1 = 0x00000004, /* */ + DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ + + DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ + DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ - DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ - DmaResetOff = 0x00000000, /* 0 */ + DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ + DmaResetOff = 0x00000000, /* 0 */ }; - /*DmaStatus = 0x0014, CSR5 - Dma status Register */ enum DmaStatusReg { /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ - GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ - GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ - GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ - - DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ - DmaErrorBit1 = 0x01000000, /* (EB)Error bits 0-write trnsf, 1-read transfr 24 RO 0 */ - DmaErrorBit0 = 0x00800000, /* (EB)Error bits 0-Rx DMA, 1-Tx DMA 23 RO 0 */ - - DmaTxState = 0x00700000, /* (TS)Transmit process state 22:20 RO */ - DmaTxStopped = 0x00000000, /* Stopped - Reset or Stop Tx Command issued 000 */ - DmaTxFetching = 0x00100000, /* Running - fetching the Tx descriptor */ - DmaTxWaiting = 0x00200000, /* Running - waiting for status */ - DmaTxReading = 0x00300000, /* Running - reading the data from host memory */ - DmaTxSuspended = 0x00600000, /* Suspended - Tx Descriptor unavailabe */ - DmaTxClosing = 0x00700000, /* Running - closing Rx descriptor */ - - DmaRxState = 0x000E0000, /* (RS)Receive process state 19:17 RO */ - DmaRxStopped = 0x00000000, /* Stopped - Reset or Stop Rx Command issued 000 */ - DmaRxFetching = 0x00020000, /* Running - fetching the Rx descriptor */ - DmaRxWaiting = 0x00060000, /* Running - waiting for packet */ - DmaRxSuspended = 0x00080000, /* Suspended - Rx Descriptor unavailable */ - DmaRxClosing = 0x000A0000, /* Running - closing descriptor */ - DmaRxQueuing = 0x000E0000, /* Running - queuing the recieve frame into host memory */ - - DmaIntNormal = 0x00010000, /* (NIS)Normal interrupt summary 16 RW 0 */ - DmaIntAbnormal = 0x00008000, /* (AIS)Abnormal interrupt summary 15 RW 0 */ - - DmaIntEarlyRx = 0x00004000, /* Early receive interrupt (Normal) RW 0 */ - DmaIntBusError = 0x00002000, /* Fatal bus error (Abnormal) RW 0 */ - DmaIntEarlyTx = 0x00000400, /* Early transmit interrupt (Abnormal) RW 0 */ - DmaIntRxWdogTO = 0x00000200, /* Receive Watchdog Timeout (Abnormal) RW 0 */ - DmaIntRxStopped = 0x00000100, /* Receive process stopped (Abnormal) RW 0 */ - DmaIntRxNoBuffer = 0x00000080, /* Receive buffer unavailable (Abnormal) RW 0 */ - DmaIntRxCompleted = 0x00000040, /* Completion of frame reception (Normal) RW 0 */ - DmaIntTxUnderflow = 0x00000020, /* Transmit underflow (Abnormal) RW 0 */ - DmaIntRcvOverflow = 0x00000010, /* Receive Buffer overflow interrupt RW 0 */ - DmaIntTxJabberTO = 0x00000008, /* Transmit Jabber Timeout (Abnormal) RW 0 */ - DmaIntTxNoBuffer = 0x00000004, /* Transmit buffer unavailable (Normal) RW 0 */ - DmaIntTxStopped = 0x00000002, /* Transmit process stopped (Abnormal) RW 0 */ - DmaIntTxCompleted = 0x00000001, /* Transmit completed (Normal) RW 0 */ + GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ + GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ + GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ + + DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ + DmaErrorBit1 = 0x01000000, /* (EB)Error bits 0-write trnsf, 1-read transfr 24 RO 0 */ + DmaErrorBit0 = 0x00800000, /* (EB)Error bits 0-Rx DMA, 1-Tx DMA 23 RO 0 */ + + DmaTxState = 0x00700000, /* (TS)Transmit process state 22:20 RO */ + DmaTxStopped = 0x00000000, /* Stopped - Reset or Stop Tx Command issued 000 */ + DmaTxFetching = 0x00100000, /* Running - fetching the Tx descriptor */ + DmaTxWaiting = 0x00200000, /* Running - waiting for status */ + DmaTxReading = 0x00300000, /* Running - reading the data from host memory */ + DmaTxSuspended = 0x00600000, /* Suspended - Tx Descriptor unavailabe */ + DmaTxClosing = 0x00700000, /* Running - closing Rx descriptor */ + + DmaRxState = 0x000E0000, /* (RS)Receive process state 19:17 RO */ + DmaRxStopped = 0x00000000, /* Stopped - Reset or Stop Rx Command issued 000 */ + DmaRxFetching = 0x00020000, /* Running - fetching the Rx descriptor */ + DmaRxWaiting = 0x00060000, /* Running - waiting for packet */ + DmaRxSuspended = 0x00080000, /* Suspended - Rx Descriptor unavailable */ + DmaRxClosing = 0x000A0000, /* Running - closing descriptor */ + DmaRxQueuing = 0x000E0000, /* Running - queuing the recieve frame into host memory */ + + DmaIntNormal = 0x00010000, /* (NIS)Normal interrupt summary 16 RW 0 */ + DmaIntAbnormal = 0x00008000, /* (AIS)Abnormal interrupt summary 15 RW 0 */ + + DmaIntEarlyRx = 0x00004000, /* Early receive interrupt (Normal) RW 0 */ + DmaIntBusError = 0x00002000, /* Fatal bus error (Abnormal) RW 0 */ + DmaIntEarlyTx = 0x00000400, /* Early transmit interrupt (Abnormal) RW 0 */ + DmaIntRxWdogTO = 0x00000200, /* Receive Watchdog Timeout (Abnormal) RW 0 */ + DmaIntRxStopped = 0x00000100, /* Receive process stopped (Abnormal) RW 0 */ + DmaIntRxNoBuffer = 0x00000080, /* Receive buffer unavailable (Abnormal) RW 0 */ + DmaIntRxCompleted = 0x00000040, /* Completion of frame reception (Normal) RW 0 */ + DmaIntTxUnderflow = 0x00000020, /* Transmit underflow (Abnormal) RW 0 */ + DmaIntRcvOverflow = 0x00000010, /* Receive Buffer overflow interrupt RW 0 */ + DmaIntTxJabberTO = 0x00000008, /* Transmit Jabber Timeout (Abnormal) RW 0 */ + DmaIntTxNoBuffer = 0x00000004, /* Transmit buffer unavailable (Normal) RW 0 */ + DmaIntTxStopped = 0x00000002, /* Transmit process stopped (Abnormal) RW 0 */ + DmaIntTxCompleted = 0x00000001, /* Transmit completed (Normal) RW 0 */ }; /*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */ enum DmaControlReg { - DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ + DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ - DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */ - DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ + DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */ + DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ - DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ - DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ - DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ - DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ - DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ - DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ - DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ - DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ - DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ + DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ + DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ + DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ + DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ + DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ + DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ + DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ + DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ + DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ - DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ - - DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ - DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ - DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ + + DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ + DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ + DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ - DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ - DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct4K = 0x00000600, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ + DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ + DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct4K = 0x00000600, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ - DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ - DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ - DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ - DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ - DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ - - DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ - DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ + DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ + DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ + DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ + DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ + DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + + DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ + DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ - DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ - DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ - DmaRxStart = 0x00000002, /* (SR)Start/Stop reception 1 RW 0 */ + DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ + DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ + DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ + DmaRxStart = 0x00000002, /* (SR)Start/Stop reception 1 RW 0 */ }; /*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */ enum DmaInterruptReg { - DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ - DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ - - DmaIeEarlyRx = DmaIntEarlyRx , /* Early receive interrupt enable RW 0 */ - DmaIeBusError = DmaIntBusError , /* Fatal bus error enable RW 0 */ - DmaIeEarlyTx = DmaIntEarlyTx , /* Early transmit interrupt enable RW 0 */ - DmaIeRxWdogTO = DmaIntRxWdogTO , /* Receive Watchdog Timeout enable RW 0 */ - DmaIeRxStopped = DmaIntRxStopped , /* Receive process stopped enable RW 0 */ - DmaIeRxNoBuffer = DmaIntRxNoBuffer , /* Receive buffer unavailable enable RW 0 */ - DmaIeRxCompleted = DmaIntRxCompleted, /* Completion of frame reception enable RW 0 */ - DmaIeTxUnderflow = DmaIntTxUnderflow, /* Transmit underflow enable RW 0 */ - - DmaIeRxOverflow = DmaIntRcvOverflow, /* Receive Buffer overflow interrupt RW 0 */ - DmaIeTxJabberTO = DmaIntTxJabberTO , /* Transmit Jabber Timeout enable RW 0 */ - DmaIeTxNoBuffer = DmaIntTxNoBuffer , /* Transmit buffer unavailable enable RW 0 */ - DmaIeTxStopped = DmaIntTxStopped , /* Transmit process stopped enable RW 0 */ - DmaIeTxCompleted = DmaIntTxCompleted, /* Transmit completed enable RW 0 */ + DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ + DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ + + DmaIeEarlyRx = DmaIntEarlyRx , /* Early receive interrupt enable RW 0 */ + DmaIeBusError = DmaIntBusError , /* Fatal bus error enable RW 0 */ + DmaIeEarlyTx = DmaIntEarlyTx , /* Early transmit interrupt enable RW 0 */ + DmaIeRxWdogTO = DmaIntRxWdogTO , /* Receive Watchdog Timeout enable RW 0 */ + DmaIeRxStopped = DmaIntRxStopped , /* Receive process stopped enable RW 0 */ + DmaIeRxNoBuffer = DmaIntRxNoBuffer , /* Receive buffer unavailable enable RW 0 */ + DmaIeRxCompleted = DmaIntRxCompleted, /* Completion of frame reception enable RW 0 */ + DmaIeTxUnderflow = DmaIntTxUnderflow, /* Transmit underflow enable RW 0 */ + + DmaIeRxOverflow = DmaIntRcvOverflow, /* Receive Buffer overflow interrupt RW 0 */ + DmaIeTxJabberTO = DmaIntTxJabberTO , /* Transmit Jabber Timeout enable RW 0 */ + DmaIeTxNoBuffer = DmaIntTxNoBuffer , /* Transmit buffer unavailable enable RW 0 */ + DmaIeTxStopped = DmaIntTxStopped , /* Transmit process stopped enable RW 0 */ + DmaIeTxCompleted = DmaIntTxCompleted, /* Transmit completed enable RW 0 */ }; @@ -818,126 +804,119 @@ DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format enum DmaDescriptorStatus /* status word of DMA descriptor */ { - DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ + DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ - DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ + DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ - DescFrameLengthShift = 16, + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ + DescFrameLengthShift = 16, - DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ + DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ /* DE || OE || IPC || LC || RWT || RE || CE */ - DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ - DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ - DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ - DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ - DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ - DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ - DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ - DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ - DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ - DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ - DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ - DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ + DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ + DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ + DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ + DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ + DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ + DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ + DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ + DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ + DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ + DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ + DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ // DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ - DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ + DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ - DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ - DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ - DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ - DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ - - DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ - - TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ - TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ + DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ + DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ + DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ + DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ + DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ + + DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + + TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ + TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - DescRxTSavail = 0x00000080, /* Time stamp available 7 */ - DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - - DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ - DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ - DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ - DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ - DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ - DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ - DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ - DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ - DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ + DescRxTSavail = 0x00000080, /* Time stamp available 7 */ + DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ + DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ + DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ + DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ + DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ + DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ + DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ + DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ + DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ - DescTxCollShift = 3, + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ + DescTxCollShift = 3, - DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ - DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ - DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ + DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ + DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ /* This explains the RDES1/TDES1 bits layout -------------------------------------------------------------------- RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | -------------------------------------------------------------------- - */ // DmaDescriptorLength length word of DMA descriptor - - - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ - RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ - RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ - - - DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */ - DescSize2Shift = 16, - DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */ - DescSize1Shift = 0, - - + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ + RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ + + DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */ + DescSize2Shift = 16, + DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */ + DescSize1Shift = 0, /* This explains the RDES4 Extended Status bits layout -------------------------------------------------------------------- RDES4 | Extended Status | -------------------------------------------------------------------- */ - DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ - DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ - DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ - DescRxPtpMessageType = 0x00000F00, /* Message Type 11:8 */ - DescRxPtpNo = 0x00000000, /* 0000 => No PTP message received */ - DescRxPtpSync = 0x00000100, /* 0001 => Sync (all clock types) received */ - DescRxPtpFollowUp = 0x00000200, /* 0010 => Follow_Up (all clock types) received */ - DescRxPtpDelayReq = 0x00000300, /* 0011 => Delay_Req (all clock types) received */ - DescRxPtpDelayResp = 0x00000400, /* 0100 => Delay_Resp (all clock types) received */ - DescRxPtpPdelayReq = 0x00000500, /* 0101 => Pdelay_Req (in P to P tras clk) or Announce in Ord and Bound clk */ - DescRxPtpPdelayResp = 0x00000600, /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk */ - DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ - DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ - DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ + DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ + DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ + DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ + DescRxPtpMessageType = 0x00000F00, /* Message Type 11:8 */ + DescRxPtpNo = 0x00000000, /* 0000 => No PTP message received */ + DescRxPtpSync = 0x00000100, /* 0001 => Sync (all clock types) received */ + DescRxPtpFollowUp = 0x00000200, /* 0010 => Follow_Up (all clock types) received */ + DescRxPtpDelayReq = 0x00000300, /* 0011 => Delay_Req (all clock types) received */ + DescRxPtpDelayResp = 0x00000400, /* 0100 => Delay_Resp (all clock types) received */ + DescRxPtpPdelayReq = 0x00000500, /* 0101 => Pdelay_Req (in P to P tras clk) or Announce in Ord and Bound clk */ + DescRxPtpPdelayResp = 0x00000600, /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk */ + DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ + DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ + DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ - DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 + DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 is bypassed */ - DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ - DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 + DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ + DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 error or IP datagram version is not consistent with Ethernet type value */ - DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 + DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 in IPdatagram processed by COE (Rx) */ - DescRxIpPayloadUnknown= 0x00000000, /* Unknown or didnot process IP payload */ - DescRxIpPayloadUDP = 0x00000001, /* UDP */ - DescRxIpPayloadTCP = 0x00000002, /* TCP */ - DescRxIpPayloadICMP = 0x00000003, /* ICMP */ + DescRxIpPayloadUnknown= 0x00000000, /* Unknown or didnot process IP payload */ + DescRxIpPayloadUDP = 0x00000001, /* UDP */ + DescRxIpPayloadTCP = 0x00000002, /* TCP */ + DescRxIpPayloadICMP = 0x00000003, /* ICMP */ }; @@ -965,55 +944,55 @@ DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format */ enum DmaDescriptorStatus /* status word of DMA descriptor */ { - DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ + DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ - DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ + DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ - DescFrameLengthShift = 16, + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ + DescFrameLengthShift = 16, - DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ + DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ /* DE || OE || IPC || LC || RWT || RE || CE */ - DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ - DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ - DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ - DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ - DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ - DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ - DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ - DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ - DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ - DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ - DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ - DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ - DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ - - //Rx Descriptor Checksum Offload engine (type 2) encoding - //DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ - //DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ + DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ + DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ + DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ + DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ + DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ + DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ + DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ + DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ + DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ + DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ + DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + +//Rx Descriptor Checksum Offload engine (type 2) encoding +//DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ +//DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ - DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ - DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ - DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ - DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ - DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ - DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ - DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ - DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ + DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ + DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ + DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ + DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ + DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ + DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ + DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ + DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ - DescTxCollShift = 3, + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ + DescTxCollShift = 3, - DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ - DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ - DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ + DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ + DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ /* This explains the RDES1/TDES1 bits layout @@ -1023,46 +1002,44 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ */ //DmaDescriptorLength length word of DMA descriptor - - DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */ - DescTxLast = 0x40000000, /* (LS)Tx - Last segment of the frame 30 */ - DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */ - DescTxDisableCrc = 0x04000000, /* (DC)Tx - Add CRC disabled (first segment only) 26 */ - - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ - RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ - RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ + DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */ + DescTxLast = 0x40000000, /* (LS)Tx - Last segment of the frame 30 */ + DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */ + DescTxDisableCrc = 0x04000000, /* (DC)Tx - Add CRC disabled (first segment only) 26 */ + + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ + RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ + DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ - TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ - TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ + TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ + TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */ - DescSize2Shift = 11, - DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */ - DescSize1Shift = 0, - - - DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */ + DescSize2Shift = 11, + DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */ + DescSize1Shift = 0, + + DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ }; #endif // Rx Descriptor COE type2 encoding enum RxDescCOEEncode { - RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ - RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ - RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ - RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ - RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ - RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ - RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ - RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ + RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ + RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ + RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ + RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ + RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ + RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ + RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ + RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ }; /********************************************************** @@ -1071,13 +1048,13 @@ enum RxDescCOEEncode enum synopGMACDmaIntEnum /* Intrerrupt types */ { - synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ - synopGMACDmaRxAbnormal = 0x02, /* abnormal receiver interrupt */ - synopGMACDmaRxStopped = 0x04, /* receiver stopped */ - synopGMACDmaTxNormal = 0x08, /* normal transmitter interrupt */ - synopGMACDmaTxAbnormal = 0x10, /* abnormal transmitter interrupt */ - synopGMACDmaTxStopped = 0x20, /* transmitter stopped */ - synopGMACDmaError = 0x80, /* Dma engine error */ + synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ + synopGMACDmaRxAbnormal = 0x02, /* abnormal receiver interrupt */ + synopGMACDmaRxStopped = 0x04, /* receiver stopped */ + synopGMACDmaTxNormal = 0x08, /* normal transmitter interrupt */ + synopGMACDmaTxAbnormal = 0x10, /* abnormal transmitter interrupt */ + synopGMACDmaTxStopped = 0x20, /* transmitter stopped */ + synopGMACDmaError = 0x80, /* Dma engine error */ }; @@ -1087,45 +1064,45 @@ enum RxDescCOEEncode enum InitialRegisters { /* Full-duplex mode with perfect filter on */ - GmacConfigInitFdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable - | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff - | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable - | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + GmacConfigInitFdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff + | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode with perfect filter on */ - GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable - | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff - | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable - | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff + | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode */ // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast // Hash filter. /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */ - GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable - | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff - | GmacPromiscuousModeOff | GmacUcastHashFilterOff, + GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable + | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff + | GmacPromiscuousModeOff | GmacUcastHashFilterOff, /* Full-duplex mode */ - GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, + GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, /* Full-duplex mode */ - GmacGmiiAddrInitFdx = GmiiCsrClk2, + GmacGmiiAddrInitFdx = GmiiCsrClk2, /* Half-duplex mode with perfect filter on */ // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/ - GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable - | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable - | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode with perfect filter on */ - GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable - | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable - | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode */ GmacFrameFilterInitHdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable @@ -1138,39 +1115,37 @@ enum InitialRegisters /* Half-duplex mode */ GmacGmiiAddrInitHdx = GmiiCsrClk2, - - /********************************************** *DMA configurations **********************************************/ - DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip1 | DmaResetOff, + DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip1 | DmaResetOff, // DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff, /* 1000 Mb/s mode */ - DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , + DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , /* 100 Mb/s mode */ - DmaControlInit100 = DmaStoreAndForward, + DmaControlInit100 = DmaStoreAndForward, /* 10 Mb/s mode */ - DmaControlInit10 = DmaStoreAndForward, + DmaControlInit10 = DmaStoreAndForward, /* Interrupt groups */ - DmaIntErrorMask = DmaIntBusError, /* Error */ - DmaIntRxAbnMask = DmaIntRxNoBuffer, /* receiver abnormal interrupt */ - DmaIntRxNormMask = DmaIntRxCompleted, /* receiver normal interrupt */ - DmaIntRxStoppedMask = DmaIntRxStopped, /* receiver stopped */ - DmaIntTxAbnMask = DmaIntTxUnderflow, /* transmitter abnormal interrupt */ - DmaIntTxNormMask = DmaIntTxCompleted, /* transmitter normal interrupt */ - DmaIntTxStoppedMask = DmaIntTxStopped, /* transmitter stopped */ - - DmaIntEnable = DmaIeNormal | DmaIeAbnormal | DmaIntErrorMask -//DmaIntEnable = DmaIeNormal | DmaIntErrorMask - | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask -// | DmaIntRxNormMask | DmaIntRxStoppedMask - | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask, - DmaIntDisable = 0, + DmaIntErrorMask = DmaIntBusError, /* Error */ + DmaIntRxAbnMask = DmaIntRxNoBuffer, /* receiver abnormal interrupt */ + DmaIntRxNormMask = DmaIntRxCompleted, /* receiver normal interrupt */ + DmaIntRxStoppedMask = DmaIntRxStopped, /* receiver stopped */ + DmaIntTxAbnMask = DmaIntTxUnderflow, /* transmitter abnormal interrupt */ + DmaIntTxNormMask = DmaIntTxCompleted, /* transmitter normal interrupt */ + DmaIntTxStoppedMask = DmaIntTxStopped, /* transmitter stopped */ + + DmaIntEnable = DmaIeNormal | DmaIeAbnormal | DmaIntErrorMask +//DmaIntEnable = DmaIeNormal | DmaIntErrorMask + | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask +// | DmaIntRxNormMask | DmaIntRxStoppedMask + | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask, + DmaIntDisable = 0, }; @@ -1180,186 +1155,185 @@ enum InitialRegisters enum MMC_ENABLE { - GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ - GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ - GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ - GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ - GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ + GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ + GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ + GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ + GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ + GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ }; enum MMC_TX { - GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ - GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ - GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ + GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ + GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ + GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ - GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ + GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ - GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ - GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ - GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ - GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ - GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ - GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ - GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ - GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ + GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ + GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ + GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ + GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ + GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ + GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ + GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ + GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ - GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ - GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ + GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ + GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ }; enum MMC_RX { - GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ - GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ - GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ - GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ + GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ + GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ + GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ + GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ - GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ + GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ - GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ - GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ + GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ + GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ - GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ + GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ - GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ - GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ + GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ + GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ + GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ - GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ - GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ - GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ + GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ + GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ + GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ - GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ + GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ }; + enum MMC_IP_RELATED { - GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ - GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ + GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ + GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ - GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ - GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ - GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ + GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ + GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ - GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ + GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ - GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ - GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ - GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ + GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ + GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ + GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ - GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ + GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ - GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ + GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ - GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ + GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ - GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ - GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ + GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ - GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ + GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ - GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ - GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ + GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ - GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ + GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ - GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ + GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ - GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ + GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ }; enum MMC_CNTRL_REG_BIT_DESCRIPTIONS { - GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ - GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ + GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ + GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ - GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ - + GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ }; enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ - GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ - GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ + GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ + GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ + GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ - GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ - GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ - GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ - GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ - GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ - GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ - GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ - GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ - GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ - GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ - GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ + GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ + GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ + GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ + GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ + GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ + GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ + GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ + GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ + GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ + GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ + GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ - GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ - GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ - GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ - GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ - GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ - GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ + GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ + GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ + GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ + GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ + GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ + GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ }; enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ + GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ - GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ - GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ - GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ - GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ - GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ - GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ - GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ - GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ - GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ + GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ + GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ + GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ + GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ + GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ + GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ + GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ + GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ + GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ - GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ - GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ - GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ - GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ - GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ - GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ - GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ - GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ - GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ - GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ - GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ - GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ - + GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ + GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ + GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ + GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ + GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ + GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ + GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ + GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ + GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ + GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ + GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ + GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ }; @@ -1385,45 +1359,40 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS enum GmacPmtCtrlStatusBitDefinition { - GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ - GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ + GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ + GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ - GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ - GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ - GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ - GmacPmtPowerDown = 0x00000001, /* Power Down */ + GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ + GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ + GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ + GmacPmtPowerDown = 0x00000001, /* Power Down */ }; - - - /********************************************************** * IEEE 1588-2008 Precision Time Protocol (PTP) Support **********************************************************/ enum PTPMessageType { - SYNC = 0x0, - Delay_Req = 0x1, - Pdelay_Req = 0x2, - Pdelay_Resp = 0x3, - Follow_up = 0x8, - Delay_Resp = 0x9, - Pdelay_Resp_Follow_Up = 0xA, - Announce = 0xB, - Signaling = 0xC, - Management = 0xD, + SYNC = 0x0, + Delay_Req = 0x1, + Pdelay_Req = 0x2, + Pdelay_Resp = 0x3, + Follow_up = 0x8, + Delay_Resp = 0x9, + Pdelay_Resp_Follow_Up = 0xA, + Announce = 0xB, + Signaling = 0xC, + Management = 0xD, }; - - typedef struct TimeStampStruct { - u32 TSversion; /* PTP Version 1 or PTP version2 */ - u32 TSmessagetype; /* Message type associated with this time stamp */ + u32 TSversion; /* PTP Version 1 or PTP version2 */ + u32 TSmessagetype; /* Message type associated with this time stamp */ - u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ - u32 TSupper32; /* Most significant 32 bit time stamp value */ - u32 TSlower32; /* Least Significat 32 bit time stamp value */ + u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ + u32 TSupper32; /* Most significant 32 bit time stamp value */ + u32 TSlower32; /* Least Significat 32 bit time stamp value */ } TimeStamp; @@ -1441,9 +1410,9 @@ typedef struct TimeStampStruct /* GmacTSControl = 0x0700, Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ enum GmacTSControlReg { - GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ + GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ - GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ + GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ /* TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken 00/01 X 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP @@ -1454,40 +1423,40 @@ enum GmacTSControlReg 11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP */ - GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ - GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ - GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ - GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ + GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ + GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ + GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ + GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ - GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ - GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ - GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ - GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ - GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ - GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ + GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ + GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ + GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ + GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ + GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ + GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ - GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ + GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ - GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ + GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ - GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ - GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ - GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ + GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ + GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ + GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ + GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ - GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ - GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ - GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ + GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ + GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ - GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ + GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ }; /* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ enum GmacTSSubSecIncrReg { - GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ + GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ }; /* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ @@ -1516,7 +1485,6 @@ enum GmacTSStatusReg GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */ }; - /********************************************************** * Time stamp related functions **********************************************************/ diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_plat.h b/bsp/ls2kdev/drivers/net/synopGMAC_plat.h index 9bbcc49ef0..3b6eaca197 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC_plat.h +++ b/bsp/ls2kdev/drivers/net/synopGMAC_plat.h @@ -239,4 +239,4 @@ static bool synopGMACCheckBits(u64 RegBase, u32 RegOffset, u32 BitPos) } } -#endif \ No newline at end of file +#endif diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c index cfb4c6bb3c..54d38d0d3f 100644 --- a/libcpu/mips/gs264/cache.c +++ b/libcpu/mips/gs264/cache.c @@ -67,4 +67,4 @@ rt_base_t rt_hw_cpu_icache_status(void) rt_base_t rt_hw_cpu_dcache_status(void) { return 0; -} \ No newline at end of file +} diff --git a/libcpu/mips/gs264/cpuinit_gcc.S b/libcpu/mips/gs264/cpuinit_gcc.S index bd84663350..592fedd88a 100644 --- a/libcpu/mips/gs264/cpuinit_gcc.S +++ b/libcpu/mips/gs264/cpuinit_gcc.S @@ -19,8 +19,8 @@ .globl rt_cpu_early_init rt_cpu_early_init: - mfc0 t0, CP0_CONFIG - ori t0, 3 - mtc0 t0, CP0_CONFIG + mfc0 t0, CP0_CONFIG + ori t0, 3 + mtc0 t0, CP0_CONFIG ehb - jr ra \ No newline at end of file + jr ra diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c index bfc694ab45..7bed69596a 100644 --- a/libcpu/mips/gs264/mips_mmu.c +++ b/libcpu/mips/gs264/mips_mmu.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-07-26 lizhirui the first version + * 2020-07-26 lizhirui the first version */ #include @@ -205,18 +205,18 @@ uint64_t mmu_tlb_get_bad_vaddr() void tlb_dump() { - uint32_t max_index = mmu_get_max_tlb_index(); - //uint32_t max_index = 10; - uint32_t entry; - tlb_item_t tlb_item; - - for(entry = 0;entry <= max_index;entry++) - { - mmu_tlb_read(entry,&tlb_item); - //mmu_tlb_write_indexed(entry,&tlb_item); - //mmu_tlb_read(entry,&tlb_item); - rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12); - rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c); - rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c); - } -} \ No newline at end of file + uint32_t max_index = mmu_get_max_tlb_index(); + //uint32_t max_index = 10; + uint32_t entry; + tlb_item_t tlb_item; + + for(entry = 0;entry <= max_index;entry++) + { + mmu_tlb_read(entry,&tlb_item); + //mmu_tlb_write_indexed(entry,&tlb_item); + //mmu_tlb_read(entry,&tlb_item); + rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c); + } +} diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h index c0b33ecf89..fcbcef3621 100644 --- a/libcpu/mips/gs264/mips_mmu.h +++ b/libcpu/mips/gs264/mips_mmu.h @@ -5,96 +5,95 @@ * * Change Logs: * Date Author Notes - * 2020-07-26 lizhirui the first version + * 2020-07-26 lizhirui the first version */ - #ifndef __MIPS_MMU_H__ #define __MIPS_MMU_H__ - typedef enum cpu_mode_t - { - CPU_MODE_KERNEL = 0x00, - CPU_MODE_SUPERVISOR = 0x01, - CPU_MODE_USER = 0x02 - }cpu_mode_t; +typedef enum cpu_mode_t +{ + CPU_MODE_KERNEL = 0x00, + CPU_MODE_SUPERVISOR = 0x01, + CPU_MODE_USER = 0x02 +}cpu_mode_t; - typedef enum page_mask_enum_t - { - PAGE_MASK_4KB = 0x00, - PAGE_MASK_16KB = 0x03, - PAGE_MASK_64KB = 0x0F, - PAGE_MASK_256KB = 0x3F, - PAGE_MASK_1MB = 0xFF, - PAGE_MASK_4MB = 0x3FF, - PAGE_MASK_16MB = 0xFFF, - PAGE_MASK_64MB = 0x3FFF, - PAGE_MASK_256MB = 0xFFFF, - PAGE_MASK_1GB = 0x3FFFF - }page_mask_enum_t; +typedef enum page_mask_enum_t +{ + PAGE_MASK_4KB = 0x00, + PAGE_MASK_16KB = 0x03, + PAGE_MASK_64KB = 0x0F, + PAGE_MASK_256KB = 0x3F, + PAGE_MASK_1MB = 0xFF, + PAGE_MASK_4MB = 0x3FF, + PAGE_MASK_16MB = 0xFFF, + PAGE_MASK_64MB = 0x3FFF, + PAGE_MASK_256MB = 0xFFFF, + PAGE_MASK_1GB = 0x3FFFF +}page_mask_enum_t; - typedef struct page_mask_t - { - uint64_t : 11; - uint64_t : 2; - uint64_t mask : 18; - uint64_t : 33; - }page_mask_t; +typedef struct page_mask_t +{ + uint64_t : 11; + uint64_t : 2; + uint64_t mask : 18; + uint64_t : 33; +}page_mask_t; - typedef struct entry_lo_t - { - uint64_t g : 1; - uint64_t v : 1; - uint64_t d : 1; - uint64_t c : 3; - uint64_t pfn : 24; - uint64_t pfnx : 3; - uint64_t : 29; - uint64_t xi : 1; - uint64_t ri : 1; - }entry_lo_t; +typedef struct entry_lo_t +{ + uint64_t g : 1; + uint64_t v : 1; + uint64_t d : 1; + uint64_t c : 3; + uint64_t pfn : 24; + uint64_t pfnx : 3; + uint64_t : 29; + uint64_t xi : 1; + uint64_t ri : 1; +}entry_lo_t; - typedef struct entry_hi_t - { - uint64_t asid : 8; - uint64_t : 5; - uint64_t vpn2 : 27; - uint64_t : 22; - uint64_t r : 2; - }entry_hi_t; +typedef struct entry_hi_t +{ + uint64_t asid : 8; + uint64_t : 5; + uint64_t vpn2 : 27; + uint64_t : 22; + uint64_t r : 2; +}entry_hi_t; - typedef struct tlb_item_t - { - entry_lo_t entry_lo[2]; - entry_hi_t entry_hi; - page_mask_t page_mask; - }tlb_item_t; +typedef struct tlb_item_t +{ + entry_lo_t entry_lo[2]; + entry_hi_t entry_hi; + page_mask_t page_mask; +}tlb_item_t; - #define read_c0_diag() __read_32bit_c0_register($22, 0) - #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) - #define read_c0_badvaddr() __read_64bit_c0_register($8, 0) - #define read_c0_random() __read_32bit_c0_register($1, 0) +#define read_c0_diag() __read_32bit_c0_register($22, 0) +#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) +#define read_c0_badvaddr() __read_64bit_c0_register($8, 0) +#define read_c0_random() __read_32bit_c0_register($1, 0) - #define reg_type_convert(variable,new_type) *((new_type *)(&variable)) - #define lowbit(x) ((x) & (-(x))) +#define reg_type_convert(variable,new_type) *((new_type *)(&variable)) +#define lowbit(x) ((x) & (-(x))) - void mmu_init(); - void mmu_set_cpu_mode(cpu_mode_t cpu_mode); - cpu_mode_t mmu_get_cpu_mode(); - void mmu_clear_tlb(); - void mmu_clear_itlb(); - uint32_t mmu_get_max_tlb_index(); - void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item); - void mmu_tlb_write_random(tlb_item_t *tlb_item); - void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item); - uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index); - void mmu_tlb_item_init(tlb_item_t *tlb_item); - void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global); - uint32_t mmu_tlb_get_random(); - uint32_t mmu_tlb_get_index(); - void mmu_tlb_set_index(uint32_t index); - uint32_t mmu_tlb_is_matched(); - uint64_t mmu_tlb_get_bad_vaddr(); +void mmu_init(); +void mmu_set_cpu_mode(cpu_mode_t cpu_mode); +cpu_mode_t mmu_get_cpu_mode(); +void mmu_clear_tlb(); +void mmu_clear_itlb(); +uint32_t mmu_get_max_tlb_index(); +void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item); +void mmu_tlb_write_random(tlb_item_t *tlb_item); +void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item); +uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index); +void mmu_tlb_item_init(tlb_item_t *tlb_item); +void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global); +uint32_t mmu_tlb_get_random(); +uint32_t mmu_tlb_get_index(); +void mmu_tlb_set_index(uint32_t index); +uint32_t mmu_tlb_is_matched(); +uint64_t mmu_tlb_get_bad_vaddr(); - void tlb_dump(); +void tlb_dump(); #endif \ No newline at end of file diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c index f6c73095d9..b2aed120ae 100644 --- a/libcpu/mips/gs264/mipscfg.c +++ b/libcpu/mips/gs264/mipscfg.c @@ -12,15 +12,15 @@ mips32_core_cfg_t g_mips_core = { - 64, /* icache_line_size */ - 128, /* icache_lines_per_way */ - 4, /* icache_ways */ + 64, /* icache_line_size */ + 128, /* icache_lines_per_way */ + 4, /* icache_ways */ 32768, - 64, /* dcache_line_size */ - 128, /* dcache_lines_per_way */ - 4, /* dcache_ways */ + 64, /* dcache_line_size */ + 128, /* dcache_lines_per_way */ + 4, /* dcache_ways */ 32768, - 64, /* max_tlb_entries */ + 64, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c index b08bdf4c65..b5bedace50 100644 --- a/libcpu/mips/gs264/mmu.c +++ b/libcpu/mips/gs264/mmu.c @@ -21,15 +21,15 @@ void *current_mmu_table = RT_NULL; void *mmu_table_get() { - return current_mmu_table; + return current_mmu_table; } void switch_mmu(void *mmu_table) { - current_mmu_table = mmu_table; + current_mmu_table = mmu_table; mmu_clear_tlb(); - mmu_clear_itlb(); + mmu_clear_itlb(); } /* dump 2nd level page table */ @@ -476,7 +476,7 @@ static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, si static void rt_hw_cpu_tlb_invalidate(void) { mmu_clear_tlb(); - mmu_clear_itlb(); + mmu_clear_itlb(); } #ifdef RT_USING_USERSPACE diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h index f2d4d11bc3..2472bf975f 100644 --- a/libcpu/mips/gs264/mmu.h +++ b/libcpu/mips/gs264/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,21 +14,21 @@ #include #define DESC_SEC (0x2) -#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ -#define MEMWB (3<<2) /* write back, no write allocate */ -#define MEMWT (2<<2) /* write through, no write allocate */ -#define SHAREDEVICE (1<<2) /* shared device */ -#define STRONGORDER (0<<2) /* strong ordered */ -#define XN (1<<4) /* eXecute Never */ +#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ +#define MEMWB (3<<2) /* write back, no write allocate */ +#define MEMWT (2<<2) /* write through, no write allocate */ +#define SHAREDEVICE (1<<2) /* shared device */ +#define STRONGORDER (0<<2) /* strong ordered */ +#define XN (1<<4) /* execute Never */ #ifdef RT_USING_USERSPACE -#define AP_RW (1<<10) /* supervisor=RW, user=No */ -#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ +#define AP_RW (1<<10) /* supervisor=RW, user=No */ +#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ #else -#define AP_RW (3<<10) /* supervisor=RW, user=RW */ -#define AP_RO ((2<<10) /* supervisor=RW, user=RO */ +#define AP_RW (3<<10) /* supervisor=RW, user=RW */ +#define AP_RO ((2<<10) /* supervisor=RW, user=RO */ #endif -#define SHARED (1<<16) /* shareable */ +#define SHARED (1<<16) /* shareable */ #define DOMAIN_FAULT (0x0) #define DOMAIN_CHK (0x1) -- GitLab