diff --git a/bsp/imxrt1052-evk/drivers/SConscript b/bsp/imxrt1052-evk/drivers/SConscript
index 1b44c183d01278033819cbcf0110936cafa00b22..6b735fe58cda2e5a734a4ee34d9526074fcb596b 100644
--- a/bsp/imxrt1052-evk/drivers/SConscript
+++ b/bsp/imxrt1052-evk/drivers/SConscript
@@ -8,6 +8,7 @@ cwd     = os.path.join(str(Dir('#')), 'drivers')
 src = Split("""
 board.c
 usart.c
+drv_sdram.c
 """)
 
 CPPPATH = [cwd]
diff --git a/bsp/imxrt1052-evk/drivers/board.c b/bsp/imxrt1052-evk/drivers/board.c
index 5060c9eae29e2b4cd446c061b398e3fef8cfed91..0e0955de88c615143eea3e2791a2c41e4e422ba5 100644
--- a/bsp/imxrt1052-evk/drivers/board.c
+++ b/bsp/imxrt1052-evk/drivers/board.c
@@ -18,6 +18,8 @@
 #include "board.h"
 #include "usart.h"
 
+static struct rt_memheap system_heap;
+
 /* ARM PLL configuration for RUN mode */
 const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U };
 
@@ -83,6 +85,64 @@ static void BOARD_BootClockRUN(void)
 }
 
 
+/* MPU configuration. */
+static void BOARD_ConfigMPU(void)
+{
+    /* Disable I cache and D cache */
+    SCB_DisableICache();
+    SCB_DisableDCache();
+
+    /* Disable MPU */
+    ARM_MPU_Disable();
+
+    /* Region 0 setting */
+    MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+    /* Region 1 setting */
+    MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+    /* Region 2 setting */
+    // spi flash: normal type, cacheable, no bufferable, no shareable
+    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+    /* Region 3 setting */
+    MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+    /* Region 4 setting */
+    MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+    /* Region 5 setting */
+    MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+    /* Region 6 setting */
+    MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
+
+#if defined(SDRAM_MPU_INIT)
+    /* Region 7 setting */
+    MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+
+    /* Region 8 setting */
+    MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
+#endif
+
+    /* Enable MPU */
+    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
+
+    /* Enable I cache and D cache */
+    SCB_EnableDCache();
+    SCB_EnableICache();
+}
+
+
 /**
  * This is the timer interrupt service routine.
  *
@@ -98,17 +158,23 @@ void SysTick_Handler(void)
     rt_interrupt_leave();
 }
 
+void rt_lowlevel_init(void)
+{
+    BOARD_ConfigMPU();
+
+    extern int imxrt_sdram_init(void);
+    imxrt_sdram_init();
+}
+
 /**
  * This function will initial LPC8XX board.
  */
 void rt_hw_board_init()
 {
     BOARD_BootClockRUN();
+
     
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
-
-    extern int imxrt_hw_usart_init(void);
-    imxrt_hw_usart_init();
     
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
@@ -119,7 +185,11 @@ void rt_hw_board_init()
 #endif
     
 #ifdef RT_USING_HEAP
-    rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
+    rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END);
+    rt_system_heap_init((void*)SDRAM_BEGIN, (void*)SDRAM_END);
+
+    rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
+    rt_memheap_init(&system_heap, "system", (void *)HEAP_BEGIN, HEAP_SIZE);
 #endif
 }
 
diff --git a/bsp/imxrt1052-evk/drivers/board.h b/bsp/imxrt1052-evk/drivers/board.h
index a356254c766c3613d0cb3bb493e3cbda2636ec38..43b2580552243a3ee90558ee4a14a34488b15265 100644
--- a/bsp/imxrt1052-evk/drivers/board.h
+++ b/bsp/imxrt1052-evk/drivers/board.h
@@ -21,18 +21,26 @@
 #include <fsl_iomuxc.h>
 
 #ifdef __CC_ARM
-extern int Image$$RW_m_data$$ZI$$Limit;
-#define HEAP_BEGIN    (&Image$$RW_m_data$$ZI$$Limit)
+extern int Image$$ARM_LIB_STACK$$ZI$$Limit;
+#define HEAP_BEGIN          (&Image$$ARM_LIB_STACK$$ZI$$Limit)
+#define HEAP_END            (0x2001FFFFu)
+
 #elif __ICCARM__
 #pragma section="HEAP"
-#define HEAP_BEGIN    (__segment_end("HEAP"))
+#define HEAP_BEGIN          (__segment_end("HEAP"))
+#define HEAP_END            (0x2001FFFFu)
+
 #else
-extern int __data_end__;
-#define HEAP_BEGIN    (&__data_end__)
+extern int heap_start;
+#define HEAP_BEGIN          (&heap_start)
+#define HEAP_END            (0x2001FFFFu)
 #endif
 
-#define HEAP_END          0x81DFFFFF
-//#define HEAP_END          0x2001FFFF
+#define HEAP_SIZE           ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
+
+#define SDRAM_MPU_INIT
+#define SDRAM_BEGIN         (0x80000000u)
+#define SDRAM_END           (0x81E00000u)
 
 void rt_hw_board_init(void);
 
diff --git a/bsp/imxrt1052-evk/drivers/drv_sdram.c b/bsp/imxrt1052-evk/drivers/drv_sdram.c
new file mode 100644
index 0000000000000000000000000000000000000000..2560caab5e22e8eae9ee8badc22c5921e1f5ad95
--- /dev/null
+++ b/bsp/imxrt1052-evk/drivers/drv_sdram.c
@@ -0,0 +1,195 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-12-04     Tanek        first implementation
+ */
+#include <stdint.h>
+#include <rthw.h>
+#include <rtthread.h>
+
+static uint32_t _RDWORD(uint32_t address)
+{    
+    return *((uint32_t *)address);
+}
+
+static void _WDWORD(uint32_t address, uint32_t value)
+{
+    *((uint32_t *)address) = value;
+}
+
+static void SDRAM_WaitIpCmdDone(void)
+{
+  unsigned long reg;
+  do
+  {
+    reg = _RDWORD(0x402F003C);
+  }while((reg & 0x3) == 0);
+}
+
+static void _clock_init(void)
+{
+    // Enable all clocks
+    _WDWORD(0x400FC068,0xffffffff);
+    _WDWORD(0x400FC06C,0xffffffff);
+    _WDWORD(0x400FC070,0xffffffff);
+    _WDWORD(0x400FC074,0xffffffff);
+    _WDWORD(0x400FC078,0xffffffff);
+    _WDWORD(0x400FC07C,0xffffffff);
+    _WDWORD(0x400FC080,0xffffffff);
+
+    _WDWORD(0x400D8030,0x00002001); 
+    _WDWORD(0x400D8100,0x001d0000);   
+    _WDWORD(0x400FC014,0x00010D40);   
+}
+
+static void _sdr_Init(void)
+{
+    // Config IOMUX
+    _WDWORD(0x401F8014, 0x00000000);
+    _WDWORD(0x401F8018, 0x00000000);
+    _WDWORD(0x401F801C, 0x00000000);
+    _WDWORD(0x401F8020, 0x00000000);
+    _WDWORD(0x401F8024, 0x00000000);
+    _WDWORD(0x401F8028, 0x00000000);
+    _WDWORD(0x401F802C, 0x00000000);
+    _WDWORD(0x401F8030, 0x00000000);
+    _WDWORD(0x401F8034, 0x00000000);
+    _WDWORD(0x401F8038, 0x00000000);
+    _WDWORD(0x401F803C, 0x00000000);
+    _WDWORD(0x401F8040, 0x00000000);
+    _WDWORD(0x401F8044, 0x00000000);
+    _WDWORD(0x401F8048, 0x00000000);
+    _WDWORD(0x401F804C, 0x00000000);
+    _WDWORD(0x401F8050, 0x00000000);
+    _WDWORD(0x401F8054, 0x00000000);
+    _WDWORD(0x401F8058, 0x00000000);
+    _WDWORD(0x401F805C, 0x00000000);
+    _WDWORD(0x401F8060, 0x00000000);
+    _WDWORD(0x401F8064, 0x00000000);
+    _WDWORD(0x401F8068, 0x00000000);
+    _WDWORD(0x401F806C, 0x00000000);
+    _WDWORD(0x401F8070, 0x00000000);
+    _WDWORD(0x401F8074, 0x00000000);
+    _WDWORD(0x401F8078, 0x00000000);
+    _WDWORD(0x401F807C, 0x00000000);
+    _WDWORD(0x401F8080, 0x00000000);
+    _WDWORD(0x401F8084, 0x00000000);
+    _WDWORD(0x401F8088, 0x00000000);
+    _WDWORD(0x401F808C, 0x00000000);
+    _WDWORD(0x401F8090, 0x00000000);
+    _WDWORD(0x401F8094, 0x00000000);
+    _WDWORD(0x401F8098, 0x00000000);
+    _WDWORD(0x401F809C, 0x00000000);
+    _WDWORD(0x401F80A0, 0x00000000);
+    _WDWORD(0x401F80A4, 0x00000000);
+    _WDWORD(0x401F80A8, 0x00000000);
+    _WDWORD(0x401F80AC, 0x00000000);
+    _WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION
+    _WDWORD(0x401F80B4, 0x00000000);
+    _WDWORD(0x401F80B8, 0x00000000);
+
+    // PAD ctrl
+    // drive strength = 0x7 to increase drive strength
+    // otherwise the data7 bit may fail.
+    _WDWORD(0x401F8204, 0x000110F9);
+    _WDWORD(0x401F8208, 0x000110F9);
+    _WDWORD(0x401F820C, 0x000110F9);
+    _WDWORD(0x401F8210, 0x000110F9);
+    _WDWORD(0x401F8214, 0x000110F9);
+    _WDWORD(0x401F8218, 0x000110F9);
+    _WDWORD(0x401F821C, 0x000110F9);
+    _WDWORD(0x401F8220, 0x000110F9);
+    _WDWORD(0x401F8224, 0x000110F9);
+    _WDWORD(0x401F8228, 0x000110F9);
+    _WDWORD(0x401F822C, 0x000110F9);
+    _WDWORD(0x401F8230, 0x000110F9);
+    _WDWORD(0x401F8234, 0x000110F9);
+    _WDWORD(0x401F8238, 0x000110F9);
+    _WDWORD(0x401F823C, 0x000110F9);
+    _WDWORD(0x401F8240, 0x000110F9);
+    _WDWORD(0x401F8244, 0x000110F9);
+    _WDWORD(0x401F8248, 0x000110F9);
+    _WDWORD(0x401F824C, 0x000110F9);
+    _WDWORD(0x401F8250, 0x000110F9);
+    _WDWORD(0x401F8254, 0x000110F9);
+    _WDWORD(0x401F8258, 0x000110F9);
+    _WDWORD(0x401F825C, 0x000110F9);
+    _WDWORD(0x401F8260, 0x000110F9);
+    _WDWORD(0x401F8264, 0x000110F9);
+    _WDWORD(0x401F8268, 0x000110F9);
+    _WDWORD(0x401F826C, 0x000110F9);
+    _WDWORD(0x401F8270, 0x000110F9);
+    _WDWORD(0x401F8274, 0x000110F9);
+    _WDWORD(0x401F8278, 0x000110F9);
+    _WDWORD(0x401F827C, 0x000110F9);
+    _WDWORD(0x401F8280, 0x000110F9);
+    _WDWORD(0x401F8284, 0x000110F9);
+    _WDWORD(0x401F8288, 0x000110F9);
+    _WDWORD(0x401F828C, 0x000110F9);
+    _WDWORD(0x401F8290, 0x000110F9);
+    _WDWORD(0x401F8294, 0x000110F9);
+    _WDWORD(0x401F8298, 0x000110F9);
+    _WDWORD(0x401F829C, 0x000110F9);
+    _WDWORD(0x401F82A0, 0x000110F9);
+    _WDWORD(0x401F82A4, 0x000110F9);
+    _WDWORD(0x401F82A8, 0x000110F9);
+
+    // Config SDR Controller Registers/
+    _WDWORD(0x402F0000,0x10000004); // MCR
+    _WDWORD(0x402F0008,0x00030524); // BMCR0
+    _WDWORD(0x402F000C,0x06030524); // BMCR1
+    _WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
+    _WDWORD(0x402F0014,0x8200001B); // BR1, 32MB
+    _WDWORD(0x402F0018,0x8400001B); // BR2, 32MB
+    _WDWORD(0x402F001C,0x8600001B); // BR3, 32MB
+    _WDWORD(0x402F0020,0x90000021); // BR4,
+    _WDWORD(0x402F0024,0xA0000019); // BR5,
+    _WDWORD(0x402F0028,0xA8000017); // BR6,
+    _WDWORD(0x402F002C,0xA900001B); // BR7,
+    _WDWORD(0x402F0030,0x00000021); // BR8,
+    _WDWORD(0x402F0004,0x000079A8);  //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.
+
+    // _WDWORD(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
+    _WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
+    _WDWORD(0x402F0044,0x00652922); // SDRAMCR1
+    _WDWORD(0x402F0048,0x00010920); // SDRAMCR2
+    _WDWORD(0x402F004C,0x50210A08); // SDRAMCR3
+
+    _WDWORD(0x402F0080,0x00000021); // DBICR0
+    _WDWORD(0x402F0084,0x00888888); // DBICR1
+    _WDWORD(0x402F0094,0x00000002); // IPCR1
+    _WDWORD(0x402F0098,0x00000000); // IPCR2
+
+    _WDWORD(0x402F0090,0x80000000); // IPCR0
+    _WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
+    SDRAM_WaitIpCmdDone();
+    _WDWORD(0x402F0090,0x80000000); // IPCR0
+    _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
+    SDRAM_WaitIpCmdDone();
+    _WDWORD(0x402F0090,0x80000000); // IPCR0
+    _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
+    SDRAM_WaitIpCmdDone();
+    _WDWORD(0x402F00A0,0x00000033); // IPTXDAT
+    _WDWORD(0x402F0090,0x80000000); // IPCR0
+    _WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
+    SDRAM_WaitIpCmdDone();
+    _WDWORD(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.
+}
+
+int imxrt_sdram_init(void)
+{
+    _clock_init();
+    _sdr_Init();
+    
+    return 0;
+}
+
+/*@}*/