diff --git a/.github/workflows/action_utest.yml b/.github/workflows/action_utest.yml index 7d0e2c44d848d2e23a4ac40190698cee3fdc47d4..2ff0bd8185fd87ff855fb7192ba86397c1a37573 100644 --- a/.github/workflows/action_utest.yml +++ b/.github/workflows/action_utest.yml @@ -12,6 +12,7 @@ jobs: matrix: legs: - {UTEST: "kernel/mem", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/mem.conf", SD_FILE: "sd.bin"} + - {UTEST: "kernel/ipc", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/ipc.conf", SD_FILE: "sd.bin"} - {UTEST: "components/utest", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "utest_self/self.conf", SD_FILE: "sd.bin"} - {UTEST: "kernel/mem/riscv64", RTT_BSP: "bsp/qemu-riscv-virt64", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", CONFIG_FILE: "kernel/mem.conf", SD_FILE: "None"} env: diff --git a/bsp/ft2004/.config b/bsp/ft2004/.config index 1bd8c76ede92376c4c9ddcad1fe79a810b078e01..1bf5a5a6eef66d4550469e4b4b458ff2767c800b 100644 --- a/bsp/ft2004/.config +++ b/bsp/ft2004/.config @@ -21,6 +21,7 @@ CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=4096 +CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 @@ -30,6 +31,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # # CONFIG_RT_KSERVICE_USING_STDLIB is not set # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -75,6 +77,7 @@ CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=4096 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_PRINTF_LONGLONG is not set CONFIG_RT_VER_NUM=0x40004 CONFIG_ARCH_ARM=y CONFIG_RT_USING_CPU_FFS=y @@ -159,6 +162,8 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=256 CONFIG_RT_USING_CAN=y @@ -219,7 +224,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set -CONFIG_RT_LIBC_FIXED_TIMEZONE=8 +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Network @@ -249,6 +254,7 @@ CONFIG_NETDEV_IPV6=0 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set # CONFIG_RT_USING_LWIP202 is not set +# CONFIG_RT_USING_LWIP203 is not set CONFIG_RT_USING_LWIP212=y # CONFIG_RT_USING_LWIP_IPV6 is not set CONFIG_RT_LWIP_MEM_ALIGNMENT=4 diff --git a/bsp/ft2004/applications/main.c b/bsp/ft2004/applications/main.c index 95fad98370a7bca879eb84cb2db73884a12cdcb9..449fc6fa3e34c64fe2d3ed85e3f0f91b1e19a896 100644 --- a/bsp/ft2004/applications/main.c +++ b/bsp/ft2004/applications/main.c @@ -62,16 +62,8 @@ void demo_core(void) int main(void) { - int count = 1; - #ifdef RT_USING_SMP demo_core(); #endif - - while (count++) - { - rt_thread_mdelay(2000); - } - return RT_EOK; } diff --git a/bsp/ft2004/drivers/board.c b/bsp/ft2004/drivers/board.c index 408a58d344a332d465b3b8fb806404ddef96f19f..55e0f0813585caddc7b6b5c93fc7e22566c1e5bc 100644 --- a/bsp/ft2004/drivers/board.c +++ b/bsp/ft2004/drivers/board.c @@ -68,11 +68,6 @@ struct mem_desc platform_mem_desc[] = { const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]); -rt_uint32_t platform_get_gic_dist_base(void) -{ - return FT_GICV3_DISTRIBUTOR_BASEADDRESS; -} - static rt_uint32_t timerStep; void rt_hw_timer_isr(int vector, void *parameter) diff --git a/bsp/ft2004/drivers/drv_can.c b/bsp/ft2004/drivers/drv_can.c index ff037557616f11f3953727540639d8985f93593c..fa743895d6eb8eb61d1c9c01a26ba0d78f5e6cc5 100644 --- a/bsp/ft2004/drivers/drv_can.c +++ b/bsp/ft2004/drivers/drv_can.c @@ -188,7 +188,8 @@ int rt_hw_can_init(void) #ifdef BSP_USING_CAN1 drv_can1.can_handle.Config.InstanceId = 1; - drv_can0.device.config.baud_rate = 1000000; + drv_can1.device.config.ticks = 20000; + drv_can1.device.config.baud_rate = 1000000; rt_sem_init(&drv_can1.recv_semaphore, "can1_recv", 0, RT_IPC_FLAG_FIFO); rt_hw_can_register(&drv_can1.device, drv_can1.name, diff --git a/bsp/ft2004/drivers/drv_usart.c b/bsp/ft2004/drivers/drv_usart.c index 96ac3c97eb70360f9d40ccd8e14fbb747b4fbeee..728174501e0349df9c66d012d571c73e49259b75 100644 --- a/bsp/ft2004/drivers/drv_usart.c +++ b/bsp/ft2004/drivers/drv_usart.c @@ -85,7 +85,8 @@ static void Ft_Os_Uart_Callback(void *Args, u32 Event, u32 EventData) if (FUART_EVENT_RECV_DATA == Event || FUART_EVENT_RECV_TOUT == Event) { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + if (serial->serial_rx) + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } else if (FUART_EVENT_RECV_ERROR == Event) { diff --git a/bsp/ft2004/drivers/ft2004.h b/bsp/ft2004/drivers/ft2004.h index fe3293ab94d24fd56221c1cb9903cb27f4b84b91..32164ae166959f118ecf0d0b30a3c2dc55a60a85 100644 --- a/bsp/ft2004/drivers/ft2004.h +++ b/bsp/ft2004/drivers/ft2004.h @@ -14,12 +14,18 @@ #include #include +#include "ft_parameters.h" #define ARM_GIC_NR_IRQS 160 #define ARM_GIC_MAX_NR 1 #define MAX_HANDLERS 160 #define GIC_IRQ_START 0 - +#define GIC_ACK_INTID_MASK 0x000003ff rt_uint64_t get_main_cpu_affval(void); +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + return FT_GICV3_DISTRIBUTOR_BASEADDRESS; +} + #endif // ! diff --git a/bsp/ft2004/drivers/gtimer.c b/bsp/ft2004/drivers/gtimer.c new file mode 100644 index 0000000000000000000000000000000000000000..b35acc6e6f9e28fe0bcd422d9a8be45618725895 --- /dev/null +++ b/bsp/ft2004/drivers/gtimer.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#include "cp15.h" +#include + +/** Set CNTFRQ + * This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * @param value: CNTFRQ Register value to set + */ +static inline void __set_cntfrq(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 0, 0); +} + +/** Get CNTFRQ + * This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * return CNTFRQ Register value + */ +static inline rt_uint32_t __get_cntfrq(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 0 , 0); + return result; +} + +/** Set CNTP_TVAL + * This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + * param value: CNTP_TVAL Register value to set + */ +static inline void __set_cntp_tval(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 0); +} + +/** Get CNTP_TVAL + * This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + * return CNTP_TVAL Register value + */ +static inline rt_uint32_t __get_cntp_tval(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 0); + return result; +} + +/** Get CNTPCT + * This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + * return CNTPCT Register value + */ +static inline rt_uint64_t __get_cntpct(void) +{ + rt_uint64_t result; + __get_cp64(15, 0, result, 14); + return result; +} + +/** Set CNTP_CVAL + * This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * param value: CNTP_CVAL Register value to set +*/ +static inline void __set_cntp_cval(rt_uint64_t value) +{ + __set_cp64(15, 2, value, 14); +} + +/** Get CNTP_CVAL + * This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * return CNTP_CVAL Register value + */ +static inline rt_uint64_t __get_cntp_cval(void) +{ + rt_uint64_t result; + __get_cp64(15, 2, result, 14); + return result; +} + +/** Set CNTP_CTL + * This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + * param value: CNTP_CTL Register value to set + */ +static inline void __set_cntp_ctl(uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 1); +} + +/** Get CNTP_CTL register + * return CNTP_CTL Register value + */ +static inline rt_uint32_t __get_cntp_ctl(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 1); + return result; +} + +/** Configures the frequency the timer shall run at. + * param value The timer frequency in Hz. + */ +void gtimer_set_counter_frequency(rt_uint32_t value) +{ + __set_cntfrq(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the frequency the timer shall run at. + * return timer frequency in Hz. + */ +rt_uint32_t gtimer_get_counter_frequency(void) +{ + return(__get_cntfrq()); +} + +/** Sets the reset value of the timer. + * param value: The value the timer is loaded with. + */ +void gtimer_set_load_value(rt_uint32_t value) +{ + __set_cntp_tval(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the current counter value. + * return Current counter value. + */ +rt_uint32_t gtimer_get_current_value(void) +{ + return(__get_cntp_tval()); +} + +/** Get the current physical counter value. + * return Current physical counter value. + */ +rt_uint64_t gtimer_get_current_physical_value(void) +{ + return(__get_cntpct()); +} + +/** Set the physical compare value. + * param value: New physical timer compare value. + */ +void gtimer_set_physical_compare_value(rt_uint64_t value) +{ + __set_cntp_cval(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the physical compare value. + * return Physical compare value. + */ +rt_uint64_t gtimer_get_physical_compare_value(void) +{ + return(__get_cntp_cval()); +} + +/** Configure the timer by setting the control value. + * param value: New timer control value. + */ +void gtimer_set_control(rt_uint32_t value) +{ + __set_cntp_ctl(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the control value. + * return Control value. + */ +rt_uint32_t gtimer_get_control(void) +{ + return(__get_cntp_ctl()); +} + diff --git a/bsp/ft2004/drivers/gtimer.h b/bsp/ft2004/drivers/gtimer.h new file mode 100644 index 0000000000000000000000000000000000000000..ec5d54127ef9709fa6a95bedf0249470ae86ce7a --- /dev/null +++ b/bsp/ft2004/drivers/gtimer.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#ifndef __GTIMER_H__ +#define __GTIMER_H__ + +#include + +void gtimer_set_counter_frequency(rt_uint32_t value); +rt_uint32_t gtimer_get_counter_frequency(void); +void gtimer_set_load_value(rt_uint32_t value); +rt_uint32_t gtimer_get_current_value(void); +rt_uint64_t gtimer_get_current_physical_value(void); +void gtimer_set_physical_compare_value(rt_uint64_t value); +rt_uint64_t gtimer_get_physical_compare_value(void); +void gtimer_set_control(rt_uint32_t value); +rt_uint32_t gtimer_get_control(void); + +#endif + diff --git a/bsp/ft2004/drivers/secondary_cpu.c b/bsp/ft2004/drivers/secondary_cpu.c index 5ffcadbefe8f8d534140b81d7da6c75ddaf356ad..0e6ffc3563dfaefa47ebe646fd62378fc7a97471 100644 --- a/bsp/ft2004/drivers/secondary_cpu.c +++ b/bsp/ft2004/drivers/secondary_cpu.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-05-26 10:09:45 - * @LastEditTime: 2021-05-26 10:31:44 + * @LastEditTime: 2021-08-16 16:32:08 * @Description:  This files is for * * @Modify History: diff --git a/bsp/ft2004/rtconfig.h b/bsp/ft2004/rtconfig.h index 17f4dd20e8510494b574a9149f327acb43eb4a7f..8c9afcbc3c134b6fe031d03fb857ad17a47805ba 100644 --- a/bsp/ft2004/rtconfig.h +++ b/bsp/ft2004/rtconfig.h @@ -18,6 +18,7 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 4096 +#define SYSTEM_THREAD_STACK_SIZE 4096 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 @@ -107,6 +108,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 256 #define RT_USING_CAN @@ -131,7 +133,7 @@ #define RT_USING_LIBC #define RT_USING_POSIX -#define RT_LIBC_FIXED_TIMEZONE 8 +#define RT_LIBC_DEFAULT_TIMEZONE 8 /* Network */ diff --git a/bsp/ft2004/rtconfig.py b/bsp/ft2004/rtconfig.py index ea482b8282145042be8bbd2e84c9395d6248a735..13fed7d6f564c183d11fa4db32eee78e41b2aa56 100644 --- a/bsp/ft2004/rtconfig.py +++ b/bsp/ft2004/rtconfig.py @@ -36,7 +36,7 @@ if PLATFORM == 'gcc': DEVICE = ' -march=armv8-a -mfpu=vfpv4-d16 -ftree-vectorize -ffast-math -mfloat-abi=soft --specs=nano.specs --specs=nosys.specs -fno-builtin ' - # DEVICE = ' -march=armv7-a -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=hard' + CFLAGS = DEVICE + ' -Wall' AFLAGS = ' -c'+ DEVICE + ' -fsingle-precision-constant -fno-builtin -x assembler-with-cpp -D__ASSEMBLY__' LINK_SCRIPT = 'ft_aarch32.lds' diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h index 3f981376976d929f0f9de96549705727fc53efb6..9ea3dd58f834894661cc709eac5b2aefad91a854 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h @@ -85,4 +85,22 @@ #define PHY_INT_MASK (1<<5) #endif +#ifdef PHY_USING_LAN8742A +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG 0x1DU +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MASK_REG 0x1EU +#define PHY_LINK_DOWN_MASK (1<<4) +#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) + +/* The PHY status register. */ +#define PHY_Status_REG 0x1FU +#define PHY_10M_MASK (1<<2) +#define PHY_100M_MASK (1<<3) +#define PHY_FULL_DUPLEX_MASK (1<<4) +#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) +#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) +#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) +#endif /* PHY_USING_LAN8742A */ + #endif /* __DRV_ETH_H__ */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c index 78ee5d0967f4d43e55a490132b1881a688138142..529b1e1157908842458e231bb22bb83c90b51318 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c @@ -83,9 +83,7 @@ static int onboard_spiflash_mount(void) { struct rt_device *mtd_dev = RT_NULL; -#ifndef FAL_USING_AUTO_INIT fal_init(); -#endif mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME); if (!mtd_dev) diff --git a/bsp/stm32/stm32f746-st-nucleo/.config b/bsp/stm32/stm32f746-st-nucleo/.config new file mode 100644 index 0000000000000000000000000000000000000000..53e188ad36b8858fd55a5f14f0f0b00c95bf5711 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/.config @@ -0,0 +1,721 @@ +# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# end of kservice optimization + +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart3" +# CONFIG_RT_PRINTF_LONGLONG is not set +# end of Kernel Device Object + +CONFIG_RT_VER_NUM=0x40004 +# end of RT-Thread Kernel + +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C++ features + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 +# end of Command shell + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_NFS is not set +# end of Device virtual file system + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +CONFIG_RT_USING_SOFT_RTC=y +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB +# end of Device Drivers + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 +# end of POSIX layer and C standard library + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set +# end of Socket abstraction layer + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set +CONFIG_NETDEV_USING_PING=y +# end of Network interface device + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP202 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +# end of Static IPv4 Address + +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set +# end of light weight TCP/IP stack + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# end of AT commands + +# CONFIG_LWIP_USING_DHCPD is not set +# end of Network + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set +# end of VBUS(Virtual Software BUS) + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_LWP is not set +# end of RT-Thread Components + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# end of language packages + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# end of tools packages + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# end of system packages + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# end of AI packages + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# end of miscellaneous packages +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F7=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F746ZG=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_USART=y +# CONFIG_BSP_USING_ETH is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART3=y +# CONFIG_BSP_UART3_RX_USING_DMA is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/stm32/stm32f746-st-nucleo/Kconfig b/bsp/stm32/stm32f746-st-nucleo/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..8cbc7b71a8c0cf95b0cefa5f35f19353215eb570 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32f746-st-nucleo/README.md b/bsp/stm32/stm32f746-st-nucleo/README.md new file mode 100644 index 0000000000000000000000000000000000000000..cf99b63464b24a4f2d0e3350830e34b1476d69f7 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/README.md @@ -0,0 +1,55 @@ +# STM32F746-Nucleo BSP Introduction + +[中文](README_zh.md) + +## MCU: STM32F746ZG @216MHz, 1MB FLASH, 320KB RAM + +he STM32 Nucleo-144 board provides an affordable and flexible way for users to try out new concepts and build prototypes by choosing from the various combinations of performance and power consumption features, provided by the STM32 microcontroller. For the compatible boards, the internal or external SMPS significantly reduces power consumption in Run mode. + +![board](figures/en.high-perf_nucleo-144_mbed.jpg) + +The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and the ST morpho headers provide an easy means of expanding the functionality of the Nucleo open development platform with a wide choice of specialized shields. + + + +The STM32 Nucleo-144 board does not require any separate probe as it integrates the ST-LINK debugger/programmer. + + + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software libraries and examples available with the STM32Cube MCU Package. + +#### KEY FEATURES + +- Common features + - STM32 microcontroller in LQFP144 package + - 3 user LEDs + - 2 user and reset push-buttons + - 32.768 kHz crystal oscillator + - Board connectors:SWDST Zio expansion connector including ARDUINO® Uno V3ST morpho expansion connector + - Flexible power-supply options: ST-LINK, USB VBUS or external sources + - On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port, and debug port + - Comprehensive free software libraries and examples available with the STM32Cube MCU Package + - Support of a wide choice of Integrated Development Environments (IDEs) including IAR™, Keil®, and STM32CubeIDE +- Board-specific features + - External or internal SMPS to generate Vcore logic supply + - Ethernet compliant with IEEE-802.3-2002 + - USB OTG full speed or device only + - Board connectors:USB with Micro-AB or USB Type-C™Ethernet RJ45 + - Arm® Mbed Enabled™ compliant + + + +## Maintained By + +[BruceOu](https://github.com/Ouxiaolong/) + + + +## Translated By +> ouxiaolong@bruceou.cn +> +> https://github.com/Ouxiaolong/ + + + + diff --git a/bsp/stm32/stm32f746-st-nucleo/README_zh.md b/bsp/stm32/stm32f746-st-nucleo/README_zh.md new file mode 100644 index 0000000000000000000000000000000000000000..4dcbfb278174bf37bd4721982e2f7c244c703ff3 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/README_zh.md @@ -0,0 +1,110 @@ +# STM32F746 NUCLEO-F746ZG开发板 BSP 说明 +## 简介 + +本文档为 NUCLEO-F746ZG 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-F746ZG是st推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 216Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F746 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/en.high-perf_nucleo-144_mbed.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32f746，主频 216MHz，1MB FLASH ，320KB RAM ，16K CACHE + +- 常用外设 + - LED ：3个，LED1 (绿色，PB0),LED2（蓝色，PB7），LED3（红色，PB14） + - 按键：2个，B1（用户按键，PC13），B2（复位引脚） +- 常用接口：USB 转串口3、以太网接口 +- 调试接口：ST-LINK + +开发板更多详细信息请参考ST [NUCLEO-F746zg开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :-----------------| :----------: | :-------------------------------------| +| USB 转串口3 | 支持 | | +| 以太网 | 支持 | PHY 选项 LAN8720A（兼容 LAN8742A） | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 | +| UART | 支持 | UART3 | +| **扩展模块** | **支持情况** | **备注** | +| 暂无 | 暂不支持 | 暂不支持 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Jan 9 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用 Ethernet 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [BruceOu](https://github.com/Ouxiaolong/), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f746-st-nucleo/SConscript b/bsp/stm32/stm32f746-st-nucleo/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..20f7689c53ca71a676748f79187f9764065466c5 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32f746-st-nucleo/SConstruct b/bsp/stm32/stm32f746-st-nucleo/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..050835a35aa7256f3ac51b8129196f3d2cb5bf7d --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32F7xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f746-st-nucleo/applications/SConscript b/bsp/stm32/stm32f746-st-nucleo/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..6f66f7ab7360b02f3561ec14d3f28841190e7e83 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32f746-st-nucleo/applications/main.c b/bsp/stm32/stm32f746-st-nucleo/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..27a423eda3f255adb1e436f7d438a6674334c83f --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-14 BruceOu first version + */ + +#include +#include +#include + +/* defined the LED1 pin: PB0 */ +#define LED1_PIN GET_PIN(B, 0) + +int main(void) +{ + int count = 1; + /* set LED1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000000000000000000000000000000000..c93c7a2d81f7dfebdeee6d41b0f08faa3141ec73 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/.mxproject @@ -0,0 +1,19 @@ +[PreviousLibFiles] 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+ +[PreviousUsedMakefileFiles] +SourceFiles=Src\main.c;Src\stm32f7xx_it.c;Src\stm32f7xx_hal_msp.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Src/system_stm32f7xx.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Src/system_stm32f7xx.c;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;; +HeaderPath=Drivers\STM32F7xx_HAL_Driver\Inc;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F7xx\Include;Drivers\CMSIS\Include;Inc; +CDefines=USE_HAL_DRIVER;STM32F746xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousUsedIarFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f7xx_it.c;..\Src\stm32f7xx_hal_msp.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;..\\Src/system_stm32f7xx.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;..\Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;..\\Src/system_stm32f7xx.c;..\Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;; +HeaderPath=..\Drivers\STM32F7xx_HAL_Driver\Inc;..\Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F7xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F746xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +HeaderPath=D:/RT-ThreadStudio/workspace/Nucleo-F746ZG/board/CubeMX_Config/Inc +HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; +SourcePath=D:/RT-ThreadStudio/workspace/Nucleo-F746ZG/board/CubeMX_Config/Src +SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;main.c; + diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000000000000000000000000000000000..51adeb8bda76ad1f37bff72dcfc438addb7532a5 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,218 @@ +#MicroXplorer Configuration settings - do not modify +ETH.IPParameters=MediaInterface +ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.Family=STM32F7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=ETH +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SPI2 +Mcu.IP5=SYS +Mcu.IP6=UART5 +Mcu.IP7=USART3 +Mcu.IPNb=8 +Mcu.Name=STM32F746ZGTx +Mcu.Package=LQFP144 +Mcu.Pin0=PC13 +Mcu.Pin1=PC14/OSC32_IN +Mcu.Pin10=PA7 +Mcu.Pin11=PC4 +Mcu.Pin12=PC5 +Mcu.Pin13=PB10 +Mcu.Pin14=PB13 +Mcu.Pin15=PD8 +Mcu.Pin16=PD9 +Mcu.Pin17=PC12 +Mcu.Pin18=PD2 +Mcu.Pin19=PG11 +Mcu.Pin2=PC15/OSC32_OUT +Mcu.Pin20=PG13 +Mcu.Pin21=VP_SYS_VS_Systick +Mcu.Pin3=PH0/OSC_IN +Mcu.Pin4=PH1/OSC_OUT +Mcu.Pin5=PC1 +Mcu.Pin6=PC2 +Mcu.Pin7=PC3 +Mcu.Pin8=PA1 +Mcu.Pin9=PA2 +Mcu.PinsNb=22 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F746ZGTx +MxCube.Version=6.0.1 +MxDb.Version=DB.6.0.0 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA1.Locked=true +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA2.Locked=true +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA7.Locked=true +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PB10.Mode=Full_Duplex_Master +PB10.Signal=SPI2_SCK +PB13.Locked=true +PB13.Mode=RMII +PB13.Signal=ETH_TXD1 +PC1.Locked=true +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC12.Mode=Asynchronous +PC12.Signal=UART5_TX +PC13.GPIOParameters=GPIO_Label +PC13.GPIO_Label=USER_Btn [B1] +PC13.Locked=true +PC13.Signal=GPXTI13 +PC14/OSC32_IN.Locked=true +PC14/OSC32_IN.Mode=LSE-External-Oscillator +PC14/OSC32_IN.Signal=RCC_OSC32_IN +PC15/OSC32_OUT.Locked=true +PC15/OSC32_OUT.Mode=LSE-External-Oscillator +PC15/OSC32_OUT.Signal=RCC_OSC32_OUT +PC2.Mode=Full_Duplex_Master +PC2.Signal=SPI2_MISO +PC3.Mode=Full_Duplex_Master +PC3.Signal=SPI2_MOSI +PC4.Locked=true +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.Locked=true +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PD2.Mode=Asynchronous +PD2.Signal=UART5_RX +PD8.Locked=true +PD8.Mode=Asynchronous +PD8.Signal=USART3_TX +PD9.Locked=true +PD9.Mode=Asynchronous +PD9.Signal=USART3_RX +PG11.Locked=true +PG11.Mode=RMII +PG11.Signal=ETH_TX_EN +PG13.Locked=true +PG13.Mode=RMII +PG13.Signal=ETH_TXD0 +PH0/OSC_IN.GPIOParameters=GPIO_Label +PH0/OSC_IN.GPIO_Label=MCO [STM32F103CBT6_PA8] +PH0/OSC_IN.Locked=true +PH0/OSC_IN.Mode=HSE-External-Clock-Source +PH0/OSC_IN.Signal=RCC_OSC_IN +PH1/OSC_OUT.Locked=true +PH1/OSC_OUT.Mode=HSE-External-Clock-Source +PH1/OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F746ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.16.1 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=EWARM V8 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_SPI1_Init-SPI1-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_UART4_Init-UART4-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.AHBFreq_Value=216000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=54000000 +RCC.APB1TimFreq_Value=108000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=108000000 +RCC.APB2TimFreq_Value=216000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=216000000 +RCC.EthernetFreq_Value=216000000 +RCC.FCLKCortexFreq_Value=216000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=216000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=54000000 +RCC.I2C2Freq_Value=54000000 +RCC.I2C3Freq_Value=54000000 +RCC.I2C4Freq_Value=54000000 +RCC.I2SFreq_Value=192000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFToutputFreq_Value=96000000 +RCC.LPTIM1Freq_Value=54000000 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=216000000 +RCC.PLLCLKFreq_Value=216000000 +RCC.PLLI2SPCLKFreq_Value=192000000 +RCC.PLLI2SQCLKFreq_Value=192000000 +RCC.PLLI2SRCLKFreq_Value=192000000 +RCC.PLLI2SRoutputFreq_Value=192000000 +RCC.PLLM=4 +RCC.PLLN=216 +RCC.PLLQCLKFreq_Value=216000000 +RCC.PLLQoutputFreq_Value=216000000 +RCC.PLLSAIPCLKFreq_Value=192000000 +RCC.PLLSAIQCLKFreq_Value=192000000 +RCC.PLLSAIRCLKFreq_Value=192000000 +RCC.PLLSAIoutputFreq_Value=192000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RNGFreq_Value=216000000 +RCC.SAI1Freq_Value=192000000 +RCC.SAI2Freq_Value=192000000 +RCC.SDMMCFreq_Value=216000000 +RCC.SPDIFRXFreq_Value=192000000 +RCC.SYSCLKFreq_VALUE=216000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=54000000 +RCC.UART5Freq_Value=54000000 +RCC.UART7Freq_Value=54000000 +RCC.UART8Freq_Value=54000000 +RCC.USART1Freq_Value=108000000 +RCC.USART2Freq_Value=54000000 +RCC.USART3Freq_Value=54000000 +RCC.USART6Freq_Value=108000000 +RCC.USBFreq_Value=216000000 +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=432000000 +RCC.VCOSAIOutputFreq_Value=384000000 +SH.GPXTI13.0=GPIO_EXTI13 +SH.GPXTI13.ConfNb=1 +SPI2.CalculateBaudRate=27.0 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER +USART3.IPParameters=VirtualMode-Asynchronous +USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000000000000000000000000000000000..89b704b3a56bfdecdd119a39331ee8626154c8eb --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define USER_Btn_Pin GPIO_PIN_13 +#define USER_Btn_GPIO_Port GPIOC +#define MCO_Pin GPIO_PIN_0 +#define MCO_GPIO_Port GPIOH +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..3400e38c5fb4a8243bd3b151268ce922fbf7cd11 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,483 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* LAN8742A_PHY_ADDRESS Address*/ +#define LAN8742A_PHY_ADDRESS 1 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ + +#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */ +#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/stm32f7xx_it.h b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/stm32f7xx_it.h new file mode 100644 index 0000000000000000000000000000000000000000..a1a9645d98d7cc34dd4a3c913c3420d80b53f5aa --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Inc/stm32f7xx_it.h @@ -0,0 +1,84 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000000000000000000000000000000000..0fb797171cd6fc49c72150e6b557f6ac1f79e66f --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/main.c @@ -0,0 +1,409 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +ETH_HandleTypeDef heth; + +SPI_HandleTypeDef hspi2; + +UART_HandleTypeDef huart5; +UART_HandleTypeDef huart3; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_ETH_Init(void); +static void MX_SPI2_Init(void); +static void MX_UART5_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART3_UART_Init(); + MX_ETH_Init(); + MX_SPI2_Init(); + MX_UART5_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_UART5; + PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + PeriphClkInitStruct.Uart5ClockSelection = RCC_UART5CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ETH Initialization Function + * @param None + * @retval None + */ +static void MX_ETH_Init(void) +{ + + /* USER CODE BEGIN ETH_Init 0 */ + + /* USER CODE END ETH_Init 0 */ + + /* USER CODE BEGIN ETH_Init 1 */ + + /* USER CODE END ETH_Init 1 */ + heth.Instance = ETH; + heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; + heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS; + heth.Init.MACAddr[0] = 0x00; + heth.Init.MACAddr[1] = 0x80; + heth.Init.MACAddr[2] = 0xE1; + heth.Init.MACAddr[3] = 0x00; + heth.Init.MACAddr[4] = 0x00; + heth.Init.MACAddr[5] = 0x00; + heth.Init.RxMode = ETH_RXPOLLING_MODE; + heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; + heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_ETH_Init(&heth) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ETH_Init 2 */ + + /* USER CODE END ETH_Init 2 */ + +} + +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_4BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 7; + hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief UART5 Initialization Function + * @param None + * @retval None + */ +static void MX_UART5_Init(void) +{ + + /* USER CODE BEGIN UART5_Init 0 */ + + /* USER CODE END UART5_Init 0 */ + + /* USER CODE BEGIN UART5_Init 1 */ + + /* USER CODE END UART5_Init 1 */ + huart5.Instance = UART5; + huart5.Init.BaudRate = 115200; + huart5.Init.WordLength = UART_WORDLENGTH_8B; + huart5.Init.StopBits = UART_STOPBITS_1; + huart5.Init.Parity = UART_PARITY_NONE; + huart5.Init.Mode = UART_MODE_TX_RX; + huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart5.Init.OverSampling = UART_OVERSAMPLING_16; + huart5.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart5.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart5) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART5_Init 2 */ + + /* USER CODE END UART5_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /*Configure GPIO pin : USER_Btn_Pin */ + GPIO_InitStruct.Pin = USER_Btn_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c new file mode 100644 index 0000000000000000000000000000000000000000..7826021b9a463725f9ecbfee2e3e90112dafff54 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f7xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ETH MSP Initialization +* This function configures the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ETH_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } + +} + +/** +* @brief ETH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_13); + + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PC2 ------> SPI2_MISO + PC3 ------> SPI2_MOSI + PB10 ------> SPI2_SCK + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PC2 ------> SPI2_MISO + PC3 ------> SPI2_MOSI + PB10 ------> SPI2_SCK + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==UART5) + { + /* USER CODE BEGIN UART5_MspInit 0 */ + + /* USER CODE END UART5_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_UART5_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN UART5_MspInit 1 */ + + /* USER CODE END UART5_MspInit 1 */ + } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==UART5) + { + /* USER CODE BEGIN UART5_MspDeInit 0 */ + + /* USER CODE END UART5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART5_CLK_DISABLE(); + + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN UART5_MspDeInit 1 */ + + /* USER CODE END UART5_MspDeInit 1 */ + } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_it.c b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_it.c new file mode 100644 index 0000000000000000000000000000000000000000..000e18671fb509ce4ba0a69b8cbd622c7a36babe --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/stm32f7xx_it.c @@ -0,0 +1,218 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/system_stm32f7xx.c b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/system_stm32f7xx.c new file mode 100644 index 0000000000000000000000000000000000000000..c07308121eb20c6f040d7e954f2fd56cb44f3726 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/CubeMX_Config/Src/system_stm32f7xx.c @@ -0,0 +1,278 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f746-st-nucleo/board/Kconfig b/bsp/stm32/stm32f746-st-nucleo/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..16a55c51f85872dd47821c1f6532ef8d68581d66 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/Kconfig @@ -0,0 +1,253 @@ +menu "Hardware Drivers Config" + +config SOC_STM32F746ZG + bool + select SOC_SERIES_STM32F7 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_USB_TO_USART + bool "Enable USB TO USART (uart3)" + select BSP_USING_UART3 + default y + + config BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_LWIP + default n + + if BSP_USING_ETH + choice + prompt "On-board PHY chip" + default PHY_USING_LAN8742A + + config PHY_USING_LAN8720A + bool "LAN8720A" + + config PHY_USING_DM9161CEP + bool "DM9161CEP" + + config PHY_USING_LAN8742A + bool "LAN8742A" + endchoice + endif +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART5 + bool "Enable UART5" + default n + + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + endif + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 175 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 175 + default 23 + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + + config BSP_USING_TIM3 + bool "Enable TIM3" + default n + + config BSP_USING_TIM4 + bool "Enable TIM4" + default n + + config BSP_USING_TIM5 + bool "Enable TIM5" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM3 + bool "Enable timer3 output pwm" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH2 + bool "Enable PWM3 channel2" + default n + + config BSP_USING_PWM3_CH3 + bool "Enable PWM3 channel3" + default n + + config BSP_USING_PWM3_CH4 + bool "Enable PWM3 channel4" + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using CAN1" + default n + endif + + config BSP_USING_USBD + bool "Enable USB device" + select RT_USING_USB_DEVICE + default n + if BSP_USING_USBD + config BSP_USB_CONNECT_PIN + int "USB connect pin" + default 67 + + config BSP_USB_PULL_UP_STATUS + int "USB PULL UP STATUS" + default 0 + endif + source "libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32f746-st-nucleo/board/SConscript b/bsp/stm32/stm32f746-st-nucleo/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..3c6a939c99a478efadbb3bba7515f7844d0b088b --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/SConscript @@ -0,0 +1,35 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add the general drivers. +src = Glob('board.c') +src += Glob('CubeMX_Config/Src/stm32f7xx_hal_msp.c') + +if GetDepend(['BSP_USING_ETH']): + src += Glob('ports/phy_reset.c') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f746xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/arm/startup_stm32f746xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/startup_stm32f746xx.s'] + +# STM32F756xx || STM32F746xx || STM32F745xx || STM32F767xx || +# STM32F769xx || STM32F777xx || STM32F779xx || STM32F722xx || +# STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx || STM32F750xx +# You can select chips from the list above +CPPDEFINES = ['STM32F746xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/stm32/stm32f746-st-nucleo/board/board.c b/bsp/stm32/stm32f746-st-nucleo/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..fb1e614bc71671591b95e0c8390710f07f179981 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/board.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-14 BruceOu first version + */ + +#include "board.h" + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32f746-st-nucleo/board/board.h b/bsp/stm32/stm32f746-st-nucleo/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..3b37641ec99ca92f380c685ca89c579a92a16d69 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/board.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-14 BruceOu first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (1024 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE (256) +#define STM32_SRAM_END (0x20010000 + STM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#endif diff --git a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..33fb05402cae7bdf2f3cbb1afad3b14a9421bbc6 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..09cdaa3a09b8b5f4853f977918b980f623b96601 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32F7xx with GNU ld + * jinsheng 2019-01-06 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 320k /* 320 K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..7a2a883cd35a3a1c418605ca1fcc7d26c1d3a09c --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00200000 { ; load region size_region + ER_IROM1 0x08000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20020000 0x00080000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f746-st-nucleo/board/ports/phy_reset.c b/bsp/stm32/stm32f746-st-nucleo/board/ports/phy_reset.c new file mode 100644 index 0000000000000000000000000000000000000000..79b8fecc16bb99c5d77584c56cf5f52a946a6684 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/board/ports/phy_reset.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-06-27 luhuadong first version + */ + +#include + +void phy_reset(void) +{ + /* + * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin, + * so no additional reset is required. + */ + + return ; +} diff --git a/bsp/stm32/stm32f746-st-nucleo/figures/en.high-perf_nucleo-144_mbed.jpg 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0000000000000000000000000000000000000000..faa93f37cdf824efd53c15b77e75dc1f03727d9a --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/stm32/stm32f746-st-nucleo/project.uvoptx b/bsp/stm32/stm32f746-st-nucleo/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..1f71708a8bba0dcd1e14d504695a42cc57e6f508 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/project.uvoptx @@ -0,0 +1,1336 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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0000000000000000000000000000000000000000..d28ac766fd0be20c9802707dc7e0cd2e5f294ddd --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/project.uvprojx @@ -0,0 +1,972 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + STM32F746ZGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.14.0 + http://www.keil.com/pack/ + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + 0 + $$Device:STM32F746ZGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746ZGTx$CMSIS\SVD\STM32F746.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + RT_USING_ARM_LIBC, USE_HAL_DRIVER, STM32F746xx, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;rt-thread\libcpu\arm\common;rt-thread\libcpu\arm\cortex-m7;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\spi;rt-thread\components\drivers\include;rt-thread\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;libraries\HAL_Drivers;libraries\HAL_Drivers\config;rt-thread\components\dfs\include;rt-thread\components\dfs\filesystems\devfs;rt-thread\components\finsh;.;rt-thread\include;rt-thread\components\libc\compilers\armlibc;rt-thread\components\libc\compilers\common;libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Inc;libraries\STM32F7xx_HAL\CMSIS\Device\ST\STM32F7xx\Include;libraries\STM32F7xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + backtrace.c + 1 + rt-thread\libcpu\arm\common\backtrace.c + + + showmem.c + 1 + rt-thread\libcpu\arm\common\showmem.c + + + div0.c + 1 + rt-thread\libcpu\arm\common\div0.c + + + context_rvds.S + 2 + rt-thread\libcpu\arm\cortex-m7\context_rvds.S + + + cpuport.c + 1 + rt-thread\libcpu\arm\cortex-m7\cpuport.c + + + cpu_cache.c + 1 + rt-thread\libcpu\arm\cortex-m7\cpu_cache.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + pin.c + 1 + rt-thread\components\drivers\misc\pin.c + + + serial.c + 1 + rt-thread\components\drivers\serial\serial.c + + + spi_core.c + 1 + rt-thread\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + rt-thread\components\drivers\spi\spi_dev.c + + + ringbuffer.c + 1 + rt-thread\components\drivers\src\ringbuffer.c + + + completion.c + 1 + rt-thread\components\drivers\src\completion.c + + + workqueue.c + 1 + rt-thread\components\drivers\src\workqueue.c + + + dataqueue.c + 1 + rt-thread\components\drivers\src\dataqueue.c + + + ringblk_buf.c + 1 + rt-thread\components\drivers\src\ringblk_buf.c + + + pipe.c + 1 + rt-thread\components\drivers\src\pipe.c + + + waitqueue.c + 1 + rt-thread\components\drivers\src\waitqueue.c + + + + + Drivers + + + startup_stm32f746xx.s + 2 + libraries\STM32F7xx_HAL\CMSIS\Device\ST\STM32F7xx\Source\Templates\arm\startup_stm32f746xx.s + + + stm32f7xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f7xx_hal_msp.c + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + libraries\HAL_Drivers\drv_usart.c + + + drv_common.c + 1 + libraries\HAL_Drivers\drv_common.c + + + drv_spi.c + 1 + libraries\HAL_Drivers\drv_spi.c + + + + + Filesystem + + + dfs_posix.c + 1 + rt-thread\components\dfs\src\dfs_posix.c + + + dfs_file.c + 1 + rt-thread\components\dfs\src\dfs_file.c + + + select.c + 1 + rt-thread\components\dfs\src\select.c + + + dfs.c + 1 + rt-thread\components\dfs\src\dfs.c + + + poll.c + 1 + rt-thread\components\dfs\src\poll.c + + + dfs_fs.c + 1 + rt-thread\components\dfs\src\dfs_fs.c + + + devfs.c + 1 + rt-thread\components\dfs\filesystems\devfs\devfs.c + + + + + finsh + + + finsh_node.c + 1 + rt-thread\components\finsh\finsh_node.c + + + finsh_parser.c + 1 + rt-thread\components\finsh\finsh_parser.c + + + cmd.c + 1 + rt-thread\components\finsh\cmd.c + + + finsh_vm.c + 1 + rt-thread\components\finsh\finsh_vm.c + + + msh_file.c + 1 + rt-thread\components\finsh\msh_file.c + + + shell.c + 1 + rt-thread\components\finsh\shell.c + + + msh.c + 1 + rt-thread\components\finsh\msh.c + + + finsh_var.c + 1 + rt-thread\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + rt-thread\components\finsh\finsh_compiler.c + + + finsh_heap.c + 1 + rt-thread\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + rt-thread\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + rt-thread\components\finsh\finsh_error.c + + + finsh_token.c + 1 + rt-thread\components\finsh\finsh_token.c + + + finsh_init.c + 1 + rt-thread\components\finsh\finsh_init.c + + + + + Kernel + + + object.c + 1 + rt-thread\src\object.c + + + idle.c + 1 + rt-thread\src\idle.c + + + device.c + 1 + rt-thread\src\device.c + + + components.c + 1 + rt-thread\src\components.c + + + thread.c + 1 + rt-thread\src\thread.c + + + timer.c + 1 + rt-thread\src\timer.c + + + scheduler.c + 1 + rt-thread\src\scheduler.c + + + mem.c + 1 + rt-thread\src\mem.c + + + irq.c + 1 + rt-thread\src\irq.c + + + kservice.c + 1 + rt-thread\src\kservice.c + + + ipc.c + 1 + rt-thread\src\ipc.c + + + mempool.c + 1 + rt-thread\src\mempool.c + + + clock.c + 1 + rt-thread\src\clock.c + + + + + libc + + + stdio.c + 1 + rt-thread\components\libc\compilers\armlibc\stdio.c + + + libc.c + 1 + rt-thread\components\libc\compilers\armlibc\libc.c + + + syscalls.c + 1 + rt-thread\components\libc\compilers\armlibc\syscalls.c + + + mem_std.c + 1 + rt-thread\components\libc\compilers\armlibc\mem_std.c + + + stdlib.c + 1 + rt-thread\components\libc\compilers\common\stdlib.c + + + time.c + 1 + rt-thread\components\libc\compilers\common\time.c + + + unistd.c + 1 + rt-thread\components\libc\compilers\common\unistd.c + + + + + Libraries + + + stm32f7xx_hal.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c + + + stm32f7xx_hal_uart_ex.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c + + + stm32f7xx_hal_pwr.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c + + + stm32f7xx_hal_sram.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_sram.c + + + stm32f7xx_hal_rcc_ex.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c + + + stm32f7xx_hal_crc.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_crc.c + + + stm32f7xx_hal_spi_ex.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_spi_ex.c + + + stm32f7xx_hal_usart.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_usart.c + + + stm32f7xx_hal_rcc.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c + + + stm32f7xx_hal_cec.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cec.c + + + stm32f7xx_hal_cryp.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cryp.c + + + stm32f7xx_hal_gpio.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c + + + stm32f7xx_hal_exti.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c + + + stm32f7xx_hal_cryp_ex.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cryp_ex.c + + + stm32f7xx_hal_dma_ex.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c + + + stm32f7xx_hal_qspi.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_qspi.c + + + stm32f7xx_hal_cortex.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c + + + stm32f7xx_hal_dma.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c + + + stm32f7xx_hal_spi.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_spi.c + + + system_stm32f7xx.c + 1 + libraries\STM32F7xx_HAL\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c + + + stm32f7xx_hal_uart.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c + + + stm32f7xx_hal_pwr_ex.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c + + + stm32f7xx_hal_rng.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rng.c + + + stm32f7xx_hal_crc_ex.c + 1 + libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_crc_ex.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f746-st-nucleo/rtconfig.h b/bsp/stm32/stm32f746-st-nucleo/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..67ccd7cd227baa9cc2de622cf026840197dc13e2 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/rtconfig.h @@ -0,0 +1,282 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +/* end of kservice optimization */ +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP +/* end of Memory Management */ + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart3" +/* end of Kernel Device Object */ +#define RT_VER_NUM 0x40004 +/* end of RT-Thread Kernel */ +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* end of C++ features */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 +/* end of Command shell */ + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS +/* end of Device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_RTC +#define RT_USING_SOFT_RTC +#define RT_USING_SPI + +/* Using USB */ + +/* end of Using USB */ +/* end of Device Drivers */ + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 +/* end of POSIX layer and C standard library */ + +/* Network */ + +/* Socket abstraction layer */ + +/* end of Socket abstraction layer */ + +/* Network interface device */ + +#define NETDEV_USING_PING +/* end of Network interface device */ + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_LWIP_MEM_ALIGNMENT 4 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +/* end of Static IPv4 Address */ +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +/* end of light weight TCP/IP stack */ + +/* AT commands */ + +/* end of AT commands */ +/* end of Network */ + +/* VBUS(Virtual Software BUS) */ + +/* end of VBUS(Virtual Software BUS) */ + +/* Utilities */ + +/* end of Utilities */ +/* end of RT-Thread Components */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* end of language packages */ + +/* multimedia packages */ + +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F7 + +/* Hardware Drivers Config */ + +#define SOC_STM32F746ZG + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_USART +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART3 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/stm32/stm32f746-st-nucleo/rtconfig.py b/bsp/stm32/stm32f746-st-nucleo/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..7402431d44cee1f7404e74ac034593fa5bb17978 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/rtconfig.py @@ -0,0 +1,157 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/usr/local/Cellar/arm-none-eabi-gcc/7-2017-q4-major/gcc/bin/' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2 -Os' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp --fpu=FPv4-SP' + CFLAGS = DEVICE + ' --apcs=interwork ' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC' + LFLAGS += ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib"' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2 -Otime' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + CFLAGS += ' --silent' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + LFLAGS = ' --config rtthread.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + LFLAGS += ' --silent' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f746-st-nucleo/rtconfig_preinc.h b/bsp/stm32/stm32f746-st-nucleo/rtconfig_preinc.h new file mode 100644 index 0000000000000000000000000000000000000000..5e99c383c024e82bba2ce7cf333fe6d5f6782677 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/rtconfig_preinc.h @@ -0,0 +1,14 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define HAVE_CCONFIG_H +#define RT_USING_NEWLIB +#define STM32F746xx +#define USE_HAL_DRIVER +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/stm32/stm32f746-st-nucleo/template.ewp b/bsp/stm32/stm32f746-st-nucleo/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..06c31aca44f26950e848e7d2d3f67cd7bd2ea445 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/template.ewp @@ -0,0 +1,2074 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32f746-st-nucleo/template.eww b/bsp/stm32/stm32f746-st-nucleo/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..c62178f07a5e15c70d24add2b6f369e079d7a335 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f746-st-nucleo/template.uvoptx b/bsp/stm32/stm32f746-st-nucleo/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..a0e01e59f9e1e0dc1b8ee24e60a754e0075a4ad3 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/template.uvoptx @@ -0,0 +1,192 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC1000 -FD20010000 -FF0STM32F7x_1024 -FF1STM32F7xTCM_1024 -FL0100000 -FL1100000 -FS08000000 -FS1200000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC1000 -FD20010000 -FF0STM32F7x_1024 -FF1STM32F7xTCM_1024 -FL0100000 -FL1100000 -FS08000000 -FS1200000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f746-st-nucleo/template.uvprojx b/bsp/stm32/stm32f746-st-nucleo/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..6eca7bfbde4282ae08dafe7c1b7ee8bb6bdb7c93 --- /dev/null +++ b/bsp/stm32/stm32f746-st-nucleo/template.uvprojx @@ -0,0 +1,411 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F746ZGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.14.0 + http://www.keil.com/pack/ + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + 0 + $$Device:STM32F746ZGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746ZGTx$CMSIS\SVD\STM32F746.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/thead-smart/README.md b/bsp/thead-smart/README.md index c65180f26b6f544050be13b41aae9ad4d3447f24..c9c293fbbaaea0b9a4e4fa49f7cc10885f0b873b 100644 --- a/bsp/thead-smart/README.md +++ b/bsp/thead-smart/README.md @@ -3,7 +3,7 @@ SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide im ## The main resources on board are as follows: -1. SMART-EVB for E906/E906F/E906FD +1. SMART-EVB for T-Head CPU E9xx Series | res | description | | -- | -- | @@ -25,15 +25,21 @@ SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide im # Compile T-HEAD BSP SMART-EVB BSP supports GCC compiler, the version information is: - -1. SMART-EVB for E906/E906F/E906FD +1. SMART-EVB for E906/7/F/D/P | IDE/Compiler| version| | - | - | | GCC | gcc version 8.4.0 (C-SKY RISCV Tools V1.9.6 B20200616) | +2. select cpu in rtconfig.py +3. scons -c; scons -# run smart-evb bsp +# Quick start with qemu +1. download qemu +wget https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource/1356021/1612269502091/csky-qemu-x86_64-Ubuntu-16.04-20210202-1445.tar.gz +2. qemu run +qemu-system-riscv32 -cpu e906fdp -M smartl -kernel rtthread-e9xx.elf -nographic +# Quick start with smart-evb 1. Connect JTAG 2. Connect the serial port 3. riscv64-unknown-elf-gdb rtthread-e906f.elf diff --git a/bsp/thead-smart/drivers/board.c b/bsp/thead-smart/drivers/board.c index fab927858744547dca0627ff6c60b92db139310f..54a7f3c292c826423b9e10832e1572d605b20a17 100644 --- a/bsp/thead-smart/drivers/board.c +++ b/bsp/thead-smart/drivers/board.c @@ -23,7 +23,7 @@ extern int __bss_end__; extern usart_handle_t console_handle; extern void ioreuse_initial(void); - +extern int rt_hw_usart_init(void); /** * This function will initial smart-evb board. diff --git a/bsp/thead-smart/drivers/csi_config.h b/bsp/thead-smart/drivers/csi_config.h index 75185caff487ee3718bf8d451377094c41b86b5d..7e7eaf00613fe0bf3729d1073144fc1e1dc4500c 100644 --- a/bsp/thead-smart/drivers/csi_config.h +++ b/bsp/thead-smart/drivers/csi_config.h @@ -13,12 +13,7 @@ #ifndef __CSI_CONFIG_H #define __CSI_CONFIG_H -#define CONFIG_ARCH_RV32 1 -#define CONFIG_CPU_E906FD 1 -#define CONFIG_RV32_CORETIM 1 -#define CONFIG_CHIP_SMARTL_RV32 1 -#define CONFIG_BOARD_SMARTL_E906_EVB 1 -#define CONFIG_BOARD_NAME_STR "smartl_e906_evb" +#define CONFIG_BOARD_NAME_STR "smart_e906_evb" #define CONFIG_SUPPORT_TSPEND 1 #define CONFIG_ARCH_INTERRUPTSTACK 4096 #define CONFIG_NEWLIB_WRAP 1 diff --git a/bsp/thead-smart/drivers/system.c b/bsp/thead-smart/drivers/system.c index f860d9fee5141967d3e35c7160b0a09938ac8724..0822361cbe8086bde877d26d2377da52d431adf8 100644 --- a/bsp/thead-smart/drivers/system.c +++ b/bsp/thead-smart/drivers/system.c @@ -65,7 +65,10 @@ void systemmap_config(void) void SystemInit(void) { int i; +#if ((CONFIG_CPU_E902 != 1) && (CONFIG_CPU_E902M != 1)) systemmap_config(); +#endif + /* enable mstatus FS */ #if (__riscv_flen) uint32_t mstatus = __get_MSTATUS(); diff --git a/bsp/thead-smart/gdbinit b/bsp/thead-smart/gdbinit index aed74eaa1dd641feb0a302834b027929df3048b8..5fa9b1b9ae9a8e1b6d663ff929ce6b8a5f8a8a6c 100644 --- a/bsp/thead-smart/gdbinit +++ b/bsp/thead-smart/gdbinit @@ -6,6 +6,9 @@ set *(int *)0x40011008=0x0 set *(int *)0x4001101c=0x0 set disassemble-next-line on show disassemble-next-line + +hb Default_Handler lo +c diff --git a/bsp/thead-smart/rtconfig.h b/bsp/thead-smart/rtconfig.h index 1f34e30fbe1ba0819702f920ff6ec137df837b9b..40b7ab9b77a7a5a65989dbd78e9162b2468e5e10 100644 --- a/bsp/thead-smart/rtconfig.h +++ b/bsp/thead-smart/rtconfig.h @@ -38,20 +38,6 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40003 -#define ARCH_RISCV -#define ARCH_RISCV32 -#if(__riscv_flen == 64) -#define ARCH_RISCV_FPU -#define ARCH_RISCV_FPU_D -#elif(__riscv_flen == 32) -#define ARCH_RISCV_FPU -#define ARCH_RISCV_FPU_S -#else -#endif -#ifdef __riscv_zp64 -#define ARCH_RISCV_DSP -#endif - /* RT-Thread Components */ diff --git a/bsp/thead-smart/rtconfig.py b/bsp/thead-smart/rtconfig.py index 95606581c862c77cac35c5309a9c999073abbf77..033a54f0e33dd6fce062b94fcba1b88a87b5a016 100644 --- a/bsp/thead-smart/rtconfig.py +++ b/bsp/thead-smart/rtconfig.py @@ -67,11 +67,5 @@ if PLATFORM == 'gcc': CXXFLAGS = CFLAGS -# M_CFLAGS = DEVICE + ' -EL -G0 -O2 -mno-abicalls -fno-common -fno-exceptions -fno-omit-frame-pointer -mlong-calls -fno-pic ' - # M_CXXFLAGS = M_CFLAGS - # M_LFLAGS = DEVICE + ' -EL -r -Wl,--gc-sections,-z,max-page-size=0x4' +\ - # ' -nostartfiles -static-libgcc' - # M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' - DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/thead-smart/theadconfig.h b/bsp/thead-smart/theadconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..071bc8dbe23187ee26b7a6bc2552797bb7a09a23 --- /dev/null +++ b/bsp/thead-smart/theadconfig.h @@ -0,0 +1,24 @@ +#ifndef THEAD_CONFIG_H__ +#define THAED_CONFIG_H__ + +#define ARCH_RISCV +#define ARCH_RISCV32 +#if(__riscv_flen == 64) +#define ARCH_RISCV_FPU +#define ARCH_RISCV_FPU_D +#elif(__riscv_flen == 32) +#define ARCH_RISCV_FPU +#define ARCH_RISCV_FPU_S +#else +#endif +#ifdef __riscv_zp64 +#define ARCH_RISCV_DSP +#endif + +#ifdef __riscv_xthead +#ifdef __riscv_xtheade +#define CONFIG_THEAD_EXT_SPUSHEN +#endif +#endif + +#endif diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c index 9bbcc440cf3d6920614807170f22c65f9e0d426b..5f0bbb6d59e7deaf868127180e4023b11ebe536e 100644 --- a/components/finsh/cmd.c +++ b/components/finsh/cmd.c @@ -810,6 +810,7 @@ static char *const device_type_str[] = "I2C Bus", "USB Slave Device", "USB Host Bus", + "USB OTG Bus", "SPI Bus", "SPI Device", "SDIO Bus", diff --git a/examples/utest/configs/kernel/ipc.conf b/examples/utest/configs/kernel/ipc.conf new file mode 100644 index 0000000000000000000000000000000000000000..0dcb6bd052fedfcc6c6a729d4e2d1236088e2c78 --- /dev/null +++ b/examples/utest/configs/kernel/ipc.conf @@ -0,0 +1,4 @@ +CONFIG_UTEST_SEMAPHORE_TC=y + +# dependencies +CONFIG_RT_USING_SEMAPHORE=y diff --git a/examples/utest/testcases/kernel/Kconfig b/examples/utest/testcases/kernel/Kconfig index 14334af16ffe9c2e5fa953cf274d80732e92a9d1..97464ecd8a5b9d2b5fdfe30d8cb7e7811c1cbb39 100644 --- a/examples/utest/testcases/kernel/Kconfig +++ b/examples/utest/testcases/kernel/Kconfig @@ -5,4 +5,9 @@ config UTEST_MEMHEAP_TC default y depends on RT_USING_MEMHEAP +config UTEST_SEMAPHORE_TC + bool "semaphore test" + default n + depends on RT_USING_SEMAPHORE + endmenu diff --git a/examples/utest/testcases/kernel/SConscript b/examples/utest/testcases/kernel/SConscript index 9411cdd9a074a6e8e1a7f5454d117f331125233d..ad6c959f4cb770b47a91afa7da08581e4eaa5457 100644 --- a/examples/utest/testcases/kernel/SConscript +++ b/examples/utest/testcases/kernel/SConscript @@ -8,6 +8,9 @@ src = Split(''' if GetDepend(['UTEST_MEMHEAP_TC']): src += ['memheap_tc.c'] +if GetDepend(['UTEST_SEMAPHORE_TC']): + src += ['semaphore_tc.c'] + CPPPATH = [cwd] group = DefineGroup('utestcases', src, depend = [], CPPPATH = CPPPATH) diff --git a/examples/utest/testcases/kernel/semaphore_tc.c b/examples/utest/testcases/kernel/semaphore_tc.c new file mode 100644 index 0000000000000000000000000000000000000000..2992831d873cffe553dfa176acdb33c257463fc4 --- /dev/null +++ b/examples/utest/testcases/kernel/semaphore_tc.c @@ -0,0 +1,559 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-12 luckyzjq the first version + */ + +#include +#include +#include "utest.h" + +static struct rt_semaphore static_semaphore; +#ifdef RT_USING_HEAP +static rt_sem_t dynamic_semaphore; +#endif /* RT_USING_HEAP */ + +static void test_static_semaphore_init(void) +{ + rt_err_t result; + int rand_num = rand() % 0x10000; + + for (int i = 0; i < rand_num; i++) + { + result = rt_sem_init(&static_semaphore, "static_sem", i, RT_IPC_FLAG_PRIO); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + break; + } + rt_sem_detach(&static_semaphore); + + result = rt_sem_init(&static_semaphore, "static_sem", i, RT_IPC_FLAG_FIFO); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + break; + } + rt_sem_detach(&static_semaphore); + } + + uassert_true(RT_TRUE); +} + +static void test_static_semaphore_detach(void) +{ + rt_err_t result; + int rand_num = rand() % 0x10000; + + for (int i = 0; i < rand_num; i++) + { + result = rt_sem_init(&static_semaphore, "static_sem", i, RT_IPC_FLAG_PRIO); + if (RT_EOK != result) + { + break; + } + + result = rt_sem_detach(&static_semaphore); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + break; + } + + result = rt_sem_init(&static_semaphore, "static_sem", i, RT_IPC_FLAG_FIFO); + if (RT_EOK != result) + { + break; + } + result = rt_sem_detach(&static_semaphore); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + break; + } + } + + uassert_true(RT_TRUE); +} + +static void test_static_semaphore_take(void) +{ + rt_err_t result; + result = rt_sem_init(&static_semaphore, "static_sem", 1, RT_IPC_FLAG_PRIO); + if (RT_EOK == result) + { + /* first take */ + result = rt_sem_take(&static_semaphore, RT_WAITING_FOREVER); + if (RT_EOK != result) + uassert_true(RT_FALSE); + /* second take */ + result = rt_sem_take(&static_semaphore, 100); + if (-RT_ETIMEOUT != result) + uassert_true(RT_FALSE); + } + else + { + return; + } + + rt_sem_detach(&static_semaphore); + uassert_true(RT_TRUE); + + return; +} + +static void test_static_semaphore_trytake(void) +{ + rt_err_t result; + result = rt_sem_init(&static_semaphore, "static_sem", 1, RT_IPC_FLAG_PRIO); + if (RT_EOK == result) + { + /* first take */ + result = rt_sem_trytake(&static_semaphore); + if (RT_EOK != result) + uassert_true(RT_FALSE); + /* second take */ + result = rt_sem_trytake(&static_semaphore); + if (-RT_ETIMEOUT != result) + uassert_true(RT_FALSE); + } + else + { + return; + } + + rt_sem_detach(&static_semaphore); + uassert_true(RT_TRUE); + + return; +} + +static void test_static_semaphore_release(void) +{ + rt_err_t result; + result = rt_sem_init(&static_semaphore, "static_sem", 0, RT_IPC_FLAG_PRIO); + if (RT_EOK == result) + { + /* first take */ + result = rt_sem_take(&static_semaphore, 100); + if (-RT_ETIMEOUT != result) + uassert_true(RT_FALSE); + + /* release */ + result = rt_sem_release(&static_semaphore); + if (RT_EOK != result) + uassert_true(RT_FALSE); + + /* second take */ + result = rt_sem_take(&static_semaphore, RT_WAITING_FOREVER); + if (RT_EOK != result) + uassert_true(RT_FALSE); + } + else + { + return; + } + + rt_sem_detach(&static_semaphore); + uassert_true(RT_TRUE); + + return; +} + +static void test_static_semaphore_control(void) +{ + rt_err_t result; + int value = 0; + + value = rand() % 100; + result = rt_sem_init(&static_semaphore, "static_sem", 1, RT_IPC_FLAG_PRIO); + if (RT_EOK == result) + { + result = rt_sem_control(&static_semaphore, RT_IPC_CMD_RESET, &value); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } + } + else + { + return; + } + + for (int i = 0; i < value; i++) + { + result = rt_sem_take(&static_semaphore, 10); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } + } + + rt_sem_detach(&static_semaphore); + uassert_true(RT_TRUE); +} + +static void static_release_isr_hardware_callback(void *param) +{ + rt_err_t result; + + result = rt_sem_release(&static_semaphore); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } +} + +static void static_release_isr_software_callback(void *param) +{ + rt_err_t result; + + result = rt_sem_release(&static_semaphore); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } +} + +static void test_static_semaphore_release_isr(void) +{ + rt_err_t result; + rt_timer_t hardware_timer; + rt_timer_t software_timer; + + /* create timer */ + hardware_timer = rt_timer_create("release_isr", + static_release_isr_hardware_callback, + RT_NULL, + 100, + RT_TIMER_FLAG_HARD_TIMER | RT_TIMER_FLAG_ONE_SHOT); + software_timer = rt_timer_create("release_isr", + static_release_isr_software_callback, + RT_NULL, + 100, + RT_TIMER_FLAG_SOFT_TIMER | RT_TIMER_FLAG_ONE_SHOT); + /* start tiemr */ + if (hardware_timer) + rt_timer_start(hardware_timer); + if (software_timer) + rt_timer_start(software_timer); + + result = rt_sem_init(&static_semaphore, "static_sem", 0, RT_IPC_FLAG_PRIO); + if (RT_EOK == result) + { + for (int i = 0; i < 2; i++) + { + result = rt_sem_take(&static_semaphore, 1000); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } + } + } + else + { + return; + } + + rt_sem_detach(&static_semaphore); + rt_timer_delete(hardware_timer); + rt_timer_delete(software_timer); + + uassert_true(RT_TRUE); +} + +#ifdef RT_USING_HEAP +static void test_dynamic_semaphore_create(void) +{ + rt_err_t result; + int rand_num = rand() % 0x10000; + + for (int i = 0; i < rand_num; i++) + { + dynamic_semaphore = rt_sem_create("static_sem", i, RT_IPC_FLAG_PRIO); + if (RT_NULL == dynamic_semaphore) + { + uassert_true(RT_FALSE); + break; + } + rt_sem_delete(dynamic_semaphore); + + dynamic_semaphore = rt_sem_create("static_sem", i, RT_IPC_FLAG_FIFO); + if (RT_NULL == dynamic_semaphore) + { + uassert_true(RT_FALSE); + break; + } + rt_sem_delete(dynamic_semaphore); + } + + uassert_true(RT_TRUE); +} + +static void test_dynamic_semaphore_delete(void) +{ + rt_err_t result; + int rand_num = rand() % 0x10000; + + for (int i = 0; i < rand_num; i++) + { + dynamic_semaphore = rt_sem_create("static_sem", i, RT_IPC_FLAG_PRIO); + if (RT_NULL == dynamic_semaphore) + { + break; + } + + result = rt_sem_delete(dynamic_semaphore); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + break; + } + + dynamic_semaphore = rt_sem_create("static_sem", i, RT_IPC_FLAG_FIFO); + if (RT_NULL == dynamic_semaphore) + { + break; + } + result = rt_sem_delete(dynamic_semaphore); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + break; + } + } + + uassert_true(RT_TRUE); +} + +static void test_dynamic_semaphore_take(void) +{ + rt_err_t result; + dynamic_semaphore = rt_sem_create("static_sem", 1, RT_IPC_FLAG_PRIO); + if (RT_NULL != dynamic_semaphore) + { + /* first take */ + result = rt_sem_take(dynamic_semaphore, RT_WAITING_FOREVER); + if (RT_EOK != result) + uassert_true(RT_FALSE); + /* second take */ + result = rt_sem_take(dynamic_semaphore, 100); + if (-RT_ETIMEOUT != result) + uassert_true(RT_FALSE); + } + else + { + return; + } + + rt_sem_delete(dynamic_semaphore); + uassert_true(RT_TRUE); + + return; +} + +static void test_dynamic_semaphore_trytake(void) +{ + rt_err_t result; + dynamic_semaphore = rt_sem_create("static_sem", 1, RT_IPC_FLAG_PRIO); + if (RT_NULL != dynamic_semaphore) + { + /* first take */ + result = rt_sem_trytake(dynamic_semaphore); + if (RT_EOK != result) + uassert_true(RT_FALSE); + /* second take */ + result = rt_sem_trytake(dynamic_semaphore); + if (-RT_ETIMEOUT != result) + uassert_true(RT_FALSE); + } + else + { + return; + } + + rt_sem_delete(dynamic_semaphore); + uassert_true(RT_TRUE); + + return; +} + +static void test_dynamic_semaphore_release(void) +{ + rt_err_t result; + dynamic_semaphore = rt_sem_create("static_sem", 0, RT_IPC_FLAG_PRIO); + if (RT_NULL != dynamic_semaphore) + { + /* first take */ + result = rt_sem_take(dynamic_semaphore, 100); + if (-RT_ETIMEOUT != result) + uassert_true(RT_FALSE); + + /* release */ + result = rt_sem_release(dynamic_semaphore); + if (RT_EOK != result) + uassert_true(RT_FALSE); + + /* second take */ + result = rt_sem_take(dynamic_semaphore, RT_WAITING_FOREVER); + if (RT_EOK != result) + uassert_true(RT_FALSE); + } + else + { + return; + } + + rt_sem_delete(dynamic_semaphore); + uassert_true(RT_TRUE); + + return; +} + +static void test_dynamic_semaphore_control(void) +{ + rt_err_t result; + int value = 0; + + value = rand() % 100; + dynamic_semaphore = rt_sem_create("static_sem", 1, RT_IPC_FLAG_PRIO); + if (RT_NULL != dynamic_semaphore) + { + result = rt_sem_control(dynamic_semaphore, RT_IPC_CMD_RESET, &value); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } + } + else + { + return; + } + + for (int i = 0; i < value; i++) + { + result = rt_sem_take(dynamic_semaphore, 10); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } + } + + rt_sem_delete(dynamic_semaphore); + uassert_true(RT_TRUE); +} + +static void dynamic_release_isr_hardware_callback(void *param) +{ + rt_err_t result; + + result = rt_sem_release(dynamic_semaphore); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } +} + +static void dynamic_release_isr_software_callback(void *param) +{ + rt_err_t result; + + result = rt_sem_release(dynamic_semaphore); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } +} + +static void test_dynamic_semaphore_release_isr(void) +{ + rt_err_t result; + rt_timer_t hardware_timer; + rt_timer_t software_timer; + + /* create timer */ + hardware_timer = rt_timer_create("release_isr", + dynamic_release_isr_hardware_callback, + RT_NULL, + 100, + RT_TIMER_FLAG_HARD_TIMER | RT_TIMER_FLAG_ONE_SHOT); + software_timer = rt_timer_create("release_isr", + dynamic_release_isr_software_callback, + RT_NULL, + 100, + RT_TIMER_FLAG_SOFT_TIMER | RT_TIMER_FLAG_ONE_SHOT); + /* start tiemr */ + if (hardware_timer) + rt_timer_start(hardware_timer); + if (software_timer) + rt_timer_start(software_timer); + + dynamic_semaphore = rt_sem_create("static_sem", 0, RT_IPC_FLAG_PRIO); + if (RT_NULL != dynamic_semaphore) + { + for (int i = 0; i < 2; i++) + { + result = rt_sem_take(dynamic_semaphore, 1000); + if (RT_EOK != result) + { + uassert_true(RT_FALSE); + } + } + } + else + { + return; + } + + rt_sem_delete(dynamic_semaphore); + rt_timer_delete(hardware_timer); + rt_timer_delete(software_timer); + + uassert_true(RT_TRUE); +} + +#endif /* RT_USING_HEAP */ + +static rt_err_t utest_tc_init(void) +{ +#ifdef RT_USING_HEAP + dynamic_semaphore = RT_NULL; +#endif /* RT_USING_HEAP */ + + return RT_EOK; +} + +static rt_err_t utest_tc_cleanup(void) +{ +#ifdef RT_USING_HEAP + dynamic_semaphore = RT_NULL; +#endif /* RT_USING_HEAP */ + + return RT_EOK; +} + +static void testcase(void) +{ + UTEST_UNIT_RUN(test_static_semaphore_init); + UTEST_UNIT_RUN(test_static_semaphore_take); + UTEST_UNIT_RUN(test_static_semaphore_release); + UTEST_UNIT_RUN(test_static_semaphore_detach); + UTEST_UNIT_RUN(test_static_semaphore_trytake); + UTEST_UNIT_RUN(test_static_semaphore_control); + UTEST_UNIT_RUN(test_static_semaphore_release_isr); + +#ifdef RT_USING_HEAP + UTEST_UNIT_RUN(test_dynamic_semaphore_create); + UTEST_UNIT_RUN(test_dynamic_semaphore_take); + UTEST_UNIT_RUN(test_dynamic_semaphore_release); + UTEST_UNIT_RUN(test_dynamic_semaphore_delete); + UTEST_UNIT_RUN(test_dynamic_semaphore_trytake); + UTEST_UNIT_RUN(test_dynamic_semaphore_control); + UTEST_UNIT_RUN(test_dynamic_semaphore_release_isr); +#endif /* RT_USING_HEAP */ +} +UTEST_TC_EXPORT(testcase, "testcases.kernel.semaphore_tc", utest_tc_init, utest_tc_cleanup, 1000); diff --git a/libcpu/risc-v/t-head/e9xx/context_gcc.S b/libcpu/risc-v/t-head/e9xx/context_gcc.S index 9deaf80e41356b44de9cfbb2d91512617deaa116..b6adb65ff7cd7642b71a9d20aacb3b568a1317ba 100644 --- a/libcpu/risc-v/t-head/e9xx/context_gcc.S +++ b/libcpu/risc-v/t-head/e9xx/context_gcc.S @@ -1,11 +1,13 @@ /* * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2021, Alibaba Group Holding Limited * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting implementation + * 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code. */ #include "cpuport.h" @@ -29,8 +31,6 @@ vPortYield: ret - - /* * #ifdef RT_USING_SMP * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread); @@ -56,12 +56,10 @@ rt_hw_context_switch_to: li t1, 1 STORE t1, (t0) - /* enable mexstatus SPUSHEN and SPSWAPEN */ -#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1)) - uint32_t mexstatus; - mexstatus = __get_MEXSTATUS(); - mexstatus |= (0x2 << 16); - __set_MEXSTATUS(mexstatus); + /* enable mexstatus SPUSHEN */ +#ifdef CONFIG_THEAD_EXT_SPUSHEN + li t0, 0x10000 + csrs mexstatus, t0 #endif csrw mscratch, sp @@ -140,7 +138,7 @@ PendSV_Handler: lw t1, (t0) beqz t1, .switch_to_thead - /* save from thread context */ + /* restore from thread context t0,t1 */ lw t0, (-4)(sp) lw t1, (-8)(sp) @@ -191,10 +189,6 @@ PendSV_Handler: csrr x1, mepc STORE x1, 0 * REGBYTES(sp) csrr x1, mstatus - andi x1, x1, 8 - beqz x1, .save_mpie - li x1, 0x80 -.save_mpie: STORE x1, 2 * REGBYTES(sp) /* x3 don't need save */ STORE x4, 4 * REGBYTES(sp) @@ -256,11 +250,9 @@ PendSV_Handler: csrw mepc, a1 LOAD x1, 1 * REGBYTES(sp) - /* force to machin mode(MPP=11) */ - li a1, 0x1880 - csrs mstatus, a1 + /* force to machine mode(MPP=11) */ LOAD a1, 2 * REGBYTES(sp) - csrs mstatus, a1 + csrw mstatus, a1 /* x3 don't need restore */ LOAD x4, 4 * REGBYTES(sp) LOAD x5, 5 * REGBYTES(sp) diff --git a/libcpu/risc-v/t-head/e9xx/cpuport.c b/libcpu/risc-v/t-head/e9xx/cpuport.c index 6fa41b6da68620591d58e54879a59e84c63e5b75..e93dd67dc3ccdc3047053ceb2259903e71f670c2 100644 --- a/libcpu/risc-v/t-head/e9xx/cpuport.c +++ b/libcpu/risc-v/t-head/e9xx/cpuport.c @@ -1,11 +1,13 @@ /* * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2021, Alibaba Group Holding Limited * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting code. + * 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code. */ #include @@ -143,8 +145,8 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, rt_base_t rt_hw_interrupt_disable(void) { - __asm volatile("csrc mstatus, 8"); - return 0; + __asm volatile("csrrci a0, mstatus, 8"); + return; } /** @@ -154,9 +156,10 @@ rt_base_t rt_hw_interrupt_disable(void) * * @return none */ +/* XXX:rename rt_hw_interrupt_restore? */ void rt_hw_interrupt_enable(rt_base_t level) { - __asm volatile("csrs mstatus, 8"); + __asm volatile("csrw mstatus, a0"); } /** shutdown CPU */ diff --git a/libcpu/risc-v/t-head/e9xx/cpuport.h b/libcpu/risc-v/t-head/e9xx/cpuport.h index 20302f44aa18ea723b34753e9c33dcc7da79e6ef..4f01d2127c37487946b82bbda812d1f5cda8d3c9 100644 --- a/libcpu/risc-v/t-head/e9xx/cpuport.h +++ b/libcpu/risc-v/t-head/e9xx/cpuport.h @@ -12,6 +12,7 @@ #define CPUPORT_H__ #include +#include /* bytes of register width */ #ifdef ARCH_RISCV_64 diff --git a/src/irq.c b/src/irq.c index 6ddcb3dd4ae6a4bbbc98a874528c38f15312fc83..40c2aa5305e9dd18a481926682331895e235de68 100644 --- a/src/irq.c +++ b/src/irq.c @@ -9,6 +9,7 @@ * 2006-05-03 Bernard add IRQ_DEBUG * 2016-08-09 ArdaFu add interrupt enter and leave hook. * 2018-11-22 Jesven rt_interrupt_get_nest function add disable irq + * 2021-08-15 Supperthomas fix the comment */ #include @@ -21,19 +22,26 @@ static void (*rt_interrupt_leave_hook)(void); /** * @ingroup Hook - * This function set a hook function when the system enter a interrupt + * + * @brief This function set a hook function when the system enter a interrupt * * @note the hook function must be simple and never be blocked or suspend. + * + * @param hook The function point to be called */ void rt_interrupt_enter_sethook(void (*hook)(void)) { rt_interrupt_enter_hook = hook; } + /** * @ingroup Hook - * This function set a hook function when the system exit a interrupt. + * + * @brief This function set a hook function when the system exit a interrupt. * * @note the hook function must be simple and never be blocked or suspend. + * + * @param hook The function point to be called */ void rt_interrupt_leave_sethook(void (*hook)(void)) { @@ -53,8 +61,9 @@ void rt_interrupt_leave_sethook(void (*hook)(void)) volatile rt_uint8_t rt_interrupt_nest = 0; #endif /* RT_USING_SMP */ + /** - * This function will be invoked by BSP, when enter interrupt service routine + * @brief This function will be invoked by BSP, when enter interrupt service routine * * @note please don't invoke this routine in application * @@ -74,8 +83,9 @@ void rt_interrupt_enter(void) } RTM_EXPORT(rt_interrupt_enter); + /** - * This function will be invoked by BSP, when leave interrupt service routine + * @brief This function will be invoked by BSP, when leave interrupt service routine * * @note please don't invoke this routine in application * @@ -95,13 +105,14 @@ void rt_interrupt_leave(void) } RTM_EXPORT(rt_interrupt_leave); + /** - * This function will return the nest of interrupt. + * @brief This function will return the nest of interrupt. * * User application can invoke this function to get whether current * context is interrupt context. * - * @return the number of nested interrupts. + * @return rt_uint8_t the number of nested interrupts. */ RT_WEAK rt_uint8_t rt_interrupt_get_nest(void) { diff --git a/src/timer.c b/src/timer.c index 1c8e70fccc6e8725d47cbd586f93b8d0cc6b03c8..44d0d4a7cc792345dd08117c418600fe2ee2bf92 100644 --- a/src/timer.c +++ b/src/timer.c @@ -16,6 +16,7 @@ * 2012-12-15 Bernard fix the next timeout issue in soft timer * 2014-07-12 Bernard does not lock scheduler when invoking soft-timer * timeout function. + * 2021-08-15 supperthomas add the comment */ #include @@ -59,10 +60,10 @@ static void (*rt_timer_exit_hook)(struct rt_timer *timer); /**@{*/ /** - * This function will set a hook function, which will be invoked when enter - * timer timeout callback function. + * @brief This function will set a hook function on timer, + * which will be invoked when enter timer timeout callback function. * - * @param hook the hook function + * @param hook the function point of timer */ void rt_timer_enter_sethook(void (*hook)(struct rt_timer *timer)) { @@ -70,10 +71,10 @@ void rt_timer_enter_sethook(void (*hook)(struct rt_timer *timer)) } /** - * This function will set a hook function, which will be invoked when exit - * timer timeout callback function. + * @brief This function will set a hook function, which will be + * invoked when exit * timer timeout callback function. * - * @param hook the hook function + * @param hook the function point of timer */ void rt_timer_exit_sethook(void (*hook)(struct rt_timer *timer)) { @@ -83,6 +84,20 @@ void rt_timer_exit_sethook(void (*hook)(struct rt_timer *timer)) /**@}*/ #endif /* RT_USING_HOOK */ + +/** + * @brief [internal] the init funtion of timer + * + * the internal called function of rt_timer_init + * + * @see rt_timer_init + * + * @param timer the static timer object + * @param timeout the timeout function + * @param parameter the parameter of timeout function + * @param time the tick of timer + * @param flag the flag of timer + */ static void _rt_timer_init(rt_timer_t timer, void (*timeout)(void *parameter), void *parameter, @@ -110,7 +125,13 @@ static void _rt_timer_init(rt_timer_t timer, } } -/* the fist timer always in the last row */ +/** + * @brief find the next emtpy timer + * + * @param timer_list the timer of the next timeout + * + * @return rt_tick_t the point of timer + */ static rt_tick_t rt_timer_list_next_timeout(rt_list_t timer_list[]) { struct rt_timer *timer; @@ -133,6 +154,11 @@ static rt_tick_t rt_timer_list_next_timeout(rt_list_t timer_list[]) return timeout_tick; } +/** + * @brief remove the timer + * + * @param timer the point of timer + */ rt_inline void _rt_timer_remove(rt_timer_t timer) { int i; @@ -144,6 +170,12 @@ rt_inline void _rt_timer_remove(rt_timer_t timer) } #if RT_DEBUG_TIMER +/** + * @brief the number of timer + * + * @param timer + * @return int the count + */ static int rt_timer_count_height(struct rt_timer *timer) { int i, cnt = 0; @@ -155,7 +187,11 @@ static int rt_timer_count_height(struct rt_timer *timer) } return cnt; } - +/** + * @brief dump the all timer information + * + * @param timer_heads the head of timer + */ void rt_timer_dump(rt_list_t timer_heads[]) { rt_list_t *list; @@ -180,9 +216,8 @@ void rt_timer_dump(rt_list_t timer_heads[]) /**@{*/ /** - * This function will initialize a timer, normally this function is used to - * initialize a static timer object. - * + * @brief This function will initialize a timer + * normally this function is used to initialize a static timer object. * @param timer the static timer object * @param name the name of timer * @param timeout the timeout function @@ -208,11 +243,10 @@ void rt_timer_init(rt_timer_t timer, RTM_EXPORT(rt_timer_init); /** - * This function will detach a timer from timer management. - * - * @param timer the static timer object + * @brief This function will detach a timer from timer management. * - * @return the operation status, RT_EOK on OK; RT_ERROR on error + * @param timer the timer to be detached + * @return rt_err_t RT_EOK */ rt_err_t rt_timer_detach(rt_timer_t timer) { @@ -241,7 +275,7 @@ RTM_EXPORT(rt_timer_detach); #ifdef RT_USING_HEAP /** - * This function will create a timer + * @brief This function will create a timer * * @param name the name of timer * @param timeout the timeout function @@ -273,7 +307,7 @@ rt_timer_t rt_timer_create(const char *name, RTM_EXPORT(rt_timer_create); /** - * This function will delete a timer and release timer memory + * @brief This function will delete a timer and release timer memory * * @param timer the timer to be deleted * @@ -306,7 +340,7 @@ RTM_EXPORT(rt_timer_delete); #endif /* RT_USING_HEAP */ /** - * This function will start the timer + * @brief This function will start the timer * * @param timer the timer to be started * @@ -429,7 +463,7 @@ rt_err_t rt_timer_start(rt_timer_t timer) RTM_EXPORT(rt_timer_start); /** - * This function will stop the timer + * @brief This function will stop the timer * * @param timer the timer to be stopped * @@ -463,7 +497,7 @@ rt_err_t rt_timer_stop(rt_timer_t timer) RTM_EXPORT(rt_timer_stop); /** - * This function will get or set some options of the timer + * @brief This function will get or set some options of the timer * * @param timer the timer to be get or set * @param cmd the control command @@ -521,8 +555,8 @@ rt_err_t rt_timer_control(rt_timer_t timer, int cmd, void *arg) RTM_EXPORT(rt_timer_control); /** - * This function will check timer list, if a timeout event happens, the - * corresponding timeout function will be invoked. + * @brief This function will check timer list, if a timeout event happens, + * the corresponding timeout function will be invoked. * * @note this function shall be invoked in operating system timer interrupt. */ @@ -596,7 +630,7 @@ void rt_timer_check(void) } /** - * This function will return the next timeout tick in the system. + * @brief This function will return the next timeout tick in the system. * * @return the next timeout tick in the system */ @@ -607,7 +641,7 @@ rt_tick_t rt_timer_next_timeout_tick(void) #ifdef RT_USING_TIMER_SOFT /** - * This function will check software-timer list, if a timeout event happens, the + * @brief This function will check software-timer list, if a timeout event happens, the * corresponding timeout function will be invoked. */ void rt_soft_timer_check(void) @@ -684,7 +718,11 @@ void rt_soft_timer_check(void) RT_DEBUG_LOG(RT_DEBUG_TIMER, ("software timer check leave\n")); } -/* system timer thread entry */ +/** + * @brief system timer thread entry + * + * @param parameter + */ static void rt_thread_timer_entry(void *parameter) { rt_tick_t next_timeout; @@ -723,7 +761,7 @@ static void rt_thread_timer_entry(void *parameter) /** * @ingroup SystemInit * - * This function will initialize system timer + * @brief This function will initialize system timer */ void rt_system_timer_init(void) { @@ -738,7 +776,7 @@ void rt_system_timer_init(void) /** * @ingroup SystemInit * - * This function will initialize system timer thread + * @brief This function will initialize system timer thread */ void rt_system_timer_thread_init(void) {