module uart_ctrl(
	input wClk,
	input nwReset,
	input wRead,
	input [31:0] bReadAddr,
	input wWrite, 
	input [31:0] bWriteAddr,
	input [31:0] bWriteData,
	output [31:0] bReadData,
	output uart_tx,
	input  uart_rx
	);

	wire [31:0] ctl_state;

	wire [7:0]  send_buf_data, send_buf_q;
	wire send_buf_full;
	wire send_buf_empty;
	wire [9:0] send_buf_used;
	reg send_buf_read;
	reg send_buf_write;
	assign send_buf_data = bWriteData[7:0];
	assign ctl_state[15:0] = {5'b0, send_buf_used, send_buf_full};

    uart_fifo uart_send_buf(
		.clock(wClk),
		.data(send_buf_data),
		.rdreq(send_buf_read),
		.wrreq(send_buf_write),
		.almost_full(send_buf_full),
		.empty(send_buf_empty),
		.full(),
		.q(send_buf_q),
		.usedw(send_buf_used));


	wire [7:0]  recv_buf_data, recv_buf_q;
	wire recv_buf_empty;
	wire recv_buf_full;
	wire [9:0] recv_buf_used;
	reg recv_buf_read;
	reg recv_buf_write;
	assign ctl_state[31:16] = {5'b0, recv_buf_used, recv_buf_empty};

    uart_fifo uart_recv_buf(
		.clock(wClk),
		.data(recv_buf_data),
		.rdreq(recv_buf_read),
		.wrreq(recv_buf_write),
		.almost_full(recv_buf_full),
		.empty(recv_buf_empty),
		.full(),
		.q(recv_buf_q),
		.usedw(recv_buf_used));

	reg [2:0] uartaddr;
	reg  uart_read, uart_write;
	reg  [15:0] uart_write_data;
	wire [15:0] uart_read_data;
	wire uart_has_data;
	wire uart_can_send;
	altera_uart uart(
                       // inputs:
                        .address(uartaddr),
                        .begintransfer(1'b1),
                        .chipselect(1'b1),
                        .clk(wClk),
                        .read_n(~uart_read),
                        .reset_n(nwReset),
                        .rxd(uart_rx),
                        .write_n(uart_write),
                        .writedata(uart_write_data),

                       // outputs:
                        .dataavailable(uart_has_data),
                        .irq(),
                        .readdata(uart_read_data),
                        .readyfordata(uart_can_send),
                        .txd(uart_tx)
                     );

	always @(posedge wClk)	
	if (~nwReset) begin
		uart_read <= 1'b0;
		uart_write < = 1'b0;
		uart_addr <= 3'b0;
		recv_buf_write <= 1'b0;
	end else begin
		uart_read <= 1'b0;
		uart_write < = 1'b0;
		uart_addr <= 3'b0;
		recv_buf_write <= 1'b0;
		if (uart_has_data && ~recv_buf_full) begin
			recv_buf_write <= 1'b1;
			recv_buf_data <= 
		end
	end

	/* ¶ÁÃüÁî´¦Àí */
	reg [31:0] bReadData;
	wire [1:0] readaddr = bReadAddr[3:2];
	always @(posedge wClk) 
	if (~nwReset) begin
		bReadData <= 32'h0;
		recv_buf_read <= 1'b0;
	end else begin
		recv_buf_read <= 1'b0;
		if (wRead) begin
			if (readaddr == 0) begin /* state */
				bReadData <= ctl_state;
			end else if (readaddr == 1) begin
				bReadData <= {24'b0, uartrecvdata};
				recv_buf_read <= ~ctl_state[16]; /* empty */
			end
		end
	end

	/* дÃüÁî´¦Àí */
	wire [1:0] writeaddr = bWriteAddr[3:2];
	always @(posedge wClk)
	if (~nwReset) begin
		send_buf_write <= 1'b0;
	end else begin
		send_buf_write <= 1'b0;
		if (wWrite && (writeaddr == 2)) begin
			send_buf_write <= 1'b1;
		end
	end

endmodule