#----------------------------------------------------------- # Vivado v2021.1 (64-bit) # SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021 # IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 # Start of session at: Mon Sep 13 12:39:50 2021 # Process ID: 55872 # Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1 # Command line: vivado.exe -log risc_axi_v5_top_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source risc_axi_v5_top_wrapper.tcl # Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/risc_axi_v5_top_wrapper.vds # Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1\vivado.jou #----------------------------------------------------------- source risc_axi_v5_top_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmster_1.0'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. WARNING: [IP_Flow 19-2207] Repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0' already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.1/data/ip'. INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'm00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'm00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm00_axi'. INFO: [IP_Flow 19-4728] Bus Interface 'm00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm00_axi_aresetn'. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmster_1.0'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. WARNING: [IP_Flow 19-2207] Repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0' already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'. INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmster_1.0'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. WARNING: [IP_Flow 19-2207] Repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0' already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'. INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmster_1.0'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. WARNING: [IP_Flow 19-2207] Repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0' already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. Command: synth_design -top risc_axi_v5_top_wrapper -part xc7z020clg400-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Device 21-403] Loading part xc7z020clg400-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 51276 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1136.770 ; gain = 0.000 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_wrapper' [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/hdl/risc_axi_v5_top_wrapper.v:12] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:305] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0/synth/risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0.v:58] INFO: [Synth 8-6157] synthesizing module 'hdl4se_uart_ctrl_axi' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/uart/hdl4se_uart_ctrl_axi.v:4] INFO: [Synth 8-6157] synthesizing module 'uart_fifo_gen' [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/new/xilinux_uart_fifo_gen.v:2] INFO: [Synth 8-638] synthesizing module 'hdl4se_uart_fifo' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/synth/hdl4se_uart_fifo.vhd:73] Parameter C_COMMON_CLOCK bound to: 1 - type: integer Parameter C_SELECT_XPM bound to: 0 - type: integer Parameter C_COUNT_TYPE bound to: 0 - type: integer Parameter C_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_DEFAULT_VALUE bound to: BlankString - type: string Parameter C_DIN_WIDTH bound to: 8 - type: integer Parameter C_DOUT_RST_VAL bound to: 0 - type: string Parameter C_DOUT_WIDTH bound to: 8 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FAMILY bound to: zynq - type: string Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer Parameter C_HAS_BACKUP bound to: 0 - type: integer Parameter C_HAS_DATA_COUNT bound to: 1 - type: integer Parameter C_HAS_INT_CLK bound to: 0 - type: integer Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer Parameter C_HAS_OVERFLOW bound to: 0 - type: integer Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_RD_RST bound to: 0 - type: integer Parameter C_HAS_RST bound to: 0 - type: integer Parameter C_HAS_SRST bound to: 1 - type: integer Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer Parameter C_HAS_VALID bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 0 - type: integer Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_WR_RST bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer Parameter C_MEMORY_TYPE bound to: 1 - type: integer Parameter C_MIF_FILE_NAME bound to: BlankString - type: string Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer Parameter C_OVERFLOW_LOW bound to: 0 - type: integer Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 1 - type: integer Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 511 - type: integer Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 510 - type: integer Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer Parameter C_RD_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_RD_DEPTH bound to: 512 - type: integer Parameter C_RD_FREQ bound to: 1 - type: integer Parameter C_RD_PNTR_WIDTH bound to: 9 - type: integer Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer Parameter C_USE_DOUT_RST bound to: 1 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer Parameter C_VALID_LOW bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_WR_DEPTH bound to: 512 - type: integer Parameter C_WR_FREQ bound to: 1 - type: integer Parameter C_WR_PNTR_WIDTH bound to: 9 - type: integer Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer Parameter C_MSGON_VAL bound to: 1 - type: integer Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer Parameter C_HAS_MASTER_CE bound to: 0 - type: integer Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer Parameter C_HAS_AXIS_TID bound to: 0 - type: integer Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer Parameter C_WACH_TYPE bound to: 0 - type: integer Parameter C_WDCH_TYPE bound to: 0 - type: integer Parameter C_WRCH_TYPE bound to: 0 - type: integer Parameter C_RACH_TYPE bound to: 0 - type: integer Parameter C_RDCH_TYPE bound to: 0 - type: integer Parameter C_AXIS_TYPE bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string Parameter C_USE_ECC_WACH bound to: 0 - type: integer Parameter C_USE_ECC_WDCH bound to: 0 - type: integer Parameter C_USE_ECC_WRCH bound to: 0 - type: integer Parameter C_USE_ECC_RACH bound to: 0 - type: integer Parameter C_USE_ECC_RDCH bound to: 0 - type: integer Parameter C_USE_ECC_AXIS bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer INFO: [Synth 8-3491] module 'fifo_generator_v13_2_5' declared at 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38604' bound to instance 'U0' of component 'fifo_generator_v13_2_5' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/synth/hdl4se_uart_fifo.vhd:541] INFO: [Synth 8-256] done synthesizing module 'hdl4se_uart_fifo' (27#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/synth/hdl4se_uart_fifo.vhd:73] INFO: [Synth 8-6155] done synthesizing module 'uart_fifo_gen' (28#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/new/xilinux_uart_fifo_gen.v:2] INFO: [Synth 8-6157] synthesizing module 'hdl4se_uart' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/uart/hdl4se_uart.v:195] INFO: [Synth 8-6157] synthesizing module 'hdl4se_uart_tx' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/uart/hdl4se_uart.v:6] INFO: [Synth 8-6155] done synthesizing module 'hdl4se_uart_tx' (29#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/uart/hdl4se_uart.v:6] INFO: [Synth 8-6157] synthesizing module 'hdl4se_uart_rx' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/uart/hdl4se_uart.v:86] INFO: [Synth 8-6155] done synthesizing module 'hdl4se_uart_rx' (30#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/uart/hdl4se_uart.v:86] INFO: [Synth 8-6155] done synthesizing module 'hdl4se_uart' (31#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/uart/hdl4se_uart.v:195] INFO: [Synth 8-6155] done synthesizing module 'hdl4se_uart_ctrl_axi' (32#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/uart/hdl4se_uart_ctrl_axi.v:4] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0' (33#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0/synth/risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0.v:58] WARNING: [Synth 8-7071] port 'dataready' of module 'risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0' is unconnected for instance 'hdl4se_uart_ctrl_axi_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:390] WARNING: [Synth 8-7071] port 'sendready' of module 'risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0' is unconnected for instance 'hdl4se_uart_ctrl_axi_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:390] WARNING: [Synth 8-7071] port 'sendfull' of module 'risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0' is unconnected for instance 'hdl4se_uart_ctrl_axi_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:390] WARNING: [Synth 8-7071] port 'recvempty' of module 'risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0' is unconnected for instance 'hdl4se_uart_ctrl_axi_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:390] WARNING: [Synth 8-7023] instance 'hdl4se_uart_ctrl_axi_0' of module 'risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0' has 27 connections declared, but only 23 given [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:390] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_led_key_0_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/synth/risc_axi_v5_top_led_key_0_0.v:58] INFO: [Synth 8-6157] synthesizing module 'led_key' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/led_key/led_key.v:4] INFO: [Synth 8-6155] done synthesizing module 'led_key' (34#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/led_key/led_key.v:4] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_led_key_0_0' (35#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/synth/risc_axi_v5_top_led_key_0_0.v:58] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_riscv_core_with_axi_0_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/synth/risc_axi_v5_top_riscv_core_with_axi_0_0.v:58] INFO: [Synth 8-6157] synthesizing module 'riscv_core_with_axi_master_xilinxwrap' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:206] INFO: [Synth 8-6157] synthesizing module 'riscv_core_with_axi_master' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:4] INFO: [Synth 8-6157] synthesizing module 'regfile' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/regfile.v:2] INFO: [Synth 8-6155] done synthesizing module 'regfile' (36#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/regfile.v:2] INFO: [Synth 8-638] synthesizing module 'ram4KB' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/synth/ram4KB.vhd:70] Parameter C_FAMILY bound to: zynq - type: string Parameter C_XDEVICEFAMILY bound to: zynq - type: string Parameter C_ELABORATION_DIR bound to: ./ - type: string Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_MEM_TYPE bound to: 0 - type: integer Parameter C_BYTE_SIZE bound to: 8 - type: integer Parameter C_ALGORITHM bound to: 1 - type: integer Parameter C_PRIM_TYPE bound to: 1 - type: integer Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer Parameter C_INIT_FILE_NAME bound to: ram4KB.mif - type: string Parameter C_INIT_FILE bound to: ram4KB.mem - type: string Parameter C_USE_DEFAULT_DATA bound to: 1 - type: integer Parameter C_DEFAULT_DATA bound to: 0 - type: string Parameter C_HAS_RSTA bound to: 0 - type: integer Parameter C_RST_PRIORITY_A bound to: CE - type: string Parameter C_RSTRAM_A bound to: 0 - type: integer Parameter C_INITA_VAL bound to: 0 - type: string Parameter C_HAS_ENA bound to: 1 - type: integer Parameter C_HAS_REGCEA bound to: 0 - type: integer Parameter C_USE_BYTE_WEA bound to: 1 - type: integer Parameter C_WEA_WIDTH bound to: 4 - type: integer Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer Parameter C_READ_WIDTH_A bound to: 32 - type: integer Parameter C_WRITE_DEPTH_A bound to: 1024 - type: integer Parameter C_READ_DEPTH_A bound to: 1024 - type: integer Parameter C_ADDRA_WIDTH bound to: 10 - type: integer Parameter C_HAS_RSTB bound to: 0 - type: integer Parameter C_RST_PRIORITY_B bound to: CE - type: string Parameter C_RSTRAM_B bound to: 0 - type: integer Parameter C_INITB_VAL bound to: 0 - type: string Parameter C_HAS_ENB bound to: 0 - type: integer Parameter C_HAS_REGCEB bound to: 0 - type: integer Parameter C_USE_BYTE_WEB bound to: 1 - type: integer Parameter C_WEB_WIDTH bound to: 4 - type: integer Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer Parameter C_READ_WIDTH_B bound to: 32 - type: integer Parameter C_WRITE_DEPTH_B bound to: 1024 - type: integer Parameter C_READ_DEPTH_B bound to: 1024 - type: integer Parameter C_ADDRB_WIDTH bound to: 10 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_USE_SOFTECC bound to: 0 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_EN_ECC_PIPE bound to: 0 - type: integer Parameter C_READ_LATENCY_A bound to: 1 - type: integer Parameter C_READ_LATENCY_B bound to: 1 - type: integer Parameter C_HAS_INJECTERR bound to: 0 - type: integer Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string Parameter C_COMMON_CLK bound to: 0 - type: integer Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer Parameter C_USE_URAM bound to: 0 - type: integer Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer Parameter C_COUNT_36K_BRAM bound to: 1 - type: string Parameter C_COUNT_18K_BRAM bound to: 0 - type: string Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 2.96495 mW - type: string INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_4' declared at 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_4' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/synth/ram4KB.vhd:236] INFO: [Synth 8-256] done synthesizing module 'ram4KB' (38#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/synth/ram4KB.vhd:70] WARNING: [Synth 8-689] width (30) of port connection 'addra' does not match port width (10) of module 'ram4KB' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:111] INFO: [Synth 8-6157] synthesizing module 'riscv_core_v5' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:58] INFO: [Synth 8-6157] synthesizing module 'mul32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/mul32.v:34] INFO: [Synth 8-6155] done synthesizing module 'mul32' (39#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/mul32.v:34] WARNING: [Synth 8-689] width (32) of port connection 'wStart' does not match port width (1) of module 'mul32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:192] INFO: [Synth 8-6157] synthesizing module 'div32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/div32.v:34] INFO: [Synth 8-6155] done synthesizing module 'div32' (40#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/div32.v:34] WARNING: [Synth 8-689] width (32) of port connection 'wStart' does not match port width (1) of module 'div32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:271] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:376] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:445] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:454] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:443] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:484] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:558] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:653] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:775] INFO: [Synth 8-226] default block is never used [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:909] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:772] INFO: [Synth 8-6155] done synthesizing module 'riscv_core_v5' (41#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:58] WARNING: [Synth 8-567] referenced signal 'bWriteAddr' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:176] INFO: [Synth 8-6155] done synthesizing module 'riscv_core_with_axi_master' (42#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:4] INFO: [Synth 8-6155] done synthesizing module 'riscv_core_with_axi_master_xilinxwrap' (43#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:206] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_riscv_core_with_axi_0_0' (44#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/synth/risc_axi_v5_top_riscv_core_with_axi_0_0.v:58] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_riscv_core_with_axi_0_axi_periph_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:535] INFO: [Synth 8-6157] synthesizing module 'm00_couplers_imp_DIBHKD' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:12] INFO: [Synth 8-6155] done synthesizing module 'm00_couplers_imp_DIBHKD' (45#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:12] INFO: [Synth 8-6157] synthesizing module 'm01_couplers_imp_15DQFTV' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:158] INFO: [Synth 8-6155] done synthesizing module 'm01_couplers_imp_15DQFTV' (46#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:158] INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_4FUU9H' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:1015] INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_4FUU9H' (47#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:1015] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_xbar_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/synth/risc_axi_v5_top_xbar_0.v:59] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_axi_crossbar' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4884] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_crossbar_sasd' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:1240] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_addr_decoder' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:794] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_carry_and' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_carry_and' (48#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' (49#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' (49#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_addr_decoder' (50#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:794] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_decerr_slave' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3501] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_decerr_slave' (51#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3501] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_addr_arbiter_sasd' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:65] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_addr_arbiter_sasd' (52#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:65] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_splitter' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_splitter' (53#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_splitter__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_splitter__parameterized0' (53#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' (54#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' (54#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' (54#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_24_axic_register_slice' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8f68/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_24_axic_register_slice' (55#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8f68/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized2' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized2' (55#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_crossbar_sasd' (56#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:1240] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_axi_crossbar' (57#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4884] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_xbar_0' (58#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/synth/risc_axi_v5_top_xbar_0.v:59] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_riscv_core_with_axi_0_axi_periph_0' (59#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:535] INFO: [Synth 8-638] synthesizing module 'risc_axi_v5_top_rst_wClk_50M_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/synth/risc_axi_v5_top_rst_wClk_50M_0.vhd:74] Parameter C_FAMILY bound to: zynq - type: string Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer Parameter C_EXT_RESET_HIGH bound to: 1'b0 Parameter C_AUX_RESET_HIGH bound to: 1'b0 Parameter C_NUM_BUS_RST bound to: 1 - type: integer Parameter C_NUM_PERP_RST bound to: 1 - type: integer Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer INFO: [Synth 8-3491] module 'proc_sys_reset' declared at 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/synth/risc_axi_v5_top_rst_wClk_50M_0.vhd:129] INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481] INFO: [Synth 8-638] synthesizing module 'lpf' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816] INFO: [Synth 8-3491] module 'SRL16' declared at 'C:/Xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:100945' bound to instance 'POR_SRL_I' of component 'SRL16' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868] INFO: [Synth 8-6157] synthesizing module 'SRL16' [C:/Xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:100945] INFO: [Synth 8-6155] done synthesizing module 'SRL16' (60#1) [C:/Xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:100945] INFO: [Synth 8-638] synthesizing module 'cdc_sync' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584] INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (61#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-256] done synthesizing module 'lpf' (62#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816] INFO: [Synth 8-638] synthesizing module 'sequence_psr' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301] INFO: [Synth 8-638] synthesizing module 'upcnt_n' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125] INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (63#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125] INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (64#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301] INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (65#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323] INFO: [Synth 8-256] done synthesizing module 'risc_axi_v5_top_rst_wClk_50M_0' (66#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/synth/risc_axi_v5_top_rst_wClk_50M_0.vhd:74] WARNING: [Synth 8-7071] port 'mb_reset' of module 'risc_axi_v5_top_rst_wClk_50M_0' is unconnected for instance 'rst_wClk_50M' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:526] WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'risc_axi_v5_top_rst_wClk_50M_0' is unconnected for instance 'rst_wClk_50M' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:526] WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'risc_axi_v5_top_rst_wClk_50M_0' is unconnected for instance 'rst_wClk_50M' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:526] WARNING: [Synth 8-7071] port 'interconnect_aresetn' of module 'risc_axi_v5_top_rst_wClk_50M_0' is unconnected for instance 'rst_wClk_50M' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:526] WARNING: [Synth 8-7023] instance 'rst_wClk_50M' of module 'risc_axi_v5_top_rst_wClk_50M_0' has 10 connections declared, but only 6 given [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:526] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top' (67#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:305] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_wrapper' (68#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/hdl/risc_axi_v5_top_wrapper.v:12] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 1425.609 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 56 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/hdl4se_uart_fifo.xdc] for cell 'risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0' Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/hdl4se_uart_fifo.xdc] for cell 'risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0' Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/hdl4se_uart_fifo.xdc] for cell 'risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0' Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/hdl4se_uart_fifo.xdc] for cell 'risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0' Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0_board.xdc] for cell 'risc_axi_v5_top_i/rst_wClk_50M/U0' Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0_board.xdc] for cell 'risc_axi_v5_top_i/rst_wClk_50M/U0' Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0.xdc] for cell 'risc_axi_v5_top_i/rst_wClk_50M/U0' Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0.xdc] for cell 'risc_axi_v5_top_i/rst_wClk_50M/U0' Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/constrs_1/new/zynq.xdc] Finished Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/constrs_1/new/zynq.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/constrs_1/new/zynq.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/risc_axi_v5_top_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/risc_axi_v5_top_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/risc_axi_v5_top_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/risc_axi_v5_top_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1425.609 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13 instances were transformed. FDR => FDRE: 12 instances SRL16 => SRL16E: 1 instance Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1425.609 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0. (constraint file D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc, line 42). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0. (constraint file D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc, line 42). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/rst_wClk_50M/U0. (constraint file D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc, line 45). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/ram. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/rst_wClk_50M. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/led_key_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/riscv_core_with_axi_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'hdl4se_uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'riscv_core_v5' INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 10 | 10 both_stages_valid | 11 | 11 stage2_valid | 01 | 01 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE3 | 00 | 0000 iSTATE0 | 01 | 0001 iSTATE1 | 10 | 0010 iSTATE2 | 11 | 0100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'hdl4se_uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0000 | 0001 iSTATE1 | 0001 | 0010 iSTATE0 | 0010 | 0011 iSTATE | 0011 | 0100 iSTATE7 | 0100 | 0101 iSTATE6 | 0101 | 0110 iSTATE4 | 0110 | 0111 iSTATE5 | 0111 | 1000 iSTATE3 | 1000 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'riscv_core_v5' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 3 Input 64 Bit Adders := 1 2 Input 64 Bit Adders := 1 2 Input 32 Bit Adders := 9 3 Input 32 Bit Adders := 1 2 Input 16 Bit Adders := 3 2 Input 10 Bit Adders := 2 2 Input 9 Bit Adders := 4 2 Input 6 Bit Adders := 2 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 2 2 Input 1 Bit XORs := 75 +---Registers : 64 Bit Registers := 4 36 Bit Registers := 2 32 Bit Registers := 18 16 Bit Registers := 4 10 Bit Registers := 2 9 Bit Registers := 8 8 Bit Registers := 9 6 Bit Registers := 2 5 Bit Registers := 3 4 Bit Registers := 5 3 Bit Registers := 6 2 Bit Registers := 7 1 Bit Registers := 67 +---RAMs : 1024 Bit (32 X 32 bit) RAMs := 2 +---Muxes : 2 Input 64 Bit Muxes := 5 2 Input 36 Bit Muxes := 2 5 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 46 10 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 11 3 Input 32 Bit Muxes := 4 8 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 6 Input 32 Bit Muxes := 1 2 Input 30 Bit Muxes := 1 2 Input 24 Bit Muxes := 4 3 Input 24 Bit Muxes := 2 4 Input 24 Bit Muxes := 1 2 Input 16 Bit Muxes := 8 4 Input 16 Bit Muxes := 1 2 Input 8 Bit Muxes := 7 4 Input 8 Bit Muxes := 3 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 7 8 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 6 Input 5 Bit Muxes := 1 3 Input 5 Bit Muxes := 2 4 Input 4 Bit Muxes := 2 2 Input 4 Bit Muxes := 14 7 Input 4 Bit Muxes := 1 8 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 3 9 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 3 2 Input 2 Bit Muxes := 25 5 Input 2 Bit Muxes := 2 3 Input 2 Bit Muxes := 1 8 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 133 3 Input 1 Bit Muxes := 10 4 Input 1 Bit Muxes := 21 8 Input 1 Bit Muxes := 1 7 Input 1 Bit Muxes := 3 10 Input 1 Bit Muxes := 1 9 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +----------------------------------------+-------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------------------------------+-------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |risc_axi_v5_top_i/riscv_core_with_axi_0 | inst/riscv_core_inst/regs/regs_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |risc_axi_v5_top_i/riscv_core_with_axi_0 | inst/riscv_core_inst/regs2/regs_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +----------------------------------------+-------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:55 ; elapsed = 00:00:56 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:55 ; elapsed = 00:00:57 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +----------------------------------------+-------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------------------------------+-------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |risc_axi_v5_top_i/riscv_core_with_axi_0 | inst/riscv_core_inst/regs/regs_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |risc_axi_v5_top_i/riscv_core_with_axi_0 | inst/riscv_core_inst/regs2/regs_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +----------------------------------------+-------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/regs/regs_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/regs2/regs_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:59 ; elapsed = 00:01:01 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:59 ; elapsed = 00:01:01 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |CARRY4 | 196| |3 |LUT1 | 186| |4 |LUT2 | 240| |5 |LUT3 | 434| |6 |LUT4 | 343| |7 |LUT5 | 586| |8 |LUT6 | 1457| |9 |MUXCY | 40| |10 |MUXF7 | 32| |11 |RAMB18E1 | 4| |13 |RAMB36E1 | 1| |14 |SRL16 | 1| |15 |FDR | 4| |16 |FDRE | 984| |17 |FDSE | 65| |18 |IBUF | 3| |19 |OBUF | 5| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 1425.609 ; gain = 288.840 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:58 . Memory (MB): peak = 1425.609 ; gain = 288.840 Synthesis Optimization Complete : Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 1425.609 ; gain = 288.840 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 1425.609 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 278 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1425.609 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 21 instances were transformed. (MUXCY,XORCY) => CARRY4: 16 instances FDR => FDRE: 4 instances SRL16 => SRL16E: 1 instance Synth Design complete, checksum: edccbfbc INFO: [Common 17-83] Releasing license: Synthesis 178 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:03 ; elapsed = 00:01:07 . Memory (MB): peak = 1425.609 ; gain = 288.840 INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/risc_axi_v5_top_wrapper.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file risc_axi_v5_top_wrapper_utilization_synth.rpt -pb risc_axi_v5_top_wrapper_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Mon Sep 13 12:41:07 2021...