Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 | Date : Mon Sep 13 12:42:12 2021 | Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) | Command : report_clock_utilization -file risc_axi_v5_top_wrapper_clock_utilization_routed.rpt | Design : risc_axi_v5_top_wrapper | Device : 7z020-clg400 | Speed File : -2 PRODUCTION 1.12 2019-11-22 | Design State : Routed ----------------------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions: Key Resource Utilization 5. Clock Regions : Global Clock Summary 6. Device Cell Placement Summary for Global Clock g0 7. Clock Region Cell Placement per Global Clock: Region X1Y0 8. Clock Region Cell Placement per Global Clock: Region X1Y1 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 1 | 32 | 0 | 0 | 0 | | BUFH | 0 | 72 | 0 | 0 | 0 | | BUFIO | 0 | 16 | 0 | 0 | 0 | | BUFMR | 0 | 8 | 0 | 0 | 0 | | BUFR | 0 | 16 | 0 | 0 | 0 | | MMCM | 0 | 4 | 0 | 0 | 0 | | PLL | 0 | 4 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 1064 | 0 | | | wClk_IBUF_BUFG_inst/O | wClk_IBUF_BUFG | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+ | src0 | g0 | IBUF/O | IOB_X1Y76 | IOB_X1Y76 | X1Y1 | 1 | 0 | | | wClk_IBUF_inst/O | wClk_IBUF | +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 1000 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 704 | 3200 | 233 | 850 | 2 | 60 | 1 | 30 | 0 | 40 | | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 349 | 2600 | 119 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | | X0Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ | Y2 | 0 | 0 | | Y1 | 0 | 1 | | Y0 | 0 | 1 | +----+----+----+ 6. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+ | g0 | BUFG/O | n/a | | | | 1059 | 0 | 0 | 0 | wClk_IBUF_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+----+------+-----------------------+ | Y2 | 0 | 0 | 0 | | Y1 | 0 | 349 | 0 | | Y0 | 0 | 710 | 0 | +----+----+------+-----------------------+ 7. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ | g0 | n/a | BUFG/O | None | 710 | 0 | 704 | 1 | 3 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 8. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ | g0 | n/a | BUFG/O | None | 349 | 0 | 349 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y16 [get_cells wClk_IBUF_BUFG_inst] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X1Y76 [get_ports wClk] # Clock net "wClk_IBUF_BUFG" driven by instance "wClk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" #startgroup create_pblock {CLKAG_wClk_IBUF_BUFG} add_cells_to_pblock [get_pblocks {CLKAG_wClk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="wClk_IBUF_BUFG"}]]] resize_pblock [get_pblocks {CLKAG_wClk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} #endgroup