xilinx.com customized_ip risc_axi_v5_top_rst_wClk_50M_0 1.0 clock Clock CLK slowest_sync_clk ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset FREQ_HZ Slowest Sync clock frequency Slowest Synchronous clock frequency 50000000 FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN risc_axi_v5_top_wClk none ASSOCIATED_BUSIF none INSERT_VIP 0 simulation.rtl ext_reset Ext_Reset RST ext_reset_in BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE required POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl aux_reset aux_reset RST aux_reset_in POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl dbg_reset DBG_Reset RST mb_debug_sys_rst POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl mb_rst MB_rst RST mb_reset POLARITY ACTIVE_HIGH TYPE PROCESSOR INSERT_VIP 0 simulation.rtl bus_struct_reset bus_struct_reset RST bus_struct_reset POLARITY ACTIVE_HIGH TYPE INTERCONNECT INSERT_VIP 0 simulation.rtl interconnect_low_rst interconnect_low_rst RST interconnect_aresetn POLARITY ACTIVE_LOW TYPE INTERCONNECT INSERT_VIP 0 simulation.rtl peripheral_high_rst peripheral_high_rst RST peripheral_reset POLARITY ACTIVE_HIGH TYPE PERIPHERAL INSERT_VIP 0 simulation.rtl peripheral_low_rst peripheral_low_rst RST peripheral_aresetn POLARITY ACTIVE_LOW TYPE PERIPHERAL INSERT_VIP 0 simulation.rtl xilinx_vhdlsynthesis VHDL Synthesis vhdlSource:vivado.xilinx.com:synthesis vhdl proc_sys_reset xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset xilinx_vhdlsynthesis_view_fileset GENtimestamp Mon Sep 13 04:39:04 UTC 2021 outputProductCRC 9:e799e8b9 xilinx_synthesisconstraints Synthesis Constraints :vivado.xilinx.com:synthesis.constraints outputProductCRC 9:e799e8b9 xilinx_vhdlsynthesiswrapper VHDL Synthesis Wrapper vhdlSource:vivado.xilinx.com:synthesis.wrapper vhdl risc_axi_v5_top_rst_wClk_50M_0 xilinx_vhdlsynthesiswrapper_view_fileset GENtimestamp Mon Sep 13 04:39:04 UTC 2021 outputProductCRC 9:e799e8b9 xilinx_vhdlbehavioralsimulation VHDL Simulation vhdlSource:vivado.xilinx.com:simulation vhdl proc_sys_reset xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset xilinx_vhdlbehavioralsimulation_view_fileset GENtimestamp Sun Sep 12 07:24:51 UTC 2021 outputProductCRC 9:a9d44bff xilinx_vhdlsimulationwrapper VHDL Simulation Wrapper vhdlSource:vivado.xilinx.com:simulation.wrapper vhdl risc_axi_v5_top_rst_wClk_50M_0 xilinx_vhdlsimulationwrapper_view_fileset GENtimestamp Mon Sep 13 04:39:04 UTC 2021 outputProductCRC 9:a9d44bff xilinx_implementation Implementation :vivado.xilinx.com:implementation xilinx_implementation_view_fileset GENtimestamp Mon Sep 13 04:39:04 UTC 2021 outputProductCRC 9:e799e8b9 slowest_sync_clk in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation ext_reset_in in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation aux_reset_in in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 1 mb_debug_sys_rst in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0 dcm_locked in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0x1 mb_reset out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0x0 bus_struct_reset out 0 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0 peripheral_reset out 0 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0 interconnect_aresetn out 0 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 1 peripheral_aresetn out 0 0 std_logic_vector xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 1 C_FAMILY zynq C_EXT_RST_WIDTH Ext Rst Width 4 C_AUX_RST_WIDTH Aux Rst Width 4 C_EXT_RESET_HIGH Ext Reset High 0 C_AUX_RESET_HIGH Aux Reset High 0 C_NUM_BUS_RST No. of Bus Reset (Active High) 1 C_NUM_PERP_RST No. of Peripheral Reset (Active High) 1 C_NUM_INTERCONNECT_ARESETN No. of Interconnect Reset (Active Low) 1 C_NUM_PERP_ARESETN No. of Peripheral Reset (Active Low) 1 choice_list_ac75ef1e Custom xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset ../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd vhdlSource lib_cdc_v1_0_2 xilinx_vhdlsynthesis_view_fileset ../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd vhdlSource proc_sys_reset_v5_0_13 risc_axi_v5_top_rst_wClk_50M_0.xdc xdc xilinx_vhdlsynthesiswrapper_view_fileset synth/risc_axi_v5_top_rst_wClk_50M_0.vhd vhdlSource xil_defaultlib xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset ../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd vhdlSource USED_IN_ipstatic lib_cdc_v1_0_2 xilinx_vhdlbehavioralsimulation_view_fileset ../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd vhdlSource USED_IN_ipstatic proc_sys_reset_v5_0_13 xilinx_vhdlsimulationwrapper_view_fileset sim/risc_axi_v5_top_rst_wClk_50M_0.vhd vhdlSource xil_defaultlib xilinx_implementation_view_fileset risc_axi_v5_top_rst_wClk_50M_0_board.xdc xdc USED_IN_board USED_IN_implementation USED_IN_synthesis Processor Reset System C_NUM_PERP_ARESETN No. of Peripheral Reset (Active Low) 1 C_NUM_INTERCONNECT_ARESETN No. of Interconnect Reset (Active Low) 1 C_NUM_PERP_RST No. of Peripheral Reset (Active High) 1 C_NUM_BUS_RST No. of Bus Reset (Active High) 1 C_AUX_RESET_HIGH Aux Reset High 0 C_EXT_RESET_HIGH Ext Reset High 0 C_AUX_RST_WIDTH Aux Rst Width 4 C_EXT_RST_WIDTH Ext Rst Width 4 Component_Name risc_axi_v5_top_rst_wClk_50M_0 USE_BOARD_FLOW Generate Board based IO Constraints false RESET_BOARD_INTERFACE Custom Processor System Reset 13 2021.1