/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
**   this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
**   this list of conditions and the following disclaimer in the documentation
**   and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
**   derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/

/*
* verilog_vardecl.c
  修改记录：
    202106061102: rxh, initial version
*/
#include "stdio.h"
#include "stdlib.h"
#include "string.h"

#include "object.h"
#include "dlist.h"
#include "verilog_parsetree.h"
#define IMPLEMENT_GUID
#include "verilog_vardecl.h"
#undef IMPLEMENT_GUID

typedef struct _sVarDecl {
    OBJECT_HEADER
    INTERFACE_DECLARE(IVerilogNode)
    VERILOGNODE_VARDECLARE
    DLIST_VARDECLARE
    
	verilogVarDecl data;
#if 0
	int type;
    const char* name;
	IVerilogNode** assignexpr;
	IDListVar* attributes;
	IDListVar* dimensions;
	int vectored_or_scalared;
	int issigned;
	int range_type;
	IVerilogNode** range_msb;
	IVerilogNode** range_lsb;
	IVerilogNode** delay0;
	IVerilogNode** delay1;
	IVerilogNode** delay2;
#endif
}sVarDecl;

OBJECT_FUNCDECLARE(vardecl, CLSID_VERILOG_VARDECL);

VERILOGNODE_FUNCDECLARE(vardecl, CLSID_VERILOG_VARDECL, sVarDecl);
DLIST_FUNCIMPL(vardecl, CLSID_VERILOG_VARDECL, sVarDecl);
OBJECT_FUNCIMPL(vardecl, sVarDecl, CLSID_VERILOG_VARDECL);

QUERYINTERFACE_BEGIN(vardecl, CLSID_VERILOG_VARDECL)
QUERYINTERFACE_ITEM(IID_VERILOG_NODE, IVerilogNode, sVarDecl)
QUERYINTERFACE_ITEM(IID_DLIST, IDList, sVarDecl)
QUERYINTERFACE_END

static const char *vardeclModuleInfo()
{
	return "1.0.0-20210606.1108 Verilog Var Declaration ";
}

static int vardeclCreate(const PARAMITEM * pParams, int paramcount, HOBJECT * pObject)
{
	sVarDecl * pobj;
	pobj = (sVarDecl *)malloc(sizeof(sVarDecl));
	if (pobj == NULL)
		return -1;

	memset(pobj, 0, sizeof(sVarDecl));
	
	*pObject = 0;
	DLIST_VARINIT(pobj, vardecl);
	VERILOGNODE_VARINIT(pobj, CLSID_VERILOG_VARDECL);
	INTERFACE_INIT(IVerilogNode, pobj, vardecl, verilognode);
  	
	/*返回生成的对象*/
	OBJECT_RETURN_GEN(vardecl, pobj, pObject, CLSID_VERILOG_VARDECL);
	return EIID_OK;
}


static void vardeclDestroy(HOBJECT object)
{
	sVarDecl * pobj;
	pobj = (sVarDecl *)objectThis(object);
    if (pobj->data.name)
        free(pobj->data.name);
    objectRelease(pobj->data.assignexpr);
	objectRelease(pobj->data.range_msb);
	objectRelease(pobj->data.range_lsb);
	objectRelease(pobj->data.delay0);
	objectRelease(pobj->data.delay1);
	objectRelease(pobj->data.delay2);
	dlistRemoveAll(pobj->data.attributes);
	objectRelease(pobj->data.attributes);
	dlistRemoveAll(pobj->data.dimensions);
	objectRelease(pobj->data.dimensions);
	memset(pobj, 0, sizeof(sVarDecl));
	free(pobj);
}

/*
    功能：判断对象是否是一个有效对象
    参数：
        object -- 对象数据指针
    返回值：
        0 -- 对象是无效的
        1 -- 对象是有效的
*/
static int vardeclValid(HOBJECT object)
{
    return 1;
}

static int output_range(FILE* pFile, int opt, int type, IVerilogNode** msb, IVerilogNode** lsb)
{
	if (type == RANGE_TYPE_NONE)
		return 0;
	if (type == RANGE_TYPE_BITSELECT) {
		fprintf(pFile, " [");
		objectCall2(msb, dump, pFile, opt);
		fprintf(pFile, "] ");
		return 0;
	}
	fprintf(pFile, " [");
	objectCall2(msb, dump, pFile, opt);
	if (type == RANGE_TYPE_PARTSELECT)
		fprintf(pFile, ":");
	else if (type == RANGE_TYPE_STARTPLUSWIDTH)
		fprintf(pFile, "+:");
	else if (type == RANGE_TYPE_STARTMINUSWIDTH)
		fprintf(pFile, "-:");
	objectCall2(lsb, dump, pFile, opt);
	fprintf(pFile, "] ");
	return 0;

}

static int vardecl_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
{
	sVarDecl * pobj;
	pobj = (sVarDecl *)objectThis(object);
	/*
	attribute_instance_list net_type drive_strength_option vectored_or_scalared_option signed_option
		range_option delay3_option list_of_net
	*/
	fprintf(pFile, "  ");
	if (dlistItemCount(pobj->data.attributes) > 0) {
		fprintf(pFile, "(* ");
		verilog_dump_node_list(pobj->data.attributes, pFile, opt, ", ");
		fprintf(pFile, " *) ");
	}
	fprintf(pFile, var_type_name[pobj->data.type]);
	output_range(pFile, opt, pobj->data.range_type, pobj->data.range_msb, pobj->data.range_lsb);
	fprintf(pFile, " %s", pobj->data.name);
	if (pobj->data.assignexpr != NULL) {
		fprintf(pFile, " = ");
		objectCall2(pobj->data.assignexpr, dump, pFile, opt);
	}
	fprintf(pFile, ";\n");
	return 0;
}

HOBJECT verilogparseCreateVarDecl(const char* name)
{
	HOBJECT vardecl = NULL;
	sVarDecl * pobj;
	A_u_t_o_registor_vardecl();
	objectCreate(CLSID_VERILOG_VARDECL, NULL, 0, &vardecl);
	if (vardecl == NULL)
		return NULL;
	pobj = (sVarDecl *)objectThis(vardecl);
	pobj->data.name = strdup(name);
	return vardecl;
}

int verilogparseVarDeclSetAssignExpr(HOBJECT object, HOBJECT expr)
{
	sVarDecl* pobj;
	if (!objectIsClass(object, CLSID_VERILOG_VARDECL))
		return -1;
	pobj = (sVarDecl*)objectThis(object);
	objectRelease(pobj->data.assignexpr);
	objectQueryInterface(expr, IID_VERILOG_NODE, (void**)&pobj->data.assignexpr);
	return 0;
}

int verilogparseVarDeclSetDimensions(HOBJECT object, IDListVar* dimensions)
{
	sVarDecl* pobj;
	if (!objectIsClass(object, CLSID_VERILOG_VARDECL))
		return -1;
	pobj = (sVarDecl*)objectThis(object);
	pobj->data.dimensions = dimensions;
	objectAddRef(pobj->data.dimensions);
	return 0;
}

int verilogparseVarDeclSetOptions(HOBJECT object,
	int type,
	IDListVar* attributes,
	int vectored_or_scalared,
	int issigned,
	int range_type,
	HOBJECT range_msb,
	HOBJECT range_lsb,
	HOBJECT delay0,
	HOBJECT delay1,
	HOBJECT delay2
)
{
#define ASSIGN_MEMBER(m) \
	objectRelease(pobj->data.m); \
	pobj->data.m = NULL; \
	objectQueryInterface(m, IID_VERILOG_NODE, (void**)&pobj->data.m);

	sVarDecl* pobj;
	if (!objectIsClass(object, CLSID_VERILOG_VARDECL))
		return -1;
	pobj = (sVarDecl*)objectThis(object);
	pobj->data.attributes = attributes;
	objectAddRef(pobj->data.attributes);
	pobj->data.type = type;
	pobj->data.vectored_or_scalared = vectored_or_scalared;
	pobj->data.issigned = issigned;
	pobj->data.range_type = range_type;
	ASSIGN_MEMBER(range_msb);
	ASSIGN_MEMBER(range_lsb);
	ASSIGN_MEMBER(delay0);
	ASSIGN_MEMBER(delay1);
	ASSIGN_MEMBER(delay2);
	return 0;
}

verilogVarDecl* verilogVarDeclGetData(HOBJECT object)
{
	sVarDecl* pobj;
	if (!objectIsClass(object, CLSID_VERILOG_VARDECL))
		return NULL;
	pobj = (sVarDecl*)objectThis(object);
	return &pobj->data;
}