Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version3247384
date_generatedMon Sep 13 22:01:42 2021 os_platformWIN64
product_versionVivado v2021.1 (64-bit) project_id091906d75735416184ea41e449c55b97
project_iteration20 random_id8b0815bdeeeb5f3fbc70bc3b90deb048
registration_id8b0815bdeeeb5f3fbc70bc3b90deb048 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-2
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i9-10900 CPU @ 2.80GHz cpu_speed2808 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
applyrsbmultiautomationdialog_checkbox_tree=6 basedialog_apply=1 basedialog_cancel=21 basedialog_ok=74
basedialog_yes=7 cmdmsgdialog_ok=15 cmdmsgdialog_open_messages_view=1 coretreetablepanel_core_tree_table=30
createconstraintsfilepanel_file_name=1 createnewdiagramdialog_design_name=1 creatersbportdialog_active_low=1 creatersbportdialog_create_vector=2
creatersbportdialog_direction=2 creatersbportdialog_frequency=1 creatersbportdialog_from=2 creatersbportdialog_port_name=6
creatersbportdialog_type=6 createsrcfiledialog_file_name=1 customizecoredialog_documentation=3 definemodulesdialog_entity_name=1
filesetpanel_file_set_panel_tree=182 flownavigatortreepanel_flow_navigator_tree=142 graphicalview_zoom_in=11 graphicalview_zoom_out=2
hacgccoefilewidget_browse=9 hpopuptitle_close=1 mainmenumgr_file=2 mainmenumgr_flow=2
mainmenumgr_open_recent_project=1 mainmenumgr_project=2 mainmenumgr_tools=10 mainmenumgr_window=20
messagewithoptiondialog_dont_show_this_dialog_again=2 msgtreepanel_message_view_tree=32 msgview_clear_messages_resulting_from_user_executed=21 msgview_critical_warnings=3
msgview_information_messages=5 msgview_warning_messages=6 newipwizard_create_new_axi4_ip_create_axi4=4 newipwizard_interface_mode=2
newipwizard_name_myip=2 pacommandnames_add_sources=7 pacommandnames_auto_connect_target=6 pacommandnames_auto_update_hier=3
pacommandnames_create_top_hdl=1 pacommandnames_ip_packager_wizard=4 pacommandnames_open_project=1 pacommandnames_ports_window=1
pacommandnames_project_summary=9 pacommandnames_save_rsb_design=1 pacommandnames_show_product_guide=1 pacommandnames_show_product_webpage=2
pacommandnames_simulation_live_restart=18 pacommandnames_simulation_live_run=94 pacommandnames_simulation_run_behavioral=15 pacommandnames_simulation_settings=1
paviews_address_editor=2 paviews_code=13 paviews_ip_catalog=1 paviews_project_summary=33
paviews_schematic=1 paviews_system=1 planaheadtab_refresh_changed_modules=22 programfpgadialog_program=20
progressdialog_background=1 propertiesview_next_object=5 propertiesview_previous_object=17 quickhelp_help=1
rdicommands_delete=1 rdicommands_properties=2 rdicommands_save_file=11 rdicommands_settings=1
rdiviews_waveform_viewer=241 rsbaddmoduledialog_hide_incompatible_modules=2 rsbaddmoduledialog_module_list=6 rsbaddmoduledialog_module_type=2
rsbapplyautomationbar_run_connection_automation=7 rsbbaseporttablepanel_pins_table=2 rtloptionspanel_select_top_module_of_your_design=1 saveprojectutils_save=2
selectmenu_highlight=5 selecttopmoduledialog_select_top_module=1 signaltreepanel_signal_tree_table=37 simpleoutputproductdialog_generate_output_products_immediately=18
simpleoutputproductdialog_synthesize_design_globally=3 simulationobjectspanel_simulation_objects_tree_table=145 simulationscopespanel_simulate_scope_table=83 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=8
srcchooserpanel_create_file=1 srcmenu_ip_hierarchy=2 srcmenu_refresh_hierarchy=1 syntheticagettingstartedview_recent_projects=8
systembuildermenu_add_ip=2 systembuildermenu_add_module=18 systembuildermenu_create_port=6 systembuilderview_add_ip=1
systembuilderview_pinning=8 systemtreeview_system_tree=6 taskbanner_close=15 tclconsoleview_clear_all_output_in_tcl_console=1
tclconsoleview_tcl_console_code_editor=1 tclobjecttreetable_treetable=10 touchpointsurveydialog_no=1 touchpointsurveydialog_remind_me_later=2
waveformnametree_waveform_name_tree=24 waveformview_goto_last_time=4 waveformview_goto_time_0=16 waveformview_next_transition=865
waveformview_previous_transition=50
java_command_handlers
addsources=7 autoconnecttarget=5 coreview=3 createblockdesign=1
createtophdl=1 customizecore=2 customizersbblock=10 editdelete=12
editproperties=2 exitapp=4 ippackagerwizardhandler=4 launchprogramfpga=20
managecompositetargets=7 openblockdesign=12 openhardwaremanager=26 openproject=1
openrecenttarget=6 programdevice=20 projectsummary=8 recustomizecore=14
runbitgen=37 runimplementation=2 runsynthesis=5 saversbdesign=1
showproductguide=1 showproductwebpage=2 showview=12 simulationrestart=18
simulationrun=15 simulationrunfortime=46 timingconstraintswizard=1 toolssettings=2
viewtaskprojectmanager=9 viewtaskrtlanalysis=1
other_data
guimode=9
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=20 export_simulation_ies=21
export_simulation_modelsim=21 export_simulation_questa=21 export_simulation_riviera=21 export_simulation_vcs=21
export_simulation_xsim=21 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=18 simulator_language=Mixed srcsetcount=14 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 carry4=174 fdre=844 fdse=53
gnd=35 ibuf=3 lut1=145 lut2=212
lut3=378 lut4=304 lut5=563 lut6=1422
muxf7=1 obuf=5 ramb18e1=2 ramb36e1=1
srl16e=19 vcc=33
pre_unisim_transformation
bufg=1 carry4=174 fdre=844 fdse=53
gnd=35 ibuf=3 lut1=145 lut2=212
lut3=378 lut4=304 lut5=563 lut6=1422
muxf7=1 obuf=5 ramb18e1=2 ramb36e1=1
srl16e=19 vcc=33

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=6 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=897 srls_augmented=0
srls_newly_gated=0 srls_total=19

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA da_axi4_cnt=7 da_board_cnt=1
iptotal=1 maxhierdepth=0 numblks=9 numhdlrefblks=2
numhierblks=4 numhlsblks=0 numnonxlnxblks=0 numpkgbdblks=0
numreposblks=5 numsysgenblks=0 synth_mode=Global x_iplanguage=VERILOG
x_iplibrary=BlockDiagram x_ipname=risc_axi_v5_top x_ipvendor=xilinx.com x_ipversion=1.00.a
axi_crossbar_v2_1_25_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=zynq
c_m_axi_addr_width=0x0000000700000007 c_m_axi_base_addr=0x00000000f000000000000000f0000100 c_m_axi_read_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_read_issuing=0x0000000100000001
c_m_axi_secure=0x00000000 c_m_axi_write_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_write_issuing=0x0000000100000001 c_num_addr_ranges=1
c_num_master_slots=2 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=25
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_uartlite/1
c_baudrate=115200 c_data_bits=8 c_family=zynq c_odd_parity=0
c_s_axi_aclk_freq_hz=50000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_use_parity=0
core_container=NA iptotal=1 x_ipcorerevision=28 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_uartlite x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.0
blk_mem_gen_v8_4_4/1
c_addra_width=10 c_addrb_width=10 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=8 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=1 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 2.96495 mW
c_family=zynq c_has_axi_id=0 c_has_ena=1 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=ram4KB.mem
c_init_file_name=[user-defined] c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=1 c_mem_type=0 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=1024 c_read_depth_b=1024 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=32 c_read_width_b=32 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=1 c_use_byte_web=1 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=4 c_web_width=4
c_write_depth_a=1024 c_write_depth_b=1024 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=32 c_write_width_b=32 c_xdevicefamily=zynq core_container=false
iptotal=1 x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
led_key/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=led_key x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=0 c_ext_rst_width=4
c_family=zynq c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=13
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
riscv_core_with_axi_master_xilinxwrap/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=riscv_core_with_axi_master_xilinxwrap x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0

report_design_analysis
command_line_options
-append=default::[not_specified] -bounding_boxes=default::[not_specified] -cells=default::[not_specified] -complexity=default::[not_specified]
-congestion=default::[not_specified] -end_point_clocks=default::[not_specified] -extend=default::[not_specified] -extract_metrics=default::[not_specified]
-file=default::[not_specified] -full_logical_pin=default::[not_specified] -hierarchical_depth=default::[not_specified] -hold=default::[not_specified]
-logic_level_dist_paths=default::[not_specified] -logic_level_distribution=default::[not_specified] -logic_levels=default::[not_specified] -max_level=default::[not_specified]
-max_paths=default::[not_specified] -min_congestion_level=default::5 -min_level=default::[not_specified] -name=default::[not_specified]
-no_header=default::[not_specified] -of_timing_paths=default::[not_specified] -pploc_distance=default::[not_specified] -qor_summary=[specified]
-quiet=default::[not_specified] -return_string=default::[not_specified] -return_timing_paths=default::[not_specified] -routed_vs_estimated=default::[not_specified]
-routes=default::[not_specified] -setup=default::[not_specified] -show_all_congestion_windows=default::false -suggestion=default::[not_specified]
-timing=default::[not_specified] -verbose=default::[not_specified]
usage
runtime=0.205 secs
usage_count
qor_summary=4

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -merge_exceptions =default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified]
-return_string=default::[not_specified] -slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-17=921

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") bram=0.321424 confidence_level_clock_activity=Low
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=1.044932
die=xc7z020clg400-2 dsp_output_toggle=12.500000 dynamic=22.899777 effective_thetaja=11.53
enable_probability=0.990000 family=zynq ff_toggle=12.500000 flow_state=routed
heatsink=none i/o=5.832398 input_toggle=12.500000 junction_temp=125.0 (C)
logic=8.573805 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=23.944709
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=clg400
pct_clock_constrained=3.000000 pct_inputs_defined=0 platform=nt64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=8.172149 simulation_file=None speedgrade=-2
static_prob=False temp_grade=commercial thetajb=7.4 (C/W) thetasa=0.0 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=11.53 user_junc_temp=125.0 (C)
user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000
vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.213284 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.099899
vccaux_total_current=0.313183 vccaux_voltage=1.800000 vccbram_dynamic_current=0.014832 vccbram_static_current=0.028747
vccbram_total_current=0.043579 vccbram_voltage=1.000000 vccint_dynamic_current=17.064547 vccint_static_current=0.300316
vccint_total_current=17.364862 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=1.647420 vcco33_static_current=0.001000
vcco33_total_current=1.648420 vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000 vcco_ddr_static_current=0.000000
vcco_ddr_total_current=0.000000 vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000 vcco_mio0_static_current=0.000000
vcco_mio0_total_current=0.000000 vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000 vcco_mio1_static_current=0.000000
vcco_mio1_total_current=0.000000 vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000 vccpaux_static_current=0.010330
vccpaux_total_current=0.010330 vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000 vccpint_static_current=0.472757
vccpint_total_current=0.472757 vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000 vccpll_static_current=0.003000
vccpll_total_current=0.003000 vccpll_voltage=1.800000 version=2021.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_prohibited=0 bufgctrl_used=1
bufgctrl_util_percentage=3.13 bufhce_available=72 bufhce_fixed=0 bufhce_prohibited=0
bufhce_used=0 bufhce_util_percentage=0.00 bufio_available=16 bufio_fixed=0
bufio_prohibited=0 bufio_used=0 bufio_util_percentage=0.00 bufmrce_available=8
bufmrce_fixed=0 bufmrce_prohibited=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_prohibited=0 bufr_used=0
bufr_util_percentage=0.00 mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_prohibited=0
mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00 plle2_adv_available=4 plle2_adv_fixed=0
plle2_adv_prohibited=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_prohibited=0 dsps_used=0
dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_prohibited=0 block_ram_tile_used=2
block_ram_tile_util_percentage=1.43 ramb18_available=280 ramb18_fixed=0 ramb18_prohibited=0
ramb18_used=2 ramb18_util_percentage=0.71 ramb18e1_only_used=2 ramb36_fifo_available=140
ramb36_fifo_fixed=0 ramb36_fifo_prohibited=0 ramb36_fifo_used=1 ramb36_fifo_util_percentage=0.71
ramb36e1_only_used=1
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=174
fdre_functional_category=Flop & Latch fdre_used=844 fdse_functional_category=Flop & Latch fdse_used=53
ibuf_functional_category=IO ibuf_used=3 lut1_functional_category=LUT lut1_used=141
lut2_functional_category=LUT lut2_used=212 lut3_functional_category=LUT lut3_used=380
lut4_functional_category=LUT lut4_used=304 lut5_functional_category=LUT lut5_used=563
lut6_functional_category=LUT lut6_used=1420 muxf7_functional_category=MuxFx muxf7_used=1
obuf_functional_category=IO obuf_used=5 ramb18e1_functional_category=Block Memory ramb18e1_used=2
ramb36e1_functional_category=Block Memory ramb36e1_used=1 srl16e_functional_category=Distributed Memory srl16e_used=19
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_prohibited=0 f7_muxes_used=1
f7_muxes_util_percentage=<0.01 f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_prohibited=0
f8_muxes_used=0 f8_muxes_util_percentage=0.00 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_prohibited=0 lut_as_logic_used=2654
lut_as_logic_util_percentage=4.99 lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_prohibited=0
lut_as_memory_used=11 lut_as_memory_util_percentage=0.06 lut_as_shift_register_fixed=0 lut_as_shift_register_used=11
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_prohibited=0 register_as_flip_flop_used=897
register_as_flip_flop_util_percentage=0.84 register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_prohibited=0
register_as_latch_used=0 register_as_latch_util_percentage=0.00 slice_luts_available=53200 slice_luts_fixed=0
slice_luts_prohibited=0 slice_luts_used=2665 slice_luts_util_percentage=5.01 slice_registers_available=106400
slice_registers_fixed=0 slice_registers_prohibited=0 slice_registers_used=897 slice_registers_util_percentage=0.84
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_prohibited=0 lut_as_logic_used=2654 lut_as_logic_util_percentage=4.99 lut_as_memory_available=17400
lut_as_memory_fixed=0 lut_as_memory_prohibited=0 lut_as_memory_used=11 lut_as_memory_util_percentage=0.06
lut_as_shift_register_fixed=0 lut_as_shift_register_used=11 lut_in_front_of_the_register_is_unused_available=11 lut_in_front_of_the_register_is_unused_fixed=11
lut_in_front_of_the_register_is_unused_prohibited=11 lut_in_front_of_the_register_is_unused_used=96 lut_in_front_of_the_register_is_used_available=96 lut_in_front_of_the_register_is_used_fixed=96
lut_in_front_of_the_register_is_used_prohibited=96 lut_in_front_of_the_register_is_used_used=142 register_driven_from_outside_the_slice_fixed=142 register_driven_from_outside_the_slice_used=238
register_driven_from_within_the_slice_fixed=238 register_driven_from_within_the_slice_used=659 slice_available=13300 slice_fixed=0
slice_prohibited=0 slice_registers_available=106400 slice_registers_fixed=0 slice_registers_prohibited=0
slice_registers_used=897 slice_registers_util_percentage=0.84 slice_used=803 slice_util_percentage=6.04
slicel_fixed=0 slicel_used=553 slicem_fixed=0 slicem_used=250
unique_control_sets_available=13300 unique_control_sets_fixed=13300 unique_control_sets_prohibited=0 unique_control_sets_used=45
unique_control_sets_util_percentage=0.34 using_o5_and_o6_available=0.34 using_o5_and_o6_fixed=0.34 using_o5_and_o6_prohibited=0.34
using_o5_and_o6_used=8 using_o5_output_only_available=8 using_o5_output_only_fixed=8 using_o5_output_only_prohibited=8
using_o5_output_only_used=2 using_o6_output_only_available=2 using_o6_output_only_fixed=2 using_o6_output_only_prohibited=2
using_o6_output_only_used=1
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_prohibited=0 bscane2_used=0
bscane2_util_percentage=0.00 capturee2_available=1 capturee2_fixed=0 capturee2_prohibited=0
capturee2_used=0 capturee2_util_percentage=0.00 dna_port_available=1 dna_port_fixed=0
dna_port_prohibited=0 dna_port_used=0 dna_port_util_percentage=0.00 efuse_usr_available=1
efuse_usr_fixed=0 efuse_usr_prohibited=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_prohibited=0 frame_ecce2_used=0
frame_ecce2_util_percentage=0.00 icape2_available=2 icape2_fixed=0 icape2_prohibited=0
icape2_used=0 icape2_util_percentage=0.00 startupe2_available=1 startupe2_fixed=0
startupe2_prohibited=0 startupe2_used=0 startupe2_util_percentage=0.00 xadc_available=1
xadc_fixed=0 xadc_prohibited=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -incremental=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified]
-max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1
-max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified]
-no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7z020clg400-2
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=risc_axi_v5_top_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:52s hls_ip=0 memory_gain=166.086MB memory_peak=1302.746MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::