risc_axi_v5_top_xbar_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/sim/risc_axi_v5_top_xbar_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v