//IP Functional Simulation Model //VERSION_BEGIN 13.1 cbx_mgl 2013:10:24:09:16:30:SJ cbx_simgen 2013:10:24:09:15:20:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = altera_pll 1 `timescale 1 ps / 1 ps module clk100M ( locked, outclk_0, outclk_1, refclk, rst) /* synthesis synthesis_clearbox=1 */; output locked; output outclk_0; output outclk_1; input refclk; input rst; wire wire_clk100m_altera_pll_altera_pll_i_1096_locked; wire [1:0] wire_clk100m_altera_pll_altera_pll_i_1096_outclk; altera_pll clk100m_altera_pll_altera_pll_i_1096 ( .fbclk(1'b0), .locked(wire_clk100m_altera_pll_altera_pll_i_1096_locked), .outclk(wire_clk100m_altera_pll_altera_pll_i_1096_outclk), .refclk(refclk), .rst(rst)); defparam clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en0 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en1 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en10 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en11 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en12 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en13 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en14 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en15 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en16 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en17 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en2 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en3 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en4 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en5 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en6 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en7 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en8 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en9 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div0 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div1 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div10 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div11 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div12 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div13 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div14 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div15 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div16 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div17 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div2 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div3 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div4 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div5 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div6 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div7 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div8 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div9 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src0 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src1 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src10 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src11 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src12 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src13 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src14 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src15 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src16 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src17 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src2 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src3 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src4 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src5 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src6 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src7 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src8 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src9 = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div0 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div1 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div10 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div11 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div12 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div13 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div14 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div15 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div16 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div17 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div2 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div3 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div4 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div5 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div6 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div7 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div8 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div9 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en0 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en1 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en10 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en11 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en12 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en13 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en14 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en15 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en16 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en17 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en2 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en3 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en4 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en5 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en6 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en7 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en8 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en9 = "false", clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst0 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst1 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst10 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst11 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst12 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst13 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst14 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst15 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst16 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst17 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst2 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst3 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst4 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst5 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst6 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst7 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst8 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst9 = 0, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst0 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst1 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst10 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst11 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst12 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst13 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst14 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst15 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst16 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst17 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst2 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst3 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst4 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst5 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst6 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst7 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst8 = 1, clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst9 = 1, clk100m_altera_pll_altera_pll_i_1096.data_rate = 0, clk100m_altera_pll_altera_pll_i_1096.deserialization_factor = 4, clk100m_altera_pll_altera_pll_i_1096.duty_cycle0 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle1 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle10 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle11 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle12 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle13 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle14 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle15 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle16 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle17 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle2 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle3 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle4 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle5 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle6 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle7 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle8 = 50, clk100m_altera_pll_altera_pll_i_1096.duty_cycle9 = 50, clk100m_altera_pll_altera_pll_i_1096.fractional_vco_multiplier = "false", clk100m_altera_pll_altera_pll_i_1096.m_cnt_bypass_en = "false", clk100m_altera_pll_altera_pll_i_1096.m_cnt_hi_div = 1, clk100m_altera_pll_altera_pll_i_1096.m_cnt_lo_div = 1, clk100m_altera_pll_altera_pll_i_1096.m_cnt_odd_div_duty_en = "false", clk100m_altera_pll_altera_pll_i_1096.mimic_fbclk_type = "gclk", clk100m_altera_pll_altera_pll_i_1096.n_cnt_bypass_en = "false", clk100m_altera_pll_altera_pll_i_1096.n_cnt_hi_div = 1, clk100m_altera_pll_altera_pll_i_1096.n_cnt_lo_div = 1, clk100m_altera_pll_altera_pll_i_1096.n_cnt_odd_div_duty_en = "false", clk100m_altera_pll_altera_pll_i_1096.number_of_clocks = 2, clk100m_altera_pll_altera_pll_i_1096.operation_mode = "direct", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "50.000000 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency1 = "75.000000 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency10 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency11 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency12 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency13 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency14 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency15 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency16 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency17 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency2 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency3 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency4 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency5 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency6 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency7 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency8 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency9 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.phase_shift0 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift1 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift10 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift11 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift12 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift13 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift14 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift15 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift16 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift17 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift2 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift3 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift4 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift5 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift6 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift7 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift8 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.phase_shift9 = "0 ps", clk100m_altera_pll_altera_pll_i_1096.pll_auto_clk_sw_en = "false", clk100m_altera_pll_altera_pll_i_1096.pll_bwctrl = 0, clk100m_altera_pll_altera_pll_i_1096.pll_clk_loss_sw_en = "false", clk100m_altera_pll_altera_pll_i_1096.pll_clk_sw_dly = 0, clk100m_altera_pll_altera_pll_i_1096.pll_clkin_0_src = "clk_0", clk100m_altera_pll_altera_pll_i_1096.pll_clkin_1_src = "clk_0", clk100m_altera_pll_altera_pll_i_1096.pll_cp_current = 0, clk100m_altera_pll_altera_pll_i_1096.pll_dsm_out_sel = "1st_order", clk100m_altera_pll_altera_pll_i_1096.pll_fbclk_mux_1 = "glb", clk100m_altera_pll_altera_pll_i_1096.pll_fbclk_mux_2 = "fb_1", clk100m_altera_pll_altera_pll_i_1096.pll_fractional_cout = 24, clk100m_altera_pll_altera_pll_i_1096.pll_fractional_division = 1, clk100m_altera_pll_altera_pll_i_1096.pll_m_cnt_in_src = "ph_mux_clk", clk100m_altera_pll_altera_pll_i_1096.pll_manu_clk_sw_en = "false", clk100m_altera_pll_altera_pll_i_1096.pll_output_clk_frequency = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.pll_subtype = "General", clk100m_altera_pll_altera_pll_i_1096.pll_type = "General", clk100m_altera_pll_altera_pll_i_1096.pll_vco_div = 1, clk100m_altera_pll_altera_pll_i_1096.pll_vcoph_div = 1, clk100m_altera_pll_altera_pll_i_1096.refclk1_frequency = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.reference_clock_frequency = "50.0 MHz", clk100m_altera_pll_altera_pll_i_1096.sim_additional_refclk_cycles_to_lock = 0; assign locked = wire_clk100m_altera_pll_altera_pll_i_1096_locked, outclk_0 = wire_clk100m_altera_pll_altera_pll_i_1096_outclk[0], outclk_1 = wire_clk100m_altera_pll_altera_pll_i_1096_outclk[1]; endmodule //clk100M //synopsys translate_on //VALID FILE