/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
**   this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
**   this list of conditions and the following disclaimer in the documentation
**   and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
**   derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/

/*
* verilog_assignment.h
  修改记录：
    202106132056: rxh, initial version
*/

#ifndef __VERILOG_ASSIGNMENT_H
#define __VERILOG_ASSIGNMENT_H

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include "guid.h"

DEFINE_GUID(CLSID_VERILOG_ASSIGNMENT, 0x63b29bb6, 0xec02, 0x4ae9, 0x9b, 0xef, 0x65, 0x94, 0xf5, 0x46, 0xfd, 0xb9);


typedef struct _s_verilog_Assignment {
    int assignmenttype;
    IDListVarPtr hierarchical_identifier;
    IDListVarPtr element_select;
    int range_type;
    int constelementsel;
    IVerilogNode** expr;
    IDListVarPtr attributes;
}verilog_Assignment;

HOBJECT verilogparseCreateAssignment(
    int assignmenttype,
    IDListVarPtr hierarchical_identifier,
    IDListVarPtr element_select,
    int range_type,
    int constelementsel,
    HOBJECT expr,
    IDListVarPtr attributes
    );

verilog_Assignment* verilogAssignmentGetData(HOBJECT object);

#endif    

#ifdef __cplusplus
}
#endif

#endif