/* **HDL4SE: 软件Verilog综合仿真平台 ** Copyright (C) 2021-2021, raoxianhong ** LCOM: 轻量级组件对象模型 ** Copyright (C) 2021-2021, raoxianhong ** All rights reserved. ** ** Redistribution and use in source and binary forms, with or without ** modification, are permitted provided that the following conditions are met: ** ** * Redistributions of source code must retain the above copyright notice, ** this list of conditions and the following disclaimer. ** * Redistributions in binary form must reproduce the above copyright notice, ** this list of conditions and the following disclaimer in the documentation ** and/or other materials provided with the distribution. ** * The name of the author may be used to endorse or promote products ** derived from this software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ** THE POSSIBILITY OF SUCH DAMAGE. */ /* * Created by HDL4SE @ Thu Jul 1 06:39:07 2021 * Don't edit it. */ #include "stdlib.h" #include "stdio.h" #include "string.h" #include "object.h" #include "dlist.h" #include "bignumber.h" #include "hdl4secell.h" #include "conststring.h" #include "verilog_parsetree.h" IHDL4SEUnit** hdl4seCreate_0010(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module turnleft */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[20]; int __netswidth[20]; IHDL4SEUnit** modules[5]; int __portswidth[2]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "inblock", 64, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 64; /* 1*/ objectCall4(module, AddPort, "outblock", 64, 1, PORT_DIRECT_OUTPUT); /* 1*/ __portswidth[1] = 64; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b00"); __netswidth[0] = 4; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b01"); __netswidth[1] = 4; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b02"); __netswidth[2] = 4; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b03"); __netswidth[3] = 4; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b10"); __netswidth[4] = 4; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b11"); __netswidth[5] = 4; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b12"); __netswidth[6] = 4; nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b13"); __netswidth[7] = 4; nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b20"); __netswidth[8] = 4; nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b21"); __netswidth[9] = 4; nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b22"); __netswidth[10] = 4; nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b23"); __netswidth[11] = 4; nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b30"); __netswidth[12] = 4; nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b31"); __netswidth[13] = 4; nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b32"); __netswidth[14] = 4; nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "b33"); __netswidth[15] = 4; nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line0"); __netswidth[16] = 16; nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line1"); __netswidth[17] = 16; nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line2"); __netswidth[18] = 16; nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line3"); __netswidth[19] = 16; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "0234ECE7-A9C5-406B-9AE7-4841EA0DF7C9", "4, 4, 4, 4", "bindline0"); objectCall3(modules[0], Connect, 0, nets[3], 0); objectCall3(modules[0], Connect, 1, nets[7], 0); objectCall3(modules[0], Connect, 2, nets[11], 0); objectCall3(modules[0], Connect, 3, nets[15], 0); objectCall3(nets[16], Connect, 0, modules[0], 4); modules[ 1] = hdl4seCreateUnit2(module, "0234ECE7-A9C5-406B-9AE7-4841EA0DF7C9", "4, 4, 4, 4", "bindline1"); objectCall3(modules[1], Connect, 0, nets[2], 0); objectCall3(modules[1], Connect, 1, nets[6], 0); objectCall3(modules[1], Connect, 2, nets[10], 0); objectCall3(modules[1], Connect, 3, nets[14], 0); objectCall3(nets[17], Connect, 0, modules[1], 4); modules[ 2] = hdl4seCreateUnit2(module, "0234ECE7-A9C5-406B-9AE7-4841EA0DF7C9", "4, 4, 4, 4", "bindline2"); objectCall3(modules[2], Connect, 0, nets[1], 0); objectCall3(modules[2], Connect, 1, nets[5], 0); objectCall3(modules[2], Connect, 2, nets[9], 0); objectCall3(modules[2], Connect, 3, nets[13], 0); objectCall3(nets[18], Connect, 0, modules[2], 4); modules[ 3] = hdl4seCreateUnit2(module, "0234ECE7-A9C5-406B-9AE7-4841EA0DF7C9", "4, 4, 4, 4", "bindline3"); objectCall3(modules[3], Connect, 0, nets[0], 0); objectCall3(modules[3], Connect, 1, nets[4], 0); objectCall3(modules[3], Connect, 2, nets[8], 0); objectCall3(modules[3], Connect, 3, nets[12], 0); objectCall3(nets[19], Connect, 0, modules[3], 4); modules[ 4] = hdl4seCreateUnit2(module, "0234ECE7-A9C5-406B-9AE7-4841EA0DF7C9", "16, 16, 16, 16", "bindline"); objectCall3(modules[4], Connect, 0, nets[16], 0); objectCall3(modules[4], Connect, 1, nets[17], 0); objectCall3(modules[4], Connect, 2, nets[18], 0); objectCall3(modules[4], Connect, 3, nets[19], 0); objectCall3(unit, Connect, 1, modules[4], 4); /* 持续性赋值 */ /* assign b00 = inblock [3:0] ; */ IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 0", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, unit, 0); objectCall3(nets[0], Connect, 0, tempvar_0, 1); /* assign b01 = inblock [7:4] ; */ IHDL4SEUnit** tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 4", "tempvar_1"); objectCall3(tempvar_1, Connect, 0, unit, 0); objectCall3(nets[1], Connect, 0, tempvar_1, 1); /* assign b02 = inblock [11:8] ; */ IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 8", "tempvar_2"); objectCall3(tempvar_2, Connect, 0, unit, 0); objectCall3(nets[2], Connect, 0, tempvar_2, 1); /* assign b03 = inblock [15:12] ; */ IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 12", "tempvar_3"); objectCall3(tempvar_3, Connect, 0, unit, 0); objectCall3(nets[3], Connect, 0, tempvar_3, 1); /* assign b10 = inblock [19:16] ; */ IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 16", "tempvar_4"); objectCall3(tempvar_4, Connect, 0, unit, 0); objectCall3(nets[4], Connect, 0, tempvar_4, 1); /* assign b11 = inblock [23:20] ; */ IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 20", "tempvar_5"); objectCall3(tempvar_5, Connect, 0, unit, 0); objectCall3(nets[5], Connect, 0, tempvar_5, 1); /* assign b12 = inblock [27:24] ; */ IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 24", "tempvar_6"); objectCall3(tempvar_6, Connect, 0, unit, 0); objectCall3(nets[6], Connect, 0, tempvar_6, 1); /* assign b13 = inblock [31:28] ; */ IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 28", "tempvar_7"); objectCall3(tempvar_7, Connect, 0, unit, 0); objectCall3(nets[7], Connect, 0, tempvar_7, 1); /* assign b20 = inblock [35:32] ; */ IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 32", "tempvar_8"); objectCall3(tempvar_8, Connect, 0, unit, 0); objectCall3(nets[8], Connect, 0, tempvar_8, 1); /* assign b21 = inblock [39:36] ; */ IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 36", "tempvar_9"); objectCall3(tempvar_9, Connect, 0, unit, 0); objectCall3(nets[9], Connect, 0, tempvar_9, 1); /* assign b22 = inblock [43:40] ; */ IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 40", "tempvar_10"); objectCall3(tempvar_10, Connect, 0, unit, 0); objectCall3(nets[10], Connect, 0, tempvar_10, 1); /* assign b23 = inblock [47:44] ; */ IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 44", "tempvar_11"); objectCall3(tempvar_11, Connect, 0, unit, 0); objectCall3(nets[11], Connect, 0, tempvar_11, 1); /* assign b30 = inblock [51:48] ; */ IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 48", "tempvar_12"); objectCall3(tempvar_12, Connect, 0, unit, 0); objectCall3(nets[12], Connect, 0, tempvar_12, 1); /* assign b31 = inblock [55:52] ; */ IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 52", "tempvar_13"); objectCall3(tempvar_13, Connect, 0, unit, 0); objectCall3(nets[13], Connect, 0, tempvar_13, 1); /* assign b32 = inblock [59:56] ; */ IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 56", "tempvar_14"); objectCall3(tempvar_14, Connect, 0, unit, 0); objectCall3(nets[14], Connect, 0, tempvar_14, 1); /* assign b33 = inblock [63:60] ; */ IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 60", "tempvar_15"); objectCall3(tempvar_15, Connect, 0, unit, 0); objectCall3(nets[15], Connect, 0, tempvar_15, 1); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_0012(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module teris_ctrl */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[62]; int __netswidth[62]; IHDL4SEUnit** modules[30]; int __portswidth[13]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "nwReset", 1, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 1; /* 2*/ objectCall4(module, AddPort, "bKeyData", 32, 1, PORT_DIRECT_INPUT ); /* 2*/ __portswidth[2] = 32; /* 3*/ objectCall4(module, AddPort, "wStateComplete", 1, 1, PORT_DIRECT_INPUT ); /* 3*/ __portswidth[3] = 1; /* 4*/ objectCall4(module, AddPort, "bState", 4, 1, PORT_DIRECT_OUTPUT); /* 4*/ __portswidth[4] = 4; /* 5*/ objectCall4(module, AddPort, "bScore", 32, 1, PORT_DIRECT_OUTPUT); /* 5*/ __portswidth[5] = 32; /* 6*/ objectCall4(module, AddPort, "bSpeed", 32, 1, PORT_DIRECT_OUTPUT); /* 6*/ __portswidth[6] = 32; /* 7*/ objectCall4(module, AddPort, "bLevel", 32, 1, PORT_DIRECT_OUTPUT); /* 7*/ __portswidth[7] = 32; /* 8*/ objectCall4(module, AddPort, "bNextBlock", 64, 1, PORT_DIRECT_OUTPUT); /* 8*/ __portswidth[8] = 64; /* 9*/ objectCall4(module, AddPort, "bCurBlock", 64, 1, PORT_DIRECT_OUTPUT); /* 9*/ __portswidth[9] = 64; /* 10*/ objectCall4(module, AddPort, "bCurBlockPos", 16, 1, PORT_DIRECT_OUTPUT); /* 10*/ __portswidth[10] = 16; /* 11*/ objectCall4(module, AddPort, "bResult", 32, 1, PORT_DIRECT_INPUT ); /* 11*/ __portswidth[11] = 32; /* 12*/ objectCall4(module, AddPort, "bNewNextBlock", 64, 1, PORT_DIRECT_INPUT ); /* 12*/ __portswidth[12] = 64; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "outputx"); __netswidth[0] = 8; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "outputy"); __netswidth[1] = 8; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "wirein_state"); __netswidth[2] = 4; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "wireout_state"); __netswidth[3] = 4; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "stateAfterFlushToDisp"); __netswidth[4] = 4; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "stateAfterCheckBlockCanSetTo"); __netswidth[5] = 4; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "stateAfterCheckLine"); __netswidth[6] = 4; nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "stateAfterCheckKey"); __netswidth[7] = 4; nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "nextstate"); __netswidth[8] = 4; nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_testx"); __netswidth[9] = 8; nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_testx"); __netswidth[10] = 8; nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "testxwencheckkey"); __netswidth[11] = 8; nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_testy"); __netswidth[12] = 8; nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_testy"); __netswidth[13] = 8; nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "testywencheckkey"); __netswidth[14] = 8; nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_testid"); __netswidth[15] = 8; nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_testid"); __netswidth[16] = 8; nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "testidwhencheckkey"); __netswidth[17] = 8; nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_startline"); __netswidth[18] = 8; nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_startline"); __netswidth[19] = 8; nets[ 20] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wirein_checklinecount"); __netswidth[20] = 32; nets[ 21] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_checklinecount"); __netswidth[21] = 32; nets[ 22] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "checklinecountAfterCheckline"); __netswidth[22] = 32; nets[ 23] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_testparam"); __netswidth[23] = 8; nets[ 24] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_testparam"); __netswidth[24] = 8; nets[ 25] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "scoreAfterCheckLine"); __netswidth[25] = 32; nets[ 26] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "scoreAfterCheckKey"); __netswidth[26] = 32; nets[ 27] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wirein_score"); __netswidth[27] = 32; nets[ 28] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_score"); __netswidth[28] = 32; nets[ 29] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "linescore"); __netswidth[29] = 32; nets[ 30] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "levelAfterCheckLine"); __netswidth[30] = 32; nets[ 31] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wirein_level"); __netswidth[31] = 32; nets[ 32] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_level"); __netswidth[32] = 32; nets[ 33] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "nextlevel"); __netswidth[33] = 32; nets[ 34] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wirein_speed"); __netswidth[34] = 32; nets[ 35] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_speed"); __netswidth[35] = 32; nets[ 36] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "scorediv4"); __netswidth[36] = 32; nets[ 37] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wirein_tick"); __netswidth[37] = 32; nets[ 38] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_tick"); __netswidth[38] = 32; nets[ 39] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "curposxAfterCheckKey"); __netswidth[39] = 8; nets[ 40] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "curposxAfterCheckLine"); __netswidth[40] = 8; nets[ 41] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_curposx"); __netswidth[41] = 8; nets[ 42] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_curposx"); __netswidth[42] = 8; nets[ 43] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "nextblockx"); __netswidth[43] = 8; nets[ 44] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "curposyAfterCheckKey"); __netswidth[44] = 8; nets[ 45] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "curposyAfterCheckLine"); __netswidth[45] = 8; nets[ 46] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "cursoryAfterCheckBlock"); __netswidth[46] = 8; nets[ 47] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_curposy"); __netswidth[47] = 8; nets[ 48] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_curposy"); __netswidth[48] = 8; nets[ 49] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "nextblocky"); __netswidth[49] = 8; nets[ 50] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockWhenFlushToDisp"); __netswidth[50] = 64; nets[ 51] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockAfterCheckBlock"); __netswidth[51] = 64; nets[ 52] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockAfterCheckLine"); __netswidth[52] = 64; nets[ 53] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "wirein_curblock"); __netswidth[53] = 64; nets[ 54] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "wireout_curblock"); __netswidth[54] = 64; nets[ 55] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockturnleft"); __netswidth[55] = 64; nets[ 56] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockturnright"); __netswidth[56] = 64; nets[ 57] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "wirein_nextblock"); __netswidth[57] = 64; nets[ 58] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "wireout_nextblock"); __netswidth[58] = 64; nets[ 59] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wirein_key"); __netswidth[59] = 32; nets[ 60] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_key"); __netswidth[60] = 32; nets[ 61] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "cur_key"); __netswidth[61] = 32; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "8, 8", "bindpos"); objectCall3(modules[0], Connect, 0, nets[0], 0); objectCall3(modules[0], Connect, 1, nets[1], 0); objectCall3(unit, Connect, 10, modules[0], 2); modules[ 1] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "4", "terris_ctrlstate"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(modules[1], Connect, 1, nets[2], 0); objectCall3(nets[3], Connect, 0, modules[1], 2); modules[ 2] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "4", "mux_nextstate"); objectCall3(modules[2], Connect, 0, nets[3], 0); IHDL4SEUnit** tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 7", "tempvar_1"); IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_2"); IHDL4SEUnit **tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, unit, 3); objectCall3(tempvar_0, Connect, 1, tempvar_2, 0); objectCall3(tempvar_0, Connect, 2, tempvar_1, 0); objectCall3(modules[2], Connect, 1, tempvar_0, 3); objectCall3(modules[2], Connect, 2, nets[4], 0); objectCall3(modules[2], Connect, 3, nets[7], 0); objectCall3(modules[2], Connect, 4, nets[5], 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 5", "tempvar_4"); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_5"); IHDL4SEUnit **tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_3"); objectCall3(tempvar_3, Connect, 0, unit, 3); objectCall3(tempvar_3, Connect, 1, tempvar_5, 0); objectCall3(tempvar_3, Connect, 2, tempvar_4, 0); objectCall3(modules[2], Connect, 5, tempvar_3, 3); objectCall3(modules[2], Connect, 6, nets[6], 0); IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 5", "tempvar_7"); IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 6", "tempvar_8"); IHDL4SEUnit **tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_6"); objectCall3(tempvar_6, Connect, 0, unit, 3); objectCall3(tempvar_6, Connect, 1, tempvar_8, 0); objectCall3(tempvar_6, Connect, 2, tempvar_7, 0); objectCall3(modules[2], Connect, 7, tempvar_6, 3); IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_10"); IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 7", "tempvar_11"); IHDL4SEUnit **tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_9"); objectCall3(tempvar_9, Connect, 0, unit, 3); objectCall3(tempvar_9, Connect, 1, tempvar_11, 0); objectCall3(tempvar_9, Connect, 2, tempvar_10, 0); objectCall3(modules[2], Connect, 8, tempvar_9, 3); objectCall3(nets[8], Connect, 0, modules[2], 9); modules[ 3] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "reg_testx"); objectCall3(modules[3], Connect, 0, unit, 0); objectCall3(modules[3], Connect, 1, nets[9], 0); objectCall3(nets[10], Connect, 0, modules[3], 2); modules[ 4] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "8", "mux_testx"); objectCall3(modules[4], Connect, 0, nets[3], 0); objectCall3(modules[4], Connect, 1, nets[10], 0); objectCall3(modules[4], Connect, 2, nets[10], 0); objectCall3(modules[4], Connect, 3, nets[11], 0); objectCall3(modules[4], Connect, 4, nets[10], 0); objectCall3(modules[4], Connect, 5, nets[10], 0); IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 8", "tempvar_12"); objectCall3(modules[4], Connect, 6, tempvar_12, 0); objectCall3(modules[4], Connect, 7, nets[10], 0); objectCall3(modules[4], Connect, 8, nets[10], 0); objectCall3(nets[9], Connect, 0, modules[4], 9); modules[ 5] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "reg_testy"); objectCall3(modules[5], Connect, 0, unit, 0); objectCall3(modules[5], Connect, 1, nets[12], 0); objectCall3(nets[13], Connect, 0, modules[5], 2); modules[ 6] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "8", "mux_testy"); objectCall3(modules[6], Connect, 0, nets[3], 0); objectCall3(modules[6], Connect, 1, nets[13], 0); objectCall3(modules[6], Connect, 2, nets[13], 0); objectCall3(modules[6], Connect, 3, nets[14], 0); objectCall3(modules[6], Connect, 4, nets[13], 0); objectCall3(modules[6], Connect, 5, nets[13], 0); IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 0", "tempvar_13"); objectCall3(modules[6], Connect, 6, tempvar_13, 0); objectCall3(modules[6], Connect, 7, nets[13], 0); objectCall3(modules[6], Connect, 8, nets[13], 0); objectCall3(nets[12], Connect, 0, modules[6], 9); modules[ 7] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "reg_testid"); objectCall3(modules[7], Connect, 0, unit, 0); objectCall3(modules[7], Connect, 1, nets[15], 0); objectCall3(nets[16], Connect, 0, modules[7], 2); modules[ 8] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "8", "mux_testid"); objectCall3(modules[8], Connect, 0, nets[3], 0); objectCall3(modules[8], Connect, 1, nets[16], 0); objectCall3(modules[8], Connect, 2, nets[16], 0); objectCall3(modules[8], Connect, 3, nets[17], 0); objectCall3(modules[8], Connect, 4, nets[16], 0); objectCall3(modules[8], Connect, 5, nets[16], 0); IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_14"); objectCall3(modules[8], Connect, 6, tempvar_14, 0); objectCall3(modules[8], Connect, 7, nets[16], 0); objectCall3(modules[8], Connect, 8, nets[16], 0); objectCall3(nets[15], Connect, 0, modules[8], 9); modules[ 9] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "reg_startline"); objectCall3(modules[9], Connect, 0, unit, 0); objectCall3(modules[9], Connect, 1, nets[18], 0); objectCall3(nets[19], Connect, 0, modules[9], 2); modules[ 10] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "32", "reg_checklinecount"); objectCall3(modules[10], Connect, 0, unit, 0); objectCall3(modules[10], Connect, 1, nets[20], 0); objectCall3(nets[21], Connect, 0, modules[10], 2); modules[ 11] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "32", "mux_checklinecount"); objectCall3(modules[11], Connect, 0, nets[3], 0); objectCall3(modules[11], Connect, 1, nets[21], 0); objectCall3(modules[11], Connect, 2, nets[21], 0); objectCall3(modules[11], Connect, 3, nets[21], 0); objectCall3(modules[11], Connect, 4, nets[21], 0); IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 0", "tempvar_15"); objectCall3(modules[11], Connect, 5, tempvar_15, 0); objectCall3(modules[11], Connect, 6, nets[22], 0); objectCall3(modules[11], Connect, 7, nets[21], 0); objectCall3(modules[11], Connect, 8, nets[21], 0); objectCall3(nets[20], Connect, 0, modules[11], 9); modules[ 12] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "reg_testparam"); objectCall3(modules[12], Connect, 0, unit, 0); objectCall3(modules[12], Connect, 1, nets[23], 0); objectCall3(nets[24], Connect, 0, modules[12], 2); modules[ 13] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "32", "terris_score"); objectCall3(modules[13], Connect, 0, unit, 0); objectCall3(modules[13], Connect, 1, nets[27], 0); objectCall3(nets[28], Connect, 0, modules[13], 2); modules[ 14] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "32", "mux_score"); objectCall3(modules[14], Connect, 0, nets[3], 0); IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hc8", "tempvar_16"); objectCall3(modules[14], Connect, 1, tempvar_16, 0); objectCall3(modules[14], Connect, 2, nets[28], 0); objectCall3(modules[14], Connect, 3, nets[26], 0); objectCall3(modules[14], Connect, 4, nets[28], 0); objectCall3(modules[14], Connect, 5, nets[28], 0); objectCall3(modules[14], Connect, 6, nets[25], 0); objectCall3(modules[14], Connect, 7, nets[28], 0); objectCall3(modules[14], Connect, 8, nets[28], 0); objectCall3(nets[27], Connect, 0, modules[14], 9); modules[ 15] = hdl4seCreateUnit2(module, "041F3AA1-97CD-4412-9E8E-D04ADF291AE2", "32", "mux_linescore"); IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_18"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[21], 2, 0, BINOP_SUB); IHDL4SEUnit **tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_17"); objectCall3(tempvar_17, Connect, 0, nets[21], 0); objectCall3(tempvar_17, Connect, 1, tempvar_18, 0); objectCall3(modules[15], Connect, 0, tempvar_17, 2); IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'ha", "tempvar_19"); objectCall3(modules[15], Connect, 1, tempvar_19, 0); IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h28", "tempvar_20"); objectCall3(modules[15], Connect, 2, tempvar_20, 0); IHDL4SEUnit** tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'ha0", "tempvar_21"); objectCall3(modules[15], Connect, 3, tempvar_21, 0); IHDL4SEUnit** tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h280", "tempvar_22"); objectCall3(modules[15], Connect, 4, tempvar_22, 0); objectCall3(nets[29], Connect, 0, modules[15], 5); modules[ 16] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "32", "terris_level"); objectCall3(modules[16], Connect, 0, unit, 0); objectCall3(modules[16], Connect, 1, nets[31], 0); objectCall3(nets[32], Connect, 0, modules[16], 2); modules[ 17] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "32", "mux_level"); objectCall3(modules[17], Connect, 0, nets[3], 0); IHDL4SEUnit** tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_23"); objectCall3(modules[17], Connect, 1, tempvar_23, 0); objectCall3(modules[17], Connect, 2, nets[32], 0); objectCall3(modules[17], Connect, 3, nets[32], 0); objectCall3(modules[17], Connect, 4, nets[32], 0); objectCall3(modules[17], Connect, 5, nets[32], 0); objectCall3(modules[17], Connect, 6, nets[30], 0); objectCall3(modules[17], Connect, 7, nets[32], 0); objectCall3(modules[17], Connect, 8, nets[32], 0); objectCall3(nets[33], Connect, 0, modules[17], 9); modules[ 18] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "32", "terris_speed"); objectCall3(modules[18], Connect, 0, unit, 0); objectCall3(modules[18], Connect, 1, nets[34], 0); objectCall3(nets[35], Connect, 0, modules[18], 2); modules[ 19] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "32", "terris_tick"); objectCall3(modules[19], Connect, 0, unit, 0); objectCall3(modules[19], Connect, 1, nets[37], 0); objectCall3(nets[38], Connect, 0, modules[19], 2); modules[ 20] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "terris_curposx"); objectCall3(modules[20], Connect, 0, unit, 0); objectCall3(modules[20], Connect, 1, nets[41], 0); objectCall3(nets[42], Connect, 0, modules[20], 2); modules[ 21] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "8", "mux_blockx"); objectCall3(modules[21], Connect, 0, nets[3], 0); IHDL4SEUnit** tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 8", "tempvar_24"); objectCall3(modules[21], Connect, 1, tempvar_24, 0); IHDL4SEUnit** tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_27"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[54], 64, 1, BINOP_EQ); IHDL4SEUnit **tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_26"); objectCall3(tempvar_26, Connect, 0, nets[54], 0); objectCall3(tempvar_26, Connect, 1, tempvar_27, 0); IHDL4SEUnit** tempvar_28 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 8", "tempvar_28"); IHDL4SEUnit **tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_25"); objectCall3(tempvar_25, Connect, 0, tempvar_26, 2); objectCall3(tempvar_25, Connect, 1, nets[42], 0); objectCall3(tempvar_25, Connect, 2, tempvar_28, 0); objectCall3(modules[21], Connect, 2, tempvar_25, 3); objectCall3(modules[21], Connect, 3, nets[39], 0); IHDL4SEUnit **tempvar_29 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_29"); objectCall3(tempvar_29, Connect, 0, unit, 11); objectCall3(tempvar_29, Connect, 1, nets[42], 0); objectCall3(tempvar_29, Connect, 2, nets[10], 0); objectCall3(modules[21], Connect, 4, tempvar_29, 3); objectCall3(modules[21], Connect, 5, nets[42], 0); objectCall3(modules[21], Connect, 6, nets[40], 0); objectCall3(modules[21], Connect, 7, nets[42], 0); objectCall3(modules[21], Connect, 8, nets[42], 0); objectCall3(nets[43], Connect, 0, modules[21], 9); modules[ 22] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "terris_curposy"); objectCall3(modules[22], Connect, 0, unit, 0); objectCall3(modules[22], Connect, 1, nets[47], 0); objectCall3(nets[48], Connect, 0, modules[22], 2); modules[ 23] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "8", "mux_blocky"); objectCall3(modules[23], Connect, 0, nets[3], 0); IHDL4SEUnit** tempvar_30 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 0", "tempvar_30"); objectCall3(modules[23], Connect, 1, tempvar_30, 0); IHDL4SEUnit** tempvar_33 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_33"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[54], 64, 1, BINOP_EQ); IHDL4SEUnit **tempvar_32 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_32"); objectCall3(tempvar_32, Connect, 0, nets[54], 0); objectCall3(tempvar_32, Connect, 1, tempvar_33, 0); IHDL4SEUnit** tempvar_34 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 0", "tempvar_34"); IHDL4SEUnit **tempvar_31 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_31"); objectCall3(tempvar_31, Connect, 0, tempvar_32, 2); objectCall3(tempvar_31, Connect, 1, nets[48], 0); objectCall3(tempvar_31, Connect, 2, tempvar_34, 0); objectCall3(modules[23], Connect, 2, tempvar_31, 3); objectCall3(modules[23], Connect, 3, nets[48], 0); objectCall3(modules[23], Connect, 4, nets[46], 0); objectCall3(modules[23], Connect, 5, nets[48], 0); objectCall3(modules[23], Connect, 6, nets[45], 0); objectCall3(modules[23], Connect, 7, nets[48], 0); objectCall3(modules[23], Connect, 8, nets[48], 0); objectCall3(nets[49], Connect, 0, modules[23], 9); modules[ 24] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "64", "terris_curblock"); objectCall3(modules[24], Connect, 0, unit, 0); objectCall3(modules[24], Connect, 1, nets[53], 0); objectCall3(nets[54], Connect, 0, modules[24], 2); modules[ 25] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "64", "mux_curblock"); objectCall3(modules[25], Connect, 0, nets[3], 0); objectCall3(modules[25], Connect, 1, nets[54], 0); objectCall3(modules[25], Connect, 2, nets[50], 0); objectCall3(modules[25], Connect, 3, nets[54], 0); objectCall3(modules[25], Connect, 4, nets[51], 0); objectCall3(modules[25], Connect, 5, nets[54], 0); objectCall3(modules[25], Connect, 6, nets[52], 0); objectCall3(modules[25], Connect, 7, nets[54], 0); objectCall3(modules[25], Connect, 8, nets[54], 0); objectCall3(nets[53], Connect, 0, modules[25], 9); modules[ 26] = hdl4seCreate_0010(module, "", "curturnleft"); objectCall3(modules[26], Connect, 0, nets[54], 0); objectCall3(nets[55], Connect, 0, modules[26], 1); modules[ 27] = hdl4seCreate_0010(module, "", "curturnright"); objectCall3(modules[27], Connect, 0, nets[54], 0); objectCall3(nets[56], Connect, 0, modules[27], 1); modules[ 28] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "64", "terris_nextblock"); objectCall3(modules[28], Connect, 0, unit, 0); objectCall3(modules[28], Connect, 1, nets[57], 0); objectCall3(nets[58], Connect, 0, modules[28], 2); modules[ 29] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "31", "terris_key"); objectCall3(modules[29], Connect, 0, unit, 0); objectCall3(modules[29], Connect, 1, nets[59], 0); objectCall3(nets[60], Connect, 0, modules[29], 2); /* 持续性赋值 */ /* assign bState = wireout_state; */ objectCall3(unit, Connect, 4, nets[3], 0); /* assign bScore = wireout_score; */ objectCall3(unit, Connect, 5, nets[28], 0); /* assign bSpeed = (32'h1f4-wireout_speed); */ IHDL4SEUnit** tempvar_36 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h1f4", "tempvar_36"); sprintf(__instparam, "%d, %d, %d, %d", 32, __netswidth[35], 0, BINOP_SUB); IHDL4SEUnit **tempvar_35 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_35"); objectCall3(tempvar_35, Connect, 0, tempvar_36, 0); objectCall3(tempvar_35, Connect, 1, nets[35], 0); objectCall3(unit, Connect, 6, tempvar_35, 2); /* assign bLevel = wireout_level; */ objectCall3(unit, Connect, 7, nets[32], 0); /* assign bNextBlock = wireout_nextblock; */ objectCall3(unit, Connect, 8, nets[58], 0); /* assign bCurBlock = ((cur_key [3] )?(curblockturnleft):(wireout_curblock)); */ IHDL4SEUnit** tempvar_38 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 3", "tempvar_38"); objectCall3(tempvar_38, Connect, 0, nets[61], 0); IHDL4SEUnit **tempvar_37 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_37"); objectCall3(tempvar_37, Connect, 0, tempvar_38, 1); objectCall3(tempvar_37, Connect, 1, nets[54], 0); objectCall3(tempvar_37, Connect, 2, nets[55], 0); objectCall3(unit, Connect, 9, tempvar_37, 3); /* assign wirein_state = ((nwReset)?(nextstate):(0)); */ IHDL4SEUnit** tempvar_40 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_40"); IHDL4SEUnit **tempvar_39 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_39"); objectCall3(tempvar_39, Connect, 0, unit, 1); objectCall3(tempvar_39, Connect, 1, tempvar_40, 0); objectCall3(tempvar_39, Connect, 2, nets[8], 0); objectCall3(nets[2], Connect, 0, tempvar_39, 3); /* assign stateAfterFlushToDisp = (((wireout_curblock==64'h0))?(7):(((wStateComplete)?(2):(1)))); */ IHDL4SEUnit** tempvar_43 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_43"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[54], 64, 1, BINOP_EQ); IHDL4SEUnit **tempvar_42 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_42"); objectCall3(tempvar_42, Connect, 0, nets[54], 0); objectCall3(tempvar_42, Connect, 1, tempvar_43, 0); IHDL4SEUnit** tempvar_44 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 7", "tempvar_44"); IHDL4SEUnit** tempvar_46 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 2", "tempvar_46"); IHDL4SEUnit** tempvar_47 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_47"); IHDL4SEUnit **tempvar_45 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "3", "tempvar_45"); objectCall3(tempvar_45, Connect, 0, unit, 3); objectCall3(tempvar_45, Connect, 1, tempvar_47, 0); objectCall3(tempvar_45, Connect, 2, tempvar_46, 0); IHDL4SEUnit **tempvar_41 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_41"); objectCall3(tempvar_41, Connect, 0, tempvar_42, 2); objectCall3(tempvar_41, Connect, 1, tempvar_45, 3); objectCall3(tempvar_41, Connect, 2, tempvar_44, 0); objectCall3(nets[4], Connect, 0, tempvar_41, 3); /* assign stateAfterCheckBlockCanSetTo = ((wStateComplete)?((((wireout_testid==0))?(((bResult)?(1):(4))):((((wireout_testid==4))?(((bResult)?(7):(0))):(1))))):(3)); */ IHDL4SEUnit** tempvar_51 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_51"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[16], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_50 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_50"); objectCall3(tempvar_50, Connect, 0, nets[16], 0); objectCall3(tempvar_50, Connect, 1, tempvar_51, 0); IHDL4SEUnit** tempvar_53 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_53"); IHDL4SEUnit** tempvar_54 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_54"); IHDL4SEUnit **tempvar_52 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_52"); objectCall3(tempvar_52, Connect, 0, unit, 11); objectCall3(tempvar_52, Connect, 1, tempvar_54, 0); objectCall3(tempvar_52, Connect, 2, tempvar_53, 0); IHDL4SEUnit** tempvar_57 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_57"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[16], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_56 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_56"); objectCall3(tempvar_56, Connect, 0, nets[16], 0); objectCall3(tempvar_56, Connect, 1, tempvar_57, 0); IHDL4SEUnit** tempvar_59 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 7", "tempvar_59"); IHDL4SEUnit** tempvar_60 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_60"); IHDL4SEUnit **tempvar_58 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_58"); objectCall3(tempvar_58, Connect, 0, unit, 11); objectCall3(tempvar_58, Connect, 1, tempvar_60, 0); objectCall3(tempvar_58, Connect, 2, tempvar_59, 0); IHDL4SEUnit** tempvar_61 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_61"); IHDL4SEUnit **tempvar_55 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_55"); objectCall3(tempvar_55, Connect, 0, tempvar_56, 2); objectCall3(tempvar_55, Connect, 1, tempvar_61, 0); objectCall3(tempvar_55, Connect, 2, tempvar_58, 3); IHDL4SEUnit **tempvar_49 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_49"); objectCall3(tempvar_49, Connect, 0, tempvar_50, 2); objectCall3(tempvar_49, Connect, 1, tempvar_55, 3); objectCall3(tempvar_49, Connect, 2, tempvar_52, 3); IHDL4SEUnit** tempvar_62 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_62"); IHDL4SEUnit **tempvar_48 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_48"); objectCall3(tempvar_48, Connect, 0, unit, 3); objectCall3(tempvar_48, Connect, 1, tempvar_62, 0); objectCall3(tempvar_48, Connect, 2, tempvar_49, 3); objectCall3(nets[5], Connect, 0, tempvar_48, 3); /* assign stateAfterCheckLine = ((wStateComplete)?((((bResult<24))?(6):(3))):(5)); */ IHDL4SEUnit** tempvar_66 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_66"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[11], 6, 1, BINOP_LT); IHDL4SEUnit **tempvar_65 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_65"); objectCall3(tempvar_65, Connect, 0, unit, 11); objectCall3(tempvar_65, Connect, 1, tempvar_66, 0); IHDL4SEUnit** tempvar_67 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 6", "tempvar_67"); IHDL4SEUnit** tempvar_68 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_68"); IHDL4SEUnit **tempvar_64 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_64"); objectCall3(tempvar_64, Connect, 0, tempvar_65, 2); objectCall3(tempvar_64, Connect, 1, tempvar_68, 0); objectCall3(tempvar_64, Connect, 2, tempvar_67, 0); IHDL4SEUnit** tempvar_69 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 5", "tempvar_69"); IHDL4SEUnit **tempvar_63 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "4", "tempvar_63"); objectCall3(tempvar_63, Connect, 0, unit, 3); objectCall3(tempvar_63, Connect, 1, tempvar_69, 0); objectCall3(tempvar_63, Connect, 2, tempvar_64, 3); objectCall3(nets[6], Connect, 0, tempvar_63, 3); /* assign stateAfterCheckKey = (((((cur_key [0] ||cur_key [1] )||cur_key [3] )&&(wireout_score==0)))?(0):(((((cur_key==0)&&(wireout_tick<=wireout_speed)))?(2):(3)))); */ IHDL4SEUnit** tempvar_74 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 0", "tempvar_74"); objectCall3(tempvar_74, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_75 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 1", "tempvar_75"); objectCall3(tempvar_75, Connect, 0, nets[61], 0); IHDL4SEUnit **tempvar_73 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_73"); objectCall3(tempvar_73, Connect, 0, tempvar_74, 1); objectCall3(tempvar_73, Connect, 1, tempvar_75, 1); IHDL4SEUnit** tempvar_76 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 3", "tempvar_76"); objectCall3(tempvar_76, Connect, 0, nets[61], 0); IHDL4SEUnit **tempvar_72 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_72"); objectCall3(tempvar_72, Connect, 0, tempvar_73, 2); objectCall3(tempvar_72, Connect, 1, tempvar_76, 1); IHDL4SEUnit** tempvar_78 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_78"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[28], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_77 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_77"); objectCall3(tempvar_77, Connect, 0, nets[28], 0); objectCall3(tempvar_77, Connect, 1, tempvar_78, 0); IHDL4SEUnit **tempvar_71 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_71"); objectCall3(tempvar_71, Connect, 0, tempvar_72, 2); objectCall3(tempvar_71, Connect, 1, tempvar_77, 2); IHDL4SEUnit** tempvar_79 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_79"); IHDL4SEUnit** tempvar_83 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_83"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[61], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_82 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_82"); objectCall3(tempvar_82, Connect, 0, nets[61], 0); objectCall3(tempvar_82, Connect, 1, tempvar_83, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[38], __netswidth[35], 1, BINOP_LE); IHDL4SEUnit **tempvar_84 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_84"); objectCall3(tempvar_84, Connect, 0, nets[38], 0); objectCall3(tempvar_84, Connect, 1, nets[35], 0); IHDL4SEUnit **tempvar_81 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_81"); objectCall3(tempvar_81, Connect, 0, tempvar_82, 2); objectCall3(tempvar_81, Connect, 1, tempvar_84, 2); IHDL4SEUnit** tempvar_85 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 2", "tempvar_85"); IHDL4SEUnit** tempvar_86 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_86"); IHDL4SEUnit **tempvar_80 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "3", "tempvar_80"); objectCall3(tempvar_80, Connect, 0, tempvar_81, 2); objectCall3(tempvar_80, Connect, 1, tempvar_86, 0); objectCall3(tempvar_80, Connect, 2, tempvar_85, 0); IHDL4SEUnit **tempvar_70 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "3", "tempvar_70"); objectCall3(tempvar_70, Connect, 0, tempvar_71, 2); objectCall3(tempvar_70, Connect, 1, tempvar_80, 3); objectCall3(tempvar_70, Connect, 2, tempvar_79, 0); objectCall3(nets[7], Connect, 0, tempvar_70, 3); /* assign wirein_startline = (((wStateComplete&&(bState==5)))?(bResult):(wireout_startline)); */ IHDL4SEUnit** tempvar_90 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 5", "tempvar_90"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[4], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_89 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_89"); objectCall3(tempvar_89, Connect, 0, unit, 4); objectCall3(tempvar_89, Connect, 1, tempvar_90, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[3], 1, 1, BINOP_ANDL); IHDL4SEUnit **tempvar_88 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_88"); objectCall3(tempvar_88, Connect, 0, unit, 3); objectCall3(tempvar_88, Connect, 1, tempvar_89, 2); IHDL4SEUnit **tempvar_87 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_87"); objectCall3(tempvar_87, Connect, 0, tempvar_88, 2); objectCall3(tempvar_87, Connect, 1, nets[19], 0); objectCall3(tempvar_87, Connect, 2, unit, 11); objectCall3(nets[18], Connect, 0, tempvar_87, 3); /* assign wirein_testparam = (((bState==2))?(cur_key):(wireout_testparam)); */ IHDL4SEUnit** tempvar_93 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 2", "tempvar_93"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[4], 3, 1, BINOP_EQ); IHDL4SEUnit **tempvar_92 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_92"); objectCall3(tempvar_92, Connect, 0, unit, 4); objectCall3(tempvar_92, Connect, 1, tempvar_93, 0); IHDL4SEUnit **tempvar_91 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_91"); objectCall3(tempvar_91, Connect, 0, tempvar_92, 2); objectCall3(tempvar_91, Connect, 1, nets[24], 0); objectCall3(tempvar_91, Connect, 2, nets[61], 0); objectCall3(nets[23], Connect, 0, tempvar_91, 3); /* assign scoreAfterCheckKey = ((((cur_key [3] ||cur_key [1] )||cur_key [0] ))?((wireout_score-1)):(((cur_key [2] )?((wireout_score+2)):(wireout_score)))); */ IHDL4SEUnit** tempvar_97 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 3", "tempvar_97"); objectCall3(tempvar_97, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_98 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 1", "tempvar_98"); objectCall3(tempvar_98, Connect, 0, nets[61], 0); IHDL4SEUnit **tempvar_96 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_96"); objectCall3(tempvar_96, Connect, 0, tempvar_97, 1); objectCall3(tempvar_96, Connect, 1, tempvar_98, 1); IHDL4SEUnit** tempvar_99 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 0", "tempvar_99"); objectCall3(tempvar_99, Connect, 0, nets[61], 0); IHDL4SEUnit **tempvar_95 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_95"); objectCall3(tempvar_95, Connect, 0, tempvar_96, 2); objectCall3(tempvar_95, Connect, 1, tempvar_99, 1); IHDL4SEUnit** tempvar_101 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_101"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[28], 2, 0, BINOP_SUB); IHDL4SEUnit **tempvar_100 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_100"); objectCall3(tempvar_100, Connect, 0, nets[28], 0); objectCall3(tempvar_100, Connect, 1, tempvar_101, 0); IHDL4SEUnit** tempvar_103 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 2", "tempvar_103"); objectCall3(tempvar_103, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_105 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 2", "tempvar_105"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[28], 3, 0, BINOP_ADD); IHDL4SEUnit **tempvar_104 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_104"); objectCall3(tempvar_104, Connect, 0, nets[28], 0); objectCall3(tempvar_104, Connect, 1, tempvar_105, 0); IHDL4SEUnit **tempvar_102 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_102"); objectCall3(tempvar_102, Connect, 0, tempvar_103, 1); objectCall3(tempvar_102, Connect, 1, nets[28], 0); objectCall3(tempvar_102, Connect, 2, tempvar_104, 2); IHDL4SEUnit **tempvar_94 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_94"); objectCall3(tempvar_94, Connect, 0, tempvar_95, 2); objectCall3(tempvar_94, Connect, 1, tempvar_102, 3); objectCall3(tempvar_94, Connect, 2, tempvar_100, 2); objectCall3(nets[26], Connect, 0, tempvar_94, 3); /* assign scoreAfterCheckLine = (((wStateComplete&&(bResult>=24)))?((wireout_score+(((wireout_checklinecount>0))?(linescore):(0)))):(wireout_score)); */ IHDL4SEUnit** tempvar_109 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_109"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[11], 6, 1, BINOP_GE); IHDL4SEUnit **tempvar_108 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_108"); objectCall3(tempvar_108, Connect, 0, unit, 11); objectCall3(tempvar_108, Connect, 1, tempvar_109, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[3], 1, 1, BINOP_ANDL); IHDL4SEUnit **tempvar_107 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_107"); objectCall3(tempvar_107, Connect, 0, unit, 3); objectCall3(tempvar_107, Connect, 1, tempvar_108, 2); IHDL4SEUnit** tempvar_113 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_113"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[21], 2, 1, BINOP_GT); IHDL4SEUnit **tempvar_112 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_112"); objectCall3(tempvar_112, Connect, 0, nets[21], 0); objectCall3(tempvar_112, Connect, 1, tempvar_113, 0); IHDL4SEUnit** tempvar_114 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_114"); IHDL4SEUnit **tempvar_111 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_111"); objectCall3(tempvar_111, Connect, 0, tempvar_112, 2); objectCall3(tempvar_111, Connect, 1, tempvar_114, 0); objectCall3(tempvar_111, Connect, 2, nets[29], 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[28], 0, 0, BINOP_ADD); IHDL4SEUnit **tempvar_110 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_110"); objectCall3(tempvar_110, Connect, 0, nets[28], 0); objectCall3(tempvar_110, Connect, 1, tempvar_111, 3); IHDL4SEUnit **tempvar_106 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_106"); objectCall3(tempvar_106, Connect, 0, tempvar_107, 2); objectCall3(tempvar_106, Connect, 1, nets[28], 0); objectCall3(tempvar_106, Connect, 2, tempvar_110, 2); objectCall3(nets[25], Connect, 0, tempvar_106, 3); /* assign wirein_level = ((wStateComplete)?(nextlevel):(wireout_level)); */ IHDL4SEUnit **tempvar_115 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_115"); objectCall3(tempvar_115, Connect, 0, unit, 3); objectCall3(tempvar_115, Connect, 1, nets[32], 0); objectCall3(tempvar_115, Connect, 2, nets[33], 0); objectCall3(nets[31], Connect, 0, tempvar_115, 3); /* assign levelAfterCheckLine = (((wStateComplete&&(bResult>=24)))?((wireout_level+wireout_checklinecount)):(wireout_level)); */ IHDL4SEUnit** tempvar_119 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_119"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[11], 6, 1, BINOP_GE); IHDL4SEUnit **tempvar_118 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_118"); objectCall3(tempvar_118, Connect, 0, unit, 11); objectCall3(tempvar_118, Connect, 1, tempvar_119, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[3], 1, 1, BINOP_ANDL); IHDL4SEUnit **tempvar_117 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_117"); objectCall3(tempvar_117, Connect, 0, unit, 3); objectCall3(tempvar_117, Connect, 1, tempvar_118, 2); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[32], __netswidth[21], 0, BINOP_ADD); IHDL4SEUnit **tempvar_120 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_120"); objectCall3(tempvar_120, Connect, 0, nets[32], 0); objectCall3(tempvar_120, Connect, 1, nets[21], 0); IHDL4SEUnit **tempvar_116 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_116"); objectCall3(tempvar_116, Connect, 0, tempvar_117, 2); objectCall3(tempvar_116, Connect, 1, nets[32], 0); objectCall3(tempvar_116, Connect, 2, tempvar_120, 2); objectCall3(nets[30], Connect, 0, tempvar_116, 3); /* assign wirein_speed = (((32'h1f4>scorediv4))?((32'd500-scorediv4)):(1)); */ IHDL4SEUnit** tempvar_123 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h1f4", "tempvar_123"); sprintf(__instparam, "%d, %d, %d, %d", 32, __netswidth[36], 1, BINOP_GT); IHDL4SEUnit **tempvar_122 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_122"); objectCall3(tempvar_122, Connect, 0, tempvar_123, 0); objectCall3(tempvar_122, Connect, 1, nets[36], 0); IHDL4SEUnit** tempvar_125 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h1f4", "tempvar_125"); sprintf(__instparam, "%d, %d, %d, %d", 32, __netswidth[36], 0, BINOP_SUB); IHDL4SEUnit **tempvar_124 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_124"); objectCall3(tempvar_124, Connect, 0, tempvar_125, 0); objectCall3(tempvar_124, Connect, 1, nets[36], 0); IHDL4SEUnit** tempvar_126 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_126"); IHDL4SEUnit **tempvar_121 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_121"); objectCall3(tempvar_121, Connect, 0, tempvar_122, 2); objectCall3(tempvar_121, Connect, 1, tempvar_126, 0); objectCall3(tempvar_121, Connect, 2, tempvar_124, 2); objectCall3(nets[34], Connect, 0, tempvar_121, 3); /* assign wirein_tick = (((((nwReset==0)||(cur_key!=0))||(wireout_state!=2)))?(0):((wireout_tick+1))); */ IHDL4SEUnit** tempvar_131 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_131"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_130 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_130"); objectCall3(tempvar_130, Connect, 0, unit, 1); objectCall3(tempvar_130, Connect, 1, tempvar_131, 0); IHDL4SEUnit** tempvar_133 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_133"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[61], 2, 1, BINOP_NE); IHDL4SEUnit **tempvar_132 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_132"); objectCall3(tempvar_132, Connect, 0, nets[61], 0); objectCall3(tempvar_132, Connect, 1, tempvar_133, 0); IHDL4SEUnit **tempvar_129 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_129"); objectCall3(tempvar_129, Connect, 0, tempvar_130, 2); objectCall3(tempvar_129, Connect, 1, tempvar_132, 2); IHDL4SEUnit** tempvar_135 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 2", "tempvar_135"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 3, 1, BINOP_NE); IHDL4SEUnit **tempvar_134 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_134"); objectCall3(tempvar_134, Connect, 0, nets[3], 0); objectCall3(tempvar_134, Connect, 1, tempvar_135, 0); IHDL4SEUnit **tempvar_128 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_128"); objectCall3(tempvar_128, Connect, 0, tempvar_129, 2); objectCall3(tempvar_128, Connect, 1, tempvar_134, 2); IHDL4SEUnit** tempvar_136 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_136"); IHDL4SEUnit** tempvar_138 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_138"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[38], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_137 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_137"); objectCall3(tempvar_137, Connect, 0, nets[38], 0); objectCall3(tempvar_137, Connect, 1, tempvar_138, 0); IHDL4SEUnit **tempvar_127 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_127"); objectCall3(tempvar_127, Connect, 0, tempvar_128, 2); objectCall3(tempvar_127, Connect, 1, tempvar_137, 2); objectCall3(tempvar_127, Connect, 2, tempvar_136, 0); objectCall3(nets[37], Connect, 0, tempvar_127, 3); /* assign wirein_curposx = ((wStateComplete)?(nextblockx):(wireout_curposx)); */ IHDL4SEUnit **tempvar_139 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_139"); objectCall3(tempvar_139, Connect, 0, unit, 3); objectCall3(tempvar_139, Connect, 1, nets[42], 0); objectCall3(tempvar_139, Connect, 2, nets[43], 0); objectCall3(nets[41], Connect, 0, tempvar_139, 3); /* assign curposxAfterCheckLine = 8; */ IHDL4SEUnit** tempvar_140 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 8", "tempvar_140"); objectCall3(nets[40], Connect, 0, tempvar_140, 0); /* assign wirein_curposy = ((wStateComplete)?(nextblocky):(wireout_curposy)); */ IHDL4SEUnit **tempvar_141 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_141"); objectCall3(tempvar_141, Connect, 0, unit, 3); objectCall3(tempvar_141, Connect, 1, nets[48], 0); objectCall3(tempvar_141, Connect, 2, nets[49], 0); objectCall3(nets[47], Connect, 0, tempvar_141, 3); /* assign curposyAfterCheckKey = wireout_curposy; */ objectCall3(nets[44], Connect, 0, nets[48], 0); /* assign curposyAfterCheckLine = 0; */ IHDL4SEUnit** tempvar_142 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 0", "tempvar_142"); objectCall3(nets[45], Connect, 0, tempvar_142, 0); /* assign cursoryAfterCheckBlock = (((bResult&&(wireout_testid==0)))?((wireout_curposy+1)):(wireout_curposy)); */ IHDL4SEUnit** tempvar_146 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_146"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[16], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_145 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_145"); objectCall3(tempvar_145, Connect, 0, nets[16], 0); objectCall3(tempvar_145, Connect, 1, tempvar_146, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[11], 1, 1, BINOP_ANDL); IHDL4SEUnit **tempvar_144 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_144"); objectCall3(tempvar_144, Connect, 0, unit, 11); objectCall3(tempvar_144, Connect, 1, tempvar_145, 2); IHDL4SEUnit** tempvar_148 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_148"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[48], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_147 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_147"); objectCall3(tempvar_147, Connect, 0, nets[48], 0); objectCall3(tempvar_147, Connect, 1, tempvar_148, 0); IHDL4SEUnit **tempvar_143 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_143"); objectCall3(tempvar_143, Connect, 0, tempvar_144, 2); objectCall3(tempvar_143, Connect, 1, nets[48], 0); objectCall3(tempvar_143, Connect, 2, tempvar_147, 2); objectCall3(nets[46], Connect, 0, tempvar_143, 3); /* assign curblockWhenFlushToDisp = (((wireout_curblock==64'b0))?(wireout_nextblock):(wireout_curblock)); */ IHDL4SEUnit** tempvar_151 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_151"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[54], 64, 1, BINOP_EQ); IHDL4SEUnit **tempvar_150 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_150"); objectCall3(tempvar_150, Connect, 0, nets[54], 0); objectCall3(tempvar_150, Connect, 1, tempvar_151, 0); IHDL4SEUnit **tempvar_149 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_149"); objectCall3(tempvar_149, Connect, 0, tempvar_150, 2); objectCall3(tempvar_149, Connect, 1, nets[54], 0); objectCall3(tempvar_149, Connect, 2, nets[58], 0); objectCall3(nets[50], Connect, 0, tempvar_149, 3); /* assign curblockAfterCheckBlock = ((((wStateComplete&&bResult)&&(wireout_testid==3)))?(curblockturnleft):(wireout_curblock)); */ sprintf(__instparam, "%d, %d, %d, %d", __portswidth[3], __portswidth[11], 1, BINOP_ANDL); IHDL4SEUnit **tempvar_154 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_154"); objectCall3(tempvar_154, Connect, 0, unit, 3); objectCall3(tempvar_154, Connect, 1, unit, 11); IHDL4SEUnit** tempvar_156 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_156"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[16], 3, 1, BINOP_EQ); IHDL4SEUnit **tempvar_155 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_155"); objectCall3(tempvar_155, Connect, 0, nets[16], 0); objectCall3(tempvar_155, Connect, 1, tempvar_156, 0); IHDL4SEUnit **tempvar_153 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_153"); objectCall3(tempvar_153, Connect, 0, tempvar_154, 2); objectCall3(tempvar_153, Connect, 1, tempvar_155, 2); IHDL4SEUnit **tempvar_152 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_152"); objectCall3(tempvar_152, Connect, 0, tempvar_153, 2); objectCall3(tempvar_152, Connect, 1, nets[54], 0); objectCall3(tempvar_152, Connect, 2, nets[55], 0); objectCall3(nets[51], Connect, 0, tempvar_152, 3); /* assign curblockAfterCheckLine = (((wStateComplete&&(bResult>=24)))?(wireout_nextblock):(wireout_curblock)); */ IHDL4SEUnit** tempvar_160 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_160"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[11], 6, 1, BINOP_GE); IHDL4SEUnit **tempvar_159 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_159"); objectCall3(tempvar_159, Connect, 0, unit, 11); objectCall3(tempvar_159, Connect, 1, tempvar_160, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[3], 1, 1, BINOP_ANDL); IHDL4SEUnit **tempvar_158 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_158"); objectCall3(tempvar_158, Connect, 0, unit, 3); objectCall3(tempvar_158, Connect, 1, tempvar_159, 2); IHDL4SEUnit **tempvar_157 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_157"); objectCall3(tempvar_157, Connect, 0, tempvar_158, 2); objectCall3(tempvar_157, Connect, 1, nets[54], 0); objectCall3(tempvar_157, Connect, 2, nets[58], 0); objectCall3(nets[52], Connect, 0, tempvar_157, 3); /* assign wirein_nextblock = (((wStateComplete&&(wireout_state==7)))?(bNewNextBlock):(wireout_nextblock)); */ IHDL4SEUnit** tempvar_164 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 7", "tempvar_164"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_163 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_163"); objectCall3(tempvar_163, Connect, 0, nets[3], 0); objectCall3(tempvar_163, Connect, 1, tempvar_164, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[3], 1, 1, BINOP_ANDL); IHDL4SEUnit **tempvar_162 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_162"); objectCall3(tempvar_162, Connect, 0, unit, 3); objectCall3(tempvar_162, Connect, 1, tempvar_163, 2); IHDL4SEUnit **tempvar_161 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_161"); objectCall3(tempvar_161, Connect, 0, tempvar_162, 2); objectCall3(tempvar_161, Connect, 1, nets[58], 0); objectCall3(tempvar_161, Connect, 2, unit, 12); objectCall3(nets[57], Connect, 0, tempvar_161, 3); /* assign wirein_key = bKeyData; */ objectCall3(nets[59], Connect, 0, unit, 2); /* assign outputx = (((wireout_state==3))?((wireout_testx+1)):((((wireout_state==6))?(wireout_startline):((wireout_curposx+1))))); */ IHDL4SEUnit** tempvar_167 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_167"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 3, 1, BINOP_EQ); IHDL4SEUnit **tempvar_166 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_166"); objectCall3(tempvar_166, Connect, 0, nets[3], 0); objectCall3(tempvar_166, Connect, 1, tempvar_167, 0); IHDL4SEUnit** tempvar_169 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_169"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[10], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_168 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_168"); objectCall3(tempvar_168, Connect, 0, nets[10], 0); objectCall3(tempvar_168, Connect, 1, tempvar_169, 0); IHDL4SEUnit** tempvar_172 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 6", "tempvar_172"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_171 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_171"); objectCall3(tempvar_171, Connect, 0, nets[3], 0); objectCall3(tempvar_171, Connect, 1, tempvar_172, 0); IHDL4SEUnit** tempvar_174 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_174"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[42], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_173 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_173"); objectCall3(tempvar_173, Connect, 0, nets[42], 0); objectCall3(tempvar_173, Connect, 1, tempvar_174, 0); IHDL4SEUnit **tempvar_170 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_170"); objectCall3(tempvar_170, Connect, 0, tempvar_171, 2); objectCall3(tempvar_170, Connect, 1, tempvar_173, 2); objectCall3(tempvar_170, Connect, 2, nets[19], 0); IHDL4SEUnit **tempvar_165 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_165"); objectCall3(tempvar_165, Connect, 0, tempvar_166, 2); objectCall3(tempvar_165, Connect, 1, tempvar_170, 3); objectCall3(tempvar_165, Connect, 2, tempvar_168, 2); objectCall3(nets[0], Connect, 0, tempvar_165, 3); /* assign outputy = (((wireout_state==3))?(((24+1)-wireout_testy)):((((wireout_state==6))?(8'b0):(((24+1)-wireout_curposy))))); */ IHDL4SEUnit** tempvar_177 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_177"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 3, 1, BINOP_EQ); IHDL4SEUnit **tempvar_176 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_176"); objectCall3(tempvar_176, Connect, 0, nets[3], 0); objectCall3(tempvar_176, Connect, 1, tempvar_177, 0); IHDL4SEUnit** tempvar_179 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 25", "tempvar_179"); sprintf(__instparam, "%d, %d, %d, %d", 6, __netswidth[13], 0, BINOP_SUB); IHDL4SEUnit **tempvar_178 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_178"); objectCall3(tempvar_178, Connect, 0, tempvar_179, 0); objectCall3(tempvar_178, Connect, 1, nets[13], 0); IHDL4SEUnit** tempvar_182 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 6", "tempvar_182"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_181 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_181"); objectCall3(tempvar_181, Connect, 0, nets[3], 0); objectCall3(tempvar_181, Connect, 1, tempvar_182, 0); IHDL4SEUnit** tempvar_183 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 0", "tempvar_183"); IHDL4SEUnit** tempvar_185 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 25", "tempvar_185"); sprintf(__instparam, "%d, %d, %d, %d", 6, __netswidth[48], 0, BINOP_SUB); IHDL4SEUnit **tempvar_184 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_184"); objectCall3(tempvar_184, Connect, 0, tempvar_185, 0); objectCall3(tempvar_184, Connect, 1, nets[48], 0); IHDL4SEUnit **tempvar_180 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_180"); objectCall3(tempvar_180, Connect, 0, tempvar_181, 2); objectCall3(tempvar_180, Connect, 1, tempvar_184, 2); objectCall3(tempvar_180, Connect, 2, tempvar_183, 0); IHDL4SEUnit **tempvar_175 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_175"); objectCall3(tempvar_175, Connect, 0, tempvar_176, 2); objectCall3(tempvar_175, Connect, 1, tempvar_180, 3); objectCall3(tempvar_175, Connect, 2, tempvar_178, 2); objectCall3(nets[1], Connect, 0, tempvar_175, 3); /* assign testxwencheckkey = ((cur_key [0] )?((wireout_curposx+1)):(((cur_key [1] )?((wireout_curposx-1)):(wireout_curposx)))); */ IHDL4SEUnit** tempvar_187 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 0", "tempvar_187"); objectCall3(tempvar_187, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_189 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_189"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[42], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_188 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_188"); objectCall3(tempvar_188, Connect, 0, nets[42], 0); objectCall3(tempvar_188, Connect, 1, tempvar_189, 0); IHDL4SEUnit** tempvar_191 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 1", "tempvar_191"); objectCall3(tempvar_191, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_193 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_193"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[42], 2, 0, BINOP_SUB); IHDL4SEUnit **tempvar_192 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_192"); objectCall3(tempvar_192, Connect, 0, nets[42], 0); objectCall3(tempvar_192, Connect, 1, tempvar_193, 0); IHDL4SEUnit **tempvar_190 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_190"); objectCall3(tempvar_190, Connect, 0, tempvar_191, 1); objectCall3(tempvar_190, Connect, 1, nets[42], 0); objectCall3(tempvar_190, Connect, 2, tempvar_192, 2); IHDL4SEUnit **tempvar_186 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_186"); objectCall3(tempvar_186, Connect, 0, tempvar_187, 1); objectCall3(tempvar_186, Connect, 1, tempvar_190, 3); objectCall3(tempvar_186, Connect, 2, tempvar_188, 2); objectCall3(nets[11], Connect, 0, tempvar_186, 3); /* assign testywencheckkey = (((cur_key [2] ||(cur_key==0)))?((wireout_curposy+1)):(wireout_curposy)); */ IHDL4SEUnit** tempvar_196 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 2", "tempvar_196"); objectCall3(tempvar_196, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_198 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_198"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[61], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_197 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_197"); objectCall3(tempvar_197, Connect, 0, nets[61], 0); objectCall3(tempvar_197, Connect, 1, tempvar_198, 0); IHDL4SEUnit **tempvar_195 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_195"); objectCall3(tempvar_195, Connect, 0, tempvar_196, 1); objectCall3(tempvar_195, Connect, 1, tempvar_197, 2); IHDL4SEUnit** tempvar_200 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_200"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[48], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_199 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_199"); objectCall3(tempvar_199, Connect, 0, nets[48], 0); objectCall3(tempvar_199, Connect, 1, tempvar_200, 0); IHDL4SEUnit **tempvar_194 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_194"); objectCall3(tempvar_194, Connect, 0, tempvar_195, 2); objectCall3(tempvar_194, Connect, 1, nets[48], 0); objectCall3(tempvar_194, Connect, 2, tempvar_199, 2); objectCall3(nets[14], Connect, 0, tempvar_194, 3); /* assign testidwhencheckkey = (((cur_key==0))?((((wireout_tick<=wireout_speed))?(wireout_testid):(0))):(((cur_key [2] )?(0):(((cur_key [1] )?(1):(((cur_key [0] )?(2):(3)))))))); */ IHDL4SEUnit** tempvar_203 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_203"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[61], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_202 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_202"); objectCall3(tempvar_202, Connect, 0, nets[61], 0); objectCall3(tempvar_202, Connect, 1, tempvar_203, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[38], __netswidth[35], 1, BINOP_LE); IHDL4SEUnit **tempvar_205 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_205"); objectCall3(tempvar_205, Connect, 0, nets[38], 0); objectCall3(tempvar_205, Connect, 1, nets[35], 0); IHDL4SEUnit** tempvar_206 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_206"); IHDL4SEUnit **tempvar_204 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_204"); objectCall3(tempvar_204, Connect, 0, tempvar_205, 2); objectCall3(tempvar_204, Connect, 1, tempvar_206, 0); objectCall3(tempvar_204, Connect, 2, nets[16], 0); IHDL4SEUnit** tempvar_208 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 2", "tempvar_208"); objectCall3(tempvar_208, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_209 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_209"); IHDL4SEUnit** tempvar_211 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 1", "tempvar_211"); objectCall3(tempvar_211, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_212 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_212"); IHDL4SEUnit** tempvar_214 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 0", "tempvar_214"); objectCall3(tempvar_214, Connect, 0, nets[61], 0); IHDL4SEUnit** tempvar_215 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 2", "tempvar_215"); IHDL4SEUnit** tempvar_216 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_216"); IHDL4SEUnit **tempvar_213 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "3", "tempvar_213"); objectCall3(tempvar_213, Connect, 0, tempvar_214, 1); objectCall3(tempvar_213, Connect, 1, tempvar_216, 0); objectCall3(tempvar_213, Connect, 2, tempvar_215, 0); IHDL4SEUnit **tempvar_210 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "3", "tempvar_210"); objectCall3(tempvar_210, Connect, 0, tempvar_211, 1); objectCall3(tempvar_210, Connect, 1, tempvar_213, 3); objectCall3(tempvar_210, Connect, 2, tempvar_212, 0); IHDL4SEUnit **tempvar_207 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "3", "tempvar_207"); objectCall3(tempvar_207, Connect, 0, tempvar_208, 1); objectCall3(tempvar_207, Connect, 1, tempvar_210, 3); objectCall3(tempvar_207, Connect, 2, tempvar_209, 0); IHDL4SEUnit **tempvar_201 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_201"); objectCall3(tempvar_201, Connect, 0, tempvar_202, 2); objectCall3(tempvar_201, Connect, 1, tempvar_207, 3); objectCall3(tempvar_201, Connect, 2, tempvar_204, 3); objectCall3(nets[17], Connect, 0, tempvar_201, 3); /* assign checklinecountAfterCheckline = (((wStateComplete&&(bResult<24)))?((wireout_checklinecount+1)):(wireout_checklinecount)); */ IHDL4SEUnit** tempvar_220 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_220"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[11], 6, 1, BINOP_LT); IHDL4SEUnit **tempvar_219 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_219"); objectCall3(tempvar_219, Connect, 0, unit, 11); objectCall3(tempvar_219, Connect, 1, tempvar_220, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[3], 1, 1, BINOP_ANDL); IHDL4SEUnit **tempvar_218 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_218"); objectCall3(tempvar_218, Connect, 0, unit, 3); objectCall3(tempvar_218, Connect, 1, tempvar_219, 2); IHDL4SEUnit** tempvar_222 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_222"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[21], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_221 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_221"); objectCall3(tempvar_221, Connect, 0, nets[21], 0); objectCall3(tempvar_221, Connect, 1, tempvar_222, 0); IHDL4SEUnit **tempvar_217 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_217"); objectCall3(tempvar_217, Connect, 0, tempvar_218, 2); objectCall3(tempvar_217, Connect, 1, nets[21], 0); objectCall3(tempvar_217, Connect, 2, tempvar_221, 2); objectCall3(nets[22], Connect, 0, tempvar_217, 3); /* assign scorediv4 = wireout_score [31:4] ; */ IHDL4SEUnit** tempvar_223 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 28, 4", "tempvar_223"); objectCall3(tempvar_223, Connect, 0, nets[28], 0); objectCall3(nets[36], Connect, 0, tempvar_223, 1); /* assign cur_key = (((wireout_key==bKeyData))?(0):(bKeyData)); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[60], __portswidth[2], 1, BINOP_EQ); IHDL4SEUnit **tempvar_225 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_225"); objectCall3(tempvar_225, Connect, 0, nets[60], 0); objectCall3(tempvar_225, Connect, 1, unit, 2); IHDL4SEUnit** tempvar_226 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_226"); IHDL4SEUnit **tempvar_224 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_224"); objectCall3(tempvar_224, Connect, 0, tempvar_225, 2); objectCall3(tempvar_224, Connect, 1, unit, 2); objectCall3(tempvar_224, Connect, 2, tempvar_226, 0); objectCall3(nets[61], Connect, 0, tempvar_224, 3); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_0019(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module rand */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[2]; int __netswidth[2]; IHDL4SEUnit** modules[1]; int __portswidth[2]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "randnum", 16, 1, PORT_DIRECT_OUTPUT); /* 1*/ __portswidth[1] = 16; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wirein_num"); __netswidth[0] = 32; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_num"); __netswidth[1] = 32; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "32", "reg_rand"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(nets[1], Connect, 0, modules[0], 2); /* 持续性赋值 */ /* assign randnum = wireout_num [15:0] ; */ IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 16, 0", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, nets[1], 0); objectCall3(unit, Connect, 1, tempvar_0, 1); /* assign wirein_num = ((wireout_num*32'd214013)+32'd2531011); */ IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h343fd", "tempvar_3"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 32, 0, BINOP_MUL); IHDL4SEUnit **tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_2"); objectCall3(tempvar_2, Connect, 0, nets[1], 0); objectCall3(tempvar_2, Connect, 1, tempvar_3, 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h269ec3", "tempvar_4"); sprintf(__instparam, "%d, %d, %d, %d", 0, 32, 0, BINOP_ADD); IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_1"); objectCall3(tempvar_1, Connect, 0, tempvar_2, 2); objectCall3(tempvar_1, Connect, 1, tempvar_4, 0); objectCall3(nets[0], Connect, 0, tempvar_1, 2); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_001A(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module blockshape */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** modules[1]; int __portswidth[2]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "sel", 4, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 4; /* 1*/ objectCall4(module, AddPort, "blockshape", 16, 1, PORT_DIRECT_OUTPUT); /* 1*/ __portswidth[1] = 16; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "69B4A095-0644-4B9E-9CF0-295474D7C243", "16", "mux_blockshape"); objectCall3(modules[0], Connect, 0, unit, 0); IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 1632", "tempvar_0"); objectCall3(modules[0], Connect, 1, tempvar_0, 0); IHDL4SEUnit** tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 61152", "tempvar_1"); objectCall3(modules[0], Connect, 2, tempvar_1, 0); IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 1568", "tempvar_2"); objectCall3(modules[0], Connect, 3, tempvar_2, 0); IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 1056", "tempvar_3"); objectCall3(modules[0], Connect, 4, tempvar_3, 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 17952", "tempvar_4"); objectCall3(modules[0], Connect, 5, tempvar_4, 0); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 17476", "tempvar_5"); objectCall3(modules[0], Connect, 6, tempvar_5, 0); IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 9792", "tempvar_6"); objectCall3(modules[0], Connect, 7, tempvar_6, 0); IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 1248", "tempvar_7"); objectCall3(modules[0], Connect, 8, tempvar_7, 0); IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 1024", "tempvar_8"); objectCall3(modules[0], Connect, 9, tempvar_8, 0); IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 25120", "tempvar_9"); objectCall3(modules[0], Connect, 10, tempvar_9, 0); IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 25664", "tempvar_10"); objectCall3(modules[0], Connect, 11, tempvar_10, 0); IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 61152", "tempvar_11"); objectCall3(modules[0], Connect, 12, tempvar_11, 0); IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 1568", "tempvar_12"); objectCall3(modules[0], Connect, 13, tempvar_12, 0); IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 1056", "tempvar_13"); objectCall3(modules[0], Connect, 14, tempvar_13, 0); IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 25668", "tempvar_14"); objectCall3(modules[0], Connect, 15, tempvar_14, 0); IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "16, 17952", "tempvar_15"); objectCall3(modules[0], Connect, 16, tempvar_15, 0); objectCall3(unit, Connect, 1, modules[0], 17); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_001B(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module genblock */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[16]; int __netswidth[16]; IHDL4SEUnit** modules[7]; int __portswidth[5]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "nwReset", 1, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 1; /* 2*/ objectCall4(module, AddPort, "bCtrlState", 4, 1, PORT_DIRECT_INPUT ); /* 2*/ __portswidth[2] = 4; /* 3*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT); /* 3*/ __portswidth[3] = 1; /* 4*/ objectCall4(module, AddPort, "newnextblock", 64, 1, PORT_DIRECT_OUTPUT); /* 4*/ __portswidth[4] = 64; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 7", "wirein_genblock_count"); __netswidth[0] = 7; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 7", "wireout_genblock_count"); __netswidth[1] = 7; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCtrlStateComplete"); __netswidth[2] = 1; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "randnum"); __netswidth[3] = 16; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "shapeindex"); __netswidth[4] = 4; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "shapedata"); __netswidth[5] = 16; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "colorindex_0"); __netswidth[6] = 4; nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "colorindex"); __netswidth[7] = 4; nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "setshape"); __netswidth[8] = 1; nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "newshape"); __netswidth[9] = 1; nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "wirein_shapedata"); __netswidth[10] = 16; nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "wireout_shapedata"); __netswidth[11] = 16; nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "settoshape"); __netswidth[12] = 16; nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "newblock"); __netswidth[13] = 64; nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "wirein_nextblock"); __netswidth[14] = 64; nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "wireout_nextblock"); __netswidth[15] = 64; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "7", "terris_genblock_count"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(nets[1], Connect, 0, modules[0], 2); modules[ 1] = hdl4seCreate_0019(module, "", "randgen"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(nets[3], Connect, 0, modules[1], 1); modules[ 2] = hdl4seCreate_001A(module, "", "shape"); objectCall3(modules[2], Connect, 0, nets[4], 0); objectCall3(nets[5], Connect, 0, modules[2], 1); modules[ 3] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "16", "terris_shape"); objectCall3(modules[3], Connect, 0, unit, 0); objectCall3(modules[3], Connect, 1, nets[10], 0); objectCall3(nets[11], Connect, 0, modules[3], 2); modules[ 4] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "15, 1", "nextblockshape"); IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 15, 1", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, nets[11], 0); objectCall3(modules[4], Connect, 0, tempvar_0, 1); IHDL4SEUnit** tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 0", "tempvar_1"); objectCall3(tempvar_1, Connect, 0, nets[11], 0); objectCall3(modules[4], Connect, 1, tempvar_1, 1); objectCall3(nets[12], Connect, 0, modules[4], 2); modules[ 5] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "64", "terris_nextblock"); objectCall3(modules[5], Connect, 0, unit, 0); objectCall3(modules[5], Connect, 1, nets[14], 0); objectCall3(nets[15], Connect, 0, modules[5], 2); modules[ 6] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "60, 4", "newnextblock"); IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 60, 4", "tempvar_2"); objectCall3(tempvar_2, Connect, 0, nets[15], 0); objectCall3(modules[6], Connect, 0, tempvar_2, 1); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 0", "tempvar_4"); objectCall3(tempvar_4, Connect, 0, nets[11], 0); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_5"); IHDL4SEUnit **tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_3"); objectCall3(tempvar_3, Connect, 0, tempvar_4, 1); objectCall3(tempvar_3, Connect, 1, tempvar_5, 0); objectCall3(tempvar_3, Connect, 2, nets[7], 0); objectCall3(modules[6], Connect, 1, tempvar_3, 3); objectCall3(nets[13], Connect, 0, modules[6], 2); /* 持续性赋值 */ /* assign wirein_genblock_count = ((((bCtrlState==7)&&(nwReset!=0)))?((wireout_genblock_count+1)):(0)); */ IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 7", "tempvar_9"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[2], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_8"); objectCall3(tempvar_8, Connect, 0, unit, 2); objectCall3(tempvar_8, Connect, 1, tempvar_9, 0); IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_11"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 2, 1, BINOP_NE); IHDL4SEUnit **tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_10"); objectCall3(tempvar_10, Connect, 0, unit, 1); objectCall3(tempvar_10, Connect, 1, tempvar_11, 0); IHDL4SEUnit **tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_7"); objectCall3(tempvar_7, Connect, 0, tempvar_8, 2); objectCall3(tempvar_7, Connect, 1, tempvar_10, 2); IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_13"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_12"); objectCall3(tempvar_12, Connect, 0, nets[1], 0); objectCall3(tempvar_12, Connect, 1, tempvar_13, 0); IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_14"); IHDL4SEUnit **tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_6"); objectCall3(tempvar_6, Connect, 0, tempvar_7, 2); objectCall3(tempvar_6, Connect, 1, tempvar_14, 0); objectCall3(tempvar_6, Connect, 2, tempvar_12, 2); objectCall3(nets[0], Connect, 0, tempvar_6, 3); /* assign wCtrlStateComplete = (wireout_genblock_count==18); */ IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 18", "tempvar_16"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 6, 1, BINOP_EQ); IHDL4SEUnit **tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_15"); objectCall3(tempvar_15, Connect, 0, nets[1], 0); objectCall3(tempvar_15, Connect, 1, tempvar_16, 0); objectCall3(unit, Connect, 3, tempvar_15, 2); /* assign wirein_shapedata = ((newshape)?(shapedata):(settoshape)); */ IHDL4SEUnit **tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_17"); objectCall3(tempvar_17, Connect, 0, nets[9], 0); objectCall3(tempvar_17, Connect, 1, nets[12], 0); objectCall3(tempvar_17, Connect, 2, nets[5], 0); objectCall3(nets[10], Connect, 0, tempvar_17, 3); /* assign wirein_nextblock = ((setshape)?(newblock):(wireout_nextblock)); */ IHDL4SEUnit **tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_18"); objectCall3(tempvar_18, Connect, 0, nets[8], 0); objectCall3(tempvar_18, Connect, 1, nets[15], 0); objectCall3(tempvar_18, Connect, 2, nets[13], 0); objectCall3(nets[14], Connect, 0, tempvar_18, 3); /* assign newnextblock = wireout_nextblock; */ objectCall3(unit, Connect, 4, nets[15], 0); /* assign shapeindex = randnum [3:0] ; */ IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 0", "tempvar_19"); objectCall3(tempvar_19, Connect, 0, nets[3], 0); objectCall3(nets[4], Connect, 0, tempvar_19, 1); /* assign colorindex_0 = randnum [3:0] ; */ IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 0", "tempvar_20"); objectCall3(tempvar_20, Connect, 0, nets[3], 0); objectCall3(nets[6], Connect, 0, tempvar_20, 1); /* assign colorindex = ((((colorindex_0==0)||(colorindex_0==1)))?((colorindex_0+4)):(colorindex_0)); */ IHDL4SEUnit** tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_24"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[6], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_23"); objectCall3(tempvar_23, Connect, 0, nets[6], 0); objectCall3(tempvar_23, Connect, 1, tempvar_24, 0); IHDL4SEUnit** tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_26"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[6], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_25"); objectCall3(tempvar_25, Connect, 0, nets[6], 0); objectCall3(tempvar_25, Connect, 1, tempvar_26, 0); IHDL4SEUnit **tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_22"); objectCall3(tempvar_22, Connect, 0, tempvar_23, 2); objectCall3(tempvar_22, Connect, 1, tempvar_25, 2); IHDL4SEUnit** tempvar_28 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_28"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[6], 4, 0, BINOP_ADD); IHDL4SEUnit **tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_27"); objectCall3(tempvar_27, Connect, 0, nets[6], 0); objectCall3(tempvar_27, Connect, 1, tempvar_28, 0); IHDL4SEUnit **tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_21"); objectCall3(tempvar_21, Connect, 0, tempvar_22, 2); objectCall3(tempvar_21, Connect, 1, nets[6], 0); objectCall3(tempvar_21, Connect, 2, tempvar_27, 2); objectCall3(nets[7], Connect, 0, tempvar_21, 3); /* assign setshape = ((wireout_genblock_count>=2)&&(wireout_genblock_count<=17)); */ IHDL4SEUnit** tempvar_31 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 2", "tempvar_31"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 3, 1, BINOP_GE); IHDL4SEUnit **tempvar_30 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_30"); objectCall3(tempvar_30, Connect, 0, nets[1], 0); objectCall3(tempvar_30, Connect, 1, tempvar_31, 0); IHDL4SEUnit** tempvar_33 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 17", "tempvar_33"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 6, 1, BINOP_LE); IHDL4SEUnit **tempvar_32 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_32"); objectCall3(tempvar_32, Connect, 0, nets[1], 0); objectCall3(tempvar_32, Connect, 1, tempvar_33, 0); IHDL4SEUnit **tempvar_29 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_29"); objectCall3(tempvar_29, Connect, 0, tempvar_30, 2); objectCall3(tempvar_29, Connect, 1, tempvar_32, 2); objectCall3(nets[8], Connect, 0, tempvar_29, 2); /* assign newshape = (wireout_genblock_count==1); */ IHDL4SEUnit** tempvar_35 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_35"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_34 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_34"); objectCall3(tempvar_34, Connect, 0, nets[1], 0); objectCall3(tempvar_34, Connect, 1, tempvar_35, 0); objectCall3(nets[9], Connect, 0, tempvar_34, 2); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_0013(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module flushtodisp */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[17]; int __netswidth[17]; IHDL4SEUnit** modules[3]; int __portswidth[14]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "bCtrlState", 4, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 4; /* 2*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT); /* 2*/ __portswidth[2] = 1; /* 3*/ objectCall4(module, AddPort, "bFlushReadAddr", 6, 1, PORT_DIRECT_OUTPUT); /* 3*/ __portswidth[3] = 6; /* 4*/ objectCall4(module, AddPort, "bFlushReadData", 64, 1, PORT_DIRECT_INPUT ); /* 4*/ __portswidth[4] = 64; /* 5*/ objectCall4(module, AddPort, "wWrite", 1, 1, PORT_DIRECT_OUTPUT); /* 5*/ __portswidth[5] = 1; /* 6*/ objectCall4(module, AddPort, "bWriteAddr", 32, 1, PORT_DIRECT_OUTPUT); /* 6*/ __portswidth[6] = 32; /* 7*/ objectCall4(module, AddPort, "bWriteData", 32, 1, PORT_DIRECT_OUTPUT); /* 7*/ __portswidth[7] = 32; /* 8*/ objectCall4(module, AddPort, "bCtrlSpeed", 32, 1, PORT_DIRECT_INPUT ); /* 8*/ __portswidth[8] = 32; /* 9*/ objectCall4(module, AddPort, "bCtrlLevel", 32, 1, PORT_DIRECT_INPUT ); /* 9*/ __portswidth[9] = 32; /* 10*/ objectCall4(module, AddPort, "bCtrlScore", 32, 1, PORT_DIRECT_INPUT ); /* 10*/ __portswidth[10] = 32; /* 11*/ objectCall4(module, AddPort, "bNextBlock", 64, 1, PORT_DIRECT_INPUT ); /* 11*/ __portswidth[11] = 64; /* 12*/ objectCall4(module, AddPort, "bCurBlock", 64, 1, PORT_DIRECT_INPUT ); /* 12*/ __portswidth[12] = 64; /* 13*/ objectCall4(module, AddPort, "bCurBlockPos", 16, 1, PORT_DIRECT_INPUT ); /* 13*/ __portswidth[13] = 16; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bNextBlockLo"); __netswidth[0] = 32; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bNextBlockHi"); __netswidth[1] = 32; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "blockx"); __netswidth[2] = 8; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "blocky"); __netswidth[3] = 8; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 10", "wirein_readaddr"); __netswidth[4] = 10; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 10", "wireout_readaddr"); __netswidth[5] = 10; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 10", "wireout_readaddr_delay_1"); __netswidth[6] = 10; nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "selecteddata"); __netswidth[7] = 32; nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "_wWrite"); __netswidth[8] = 1; nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "_bWriteAddr"); __netswidth[9] = 32; nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "_bWriteData"); __netswidth[10] = 32; nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 10", "bWriteDataSel"); __netswidth[11] = 10; nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "y"); __netswidth[12] = 8; nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_0"); __netswidth[13] = 64; nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline"); __netswidth[14] = 64; nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "data"); __netswidth[15] = 64; nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "right"); __netswidth[16] = 1; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "10", "reg_readaddr"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[4], 0); objectCall3(nets[5], Connect, 0, modules[0], 2); modules[ 1] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "10", "reg_readaddr_delay_1"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(modules[1], Connect, 1, nets[5], 0); objectCall3(nets[6], Connect, 0, modules[1], 2); modules[ 2] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "32", "writedatasel"); IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 3, 0", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, nets[11], 0); objectCall3(modules[2], Connect, 0, tempvar_0, 1); IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 32, 32", "tempvar_2"); objectCall3(tempvar_2, Connect, 0, nets[15], 0); IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 32, 0", "tempvar_3"); objectCall3(tempvar_3, Connect, 0, nets[15], 0); IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_1"); objectCall3(tempvar_1, Connect, 0, nets[16], 0); objectCall3(tempvar_1, Connect, 1, tempvar_3, 1); objectCall3(tempvar_1, Connect, 2, tempvar_2, 1); objectCall3(modules[2], Connect, 1, tempvar_1, 3); objectCall3(modules[2], Connect, 2, nets[0], 0); objectCall3(modules[2], Connect, 3, nets[1], 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_4"); objectCall3(modules[2], Connect, 4, tempvar_4, 0); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_5"); objectCall3(modules[2], Connect, 5, tempvar_5, 0); objectCall3(modules[2], Connect, 6, unit, 10); objectCall3(modules[2], Connect, 7, unit, 9); objectCall3(modules[2], Connect, 8, unit, 8); objectCall3(nets[7], Connect, 0, modules[2], 9); /* 持续性赋值 */ /* assign wirein_readaddr = (((bCtrlState==1))?((wireout_readaddr+1)):(6'b0)); */ IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_8"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_7"); objectCall3(tempvar_7, Connect, 0, unit, 1); objectCall3(tempvar_7, Connect, 1, tempvar_8, 0); IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_10"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_9"); objectCall3(tempvar_9, Connect, 0, nets[5], 0); objectCall3(tempvar_9, Connect, 1, tempvar_10, 0); IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_11"); IHDL4SEUnit **tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_6"); objectCall3(tempvar_6, Connect, 0, tempvar_7, 2); objectCall3(tempvar_6, Connect, 1, tempvar_11, 0); objectCall3(tempvar_6, Connect, 2, tempvar_9, 2); objectCall3(nets[4], Connect, 0, tempvar_6, 3); /* assign wCtrlStateComplete = (wireout_readaddr==8'd60); */ IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 60", "tempvar_13"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 8, 1, BINOP_EQ); IHDL4SEUnit **tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_12"); objectCall3(tempvar_12, Connect, 0, nets[5], 0); objectCall3(tempvar_12, Connect, 1, tempvar_13, 0); objectCall3(unit, Connect, 2, tempvar_12, 2); /* assign bFlushReadAddr = wireout_readaddr [6:1] ; */ IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 6, 1", "tempvar_14"); objectCall3(tempvar_14, Connect, 0, nets[5], 0); objectCall3(unit, Connect, 3, tempvar_14, 1); /* assign wWrite = _wWrite; */ objectCall3(unit, Connect, 5, nets[8], 0); /* assign bWriteAddr = _bWriteAddr; */ objectCall3(unit, Connect, 6, nets[9], 0); /* assign bWriteData = _bWriteData; */ objectCall3(unit, Connect, 7, nets[10], 0); /* assign bNextBlockLo = bNextBlock [31:0] ; */ IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 32, 0", "tempvar_15"); objectCall3(tempvar_15, Connect, 0, unit, 11); objectCall3(nets[0], Connect, 0, tempvar_15, 1); /* assign bNextBlockHi = bNextBlock [63:32] ; */ IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 32, 32", "tempvar_16"); objectCall3(tempvar_16, Connect, 0, unit, 11); objectCall3(nets[1], Connect, 0, tempvar_16, 1); /* assign blockx = bCurBlockPos [7:0] ; */ IHDL4SEUnit** tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 8, 0", "tempvar_17"); objectCall3(tempvar_17, Connect, 0, unit, 13); objectCall3(nets[2], Connect, 0, tempvar_17, 1); /* assign blocky = bCurBlockPos [15:8] ; */ IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 8, 8", "tempvar_18"); objectCall3(tempvar_18, Connect, 0, unit, 13); objectCall3(nets[3], Connect, 0, tempvar_18, 1); /* assign _wWrite = ((bCtrlState==1)&&(bWriteDataSel<=7)); */ IHDL4SEUnit** tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_21"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_20"); objectCall3(tempvar_20, Connect, 0, unit, 1); objectCall3(tempvar_20, Connect, 1, tempvar_21, 0); IHDL4SEUnit** tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 7", "tempvar_23"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[11], 4, 1, BINOP_LE); IHDL4SEUnit **tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_22"); objectCall3(tempvar_22, Connect, 0, nets[11], 0); objectCall3(tempvar_22, Connect, 1, tempvar_23, 0); IHDL4SEUnit **tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_19"); objectCall3(tempvar_19, Connect, 0, tempvar_20, 2); objectCall3(tempvar_19, Connect, 1, tempvar_22, 2); objectCall3(nets[8], Connect, 0, tempvar_19, 2); /* assign _bWriteAddr = (32'hf0000010+(wireout_readaddr_delay_1*4)); */ IHDL4SEUnit** tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hf0000010", "tempvar_25"); IHDL4SEUnit** tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_27"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[6], 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_26"); objectCall3(tempvar_26, Connect, 0, nets[6], 0); objectCall3(tempvar_26, Connect, 1, tempvar_27, 0); sprintf(__instparam, "%d, %d, %d, %d", 32, 0, 0, BINOP_ADD); IHDL4SEUnit **tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_24"); objectCall3(tempvar_24, Connect, 0, tempvar_25, 0); objectCall3(tempvar_24, Connect, 1, tempvar_26, 2); objectCall3(nets[9], Connect, 0, tempvar_24, 2); /* assign _bWriteData = selecteddata; */ objectCall3(nets[10], Connect, 0, nets[7], 0); /* assign bWriteDataSel = (((wireout_readaddr_delay_1<8'd52))?(8'd0):((wireout_readaddr_delay_1-8'd51))); */ IHDL4SEUnit** tempvar_30 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 52", "tempvar_30"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[6], 8, 1, BINOP_LT); IHDL4SEUnit **tempvar_29 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_29"); objectCall3(tempvar_29, Connect, 0, nets[6], 0); objectCall3(tempvar_29, Connect, 1, tempvar_30, 0); IHDL4SEUnit** tempvar_31 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 0", "tempvar_31"); IHDL4SEUnit** tempvar_33 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 51", "tempvar_33"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[6], 8, 0, BINOP_SUB); IHDL4SEUnit **tempvar_32 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_32"); objectCall3(tempvar_32, Connect, 0, nets[6], 0); objectCall3(tempvar_32, Connect, 1, tempvar_33, 0); IHDL4SEUnit **tempvar_28 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_28"); objectCall3(tempvar_28, Connect, 0, tempvar_29, 2); objectCall3(tempvar_28, Connect, 1, tempvar_32, 2); objectCall3(tempvar_28, Connect, 2, tempvar_31, 0); objectCall3(nets[11], Connect, 0, tempvar_28, 3); /* assign y = wireout_readaddr_delay_1 [7:1] ; */ IHDL4SEUnit** tempvar_34 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 7, 1", "tempvar_34"); objectCall3(tempvar_34, Connect, 0, nets[6], 0); objectCall3(nets[12], Connect, 0, tempvar_34, 1); /* assign curblockline_0 = ((((blocky>=y)&&(blocky<(4+y))))?(((bCurBlock>>((blocky-y)*16))&64'hffff)):(64'h0)); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], __netswidth[12], 1, BINOP_GE); IHDL4SEUnit **tempvar_37 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_37"); objectCall3(tempvar_37, Connect, 0, nets[3], 0); objectCall3(tempvar_37, Connect, 1, nets[12], 0); IHDL4SEUnit** tempvar_40 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_40"); sprintf(__instparam, "%d, %d, %d, %d", 4, __netswidth[12], 0, BINOP_ADD); IHDL4SEUnit **tempvar_39 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_39"); objectCall3(tempvar_39, Connect, 0, tempvar_40, 0); objectCall3(tempvar_39, Connect, 1, nets[12], 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 0, 1, BINOP_LT); IHDL4SEUnit **tempvar_38 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_38"); objectCall3(tempvar_38, Connect, 0, nets[3], 0); objectCall3(tempvar_38, Connect, 1, tempvar_39, 2); IHDL4SEUnit **tempvar_36 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_36"); objectCall3(tempvar_36, Connect, 0, tempvar_37, 2); objectCall3(tempvar_36, Connect, 1, tempvar_38, 2); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], __netswidth[12], 0, BINOP_SUB); IHDL4SEUnit **tempvar_44 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_44"); objectCall3(tempvar_44, Connect, 0, nets[3], 0); objectCall3(tempvar_44, Connect, 1, nets[12], 0); IHDL4SEUnit** tempvar_45 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 16", "tempvar_45"); sprintf(__instparam, "%d, %d, %d, %d", 0, 6, 0, BINOP_MUL); IHDL4SEUnit **tempvar_43 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_43"); objectCall3(tempvar_43, Connect, 0, tempvar_44, 2); objectCall3(tempvar_43, Connect, 1, tempvar_45, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[12], 0, 0, BINOP_SHR); IHDL4SEUnit **tempvar_42 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_42"); objectCall3(tempvar_42, Connect, 0, unit, 12); objectCall3(tempvar_42, Connect, 1, tempvar_43, 2); IHDL4SEUnit** tempvar_46 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h00000ffff", "tempvar_46"); sprintf(__instparam, "%d, %d, %d, %d", 0, 64, 0, BINOP_AND); IHDL4SEUnit **tempvar_41 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_41"); objectCall3(tempvar_41, Connect, 0, tempvar_42, 2); objectCall3(tempvar_41, Connect, 1, tempvar_46, 0); IHDL4SEUnit** tempvar_47 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_47"); IHDL4SEUnit **tempvar_35 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_35"); objectCall3(tempvar_35, Connect, 0, tempvar_36, 2); objectCall3(tempvar_35, Connect, 1, tempvar_47, 0); objectCall3(tempvar_35, Connect, 2, tempvar_41, 2); objectCall3(nets[13], Connect, 0, tempvar_35, 3); /* assign curblockline = (((blockx<3))?((curblockline_0>>((3-blockx)*4))):((curblockline_0<<((blockx-3)*4)))); */ IHDL4SEUnit** tempvar_50 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_50"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], 3, 1, BINOP_LT); IHDL4SEUnit **tempvar_49 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_49"); objectCall3(tempvar_49, Connect, 0, nets[2], 0); objectCall3(tempvar_49, Connect, 1, tempvar_50, 0); IHDL4SEUnit** tempvar_54 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_54"); sprintf(__instparam, "%d, %d, %d, %d", 3, __netswidth[2], 0, BINOP_SUB); IHDL4SEUnit **tempvar_53 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_53"); objectCall3(tempvar_53, Connect, 0, tempvar_54, 0); objectCall3(tempvar_53, Connect, 1, nets[2], 0); IHDL4SEUnit** tempvar_55 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_55"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_52 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_52"); objectCall3(tempvar_52, Connect, 0, tempvar_53, 2); objectCall3(tempvar_52, Connect, 1, tempvar_55, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[13], 0, 0, BINOP_SHR); IHDL4SEUnit **tempvar_51 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_51"); objectCall3(tempvar_51, Connect, 0, nets[13], 0); objectCall3(tempvar_51, Connect, 1, tempvar_52, 2); IHDL4SEUnit** tempvar_59 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_59"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], 3, 0, BINOP_SUB); IHDL4SEUnit **tempvar_58 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_58"); objectCall3(tempvar_58, Connect, 0, nets[2], 0); objectCall3(tempvar_58, Connect, 1, tempvar_59, 0); IHDL4SEUnit** tempvar_60 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_60"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_57 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_57"); objectCall3(tempvar_57, Connect, 0, tempvar_58, 2); objectCall3(tempvar_57, Connect, 1, tempvar_60, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[13], 0, 0, BINOP_SHL); IHDL4SEUnit **tempvar_56 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_56"); objectCall3(tempvar_56, Connect, 0, nets[13], 0); objectCall3(tempvar_56, Connect, 1, tempvar_57, 2); IHDL4SEUnit **tempvar_48 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_48"); objectCall3(tempvar_48, Connect, 0, tempvar_49, 2); objectCall3(tempvar_48, Connect, 1, tempvar_56, 2); objectCall3(tempvar_48, Connect, 2, tempvar_51, 2); objectCall3(nets[14], Connect, 0, tempvar_48, 3); /* assign data = (bFlushReadData|curblockline); */ sprintf(__instparam, "%d, %d, %d, %d", __portswidth[4], __netswidth[14], 0, BINOP_OR); IHDL4SEUnit **tempvar_61 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_61"); objectCall3(tempvar_61, Connect, 0, unit, 4); objectCall3(tempvar_61, Connect, 1, nets[14], 0); objectCall3(nets[15], Connect, 0, tempvar_61, 2); /* assign right = wireout_readaddr_delay_1 [0] ; */ IHDL4SEUnit** tempvar_62 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 1, 0", "tempvar_62"); objectCall3(tempvar_62, Connect, 0, nets[6], 0); objectCall3(nets[16], Connect, 0, tempvar_62, 1); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_0014(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module blockwrite */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[7]; int __netswidth[7]; IHDL4SEUnit** modules[2]; int __portswidth[10]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "bCtrlState", 4, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 4; /* 2*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT); /* 2*/ __portswidth[2] = 1; /* 3*/ objectCall4(module, AddPort, "bBWReadAddr", 6, 1, PORT_DIRECT_OUTPUT); /* 3*/ __portswidth[3] = 6; /* 4*/ objectCall4(module, AddPort, "bBWReadData", 64, 1, PORT_DIRECT_INPUT ); /* 4*/ __portswidth[4] = 64; /* 5*/ objectCall4(module, AddPort, "wBWWrite", 1, 1, PORT_DIRECT_OUTPUT); /* 5*/ __portswidth[5] = 1; /* 6*/ objectCall4(module, AddPort, "bBWWriteAddr", 6, 1, PORT_DIRECT_OUTPUT); /* 6*/ __portswidth[6] = 6; /* 7*/ objectCall4(module, AddPort, "bBWWriteData", 64, 1, PORT_DIRECT_OUTPUT); /* 7*/ __portswidth[7] = 64; /* 8*/ objectCall4(module, AddPort, "bCurBlock", 64, 1, PORT_DIRECT_INPUT ); /* 8*/ __portswidth[8] = 64; /* 9*/ objectCall4(module, AddPort, "bCurBlockPos", 16, 1, PORT_DIRECT_INPUT ); /* 9*/ __portswidth[9] = 16; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 7", "wirein_readaddr"); __netswidth[0] = 7; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 7", "wireout_readaddr"); __netswidth[1] = 7; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 7", "wireout_readaddr_delay_1"); __netswidth[2] = 7; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "blockx"); __netswidth[3] = 8; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "blocky"); __netswidth[4] = 8; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline"); __netswidth[5] = 64; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_1"); __netswidth[6] = 64; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramreadaddr"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(nets[1], Connect, 0, modules[0], 2); modules[ 1] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramreadaddr_delay_1"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(modules[1], Connect, 1, nets[1], 0); objectCall3(nets[2], Connect, 0, modules[1], 2); /* 持续性赋值 */ /* assign wirein_readaddr = (((bCtrlState==4))?((wireout_readaddr+1)):(0)); */ IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_2"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_1"); objectCall3(tempvar_1, Connect, 0, unit, 1); objectCall3(tempvar_1, Connect, 1, tempvar_2, 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_4"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_3"); objectCall3(tempvar_3, Connect, 0, nets[1], 0); objectCall3(tempvar_3, Connect, 1, tempvar_4, 0); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_5"); IHDL4SEUnit **tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, tempvar_1, 2); objectCall3(tempvar_0, Connect, 1, tempvar_5, 0); objectCall3(tempvar_0, Connect, 2, tempvar_3, 2); objectCall3(nets[0], Connect, 0, tempvar_0, 3); /* assign curblockline_1 = ((bCurBlock>>((3-wireout_readaddr_delay_1)*16))&64'hffff); */ IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_10"); sprintf(__instparam, "%d, %d, %d, %d", 3, __netswidth[2], 0, BINOP_SUB); IHDL4SEUnit **tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_9"); objectCall3(tempvar_9, Connect, 0, tempvar_10, 0); objectCall3(tempvar_9, Connect, 1, nets[2], 0); IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 16", "tempvar_11"); sprintf(__instparam, "%d, %d, %d, %d", 0, 6, 0, BINOP_MUL); IHDL4SEUnit **tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_8"); objectCall3(tempvar_8, Connect, 0, tempvar_9, 2); objectCall3(tempvar_8, Connect, 1, tempvar_11, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[8], 0, 0, BINOP_SHR); IHDL4SEUnit **tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_7"); objectCall3(tempvar_7, Connect, 0, unit, 8); objectCall3(tempvar_7, Connect, 1, tempvar_8, 2); IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h00000ffff", "tempvar_12"); sprintf(__instparam, "%d, %d, %d, %d", 0, 64, 0, BINOP_AND); IHDL4SEUnit **tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_6"); objectCall3(tempvar_6, Connect, 0, tempvar_7, 2); objectCall3(tempvar_6, Connect, 1, tempvar_12, 0); objectCall3(nets[6], Connect, 0, tempvar_6, 2); /* assign curblockline = (((blockx<3))?((curblockline_1>>((3-blockx)*4))):((curblockline_1<<((blockx-3)*4)))); */ IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_15"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 3, 1, BINOP_LT); IHDL4SEUnit **tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_14"); objectCall3(tempvar_14, Connect, 0, nets[3], 0); objectCall3(tempvar_14, Connect, 1, tempvar_15, 0); IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_19"); sprintf(__instparam, "%d, %d, %d, %d", 3, __netswidth[3], 0, BINOP_SUB); IHDL4SEUnit **tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_18"); objectCall3(tempvar_18, Connect, 0, tempvar_19, 0); objectCall3(tempvar_18, Connect, 1, nets[3], 0); IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_20"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_17"); objectCall3(tempvar_17, Connect, 0, tempvar_18, 2); objectCall3(tempvar_17, Connect, 1, tempvar_20, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[6], 0, 0, BINOP_SHR); IHDL4SEUnit **tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_16"); objectCall3(tempvar_16, Connect, 0, nets[6], 0); objectCall3(tempvar_16, Connect, 1, tempvar_17, 2); IHDL4SEUnit** tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_24"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], 3, 0, BINOP_SUB); IHDL4SEUnit **tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_23"); objectCall3(tempvar_23, Connect, 0, nets[3], 0); objectCall3(tempvar_23, Connect, 1, tempvar_24, 0); IHDL4SEUnit** tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_25"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_22"); objectCall3(tempvar_22, Connect, 0, tempvar_23, 2); objectCall3(tempvar_22, Connect, 1, tempvar_25, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[6], 0, 0, BINOP_SHL); IHDL4SEUnit **tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_21"); objectCall3(tempvar_21, Connect, 0, nets[6], 0); objectCall3(tempvar_21, Connect, 1, tempvar_22, 2); IHDL4SEUnit **tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_13"); objectCall3(tempvar_13, Connect, 0, tempvar_14, 2); objectCall3(tempvar_13, Connect, 1, tempvar_21, 2); objectCall3(tempvar_13, Connect, 2, tempvar_16, 2); objectCall3(nets[5], Connect, 0, tempvar_13, 3); /* assign wCtrlStateComplete = (wireout_readaddr_delay_1>=4); */ IHDL4SEUnit** tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_27"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], 4, 1, BINOP_GE); IHDL4SEUnit **tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_26"); objectCall3(tempvar_26, Connect, 0, nets[2], 0); objectCall3(tempvar_26, Connect, 1, tempvar_27, 0); objectCall3(unit, Connect, 2, tempvar_26, 2); /* assign bBWReadAddr = ((wireout_readaddr+blocky)-4); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], __netswidth[4], 0, BINOP_ADD); IHDL4SEUnit **tempvar_29 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_29"); objectCall3(tempvar_29, Connect, 0, nets[1], 0); objectCall3(tempvar_29, Connect, 1, nets[4], 0); IHDL4SEUnit** tempvar_30 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_30"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_SUB); IHDL4SEUnit **tempvar_28 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_28"); objectCall3(tempvar_28, Connect, 0, tempvar_29, 2); objectCall3(tempvar_28, Connect, 1, tempvar_30, 0); objectCall3(unit, Connect, 3, tempvar_28, 2); /* assign wBWWrite = (((wireout_readaddr>0)&&(wireout_readaddr_delay_1>=0))&&(wireout_readaddr_delay_1<=3)); */ IHDL4SEUnit** tempvar_34 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_34"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 1, BINOP_GT); IHDL4SEUnit **tempvar_33 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_33"); objectCall3(tempvar_33, Connect, 0, nets[1], 0); objectCall3(tempvar_33, Connect, 1, tempvar_34, 0); IHDL4SEUnit** tempvar_36 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_36"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], 2, 1, BINOP_GE); IHDL4SEUnit **tempvar_35 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_35"); objectCall3(tempvar_35, Connect, 0, nets[2], 0); objectCall3(tempvar_35, Connect, 1, tempvar_36, 0); IHDL4SEUnit **tempvar_32 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_32"); objectCall3(tempvar_32, Connect, 0, tempvar_33, 2); objectCall3(tempvar_32, Connect, 1, tempvar_35, 2); IHDL4SEUnit** tempvar_38 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_38"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], 3, 1, BINOP_LE); IHDL4SEUnit **tempvar_37 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_37"); objectCall3(tempvar_37, Connect, 0, nets[2], 0); objectCall3(tempvar_37, Connect, 1, tempvar_38, 0); IHDL4SEUnit **tempvar_31 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_31"); objectCall3(tempvar_31, Connect, 0, tempvar_32, 2); objectCall3(tempvar_31, Connect, 1, tempvar_37, 2); objectCall3(unit, Connect, 5, tempvar_31, 2); /* assign bBWWriteAddr = ((wireout_readaddr_delay_1+blocky)-4); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], __netswidth[4], 0, BINOP_ADD); IHDL4SEUnit **tempvar_40 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_40"); objectCall3(tempvar_40, Connect, 0, nets[2], 0); objectCall3(tempvar_40, Connect, 1, nets[4], 0); IHDL4SEUnit** tempvar_41 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_41"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_SUB); IHDL4SEUnit **tempvar_39 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_39"); objectCall3(tempvar_39, Connect, 0, tempvar_40, 2); objectCall3(tempvar_39, Connect, 1, tempvar_41, 0); objectCall3(unit, Connect, 6, tempvar_39, 2); /* assign bBWWriteData = (bBWReadData|curblockline); */ sprintf(__instparam, "%d, %d, %d, %d", __portswidth[4], __netswidth[5], 0, BINOP_OR); IHDL4SEUnit **tempvar_42 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_42"); objectCall3(tempvar_42, Connect, 0, unit, 4); objectCall3(tempvar_42, Connect, 1, nets[5], 0); objectCall3(unit, Connect, 7, tempvar_42, 2); /* assign blockx = bCurBlockPos [7:0] ; */ IHDL4SEUnit** tempvar_43 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 8, 0", "tempvar_43"); objectCall3(tempvar_43, Connect, 0, unit, 9); objectCall3(nets[3], Connect, 0, tempvar_43, 1); /* assign blocky = bCurBlockPos [15:8] ; */ IHDL4SEUnit** tempvar_44 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 8, 8", "tempvar_44"); objectCall3(tempvar_44, Connect, 0, unit, 9); objectCall3(nets[4], Connect, 0, tempvar_44, 1); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_0015(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module canblocksetto */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[36]; int __netswidth[36]; IHDL4SEUnit** modules[3]; int __portswidth[8]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "bCtrlState", 4, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 4; /* 2*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT); /* 2*/ __portswidth[2] = 1; /* 3*/ objectCall4(module, AddPort, "bCBWReadAddr", 6, 1, PORT_DIRECT_OUTPUT); /* 3*/ __portswidth[3] = 6; /* 4*/ objectCall4(module, AddPort, "bCBWReadData", 64, 1, PORT_DIRECT_INPUT ); /* 4*/ __portswidth[4] = 64; /* 5*/ objectCall4(module, AddPort, "bCurBlock", 64, 1, PORT_DIRECT_INPUT ); /* 5*/ __portswidth[5] = 64; /* 6*/ objectCall4(module, AddPort, "bSetToPos", 16, 1, PORT_DIRECT_INPUT ); /* 6*/ __portswidth[6] = 16; /* 7*/ objectCall4(module, AddPort, "wCanSet", 1, 1, PORT_DIRECT_OUTPUT); /* 7*/ __portswidth[7] = 1; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_readaddr"); __netswidth[0] = 8; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_readaddr"); __netswidth[1] = 8; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_readaddr_delay_1"); __netswidth[2] = 8; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wirein_cansetto"); __netswidth[3] = 1; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wireout_cansetto"); __netswidth[4] = 1; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "blockx"); __netswidth[5] = 8; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "blocky"); __netswidth[6] = 8; nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "readdata"); __netswidth[7] = 64; nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "_bCBWReadAddr"); __netswidth[8] = 8; nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCanSetCurrent"); __netswidth[9] = 1; nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCanSetCurrentPre"); __netswidth[10] = 1; nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "y"); __netswidth[11] = 8; nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCanSetCurrent_1"); __netswidth[12] = 1; nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCanSetCurrent_1_1"); __netswidth[13] = 1; nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCanSetCurrent_1_2"); __netswidth[14] = 1; nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCanSetCurrent_1_3"); __netswidth[15] = 1; nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCanSetCurrent_2"); __netswidth[16] = 1; nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCanSetCurrent_3"); __netswidth[17] = 1; nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline"); __netswidth[18] = 64; nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_0"); __netswidth[19] = 64; nets[ 20] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_1"); __netswidth[20] = 64; nets[ 21] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_2"); __netswidth[21] = 64; nets[ 22] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_3"); __netswidth[22] = 64; nets[ 23] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_mask"); __netswidth[23] = 64; nets[ 24] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_mask_1"); __netswidth[24] = 64; nets[ 25] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "all1"); __netswidth[25] = 64; nets[ 26] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "shift0"); __netswidth[26] = 8; nets[ 27] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "shift1"); __netswidth[27] = 8; nets[ 28] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "mask0"); __netswidth[28] = 64; nets[ 29] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "mask1"); __netswidth[29] = 64; nets[ 30] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_mask_0"); __netswidth[30] = 64; nets[ 31] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_mask_1"); __netswidth[31] = 64; nets[ 32] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "cblmask1"); __netswidth[32] = 1; nets[ 33] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "blockxgt3"); __netswidth[33] = 1; nets[ 34] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "curblockline_mask_2"); __netswidth[34] = 64; nets[ 35] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "line"); __netswidth[35] = 64; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "reg_readaddr"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(nets[1], Connect, 0, modules[0], 2); modules[ 1] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "8", "reg_readaddr_delay_1"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(modules[1], Connect, 1, nets[1], 0); objectCall3(nets[2], Connect, 0, modules[1], 2); modules[ 2] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "1", "reg_cansetto"); objectCall3(modules[2], Connect, 0, unit, 0); objectCall3(modules[2], Connect, 1, nets[3], 0); objectCall3(nets[4], Connect, 0, modules[2], 2); /* 持续性赋值 */ /* assign wCanSet = wireout_cansetto; */ objectCall3(unit, Connect, 7, nets[4], 0); /* assign bCBWReadAddr = _bCBWReadAddr; */ objectCall3(unit, Connect, 3, nets[8], 0); /* assign wCtrlStateComplete = ((wireout_readaddr_delay_1>4)||(wireout_cansetto==0)); */ IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_2"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], 4, 1, BINOP_GT); IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_1"); objectCall3(tempvar_1, Connect, 0, nets[2], 0); objectCall3(tempvar_1, Connect, 1, tempvar_2, 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_4"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[4], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_3"); objectCall3(tempvar_3, Connect, 0, nets[4], 0); objectCall3(tempvar_3, Connect, 1, tempvar_4, 0); IHDL4SEUnit **tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, tempvar_1, 2); objectCall3(tempvar_0, Connect, 1, tempvar_3, 2); objectCall3(unit, Connect, 2, tempvar_0, 2); /* assign wirein_readaddr = (((bCtrlState==3))?((wireout_readaddr+1)):(0)); */ IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_7"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 3, 1, BINOP_EQ); IHDL4SEUnit **tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_6"); objectCall3(tempvar_6, Connect, 0, unit, 1); objectCall3(tempvar_6, Connect, 1, tempvar_7, 0); IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_9"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_8"); objectCall3(tempvar_8, Connect, 0, nets[1], 0); objectCall3(tempvar_8, Connect, 1, tempvar_9, 0); IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_10"); IHDL4SEUnit **tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_5"); objectCall3(tempvar_5, Connect, 0, tempvar_6, 2); objectCall3(tempvar_5, Connect, 1, tempvar_10, 0); objectCall3(tempvar_5, Connect, 2, tempvar_8, 2); objectCall3(nets[0], Connect, 0, tempvar_5, 3); /* assign wirein_cansetto = (((bCtrlState==3))?(wCanSetCurrentPre):(1)); */ IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 3", "tempvar_13"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 3, 1, BINOP_EQ); IHDL4SEUnit **tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_12"); objectCall3(tempvar_12, Connect, 0, unit, 1); objectCall3(tempvar_12, Connect, 1, tempvar_13, 0); IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_14"); IHDL4SEUnit **tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_11"); objectCall3(tempvar_11, Connect, 0, tempvar_12, 2); objectCall3(tempvar_11, Connect, 1, tempvar_14, 0); objectCall3(tempvar_11, Connect, 2, nets[10], 0); objectCall3(nets[3], Connect, 0, tempvar_11, 3); /* assign wCanSetCurrentPre = ((((wireout_readaddr>0)&&(wCanSetCurrent==0)))?(0):(wireout_cansetto)); */ IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_18"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 1, BINOP_GT); IHDL4SEUnit **tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_17"); objectCall3(tempvar_17, Connect, 0, nets[1], 0); objectCall3(tempvar_17, Connect, 1, tempvar_18, 0); IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_20"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[9], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_19"); objectCall3(tempvar_19, Connect, 0, nets[9], 0); objectCall3(tempvar_19, Connect, 1, tempvar_20, 0); IHDL4SEUnit **tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_16"); objectCall3(tempvar_16, Connect, 0, tempvar_17, 2); objectCall3(tempvar_16, Connect, 1, tempvar_19, 2); IHDL4SEUnit** tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_21"); IHDL4SEUnit **tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_15"); objectCall3(tempvar_15, Connect, 0, tempvar_16, 2); objectCall3(tempvar_15, Connect, 1, nets[4], 0); objectCall3(tempvar_15, Connect, 2, tempvar_21, 0); objectCall3(nets[10], Connect, 0, tempvar_15, 3); /* assign wCanSetCurrent = (((wireout_readaddr_delay_1>=4))?(1):(wCanSetCurrent_1_1)); */ IHDL4SEUnit** tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_24"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], 4, 1, BINOP_GE); IHDL4SEUnit **tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_23"); objectCall3(tempvar_23, Connect, 0, nets[2], 0); objectCall3(tempvar_23, Connect, 1, tempvar_24, 0); IHDL4SEUnit** tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_25"); IHDL4SEUnit **tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_22"); objectCall3(tempvar_22, Connect, 0, tempvar_23, 2); objectCall3(tempvar_22, Connect, 1, nets[13], 0); objectCall3(tempvar_22, Connect, 2, tempvar_25, 0); objectCall3(nets[9], Connect, 0, tempvar_22, 3); /* assign wCanSetCurrent_1_1 = (((y>=(24+4)))?(1):(wCanSetCurrent_1_2)); */ IHDL4SEUnit** tempvar_28 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 28", "tempvar_28"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[11], 6, 1, BINOP_GE); IHDL4SEUnit **tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_27"); objectCall3(tempvar_27, Connect, 0, nets[11], 0); objectCall3(tempvar_27, Connect, 1, tempvar_28, 0); IHDL4SEUnit** tempvar_29 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_29"); IHDL4SEUnit **tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_26"); objectCall3(tempvar_26, Connect, 0, tempvar_27, 2); objectCall3(tempvar_26, Connect, 1, nets[14], 0); objectCall3(tempvar_26, Connect, 2, tempvar_29, 0); objectCall3(nets[13], Connect, 0, tempvar_26, 3); /* assign wCanSetCurrent_1_2 = (((curblockline==0))?(1):(wCanSetCurrent_1)); */ IHDL4SEUnit** tempvar_32 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_32"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[18], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_31 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_31"); objectCall3(tempvar_31, Connect, 0, nets[18], 0); objectCall3(tempvar_31, Connect, 1, tempvar_32, 0); IHDL4SEUnit** tempvar_33 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_33"); IHDL4SEUnit **tempvar_30 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_30"); objectCall3(tempvar_30, Connect, 0, tempvar_31, 2); objectCall3(tempvar_30, Connect, 1, nets[12], 0); objectCall3(tempvar_30, Connect, 2, tempvar_33, 0); objectCall3(nets[14], Connect, 0, tempvar_30, 3); /* assign wCanSetCurrent_1 = ((((curblockline [15:0] !=0)&&(y<8'd4)))?(0):(wCanSetCurrent_2)); */ IHDL4SEUnit** tempvar_37 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 16, 0", "tempvar_37"); objectCall3(tempvar_37, Connect, 0, nets[18], 0); IHDL4SEUnit** tempvar_38 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_38"); IHDL4SEUnit **tempvar_36 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "16, 16, 1, 13", "tempvar_36"); objectCall3(tempvar_36, Connect, 0, tempvar_37, 1); objectCall3(tempvar_36, Connect, 1, tempvar_38, 0); IHDL4SEUnit** tempvar_40 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 4", "tempvar_40"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[11], 8, 1, BINOP_LT); IHDL4SEUnit **tempvar_39 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_39"); objectCall3(tempvar_39, Connect, 0, nets[11], 0); objectCall3(tempvar_39, Connect, 1, tempvar_40, 0); IHDL4SEUnit **tempvar_35 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_35"); objectCall3(tempvar_35, Connect, 0, tempvar_36, 2); objectCall3(tempvar_35, Connect, 1, tempvar_39, 2); IHDL4SEUnit** tempvar_41 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_41"); IHDL4SEUnit **tempvar_34 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_34"); objectCall3(tempvar_34, Connect, 0, tempvar_35, 2); objectCall3(tempvar_34, Connect, 1, nets[16], 0); objectCall3(tempvar_34, Connect, 2, tempvar_41, 0); objectCall3(nets[12], Connect, 0, tempvar_34, 3); /* assign curblockline_0 = (((curblockline [3:0] !=0))?(64'hf):(64'h0)); */ IHDL4SEUnit** tempvar_44 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 0", "tempvar_44"); objectCall3(tempvar_44, Connect, 0, nets[18], 0); IHDL4SEUnit** tempvar_45 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_45"); IHDL4SEUnit **tempvar_43 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_43"); objectCall3(tempvar_43, Connect, 0, tempvar_44, 1); objectCall3(tempvar_43, Connect, 1, tempvar_45, 0); IHDL4SEUnit** tempvar_46 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h00000000f", "tempvar_46"); IHDL4SEUnit** tempvar_47 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_47"); IHDL4SEUnit **tempvar_42 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "64", "tempvar_42"); objectCall3(tempvar_42, Connect, 0, tempvar_43, 2); objectCall3(tempvar_42, Connect, 1, tempvar_47, 0); objectCall3(tempvar_42, Connect, 2, tempvar_46, 0); objectCall3(nets[19], Connect, 0, tempvar_42, 3); /* assign curblockline_1 = (((curblockline [7:4] !=0))?(64'hf0):(64'h0)); */ IHDL4SEUnit** tempvar_50 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 4", "tempvar_50"); objectCall3(tempvar_50, Connect, 0, nets[18], 0); IHDL4SEUnit** tempvar_51 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_51"); IHDL4SEUnit **tempvar_49 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_49"); objectCall3(tempvar_49, Connect, 0, tempvar_50, 1); objectCall3(tempvar_49, Connect, 1, tempvar_51, 0); IHDL4SEUnit** tempvar_52 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h0000000f0", "tempvar_52"); IHDL4SEUnit** tempvar_53 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_53"); IHDL4SEUnit **tempvar_48 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "64", "tempvar_48"); objectCall3(tempvar_48, Connect, 0, tempvar_49, 2); objectCall3(tempvar_48, Connect, 1, tempvar_53, 0); objectCall3(tempvar_48, Connect, 2, tempvar_52, 0); objectCall3(nets[20], Connect, 0, tempvar_48, 3); /* assign curblockline_2 = (((curblockline [11:8] !=0))?(64'hf00):(64'h0)); */ IHDL4SEUnit** tempvar_56 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 8", "tempvar_56"); objectCall3(tempvar_56, Connect, 0, nets[18], 0); IHDL4SEUnit** tempvar_57 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_57"); IHDL4SEUnit **tempvar_55 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_55"); objectCall3(tempvar_55, Connect, 0, tempvar_56, 1); objectCall3(tempvar_55, Connect, 1, tempvar_57, 0); IHDL4SEUnit** tempvar_58 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000f00", "tempvar_58"); IHDL4SEUnit** tempvar_59 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_59"); IHDL4SEUnit **tempvar_54 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "64", "tempvar_54"); objectCall3(tempvar_54, Connect, 0, tempvar_55, 2); objectCall3(tempvar_54, Connect, 1, tempvar_59, 0); objectCall3(tempvar_54, Connect, 2, tempvar_58, 0); objectCall3(nets[21], Connect, 0, tempvar_54, 3); /* assign curblockline_3 = (((curblockline [15:12] !=0))?(64'hf000):(64'h0)); */ IHDL4SEUnit** tempvar_62 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 12", "tempvar_62"); objectCall3(tempvar_62, Connect, 0, nets[18], 0); IHDL4SEUnit** tempvar_63 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_63"); IHDL4SEUnit **tempvar_61 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_61"); objectCall3(tempvar_61, Connect, 0, tempvar_62, 1); objectCall3(tempvar_61, Connect, 1, tempvar_63, 0); IHDL4SEUnit** tempvar_64 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h00000f000", "tempvar_64"); IHDL4SEUnit** tempvar_65 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_65"); IHDL4SEUnit **tempvar_60 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "64", "tempvar_60"); objectCall3(tempvar_60, Connect, 0, tempvar_61, 2); objectCall3(tempvar_60, Connect, 1, tempvar_65, 0); objectCall3(tempvar_60, Connect, 2, tempvar_64, 0); objectCall3(nets[22], Connect, 0, tempvar_60, 3); /* assign curblockline_mask = (((curblockline_0|curblockline_1)|curblockline_2)|curblockline_3); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[19], __netswidth[20], 0, BINOP_OR); IHDL4SEUnit **tempvar_68 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_68"); objectCall3(tempvar_68, Connect, 0, nets[19], 0); objectCall3(tempvar_68, Connect, 1, nets[20], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[21], 0, BINOP_OR); IHDL4SEUnit **tempvar_67 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_67"); objectCall3(tempvar_67, Connect, 0, tempvar_68, 2); objectCall3(tempvar_67, Connect, 1, nets[21], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[22], 0, BINOP_OR); IHDL4SEUnit **tempvar_66 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_66"); objectCall3(tempvar_66, Connect, 0, tempvar_67, 2); objectCall3(tempvar_66, Connect, 1, nets[22], 0); objectCall3(nets[23], Connect, 0, tempvar_66, 2); /* assign wCanSetCurrent_2 = (((blockx<8'd3))?((((curblockline_mask_0!=0))?(0):(wCanSetCurrent_3))):((((cblmask1&blockxgt3))?(0):(wCanSetCurrent_3)))); */ IHDL4SEUnit** tempvar_71 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 3", "tempvar_71"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 8, 1, BINOP_LT); IHDL4SEUnit **tempvar_70 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_70"); objectCall3(tempvar_70, Connect, 0, nets[5], 0); objectCall3(tempvar_70, Connect, 1, tempvar_71, 0); IHDL4SEUnit** tempvar_74 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_74"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[30], 2, 1, BINOP_NE); IHDL4SEUnit **tempvar_73 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_73"); objectCall3(tempvar_73, Connect, 0, nets[30], 0); objectCall3(tempvar_73, Connect, 1, tempvar_74, 0); IHDL4SEUnit** tempvar_75 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_75"); IHDL4SEUnit **tempvar_72 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_72"); objectCall3(tempvar_72, Connect, 0, tempvar_73, 2); objectCall3(tempvar_72, Connect, 1, nets[17], 0); objectCall3(tempvar_72, Connect, 2, tempvar_75, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[32], __netswidth[33], 0, BINOP_AND); IHDL4SEUnit **tempvar_77 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_77"); objectCall3(tempvar_77, Connect, 0, nets[32], 0); objectCall3(tempvar_77, Connect, 1, nets[33], 0); IHDL4SEUnit** tempvar_78 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_78"); IHDL4SEUnit **tempvar_76 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_76"); objectCall3(tempvar_76, Connect, 0, tempvar_77, 2); objectCall3(tempvar_76, Connect, 1, nets[17], 0); objectCall3(tempvar_76, Connect, 2, tempvar_78, 0); IHDL4SEUnit **tempvar_69 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_69"); objectCall3(tempvar_69, Connect, 0, tempvar_70, 2); objectCall3(tempvar_69, Connect, 1, tempvar_76, 3); objectCall3(tempvar_69, Connect, 2, tempvar_72, 3); objectCall3(nets[16], Connect, 0, tempvar_69, 3); /* assign wCanSetCurrent_3 = ((bCBWReadData&curblockline_mask_2)==0); */ sprintf(__instparam, "%d, %d, %d, %d", __portswidth[4], __netswidth[34], 0, BINOP_AND); IHDL4SEUnit **tempvar_80 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_80"); objectCall3(tempvar_80, Connect, 0, unit, 4); objectCall3(tempvar_80, Connect, 1, nets[34], 0); IHDL4SEUnit** tempvar_81 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_81"); sprintf(__instparam, "%d, %d, %d, %d", 0, 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_79 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_79"); objectCall3(tempvar_79, Connect, 0, tempvar_80, 2); objectCall3(tempvar_79, Connect, 1, tempvar_81, 0); objectCall3(nets[17], Connect, 0, tempvar_79, 2); /* assign blockx = bSetToPos [7:0] ; */ IHDL4SEUnit** tempvar_82 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 8, 0", "tempvar_82"); objectCall3(tempvar_82, Connect, 0, unit, 6); objectCall3(nets[5], Connect, 0, tempvar_82, 1); /* assign blocky = bSetToPos [15:8] ; */ IHDL4SEUnit** tempvar_83 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 8, 8", "tempvar_83"); objectCall3(tempvar_83, Connect, 0, unit, 6); objectCall3(nets[6], Connect, 0, tempvar_83, 1); /* assign readdata = bCBWReadData; */ objectCall3(nets[7], Connect, 0, unit, 4); /* assign _bCBWReadAddr = ((wireout_readaddr+blocky)-4); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], __netswidth[6], 0, BINOP_ADD); IHDL4SEUnit **tempvar_85 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_85"); objectCall3(tempvar_85, Connect, 0, nets[1], 0); objectCall3(tempvar_85, Connect, 1, nets[6], 0); IHDL4SEUnit** tempvar_86 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_86"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_SUB); IHDL4SEUnit **tempvar_84 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_84"); objectCall3(tempvar_84, Connect, 0, tempvar_85, 2); objectCall3(tempvar_84, Connect, 1, tempvar_86, 0); objectCall3(nets[8], Connect, 0, tempvar_84, 2); /* assign y = (wireout_readaddr_delay_1+blocky); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], __netswidth[6], 0, BINOP_ADD); IHDL4SEUnit **tempvar_87 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_87"); objectCall3(tempvar_87, Connect, 0, nets[2], 0); objectCall3(tempvar_87, Connect, 1, nets[6], 0); objectCall3(nets[11], Connect, 0, tempvar_87, 2); /* assign curblockline = (bCurBlock>>((8'd3-wireout_readaddr_delay_1)*16)); */ IHDL4SEUnit** tempvar_91 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 3", "tempvar_91"); sprintf(__instparam, "%d, %d, %d, %d", 8, __netswidth[2], 0, BINOP_SUB); IHDL4SEUnit **tempvar_90 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_90"); objectCall3(tempvar_90, Connect, 0, tempvar_91, 0); objectCall3(tempvar_90, Connect, 1, nets[2], 0); IHDL4SEUnit** tempvar_92 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 16", "tempvar_92"); sprintf(__instparam, "%d, %d, %d, %d", 0, 6, 0, BINOP_MUL); IHDL4SEUnit **tempvar_89 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_89"); objectCall3(tempvar_89, Connect, 0, tempvar_90, 2); objectCall3(tempvar_89, Connect, 1, tempvar_92, 0); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[5], 0, 0, BINOP_SHR); IHDL4SEUnit **tempvar_88 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_88"); objectCall3(tempvar_88, Connect, 0, unit, 5); objectCall3(tempvar_88, Connect, 1, tempvar_89, 2); objectCall3(nets[18], Connect, 0, tempvar_88, 2); /* assign all1 = 64'hffffffffffffffff; */ IHDL4SEUnit** tempvar_93 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'hffffffffffffffff", "tempvar_93"); objectCall3(nets[25], Connect, 0, tempvar_93, 0); /* assign shift0 = (64-((3-blockx)*4)); */ IHDL4SEUnit** tempvar_95 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 64", "tempvar_95"); IHDL4SEUnit** tempvar_98 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 3", "tempvar_98"); sprintf(__instparam, "%d, %d, %d, %d", 8, __netswidth[5], 0, BINOP_SUB); IHDL4SEUnit **tempvar_97 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_97"); objectCall3(tempvar_97, Connect, 0, tempvar_98, 0); objectCall3(tempvar_97, Connect, 1, nets[5], 0); IHDL4SEUnit** tempvar_99 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_99"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_96 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_96"); objectCall3(tempvar_96, Connect, 0, tempvar_97, 2); objectCall3(tempvar_96, Connect, 1, tempvar_99, 0); sprintf(__instparam, "%d, %d, %d, %d", 8, 0, 0, BINOP_SUB); IHDL4SEUnit **tempvar_94 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_94"); objectCall3(tempvar_94, Connect, 0, tempvar_95, 0); objectCall3(tempvar_94, Connect, 1, tempvar_96, 2); objectCall3(nets[26], Connect, 0, tempvar_94, 2); /* assign shift1 = (64-((blockx-8'd3)*4)); */ IHDL4SEUnit** tempvar_101 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 64", "tempvar_101"); IHDL4SEUnit** tempvar_104 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 3", "tempvar_104"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 8, 0, BINOP_SUB); IHDL4SEUnit **tempvar_103 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_103"); objectCall3(tempvar_103, Connect, 0, nets[5], 0); objectCall3(tempvar_103, Connect, 1, tempvar_104, 0); IHDL4SEUnit** tempvar_105 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_105"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_102 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_102"); objectCall3(tempvar_102, Connect, 0, tempvar_103, 2); objectCall3(tempvar_102, Connect, 1, tempvar_105, 0); sprintf(__instparam, "%d, %d, %d, %d", 8, 0, 0, BINOP_SUB); IHDL4SEUnit **tempvar_100 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_100"); objectCall3(tempvar_100, Connect, 0, tempvar_101, 0); objectCall3(tempvar_100, Connect, 1, tempvar_102, 2); objectCall3(nets[27], Connect, 0, tempvar_100, 2); /* assign mask0 = (all1>>shift0); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[25], __netswidth[26], 0, BINOP_SHR); IHDL4SEUnit **tempvar_106 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_106"); objectCall3(tempvar_106, Connect, 0, nets[25], 0); objectCall3(tempvar_106, Connect, 1, nets[26], 0); objectCall3(nets[28], Connect, 0, tempvar_106, 2); /* assign mask1 = (all1<8'd3); */ IHDL4SEUnit** tempvar_113 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 3", "tempvar_113"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 8, 1, BINOP_GT); IHDL4SEUnit **tempvar_112 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_112"); objectCall3(tempvar_112, Connect, 0, nets[5], 0); objectCall3(tempvar_112, Connect, 1, tempvar_113, 0); objectCall3(nets[33], Connect, 0, tempvar_112, 2); /* assign curblockline_mask_2 = (((blockx<8'd3))?((curblockline_mask>>((8'd3-blockx)*4))):((curblockline_mask<<((blockx-8'd3)*4)))); */ IHDL4SEUnit** tempvar_116 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 3", "tempvar_116"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 8, 1, BINOP_LT); IHDL4SEUnit **tempvar_115 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_115"); objectCall3(tempvar_115, Connect, 0, nets[5], 0); objectCall3(tempvar_115, Connect, 1, tempvar_116, 0); IHDL4SEUnit** tempvar_120 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 3", "tempvar_120"); sprintf(__instparam, "%d, %d, %d, %d", 8, __netswidth[5], 0, BINOP_SUB); IHDL4SEUnit **tempvar_119 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_119"); objectCall3(tempvar_119, Connect, 0, tempvar_120, 0); objectCall3(tempvar_119, Connect, 1, nets[5], 0); IHDL4SEUnit** tempvar_121 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_121"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_118 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_118"); objectCall3(tempvar_118, Connect, 0, tempvar_119, 2); objectCall3(tempvar_118, Connect, 1, tempvar_121, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[23], 0, 0, BINOP_SHR); IHDL4SEUnit **tempvar_117 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_117"); objectCall3(tempvar_117, Connect, 0, nets[23], 0); objectCall3(tempvar_117, Connect, 1, tempvar_118, 2); IHDL4SEUnit** tempvar_125 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "8, 3", "tempvar_125"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 8, 0, BINOP_SUB); IHDL4SEUnit **tempvar_124 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_124"); objectCall3(tempvar_124, Connect, 0, nets[5], 0); objectCall3(tempvar_124, Connect, 1, tempvar_125, 0); IHDL4SEUnit** tempvar_126 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 4", "tempvar_126"); sprintf(__instparam, "%d, %d, %d, %d", 0, 4, 0, BINOP_MUL); IHDL4SEUnit **tempvar_123 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_123"); objectCall3(tempvar_123, Connect, 0, tempvar_124, 2); objectCall3(tempvar_123, Connect, 1, tempvar_126, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[23], 0, 0, BINOP_SHL); IHDL4SEUnit **tempvar_122 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_122"); objectCall3(tempvar_122, Connect, 0, nets[23], 0); objectCall3(tempvar_122, Connect, 1, tempvar_123, 2); IHDL4SEUnit **tempvar_114 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_114"); objectCall3(tempvar_114, Connect, 0, tempvar_115, 2); objectCall3(tempvar_114, Connect, 1, tempvar_122, 2); objectCall3(tempvar_114, Connect, 2, tempvar_117, 2); objectCall3(nets[34], Connect, 0, tempvar_114, 3); /* assign line = bCBWReadData; */ objectCall3(nets[35], Connect, 0, unit, 4); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_0016(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module checkline */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[20]; int __netswidth[20]; IHDL4SEUnit** modules[2]; int __portswidth[6]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "bCtrlState", 4, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 4; /* 2*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT); /* 2*/ __portswidth[2] = 1; /* 3*/ objectCall4(module, AddPort, "bCKLReadAddr", 6, 1, PORT_DIRECT_OUTPUT); /* 3*/ __portswidth[3] = 6; /* 4*/ objectCall4(module, AddPort, "bCKLReadData", 64, 1, PORT_DIRECT_INPUT ); /* 4*/ __portswidth[4] = 64; /* 5*/ objectCall4(module, AddPort, "bFindLine", 32, 1, PORT_DIRECT_OUTPUT); /* 5*/ __portswidth[5] = 32; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_readaddr"); __netswidth[0] = 8; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_readaddr"); __netswidth[1] = 8; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_readaddr_delay_1"); __netswidth[2] = 8; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_0"); __netswidth[3] = 1; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_1"); __netswidth[4] = 1; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_2"); __netswidth[5] = 1; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_3"); __netswidth[6] = 1; nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_4"); __netswidth[7] = 1; nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_5"); __netswidth[8] = 1; nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_6"); __netswidth[9] = 1; nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_7"); __netswidth[10] = 1; nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_8"); __netswidth[11] = 1; nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_9"); __netswidth[12] = 1; nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_a"); __netswidth[13] = 1; nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_b"); __netswidth[14] = 1; nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_c"); __netswidth[15] = 1; nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_d"); __netswidth[16] = 1; nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_e"); __netswidth[17] = 1; nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "block_f"); __netswidth[18] = 1; nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "blockline"); __netswidth[19] = 1; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramreadaddr"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(nets[1], Connect, 0, modules[0], 2); modules[ 1] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramreadaddr_delay_1"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(modules[1], Connect, 1, nets[1], 0); objectCall3(nets[2], Connect, 0, modules[1], 2); /* 持续性赋值 */ /* assign wirein_readaddr = (((bCtrlState==5))?((wireout_readaddr+1)):(0)); */ IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 5", "tempvar_2"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_1"); objectCall3(tempvar_1, Connect, 0, unit, 1); objectCall3(tempvar_1, Connect, 1, tempvar_2, 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_4"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_3"); objectCall3(tempvar_3, Connect, 0, nets[1], 0); objectCall3(tempvar_3, Connect, 1, tempvar_4, 0); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_5"); IHDL4SEUnit **tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, tempvar_1, 2); objectCall3(tempvar_0, Connect, 1, tempvar_5, 0); objectCall3(tempvar_0, Connect, 2, tempvar_3, 2); objectCall3(nets[0], Connect, 0, tempvar_0, 3); /* assign bCKLReadAddr = wireout_readaddr; */ objectCall3(unit, Connect, 3, nets[1], 0); /* assign bFindLine = wireout_readaddr_delay_1; */ objectCall3(unit, Connect, 5, nets[2], 0); /* assign wCtrlStateComplete = ((wireout_readaddr_delay_1>24)||(blockline&&(wireout_readaddr>0))); */ IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_8"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[2], 6, 1, BINOP_GT); IHDL4SEUnit **tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_7"); objectCall3(tempvar_7, Connect, 0, nets[2], 0); objectCall3(tempvar_7, Connect, 1, tempvar_8, 0); IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_11"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 1, BINOP_GT); IHDL4SEUnit **tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_10"); objectCall3(tempvar_10, Connect, 0, nets[1], 0); objectCall3(tempvar_10, Connect, 1, tempvar_11, 0); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[19], 1, 1, BINOP_ANDL); IHDL4SEUnit **tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_9"); objectCall3(tempvar_9, Connect, 0, nets[19], 0); objectCall3(tempvar_9, Connect, 1, tempvar_10, 2); IHDL4SEUnit **tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 17", "tempvar_6"); objectCall3(tempvar_6, Connect, 0, tempvar_7, 2); objectCall3(tempvar_6, Connect, 1, tempvar_9, 2); objectCall3(unit, Connect, 2, tempvar_6, 2); /* assign block_0 = (bCKLReadData [3:0] !=4'b0); */ IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 0", "tempvar_13"); objectCall3(tempvar_13, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_14"); IHDL4SEUnit **tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_12"); objectCall3(tempvar_12, Connect, 0, tempvar_13, 1); objectCall3(tempvar_12, Connect, 1, tempvar_14, 0); objectCall3(nets[3], Connect, 0, tempvar_12, 2); /* assign block_1 = (bCKLReadData [7:4] !=4'b0); */ IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 4", "tempvar_16"); objectCall3(tempvar_16, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_17"); IHDL4SEUnit **tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_15"); objectCall3(tempvar_15, Connect, 0, tempvar_16, 1); objectCall3(tempvar_15, Connect, 1, tempvar_17, 0); objectCall3(nets[4], Connect, 0, tempvar_15, 2); /* assign block_2 = (bCKLReadData [11:8] !=4'b0); */ IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 8", "tempvar_19"); objectCall3(tempvar_19, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_20"); IHDL4SEUnit **tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_18"); objectCall3(tempvar_18, Connect, 0, tempvar_19, 1); objectCall3(tempvar_18, Connect, 1, tempvar_20, 0); objectCall3(nets[5], Connect, 0, tempvar_18, 2); /* assign block_3 = (bCKLReadData [15:12] !=4'b0); */ IHDL4SEUnit** tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 12", "tempvar_22"); objectCall3(tempvar_22, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_23"); IHDL4SEUnit **tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_21"); objectCall3(tempvar_21, Connect, 0, tempvar_22, 1); objectCall3(tempvar_21, Connect, 1, tempvar_23, 0); objectCall3(nets[6], Connect, 0, tempvar_21, 2); /* assign block_4 = (bCKLReadData [19:16] !=4'b0); */ IHDL4SEUnit** tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 16", "tempvar_25"); objectCall3(tempvar_25, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_26"); IHDL4SEUnit **tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_24"); objectCall3(tempvar_24, Connect, 0, tempvar_25, 1); objectCall3(tempvar_24, Connect, 1, tempvar_26, 0); objectCall3(nets[7], Connect, 0, tempvar_24, 2); /* assign block_5 = (bCKLReadData [23:20] !=4'b0); */ IHDL4SEUnit** tempvar_28 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 20", "tempvar_28"); objectCall3(tempvar_28, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_29 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_29"); IHDL4SEUnit **tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_27"); objectCall3(tempvar_27, Connect, 0, tempvar_28, 1); objectCall3(tempvar_27, Connect, 1, tempvar_29, 0); objectCall3(nets[8], Connect, 0, tempvar_27, 2); /* assign block_6 = (bCKLReadData [27:24] !=4'b0); */ IHDL4SEUnit** tempvar_31 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 24", "tempvar_31"); objectCall3(tempvar_31, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_32 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_32"); IHDL4SEUnit **tempvar_30 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_30"); objectCall3(tempvar_30, Connect, 0, tempvar_31, 1); objectCall3(tempvar_30, Connect, 1, tempvar_32, 0); objectCall3(nets[9], Connect, 0, tempvar_30, 2); /* assign block_7 = (bCKLReadData [31:28] !=4'b0); */ IHDL4SEUnit** tempvar_34 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 28", "tempvar_34"); objectCall3(tempvar_34, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_35 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_35"); IHDL4SEUnit **tempvar_33 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_33"); objectCall3(tempvar_33, Connect, 0, tempvar_34, 1); objectCall3(tempvar_33, Connect, 1, tempvar_35, 0); objectCall3(nets[10], Connect, 0, tempvar_33, 2); /* assign block_8 = (bCKLReadData [35:32] !=4'b0); */ IHDL4SEUnit** tempvar_37 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 32", "tempvar_37"); objectCall3(tempvar_37, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_38 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_38"); IHDL4SEUnit **tempvar_36 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_36"); objectCall3(tempvar_36, Connect, 0, tempvar_37, 1); objectCall3(tempvar_36, Connect, 1, tempvar_38, 0); objectCall3(nets[11], Connect, 0, tempvar_36, 2); /* assign block_9 = (bCKLReadData [39:36] !=4'b0); */ IHDL4SEUnit** tempvar_40 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 36", "tempvar_40"); objectCall3(tempvar_40, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_41 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_41"); IHDL4SEUnit **tempvar_39 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_39"); objectCall3(tempvar_39, Connect, 0, tempvar_40, 1); objectCall3(tempvar_39, Connect, 1, tempvar_41, 0); objectCall3(nets[12], Connect, 0, tempvar_39, 2); /* assign block_a = (bCKLReadData [43:40] !=4'b0); */ IHDL4SEUnit** tempvar_43 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 40", "tempvar_43"); objectCall3(tempvar_43, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_44 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_44"); IHDL4SEUnit **tempvar_42 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_42"); objectCall3(tempvar_42, Connect, 0, tempvar_43, 1); objectCall3(tempvar_42, Connect, 1, tempvar_44, 0); objectCall3(nets[13], Connect, 0, tempvar_42, 2); /* assign block_b = (bCKLReadData [47:44] !=4'b0); */ IHDL4SEUnit** tempvar_46 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 44", "tempvar_46"); objectCall3(tempvar_46, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_47 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_47"); IHDL4SEUnit **tempvar_45 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_45"); objectCall3(tempvar_45, Connect, 0, tempvar_46, 1); objectCall3(tempvar_45, Connect, 1, tempvar_47, 0); objectCall3(nets[14], Connect, 0, tempvar_45, 2); /* assign block_c = (bCKLReadData [51:48] !=4'b0); */ IHDL4SEUnit** tempvar_49 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 48", "tempvar_49"); objectCall3(tempvar_49, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_50 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_50"); IHDL4SEUnit **tempvar_48 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_48"); objectCall3(tempvar_48, Connect, 0, tempvar_49, 1); objectCall3(tempvar_48, Connect, 1, tempvar_50, 0); objectCall3(nets[15], Connect, 0, tempvar_48, 2); /* assign block_d = (bCKLReadData [55:52] !=4'b0); */ IHDL4SEUnit** tempvar_52 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 52", "tempvar_52"); objectCall3(tempvar_52, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_53 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_53"); IHDL4SEUnit **tempvar_51 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_51"); objectCall3(tempvar_51, Connect, 0, tempvar_52, 1); objectCall3(tempvar_51, Connect, 1, tempvar_53, 0); objectCall3(nets[16], Connect, 0, tempvar_51, 2); /* assign block_e = (bCKLReadData [59:56] !=4'b0); */ IHDL4SEUnit** tempvar_55 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 56", "tempvar_55"); objectCall3(tempvar_55, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_56 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_56"); IHDL4SEUnit **tempvar_54 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_54"); objectCall3(tempvar_54, Connect, 0, tempvar_55, 1); objectCall3(tempvar_54, Connect, 1, tempvar_56, 0); objectCall3(nets[17], Connect, 0, tempvar_54, 2); /* assign block_f = (bCKLReadData [63:60] !=4'b0); */ IHDL4SEUnit** tempvar_58 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "0, 4, 60", "tempvar_58"); objectCall3(tempvar_58, Connect, 0, unit, 4); IHDL4SEUnit** tempvar_59 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 0", "tempvar_59"); IHDL4SEUnit **tempvar_57 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "4, 4, 1, 13", "tempvar_57"); objectCall3(tempvar_57, Connect, 0, tempvar_58, 1); objectCall3(tempvar_57, Connect, 1, tempvar_59, 0); objectCall3(nets[18], Connect, 0, tempvar_57, 2); /* assign blockline = (((((((((((((((block_0&block_1)&block_2)&block_3)&block_4)&block_5)&block_6)&block_7)&block_8)&block_9)&block_a)&block_b)&block_c)&block_d)&block_e)&block_f); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[3], __netswidth[4], 0, BINOP_AND); IHDL4SEUnit **tempvar_74 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_74"); objectCall3(tempvar_74, Connect, 0, nets[3], 0); objectCall3(tempvar_74, Connect, 1, nets[4], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[5], 0, BINOP_AND); IHDL4SEUnit **tempvar_73 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_73"); objectCall3(tempvar_73, Connect, 0, tempvar_74, 2); objectCall3(tempvar_73, Connect, 1, nets[5], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[6], 0, BINOP_AND); IHDL4SEUnit **tempvar_72 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_72"); objectCall3(tempvar_72, Connect, 0, tempvar_73, 2); objectCall3(tempvar_72, Connect, 1, nets[6], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[7], 0, BINOP_AND); IHDL4SEUnit **tempvar_71 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_71"); objectCall3(tempvar_71, Connect, 0, tempvar_72, 2); objectCall3(tempvar_71, Connect, 1, nets[7], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[8], 0, BINOP_AND); IHDL4SEUnit **tempvar_70 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_70"); objectCall3(tempvar_70, Connect, 0, tempvar_71, 2); objectCall3(tempvar_70, Connect, 1, nets[8], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[9], 0, BINOP_AND); IHDL4SEUnit **tempvar_69 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_69"); objectCall3(tempvar_69, Connect, 0, tempvar_70, 2); objectCall3(tempvar_69, Connect, 1, nets[9], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[10], 0, BINOP_AND); IHDL4SEUnit **tempvar_68 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_68"); objectCall3(tempvar_68, Connect, 0, tempvar_69, 2); objectCall3(tempvar_68, Connect, 1, nets[10], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[11], 0, BINOP_AND); IHDL4SEUnit **tempvar_67 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_67"); objectCall3(tempvar_67, Connect, 0, tempvar_68, 2); objectCall3(tempvar_67, Connect, 1, nets[11], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[12], 0, BINOP_AND); IHDL4SEUnit **tempvar_66 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_66"); objectCall3(tempvar_66, Connect, 0, tempvar_67, 2); objectCall3(tempvar_66, Connect, 1, nets[12], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[13], 0, BINOP_AND); IHDL4SEUnit **tempvar_65 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_65"); objectCall3(tempvar_65, Connect, 0, tempvar_66, 2); objectCall3(tempvar_65, Connect, 1, nets[13], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[14], 0, BINOP_AND); IHDL4SEUnit **tempvar_64 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_64"); objectCall3(tempvar_64, Connect, 0, tempvar_65, 2); objectCall3(tempvar_64, Connect, 1, nets[14], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[15], 0, BINOP_AND); IHDL4SEUnit **tempvar_63 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_63"); objectCall3(tempvar_63, Connect, 0, tempvar_64, 2); objectCall3(tempvar_63, Connect, 1, nets[15], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[16], 0, BINOP_AND); IHDL4SEUnit **tempvar_62 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_62"); objectCall3(tempvar_62, Connect, 0, tempvar_63, 2); objectCall3(tempvar_62, Connect, 1, nets[16], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[17], 0, BINOP_AND); IHDL4SEUnit **tempvar_61 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_61"); objectCall3(tempvar_61, Connect, 0, tempvar_62, 2); objectCall3(tempvar_61, Connect, 1, nets[17], 0); sprintf(__instparam, "%d, %d, %d, %d", 0, __netswidth[18], 0, BINOP_AND); IHDL4SEUnit **tempvar_60 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_60"); objectCall3(tempvar_60, Connect, 0, tempvar_61, 2); objectCall3(tempvar_60, Connect, 1, nets[18], 0); objectCall3(nets[19], Connect, 0, tempvar_60, 2); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_0017(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module panelinit */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[2]; int __netswidth[2]; IHDL4SEUnit** modules[1]; int __portswidth[6]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "bCtrlState", 4, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 4; /* 2*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT); /* 2*/ __portswidth[2] = 1; /* 3*/ objectCall4(module, AddPort, "wInitWrite", 1, 1, PORT_DIRECT_OUTPUT); /* 3*/ __portswidth[3] = 1; /* 4*/ objectCall4(module, AddPort, "bInitWriteAddr", 6, 1, PORT_DIRECT_OUTPUT); /* 4*/ __portswidth[4] = 6; /* 5*/ objectCall4(module, AddPort, "bInitWriteData", 64, 1, PORT_DIRECT_OUTPUT); /* 5*/ __portswidth[5] = 64; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_writeaddr"); __netswidth[0] = 8; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_writeaddr"); __netswidth[1] = 8; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramwriteaddr"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(nets[1], Connect, 0, modules[0], 2); /* 持续性赋值 */ /* assign bInitWriteData = 64'h000000000; */ IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_0"); objectCall3(unit, Connect, 5, tempvar_0, 0); /* assign wirein_writeaddr = (((bCtrlState==0))?((wireout_writeaddr+1)):(0)); */ IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_3"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 2, 1, BINOP_EQ); IHDL4SEUnit **tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_2"); objectCall3(tempvar_2, Connect, 0, unit, 1); objectCall3(tempvar_2, Connect, 1, tempvar_3, 0); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_5"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_4"); objectCall3(tempvar_4, Connect, 0, nets[1], 0); objectCall3(tempvar_4, Connect, 1, tempvar_5, 0); IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_6"); IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_1"); objectCall3(tempvar_1, Connect, 0, tempvar_2, 2); objectCall3(tempvar_1, Connect, 1, tempvar_6, 0); objectCall3(tempvar_1, Connect, 2, tempvar_4, 2); objectCall3(nets[0], Connect, 0, tempvar_1, 3); /* assign wInitWrite = (wireout_writeaddr<=24); */ IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_8"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 6, 1, BINOP_LE); IHDL4SEUnit **tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_7"); objectCall3(tempvar_7, Connect, 0, nets[1], 0); objectCall3(tempvar_7, Connect, 1, tempvar_8, 0); objectCall3(unit, Connect, 3, tempvar_7, 2); /* assign wCtrlStateComplete = (wireout_writeaddr>24); */ IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_10"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 6, 1, BINOP_GT); IHDL4SEUnit **tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_9"); objectCall3(tempvar_9, Connect, 0, nets[1], 0); objectCall3(tempvar_9, Connect, 1, tempvar_10, 0); objectCall3(unit, Connect, 2, tempvar_9, 2); /* assign bInitWriteAddr = wireout_writeaddr; */ objectCall3(unit, Connect, 4, nets[1], 0); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_0018(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module copylines */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[6]; int __netswidth[6]; IHDL4SEUnit** modules[3]; int __portswidth[9]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "bCtrlState", 4, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 4; /* 2*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT); /* 2*/ __portswidth[2] = 1; /* 3*/ objectCall4(module, AddPort, "bReadAddr", 6, 1, PORT_DIRECT_OUTPUT); /* 3*/ __portswidth[3] = 6; /* 4*/ objectCall4(module, AddPort, "bReadData", 64, 1, PORT_DIRECT_INPUT ); /* 4*/ __portswidth[4] = 64; /* 5*/ objectCall4(module, AddPort, "wWrite", 1, 1, PORT_DIRECT_OUTPUT); /* 5*/ __portswidth[5] = 1; /* 6*/ objectCall4(module, AddPort, "bWriteAddr", 6, 1, PORT_DIRECT_OUTPUT); /* 6*/ __portswidth[6] = 6; /* 7*/ objectCall4(module, AddPort, "bWriteData", 64, 1, PORT_DIRECT_OUTPUT); /* 7*/ __portswidth[7] = 64; /* 8*/ objectCall4(module, AddPort, "bFromLine", 16, 1, PORT_DIRECT_INPUT ); /* 8*/ __portswidth[8] = 16; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_readaddr"); __netswidth[0] = 8; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_readaddr"); __netswidth[1] = 8; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_readaddr_delay_1"); __netswidth[2] = 8; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "wirein_fromline"); __netswidth[3] = 16; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "wireout_fromline"); __netswidth[4] = 16; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "y"); __netswidth[5] = 8; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "reg_readaddr"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(nets[1], Connect, 0, modules[0], 2); modules[ 1] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "reg_readaddr_delay_1"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(modules[1], Connect, 1, nets[1], 0); objectCall3(nets[2], Connect, 0, modules[1], 2); modules[ 2] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "reg_fromline"); objectCall3(modules[2], Connect, 0, unit, 0); objectCall3(modules[2], Connect, 1, nets[3], 0); objectCall3(nets[4], Connect, 0, modules[2], 2); /* 持续性赋值 */ /* assign wirein_readaddr = (((bCtrlState==6))?((wireout_readaddr+1)):(0)); */ IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 6", "tempvar_2"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_1"); objectCall3(tempvar_1, Connect, 0, unit, 1); objectCall3(tempvar_1, Connect, 1, tempvar_2, 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_4"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 2, 0, BINOP_ADD); IHDL4SEUnit **tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_3"); objectCall3(tempvar_3, Connect, 0, nets[1], 0); objectCall3(tempvar_3, Connect, 1, tempvar_4, 0); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_5"); IHDL4SEUnit **tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_0"); objectCall3(tempvar_0, Connect, 0, tempvar_1, 2); objectCall3(tempvar_0, Connect, 1, tempvar_5, 0); objectCall3(tempvar_0, Connect, 2, tempvar_3, 2); objectCall3(nets[0], Connect, 0, tempvar_0, 3); /* assign wirein_fromline = (((bCtrlState==6))?(bFromLine):(0)); */ IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "4, 6", "tempvar_8"); sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 4, 1, BINOP_EQ); IHDL4SEUnit **tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_7"); objectCall3(tempvar_7, Connect, 0, unit, 1); objectCall3(tempvar_7, Connect, 1, tempvar_8, 0); IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 0", "tempvar_9"); IHDL4SEUnit **tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_6"); objectCall3(tempvar_6, Connect, 0, tempvar_7, 2); objectCall3(tempvar_6, Connect, 1, tempvar_9, 0); objectCall3(tempvar_6, Connect, 2, unit, 8); objectCall3(nets[3], Connect, 0, tempvar_6, 3); /* assign bWriteAddr = (y-1); */ IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_11"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 2, 0, BINOP_SUB); IHDL4SEUnit **tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_10"); objectCall3(tempvar_10, Connect, 0, nets[5], 0); objectCall3(tempvar_10, Connect, 1, tempvar_11, 0); objectCall3(unit, Connect, 6, tempvar_10, 2); /* assign bWriteData = bReadData; */ objectCall3(unit, Connect, 7, unit, 4); /* assign wWrite = ((y>=1)&&(y<=24)); */ IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 1", "tempvar_14"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 2, 1, BINOP_GE); IHDL4SEUnit **tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_13"); objectCall3(tempvar_13, Connect, 0, nets[5], 0); objectCall3(tempvar_13, Connect, 1, tempvar_14, 0); IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_16"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 6, 1, BINOP_LE); IHDL4SEUnit **tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_15"); objectCall3(tempvar_15, Connect, 0, nets[5], 0); objectCall3(tempvar_15, Connect, 1, tempvar_16, 0); IHDL4SEUnit **tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "1, 1, 1, 16", "tempvar_12"); objectCall3(tempvar_12, Connect, 0, tempvar_13, 2); objectCall3(tempvar_12, Connect, 1, tempvar_15, 2); objectCall3(unit, Connect, 5, tempvar_12, 2); /* assign wCtrlStateComplete = (y>24); */ IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_18"); sprintf(__instparam, "%d, %d, %d, %d", __netswidth[5], 6, 1, BINOP_GT); IHDL4SEUnit **tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_17"); objectCall3(tempvar_17, Connect, 0, nets[5], 0); objectCall3(tempvar_17, Connect, 1, tempvar_18, 0); objectCall3(unit, Connect, 2, tempvar_17, 2); /* assign bReadAddr = (wireout_fromline+wireout_readaddr); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[4], __netswidth[1], 0, BINOP_ADD); IHDL4SEUnit **tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_19"); objectCall3(tempvar_19, Connect, 0, nets[4], 0); objectCall3(tempvar_19, Connect, 1, nets[1], 0); objectCall3(unit, Connect, 3, tempvar_19, 2); /* assign y = (wireout_fromline+wireout_readaddr_delay_1); */ sprintf(__instparam, "%d, %d, %d, %d", __netswidth[4], __netswidth[2], 0, BINOP_ADD); IHDL4SEUnit **tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_20"); objectCall3(tempvar_20, Connect, 0, nets[4], 0); objectCall3(tempvar_20, Connect, 1, nets[2], 0); objectCall3(nets[5], Connect, 0, tempvar_20, 2); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_001C(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module main */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[39]; int __netswidth[39]; IHDL4SEUnit** modules[15]; int __portswidth[9]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "nwReset", 1, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 1; /* 2*/ objectCall4(module, AddPort, "wWrite", 1, 1, PORT_DIRECT_OUTPUT); /* 2*/ __portswidth[2] = 1; /* 3*/ objectCall4(module, AddPort, "bWriteAddr", 32, 1, PORT_DIRECT_OUTPUT); /* 3*/ __portswidth[3] = 32; /* 4*/ objectCall4(module, AddPort, "bWriteData", 32, 1, PORT_DIRECT_OUTPUT); /* 4*/ __portswidth[4] = 32; /* 5*/ objectCall4(module, AddPort, "bWriteMask", 4, 1, PORT_DIRECT_OUTPUT); /* 5*/ __portswidth[5] = 4; /* 6*/ objectCall4(module, AddPort, "wRead", 1, 1, PORT_DIRECT_OUTPUT); /* 6*/ __portswidth[6] = 1; /* 7*/ objectCall4(module, AddPort, "bReadAddr", 32, 1, PORT_DIRECT_OUTPUT); /* 7*/ __portswidth[7] = 32; /* 8*/ objectCall4(module, AddPort, "bReadData", 32, 1, PORT_DIRECT_INPUT ); /* 8*/ __portswidth[8] = 32; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wram_Write"); __netswidth[0] = 1; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bram_WriteAddr"); __netswidth[1] = 6; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bram_WriteData"); __netswidth[2] = 64; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bram_ReadAddr"); __netswidth[3] = 6; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bram_ReadData"); __netswidth[4] = 64; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlKeyData"); __netswidth[5] = 32; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCtrlStateComplete"); __netswidth[6] = 1; nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "bCtrlState"); __netswidth[7] = 4; nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlSpeed"); __netswidth[8] = 32; nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlLevel"); __netswidth[9] = 32; nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlScore"); __netswidth[10] = 32; nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bNextBlock"); __netswidth[11] = 64; nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCurBlock"); __netswidth[12] = 64; nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "bCurBlockPos"); __netswidth[13] = 16; nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bResult"); __netswidth[14] = 32; nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bNewNextBlock"); __netswidth[15] = 64; nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wGBStateComplete"); __netswidth[16] = 1; nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bFlushReadAddr"); __netswidth[17] = 6; nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wFlushCtrlStateComplete"); __netswidth[18] = 1; nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bBWReadAddr"); __netswidth[19] = 6; nets[ 20] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bBWWriteAddr"); __netswidth[20] = 6; nets[ 21] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bBWWriteData"); __netswidth[21] = 64; nets[ 22] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wBWCtrlStateComplete"); __netswidth[22] = 1; nets[ 23] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wBWWrite"); __netswidth[23] = 1; nets[ 24] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bCBWReadAddr"); __netswidth[24] = 6; nets[ 25] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCBWCtrlStateComplete"); __netswidth[25] = 1; nets[ 26] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCBWCanSetTo"); __netswidth[26] = 1; nets[ 27] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bCKLReadAddr"); __netswidth[27] = 6; nets[ 28] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCKLCtrlStateComplete"); __netswidth[28] = 1; nets[ 29] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCKLResult"); __netswidth[29] = 32; nets[ 30] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bInitWriteAddr"); __netswidth[30] = 6; nets[ 31] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bInitWriteData"); __netswidth[31] = 64; nets[ 32] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wInitCtrlStateComplete"); __netswidth[32] = 1; nets[ 33] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wInitWrite"); __netswidth[33] = 1; nets[ 34] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bCLReadAddr"); __netswidth[34] = 6; nets[ 35] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bCLWriteAddr"); __netswidth[35] = 6; nets[ 36] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCLWriteData"); __netswidth[36] = 64; nets[ 37] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCLCtrlStateComplete"); __netswidth[37] = 1; nets[ 38] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCLWrite"); __netswidth[38] = 1; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "dffb1080-8b92-4b42-a607-d1b377c27bb1", "64, 5", "ram_0"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(modules[0], Connect, 2, nets[1], 0); objectCall3(modules[0], Connect, 3, nets[2], 0); objectCall3(modules[0], Connect, 4, nets[3], 0); objectCall3(nets[4], Connect, 0, modules[0], 5); modules[ 1] = hdl4seCreate_0012(module, "", "ctrl"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(modules[1], Connect, 1, unit, 1); objectCall3(modules[1], Connect, 2, nets[5], 0); objectCall3(modules[1], Connect, 3, nets[6], 0); objectCall3(nets[7], Connect, 0, modules[1], 4); objectCall3(nets[10], Connect, 0, modules[1], 5); objectCall3(nets[8], Connect, 0, modules[1], 6); objectCall3(nets[9], Connect, 0, modules[1], 7); objectCall3(nets[11], Connect, 0, modules[1], 8); objectCall3(nets[12], Connect, 0, modules[1], 9); objectCall3(nets[13], Connect, 0, modules[1], 10); objectCall3(modules[1], Connect, 11, nets[14], 0); objectCall3(modules[1], Connect, 12, nets[15], 0); modules[ 2] = hdl4seCreate_001B(module, "", "gennewblock"); objectCall3(modules[2], Connect, 0, unit, 0); objectCall3(modules[2], Connect, 1, unit, 1); objectCall3(modules[2], Connect, 2, nets[7], 0); objectCall3(nets[16], Connect, 0, modules[2], 3); objectCall3(nets[15], Connect, 0, modules[2], 4); modules[ 3] = hdl4seCreate_0013(module, "", "flusher"); objectCall3(modules[3], Connect, 0, unit, 0); objectCall3(modules[3], Connect, 1, nets[7], 0); objectCall3(nets[18], Connect, 0, modules[3], 2); objectCall3(nets[17], Connect, 0, modules[3], 3); objectCall3(modules[3], Connect, 4, nets[4], 0); objectCall3(unit, Connect, 2, modules[3], 5); objectCall3(unit, Connect, 3, modules[3], 6); objectCall3(unit, Connect, 4, modules[3], 7); objectCall3(modules[3], Connect, 8, nets[8], 0); objectCall3(modules[3], Connect, 9, nets[9], 0); objectCall3(modules[3], Connect, 10, nets[10], 0); objectCall3(modules[3], Connect, 11, nets[11], 0); objectCall3(modules[3], Connect, 12, nets[12], 0); objectCall3(modules[3], Connect, 13, nets[13], 0); modules[ 4] = hdl4seCreate_0014(module, "", "blockwriter"); objectCall3(modules[4], Connect, 0, unit, 0); objectCall3(modules[4], Connect, 1, nets[7], 0); objectCall3(nets[22], Connect, 0, modules[4], 2); objectCall3(nets[19], Connect, 0, modules[4], 3); objectCall3(modules[4], Connect, 4, nets[4], 0); objectCall3(nets[23], Connect, 0, modules[4], 5); objectCall3(nets[20], Connect, 0, modules[4], 6); objectCall3(nets[21], Connect, 0, modules[4], 7); objectCall3(modules[4], Connect, 8, nets[12], 0); objectCall3(modules[4], Connect, 9, nets[13], 0); modules[ 5] = hdl4seCreate_0015(module, "", "blocksetto"); objectCall3(modules[5], Connect, 0, unit, 0); objectCall3(modules[5], Connect, 1, nets[7], 0); objectCall3(nets[25], Connect, 0, modules[5], 2); objectCall3(nets[24], Connect, 0, modules[5], 3); objectCall3(modules[5], Connect, 4, nets[4], 0); objectCall3(modules[5], Connect, 5, nets[12], 0); objectCall3(modules[5], Connect, 6, nets[13], 0); objectCall3(nets[26], Connect, 0, modules[5], 7); modules[ 6] = hdl4seCreate_0016(module, "", "checkliner"); objectCall3(modules[6], Connect, 0, unit, 0); objectCall3(modules[6], Connect, 1, nets[7], 0); objectCall3(nets[28], Connect, 0, modules[6], 2); objectCall3(nets[27], Connect, 0, modules[6], 3); objectCall3(modules[6], Connect, 4, nets[4], 0); objectCall3(nets[29], Connect, 0, modules[6], 5); modules[ 7] = hdl4seCreate_0017(module, "", "initor"); objectCall3(modules[7], Connect, 0, unit, 0); objectCall3(modules[7], Connect, 1, nets[7], 0); objectCall3(nets[32], Connect, 0, modules[7], 2); objectCall3(nets[33], Connect, 0, modules[7], 3); objectCall3(nets[30], Connect, 0, modules[7], 4); objectCall3(nets[31], Connect, 0, modules[7], 5); modules[ 8] = hdl4seCreate_0018(module, "", "lineclear"); objectCall3(modules[8], Connect, 0, unit, 0); objectCall3(modules[8], Connect, 1, nets[7], 0); objectCall3(nets[37], Connect, 0, modules[8], 2); objectCall3(nets[34], Connect, 0, modules[8], 3); objectCall3(modules[8], Connect, 4, nets[4], 0); objectCall3(nets[38], Connect, 0, modules[8], 5); objectCall3(nets[35], Connect, 0, modules[8], 6); objectCall3(nets[36], Connect, 0, modules[8], 7); objectCall3(modules[8], Connect, 8, nets[13], 0); modules[ 9] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "32", "mux_Result"); objectCall3(modules[9], Connect, 0, nets[7], 0); IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_0"); objectCall3(modules[9], Connect, 1, tempvar_0, 0); IHDL4SEUnit** tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_1"); objectCall3(modules[9], Connect, 2, tempvar_1, 0); IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_2"); objectCall3(modules[9], Connect, 3, tempvar_2, 0); objectCall3(modules[9], Connect, 4, nets[26], 0); IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_3"); objectCall3(modules[9], Connect, 5, tempvar_3, 0); objectCall3(modules[9], Connect, 6, nets[29], 0); IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_4"); objectCall3(modules[9], Connect, 7, tempvar_4, 0); IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_5"); objectCall3(modules[9], Connect, 8, tempvar_5, 0); objectCall3(nets[14], Connect, 0, modules[9], 9); modules[ 10] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "1", "mux_Complete"); objectCall3(modules[10], Connect, 0, nets[7], 0); objectCall3(modules[10], Connect, 1, nets[32], 0); objectCall3(modules[10], Connect, 2, nets[18], 0); IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_6"); objectCall3(modules[10], Connect, 3, tempvar_6, 0); objectCall3(modules[10], Connect, 4, nets[25], 0); objectCall3(modules[10], Connect, 5, nets[22], 0); objectCall3(modules[10], Connect, 6, nets[28], 0); objectCall3(modules[10], Connect, 7, nets[37], 0); objectCall3(modules[10], Connect, 8, nets[16], 0); objectCall3(nets[6], Connect, 0, modules[10], 9); modules[ 11] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "1", "mux_ramWrite"); objectCall3(modules[11], Connect, 0, nets[7], 0); objectCall3(modules[11], Connect, 1, nets[33], 0); IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_7"); objectCall3(modules[11], Connect, 2, tempvar_7, 0); IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_8"); objectCall3(modules[11], Connect, 3, tempvar_8, 0); IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_9"); objectCall3(modules[11], Connect, 4, tempvar_9, 0); objectCall3(modules[11], Connect, 5, nets[23], 0); IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_10"); objectCall3(modules[11], Connect, 6, tempvar_10, 0); objectCall3(modules[11], Connect, 7, nets[38], 0); IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_11"); objectCall3(modules[11], Connect, 8, tempvar_11, 0); objectCall3(nets[0], Connect, 0, modules[11], 9); modules[ 12] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "6", "mux_ramWriteAddr"); objectCall3(modules[12], Connect, 0, nets[7], 0); objectCall3(modules[12], Connect, 1, nets[30], 0); IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_12"); objectCall3(modules[12], Connect, 2, tempvar_12, 0); IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_13"); objectCall3(modules[12], Connect, 3, tempvar_13, 0); IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_14"); objectCall3(modules[12], Connect, 4, tempvar_14, 0); objectCall3(modules[12], Connect, 5, nets[20], 0); IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_15"); objectCall3(modules[12], Connect, 6, tempvar_15, 0); objectCall3(modules[12], Connect, 7, nets[35], 0); IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_16"); objectCall3(modules[12], Connect, 8, tempvar_16, 0); objectCall3(nets[1], Connect, 0, modules[12], 9); modules[ 13] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "64", "mux_ramWriteData"); objectCall3(modules[13], Connect, 0, nets[7], 0); objectCall3(modules[13], Connect, 1, nets[31], 0); IHDL4SEUnit** tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_17"); objectCall3(modules[13], Connect, 2, tempvar_17, 0); IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_18"); objectCall3(modules[13], Connect, 3, tempvar_18, 0); IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_19"); objectCall3(modules[13], Connect, 4, tempvar_19, 0); objectCall3(modules[13], Connect, 5, nets[21], 0); IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_20"); objectCall3(modules[13], Connect, 6, tempvar_20, 0); objectCall3(modules[13], Connect, 7, nets[36], 0); IHDL4SEUnit** tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_21"); objectCall3(modules[13], Connect, 8, tempvar_21, 0); objectCall3(nets[2], Connect, 0, modules[13], 9); modules[ 14] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "6", "mux_ramReadAddr"); objectCall3(modules[14], Connect, 0, nets[7], 0); IHDL4SEUnit** tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_22"); objectCall3(modules[14], Connect, 1, tempvar_22, 0); objectCall3(modules[14], Connect, 2, nets[17], 0); IHDL4SEUnit** tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_23"); objectCall3(modules[14], Connect, 3, tempvar_23, 0); objectCall3(modules[14], Connect, 4, nets[24], 0); objectCall3(modules[14], Connect, 5, nets[19], 0); objectCall3(modules[14], Connect, 6, nets[27], 0); objectCall3(modules[14], Connect, 7, nets[34], 0); IHDL4SEUnit** tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_24"); objectCall3(modules[14], Connect, 8, tempvar_24, 0); objectCall3(nets[3], Connect, 0, modules[14], 9); /* 持续性赋值 */ /* assign wRead = 1; */ IHDL4SEUnit** tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_25"); objectCall3(unit, Connect, 6, tempvar_25, 0); /* assign bReadAddr = 32'hf0000000; */ IHDL4SEUnit** tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hf0000000", "tempvar_26"); objectCall3(unit, Connect, 7, tempvar_26, 0); /* assign bCtrlKeyData = bReadData; */ objectCall3(nets[5], Connect, 0, unit, 8); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_001E(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module top */ IHDL4SEModule** module; IHDL4SEUnit** unit; IHDL4SEUnit** nets[7]; int __netswidth[7]; IHDL4SEUnit** modules[2]; int __portswidth[2]; char __instparam[128]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); /* 得到对象的IHDL4SEModule 接口 */ objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); /* 端口 */ /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); /* 0*/ __portswidth[0] = 1; /* 1*/ objectCall4(module, AddPort, "nwReset", 1, 1, PORT_DIRECT_INPUT ); /* 1*/ __portswidth[1] = 1; /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wWrite"); __netswidth[0] = 1; nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wRead"); __netswidth[1] = 1; nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bWriteAddr"); __netswidth[2] = 32; nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bWriteData"); __netswidth[3] = 32; nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bReadAddr"); __netswidth[4] = 32; nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bReadData"); __netswidth[5] = 32; nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 4", "bWriteMask"); __netswidth[6] = 4; /* 模块实例化 */ modules[ 0] = hdl4seCreateUnit2(module, "81de7969-f783-4023-bde6-f815f8d59c05", "", "terrisui"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, unit, 1); objectCall3(modules[0], Connect, 2, nets[0], 0); objectCall3(modules[0], Connect, 3, nets[2], 0); objectCall3(modules[0], Connect, 4, nets[3], 0); objectCall3(modules[0], Connect, 5, nets[6], 0); objectCall3(modules[0], Connect, 6, nets[1], 0); objectCall3(modules[0], Connect, 7, nets[4], 0); objectCall3(nets[5], Connect, 0, modules[0], 8); modules[ 1] = hdl4seCreate_001C(module, "", "terrisctrl"); objectCall3(modules[1], Connect, 0, unit, 0); objectCall3(modules[1], Connect, 1, unit, 1); objectCall3(nets[0], Connect, 0, modules[1], 2); objectCall3(nets[2], Connect, 0, modules[1], 3); objectCall3(nets[3], Connect, 0, modules[1], 4); objectCall3(nets[6], Connect, 0, modules[1], 5); objectCall3(nets[1], Connect, 0, modules[1], 6); objectCall3(nets[4], Connect, 0, modules[1], 7); objectCall3(modules[1], Connect, 8, nets[5], 0); /*释放module接口*/ objectRelease(module); /*返回unit接口*/ return unit; } IHDL4SEUnit** hdl4seCreate_main(IHDL4SEModule** parent, const char* instanceparam, const char* name) { return hdl4seCreate_001E(parent, instanceparam, name); }