Analysis & Synthesis report for de1_riscv Mon Aug 30 18:40:06 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. Analysis & Synthesis RAM Summary 9. Analysis & Synthesis DSP Block Usage Summary 10. Analysis & Synthesis IP Cores Summary 11. State Machine - |de1_riscv|riscv_core:core|state 12. State Machine - |de1_riscv|uart_ctrl:uart_ctrl|ctrlstate 13. Registers Protected by Synthesis 14. Registers Removed During Synthesis 15. Removed Registers Triggering Further Register Optimizations 16. General Register Statistics 17. Inverted Register Statistics 18. Registers Packed Into Inferred Megafunctions 19. Multiplexer Restructuring Statistics (Restructuring Performed) 20. Source assignments for uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram 21. Source assignments for uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram 22. Source assignments for uart_ctrl:uart_ctrl|altera_uart:uart 23. Source assignments for uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer 24. Source assignments for regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated 25. Source assignments for regfile:regs2|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated 26. Source assignments for ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated 27. Source assignments for riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider 28. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider 29. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 30. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 31. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 32. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 33. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 34. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 35. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 36. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 37. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 38. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 39. Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i 40. Parameter Settings for User Entity Instance: uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component 41. Parameter Settings for User Entity Instance: uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component 42. Parameter Settings for User Entity Instance: uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer 43. Parameter Settings for User Entity Instance: regfile:regs|altsyncram:altsyncram_component 44. Parameter Settings for User Entity Instance: regfile:regs2|altsyncram:altsyncram_component 45. Parameter Settings for User Entity Instance: ram128kB:ram|altsyncram:altsyncram_component 46. Parameter Settings for User Entity Instance: riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component 47. Parameter Settings for User Entity Instance: riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component 48. Parameter Settings for User Entity Instance: riscv_core:core|mult:mul|lpm_mult:lpm_mult_component 49. Parameter Settings for User Entity Instance: riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component 50. Parameter Settings for User Entity Instance: riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component 51. Parameter Settings for User Entity Instance: riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component 52. Parameter Settings for User Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component 53. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 54. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 55. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 56. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 57. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 58. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 59. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 60. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 61. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 62. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 63. scfifo Parameter Settings by Entity Instance 64. altsyncram Parameter Settings by Entity Instance 65. lpm_mult Parameter Settings by Entity Instance 66. altshift_taps Parameter Settings by Entity Instance 67. Port Connectivity Checks: "riscv_core:core|mulsu:mul_su" 68. Port Connectivity Checks: "riscv_core:core|mult:mul" 69. Port Connectivity Checks: "ram128kB:ram" 70. Port Connectivity Checks: "uart_ctrl:uart_ctrl|altera_uart:uart" 71. Port Connectivity Checks: "uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf" 72. Port Connectivity Checks: "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf" 73. Port Connectivity Checks: "clk100M:clk100" 74. Elapsed Time Per Partition 75. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+---------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Mon Aug 30 18:40:06 2021 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; ; Logic utilization (in ALMs) ; N/A ; ; Total registers ; 1839 ; ; Total pins ; 204 ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 1,067,744 ; ; Total DSP Blocks ; 10 ; ; Total HSSI RX PCSs ; 0 ; ; Total HSSI PMA RX Deserializers ; 0 ; ; Total HSSI TX PCSs ; 0 ; ; Total HSSI TX Channels ; 0 ; ; Total PLLs ; 1 ; ; Total DLLs ; 0 ; +---------------------------------+---------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +---------------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +---------------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; 5CSEMA5F31C6 ; ; ; Top-level entity name ; de1_riscv ; de1_riscv ; ; Family name ; Cyclone V ; Cyclone IV GX ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 3 ; 3 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; ; Synthesis Seed ; 1 ; 1 ; ; Automatic Parallel Synthesis ; On ; On ; +---------------------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; < 0.1% ; ; Processors 3-4 ; 0.0% ; +----------------------------+-------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ ; ../verilog/riscv_core_v3.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v3.v ; ; ; de1_riscv_v3.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv_v3.v ; ; ; uart/uart_fifo.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/uart/uart_fifo.v ; ; ; uart/uart_ctrl.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/uart/uart_ctrl.v ; ; ; uart/altera_uart.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/uart/altera_uart.v ; ; ; regfile/regfile.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v ; ; ; alu/mult.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v ; ; ; alu/mult_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v ; ; ; alu/div.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v ; ; ; alu/div_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v ; ; ; alu/adder.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v ; ; ; alu/suber.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v ; ; ; alu/mulsu.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v ; ; ; clk/clk100M.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v ; clk100M ; ; clk/clk100M/clk100M_0002.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v ; clk100M ; ; ram/ram128kB.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram128kB.v ; ; ; altera_pll.v ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altera_pll.v ; ; ; scfifo.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/scfifo.tdf ; ; ; a_regfifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_regfifo.inc ; ; ; a_dpfifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_dpfifo.inc ; ; ; a_i2fifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_i2fifo.inc ; ; ; a_fffifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_fffifo.inc ; ; ; a_f2fifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_f2fifo.inc ; ; ; aglobal131.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ; ; db/scfifo_nrc1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/scfifo_nrc1.tdf ; ; ; db/a_dpfifo_br91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/a_dpfifo_br91.tdf ; ; ; db/altsyncram_fqe1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_fqe1.tdf ; ; ; db/cmpr_gm8.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_gm8.tdf ; ; ; db/cntr_k2b.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_k2b.tdf ; ; ; db/cntr_847.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_847.tdf ; ; ; db/cntr_s3b.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_s3b.tdf ; ; ; altera_std_synchronizer.v ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altera_std_synchronizer.v ; ; ; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf ; ; ; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; ; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; ; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc ; ; ; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; ; altrom.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altrom.inc ; ; ; altram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altram.inc ; ; ; altdpram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc ; ; ; db/altsyncram_nco1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_nco1.tdf ; ; ; db/altsyncram_vir1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_vir1.tdf ; ; ; ../test_code/test.mif ; yes ; Auto-Found Memory Initialization File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/test_code/test.mif ; ; ; db/decode_8la.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/decode_8la.tdf ; ; ; db/decode_11a.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/decode_11a.tdf ; ; ; db/mux_5hb.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mux_5hb.tdf ; ; ; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; ; addcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/addcore.inc ; ; ; look_add.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/look_add.inc ; ; ; bypassff.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/bypassff.inc ; ; ; altshift.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift.inc ; ; ; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; ; db/add_sub_tih.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_tih.tdf ; ; ; db/add_sub_ujh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_ujh.tdf ; ; ; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; ; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; ; multcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/multcore.inc ; ; ; db/mult_b8n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_b8n.v ; ; ; db/mult_81n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_81n.v ; ; ; db/mult_61n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_61n.v ; ; ; lpm_divide.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_divide.tdf ; ; ; abs_divider.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/abs_divider.inc ; ; ; sign_div_unsign.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/sign_div_unsign.inc ; ; ; db/lpm_divide_2jt.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_2jt.tdf ; ; ; db/sign_div_unsign_8ai.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_8ai.tdf ; ; ; db/alt_u_div_nlf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_nlf.tdf ; ; ; db/lpm_divide_s4t.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_s4t.tdf ; ; ; db/sign_div_unsign_2sh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_2sh.tdf ; ; ; db/alt_u_div_5eg.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_5eg.tdf ; ; ; altshift_taps.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf ; ; ; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc ; ; ; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc ; ; ; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc ; ; ; db/shift_taps_7l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_7l21.tdf ; ; ; db/altsyncram_kr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_kr91.tdf ; ; ; db/cntr_8jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_8jf.tdf ; ; ; db/cmpr_c9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_c9c.tdf ; ; ; db/shift_taps_hm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_hm21.tdf ; ; ; db/altsyncram_9u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9u91.tdf ; ; ; db/cntr_9jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_9jf.tdf ; ; ; db/shift_taps_gm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_gm21.tdf ; ; ; db/altsyncram_7u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_7u91.tdf ; ; ; db/shift_taps_bl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_bl21.tdf ; ; ; db/altsyncram_rr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_rr91.tdf ; ; ; db/cntr_0if.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_0if.tdf ; ; ; db/shift_taps_9l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_9l21.tdf ; ; ; db/altsyncram_lr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_lr91.tdf ; ; ; db/cntr_uhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_uhf.tdf ; ; ; db/shift_taps_cl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_cl21.tdf ; ; ; db/altsyncram_hr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_hr91.tdf ; ; ; db/cntr_thf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_thf.tdf ; ; ; db/cmpr_b9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_b9c.tdf ; ; ; db/shift_taps_dl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_dl21.tdf ; ; ; db/altsyncram_mr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_mr91.tdf ; ; ; db/cntr_shf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_shf.tdf ; ; ; db/shift_taps_4l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_4l21.tdf ; ; ; db/altsyncram_dr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_dr91.tdf ; ; ; db/cntr_rhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_rhf.tdf ; ; ; db/shift_taps_3l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_3l21.tdf ; ; ; db/altsyncram_9r91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9r91.tdf ; ; ; db/cntr_phf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_phf.tdf ; ; ; db/shift_taps_5l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_5l21.tdf ; ; ; db/altsyncram_br91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_br91.tdf ; ; ; db/cntr_ohf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_ohf.tdf ; ; ; db/cmpr_a9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_a9c.tdf ; ; +----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+---------------------------------------------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+---------------------------------------------------------------------------------+ ; Estimate of Logic utilization (ALMs needed) ; 2458 ; ; ; ; ; Combinational ALUT usage for logic ; 4217 ; ; -- 7 input functions ; 50 ; ; -- 6 input functions ; 464 ; ; -- 5 input functions ; 466 ; ; -- 4 input functions ; 959 ; ; -- <=3 input functions ; 2278 ; ; ; ; ; Dedicated logic registers ; 1839 ; ; ; ; ; I/O pins ; 204 ; ; Total MLAB memory bits ; 0 ; ; Total block memory bits ; 1067744 ; ; Total DSP Blocks ; 10 ; ; Total PLLs ; 1 ; ; -- PLLs ; 1 ; ; ; ; ; Maximum fan-out node ; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; ; Maximum fan-out ; 2151 ; ; Total fan-out ; 26035 ; ; Average fan-out ; 3.80 ; +---------------------------------------------+---------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +-------------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; +-------------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; |de1_riscv ; 4217 (191) ; 1839 (76) ; 1067744 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; ; |clk100M:clk100| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; ; |clk100M_0002:clk100m_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; ; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; ; |ram128kB:ram| ; 10 (0) ; 2 (0) ; 1048576 ; 0 ; 0 ; 0 ; |de1_riscv|ram128kB:ram ; work ; ; |altsyncram:altsyncram_component| ; 10 (0) ; 2 (0) ; 1048576 ; 0 ; 0 ; 0 ; |de1_riscv|ram128kB:ram|altsyncram:altsyncram_component ; work ; ; |altsyncram_vir1:auto_generated| ; 10 (0) ; 2 (2) ; 1048576 ; 0 ; 0 ; 0 ; |de1_riscv|ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated ; work ; ; |decode_11a:rden_decode| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated|decode_11a:rden_decode ; work ; ; |decode_8la:decode3| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated|decode_8la:decode3 ; work ; ; |mux_5hb:mux2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated|mux_5hb:mux2 ; work ; ; |regfile:regs2| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs2 ; work ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs2|altsyncram:altsyncram_component ; work ; ; |altsyncram_nco1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs2|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; ; |regfile:regs| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; ; |altsyncram_nco1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; ; |riscv_core:core| ; 3743 (1237) ; 1462 (206) ; 736 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; ; |adder:add| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; ; |lpm_add_sub:LPM_ADD_SUB_component| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; ; |add_sub_tih:auto_generated| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; ; |div:div| ; 1008 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; ; |lpm_divide:LPM_DIVIDE_component| ; 1008 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; ; |lpm_divide_2jt:auto_generated| ; 1008 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; ; |sign_div_unsign_8ai:divider| ; 1008 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; ; |alt_u_div_nlf:divider| ; 1008 (1008) ; 583 (583) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; ; |div_s:divs| ; 1335 (0) ; 673 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; ; |lpm_divide:LPM_DIVIDE_component| ; 1335 (0) ; 673 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; ; |lpm_divide_s4t:auto_generated| ; 1335 (0) ; 673 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; ; |sign_div_unsign_2sh:divider| ; 1335 (209) ; 673 (14) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; ; |alt_u_div_5eg:divider| ; 1113 (1010) ; 651 (595) ; 666 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; ; |altshift_taps:DFFNumerator_rtl_0| ; 14 (0) ; 8 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; ; |shift_taps_hm21:auto_generated| ; 14 (8) ; 8 (4) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; ; |altsyncram_9u91:altsyncram5| ; 0 (0) ; 0 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; ; |cntr_9jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; ; |altshift_taps:DFFNumerator_rtl_1| ; 13 (0) ; 8 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; ; |shift_taps_gm21:auto_generated| ; 13 (7) ; 8 (4) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; ; |altsyncram_7u91:altsyncram5| ; 0 (0) ; 0 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; ; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; ; |altshift_taps:DFFNumerator_rtl_2| ; 14 (0) ; 8 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; ; |shift_taps_bl21:auto_generated| ; 14 (8) ; 8 (4) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; ; |altsyncram_rr91:altsyncram5| ; 0 (0) ; 0 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; ; |cntr_0if:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; ; |altshift_taps:DFFNumerator_rtl_3| ; 8 (0) ; 6 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; ; |shift_taps_9l21:auto_generated| ; 8 (5) ; 6 (3) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; ; |altsyncram_lr91:altsyncram4| ; 0 (0) ; 0 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; ; |cntr_uhf:cntr1| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; ; |altshift_taps:DFFNumerator_rtl_4| ; 14 (0) ; 6 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; ; |shift_taps_cl21:auto_generated| ; 14 (7) ; 6 (3) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; ; |altsyncram_hr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; ; |cntr_thf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; ; |altshift_taps:DFFNumerator_rtl_5| ; 13 (0) ; 6 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; ; |shift_taps_dl21:auto_generated| ; 13 (6) ; 6 (3) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; ; |altsyncram_mr91:altsyncram5| ; 0 (0) ; 0 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; ; |cntr_shf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; ; |altshift_taps:DFFNumerator_rtl_6| ; 14 (0) ; 6 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; ; |shift_taps_4l21:auto_generated| ; 14 (7) ; 6 (3) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; ; |altsyncram_dr91:altsyncram5| ; 0 (0) ; 0 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; ; |cntr_rhf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; ; |altshift_taps:DFFNumerator_rtl_7| ; 6 (0) ; 4 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; ; |shift_taps_3l21:auto_generated| ; 6 (4) ; 4 (2) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; ; |altsyncram_9r91:altsyncram4| ; 0 (0) ; 0 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; ; |cntr_phf:cntr1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; ; |altshift_taps:DFFNumerator_rtl_8| ; 7 (0) ; 4 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; ; |shift_taps_5l21:auto_generated| ; 7 (2) ; 4 (2) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; ; |altsyncram_br91:altsyncram4| ; 0 (0) ; 0 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; ; |cntr_ohf:cntr1| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; ; |altshift_taps:DFF_Num_Sign_rtl_0| ; 13 (0) ; 8 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; ; |shift_taps_7l21:auto_generated| ; 13 (7) ; 8 (4) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; ; |altsyncram_kr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; ; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; ; |mulsu:mul_su| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; ; |lpm_mult:lpm_mult_component| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; ; |mult_61n:auto_generated| ; 38 (38) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; ; |mult:mul| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; ; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; ; |mult_b8n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; ; |mult_s:mul_s| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; ; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; ; |mult_81n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; ; |uart_ctrl:uart_ctrl| ; 273 (54) ; 299 (101) ; 16384 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl ; work ; ; |altera_uart:uart| ; 102 (0) ; 106 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|altera_uart:uart ; work ; ; |altera_uart_regs:the_altera_uart_regs| ; 21 (21) ; 34 (34) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ; ; |altera_uart_rx:the_altera_uart_rx| ; 52 (52) ; 41 (39) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ; ; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; work ; ; |altera_uart_tx:the_altera_uart_tx| ; 29 (29) ; 31 (31) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx ; work ; ; |uart_fifo:uart_recv_buf| ; 59 (0) ; 46 (0) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf ; work ; ; |scfifo:scfifo_component| ; 59 (0) ; 46 (0) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component ; work ; ; |scfifo_nrc1:auto_generated| ; 59 (6) ; 46 (1) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated ; work ; ; |a_dpfifo_br91:dpfifo| ; 53 (24) ; 45 (16) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo ; work ; ; |altsyncram_fqe1:FIFOram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram ; work ; ; |cntr_847:usedw_counter| ; 10 (10) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_847:usedw_counter ; work ; ; |cntr_k2b:rd_ptr_msb| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_k2b:rd_ptr_msb ; work ; ; |cntr_s3b:wr_ptr| ; 10 (10) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_s3b:wr_ptr ; work ; ; |uart_fifo:uart_send_buf| ; 58 (0) ; 46 (0) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf ; work ; ; |scfifo:scfifo_component| ; 58 (0) ; 46 (0) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component ; work ; ; |scfifo_nrc1:auto_generated| ; 58 (6) ; 46 (1) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated ; work ; ; |a_dpfifo_br91:dpfifo| ; 52 (23) ; 45 (16) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo ; work ; ; |altsyncram_fqe1:FIFOram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram ; work ; ; |cntr_847:usedw_counter| ; 10 (10) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_847:usedw_counter ; work ; ; |cntr_k2b:rd_ptr_msb| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_k2b:rd_ptr_msb ; work ; ; |cntr_s3b:wr_ptr| ; 10 (10) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_s3b:wr_ptr ; work ; +-------------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+-----------------------+ ; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+-----------------------+ ; ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 32768 ; 32 ; -- ; -- ; 1048576 ; ../test_code/test.mif ; ; regfile:regs2|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 32 ; 32 ; -- ; -- ; 1024 ; None ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 32 ; 32 ; -- ; -- ; 1024 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 11 ; 10 ; 11 ; 10 ; 110 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 10 ; 10 ; 10 ; 10 ; 100 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 9 ; 12 ; 9 ; 12 ; 108 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8 ; 10 ; 8 ; 10 ; 80 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 7 ; 10 ; 7 ; 10 ; 70 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 6 ; 12 ; 6 ; 12 ; 72 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 5 ; 10 ; 5 ; 10 ; 50 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4 ; 10 ; 4 ; 10 ; 40 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 3 ; 12 ; 3 ; 12 ; 36 ; None ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 10 ; 7 ; 10 ; 7 ; 70 ; None ; ; uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 8 ; 1024 ; 8 ; 8192 ; None ; ; uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 8 ; 1024 ; 8 ; 8192 ; None ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+-----------------------+ +--------------------------------------------------------------------------------------+ ; Analysis & Synthesis DSP Block Usage Summary ; +------------------------------+-------------+---------------------+-------------------+ ; Statistic ; Number Used ; Available per Block ; Maximum Available ; +------------------------------+-------------+---------------------+-------------------+ ; Independent 18x18 ; 5 ; 2.00 ; -- ; ; Sum of two 18x18 ; 2 ; 1.00 ; -- ; ; Independent 27x27 ; 3 ; 1.00 ; -- ; ; DSP Block ; 10 ; -- ; -- ; ; DSP 18-bit Element ; 9 ; 2.00 ; -- ; ; DSP 27-bit Element ; 3 ; 1.00 ; -- ; ; Signed Multiplier ; 1 ; -- ; -- ; ; Unsigned Multiplier ; 7 ; -- ; -- ; ; Mixed Sign Multiplier ; 4 ; -- ; -- ; ; Dedicated Output Adder Chain ; 1 ; -- ; -- ; +------------------------------+-------------+---------------------+-------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis IP Cores Summary ; +--------+--------------+---------+--------------+--------------+--------------------------------------------------------+---------------------------------------------------------------+ ; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; +--------+--------------+---------+--------------+--------------+--------------------------------------------------------+---------------------------------------------------------------+ ; Altera ; altera_pll ; 13.1 ; N/A ; N/A ; |de1_riscv|clk100M:clk100 ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v ; ; Altera ; LPM_ADD_SUB ; 13.1 ; N/A ; N/A ; |de1_riscv|riscv_core:core|adder:add ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v ; ; Altera ; LPM_DIVIDE ; 13.1 ; N/A ; N/A ; |de1_riscv|riscv_core:core|div:div ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v ; ; Altera ; LPM_DIVIDE ; 13.1 ; N/A ; N/A ; |de1_riscv|riscv_core:core|div_s:divs ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v ; ; Altera ; LPM_MULT ; 13.1 ; N/A ; N/A ; |de1_riscv|riscv_core:core|mult:mul ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v ; ; Altera ; LPM_MULT ; 13.1 ; N/A ; N/A ; |de1_riscv|riscv_core:core|mult_s:mul_s ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v ; ; Altera ; LPM_MULT ; 13.1 ; N/A ; N/A ; |de1_riscv|riscv_core:core|mulsu:mul_su ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v ; ; Altera ; LPM_ADD_SUB ; 13.1 ; N/A ; N/A ; |de1_riscv|riscv_core:core|suber:sub ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v ; ; Altera ; RAM: 1-PORT ; 13.1 ; N/A ; N/A ; |de1_riscv|ram128kB:ram ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram128kB.v ; ; Altera ; RAM: 1-PORT ; 13.1 ; N/A ; N/A ; |de1_riscv|regfile:regs ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v ; ; Altera ; RAM: 1-PORT ; 13.1 ; N/A ; N/A ; |de1_riscv|regfile:regs2 ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v ; ; Altera ; FIFO ; 13.1 ; N/A ; N/A ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/uart/uart_fifo.v ; ; Altera ; FIFO ; 13.1 ; N/A ; N/A ; |de1_riscv|uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/uart/uart_fifo.v ; +--------+--------------+---------+--------------+--------------+--------------------------------------------------------+---------------------------------------------------------------+ Encoding Type: One-Hot +---------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |de1_riscv|riscv_core:core|state ; +------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+ ; Name ; state.0111 ; state.0110 ; state.0101 ; state.0100 ; state.0011 ; state.0010 ; state.0001 ; state.0000 ; state.1000 ; +------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+ ; state.0000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; state.0001 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; 0 ; ; state.0010 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; 0 ; ; state.0011 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; 0 ; ; state.0100 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; ; state.0101 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; ; state.0110 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; ; state.0111 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; ; state.1000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+ Encoding Type: One-Hot +--------------------------------------------------------------------------------------------------------+ ; State Machine - |de1_riscv|uart_ctrl:uart_ctrl|ctrlstate ; +--------------------+--------------------+--------------------+--------------------+--------------------+ ; Name ; ctrlstate.00000011 ; ctrlstate.00000010 ; ctrlstate.00000001 ; ctrlstate.00000000 ; +--------------------+--------------------+--------------------+--------------------+--------------------+ ; ctrlstate.00000000 ; 0 ; 0 ; 0 ; 0 ; ; ctrlstate.00000001 ; 0 ; 0 ; 1 ; 1 ; ; ctrlstate.00000010 ; 0 ; 1 ; 0 ; 1 ; ; ctrlstate.00000011 ; 1 ; 0 ; 0 ; 1 ; +--------------------+--------------------+--------------------+--------------------+--------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Protected by Synthesis ; +------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ ; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; +------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; yes ; yes ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; yes ; yes ; +------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[31] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[11] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[63] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[10] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[95] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[9] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[127] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[8] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[159] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[7] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[191] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[6] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[223] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[5] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[255] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[4] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[287] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[3] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[319] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[2] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[351] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[383] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx2 ; Merged with uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; ; uart_ctrl:uart_ctrl|readdata[13..15,28..30] ; Merged with uart_ctrl:uart_ctrl|readdata[12] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[0] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[0] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[32] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[32] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[64] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[64] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[96] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[128] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[128] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[160] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[160] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[192] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[192] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[224] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[224] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[256] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[288] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[320] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[352] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; ; uart_ctrl:uart_ctrl|readdata[12] ; Stuck at GND due to stuck port data_in ; ; uart_ctrl:uart_ctrl|uart_addr[1] ; Stuck at GND due to stuck port data_in ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[0..7,9] ; Stuck at GND due to stuck port clock_enable ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ; Lost fanout ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ; Lost fanout ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect ; Lost fanout ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun ; Lost fanout ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_overrun ; Lost fanout ; ; riscv_core:core|state~10 ; Lost fanout ; ; riscv_core:core|state~11 ; Lost fanout ; ; riscv_core:core|state~12 ; Lost fanout ; ; uart_ctrl:uart_ctrl|ctrlstate~6 ; Lost fanout ; ; uart_ctrl:uart_ctrl|ctrlstate~7 ; Lost fanout ; ; uart_ctrl:uart_ctrl|ctrlstate~8 ; Lost fanout ; ; uart_ctrl:uart_ctrl|ctrlstate~9 ; Lost fanout ; ; uart_ctrl:uart_ctrl|ctrlstate~10 ; Lost fanout ; ; uart_ctrl:uart_ctrl|ctrlstate~11 ; Lost fanout ; ; uart_ctrl:uart_ctrl|ctrlstate~12 ; Lost fanout ; ; uart_ctrl:uart_ctrl|ctrlstate~13 ; Lost fanout ; ; Total Number of Removed Registers = 58 ; ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removed Registers Triggering Further Register Optimizations ; +----------------------------------+---------------------------+--------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; Registers Removed due to This Register ; +----------------------------------+---------------------------+--------------------------------------------------------------------------------------------+ ; uart_ctrl:uart_ctrl|uart_addr[1] ; Stuck at GND ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[9], ; ; ; due to stuck port data_in ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty, ; ; ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error, ; ; ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect, ; ; ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun, ; ; ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_overrun ; +----------------------------------+---------------------------+--------------------------------------------------------------------------------------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 1839 ; ; Number of registers using Synchronous Clear ; 210 ; ; Number of registers using Synchronous Load ; 509 ; ; Number of registers using Asynchronous Clear ; 106 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 429 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Inverted Register Statistics ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; Inverted Register ; Fan out ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; 2 ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd ; 2 ; ; uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 6 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[353] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[354] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[350] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[355] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[356] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[357] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[358] ; 1 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[3] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[282] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[283] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[284] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[286] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[285] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[360] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[280] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[281] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[361] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[249] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[250] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[251] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[252] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[254] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[253] ; 2 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[4] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[248] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[247] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[362] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[246] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[363] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[245] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[364] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[217] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[218] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[219] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[220] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[222] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[221] ; 2 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[5] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[212] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[213] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[214] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[216] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[215] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[365] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[211] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[366] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[178] ; 2 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[6] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[185] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[186] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[187] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[188] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[190] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[189] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[179] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[180] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[181] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[182] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[184] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[183] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[368] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[176] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[177] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[369] ; 1 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[7] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[143] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[144] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[146] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[145] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[153] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[154] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[155] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[156] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[158] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[157] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[147] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[148] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[149] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[150] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[152] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[151] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[370] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[371] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[141] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[372] ; 1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[108] ; 2 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[8] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[109] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[110] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[111] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[112] ; 2 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[114] ; 2 ; ; Total number of inverted registers = 392* ; ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ * Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Packed Into Inferred Megafunctions ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+ ; Register Name ; Megafunction ; Type ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+ ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign[1..10] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[32,64,96,128,160,192,224,256,288,320] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[62,63,94,95,126,127,158,159,190,191,222,223,254,255,286,287,318,319,350,351] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[32,64,96,128,160,192,224,256,288,320] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[62,63,94,95,126,127,158,159,190,191,222,223,254,255,286,287,318,319,350,351] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[1..3,33..35,65..67,97..99,129..131,161..163,193..195,225..227,257..259,289..291,321..323] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[60,61,92,93,124,125,156,157,188,189,220,221,252,253,284,285,316,317,348,349,380,381] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[1..3,33..35,65..67,97..99,129..131,161..163,193..195,225..227,257..259,289..291,321..323] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[60,61,92,93,124,125,156,157,188,189,220,221,252,253,284,285,316,317,348,349,380,381] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_0 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[4,5,36,37,68,69,100,101,132,133,164,165,196,197,228,229,260,261,292,293] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_1 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[89..91,121..123,153..155,185..187,217..219,249..251,281..283,313..315,345..347,377..379] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_1 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[4,5,36,37,68,69,100,101,132,133,164,165,196,197,228,229,260,261,292,293] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_1 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[89..91,121..123,153..155,185..187,217..219,249..251,281..283,313..315,345..347,377..379] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_1 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[6..8,38..40,70..72,102..104,134..136,166..168,198..200,230..232,262..264] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_2 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[118..120,150..152,182..184,214..216,246..248,278..280,310..312,342..344,374..376] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_2 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[6..8,38..40,70..72,102..104,134..136,166..168,198..200,230..232,262..264] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_2 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[118..120,150..152,182..184,214..216,246..248,278..280,310..312,342..344,374..376] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_2 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[9..11,41..43,73..75,105..107,137..139,169..171,201..203,233..235] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_3 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[148,149,180,181,212,213,244,245,276,277,308,309,340,341,372,373] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_3 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[9..11,41..43,73..75,105..107,137..139,169..171,201..203,233..235] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_3 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[148,149,180,181,212,213,244,245,276,277,308,309,340,341,372,373] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_3 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[12,13,44,45,76,77,108,109,140,141,172,173,204,205] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_4 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[177..179,209..211,241..243,273..275,305..307,337..339,369..371] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_4 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[12,13,44,45,76,77,108,109,140,141,172,173,204,205] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_4 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[177..179,209..211,241..243,273..275,305..307,337..339,369..371] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_4 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[14..16,46..48,78..80,110..112,142..144,174..176] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_5 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[206..208,238..240,270..272,302..304,334..336,366..368] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_5 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[14..16,46..48,78..80,110..112,142..144,174..176] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_5 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[206..208,238..240,270..272,302..304,334..336,366..368] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_5 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[17..19,49..51,81..83,113..115,145..147] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_6 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[236,237,268,269,300,301,332,333,364,365] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_6 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[17..19,49..51,81..83,113..115,145..147] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_6 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[236,237,268,269,300,301,332,333,364,365] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_6 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[20,21,52,53,84,85,116,117] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_7 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[265..267,297..299,329..331,361..363] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_7 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[20,21,52,53,84,85,116,117] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_7 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[265..267,297..299,329..331,361..363] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_7 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[22..24,54..56,86..88] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_8 ; SHIFT_TAPS ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[294..296,326..328,358..360] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_8 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[22..24,54..56,86..88] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_8 ; SHIFT_TAPS ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[294..296,326..328,358..360] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_8 ; SHIFT_TAPS ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+ ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] ; ; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; ; 3:1 ; 15 bits ; 30 LEs ; 30 LEs ; 0 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[4] ; ; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de1_riscv|riscv_core:core|ldaddr[0] ; ; 4:1 ; 11 bits ; 22 LEs ; 0 LEs ; 22 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|newdiv[9] ; ; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|newdiv[1] ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[12] ; ; 5:1 ; 16 bits ; 48 LEs ; 0 LEs ; 48 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|readdata[25] ; ; 5:1 ; 8 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|readdata[4] ; ; 6:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|recv_buf_data[6] ; ; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |de1_riscv|led1[6] ; ; 6:1 ; 24 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |de1_riscv|led1[1] ; ; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[4] ; ; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|uart_addr[2] ; ; 6:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|uart_write_data[12] ; ; 6:1 ; 11 bits ; 44 LEs ; 0 LEs ; 44 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|lastdiv[9] ; ; 6:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|uart_write_data[7] ; ; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |de1_riscv|uart_ctrl:uart_ctrl|lastdiv[4] ; ; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de1_riscv|led5[6] ; ; 7:1 ; 12 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |de1_riscv|led4[1] ; ; 14:1 ; 6 bits ; 54 LEs ; 6 LEs ; 48 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[5] ; ; 7:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |de1_riscv|riscv_core:core|divclk[4] ; ; 15:1 ; 8 bits ; 80 LEs ; 0 LEs ; 80 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[18] ; ; 16:1 ; 4 bits ; 40 LEs ; 8 LEs ; 32 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[4] ; ; 10:1 ; 11 bits ; 66 LEs ; 0 LEs ; 66 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[24] ; ; 21:1 ; 2 bits ; 28 LEs ; 4 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[0] ; ; 21:1 ; 26 bits ; 364 LEs ; 52 LEs ; 312 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[13] ; ; 21:1 ; 4 bits ; 56 LEs ; 8 LEs ; 48 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[6] ; ; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[19] ; ; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[25] ; ; 39:1 ; 5 bits ; 130 LEs ; 25 LEs ; 105 LEs ; Yes ; |de1_riscv|riscv_core:core|dstreg[1] ; ; 58:1 ; 12 bits ; 456 LEs ; 264 LEs ; 192 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[16] ; ; 61:1 ; 7 bits ; 280 LEs ; 217 LEs ; 63 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[13] ; ; 63:1 ; 3 bits ; 126 LEs ; 93 LEs ; 33 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[4] ; ; 62:1 ; 3 bits ; 123 LEs ; 96 LEs ; 27 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[28] ; ; 67:1 ; 2 bits ; 88 LEs ; 68 LEs ; 20 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[3] ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft1 ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ; ; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|bReadAddr[21] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|Selector163 ; ; 6:1 ; 3 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[15] ; ; 6:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[12] ; ; 6:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[14] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|Selector185 ; ; 7:1 ; 11 bits ; 44 LEs ; 44 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[20] ; ; 7:1 ; 10 bits ; 40 LEs ; 40 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[8] ; ; 7:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[25] ; ; 9:1 ; 3 bits ; 18 LEs ; 15 LEs ; 3 LEs ; No ; |de1_riscv|uart_ctrl:uart_ctrl|ctrlstate ; +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------+ ; Source assignments for uart_ctrl:uart_ctrl|altera_uart:uart ; +-----------------------------+-------+------+----------------+ ; Assignment ; Value ; From ; To ; +-----------------------------+-------+------+----------------+ ; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +-----------------------------+-------+------+----------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; +-----------------------------+------------------------+------+-------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +-----------------------------+------------------------+------+-------------------------------------------------------------------------------------+ ; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; ; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; ; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; ; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; ; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; ; PRESERVE_REGISTER ; ON ; - ; din_s1 ; +-----------------------------+------------------------+------+-------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------+ ; Source assignments for regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Source assignments for regfile:regs2|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; +---------------------------------+--------------------+------+---------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+---------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+---------------------------------------+ +----------------------------------------------------------------------------------------------------+ ; Source assignments for ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; +----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------+ ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[0] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[1] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[2] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[3] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[4] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[5] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[6] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[7] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[8] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[9] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[10] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[11] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[12] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[13] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[14] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[15] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[16] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[17] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[18] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[19] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[20] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[21] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[22] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[23] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[24] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[25] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[26] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[27] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[28] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[29] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[30] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[31] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[32] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[33] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[34] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[35] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[36] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[37] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[38] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[39] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[40] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[41] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[42] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[43] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[44] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[45] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[46] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[47] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[48] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[49] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[50] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[51] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[52] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[53] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[54] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[55] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[56] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[57] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[58] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[59] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[60] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[61] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[62] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[63] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[64] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[65] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[66] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[67] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[68] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[69] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[70] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[71] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[72] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[73] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[74] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[75] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[76] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[77] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[78] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[79] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[80] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[81] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[82] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[83] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[84] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[85] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[86] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[87] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[88] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[89] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[90] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[91] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[92] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[93] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[94] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[95] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[96] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[97] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[98] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[99] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[100] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[101] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[102] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[103] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[104] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[105] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[106] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[107] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[108] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[109] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[110] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[111] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[112] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[113] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[114] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[115] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[116] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[117] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[118] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[119] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[120] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[121] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[122] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[123] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[124] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[125] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[126] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[127] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[128] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[129] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[130] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[131] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[132] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[133] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[134] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[135] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[136] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[137] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[138] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[139] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[140] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[141] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[142] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[143] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[144] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[145] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[146] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[147] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[148] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[149] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[150] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[151] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[152] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[153] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[154] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[155] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[156] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[157] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[158] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[159] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[160] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[161] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[162] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[163] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[164] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[165] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[166] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[167] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[168] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[169] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[170] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[171] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[172] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[173] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[174] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[175] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[176] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[177] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[178] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[179] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[180] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[181] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[182] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[183] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[184] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[185] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[186] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[187] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[188] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[189] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[190] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[191] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[192] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[193] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[194] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[195] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[196] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[197] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[198] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[199] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[200] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[201] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[202] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[203] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[204] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[205] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[206] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[207] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[208] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[209] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[210] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[211] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[212] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[213] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[214] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[215] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[216] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[217] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[218] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[219] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[220] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[221] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[222] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[223] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[224] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[225] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[226] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[227] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[228] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[229] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[230] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[231] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[232] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[233] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[234] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[235] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[236] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[237] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[238] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[239] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[240] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[241] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[242] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[243] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[244] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[245] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[246] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[247] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[248] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[249] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[250] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[251] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[252] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[253] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[254] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[255] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[256] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[257] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[258] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[259] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[260] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[261] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[262] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[263] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[264] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[265] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[266] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[267] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[268] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[269] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[270] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[271] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[272] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[273] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[274] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[275] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[276] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[277] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[278] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[279] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[280] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[281] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[282] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[283] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[284] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[285] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[286] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[287] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[288] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[289] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[290] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[291] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[292] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[293] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[294] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[295] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[296] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[297] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[298] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[299] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[300] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[301] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[302] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[303] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[304] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[305] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[306] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[307] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[308] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[309] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[310] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[311] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[312] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[313] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[314] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[315] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[316] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[317] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[318] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[319] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[320] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[321] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[322] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[323] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[324] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[325] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[326] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[327] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[328] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[329] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[330] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[331] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[332] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[333] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[334] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[335] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[336] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[337] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[338] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[339] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[340] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[341] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[342] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[343] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[344] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[345] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[346] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[347] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[348] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[349] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[350] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[351] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[352] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[353] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[354] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[355] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[356] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[357] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[358] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[359] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[360] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[361] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[362] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[363] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[364] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[365] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[366] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[367] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[368] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[369] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[370] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[371] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[372] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[373] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[374] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[375] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[376] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[377] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[378] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[379] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[380] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[381] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[382] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[383] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator ; +----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; +----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[0] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[1] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[2] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[3] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[4] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[5] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[6] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[7] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[8] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[9] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[10] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[11] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[12] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[13] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[14] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[15] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[16] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[17] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[18] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[19] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[20] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[21] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[22] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[23] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[24] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[25] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[26] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[27] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[28] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[29] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[30] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[31] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[32] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[33] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[34] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[35] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[36] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[37] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[38] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[39] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[40] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[41] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[42] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[43] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[44] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[45] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[46] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[47] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[48] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[49] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[50] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[51] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[52] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[53] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[54] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[55] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[56] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[57] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[58] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[59] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[60] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[61] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[62] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[63] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[64] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[65] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[66] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[67] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[68] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[69] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[70] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[71] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[72] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[73] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[74] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[75] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[76] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[77] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[78] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[79] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[80] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[81] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[82] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[83] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[84] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[85] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[86] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[87] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[88] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[89] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[90] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[91] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[92] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[93] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[94] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[95] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[96] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[97] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[98] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[99] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[100] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[101] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[102] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[103] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[104] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[105] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[106] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[107] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[108] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[109] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[110] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[111] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[112] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[113] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[114] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[115] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[116] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[117] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[118] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[119] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[120] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[121] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[122] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[123] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[124] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[125] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[126] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[127] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[128] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[129] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[130] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[131] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[132] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[133] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[134] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[135] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[136] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[137] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[138] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[139] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[140] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[141] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[142] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[143] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[144] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[145] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[146] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[147] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[148] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[149] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[150] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[151] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[152] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[153] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[154] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[155] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[156] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[157] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[158] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[159] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[160] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[161] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[162] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[163] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[164] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[165] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[166] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[167] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[168] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[169] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[170] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[171] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[172] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[173] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[174] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[175] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[176] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[177] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[178] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[179] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[180] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[181] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[182] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[183] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[184] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[185] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[186] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[187] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[188] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[189] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[190] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[191] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[192] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[193] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[194] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[195] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[196] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[197] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[198] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[199] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[200] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[201] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[202] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[203] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[204] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[205] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[206] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[207] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[208] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[209] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[210] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[211] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[212] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[213] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[214] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[215] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[216] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[217] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[218] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[219] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[220] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[221] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[222] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[223] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[224] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[225] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[226] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[227] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[228] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[229] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[230] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[231] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[232] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[233] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[234] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[235] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[236] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[237] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[238] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[239] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[240] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[241] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[242] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[243] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[244] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[245] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[246] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[247] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[248] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[249] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[250] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[251] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[252] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[253] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[254] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[255] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[256] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[257] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[258] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[259] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[260] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[261] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[262] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[263] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[264] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[265] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[266] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[267] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[268] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[269] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[270] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[271] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[272] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[273] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[274] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[275] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[276] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[277] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[278] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[279] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[280] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[281] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[282] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[283] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[284] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[285] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[286] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[287] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[288] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[289] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[290] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[291] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[292] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[293] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[294] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[295] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[296] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[297] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[298] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[299] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[300] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[301] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[302] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[303] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[304] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[305] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[306] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[307] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[308] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[309] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[310] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[311] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[312] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[313] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[314] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[315] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[316] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[317] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[318] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[319] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[320] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[321] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[322] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[323] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[324] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[325] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[326] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[327] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[328] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[329] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[330] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[331] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[332] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[333] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[334] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[335] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[336] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[337] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[338] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[339] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[340] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[341] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[342] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[343] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[344] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[345] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[346] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[347] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[348] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[349] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[350] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[351] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFDenominator[352] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[353] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[354] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[355] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[356] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[357] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[358] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[359] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[360] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[361] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[362] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[363] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[364] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[365] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[366] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[367] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[368] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[369] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[370] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[371] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[372] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[373] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[374] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[375] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[376] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[377] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[378] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[379] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[380] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[381] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[382] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFDenominator[383] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[0] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[1] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[2] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[3] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[4] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[5] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[6] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[7] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[8] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[9] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[10] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[11] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[12] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[13] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[14] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[15] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[16] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[17] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[18] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[19] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[20] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[21] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[22] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[23] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[24] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[25] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[26] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[27] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[28] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[29] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[30] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[31] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[32] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[33] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[34] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[35] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[36] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[37] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[38] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[39] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[40] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[41] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[42] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[43] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[44] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[45] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[46] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[47] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[48] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[49] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[50] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[51] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[52] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[53] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[54] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[55] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[56] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[57] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[58] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[59] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[60] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[61] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[62] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[63] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[64] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[65] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[66] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[67] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[68] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[69] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[70] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[71] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[72] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[73] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[74] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[75] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[76] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[77] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[78] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[79] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[80] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[81] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[82] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[83] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[84] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[85] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[86] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[87] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[88] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[89] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[90] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[91] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[92] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[93] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[94] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[95] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[96] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[97] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[98] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[99] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[100] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[101] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[102] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[103] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[104] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[105] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[106] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[107] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[108] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[109] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[110] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[111] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[112] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[113] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[114] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[115] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[116] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[117] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[118] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[119] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[120] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[121] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[122] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[123] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[124] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[125] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[126] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[127] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[128] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[129] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[130] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[131] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[132] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[133] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[134] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[135] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[136] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[137] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[138] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[139] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[140] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[141] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[142] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[143] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[144] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[145] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[146] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[147] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[148] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[149] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[150] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[151] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[152] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[153] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[154] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[155] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[156] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[157] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[158] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[159] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[160] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[161] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[162] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[163] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[164] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[165] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[166] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[167] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[168] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[169] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[170] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[171] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[172] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[173] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[174] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[175] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[176] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[177] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[178] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[179] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[180] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[181] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[182] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[183] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[184] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[185] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[186] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[187] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[188] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[189] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[190] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[191] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[192] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[193] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[194] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[195] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[196] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[197] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[198] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[199] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[200] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[201] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[202] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[203] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[204] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[205] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[206] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[207] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[208] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[209] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[210] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[211] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[212] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[213] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[214] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[215] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[216] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[217] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[218] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[219] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[220] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[221] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[222] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[223] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[224] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[225] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[226] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[227] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[228] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[229] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[230] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[231] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[232] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[233] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[234] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[235] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[236] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[237] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[238] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[239] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[240] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[241] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[242] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[243] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[244] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[245] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[246] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[247] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[248] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[249] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[250] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[251] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[252] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[253] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[254] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[255] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[256] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[257] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[258] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[259] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[260] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[261] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[262] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[263] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[264] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[265] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[266] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[267] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[268] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[269] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[270] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[271] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[272] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[273] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[274] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[275] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[276] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[277] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[278] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[279] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[280] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[281] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[282] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[283] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[284] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[285] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[286] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[287] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[288] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[289] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[290] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[291] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[292] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[293] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[294] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[295] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[296] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[297] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[298] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[299] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[300] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[301] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[302] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[303] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[304] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[305] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[306] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[307] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[308] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[309] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[310] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[311] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[312] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[313] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[314] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[315] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[316] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[317] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[318] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[319] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[320] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[321] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[322] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[323] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[324] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[325] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[326] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[327] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[328] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[329] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[330] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[331] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[332] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[333] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[334] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[335] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[336] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[337] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[338] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[339] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[340] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[341] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[342] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[343] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[344] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[345] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[346] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[347] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[348] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[349] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[350] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[351] ; ; POWER_UP_LEVEL ; HIGH ; - ; DFFQuotient[352] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[353] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[354] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[355] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[356] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[357] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[358] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[359] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[360] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[361] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[362] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[363] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[364] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[365] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[366] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[367] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[368] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[369] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[370] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[371] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[372] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[373] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[374] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[375] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[376] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[377] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[378] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[379] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[380] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[381] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[382] ; ; POWER_UP_LEVEL ; LOW ; - ; DFFQuotient[383] ; +----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; +---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; +--------------------------------------+---------------+--------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +--------------------------------------+---------------+--------------------------------------------------------+ ; reference_clock_frequency ; 50.0 MHz ; String ; ; fractional_vco_multiplier ; false ; String ; ; pll_type ; General ; String ; ; pll_subtype ; General ; String ; ; number_of_clocks ; 2 ; Signed Integer ; ; operation_mode ; direct ; String ; ; deserialization_factor ; 4 ; Signed Integer ; ; data_rate ; 0 ; Signed Integer ; ; sim_additional_refclk_cycles_to_lock ; 0 ; Signed Integer ; ; output_clock_frequency0 ; 50.000000 MHz ; String ; ; phase_shift0 ; 0 ps ; String ; ; duty_cycle0 ; 50 ; Signed Integer ; ; output_clock_frequency1 ; 75.000000 MHz ; String ; ; phase_shift1 ; 0 ps ; String ; ; duty_cycle1 ; 50 ; Signed Integer ; ; output_clock_frequency2 ; 0 MHz ; String ; ; phase_shift2 ; 0 ps ; String ; ; duty_cycle2 ; 50 ; Signed Integer ; ; output_clock_frequency3 ; 0 MHz ; String ; ; phase_shift3 ; 0 ps ; String ; ; duty_cycle3 ; 50 ; Signed Integer ; ; output_clock_frequency4 ; 0 MHz ; String ; ; phase_shift4 ; 0 ps ; String ; ; duty_cycle4 ; 50 ; Signed Integer ; ; output_clock_frequency5 ; 0 MHz ; String ; ; phase_shift5 ; 0 ps ; String ; ; duty_cycle5 ; 50 ; Signed Integer ; ; output_clock_frequency6 ; 0 MHz ; String ; ; phase_shift6 ; 0 ps ; String ; ; duty_cycle6 ; 50 ; Signed Integer ; ; output_clock_frequency7 ; 0 MHz ; String ; ; phase_shift7 ; 0 ps ; String ; ; duty_cycle7 ; 50 ; Signed Integer ; ; output_clock_frequency8 ; 0 MHz ; String ; ; phase_shift8 ; 0 ps ; String ; ; duty_cycle8 ; 50 ; Signed Integer ; ; output_clock_frequency9 ; 0 MHz ; String ; ; phase_shift9 ; 0 ps ; String ; ; duty_cycle9 ; 50 ; Signed Integer ; ; output_clock_frequency10 ; 0 MHz ; String ; ; phase_shift10 ; 0 ps ; String ; ; duty_cycle10 ; 50 ; Signed Integer ; ; output_clock_frequency11 ; 0 MHz ; String ; ; phase_shift11 ; 0 ps ; String ; ; duty_cycle11 ; 50 ; Signed Integer ; ; output_clock_frequency12 ; 0 MHz ; String ; ; phase_shift12 ; 0 ps ; String ; ; duty_cycle12 ; 50 ; Signed Integer ; ; output_clock_frequency13 ; 0 MHz ; String ; ; phase_shift13 ; 0 ps ; String ; ; duty_cycle13 ; 50 ; Signed Integer ; ; output_clock_frequency14 ; 0 MHz ; String ; ; phase_shift14 ; 0 ps ; String ; ; duty_cycle14 ; 50 ; Signed Integer ; ; output_clock_frequency15 ; 0 MHz ; String ; ; phase_shift15 ; 0 ps ; String ; ; duty_cycle15 ; 50 ; Signed Integer ; ; output_clock_frequency16 ; 0 MHz ; String ; ; phase_shift16 ; 0 ps ; String ; ; duty_cycle16 ; 50 ; Signed Integer ; ; output_clock_frequency17 ; 0 MHz ; String ; ; phase_shift17 ; 0 ps ; String ; ; duty_cycle17 ; 50 ; Signed Integer ; ; m_cnt_hi_div ; 1 ; Signed Integer ; ; m_cnt_lo_div ; 1 ; Signed Integer ; ; m_cnt_bypass_en ; false ; String ; ; m_cnt_odd_div_duty_en ; false ; String ; ; n_cnt_hi_div ; 1 ; Signed Integer ; ; n_cnt_lo_div ; 1 ; Signed Integer ; ; n_cnt_bypass_en ; false ; String ; ; n_cnt_odd_div_duty_en ; false ; String ; ; c_cnt_hi_div0 ; 1 ; Signed Integer ; ; c_cnt_lo_div0 ; 1 ; Signed Integer ; ; c_cnt_bypass_en0 ; false ; String ; ; c_cnt_in_src0 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en0 ; false ; String ; ; c_cnt_prst0 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst0 ; 0 ; Signed Integer ; ; c_cnt_hi_div1 ; 1 ; Signed Integer ; ; c_cnt_lo_div1 ; 1 ; Signed Integer ; ; c_cnt_bypass_en1 ; false ; String ; ; c_cnt_in_src1 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en1 ; false ; String ; ; c_cnt_prst1 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst1 ; 0 ; Signed Integer ; ; c_cnt_hi_div2 ; 1 ; Signed Integer ; ; c_cnt_lo_div2 ; 1 ; Signed Integer ; ; c_cnt_bypass_en2 ; false ; String ; ; c_cnt_in_src2 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en2 ; false ; String ; ; c_cnt_prst2 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst2 ; 0 ; Signed Integer ; ; c_cnt_hi_div3 ; 1 ; Signed Integer ; ; c_cnt_lo_div3 ; 1 ; Signed Integer ; ; c_cnt_bypass_en3 ; false ; String ; ; c_cnt_in_src3 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en3 ; false ; String ; ; c_cnt_prst3 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst3 ; 0 ; Signed Integer ; ; c_cnt_hi_div4 ; 1 ; Signed Integer ; ; c_cnt_lo_div4 ; 1 ; Signed Integer ; ; c_cnt_bypass_en4 ; false ; String ; ; c_cnt_in_src4 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en4 ; false ; String ; ; c_cnt_prst4 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst4 ; 0 ; Signed Integer ; ; c_cnt_hi_div5 ; 1 ; Signed Integer ; ; c_cnt_lo_div5 ; 1 ; Signed Integer ; ; c_cnt_bypass_en5 ; false ; String ; ; c_cnt_in_src5 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en5 ; false ; String ; ; c_cnt_prst5 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst5 ; 0 ; Signed Integer ; ; c_cnt_hi_div6 ; 1 ; Signed Integer ; ; c_cnt_lo_div6 ; 1 ; Signed Integer ; ; c_cnt_bypass_en6 ; false ; String ; ; c_cnt_in_src6 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en6 ; false ; String ; ; c_cnt_prst6 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst6 ; 0 ; Signed Integer ; ; c_cnt_hi_div7 ; 1 ; Signed Integer ; ; c_cnt_lo_div7 ; 1 ; Signed Integer ; ; c_cnt_bypass_en7 ; false ; String ; ; c_cnt_in_src7 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en7 ; false ; String ; ; c_cnt_prst7 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst7 ; 0 ; Signed Integer ; ; c_cnt_hi_div8 ; 1 ; Signed Integer ; ; c_cnt_lo_div8 ; 1 ; Signed Integer ; ; c_cnt_bypass_en8 ; false ; String ; ; c_cnt_in_src8 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en8 ; false ; String ; ; c_cnt_prst8 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst8 ; 0 ; Signed Integer ; ; c_cnt_hi_div9 ; 1 ; Signed Integer ; ; c_cnt_lo_div9 ; 1 ; Signed Integer ; ; c_cnt_bypass_en9 ; false ; String ; ; c_cnt_in_src9 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en9 ; false ; String ; ; c_cnt_prst9 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst9 ; 0 ; Signed Integer ; ; c_cnt_hi_div10 ; 1 ; Signed Integer ; ; c_cnt_lo_div10 ; 1 ; Signed Integer ; ; c_cnt_bypass_en10 ; false ; String ; ; c_cnt_in_src10 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en10 ; false ; String ; ; c_cnt_prst10 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst10 ; 0 ; Signed Integer ; ; c_cnt_hi_div11 ; 1 ; Signed Integer ; ; c_cnt_lo_div11 ; 1 ; Signed Integer ; ; c_cnt_bypass_en11 ; false ; String ; ; c_cnt_in_src11 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en11 ; false ; String ; ; c_cnt_prst11 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst11 ; 0 ; Signed Integer ; ; c_cnt_hi_div12 ; 1 ; Signed Integer ; ; c_cnt_lo_div12 ; 1 ; Signed Integer ; ; c_cnt_bypass_en12 ; false ; String ; ; c_cnt_in_src12 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en12 ; false ; String ; ; c_cnt_prst12 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst12 ; 0 ; Signed Integer ; ; c_cnt_hi_div13 ; 1 ; Signed Integer ; ; c_cnt_lo_div13 ; 1 ; Signed Integer ; ; c_cnt_bypass_en13 ; false ; String ; ; c_cnt_in_src13 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en13 ; false ; String ; ; c_cnt_prst13 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst13 ; 0 ; Signed Integer ; ; c_cnt_hi_div14 ; 1 ; Signed Integer ; ; c_cnt_lo_div14 ; 1 ; Signed Integer ; ; c_cnt_bypass_en14 ; false ; String ; ; c_cnt_in_src14 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en14 ; false ; String ; ; c_cnt_prst14 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst14 ; 0 ; Signed Integer ; ; c_cnt_hi_div15 ; 1 ; Signed Integer ; ; c_cnt_lo_div15 ; 1 ; Signed Integer ; ; c_cnt_bypass_en15 ; false ; String ; ; c_cnt_in_src15 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en15 ; false ; String ; ; c_cnt_prst15 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst15 ; 0 ; Signed Integer ; ; c_cnt_hi_div16 ; 1 ; Signed Integer ; ; c_cnt_lo_div16 ; 1 ; Signed Integer ; ; c_cnt_bypass_en16 ; false ; String ; ; c_cnt_in_src16 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en16 ; false ; String ; ; c_cnt_prst16 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst16 ; 0 ; Signed Integer ; ; c_cnt_hi_div17 ; 1 ; Signed Integer ; ; c_cnt_lo_div17 ; 1 ; Signed Integer ; ; c_cnt_bypass_en17 ; false ; String ; ; c_cnt_in_src17 ; ph_mux_clk ; String ; ; c_cnt_odd_div_duty_en17 ; false ; String ; ; c_cnt_prst17 ; 1 ; Signed Integer ; ; c_cnt_ph_mux_prst17 ; 0 ; Signed Integer ; ; pll_vco_div ; 1 ; Signed Integer ; ; pll_output_clk_frequency ; 0 MHz ; String ; ; pll_cp_current ; 0 ; Signed Integer ; ; pll_bwctrl ; 0 ; Signed Integer ; ; pll_fractional_division ; 1 ; Signed Integer ; ; pll_fractional_cout ; 24 ; Signed Integer ; ; pll_dsm_out_sel ; 1st_order ; String ; ; mimic_fbclk_type ; gclk ; String ; ; pll_fbclk_mux_1 ; glb ; String ; ; pll_fbclk_mux_2 ; fb_1 ; String ; ; pll_m_cnt_in_src ; ph_mux_clk ; String ; ; pll_vcoph_div ; 1 ; Signed Integer ; ; refclk1_frequency ; 0 MHz ; String ; ; pll_clkin_0_src ; clk_0 ; String ; ; pll_clkin_1_src ; clk_0 ; String ; ; pll_clk_loss_sw_en ; false ; String ; ; pll_auto_clk_sw_en ; false ; String ; ; pll_manu_clk_sw_en ; false ; String ; ; pll_clk_sw_dly ; 0 ; Signed Integer ; +--------------------------------------+---------------+--------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component ; +-------------------------+-------------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------+-------------+--------------------------------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; lpm_width ; 8 ; Signed Integer ; ; LPM_NUMWORDS ; 1024 ; Signed Integer ; ; LPM_WIDTHU ; 10 ; Signed Integer ; ; LPM_SHOWAHEAD ; ON ; Untyped ; ; UNDERFLOW_CHECKING ; ON ; Untyped ; ; OVERFLOW_CHECKING ; ON ; Untyped ; ; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; ; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; ; ALMOST_FULL_VALUE ; 240 ; Signed Integer ; ; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; ; USE_EAB ; ON ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; CBXI_PARAMETER ; scfifo_nrc1 ; Untyped ; +-------------------------+-------------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component ; +-------------------------+-------------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------+-------------+--------------------------------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; lpm_width ; 8 ; Signed Integer ; ; LPM_NUMWORDS ; 1024 ; Signed Integer ; ; LPM_WIDTHU ; 10 ; Signed Integer ; ; LPM_SHOWAHEAD ; ON ; Untyped ; ; UNDERFLOW_CHECKING ; ON ; Untyped ; ; OVERFLOW_CHECKING ; ON ; Untyped ; ; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; ; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; ; ALMOST_FULL_VALUE ; 240 ; Signed Integer ; ; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; ; USE_EAB ; ON ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; CBXI_PARAMETER ; scfifo_nrc1 ; Untyped ; +-------------------------+-------------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; +----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ ; depth ; 2 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: regfile:regs|altsyncram:altsyncram_component ; +------------------------------------+----------------------+-------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; SINGLE_PORT ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 5 ; Signed Integer ; ; NUMWORDS_A ; 32 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 1 ; Untyped ; ; WIDTHAD_B ; 1 ; Untyped ; ; NUMWORDS_B ; 1 ; Untyped ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Signed Integer ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; ; WIDTH_ECCSTATUS ; 3 ; Untyped ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; CBXI_PARAMETER ; altsyncram_nco1 ; Untyped ; +------------------------------------+----------------------+-------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: regfile:regs2|altsyncram:altsyncram_component ; +------------------------------------+----------------------+--------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+--------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; SINGLE_PORT ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 5 ; Signed Integer ; ; NUMWORDS_A ; 32 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 1 ; Untyped ; ; WIDTHAD_B ; 1 ; Untyped ; ; NUMWORDS_B ; 1 ; Untyped ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Signed Integer ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; ; WIDTH_ECCSTATUS ; 3 ; Untyped ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; CBXI_PARAMETER ; altsyncram_nco1 ; Untyped ; +------------------------------------+----------------------+--------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: ram128kB:ram|altsyncram:altsyncram_component ; +------------------------------------+-----------------------+------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+-----------------------+------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; SINGLE_PORT ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 15 ; Signed Integer ; ; NUMWORDS_A ; 32768 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 1 ; Untyped ; ; WIDTHAD_B ; 1 ; Untyped ; ; NUMWORDS_B ; 1 ; Untyped ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Signed Integer ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; ../test_code/test.mif ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; ; WIDTH_ECCSTATUS ; 3 ; Untyped ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; CBXI_PARAMETER ; altsyncram_vir1 ; Untyped ; +------------------------------------+-----------------------+------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; +------------------------+-------------+-------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+-------------+-------------------------------------------------------------------+ ; LPM_WIDTH ; 32 ; Signed Integer ; ; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; ; LPM_DIRECTION ; ADD ; Untyped ; ; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; REGISTERED_AT_END ; 0 ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; USE_CS_BUFFERS ; 1 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; USE_WYS ; OFF ; Untyped ; ; STYLE ; FAST ; Untyped ; ; CBXI_PARAMETER ; add_sub_tih ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +------------------------+-------------+-------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component ; +------------------------+-------------+-------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+-------------+-------------------------------------------------------------------+ ; LPM_WIDTH ; 32 ; Signed Integer ; ; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; ; LPM_DIRECTION ; SUB ; Untyped ; ; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; REGISTERED_AT_END ; 0 ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; USE_CS_BUFFERS ; 1 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; USE_WYS ; OFF ; Untyped ; ; STYLE ; FAST ; Untyped ; ; CBXI_PARAMETER ; add_sub_ujh ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +------------------------+-------------+-------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; +------------------------------------------------+-----------+--------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+-----------+--------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 32 ; Signed Integer ; ; LPM_WIDTHB ; 32 ; Signed Integer ; ; LPM_WIDTHP ; 64 ; Signed Integer ; ; LPM_WIDTHR ; 0 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_b8n ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+-----------+--------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; +------------------------------------------------+-----------+------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+-----------+------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 32 ; Signed Integer ; ; LPM_WIDTHB ; 32 ; Signed Integer ; ; LPM_WIDTHP ; 64 ; Signed Integer ; ; LPM_WIDTHR ; 0 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_81n ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+-----------+------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; +------------------------------------------------+-----------+------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+-----------+------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 32 ; Signed Integer ; ; LPM_WIDTHB ; 40 ; Signed Integer ; ; LPM_WIDTHP ; 72 ; Signed Integer ; ; LPM_WIDTHR ; 0 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone V ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_61n ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+-----------+------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; +------------------------+----------------+------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+----------------+------------------------------------------------------------+ ; LPM_WIDTHN ; 32 ; Signed Integer ; ; LPM_WIDTHD ; 32 ; Signed Integer ; ; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ; ; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ; ; LPM_PIPELINE ; 12 ; Signed Integer ; ; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; CBXI_PARAMETER ; lpm_divide_2jt ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +------------------------+----------------+------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; +------------------------+----------------+---------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+----------------+---------------------------------------------------------------+ ; LPM_WIDTHN ; 32 ; Signed Integer ; ; LPM_WIDTHD ; 32 ; Signed Integer ; ; LPM_NREPRESENTATION ; SIGNED ; Untyped ; ; LPM_DREPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 12 ; Signed Integer ; ; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; CBXI_PARAMETER ; lpm_divide_s4t ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +------------------------+----------------+---------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; +----------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 10 ; Untyped ; ; WIDTH ; 7 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_7l21 ; Untyped ; +----------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 11 ; Untyped ; ; WIDTH ; 10 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_hm21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 10 ; Untyped ; ; WIDTH ; 10 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_gm21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 9 ; Untyped ; ; WIDTH ; 12 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_bl21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 8 ; Untyped ; ; WIDTH ; 10 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_9l21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 7 ; Untyped ; ; WIDTH ; 10 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_cl21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 6 ; Untyped ; ; WIDTH ; 12 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_dl21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 5 ; Untyped ; ; WIDTH ; 10 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_4l21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 4 ; Untyped ; ; WIDTH ; 10 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_3l21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; WIDTH_BYTEENA ; 1 ; Untyped ; ; NUMBER_OF_TAPS ; 1 ; Untyped ; ; TAP_DISTANCE ; 3 ; Untyped ; ; WIDTH ; 12 ; Untyped ; ; POWER_UP_STATE ; DONT_CARE ; Untyped ; ; CBXI_PARAMETER ; shift_taps_5l21 ; Untyped ; +----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------+ ; scfifo Parameter Settings by Entity Instance ; +----------------------------+---------------------------------------------------------------------+ ; Name ; Value ; +----------------------------+---------------------------------------------------------------------+ ; Number of entity instances ; 2 ; ; Entity Instance ; uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component ; ; -- FIFO Type ; Single Clock ; ; -- lpm_width ; 8 ; ; -- LPM_NUMWORDS ; 1024 ; ; -- LPM_SHOWAHEAD ; ON ; ; -- USE_EAB ; ON ; ; Entity Instance ; uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf|scfifo:scfifo_component ; ; -- FIFO Type ; Single Clock ; ; -- lpm_width ; 8 ; ; -- LPM_NUMWORDS ; 1024 ; ; -- LPM_SHOWAHEAD ; ON ; ; -- USE_EAB ; ON ; +----------------------------+---------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------+ ; altsyncram Parameter Settings by Entity Instance ; +-------------------------------------------+-----------------------------------------------+ ; Name ; Value ; +-------------------------------------------+-----------------------------------------------+ ; Number of entity instances ; 3 ; ; Entity Instance ; regfile:regs|altsyncram:altsyncram_component ; ; -- OPERATION_MODE ; SINGLE_PORT ; ; -- WIDTH_A ; 32 ; ; -- NUMWORDS_A ; 32 ; ; -- OUTDATA_REG_A ; UNREGISTERED ; ; -- WIDTH_B ; 1 ; ; -- NUMWORDS_B ; 1 ; ; -- ADDRESS_REG_B ; CLOCK1 ; ; -- OUTDATA_REG_B ; UNREGISTERED ; ; -- RAM_BLOCK_TYPE ; AUTO ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ; Entity Instance ; regfile:regs2|altsyncram:altsyncram_component ; ; -- OPERATION_MODE ; SINGLE_PORT ; ; -- WIDTH_A ; 32 ; ; -- NUMWORDS_A ; 32 ; ; -- OUTDATA_REG_A ; UNREGISTERED ; ; -- WIDTH_B ; 1 ; ; -- NUMWORDS_B ; 1 ; ; -- ADDRESS_REG_B ; CLOCK1 ; ; -- OUTDATA_REG_B ; UNREGISTERED ; ; -- RAM_BLOCK_TYPE ; AUTO ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ; Entity Instance ; ram128kB:ram|altsyncram:altsyncram_component ; ; -- OPERATION_MODE ; SINGLE_PORT ; ; -- WIDTH_A ; 32 ; ; -- NUMWORDS_A ; 32768 ; ; -- OUTDATA_REG_A ; UNREGISTERED ; ; -- WIDTH_B ; 1 ; ; -- NUMWORDS_B ; 1 ; ; -- ADDRESS_REG_B ; CLOCK1 ; ; -- OUTDATA_REG_B ; UNREGISTERED ; ; -- RAM_BLOCK_TYPE ; AUTO ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +-------------------------------------------+-----------------------------------------------+ +--------------------------------------------------------------------------------------------------+ ; lpm_mult Parameter Settings by Entity Instance ; +---------------------------------------+----------------------------------------------------------+ ; Name ; Value ; +---------------------------------------+----------------------------------------------------------+ ; Number of entity instances ; 3 ; ; Entity Instance ; riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; ; -- LPM_WIDTHA ; 32 ; ; -- LPM_WIDTHB ; 32 ; ; -- LPM_WIDTHP ; 64 ; ; -- LPM_REPRESENTATION ; UNSIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; ; -- LPM_WIDTHA ; 32 ; ; -- LPM_WIDTHB ; 32 ; ; -- LPM_WIDTHP ; 64 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; ; -- LPM_WIDTHA ; 32 ; ; -- LPM_WIDTHB ; 40 ; ; -- LPM_WIDTHP ; 72 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; +---------------------------------------+----------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; altshift_taps Parameter Settings by Entity Instance ; +----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Name ; Value ; +----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Number of entity instances ; 10 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 10 ; ; -- WIDTH ; 7 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 11 ; ; -- WIDTH ; 10 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 10 ; ; -- WIDTH ; 10 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 9 ; ; -- WIDTH ; 12 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 8 ; ; -- WIDTH ; 10 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 7 ; ; -- WIDTH ; 10 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 6 ; ; -- WIDTH ; 12 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 5 ; ; -- WIDTH ; 10 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 4 ; ; -- WIDTH ; 10 ; ; Entity Instance ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; ; -- NUMBER_OF_TAPS ; 1 ; ; -- TAP_DISTANCE ; 3 ; ; -- WIDTH ; 12 ; +----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "riscv_core:core|mulsu:mul_su" ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ ; datab[39..32] ; Input ; Info ; Stuck at GND ; ; result[71..64] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; result[31..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "riscv_core:core|mult:mul" ; +---------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +---------------+--------+----------+-------------------------------------------------------------------------------------+ ; result[31..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +---------------+--------+----------+-------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "ram128kB:ram" ; +---------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +---------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; address ; Input ; Warning ; Input port expression (30 bits) is wider than the input port (15 bits) it drives. The 15 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +---------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "uart_ctrl:uart_ctrl|altera_uart:uart" ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ; begintransfer ; Input ; Info ; Stuck at VCC ; ; chipselect ; Input ; Info ; Stuck at VCC ; ; irq ; Output ; Info ; Explicitly unconnected ; ; readdata[15..8] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------+ ; Port Connectivity Checks: "uart_ctrl:uart_ctrl|uart_fifo:uart_recv_buf" ; +------+--------+----------+----------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+--------+----------+----------------------------------------------+ ; full ; Output ; Info ; Explicitly unconnected ; +------+--------+----------+----------------------------------------------+ +-------------------------------------------------------------------------+ ; Port Connectivity Checks: "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf" ; +------+--------+----------+----------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+--------+----------+----------------------------------------------+ ; full ; Output ; Info ; Explicitly unconnected ; +------+--------+----------+----------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "clk100M:clk100" ; +----------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------+--------+----------+-------------------------------------------------------------------------------------+ ; outclk_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; locked ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ ; Top ; 00:00:27 ; +----------------+--------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version Info: Processing started: Mon Aug 30 18:39:30 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv Warning (125092): Tcl Script File alu/add_sub.qip not found Info (125063): set_global_assignment -name QIP_FILE alu/add_sub.qip Warning (125092): Tcl Script File alu/add_sub_s.qip not found Info (125063): set_global_assignment -name QIP_FILE alu/add_sub_s.qip Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. Warning (10335): Unrecognized synthesis attribute "HDL4SE" at ../verilog/riscv_core_v3.v(47) Warning (10335): Unrecognized synthesis attribute "CLSID" at ../verilog/riscv_core_v3.v(48) Warning (10335): Unrecognized synthesis attribute "softmodule" at ../verilog/riscv_core_v3.v(49) Info (12021): Found 1 design units, including 1 entities, in source file /gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v3.v Info (12023): Found entity 1: riscv_core Info (12021): Found 1 design units, including 1 entities, in source file de1_riscv_v3.v Info (12023): Found entity 1: de1_riscv Info (12021): Found 1 design units, including 1 entities, in source file uart/uart_fifo.v Info (12023): Found entity 1: uart_fifo Info (12021): Found 1 design units, including 1 entities, in source file uart/uart_ctrl.v Info (12023): Found entity 1: uart_ctrl Info (12021): Found 5 design units, including 5 entities, in source file uart/altera_uart.v Info (12023): Found entity 1: altera_uart_tx Info (12023): Found entity 2: altera_uart_rx_stimulus_source Info (12023): Found entity 3: altera_uart_rx Info (12023): Found entity 4: altera_uart_regs Info (12023): Found entity 5: altera_uart Info (12021): Found 1 design units, including 1 entities, in source file vgasig.v Info (12023): Found entity 1: vga_output Info (12021): Found 1 design units, including 1 entities, in source file vga_pll/vga_pll_0002.v Info (12023): Found entity 1: vga_pll_0002 Info (12021): Found 1 design units, including 1 entities, in source file ram/ram8kb.v Info (12023): Found entity 1: ram8kb Info (12021): Found 1 design units, including 1 entities, in source file regfile/regfile.v Info (12023): Found entity 1: regfile Info (12021): Found 1 design units, including 1 entities, in source file alu/mult.v Info (12023): Found entity 1: mult Info (12021): Found 1 design units, including 1 entities, in source file alu/mult_s.v Info (12023): Found entity 1: mult_s Info (12021): Found 1 design units, including 1 entities, in source file alu/div.v Info (12023): Found entity 1: div Info (12021): Found 1 design units, including 1 entities, in source file alu/div_s.v Info (12023): Found entity 1: div_s Info (12021): Found 1 design units, including 1 entities, in source file alu/adder.v Info (12023): Found entity 1: adder Info (12021): Found 1 design units, including 1 entities, in source file alu/suber.v Info (12023): Found entity 1: suber Info (12021): Found 1 design units, including 1 entities, in source file alu/mulsu.v Info (12023): Found entity 1: mulsu Info (12021): Found 1 design units, including 1 entities, in source file clk/clk100m.v Info (12023): Found entity 1: clk100M Info (12021): Found 1 design units, including 1 entities, in source file clk/clk100m/clk100m_0002.v Info (12023): Found entity 1: clk100M_0002 Info (12021): Found 1 design units, including 1 entities, in source file regfile/regfile_2.v Info (12023): Found entity 1: regfile_2 Info (12021): Found 1 design units, including 1 entities, in source file ram/ram16kb.v Info (12023): Found entity 1: ram16kB Info (12021): Found 1 design units, including 1 entities, in source file ram/ram128kb.v Info (12023): Found entity 1: ram128kB Info (12127): Elaborating entity "de1_riscv" for the top level hierarchy Warning (10036): Verilog HDL or VHDL warning at de1_riscv_v3.v(124): object "readcmd" assigned a value but never read Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(208): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(209): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(210): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(211): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(212): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(213): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(216): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(217): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(218): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(219): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(220): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(221): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(224): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(225): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(226): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(227): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(228): truncated value with size 8 to match size of target (7) Warning (10230): Verilog HDL assignment warning at de1_riscv_v3.v(229): truncated value with size 8 to match size of target (7) Warning (10034): Output port "DRAM_ADDR" at de1_riscv_v3.v(31) has no driver Warning (10034): Output port "DRAM_BA" at de1_riscv_v3.v(32) has no driver Warning (10034): Output port "LEDR[9..6]" at de1_riscv_v3.v(63) has no driver Warning (10034): Output port "VGA_B" at de1_riscv_v3.v(83) has no driver Warning (10034): Output port "VGA_G" at de1_riscv_v3.v(85) has no driver Warning (10034): Output port "VGA_R" at de1_riscv_v3.v(87) has no driver Warning (10034): Output port "ADC_CONVST" at de1_riscv_v3.v(11) has no driver Warning (10034): Output port "ADC_DIN" at de1_riscv_v3.v(12) has no driver Warning (10034): Output port "ADC_SCLK" at de1_riscv_v3.v(14) has no driver Warning (10034): Output port "AUD_DACDAT" at de1_riscv_v3.v(20) has no driver Warning (10034): Output port "AUD_XCK" at de1_riscv_v3.v(22) has no driver Warning (10034): Output port "DRAM_CAS_N" at de1_riscv_v3.v(33) has no driver Warning (10034): Output port "DRAM_CKE" at de1_riscv_v3.v(34) has no driver Warning (10034): Output port "DRAM_CLK" at de1_riscv_v3.v(35) has no driver Warning (10034): Output port "DRAM_CS_N" at de1_riscv_v3.v(36) has no driver Warning (10034): Output port "DRAM_LDQM" at de1_riscv_v3.v(38) has no driver Warning (10034): Output port "DRAM_RAS_N" at de1_riscv_v3.v(39) has no driver Warning (10034): Output port "DRAM_UDQM" at de1_riscv_v3.v(40) has no driver Warning (10034): Output port "DRAM_WE_N" at de1_riscv_v3.v(41) has no driver Warning (10034): Output port "FPGA_I2C_SCLK" at de1_riscv_v3.v(44) has no driver Warning (10034): Output port "IRDA_TXD" at de1_riscv_v3.v(57) has no driver Warning (10034): Output port "TD_RESET_N" at de1_riscv_v3.v(78) has no driver Warning (10034): Output port "VGA_BLANK_N" at de1_riscv_v3.v(82) has no driver Warning (10034): Output port "VGA_CLK" at de1_riscv_v3.v(84) has no driver Warning (10034): Output port "VGA_HS" at de1_riscv_v3.v(86) has no driver Warning (10034): Output port "VGA_SYNC_N" at de1_riscv_v3.v(88) has no driver Warning (10034): Output port "VGA_VS" at de1_riscv_v3.v(89) has no driver Info (12128): Elaborating entity "clk100M" for hierarchy "clk100M:clk100" Info (12128): Elaborating entity "clk100M_0002" for hierarchy "clk100M:clk100|clk100M_0002:clk100m_inst" Info (12128): Elaborating entity "altera_pll" for hierarchy "clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i" Warning (10036): Verilog HDL or VHDL warning at altera_pll.v(398): object "cntsel_temp" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altera_pll.v(400): object "gnd" assigned a value but never read Warning (10034): Output port "lvds_clk" at altera_pll.v(295) has no driver Warning (10034): Output port "loaden" at altera_pll.v(296) has no driver Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus Info (12130): Elaborated megafunction instantiation "clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i" Info (12133): Instantiated megafunction "clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i" with the following parameter: Info (12134): Parameter "fractional_vco_multiplier" = "false" Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" Info (12134): Parameter "operation_mode" = "direct" Info (12134): Parameter "number_of_clocks" = "2" Info (12134): Parameter "output_clock_frequency0" = "50.000000 MHz" Info (12134): Parameter "phase_shift0" = "0 ps" Info (12134): Parameter "duty_cycle0" = "50" Info (12134): Parameter "output_clock_frequency1" = "75.000000 MHz" Info (12134): Parameter "phase_shift1" = "0 ps" Info (12134): Parameter "duty_cycle1" = "50" Info (12134): Parameter "output_clock_frequency2" = "0 MHz" Info (12134): Parameter "phase_shift2" = "0 ps" Info (12134): Parameter "duty_cycle2" = "50" Info (12134): Parameter "output_clock_frequency3" = "0 MHz" Info (12134): Parameter "phase_shift3" = "0 ps" Info (12134): Parameter "duty_cycle3" = "50" Info (12134): Parameter "output_clock_frequency4" = "0 MHz" Info (12134): Parameter "phase_shift4" = "0 ps" Info (12134): Parameter "duty_cycle4" = "50" Info (12134): Parameter "output_clock_frequency5" = "0 MHz" Info (12134): Parameter "phase_shift5" = "0 ps" Info (12134): Parameter "duty_cycle5" = "50" Info (12134): Parameter "output_clock_frequency6" = "0 MHz" Info (12134): Parameter "phase_shift6" = "0 ps" Info (12134): Parameter "duty_cycle6" = "50" Info (12134): Parameter "output_clock_frequency7" = "0 MHz" Info (12134): Parameter "phase_shift7" = "0 ps" Info (12134): Parameter "duty_cycle7" = "50" Info (12134): Parameter "output_clock_frequency8" = "0 MHz" Info (12134): Parameter "phase_shift8" = "0 ps" Info (12134): Parameter "duty_cycle8" = "50" Info (12134): Parameter "output_clock_frequency9" = "0 MHz" Info (12134): Parameter "phase_shift9" = "0 ps" Info (12134): Parameter "duty_cycle9" = "50" Info (12134): Parameter "output_clock_frequency10" = "0 MHz" Info (12134): Parameter "phase_shift10" = "0 ps" Info (12134): Parameter "duty_cycle10" = "50" Info (12134): Parameter "output_clock_frequency11" = "0 MHz" Info (12134): Parameter "phase_shift11" = "0 ps" Info (12134): Parameter "duty_cycle11" = "50" Info (12134): Parameter "output_clock_frequency12" = "0 MHz" Info (12134): Parameter "phase_shift12" = "0 ps" Info (12134): Parameter "duty_cycle12" = "50" Info (12134): Parameter "output_clock_frequency13" = "0 MHz" Info (12134): Parameter "phase_shift13" = "0 ps" Info (12134): Parameter "duty_cycle13" = "50" Info (12134): Parameter "output_clock_frequency14" = "0 MHz" Info (12134): Parameter "phase_shift14" = "0 ps" Info (12134): Parameter "duty_cycle14" = "50" Info (12134): Parameter "output_clock_frequency15" = "0 MHz" Info (12134): Parameter "phase_shift15" = "0 ps" Info (12134): Parameter "duty_cycle15" = "50" Info (12134): Parameter "output_clock_frequency16" = "0 MHz" Info (12134): Parameter "phase_shift16" = "0 ps" Info (12134): Parameter "duty_cycle16" = "50" Info (12134): Parameter "output_clock_frequency17" = "0 MHz" Info (12134): Parameter "phase_shift17" = "0 ps" Info (12134): Parameter "duty_cycle17" = "50" Info (12134): Parameter "pll_type" = "General" Info (12134): Parameter "pll_subtype" = "General" Info (12128): Elaborating entity "uart_ctrl" for hierarchy "uart_ctrl:uart_ctrl" Warning (10036): Verilog HDL or VHDL warning at uart_ctrl.v(94): object "waitclk" assigned a value but never read Warning (10230): Verilog HDL assignment warning at uart_ctrl.v(106): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at uart_ctrl.v(177): truncated value with size 32 to match size of target (16) Info (12128): Elaborating entity "uart_fifo" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf" Info (12128): Elaborating entity "scfifo" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component" Info (12130): Elaborated megafunction instantiation "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component" Info (12133): Instantiated megafunction "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component" with the following parameter: Info (12134): Parameter "add_ram_output_register" = "OFF" Info (12134): Parameter "almost_full_value" = "240" Info (12134): Parameter "intended_device_family" = "Cyclone V" Info (12134): Parameter "lpm_numwords" = "1024" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "8" Info (12134): Parameter "lpm_widthu" = "10" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_nrc1.tdf Info (12023): Found entity 1: scfifo_nrc1 Info (12128): Elaborating entity "scfifo_nrc1" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated" Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_br91.tdf Info (12023): Found entity 1: a_dpfifo_br91 Info (12128): Elaborating entity "a_dpfifo_br91" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fqe1.tdf Info (12023): Found entity 1: altsyncram_fqe1 Info (12128): Elaborating entity "altsyncram_fqe1" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|altsyncram_fqe1:FIFOram" Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_gm8.tdf Info (12023): Found entity 1: cmpr_gm8 Info (12128): Elaborating entity "cmpr_gm8" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cmpr_gm8:almost_full_comparer" Info (12128): Elaborating entity "cmpr_gm8" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cmpr_gm8:three_comparison" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_k2b.tdf Info (12023): Found entity 1: cntr_k2b Info (12128): Elaborating entity "cntr_k2b" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_k2b:rd_ptr_msb" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_847.tdf Info (12023): Found entity 1: cntr_847 Info (12128): Elaborating entity "cntr_847" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_847:usedw_counter" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_s3b.tdf Info (12023): Found entity 1: cntr_s3b Info (12128): Elaborating entity "cntr_s3b" for hierarchy "uart_ctrl:uart_ctrl|uart_fifo:uart_send_buf|scfifo:scfifo_component|scfifo_nrc1:auto_generated|a_dpfifo_br91:dpfifo|cntr_s3b:wr_ptr" Info (12128): Elaborating entity "altera_uart" for hierarchy "uart_ctrl:uart_ctrl|altera_uart:uart" Info (12128): Elaborating entity "altera_uart_tx" for hierarchy "uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_tx:the_altera_uart_tx" Info (12128): Elaborating entity "altera_uart_rx" for hierarchy "uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx" Info (12128): Elaborating entity "altera_uart_rx_stimulus_source" for hierarchy "uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_uart_rx_stimulus_source:the_altera_uart_rx_stimulus_source" Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" Info (12130): Elaborated megafunction instantiation "uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" Info (12133): Instantiated megafunction "uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: Info (12134): Parameter "depth" = "2" Info (12128): Elaborating entity "altera_uart_regs" for hierarchy "uart_ctrl:uart_ctrl|altera_uart:uart|altera_uart_regs:the_altera_uart_regs" Info (12128): Elaborating entity "regfile" for hierarchy "regfile:regs" Info (12128): Elaborating entity "altsyncram" for hierarchy "regfile:regs|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "regfile:regs|altsyncram:altsyncram_component" Info (12133): Instantiated megafunction "regfile:regs|altsyncram:altsyncram_component" with the following parameter: Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "intended_device_family" = "Cyclone V" Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "32" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "widthad_a" = "5" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nco1.tdf Info (12023): Found entity 1: altsyncram_nco1 Info (12128): Elaborating entity "altsyncram_nco1" for hierarchy "regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated" Info (12128): Elaborating entity "ram128kB" for hierarchy "ram128kB:ram" Info (12128): Elaborating entity "altsyncram" for hierarchy "ram128kB:ram|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "ram128kB:ram|altsyncram:altsyncram_component" Info (12133): Instantiated megafunction "ram128kB:ram|altsyncram:altsyncram_component" with the following parameter: Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "init_file" = "../test_code/test.mif" Info (12134): Parameter "intended_device_family" = "Cyclone V" Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "32768" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "widthad_a" = "15" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_vir1.tdf Info (12023): Found entity 1: altsyncram_vir1 Info (12128): Elaborating entity "altsyncram_vir1" for hierarchy "ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated" Info (12021): Found 1 design units, including 1 entities, in source file db/decode_8la.tdf Info (12023): Found entity 1: decode_8la Info (12128): Elaborating entity "decode_8la" for hierarchy "ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated|decode_8la:decode3" Info (12021): Found 1 design units, including 1 entities, in source file db/decode_11a.tdf Info (12023): Found entity 1: decode_11a Info (12128): Elaborating entity "decode_11a" for hierarchy "ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated|decode_11a:rden_decode" Info (12021): Found 1 design units, including 1 entities, in source file db/mux_5hb.tdf Info (12023): Found entity 1: mux_5hb Info (12128): Elaborating entity "mux_5hb" for hierarchy "ram128kB:ram|altsyncram:altsyncram_component|altsyncram_vir1:auto_generated|mux_5hb:mux2" Info (12128): Elaborating entity "riscv_core" for hierarchy "riscv_core:core" Warning (10762): Verilog HDL Case Statement warning at riscv_core_v3.v(174): can't check case statement for completeness because the case expression has too many possible states Warning (10762): Verilog HDL Case Statement warning at riscv_core_v3.v(194): can't check case statement for completeness because the case expression has too many possible states Warning (10230): Verilog HDL assignment warning at riscv_core_v3.v(243): truncated value with size 32 to match size of target (5) Warning (10230): Verilog HDL assignment warning at riscv_core_v3.v(278): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at riscv_core_v3.v(282): truncated value with size 32 to match size of target (1) Info (10264): Verilog HDL Case Statement information at riscv_core_v3.v(266): all case item expressions in this case statement are onehot Warning (10230): Verilog HDL assignment warning at riscv_core_v3.v(322): truncated value with size 32 to match size of target (2) Warning (10230): Verilog HDL assignment warning at riscv_core_v3.v(326): truncated value with size 32 to match size of target (2) Info (10264): Verilog HDL Case Statement information at riscv_core_v3.v(332): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "adder" for hierarchy "riscv_core:core|adder:add" Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component" Info (12133): Instantiated megafunction "riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component" with the following parameter: Info (12134): Parameter "lpm_direction" = "ADD" Info (12134): Parameter "lpm_hint" = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" Info (12134): Parameter "lpm_representation" = "UNSIGNED" Info (12134): Parameter "lpm_type" = "LPM_ADD_SUB" Info (12134): Parameter "lpm_width" = "32" Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_tih.tdf Info (12023): Found entity 1: add_sub_tih Info (12128): Elaborating entity "add_sub_tih" for hierarchy "riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated" Info (12128): Elaborating entity "suber" for hierarchy "riscv_core:core|suber:sub" Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component" Info (12133): Instantiated megafunction "riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component" with the following parameter: Info (12134): Parameter "lpm_direction" = "SUB" Info (12134): Parameter "lpm_hint" = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" Info (12134): Parameter "lpm_representation" = "UNSIGNED" Info (12134): Parameter "lpm_type" = "LPM_ADD_SUB" Info (12134): Parameter "lpm_width" = "32" Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_ujh.tdf Info (12023): Found entity 1: add_sub_ujh Info (12128): Elaborating entity "add_sub_ujh" for hierarchy "riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component|add_sub_ujh:auto_generated" Info (12128): Elaborating entity "mult" for hierarchy "riscv_core:core|mult:mul" Info (12128): Elaborating entity "lpm_mult" for hierarchy "riscv_core:core|mult:mul|lpm_mult:lpm_mult_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|mult:mul|lpm_mult:lpm_mult_component" Info (12133): Instantiated megafunction "riscv_core:core|mult:mul|lpm_mult:lpm_mult_component" with the following parameter: Info (12134): Parameter "lpm_hint" = "MAXIMIZE_SPEED=5" Info (12134): Parameter "lpm_representation" = "UNSIGNED" Info (12134): Parameter "lpm_type" = "LPM_MULT" Info (12134): Parameter "lpm_widtha" = "32" Info (12134): Parameter "lpm_widthb" = "32" Info (12134): Parameter "lpm_widthp" = "64" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_b8n.v Info (12023): Found entity 1: mult_b8n Info (12128): Elaborating entity "mult_b8n" for hierarchy "riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated" Info (12128): Elaborating entity "mult_s" for hierarchy "riscv_core:core|mult_s:mul_s" Info (12128): Elaborating entity "lpm_mult" for hierarchy "riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component" Info (12133): Instantiated megafunction "riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component" with the following parameter: Info (12134): Parameter "lpm_hint" = "MAXIMIZE_SPEED=5" Info (12134): Parameter "lpm_representation" = "SIGNED" Info (12134): Parameter "lpm_type" = "LPM_MULT" Info (12134): Parameter "lpm_widtha" = "32" Info (12134): Parameter "lpm_widthb" = "32" Info (12134): Parameter "lpm_widthp" = "64" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_81n.v Info (12023): Found entity 1: mult_81n Info (12128): Elaborating entity "mult_81n" for hierarchy "riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated" Info (12128): Elaborating entity "mulsu" for hierarchy "riscv_core:core|mulsu:mul_su" Info (12128): Elaborating entity "lpm_mult" for hierarchy "riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component" Info (12133): Instantiated megafunction "riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component" with the following parameter: Info (12134): Parameter "lpm_hint" = "MAXIMIZE_SPEED=5" Info (12134): Parameter "lpm_representation" = "SIGNED" Info (12134): Parameter "lpm_type" = "LPM_MULT" Info (12134): Parameter "lpm_widtha" = "32" Info (12134): Parameter "lpm_widthb" = "40" Info (12134): Parameter "lpm_widthp" = "72" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_61n.v Info (12023): Found entity 1: mult_61n Info (12128): Elaborating entity "mult_61n" for hierarchy "riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated" Info (12128): Elaborating entity "div" for hierarchy "riscv_core:core|div:div" Info (12128): Elaborating entity "lpm_divide" for hierarchy "riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component" Info (12133): Instantiated megafunction "riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component" with the following parameter: Info (12134): Parameter "lpm_drepresentation" = "UNSIGNED" Info (12134): Parameter "lpm_hint" = "LPM_REMAINDERPOSITIVE=TRUE" Info (12134): Parameter "lpm_nrepresentation" = "UNSIGNED" Info (12134): Parameter "lpm_pipeline" = "12" Info (12134): Parameter "lpm_type" = "LPM_DIVIDE" Info (12134): Parameter "lpm_widthd" = "32" Info (12134): Parameter "lpm_widthn" = "32" Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_2jt.tdf Info (12023): Found entity 1: lpm_divide_2jt Info (12128): Elaborating entity "lpm_divide_2jt" for hierarchy "riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated" Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_8ai.tdf Info (12023): Found entity 1: sign_div_unsign_8ai Info (12128): Elaborating entity "sign_div_unsign_8ai" for hierarchy "riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider" Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_nlf.tdf Info (12023): Found entity 1: alt_u_div_nlf Info (12128): Elaborating entity "alt_u_div_nlf" for hierarchy "riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider" Info (12128): Elaborating entity "div_s" for hierarchy "riscv_core:core|div_s:divs" Info (12128): Elaborating entity "lpm_divide" for hierarchy "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component" with the following parameter: Info (12134): Parameter "lpm_drepresentation" = "SIGNED" Info (12134): Parameter "lpm_hint" = "LPM_REMAINDERPOSITIVE=TRUE" Info (12134): Parameter "lpm_nrepresentation" = "SIGNED" Info (12134): Parameter "lpm_pipeline" = "12" Info (12134): Parameter "lpm_type" = "LPM_DIVIDE" Info (12134): Parameter "lpm_widthd" = "32" Info (12134): Parameter "lpm_widthn" = "32" Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_s4t.tdf Info (12023): Found entity 1: lpm_divide_s4t Info (12128): Elaborating entity "lpm_divide_s4t" for hierarchy "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated" Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_2sh.tdf Info (12023): Found entity 1: sign_div_unsign_2sh Info (12128): Elaborating entity "sign_div_unsign_2sh" for hierarchy "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider" Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_5eg.tdf Info (12023): Found entity 1: alt_u_div_5eg Info (12128): Elaborating entity "alt_u_div_5eg" for hierarchy "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider" Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following PLL node(s): Warning (14320): Synthesized away node "clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[1]" Info (286030): Timing-Driven Synthesis is running Info (19000): Inferred 10 megafunctions from design logic Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign_rtl_0" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 10 Info (286033): Parameter WIDTH set to 7 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_0" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 11 Info (286033): Parameter WIDTH set to 10 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_1" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 10 Info (286033): Parameter WIDTH set to 10 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_2" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 9 Info (286033): Parameter WIDTH set to 12 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_3" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 8 Info (286033): Parameter WIDTH set to 10 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_4" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 7 Info (286033): Parameter WIDTH set to 10 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_5" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 6 Info (286033): Parameter WIDTH set to 12 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_6" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 5 Info (286033): Parameter WIDTH set to 10 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_7" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 4 Info (286033): Parameter WIDTH set to 10 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator_rtl_8" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 3 Info (286033): Parameter WIDTH set to 12 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "10" Info (12134): Parameter "WIDTH" = "7" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_7l21.tdf Info (12023): Found entity 1: shift_taps_7l21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_kr91.tdf Info (12023): Found entity 1: altsyncram_kr91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_8jf.tdf Info (12023): Found entity 1: cntr_8jf Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_c9c.tdf Info (12023): Found entity 1: cmpr_c9c Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "11" Info (12134): Parameter "WIDTH" = "10" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_hm21.tdf Info (12023): Found entity 1: shift_taps_hm21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_9u91.tdf Info (12023): Found entity 1: altsyncram_9u91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_9jf.tdf Info (12023): Found entity 1: cntr_9jf Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "10" Info (12134): Parameter "WIDTH" = "10" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_gm21.tdf Info (12023): Found entity 1: shift_taps_gm21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_7u91.tdf Info (12023): Found entity 1: altsyncram_7u91 Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "9" Info (12134): Parameter "WIDTH" = "12" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_bl21.tdf Info (12023): Found entity 1: shift_taps_bl21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rr91.tdf Info (12023): Found entity 1: altsyncram_rr91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_0if.tdf Info (12023): Found entity 1: cntr_0if Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "8" Info (12134): Parameter "WIDTH" = "10" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_9l21.tdf Info (12023): Found entity 1: shift_taps_9l21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lr91.tdf Info (12023): Found entity 1: altsyncram_lr91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_uhf.tdf Info (12023): Found entity 1: cntr_uhf Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "7" Info (12134): Parameter "WIDTH" = "10" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_cl21.tdf Info (12023): Found entity 1: shift_taps_cl21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_hr91.tdf Info (12023): Found entity 1: altsyncram_hr91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_thf.tdf Info (12023): Found entity 1: cntr_thf Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_b9c.tdf Info (12023): Found entity 1: cmpr_b9c Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "6" Info (12134): Parameter "WIDTH" = "12" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_dl21.tdf Info (12023): Found entity 1: shift_taps_dl21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_mr91.tdf Info (12023): Found entity 1: altsyncram_mr91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_shf.tdf Info (12023): Found entity 1: cntr_shf Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "5" Info (12134): Parameter "WIDTH" = "10" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_4l21.tdf Info (12023): Found entity 1: shift_taps_4l21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dr91.tdf Info (12023): Found entity 1: altsyncram_dr91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_rhf.tdf Info (12023): Found entity 1: cntr_rhf Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "4" Info (12134): Parameter "WIDTH" = "10" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_3l21.tdf Info (12023): Found entity 1: shift_taps_3l21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_9r91.tdf Info (12023): Found entity 1: altsyncram_9r91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_phf.tdf Info (12023): Found entity 1: cntr_phf Info (12130): Elaborated megafunction instantiation "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8" Info (12133): Instantiated megafunction "riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "3" Info (12134): Parameter "WIDTH" = "12" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_5l21.tdf Info (12023): Found entity 1: shift_taps_5l21 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_br91.tdf Info (12023): Found entity 1: altsyncram_br91 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ohf.tdf Info (12023): Found entity 1: cntr_ohf Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_a9c.tdf Info (12023): Found entity 1: cmpr_a9c Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder Warning (13034): The following nodes have both tri-state and non-tri-state drivers Warning (13035): Inserted always-enabled tri-state buffer between "GPIO[5]" and its non-tri-state driver. Warning (13039): The following bidir pins have no drivers Warning (13040): Bidir "AUD_ADCLRCK" has no driver Warning (13040): Bidir "AUD_BCLK" has no driver Warning (13040): Bidir "AUD_DACLRCK" has no driver Warning (13040): Bidir "DRAM_DQ[0]" has no driver Warning (13040): Bidir "DRAM_DQ[1]" has no driver Warning (13040): Bidir "DRAM_DQ[2]" has no driver Warning (13040): Bidir "DRAM_DQ[3]" has no driver Warning (13040): Bidir "DRAM_DQ[4]" has no driver Warning (13040): Bidir "DRAM_DQ[5]" has no driver Warning (13040): Bidir "DRAM_DQ[6]" has no driver Warning (13040): Bidir "DRAM_DQ[7]" has no driver Warning (13040): Bidir "DRAM_DQ[8]" has no driver Warning (13040): Bidir "DRAM_DQ[9]" has no driver Warning (13040): Bidir "DRAM_DQ[10]" has no driver Warning (13040): Bidir "DRAM_DQ[11]" has no driver Warning (13040): Bidir "DRAM_DQ[12]" has no driver Warning (13040): Bidir "DRAM_DQ[13]" has no driver Warning (13040): Bidir "DRAM_DQ[14]" has no driver Warning (13040): Bidir "DRAM_DQ[15]" has no driver Warning (13040): Bidir "FPGA_I2C_SDAT" has no driver Warning (13040): Bidir "PS2_CLK" has no driver Warning (13040): Bidir "PS2_CLK2" has no driver Warning (13040): Bidir "PS2_DAT" has no driver Warning (13040): Bidir "PS2_DAT2" has no driver Warning (13040): Bidir "GPIO[0]" has no driver Warning (13040): Bidir "GPIO[1]" has no driver Warning (13040): Bidir "GPIO[2]" has no driver Warning (13040): Bidir "GPIO[3]" has no driver Warning (13040): Bidir "GPIO[4]" has no driver Warning (13040): Bidir "GPIO[6]" has no driver Warning (13040): Bidir "GPIO[8]" has no driver Warning (13040): Bidir "GPIO[9]" has no driver Warning (13040): Bidir "GPIO[10]" has no driver Warning (13040): Bidir "GPIO[11]" has no driver Warning (13040): Bidir "GPIO[12]" has no driver Warning (13040): Bidir "GPIO[13]" has no driver Warning (13040): Bidir "GPIO[14]" has no driver Warning (13040): Bidir "GPIO[15]" has no driver Warning (13040): Bidir "GPIO[16]" has no driver Warning (13040): Bidir "GPIO[17]" has no driver Warning (13040): Bidir "GPIO[18]" has no driver Warning (13040): Bidir "GPIO[19]" has no driver Warning (13040): Bidir "GPIO[20]" has no driver Warning (13040): Bidir "GPIO[21]" has no driver Warning (13040): Bidir "GPIO[22]" has no driver Warning (13040): Bidir "GPIO[23]" has no driver Warning (13040): Bidir "GPIO[24]" has no driver Warning (13040): Bidir "GPIO[25]" has no driver Warning (13040): Bidir "GPIO[26]" has no driver Warning (13040): Bidir "GPIO[27]" has no driver Warning (13040): Bidir "GPIO[28]" has no driver Warning (13040): Bidir "GPIO[29]" has no driver Warning (13040): Bidir "GPIO[30]" has no driver Warning (13040): Bidir "GPIO[31]" has no driver Warning (13040): Bidir "GPIO[32]" has no driver Warning (13040): Bidir "GPIO[33]" has no driver Warning (13040): Bidir "GPIO[34]" has no driver Warning (13040): Bidir "GPIO[35]" has no driver Info (13000): Registers with preset signals will power-up high Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (13009): TRI or OPNDRN buffers permanently enabled Warning (13010): Node "GPIO[5]~synth" Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "ADC_CONVST" is stuck at GND Warning (13410): Pin "ADC_DIN" is stuck at GND Warning (13410): Pin "ADC_SCLK" is stuck at GND Warning (13410): Pin "AUD_DACDAT" is stuck at GND Warning (13410): Pin "AUD_XCK" is stuck at GND Warning (13410): Pin "DRAM_ADDR[0]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[1]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[2]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[3]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[4]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[5]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[6]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[7]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[8]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[9]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[10]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[11]" is stuck at GND Warning (13410): Pin "DRAM_ADDR[12]" is stuck at GND Warning (13410): Pin "DRAM_BA[0]" is stuck at GND Warning (13410): Pin "DRAM_BA[1]" is stuck at GND Warning (13410): Pin "DRAM_CAS_N" is stuck at GND Warning (13410): Pin "DRAM_CKE" is stuck at GND Warning (13410): Pin "DRAM_CLK" is stuck at GND Warning (13410): Pin "DRAM_CS_N" is stuck at GND Warning (13410): Pin "DRAM_LDQM" is stuck at GND Warning (13410): Pin "DRAM_RAS_N" is stuck at GND Warning (13410): Pin "DRAM_UDQM" is stuck at GND Warning (13410): Pin "DRAM_WE_N" is stuck at GND Warning (13410): Pin "FPGA_I2C_SCLK" is stuck at GND Warning (13410): Pin "IRDA_TXD" is stuck at GND Warning (13410): Pin "LEDR[6]" is stuck at GND Warning (13410): Pin "LEDR[7]" is stuck at GND Warning (13410): Pin "LEDR[8]" is stuck at GND Warning (13410): Pin "LEDR[9]" is stuck at GND Warning (13410): Pin "TD_RESET_N" is stuck at GND Warning (13410): Pin "VGA_BLANK_N" is stuck at GND Warning (13410): Pin "VGA_B[0]" is stuck at GND Warning (13410): Pin "VGA_B[1]" is stuck at GND Warning (13410): Pin "VGA_B[2]" is stuck at GND Warning (13410): Pin "VGA_B[3]" is stuck at GND Warning (13410): Pin "VGA_B[4]" is stuck at GND Warning (13410): Pin "VGA_B[5]" is stuck at GND Warning (13410): Pin "VGA_B[6]" is stuck at GND Warning (13410): Pin "VGA_B[7]" is stuck at GND Warning (13410): Pin "VGA_CLK" is stuck at GND Warning (13410): Pin "VGA_G[0]" is stuck at GND Warning (13410): Pin "VGA_G[1]" is stuck at GND Warning (13410): Pin "VGA_G[2]" is stuck at GND Warning (13410): Pin "VGA_G[3]" is stuck at GND Warning (13410): Pin "VGA_G[4]" is stuck at GND Warning (13410): Pin "VGA_G[5]" is stuck at GND Warning (13410): Pin "VGA_G[6]" is stuck at GND Warning (13410): Pin "VGA_G[7]" is stuck at GND Warning (13410): Pin "VGA_HS" is stuck at GND Warning (13410): Pin "VGA_R[0]" is stuck at GND Warning (13410): Pin "VGA_R[1]" is stuck at GND Warning (13410): Pin "VGA_R[2]" is stuck at GND Warning (13410): Pin "VGA_R[3]" is stuck at GND Warning (13410): Pin "VGA_R[4]" is stuck at GND Warning (13410): Pin "VGA_R[5]" is stuck at GND Warning (13410): Pin "VGA_R[6]" is stuck at GND Warning (13410): Pin "VGA_R[7]" is stuck at GND Warning (13410): Pin "VGA_SYNC_N" is stuck at GND Warning (13410): Pin "VGA_VS" is stuck at GND Warning (18029): Output pin "LEDR[1]" driven by bidirectional pin "GPIO[7]" cannot be tri-stated Info (17049): 16 registers lost all their fanouts during netlist optimizations. Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 5 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 17 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "ADC_DOUT" Warning (15610): No output dependent on input pin "AUD_ADCDAT" Warning (15610): No output dependent on input pin "CLOCK2_50" Warning (15610): No output dependent on input pin "CLOCK3_50" Warning (15610): No output dependent on input pin "CLOCK4_50" Warning (15610): No output dependent on input pin "IRDA_RXD" Warning (15610): No output dependent on input pin "TD_CLK27" Warning (15610): No output dependent on input pin "TD_DATA[0]" Warning (15610): No output dependent on input pin "TD_DATA[1]" Warning (15610): No output dependent on input pin "TD_DATA[2]" Warning (15610): No output dependent on input pin "TD_DATA[3]" Warning (15610): No output dependent on input pin "TD_DATA[4]" Warning (15610): No output dependent on input pin "TD_DATA[5]" Warning (15610): No output dependent on input pin "TD_DATA[6]" Warning (15610): No output dependent on input pin "TD_DATA[7]" Warning (15610): No output dependent on input pin "TD_HS" Warning (15610): No output dependent on input pin "TD_VS" Info (21057): Implemented 5789 device resources after synthesis - the final resource count might be different Info (21058): Implemented 32 input pins Info (21059): Implemented 112 output pins Info (21060): Implemented 60 bidirectional pins Info (21061): Implemented 5263 logic cells Info (21064): Implemented 311 RAM segments Info (21065): Implemented 1 PLLs Info (21062): Implemented 10 DSP elements Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 216 warnings Info: Peak virtual memory: 698 megabytes Info: Processing ended: Mon Aug 30 18:40:06 2021 Info: Elapsed time: 00:00:36 Info: Total CPU time (on all processors): 00:00:35