# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.

# IP: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/risc_axi_v5_top_riscv_core_with_axi_0_0.xci
# IP: The module: 'risc_axi_v5_top_riscv_core_with_axi_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.

# IP: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/ip/ram4KB/ram4KB.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==ram4KB || ORIG_REF_NAME==ram4KB} -quiet] -quiet

# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/ram4KB_ooc.xdc

# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/risc_axi_v5_top_riscv_core_with_axi_0_0_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'risc_axi_v5_top_riscv_core_with_axi_0_0'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet

# IP: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/risc_axi_v5_top_riscv_core_with_axi_0_0.xci
# IP: The module: 'risc_axi_v5_top_riscv_core_with_axi_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.

# IP: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/ip/ram4KB/ram4KB.xci
#dup# set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==ram4KB || ORIG_REF_NAME==ram4KB} -quiet] -quiet

# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/ram4KB_ooc.xdc

# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/risc_axi_v5_top_riscv_core_with_axi_0_0_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'risc_axi_v5_top_riscv_core_with_axi_0_0'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet