`timescale 1 ns / 1 ps

module riscv_core_with_axi_master (
	    // clock and reset
		input wire				wClk,
		input wire				nwReset,

		// Write Address
		output wire				wAWValid,
		output wire [31 : 0]	bAWAddr,
		output wire [2 : 0]		bAWProt,
		input wire				wAWReady,

		// Write Data 
		output wire				wWValid,
		output wire [31 : 0]	bWData,
		output wire [3 : 0]		bWStrb,
		input wire				wWReady,

		// Write Response
		output wire				wBReady,
		input wire [1 : 0]		bBResp,
		input wire				wBValid,

		// ReadAddr
		output wire				wARValid,
		output wire [31 : 0]	bARAddr,
		output wire [2 : 0]		bARProt,
		input wire				wARReady,

		//ReadData
		output wire				wRReady,
		input wire				wRValid,
		input wire [31 : 0]		bRData,
		input wire [1 : 0]		bRResp
);

	reg			axi_awvalid;	assign wAWValid = axi_awvalid;
	reg [31:0] 	axi_awaddr;		assign bAWAddr = axi_awaddr;
								assign bAWProt = 3'b000;

	reg			axi_wvalid;		assign wWValid = axi_wvalid;
	reg [31:0] 	axi_wdata;		assign bWData = axi_wdata;
	reg [3:0]   axi_wstrb;		assign bWStrb = axi_wstrb;

								assign wBReady = 1'b1;

	reg			axi_arvalid;	assign wARValid = axi_arvalid;
	reg [31:0] 	axi_araddr;		assign bARAddr = axi_araddr;
								assign bARProt = 3'b001;

								assign wRReady = 1'b1;

    wire wWrite, wRead, wReadReady, wWriteReady;
    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
	wire [3:0]  bWriteMask;

	wire [4:0]  regno;
    wire [3:0]  regena;
    wire [31:0] regwrdata;
    wire        regwren;
    wire [31:0] regrddata;
    wire [4:0]  regno2;
    wire [3:0]  regena2;
    wire [31:0] regwrdata2;
    wire        regwren2;
    wire [31:0] regrddata2;

	reg [31:0] lastreadaddr;
	reg		   lastread;

	always @(posedge wClk)
	if (~nwReset) begin
		lastreadaddr <= 0;
		lastread <= 0;
	end else begin
		lastreadaddr <= bReadAddr;
		lastread <= wRead;
	end

	assign bReadData = 
            ((lastreadaddr & 32'hf000_0000) == 32'hf000_0000) ? bRData : (
            ((lastreadaddr & 32'hff00_0000) == 32'h0000_0000) ? bReadDataRam : (32'h0)
            );

	assign wReadReady = ((lastreadaddr & 32'hf000_0000) == 32'hf000_0000) ? wRValid : (
						((lastreadaddr & 32'hfff0_0000) == 32'h0000_0000) ? lastread : (0)
						);


    wire [29:0] ramaddr;
    assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];

	reg [4:0] lastregno;
	reg [4:0] lastregno2;

	always @(posedge wClk) begin
		lastregno <= regno;
		lastregno2 <= regno2;
	end

    regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
    regfile    regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);

`define ALTERA

`ifdef ALTERA
	ram4kB    ram(.clock(wClk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0), .q(bReadDataRam));
`else
    ram4KB  ram(.clka(wClk), .ena(1'b1), .addra(ramaddr), .wea(((bWriteAddr & 32'hff000000) == 0 && wWrite)?(~bWriteMask):4'b0), .dina(bWriteData) , .douta(bReadDataRam));
`endif
	riscv_core_v5 core(
				wClk, 
				nwReset, 
				wWrite, 
				bWriteAddr, 
				bWriteData, 
				bWriteMask, 
				wWriteReady,
				wRead, 
				bReadAddr, 
				bReadData, 
				wReadReady,
                regno, 
				regena, 
				regwrdata, 
				regwren, 
				(lastregno == 0) ? 0 : regrddata,
				regno2, 
				regena2, 
				regwrdata2, 
				regwren2, 
				(lastregno2 == 0) ? 0 : regrddata2
				);


	//Write Address
	wire writeaxi = (wWrite && ((bWriteAddr & 32'hfff00000) != 0));
	reg [31:0] awaddr;
	reg awvalid;
	always @(posedge wClk)
	if (~nwReset) begin
		awvalid <= 1'b0;
	end else if (writeaxi) begin
		awaddr <= bWriteAddr;
		awvalid <= 1'b1;
	end else if (wAWReady) begin
		awvalid <= 1'b0;
	end

	always @(wWrite or awvalid or bWriteAddr or awaddr)
	begin
		axi_awvalid = writeaxi ? 1'b1 : awvalid;
		axi_awaddr = wWrite ? bWriteAddr : awaddr;
	end

	/* Write Data */
	reg [31:0] wdata;
	reg [3:0]  wstrb;
	reg		   wvalid;
	always @(posedge wClk)
	begin
		if (~nwReset) begin
			wvalid <= 1'b0;
		end if (writeaxi) begin
			wdata <= bWriteData;
			wstrb <= ~bWriteMask;
			wvalid <= 1'b1;
		end if (wWReady) begin
			wvalid <= 1'b0;
		end
	end

	assign wWriteReady = ((wWrite || wvalid) && wWReady) || writeaxi;

	always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb)
	begin
		axi_wvalid = writeaxi ? 1'b1 : wvalid;
		axi_wdata = writeaxi  ? bWriteData : wdata;
		axi_wstrb = writeaxi  ? ~bWriteMask : wstrb;
	end

	wire readaxi = wRead && ((bReadAddr & 32'hfff00000) != 0);
	//Read Address
	reg [31:0] araddr;
	reg arvalid;
	always @(posedge wClk)
	if (~nwReset) begin
		arvalid <= 1'b0;
	end else if (readaxi) begin
		araddr <= bReadAddr;
		arvalid <= 1'b1;
	end else if (wARReady) begin
		arvalid <= 1'b0;
	end

	always @(wRead or arvalid or bReadAddr or araddr)
	begin
		axi_arvalid = readaxi ? 1'b1 : arvalid;
		axi_araddr = wRead ? bReadAddr : araddr;
	end

endmodule

`timescale 1 ns / 1 ps

module riscv_core_with_axi_master_xilinxwrap
	(
		input wire  m00_axi_aclk,
		input wire  m00_axi_aresetn,
		output wire [31 : 0] m00_axi_awaddr,
		output wire [2 : 0] m00_axi_awprot,
		output wire  m00_axi_awvalid,
		input wire  m00_axi_awready,
		output wire [31 : 0] m00_axi_wdata,
		output wire [3 : 0] m00_axi_wstrb,
		output wire  m00_axi_wvalid,
		input wire  m00_axi_wready,
		input wire [1 : 0] m00_axi_bresp,
		input wire  m00_axi_bvalid,
		output wire  m00_axi_bready,
		output wire [31 : 0] m00_axi_araddr,
		output wire [2 : 0] m00_axi_arprot,
		output wire  m00_axi_arvalid,
		input wire  m00_axi_arready,
		input wire [31 : 0] m00_axi_rdata,
		input wire [1 : 0] m00_axi_rresp,
		input wire  m00_axi_rvalid,
		output wire  m00_axi_rready
	);

	riscv_core_with_axi_master riscv_core_inst (
		.wClk(m00_axi_aclk),
		.nwReset(m00_axi_aresetn),

		.bAWAddr(m00_axi_awaddr),
		.bAWProt(m00_axi_awprot),
		.wAWValid(m00_axi_awvalid),
		.wAWReady(m00_axi_awready),

		.bWData(m00_axi_wdata),
		.bWStrb(m00_axi_wstrb),
		.wWValid(m00_axi_wvalid),
		.wWReady(m00_axi_wready),

		.bBResp(m00_axi_bresp),
		.wBValid(m00_axi_bvalid),
		.wBReady(m00_axi_bready),

		.bARAddr(m00_axi_araddr),
		.bARProt(m00_axi_arprot),
		.wARValid(m00_axi_arvalid),
		.wARReady(m00_axi_arready),

		.bRData(m00_axi_rdata),
		.bRResp(m00_axi_rresp),
		.wRValid(m00_axi_rvalid),
		.wRReady(m00_axi_rready)
	);


endmodule