//======================================================= // This code is generated by Terasic System Builder //======================================================= module de1_riscv_axi( //////////// ADC ////////// output ADC_CONVST, output ADC_DIN, input ADC_DOUT, output ADC_SCLK, //////////// Audio ////////// input AUD_ADCDAT, inout AUD_ADCLRCK, inout AUD_BCLK, output AUD_DACDAT, inout AUD_DACLRCK, output AUD_XCK, //////////// CLOCK ////////// input CLOCK2_50, input CLOCK3_50, input CLOCK4_50, input CLOCK_50, //////////// SDRAM ////////// output [12:0] DRAM_ADDR, output [1:0] DRAM_BA, output DRAM_CAS_N, output DRAM_CKE, output DRAM_CLK, output DRAM_CS_N, inout [15:0] DRAM_DQ, output DRAM_LDQM, output DRAM_RAS_N, output DRAM_UDQM, output DRAM_WE_N, //////////// I2C for Audio and Video-In ////////// output FPGA_I2C_SCLK, inout FPGA_I2C_SDAT, //////////// SEG7 ////////// output [6:0] HEX0, output [6:0] HEX1, output [6:0] HEX2, output [6:0] HEX3, output [6:0] HEX4, output [6:0] HEX5, //////////// IR ////////// input IRDA_RXD, output IRDA_TXD, //////////// KEY ////////// input [3:0] KEY, //////////// LED ////////// output [9:0] LEDR, //////////// PS2 ////////// inout PS2_CLK, inout PS2_CLK2, inout PS2_DAT, inout PS2_DAT2, //////////// SW ////////// input [9:0] SW, //////////// Video-In ////////// input TD_CLK27, input [7:0] TD_DATA, input TD_HS, output TD_RESET_N, input TD_VS, //////////// VGA ////////// output VGA_BLANK_N, output [7:0] VGA_B, output VGA_CLK, output [7:0] VGA_G, output VGA_HS, output [7:0] VGA_R, output VGA_SYNC_N, output VGA_VS, //////////// GPIO_0, GPIO_0 connect to GPIO Default ////////// inout [35:0] GPIO ); wire uart_tx; wire uart_rx; assign GPIO[5] = uart_tx; assign GPIO[7] = 1'bz; assign uart_rx = GPIO[7]; assign LEDR[0] = uart_tx; assign LEDR[1] = uart_rx; `define USECLOCK50 `ifdef USECLOCK50 wire wClk = CLOCK_50; `else wire clk100MHz, clk75MHz, clklocked; clk100M clk100(.refclk(CLOCK_50), .rst(~KEY[3]), .outclk_0(clk100MHz), .outclk_1(clk75MHz), .locked(clklocked)); wire wClk = clk100MHz; `endif wire nwReset = KEY[3]; reg [6:0] led0; reg [6:0] led1; reg [6:0] led2; reg [6:0] led3; reg [6:0] led4; reg [6:0] led5; assign HEX0 = ~led0; assign HEX1 = ~led1; assign HEX2 = ~led2; assign HEX3 = ~led3; assign HEX4 = ~led4; assign HEX5 = ~led5; /* axi signals */ wire [31 : 0] m00_axi_awaddr; wire [2 : 0] m00_axi_awprot; wire m00_axi_awvalid; reg m00_axi_awready; wire [31 : 0] m00_axi_wdata; wire [3 : 0] m00_axi_wstrb; wire m00_axi_wvalid; reg m00_axi_wready; reg [1 : 0] m00_axi_bresp; reg m00_axi_bvalid; wire m00_axi_bready; wire [31 : 0] m00_axi_araddr; wire [2 : 0] m00_axi_arprot; wire m00_axi_arvalid; reg m00_axi_arready; reg [31 : 0] m00_axi_rdata; reg [1 : 0] m00_axi_rresp; reg m00_axi_rvalid; wire m00_axi_rready; riscv_core_with_axi_master_xilinxwrap core ( .m00_axi_aclk(wClk), .m00_axi_aresetn(nwReset), .m00_axi_awaddr(m00_axi_awaddr), .m00_axi_awprot(m00_axi_awprot), .m00_axi_awvalid(m00_axi_awvalid), .m00_axi_awready(m00_axi_awready), .m00_axi_wdata(m00_axi_wdata), .m00_axi_wstrb(m00_axi_wstrb), .m00_axi_wvalid(m00_axi_wvalid), .m00_axi_wready(m00_axi_wready), .m00_axi_bresp(m00_axi_bresp), .m00_axi_bvalid(m00_axi_bvalid), .m00_axi_bready(m00_axi_bready), .m00_axi_araddr(m00_axi_araddr), .m00_axi_arprot(m00_axi_arprot), .m00_axi_arvalid(m00_axi_arvalid), .m00_axi_arready(m00_axi_arready), .m00_axi_rdata(m00_axi_rdata), .m00_axi_rresp(m00_axi_rresp), .m00_axi_rvalid(m00_axi_rvalid), .m00_axi_rready(m00_axi_rready) ); wire is_led_key_w = ((m00_axi_awaddr & 32'hffff_ff00) == 32'hf000_0000); wire is_led_key_r = ((m00_axi_araddr & 32'hffff_ff00) == 32'hf000_0000); wire [3 : 0] s00_axi_awaddr = m00_axi_awaddr[3:0]; wire [2 : 0] s00_axi_awprot = m00_axi_awprot; wire s00_axi_awvalid = m00_axi_awvalid && is_led_key_w; wire s00_axi_awready; wire [31 : 0] s00_axi_wdata = m00_axi_wdata; wire [3 : 0] s00_axi_wstrb = m00_axi_wstrb; wire s00_axi_wvalid = m00_axi_wvalid && is_led_key_w; wire s00_axi_wready; wire [1 : 0] s00_axi_bresp; wire s00_axi_bvalid; wire s00_axi_bready = m00_axi_bready;//?? && is_led_key_w; wire [3 : 0] s00_axi_araddr = m00_axi_araddr; wire [2 : 0] s00_axi_arprot = m00_axi_arprot; wire s00_axi_arvalid = m00_axi_arvalid && is_led_key_r; wire s00_axi_arready; wire [31 : 0] s00_axi_rdata; wire [1 : 0] s00_axi_rresp; wire s00_axi_rvalid; wire s00_axi_rready = m00_axi_rready && is_led_key_r; led_key led_key_inst ( .s00_axi_aclk(wClk), .s00_axi_aresetn(nwReset), .s00_axi_awaddr(s00_axi_awaddr), .s00_axi_awprot(s00_axi_awprot), .s00_axi_awvalid(s00_axi_awvalid), .s00_axi_awready(s00_axi_awready), .s00_axi_wdata(s00_axi_wdata), .s00_axi_wstrb(s00_axi_wstrb), .s00_axi_wvalid(s00_axi_wvalid), .s00_axi_wready(s00_axi_wready), .s00_axi_bresp(s00_axi_bresp), .s00_axi_bvalid(s00_axi_bvalid), .s00_axi_bready(s00_axi_bready), .s00_axi_araddr(s00_axi_araddr), .s00_axi_arprot(s00_axi_arprot), .s00_axi_arvalid(s00_axi_arvalid), .s00_axi_arready(s00_axi_arready), .s00_axi_rdata(s00_axi_rdata), .s00_axi_rresp(s00_axi_rresp), .s00_axi_rvalid(s00_axi_rvalid), .s00_axi_rready(s00_axi_rready), .key(KEY[2:0]), .led(LEDR[5:2]) ); wire is_uart_w = ((m00_axi_awaddr & 32'hffff_ff00) == 32'hf000_0100); wire is_uart_r = ((m00_axi_araddr & 32'hffff_ff00) == 32'hf000_0100); wire [3 : 0] s01_axi_awaddr = m00_axi_awaddr[3:0]; wire [2 : 0] s01_axi_awprot = m00_axi_awprot; wire s01_axi_awvalid = m00_axi_awvalid && is_uart_w; wire s01_axi_awready; wire [31 : 0] s01_axi_wdata = m00_axi_wdata; wire [3 : 0] s01_axi_wstrb = m00_axi_wstrb; wire s01_axi_wvalid = m00_axi_wvalid && is_uart_w; wire s01_axi_wready; wire [1 : 0] s01_axi_bresp; wire s01_axi_bvalid; wire s01_axi_bready = m00_axi_bready;//?? && is_uart_w; wire [3 : 0] s01_axi_araddr = m00_axi_araddr; wire [2 : 0] s01_axi_arprot = m00_axi_arprot; wire s01_axi_arvalid = m00_axi_arvalid && is_uart_r; wire s01_axi_arready; wire [31 : 0] s01_axi_rdata; wire [1 : 0] s01_axi_rresp; wire s01_axi_rvalid; wire s01_axi_rready = m00_axi_rready && is_uart_r; hdl4se_uart_ctrl_axi ( .s00_axi_aclk(wClk), .s00_axi_aresetn(nwReset), .s00_axi_awaddr(s01_axi_awaddr), .s00_axi_awprot(s01_axi_awprot), .s00_axi_awvalid(s01_axi_awvalid), .s00_axi_awready(s01_axi_awready), .s00_axi_wdata(s01_axi_wdata), .s00_axi_wstrb(s01_axi_wstrb), .s00_axi_wvalid(s01_axi_wvalid), .s00_axi_wready(s01_axi_wready), .s00_axi_bresp(s01_axi_bresp), .s00_axi_bvalid(s01_axi_bvalid), .s00_axi_bready(s01_axi_bready), .s00_axi_araddr(s01_axi_araddr), .s00_axi_arprot(s01_axi_arprot), .s00_axi_arvalid(s01_axi_arvalid), .s00_axi_arready(s01_axi_arready), .s00_axi_rdata(s01_axi_rdata), .s00_axi_rresp(s01_axi_rresp), .s00_axi_rvalid(s01_axi_rvalid), .s00_axi_rready(s01_axi_rready), .uart_tx(uart_tx), .uart_rx(uart_rx), .dataready(LEDR[6]), .sendready(LEDR[7]), .sendfull(LEDR[8]), .recvempty(LEDR[9]) ); always @(*) if (is_led_key_w) m00_axi_awready = s00_axi_awready; else if (is_uart_w) m00_axi_awready = s01_axi_awready; else m00_axi_awready = 0; always @(*) if (is_led_key_w) m00_axi_wready = s00_axi_wready; else if (is_uart_w) m00_axi_wready = s01_axi_wready; else m00_axi_wready = 0; always @(*) if (is_led_key_w) m00_axi_bresp = s00_axi_bresp; else if (is_uart_w) m00_axi_bresp = s01_axi_bresp; else m00_axi_bresp = 0; always @(*) if (is_led_key_w) m00_axi_bvalid = s00_axi_bvalid; else if (is_uart_w) m00_axi_bvalid = s01_axi_bvalid; else m00_axi_bvalid = 0; always @(*) if (is_led_key_r) m00_axi_arready = s00_axi_arready; else if (is_uart_r) m00_axi_arready = s01_axi_arready; else m00_axi_arready = 0; always @(*) if (is_led_key_r) m00_axi_rdata = s00_axi_rdata; else if (is_uart_r) m00_axi_rdata = s01_axi_rdata; else m00_axi_rdata = 0; always @(*) if (is_led_key_r) m00_axi_rresp = s00_axi_rresp; else if (is_uart_r) m00_axi_rresp = s01_axi_rresp; else m00_axi_rresp = 0; always @(*) if (is_led_key_r) m00_axi_rvalid = s00_axi_rvalid; else if (is_uart_r) m00_axi_rvalid = s01_axi_rvalid; else m00_axi_rvalid = 0; endmodule module uart_fifo_gen ( clock, rst, data, rdreq, wrreq, empty, full, q, usedw); input clock; input rst; input [7:0] data; input rdreq; input wrreq; output empty; output full; output [7:0] q; output [9:0] usedw; uart_fifo uart_buf( .clock(clock), .data(data), .rdreq(rdreq), .wrreq(wrreq), .empty(empty), .almost_full(full), .full(), .q(q), .usedw(usedw)); endmodule