/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
**   this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
**   this list of conditions and the following disclaimer in the documentation
**   and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
**   derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/* riscv-sim_v4.v */

`include "riscv_core_v4.v"

(* 
  HDL4SE="LCOM", 
  CLSID="2925e2cf-dd49-4155-b31d-41d48f0f98dc", 
  softmodule="hdl4se" 
*) 
module digitled(
    input wClk, nwReset,
    input wWrite,
    input [31:0] bWriteAddr,
    input [31:0] bWriteData,
    input [3:0]  bWriteMask,
    input wRead,
    input [31:0] bReadAddr,
    output [31:0]  bReadData);
endmodule

(* 
  HDL4SE="LCOM", 
  CLSID="EE3409B2-6D04-42B3-A44D-7F2444DDC00D", 
  softmodule="hdl4se" 
*) 
module ram8kb (
    input	[29:0]  address,
    input	[3:0]   byteena,
    input           clock,
    input	[31:0]  data,
    input           wren,
    output	[31:0]  q);
endmodule

(* 
  HDL4SE="LCOM", 
  CLSID="2E577C6B-2FF1-425E-90B3-947EB523B863", 
  softmodule="hdl4se" 
*) 
module regfile (
    input	[4:0]  address,
    input	[3:0]   byteena,
    input           clock,
    input	[31:0]  data,
    input           wren,
    output	[31:0]  q);
endmodule


(* 
   HDL4SE="LCOM", 
   CLSID="76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2",
   softmodule="hdl4se" 
*) 
module hdl4se_reg
    #(parameter WIDTH=8) 
    (
      input wClk,
      input [WIDTH-1:0] wirein,
      output [WIDTH-1:0] wireout
    );
  wire [WIDTH-1:0] wirein;
  reg [WIDTH-1:0] wireout;
  always @(posedge wClk) wireout <= wirein;
endmodule

module top(input wClk, nwReset);
    wire wWrite, wRead;
    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
    wire [3:0]  bWriteMask;
    wire wRead_out;
    wire [31:0] bReadAddr_out;

    hdl4se_reg #(1) readcmd(wClk, wRead, wRead_out);
    hdl4se_reg #(32) readaddr(wClk, bReadAddr, bReadAddr_out);
    
    assign bReadData = 
            ((bReadAddr_out & 32'hffffff00) == 32'hf0000000) ? bReadDataKey : (
            ((bReadAddr_out & 32'hff000000) == 32'h00000000) ? bReadDataRam : (32'hffffffff)
            );

    wire [29:0] ramaddr;
    assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];

    wire [4:0]  regno;
    wire [3:0]  regena;
    wire [31:0] regwrdata;
    wire        regwren;
    wire [31:0] regrddata;
    wire [4:0]  regno2;
    wire [3:0]  regena2;
    wire [31:0] regwrdata2;
    wire        regwren2;
    wire [31:0] regrddata2;

    regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
    regfile    regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
    ram8kb     ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
    digitled   led(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadDataKey);
	riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
                regno, regena, regwrdata, regwren, regrddata,
                regno2, regena2, regwrdata2, regwren2, regrddata2
                );
endmodule