Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 | Date : Tue Sep 14 06:28:25 2021 | Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file risc_axi_v5_top_wrapper_timing_summary_routed.rpt -pb risc_axi_v5_top_wrapper_timing_summary_routed.pb -rpx risc_axi_v5_top_wrapper_timing_summary_routed.rpx -warn_on_violation | Design : risc_axi_v5_top_wrapper | Device : 7z020-clg400 | Speed File : -2 PRODUCTION 1.12 2019-11-22 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ Rule Severity Description Violations --------- ---------------- --------------------------- ---------- TIMING-17 Critical Warning Non-clocked sequential cell 891 Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report. check_timing report Table of Contents ----------------- 1. checking no_clock (891) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (2171) 5. checking no_input_delay (2) 6. checking no_output_delay (5) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (891) -------------------------- There are 891 register/latch pins with no clock driven by root clock pin: wClk (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (2171) --------------------------------------------------- There are 2171 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (2) ------------------------------ There are 2 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (5) ------------------------------- There are 5 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- NA NA NA NA NA NA NA NA NA NA NA NA All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------