/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
**   this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
**   this list of conditions and the following disclaimer in the documentation
**   and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
**   derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/

#include "stdlib.h"
#include "stdio.h"
#include "string.h"
#include "object.h"
#include "bignumber.h"
#include "hdl4secell.h"
#include "hdl4sesim.h"
#include "hdl4sevcdfile.h"
#include "counter.h"
#include "digitled.h"
#include "threadlock.h"

IHDL4SESimulator** sim;
IHDL4SEModuleVar* topmodule;
unsigned long long clocks = 0;

#define RECORDVCD 0

static int running = 1;
int StopRunning()
{
	running = 0;
	return 0;
}

IHDL4SEModuleVar* hdl4seCreate_main(IHDL4SEModuleVar* parent, const char* instanceparam, const char* name);

extern int (*A_u_t_o_registor_digitled)();
extern int (*A_u_t_o_registor_riscv_core)();

FILE* recordfile;
THREADLOCK recordfilelock;

FILE* recordfileGet()
{
	threadlockLock(recordfilelock);
	return recordfile;
}

void recordfileRelease()
{
	threadlockUnlock(recordfilelock);
}

int main(int argc, char* argv[])
{
	int i;
	int width;
	time_t starttime;
	time_t lasttime;
	IHDL4SEWaveOutput** vcdfile;
	A_u_t_o_registor_digitled();
	A_u_t_o_registor_riscv_core();
	recordfile = fopen("d:/gitwork/recordfile.txt", "w");
	recordfilelock = threadlockCreate();
	sim = hdl4sesimCreateSimulator();
	topmodule = hdl4seCreate_main(NULL, "", "top");
	objectCall1(sim, SetTopModule, topmodule);
	objectCall1(sim, SetReset, 0);
#if RECORDVCD
	vcdfile = hdl4sesimCreateVCDFile("riscv.vcd");
	objectCall2(vcdfile, AddSignal, "/top/core", "pc");
	objectCall2(vcdfile, AddSignal, "/top/core", "instr");
	objectCall2(vcdfile, AddSignal, "/top/core", "wWrite");
	objectCall2(vcdfile, AddSignal, "/top/core", "bWriteAddr");
	objectCall2(vcdfile, AddSignal, "/top/core", "bWriteData");
	objectCall2(vcdfile, AddSignal, "/top/core", "x1");
	objectCall2(vcdfile, AddSignal, "/top/core", "x2");
	objectCall2(vcdfile, AddSignal, "/top/core", "x3");
	objectCall2(vcdfile, AddSignal, "/top/core", "x4");
	objectCall2(vcdfile, AddSignal, "/top/core", "x5");
	objectCall2(vcdfile, AddSignal, "/top/core", "x6");
	objectCall2(vcdfile, AddSignal, "/top/core", "x7");
	objectCall2(vcdfile, AddSignal, "/top/core", "x8");
	objectCall2(vcdfile, AddSignal, "/top/core", "x9");
	objectCall2(vcdfile, AddSignal, "/top/core", "x10");
	objectCall2(vcdfile, AddSignal, "/top/core", "x11");
	objectCall2(vcdfile, AddSignal, "/top/core", "x12");
	objectCall2(vcdfile, AddSignal, "/top/core", "x13");
	objectCall2(vcdfile, AddSignal, "/top/core", "x14");
	objectCall2(vcdfile, AddSignal, "/top/core", "x15");
	objectCall2(vcdfile, AddSignal, "/top/core", "x16");
	objectCall2(vcdfile, AddSignal, "/top/core", "x17");
	objectCall2(vcdfile, AddSignal, "/top/core", "x18");
	objectCall2(vcdfile, AddSignal, "/top/core", "x19");
	objectCall2(vcdfile, AddSignal, "/top/core", "x20");
	objectCall2(vcdfile, AddSignal, "/top/core", "x21");
	objectCall2(vcdfile, AddSignal, "/top/core", "x22");
	objectCall2(vcdfile, AddSignal, "/top/core", "x23");
	objectCall2(vcdfile, AddSignal, "/top/core", "x24");
	objectCall2(vcdfile, AddSignal, "/top/core", "x25");
	objectCall2(vcdfile, AddSignal, "/top/core", "x26");
	objectCall2(vcdfile, AddSignal, "/top/core", "x27");
	objectCall2(vcdfile, AddSignal, "/top/core", "x28");
	objectCall2(vcdfile, AddSignal, "/top/core", "x29");
	objectCall2(vcdfile, AddSignal, "/top/core", "x30");
	objectCall2(vcdfile, AddSignal, "/top/core", "x31");
	objectCall1(vcdfile, SetTopModule, topmodule);
	objectCall0(vcdfile, StartRecord);
#endif
	objectPrintInfo(stdout, fprintf);
	lasttime = starttime = time(NULL);
	clocks = 0;
	do {
		objectCall0(sim, ClkTick);
#if RECORDVCD
		objectCall1(vcdfile, ClkTick, clocks);
#endif
		objectCall0(sim, Setup);
		clocks++;
		if (clocks == 4)
			objectCall1(sim, SetReset, 1);
		if ((clocks & 0xFFFF) == 0) {
			time_t thistime = time(NULL);
			printf("clocks: %lld, TSPD=%lfcps, LSPD=%lfcps\n",
				clocks,
				(double)clocks / (double)(thistime - starttime),
				4096.0 * 16 / (double)(thistime - lasttime));
			lasttime = time(NULL);
		}
	} while (running);
#if RECORDVCD
	objectCall0(vcdfile, StopRecord);
	objectRelease(vcdfile);
#endif
	return 0;
}