// sdram.v

// Generated using ACDS version 13.1 162 at 2021.09.23.20:17:56

`timescale 1 ps / 1 ps
module sdram (
		input  wire        clk_clk,                                 //                          clk.clk
		input  wire        reset_reset_n,                           //                        reset.reset_n
		output wire        clk_0_clk_reset_reset_n,                 //              clk_0_clk_reset.reset_n
		input  wire        new_sdram_controller_0_reset_reset_n,    // new_sdram_controller_0_reset.reset_n
		input  wire [24:0] new_sdram_controller_0_s1_address,       //    new_sdram_controller_0_s1.address
		input  wire [3:0]  new_sdram_controller_0_s1_byteenable_n,  //                             .byteenable_n
		input  wire        new_sdram_controller_0_s1_chipselect,    //                             .chipselect
		input  wire [31:0] new_sdram_controller_0_s1_writedata,     //                             .writedata
		input  wire        new_sdram_controller_0_s1_read_n,        //                             .read_n
		input  wire        new_sdram_controller_0_s1_write_n,       //                             .write_n
		output wire [31:0] new_sdram_controller_0_s1_readdata,      //                             .readdata
		output wire        new_sdram_controller_0_s1_readdatavalid, //                             .readdatavalid
		output wire        new_sdram_controller_0_s1_waitrequest,   //                             .waitrequest
		output wire [12:0] new_sdram_controller_0_wire_addr,        //  new_sdram_controller_0_wire.addr
		output wire [1:0]  new_sdram_controller_0_wire_ba,          //                             .ba
		output wire        new_sdram_controller_0_wire_cas_n,       //                             .cas_n
		output wire        new_sdram_controller_0_wire_cke,         //                             .cke
		output wire        new_sdram_controller_0_wire_cs_n,        //                             .cs_n
		inout  wire [31:0] new_sdram_controller_0_wire_dq,          //                             .dq
		output wire [3:0]  new_sdram_controller_0_wire_dqm,         //                             .dqm
		output wire        new_sdram_controller_0_wire_ras_n,       //                             .ras_n
		output wire        new_sdram_controller_0_wire_we_n         //                             .we_n
	);

	sdram_new_sdram_controller_0 new_sdram_controller_0 (
		.clk            (clk_clk),                                 //   clk.clk
		.reset_n        (new_sdram_controller_0_reset_reset_n),    // reset.reset_n
		.az_addr        (new_sdram_controller_0_s1_address),       //    s1.address
		.az_be_n        (new_sdram_controller_0_s1_byteenable_n),  //      .byteenable_n
		.az_cs          (new_sdram_controller_0_s1_chipselect),    //      .chipselect
		.az_data        (new_sdram_controller_0_s1_writedata),     //      .writedata
		.az_rd_n        (new_sdram_controller_0_s1_read_n),        //      .read_n
		.az_wr_n        (new_sdram_controller_0_s1_write_n),       //      .write_n
		.za_data        (new_sdram_controller_0_s1_readdata),      //      .readdata
		.za_valid       (new_sdram_controller_0_s1_readdatavalid), //      .readdatavalid
		.za_waitrequest (new_sdram_controller_0_s1_waitrequest),   //      .waitrequest
		.zs_addr        (new_sdram_controller_0_wire_addr),        //  wire.export
		.zs_ba          (new_sdram_controller_0_wire_ba),          //      .export
		.zs_cas_n       (new_sdram_controller_0_wire_cas_n),       //      .export
		.zs_cke         (new_sdram_controller_0_wire_cke),         //      .export
		.zs_cs_n        (new_sdram_controller_0_wire_cs_n),        //      .export
		.zs_dq          (new_sdram_controller_0_wire_dq),          //      .export
		.zs_dqm         (new_sdram_controller_0_wire_dqm),         //      .export
		.zs_ras_n       (new_sdram_controller_0_wire_ras_n),       //      .export
		.zs_we_n        (new_sdram_controller_0_wire_we_n)         //      .export
	);

	assign clk_0_clk_reset_reset_n = reset_reset_n;

endmodule