if {[string first $scripts_vivado_version $current_vivado_version] == -1 }{
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR""This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq ""}{
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq ""}{
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name }{
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO""Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR""Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $led_key_0 eq ""}{
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR""Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: riscv_core_with_axi_0, and set properties
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR""Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $riscv_core_with_axi_0 eq ""}{
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR""Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: riscv_core_with_axi_0_axi_periph, and set properties
set riscv_core_with_axi_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 riscv_core_with_axi_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {2}\
] $riscv_core_with_axi_0_axi_periph
# Create instance: rst_wClk_50M, and set properties
set rst_wClk_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_wClk_50M ]
