Merge branch 'master' of https://codechina.csdn.net/m0_56903617/hdl4se

bignumber/src/bignumber.c

@@ -52,7 +52,7 @@
 #define HDL4SEDEBUG 1
 
 #if HDL4SEDEBUG
-char __debug_buf[60];
+static char __debug_buf[60];
 #endif
 
 #define CELL_WIDTH 32

examples/counter/CMakeLists.txt

@@ -10,7 +10,7 @@ add_executable (counter
 	"src/main.c"
 	"src/counter_main.c"
 	)
-target_link_libraries(counter hdl4sesim hdl4secell bignumber digitled hdl4seutils verilog_preprocess verilog_parser glfw lcom)
+target_link_libraries(counter hdl4sesim hdl4secell bignumber digitled hdl4seutils verilog_parser verilog_preprocess glfw lcom)
 
 include_directories("../../../lcom/include")
 include_directories("../../hdl4sesim/include")

examples/terris/src/main.c

@@ -49,7 +49,7 @@ unsigned long long clocks = 0;
 
 static int running = 1;
 
-#define VCDOUTPUT 0
+#define VCDOUTPUT 1
 
 int StopRunning()
 {

examples/terris/src/terris_main_module.c

@@ -31,7 +31,7 @@
 
 
 /*
-*  Created by HDL4SE @ Wed Jun 30 08:28:32 2021
+*  Created by HDL4SE @ Thu Jul  1 06:39:07 2021
 *  Don't edit it.
 */
 

hdl4secell/src/hdl4se_binop.c

@@ -47,7 +47,7 @@
 #define  HDL4SEDEBUG 1
 
 #if HDL4SEDEBUG
-char __debug_buf[60];
+static char __debug_buf[60];
 #endif
 
 #define INCOUNT 2

parser/CMakeLists.txt

@@ -32,7 +32,8 @@ add_library (verilog_parser STATIC
   "verilog_moduleinst.c" 
   "verilog_assignment.h" 
   "verilog_assignment.c"
-  )
+   "verilog_statement.h"
+   "verilog_statement.c")
  
 include_directories("../../lcom/include")
 include_directories("../hdl4secell/include")

parser/verilog_assignment.c

@@ -212,6 +212,7 @@ static int assignment_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT
 }
 
 HOBJECT verilogparseCreateAssignment(
+	int assignmenttype,
 	IDListVarPtr hierarchical_identifier,
 	IDListVarPtr element_select,
 	int range_type,
@@ -227,6 +228,7 @@ HOBJECT verilogparseCreateAssignment(
 	if (assignment == NULL)
 		return NULL;
 	pobj = (sAssignment *)objectThis(assignment);
+	pobj->data.assignmenttype = assignmenttype;
 	pobj->data.constelementsel = constelementsel;
 	pobj->data.attributes = attributes;
 	pobj->data.hierarchical_identifier = hierarchical_identifier;

parser/verilog_assignment.h

@@ -50,6 +50,7 @@ DEFINE_GUID(CLSID_VERILOG_ASSIGNMENT, 0x63b29bb6, 0xec02, 0x4ae9, 0x9b, 0xef, 0x
 
 
 typedef struct _s_verilog_Assignment {
+    int assignmenttype;
     IDListVarPtr hierarchical_identifier;
     IDListVarPtr element_select;
     int range_type;
@@ -59,6 +60,7 @@ typedef struct _s_verilog_Assignment {
 }verilog_Assignment;
 
 HOBJECT verilogparseCreateAssignment(
+    int assignmenttype,
     IDListVarPtr hierarchical_identifier,
     IDListVarPtr element_select,
     int range_type,

parser/verilog_module.c

@@ -425,6 +425,12 @@ int verilogparseAddModuleItems(HOBJECT object, IDListVarPtr itemlist, int type)
         dlistConcat(pModule->data.continuous_assignments, itemlist);
         return 0;
     }
+    if (type == MODULE_ITEM_TYPE_ALWAYS_CONSTRUCT) {
+        if (pModule->data.always_blocks == NULL)
+            pModule->data.always_blocks = dlistCreate();
+        dlistConcat(pModule->data.always_blocks, itemlist);
+        return 0;
+    }
     return -2;
 }
 

parser/verilog_module.h

@@ -101,6 +101,7 @@ enum MODULE_ITEM_TYPE {
     MODULE_ITEM_TYPE_NET_DECLARATION,
     MODULE_ITEM_TYPE_MODULE_INSTANCE,
     MODULE_ITEM_TYPE_CONTINUOUS_ASSIGNMENT,
+    MODULE_ITEM_TYPE_ALWAYS_CONSTRUCT,
 };
 
 int verilogparseAddModuleItems(HOBJECT object, IDListVarPtr itemlist, int type);

parser/verilog_parser.h

@@ -66,8 +66,9 @@ extern int yydebug;
 #include "verilog_paraminst.h"
 #include "verilog_moduleinst.h"
 #include "verilog_assignment.h"
+#include "verilog_statement.h"
 
-#line 71 "D:/gitwork/hdl4se/parser/verilog_parser.h"
+#line 72 "D:/gitwork/hdl4se/parser/verilog_parser.h"
 
 /* Token kinds.  */
 #ifndef YYTOKENTYPE
@@ -271,7 +272,7 @@ extern int yydebug;
 #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
 union YYSTYPE
 {
-#line 104 "D:/gitwork/hdl4se/parser/verilog_parser.y"
+#line 105 "D:/gitwork/hdl4se/parser/verilog_parser.y"
 
 	HOBJECT treenode;
     HOBJECT obj;
@@ -290,7 +291,7 @@ union YYSTYPE
 	int ival;
 	IDListVar* list;
 
-#line 294 "D:/gitwork/hdl4se/parser/verilog_parser.h"
+#line 295 "D:/gitwork/hdl4se/parser/verilog_parser.h"
 
 };
 typedef union YYSTYPE YYSTYPE;

parser/verilog_parser.y

@@ -98,6 +98,7 @@
 #include "verilog_paraminst.h"
 #include "verilog_moduleinst.h"
 #include "verilog_assignment.h"
+#include "verilog_statement.h"
 }
 
 /* token types */
@@ -216,6 +217,7 @@
                   named_port_connection ordered_port_connection
                   net_assignment
                   hierarchical_identifier_part
+                  statement statement_or_null blocking_assignment  nonblocking_assignment
 
 %type <list> attribute_instance_list attribute_instance attribute_instance_spec_list
              hierarchical_identifier 
@@ -730,7 +732,7 @@ module_or_generate_item :
   }
 | attribute_instance_list initial_construct {
   }
-| attribute_instance_list always_construct {
+| always_construct {
   }
 | attribute_instance_list loop_generate_construct {
   }
@@ -2721,6 +2723,7 @@ net_assignment :
 net_assignment : 
     var '=' expression {
         $$ = verilogparseCreateAssignment(
+            0,
 	        $1.obj[0], /* IDListVarPtr hierarchical_identifier */
 	        $1.obj[1], /* IDListVarPtr element_select */
             $1.type, //int range_type,
@@ -2741,7 +2744,8 @@ initial_construct :
   ;
 
 always_construct : 
-    KW_ALWAYS statement {
+    attribute_instance_list KW_ALWAYS statement {
+    verilogparseAddModuleItems(currentmodule, $3, MODULE_ITEM_TYPE_ALWAYS_CONSTRUCT);
     }
   ;
 
@@ -2753,15 +2757,48 @@ delay_or_event_control_option :
   ;
 
 blocking_assignment : 
-    variable_lvalue '=' expression {
+    attribute_instance_list var '=' delay_or_event_control_option expression {
+        $$ = verilogparseCreateAssignmentStatement(
+            TIMECONTROL_NONE,
+            STATEMENT_BLOCKING_ASSIGNMENT,
+            verilogparseCreateAssignment(
+                0,
+	            $2.obj[0], /* IDListVarPtr hierarchical_identifier */
+	            $2.obj[1], /* IDListVarPtr element_select */
+                $2.type, //int range_type,
+	            1, /* int constelementsel */
+	            $5, /* HOBJECT expr */
+	            $1 /* IDListVarPtr attributes */
+            )
+        );
     }
+/* 
+    variable_lvalue '=' expression
 |   variable_lvalue '=' delay_or_event_control_option  expression {
     }
+*/
   ;
 
 nonblocking_assignment : 
+    attribute_instance_list var LTE delay_or_event_control_option expression {
+        $$ = verilogparseCreateAssignmentStatement(
+            TIMECONTROL_NONE,
+            STATEMENT_NONBLOCKING_ASSIGNMENT,
+            verilogparseCreateAssignment (
+                1,
+	            $2.obj[0], /* IDListVarPtr hierarchical_identifier */
+	            $2.obj[1], /* IDListVarPtr element_select */
+                $2.type, //int range_type,
+	            1, /* int constelementsel */
+	            $5, /* HOBJECT expr */
+	            $1 /* IDListVarPtr attributes */
+            )
+        );
+    }
+/*
     variable_lvalue LTE delay_or_event_control_option expression {
     }
+*/
   ;
 procedural_continuous_assignments :
     KW_ASSIGN variable_assignment {
@@ -2822,7 +2859,8 @@ seq_block :
 A.6.4 Statements
 */
 statement :
-    attribute_instance_list blocking_assignment ';' {
+    blocking_assignment ';' {
+    $$ = 1;
     }
 |   attribute_instance_list case_statement {
     }
@@ -2834,7 +2872,8 @@ statement :
     }
 |   attribute_instance_list loop_statement {
     }
-|   attribute_instance_list nonblocking_assignment ';' {
+|   nonblocking_assignment ';' {
+    $$ = 1;
     }
 |   attribute_instance_list par_block {
     }
@@ -2854,8 +2893,10 @@ statement :
 
 statement_or_null :
     statement {
+    $$ = $1;
     }
 |   attribute_instance_list ';' {
+    /*$$ = NULL*/
     }
   ;
 

parser/verilog_parsetree.h

@@ -120,6 +120,7 @@ enum VAR_TYPE {
     VAR_TYPE_REG,
 };
 
+
 enum VECT_OR_SCALAR {
     VS_NONE,
     VS_VECTORED,

parser/verilog_statement.c

+/*
+** HDL4SE: 软件Verilog综合仿真平台
+** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
+** LCOM: 轻量级组件对象模型
+** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without
+** modification, are permitted provided that the following conditions are met:
+**
+** * Redistributions of source code must retain the above copyright notice,
+**   this list of conditions and the following disclaimer.
+** * Redistributions in binary form must reproduce the above copyright notice,
+**   this list of conditions and the following disclaimer in the documentation
+**   and/or other materials provided with the distribution.
+** * The name of the author may be used to endorse or promote products
+**   derived from this software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY statementESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+** THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* verilog_statement.c
+  修改记录：
+    202107010615: rxh, initial version
+*/
+#include "stdio.h"
+#include "stdlib.h"
+#include "string.h"
+
+#include "object.h"
+#include "dlist.h"
+#include "bignumber.h"
+#include "conststring.h"
+#include "verilog_parsetree.h"
+#include "verilog_varsel.h"
+#include "verilog_expr.h"
+#include "verilog_assignment.h"
+#define IMPLEMENT_GUID
+#include "verilog_statement.h"
+#undef IMPLEMENT_GUID
+
+typedef struct _sAssignment {
+	OBJECT_HEADER
+	INTERFACE_DECLARE(IVerilogNode)
+	VERILOGNODE_VARDECLARE
+	DLIST_VARDECLARE
+
+	verilog_Statement data;
+}sStatement;
+
+OBJECT_FUNCDECLARE(statement, CLSID_VERILOG_STATEMENT);
+
+VERILOGNODE_FUNCDECLARE(statement, CLSID_VERILOG_STATEMENT, sStatement);
+DLIST_FUNCIMPL(statement, CLSID_VERILOG_STATEMENT, sStatement);
+OBJECT_FUNCIMPL(statement, sStatement, CLSID_VERILOG_STATEMENT);
+
+QUERYINTERFACE_BEGIN(statement, CLSID_VERILOG_STATEMENT)
+QUERYINTERFACE_ITEM(IID_VERILOG_NODE, IVerilogNode, sStatement)
+QUERYINTERFACE_ITEM(IID_DLIST, IDList, sStatement)
+QUERYINTERFACE_END
+
+static const char *statementModuleInfo()
+{
+	return "1.0.0-20210701.0615 Statement ";
+}
+
+static int statementCreate(const PARAMITEM * pParams, int paramcount, HOBJECT * pObject)
+{
+	sStatement * pobj;
+	pobj = (sStatement *)malloc(sizeof(sStatement));
+	if (pobj == NULL)
+		return -1;
+
+	memset(pobj, 0, sizeof(sStatement));
+	
+	*pObject = 0;
+	DLIST_VARINIT(pobj, statement);
+	VERILOGNODE_VARINIT(pobj, CLSID_VERILOG_STATEMENT);
+	INTERFACE_INIT(IVerilogNode, pobj, statement, verilognode);
+  	
+	/*返回生成的对象*/
+	OBJECT_RETURN_GEN(statement, pobj, pObject, CLSID_VERILOG_STATEMENT);
+	return EIID_OK;
+}
+
+
+static void statementDestroy(HOBJECT object)
+{
+	sStatement * pobj;
+	pobj = (sStatement *)objectThis(object);
+
+	free(pobj);
+}
+
+/*
+    功能：判断对象是否是一个有效对象
+    参数：
+        object -- 对象数据指针
+    返回值：
+        0 -- 对象是无效的
+        1 -- 对象是有效的
+*/
+static int statementValid(HOBJECT object)
+{
+    return 1;
+}
+
+static int output_attributes(FILE* pFile, int opt, sStatement* pobj)
+{
+	return 0;
+}
+
+static int statement_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
+{
+	sStatement * pobj;
+	pobj = (sStatement *)objectThis(object);
+	return 0;
+}
+
+static int statement_verilognode_procheck(HOBJECT object, HOBJECT module, void * param)
+{
+	sStatement* pobj;
+	pobj = (sStatement*)objectThis(object);
+	return 0;
+}
+
+static int statement_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module, void * param)
+{
+	return 0;
+}
+
+HOBJECT verilogparseCreateAssignmentStatement(
+	int timecontrol,
+	int statementtype,
+	HOBJECT assignment
+)
+{
+	HOBJECT statement = NULL;
+	sStatement * pobj;
+	A_u_t_o_registor_statement();
+	objectCreate(CLSID_VERILOG_STATEMENT, NULL, 0, &statement);
+	if (statement == NULL)
+		return NULL;
+	pobj = (sStatement *)objectThis(statement);
+	pobj->data.timecontrol = timecontrol;
+	pobj->data.statementtype = statementtype;
+	objectQueryInterface(assignment, IID_VERILOG_NODE, (void**)&pobj->data.assignment);
+	objectRelease(assignment);
+	return statement;
+}
+
+verilog_Statement* verilogStatementGetData(HOBJECT object)
+{
+	sStatement* pobj;
+	if (!objectIsClass(object, CLSID_VERILOG_STATEMENT))
+		return NULL;
+	pobj = (sStatement*)objectThis(object);
+	return &pobj->data;
+}
\ No newline at end of file

parser/verilog_statement.h

+/*
+** HDL4SE: 软件Verilog综合仿真平台
+** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
+** LCOM: 轻量级组件对象模型
+** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without
+** modification, are permitted provided that the following conditions are met:
+**
+** * Redistributions of source code must retain the above copyright notice,
+**   this list of conditions and the following disclaimer.
+** * Redistributions in binary form must reproduce the above copyright notice,
+**   this list of conditions and the following disclaimer in the documentation
+**   and/or other materials provided with the distribution.
+** * The name of the author may be used to endorse or promote products
+**   derived from this software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+** THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* verilog_statement.h
+  修改记录：
+    202107010553: rxh, initial version
+*/
+
+#ifndef __VERILOG_STATEMENT_H
+#define __VERILOG_STATEMENT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASMLANGUAGE
+
+#include "guid.h"
+
+DEFINE_GUID(CLSID_VERILOG_STATEMENT, 0xdc134100, 0xf8b0, 0x4093, 0x91, 0xdc, 0x45, 0x9a, 0xd2, 0x72, 0x93, 0x29);
+
+enum TIMECONTROL_TYPE {
+    TIMECONTROL_NONE,
+    TIMECONTROL_DELAY,
+    TIMECONTROL_SINGALCHANGE,
+    TIMECONTROL_ATPOSEDGE,
+    TIMECONTROL_ATNEGEDGE
+};
+
+enum STATEMENT_TYPE {
+    STATEMENT_NULL,
+    STATEMENT_BLOCKING_ASSIGNMENT,
+    STATEMENT_CASE,
+    STATEMENT_CONDITIONAL,
+    STATEMENT_DISABLE,
+    STATEMENT_EVENT_TRIGGER,
+    STATEMENT_FOREVER,
+    STATEMENT_REPEAT,
+    STATEMENT_WHILE,
+    STATEMENT_FOR,
+    STATEMENT_NONBLOCKING_ASSIGNMENT,
+    STATEMENT_CONTINUOUS_ASSIGNMENT,
+    STATEMENT_SEQ,
+    STATEMENT_PAR,
+    STATEMENT_SYSTEM_TASK_ENABLE,
+    STATEMENT_TASK_ENABLE,
+    STATEMENT_WAIT
+};
+
+typedef struct _s_verilog_Statement {
+    int timecontrol; 
+    int statementtype;
+
+    union {
+        struct {
+            HOBJECT assignment;
+        };
+    };
+}verilog_Statement;
+
+HOBJECT verilogparseCreateAssignmentStatement(
+    int timecontrol,
+    int statementtype,
+    HOBJECT assignment
+    );
+
+verilog_Statement* verilogStatementGetData(HOBJECT object);
+
+#endif    
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 

parser/verilog_vardecl.c

@@ -214,6 +214,7 @@ static int vardecl_verilognode_procheck(HOBJECT object, HOBJECT module, void * p
 				NULL  //HOBJECT range_lsb
 			));
 			continuous_assign = verilogparseCreateAssignment(
+				0,
 				lvalue,
 				NULL, 
 				RANGE_TYPE_NONE,

testparser/main.c

@@ -14,7 +14,7 @@
 int SetPreProcess(HOBJECT object);
 int yylex();
 int yyparse(void);
-char* yytext;
+extern char* yytext;
 
 static char logbuf[64 * 1024];
 

testscanner/main.c

@@ -12,7 +12,7 @@
 
 int SetPreProcess(HOBJECT object);
 int yylex();
-char* yytext;
+extern char* yytext;
 
 int main(int argc, char* argv[])
 {