diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4.qws b/examples/hdl4se_riscv/de2/de2_riscv_v4.qws new file mode 100644 index 0000000000000000000000000000000000000000..4e88154a445eb119971cb5c8b448465b1098cc85 Binary files /dev/null and b/examples/hdl4se_riscv/de2/de2_riscv_v4.qws differ diff --git a/examples/hdl4se_riscv/hdl4se_riscv_sim/CMakeLists.txt b/examples/hdl4se_riscv/hdl4se_riscv_sim/CMakeLists.txt index f3efb134b5c5e279d95d0f094fad97001f849be5..feb8d168be99ed9811ad89fe3e81f4753d7f2dbe 100644 --- a/examples/hdl4se_riscv/hdl4se_riscv_sim/CMakeLists.txt +++ b/examples/hdl4se_riscv/hdl4se_riscv_sim/CMakeLists.txt @@ -33,6 +33,11 @@ add_executable(riscv_sim "hdl4se_riscv_core.c" ) +add_executable(cod2mif + "cod2mif.c" + ) + + add_definitions(-D_CRT_SECURE_NO_WARNINGS) if(WIN32) diff --git a/examples/hdl4se_riscv/hdl4se_riscv_sim/cod2mif.c b/examples/hdl4se_riscv/hdl4se_riscv_sim/cod2mif.c new file mode 100644 index 0000000000000000000000000000000000000000..30e3f9be0b76f93ff6ea4043e79a357ec38ac164 --- /dev/null +++ b/examples/hdl4se_riscv/hdl4se_riscv_sim/cod2mif.c @@ -0,0 +1,107 @@ +/* +** HDL4SE: Èí¼þVerilog×ۺϷÂÕæƽ̨ +** Copyright (C) 2021-2021, raoxianhong +** LCOM: ÇáÁ¿¼¶×é¼þ¶ÔÏóÄ£ÐÍ +** Copyright (C) 2021-2021, raoxianhong +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** * Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** * The name of the author may be used to endorse or promote products +** derived from this software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* +* cod2mif.c + 202109080600: rxh, initial version +*/ + +#include "stdlib.h" +#include "stdio.h" +#include "string.h" + +int main(int argc, char * argv[]) +{ + unsigned int addr; + unsigned int RAMSIZE; + unsigned char* data; + if (argc < 4) { + printf("Usage : %s \n", argv[0]); + exit(-1); + } + FILE* pFile = fopen(argv[1], "rt"); + RAMSIZE = atoi(argv[3]); + if (RAMSIZE < 0x10 || RAMSIZE > 16 * 1024 * 1024) { + printf("size %d must between 16 .. 16M\n", RAMSIZE); + exit(-2); + } + if (pFile == NULL) { + printf("File %s can not open\n", argv[1]); + exit(-1); + } + data = (unsigned int*)malloc(RAMSIZE * 4); + addr = 0; + while (!feof(pFile)) { + char line[256]; + fgets(line, 256, pFile); + if (strlen(line) < 2) + break; + if (line[0] == '@') { + sscanf(line + 1, "%08x", &addr); + } + else { + int len; + int i; + unsigned int temp[16]; + if (addr >= RAMSIZE*4 - 16) { + printf("read file failed, address [%08x] overflow(maxaddr = %08x)\n", addr, RAMSIZE*4); + exit(-5); + } + len = sscanf(line, "%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X", + &temp[0], &temp[1], &temp[2], &temp[3], + &temp[4], &temp[5], &temp[6], &temp[7], + &temp[8], &temp[9], &temp[10], &temp[11], + &temp[12], &temp[13], &temp[14], &temp[15]); + for (i = 0; i < len; i++) + data[addr + i] = temp[i]; + addr += len; + } + } + fclose(pFile); + + pFile = fopen(argv[2], "wt"); + if (pFile == NULL) { + printf("Can create file %s\n", argv[2]); + exit(-3); } + fprintf(pFile, "DEPTH = %d;\n", RAMSIZE); + fprintf(pFile, "WIDTH = 32;\n"); + fprintf(pFile, "ADDRESS_RADIX = HEX;\n"); + fprintf(pFile, "DATA_RADIX = HEX;\n"); + fprintf(pFile, "CONTENT\n"); + fprintf(pFile, "BEGIN\n"); + for (addr = 0; addr < RAMSIZE; addr++) { + fprintf(pFile, "%04X : %08X;\n", addr, *(unsigned int *)(data + addr * 4)); + } + fprintf(pFile, "END;\n"); + fclose(pFile); + return 0; +} + diff --git a/examples/hdl4se_riscv/test_code/console.bat b/examples/hdl4se_riscv/test_code/console.bat index b78e4c282199a95a1ddf5f2f1715bded112b0092..375209ab4ea5f0a7250d942228d9b3372a130f60 100644 --- a/examples/hdl4se_riscv/test_code/console.bat +++ b/examples/hdl4se_riscv/test_code/console.bat @@ -1,8 +1,8 @@ -set pathold=%path% -set path=%path%;D:/gitwork/riscv-tools-rv32im/bin;D:/gitwork/riscv-tools-rv32im/cygwin64/bin -riscv32-unknown-elf-gcc -nostdlib -ffunction-sections -fdata-sections -Wl,-Tnostdlib.ld -Wl,--gc-sections console.c csr.S -o test.elf -riscv32-unknown-elf-objcopy test.elf -O ihex test.hex -riscv32-unknown-elf-objcopy test.elf -O verilog test.cod -riscv32-unknown-elf-objdump -D -M no-aliases,numeric test.elf > test.txt -riscv32-unknown-elf-readelf -a test.elf > test.info -set path=%pathold% + +d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-gcc.exe -ffunction-sections -fdata-sections -Wl,-Tnostdlib.ld -Wl,--gc-sections console.c csr.S -o test.elf +d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-objcopy.exe test.elf -O ihex test.hex +d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-objcopy.exe test.elf -O verilog test.cod +d:/gitwork/riscv-tools-rv32im/bin/cod2mif.exe test.cod test.mif 1024 +d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-objdump.exe -D -M no-aliases,numeric test.elf > test.txt +d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-readelf.exe -a test.elf > test.info + diff --git a/examples/hdl4se_riscv/test_code/test.cod b/examples/hdl4se_riscv/test_code/test.cod deleted file mode 100644 index 1ea75564e733a1517f072fd29a999b3ef5f6f7cd..0000000000000000000000000000000000000000 --- a/examples/hdl4se_riscv/test_code/test.cod +++ /dev/null @@ -1,263 +0,0 @@ -@00000000 -37 11 00 00 EF 00 50 29 6F F0 9F FF -@0000000C -13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00 -83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00 -23 A6 E7 EE B7 17 00 00 83 A7 C7 EE 93 F7 17 00 -93 B7 17 00 93 F7 F7 0F 13 85 07 00 03 24 C1 00 -13 01 01 01 67 80 00 00 -@00000054 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00 -83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00 -23 A6 E7 EE B7 17 00 00 03 A7 C7 EE B7 07 01 00 -B3 77 F7 00 93 B7 17 00 93 F7 F7 0F 13 85 07 00 -03 24 C1 00 13 01 01 01 67 80 00 00 -@000000A0 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -B7 17 00 00 83 A7 47 EE 93 87 87 00 03 A7 07 00 -B7 17 00 00 23 A6 E7 EE B7 17 00 00 83 A7 C7 EE -93 F7 17 00 63 90 07 02 B7 17 00 00 83 A7 47 EE -93 87 47 00 03 27 C4 FE 23 A0 E7 00 93 07 00 00 -6F 00 80 00 93 07 F0 FF 13 85 07 00 03 24 C1 01 -13 01 01 02 67 80 00 00 -@00000108 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00 -83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00 -23 A6 E7 EE B7 17 00 00 03 A7 C7 EE B7 07 01 00 -B3 77 F7 00 63 9A 07 00 B7 17 00 00 83 A7 47 EE -83 A7 07 00 6F 00 80 00 93 07 F0 FF 13 85 07 00 -03 24 C1 00 13 01 01 01 67 80 00 00 -@00000164 -13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 -23 26 A4 FE 6F 00 00 03 13 00 00 00 83 27 C4 FE -83 C7 07 00 13 85 07 00 EF F0 5F F1 13 07 05 00 -93 07 F0 FF E3 04 F7 FE 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 83 27 C4 FE 83 C7 07 00 E3 96 07 FC -93 07 00 00 13 85 07 00 83 20 C1 01 03 24 81 01 -13 01 01 02 67 80 00 00 -@000001CC -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 23 2C B4 FC 23 26 04 FE 03 27 84 FD -93 07 10 00 63 C6 E7 00 93 07 00 00 6F 00 80 09 -EF F0 DF F0 23 24 A4 FE 03 27 84 FE 93 07 F0 FF -E3 08 F7 FE 83 27 C4 FE 13 87 17 00 23 26 E4 FE -13 87 07 00 83 27 C4 FD B3 87 E7 00 03 27 84 FE -13 77 F7 0F 23 80 E7 00 13 00 00 00 03 25 84 FE -EF F0 5F E6 13 07 05 00 93 07 F0 FF E3 08 F7 FE -83 27 84 FD 93 87 F7 FF 03 27 C4 FE 63 50 F7 02 -03 27 84 FE 93 07 A0 00 63 0C F7 00 03 27 84 FE -93 07 D0 00 63 06 F7 00 6F F0 9F F8 13 00 00 00 -83 27 C4 FE 03 27 C4 FD B3 07 F7 00 23 80 07 00 -83 27 C4 FE 13 85 07 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 -@000002A4 -13 01 01 FC 23 2E 81 02 13 04 01 04 23 26 A4 FC -23 24 B4 FC 23 24 04 FE 23 22 04 FE 83 27 84 FC -63 DA 07 00 83 27 84 FC B3 07 F0 40 23 24 F4 FC -23 22 04 FE 83 27 84 FC 63 96 07 06 83 27 84 FE -13 87 17 00 23 24 E4 FE 13 87 07 00 83 27 C4 FC -B3 87 E7 00 13 07 00 03 23 80 E7 00 6F 00 80 07 -03 27 84 FC 93 07 A0 00 B3 67 F7 02 13 F7 F7 0F -83 27 84 FE 93 86 17 00 23 24 D4 FE 93 86 07 00 -83 27 C4 FC B3 87 D7 00 13 07 07 03 13 77 F7 0F -23 80 E7 00 03 27 84 FC 93 07 A0 00 B3 47 F7 02 -23 24 F4 FC 83 27 84 FC E3 4C F0 FA 83 27 44 FE -63 82 07 02 83 27 84 FE 13 87 17 00 23 24 E4 FE -13 87 07 00 83 27 C4 FC B3 87 E7 00 13 07 D0 02 -23 80 E7 00 23 26 04 FE 6F 00 C0 06 83 27 84 FE -13 87 F7 FF 83 27 C4 FE B3 07 F7 40 23 20 F4 FE -83 27 C4 FE 03 27 C4 FC B3 07 F7 00 83 C7 07 00 -A3 0F F4 FC 83 27 04 FE 03 27 C4 FC 33 07 F7 00 -83 27 C4 FE 83 26 C4 FC B3 87 F6 00 03 47 07 00 -23 80 E7 00 83 27 04 FE 03 27 C4 FC B3 07 F7 00 -03 47 F4 FD 23 80 E7 00 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 83 27 84 FE 13 D7 F7 01 B3 07 F7 00 -93 D7 17 40 13 87 07 00 83 27 C4 FE E3 C0 E7 F8 -83 27 84 FE 03 27 C4 FC B3 07 F7 00 23 80 07 00 -83 27 84 FE 13 85 07 00 03 24 C1 03 13 01 01 04 -67 80 00 00 -@00000428 -13 01 01 FB 23 26 81 04 13 04 01 05 23 26 A4 FC -23 20 B4 FC 23 22 C4 FC 23 24 D4 FC 93 07 07 00 -A3 0F F4 FA 23 24 04 FE 6F 00 00 09 83 27 04 FC -93 F7 F7 00 23 2E F4 FC 03 27 C4 FD 93 07 90 00 -63 C4 E7 02 83 27 C4 FD 13 F7 F7 0F 83 27 84 FE -83 26 C4 FC B3 87 F6 00 13 07 07 03 13 77 F7 0F -23 80 E7 00 6F 00 40 02 83 27 C4 FD 13 F7 F7 0F -83 27 84 FE 83 26 C4 FC B3 87 F6 00 13 07 77 05 -13 77 F7 0F 23 80 E7 00 83 27 44 FC 93 97 C7 01 -03 27 04 FC 13 58 47 00 33 E8 07 01 83 27 44 FC -93 D8 47 00 23 20 04 FD 23 22 14 FD 83 27 84 FE -93 87 17 00 23 24 F4 FE 83 27 04 FC 03 27 44 FC -B3 E7 E7 00 E3 94 07 F6 6F 00 40 02 83 27 84 FE -13 87 17 00 23 24 E4 FE 13 87 07 00 83 27 C4 FC -B3 87 E7 00 03 47 F4 FB 23 80 E7 00 03 27 84 FE -83 27 84 FC E3 4C F7 FC 23 26 04 FE 6F 00 C0 06 -83 27 84 FE 13 87 F7 FF 83 27 C4 FE B3 07 F7 40 -23 22 F4 FE 83 27 C4 FE 03 27 C4 FC B3 07 F7 00 -83 C7 07 00 A3 01 F4 FE 83 27 44 FE 03 27 C4 FC -33 07 F7 00 83 27 C4 FE 83 26 C4 FC B3 87 F6 00 -03 47 07 00 23 80 E7 00 83 27 44 FE 03 27 C4 FC -B3 07 F7 00 03 47 34 FE 23 80 E7 00 83 27 C4 FE -93 87 17 00 23 26 F4 FE 83 27 84 FE 13 D7 F7 01 -B3 07 F7 00 93 D7 17 40 13 87 07 00 83 27 C4 FE -E3 C0 E7 F8 83 27 84 FE 03 27 C4 FC B3 07 F7 00 -23 80 07 00 83 27 84 FE 13 85 07 00 03 24 C1 04 -13 01 01 05 67 80 00 00 -@000005D0 -13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC -23 2C B4 FC 23 26 04 FE 23 24 04 FE 93 07 10 00 -23 22 F4 FE 6F 00 C0 08 83 27 C4 FD 83 C7 07 00 -23 20 F4 FE 03 27 04 FE 93 07 F0 02 63 D2 E7 04 -03 27 04 FE 93 07 90 03 63 CC E7 02 03 27 84 FE -93 07 07 00 93 97 27 00 B3 87 E7 00 93 97 17 00 -13 87 07 00 83 27 04 FE B3 07 F7 00 93 87 07 FD -23 24 F4 FE 93 07 10 00 23 26 F4 FE 6F 00 80 02 -83 27 C4 FE 63 9E 07 02 03 27 04 FE 93 07 D0 02 -63 1A F7 00 93 07 F0 FF 23 22 F4 FE 93 07 10 00 -23 26 F4 FE 83 27 C4 FD 93 87 17 00 23 2E F4 FC -83 27 C4 FD 83 C7 07 00 E3 98 07 F6 6F 00 80 00 -13 00 00 00 03 27 84 FE 83 27 44 FE B3 07 F7 02 -23 24 F4 FE 83 27 84 FD 63 88 07 00 83 27 84 FD -03 27 C4 FD 23 A0 E7 00 83 27 84 FE 13 85 07 00 -03 24 C1 02 13 01 01 03 67 80 00 00 -@000006CC -13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC -23 2C B4 FC 23 26 04 FE 23 24 04 FE 6F 00 00 0E -83 27 C4 FD 83 C7 07 00 23 22 F4 FE 03 27 44 FE -93 07 F0 02 63 DA E7 02 03 27 44 FE 93 07 90 03 -63 C4 E7 02 93 07 10 00 23 26 F4 FE 83 27 84 FE -13 97 47 00 83 27 44 FE B3 07 F7 00 93 87 07 FD -23 24 F4 FE 6F 00 C0 08 03 27 44 FE 93 07 00 06 -63 DA E7 02 03 27 44 FE 93 07 60 06 63 C4 E7 02 -93 07 10 00 23 26 F4 FE 83 27 84 FE 13 97 47 00 -83 27 44 FE B3 07 F7 00 93 87 97 FA 23 24 F4 FE -6F 00 00 05 03 27 44 FE 93 07 00 04 63 DA E7 02 -03 27 44 FE 93 07 60 04 63 C4 E7 02 93 07 10 00 -23 26 F4 FE 83 27 84 FE 13 97 47 00 83 27 44 FE -B3 07 F7 00 93 87 97 FC 23 24 F4 FE 6F 00 40 01 -83 27 C4 FE 63 94 07 02 93 07 10 00 23 26 F4 FE -83 27 C4 FD 93 87 17 00 23 2E F4 FC 83 27 C4 FD -83 C7 07 00 E3 9E 07 F0 6F 00 80 00 13 00 00 00 -83 27 84 FD 63 88 07 00 83 27 84 FD 03 27 C4 FD -23 A0 E7 00 83 27 84 FE 13 85 07 00 03 24 C1 02 -13 01 01 03 67 80 00 00 -@00000804 -13 01 01 FB 23 26 11 04 23 24 81 04 23 22 21 05 -23 20 31 05 23 2E 41 03 23 2C 51 03 13 04 01 05 -B7 17 00 00 83 A7 87 EE 93 F7 07 FF 23 2A F4 FC -23 2C 04 FC 6F 00 C0 1B 83 27 44 FD 13 89 07 00 -93 09 00 00 93 07 C4 FB 13 07 00 03 93 06 80 00 -93 05 09 00 13 86 09 00 13 85 07 00 EF F0 9F BC -93 07 C4 FB 13 85 07 00 EF F0 9F 8F B7 17 00 00 -13 85 87 E4 EF F0 DF 8E 23 2E 04 FC 6F 00 40 0A -83 27 44 FD 23 26 F4 FC 03 27 C4 FD 83 27 44 FD -33 07 F7 00 B7 17 00 00 83 A7 87 EE 63 7A F7 00 -B7 17 00 00 13 85 C7 E4 EF F0 9F 8B 6F 00 00 05 -83 27 C4 FD 03 27 C4 FC B3 07 F7 00 83 C7 07 00 -13 8A 07 00 93 0A 00 00 93 07 C4 FB 13 07 00 03 -93 06 20 00 93 05 0A 00 13 86 0A 00 13 85 07 00 -EF F0 5F B4 93 07 C4 FB 13 85 07 00 EF F0 5F 87 -B7 17 00 00 13 85 07 E5 EF F0 9F 86 03 27 C4 FD -93 07 70 00 63 18 F7 00 B7 17 00 00 13 85 47 E5 -EF F0 1F 85 83 27 C4 FD 93 87 17 00 23 2E F4 FC -03 27 C4 FD 93 07 F0 00 E3 DC E7 F4 B7 17 00 00 -13 85 87 E5 EF F0 DF 82 23 2E 04 FC 6F 00 80 07 -83 27 44 FD 23 28 F4 FC 83 27 C4 FD 03 27 04 FD -B3 07 F7 00 03 C7 07 00 93 07 F0 01 63 FA E7 02 -83 27 C4 FD 03 27 04 FD B3 07 F7 00 03 C7 07 00 -93 07 E0 07 63 EE E7 00 83 27 C4 FD 03 27 04 FD -B3 07 F7 00 83 C7 07 00 23 0E F4 FA 6F 00 C0 00 -93 07 E0 02 23 0E F4 FA A3 0E 04 FA 93 07 C4 FB -13 85 07 00 EF F0 CF FB 83 27 C4 FD 93 87 17 00 -23 2E F4 FC 03 27 C4 FD 93 07 F0 00 E3 D2 E7 F8 -B7 17 00 00 13 85 C7 E5 EF F0 8F F9 83 27 44 FD -93 87 07 01 23 2A F4 FC 83 27 44 FD 93 F7 F7 0F -63 80 07 02 83 27 84 FD 93 87 17 00 23 2C F4 FC -03 27 84 FD 93 07 F0 00 E3 D0 E7 E4 6F 00 80 00 -13 00 00 00 B7 17 00 00 13 85 07 E6 EF F0 4F F5 -B7 17 00 00 03 27 44 FD 23 A4 E7 EE 13 00 00 00 -83 20 C1 04 03 24 81 04 03 29 41 04 83 29 01 04 -03 2A C1 03 83 2A 81 03 13 01 01 05 67 80 00 00 -@00000A44 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -B7 17 00 00 13 85 47 E6 EF F0 8F F0 B7 17 00 00 -13 85 47 E7 EF F0 CF EF B7 17 00 00 13 85 87 E8 -EF F0 0F EF B7 17 00 00 13 85 C7 E9 EF F0 4F EE -13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01 -67 80 00 00 -@00000A98 -13 01 01 F8 23 2E 11 06 23 2C 81 06 23 2A 21 07 -23 28 31 07 23 26 41 07 23 24 51 07 13 04 01 08 -23 26 A4 F8 23 24 B4 F8 B7 07 00 F0 93 87 07 01 -37 07 3F 3F 13 07 77 70 23 A0 E7 00 B7 17 00 00 -83 A7 47 EE 93 87 07 01 13 07 20 1B 23 A0 E7 00 -EF F0 4F D2 93 07 05 00 63 88 07 00 B7 17 00 00 -13 85 87 EB EF F0 8F E6 EF F0 4F D5 93 07 05 00 -E3 8C 07 FE 93 07 04 F9 93 05 70 02 13 85 07 00 -EF F0 4F EB 13 00 00 00 B7 17 00 00 13 85 C7 EB -EF F0 CF E3 93 07 04 F9 13 85 07 00 EF F0 0F E3 -B7 17 00 00 13 85 07 E6 EF F0 4F E2 03 47 04 F9 -93 07 20 06 63 18 F7 04 93 07 04 F9 93 87 27 00 -93 05 00 00 13 85 07 00 EF F0 1F A7 23 20 A4 FC -83 27 04 FC 63 54 F0 02 B7 F7 FA 02 13 87 07 08 -83 27 04 FC 33 47 F7 02 B7 17 00 00 83 A7 47 EE -93 87 07 01 23 A0 E7 00 6F 00 40 2A EF F0 1F EB -6F 00 C0 29 03 47 04 F9 93 07 40 06 63 1C F7 02 -93 07 04 F9 93 87 27 00 93 05 00 00 13 85 07 00 -EF F0 5F B1 23 22 A4 FC 83 27 44 FC 63 58 F0 00 -03 27 44 FC B7 17 00 00 23 A4 E7 EE EF F0 1F C3 -6F 00 C0 25 03 47 04 F9 93 07 70 07 63 1C F7 0A -93 07 04 F9 93 87 27 00 13 07 C4 FB 93 05 07 00 -13 85 07 00 EF F0 1F AD 23 28 A4 FC 83 27 C4 FB -13 07 C4 FB 93 05 07 00 13 85 07 00 EF F0 9F AB -23 26 A4 FC 83 27 C4 FB 13 07 C4 FB 93 05 07 00 -13 85 07 00 EF F0 1F AA 23 24 A4 FC 03 27 84 FC -93 07 10 00 63 1C F7 00 83 27 04 FD 03 27 C4 FC -13 77 F7 0F 23 80 E7 00 6F 00 40 1E 03 27 84 FC -93 07 20 00 63 1E F7 00 83 27 04 FD 03 27 C4 FC -13 17 07 01 13 57 07 41 23 90 E7 00 6F 00 00 1C -03 27 84 FC 93 07 40 00 63 1A F7 00 83 27 04 FD -03 27 C4 FC 23 A0 E7 00 6F 00 40 1A EF F0 1F DB -6F 00 C0 19 03 47 04 F9 93 07 20 07 63 18 F7 18 -23 2E 04 FC 93 07 04 F9 93 87 27 00 13 07 84 FB -93 05 07 00 13 85 07 00 EF F0 DF A0 23 2C A4 FC -83 27 84 FB 13 07 84 FB 93 05 07 00 13 85 07 00 -EF F0 5F 9F 23 2A A4 FC 03 27 44 FD 93 07 10 00 -63 10 F7 02 83 27 84 FD 83 C7 07 00 23 2E F4 FC -B7 17 00 00 13 85 07 EC EF F0 4F C6 6F 00 80 05 -03 27 44 FD 93 07 20 00 63 10 F7 02 83 27 84 FD -83 97 07 00 23 2E F4 FC B7 17 00 00 13 85 87 EC -EF F0 CF C3 6F 00 00 03 03 27 44 FD 93 07 40 00 -63 10 F7 02 83 27 84 FD 83 A7 07 00 23 2E F4 FC -B7 17 00 00 13 85 07 ED EF F0 4F C1 6F 00 80 00 -EF F0 DF CE 03 27 44 FD 93 07 10 00 63 0E F7 00 -03 27 44 FD 93 07 20 00 63 08 F7 00 03 27 44 FD -93 07 40 00 63 1C F7 0A 83 27 84 FD 13 89 07 00 -93 D7 F7 41 93 89 07 00 93 07 04 F9 13 07 00 03 -93 06 80 00 93 05 09 00 13 86 09 00 13 85 07 00 -EF F0 0F E8 93 07 04 F9 13 85 07 00 EF F0 0F BB -B7 17 00 00 13 85 87 ED EF F0 4F BA 93 07 04 F9 -83 25 C4 FD 13 85 07 00 EF F0 4F CD 93 07 04 F9 -13 85 07 00 EF F0 8F B8 B7 17 00 00 13 85 C7 ED -EF F0 CF B7 83 27 C4 FD 13 8A 07 00 93 D7 F7 41 -93 8A 07 00 83 27 44 FD 93 96 17 00 93 07 04 F9 -13 07 00 03 93 05 0A 00 13 86 0A 00 13 85 07 00 -EF F0 0F E1 93 07 04 F9 13 85 07 00 EF F0 0F B4 -B7 17 00 00 13 85 07 EE EF F0 4F B3 13 00 00 00 -EF F0 4F 9D 93 07 05 00 E3 8C 07 FE 6F F0 5F CA -@00000E48 -20 20 00 00 20 20 20 00 20 00 00 00 2D 20 00 00 -20 20 7C 00 7C 0A 00 00 0A 0D 00 00 20 20 64 20 -3C 61 64 64 72 3E 20 0A 00 00 00 00 20 20 62 20 -3C 62 61 75 64 72 61 74 65 3E 20 0A 00 00 00 00 -20 20 72 20 3C 61 64 64 72 3E 20 3C 77 69 64 74 -68 3E 0A 00 20 20 77 20 3C 61 64 64 72 3E 20 3C -76 61 6C 75 65 3E 20 3C 77 69 64 74 68 3E 0A 00 -3E 3E 00 00 0A 0D 3A 00 63 68 61 72 20 40 00 00 -73 68 6F 72 74 20 40 00 69 6E 74 20 40 00 00 00 -20 3D 20 00 28 00 00 00 29 0A 0D 00 -@00000EE4 -00 01 00 F0 -@00000EE8 -01 00 00 00 diff --git a/examples/hdl4se_riscv/test_code/test.elf b/examples/hdl4se_riscv/test_code/test.elf deleted file mode 100644 index 3165b3d6d569439a3ca0e331cc76c4d7798f2799..0000000000000000000000000000000000000000 Binary files a/examples/hdl4se_riscv/test_code/test.elf and /dev/null differ diff --git a/examples/hdl4se_riscv/test_code/test.hex b/examples/hdl4se_riscv/test_code/test.hex deleted file mode 100644 index 597f434a3be9a9e27878a75be0788b2ec3d10e8c..0000000000000000000000000000000000000000 --- a/examples/hdl4se_riscv/test_code/test.hex +++ /dev/null @@ -1,247 +0,0 @@ -:0C00000037110000EF0050296FF09FFF47 -:10000C00130101FF2326810013040101B71700001F -:10001C0083A747EE9387870003A70700B717000055 -:10002C0023A6E7EEB717000083A7C7EE93F71700D8 -:10003C0093B7170093F7F70F138507000324C1003C -:08004C001301010167800000AF -:10005400130101FF2326810013040101B7170000D7 -:1000640083A747EE9387870003A70700B71700000D -:1000740023A6E7EEB717000003A7C7EEB7070100F2 -:10008400B377F70093B7170093F7F70F13850700BB -:0C0094000324C10013010101678000007B -:1000A000130101FE232E8100130401022326A4FE66 -:1000B000B717000083A747EE9387870003A70700C1 -:1000C000B717000023A6E7EEB717000083A7C7EE17 -:1000D00093F7170063900702B717000083A747EE56 -:1000E000938747000327C4FE23A0E700930700007F -:1000F0006F0080009307F0FF138507000324C10100 -:080100001301010267800000F9 -:10010800130101FF2326810013040101B717000022 -:1001180083A747EE9387870003A70700B717000058 -:1001280023A6E7EEB717000003A7C7EEB70701003D -:10013800B377F700639A0700B717000083A747EE65 -:1001480083A707006F0080009307F0FF138507005F -:0C0158000324C1001301010167800000B6 -:10016400130101FE232E1100232C8100130401022C -:100174002326A4FE6F000003130000008327C4FE9F -:1001840083C7070013850700EFF05FF1130705002D -:100194009307F0FFE304F7FE8327C4FE9387170059 -:1001A4002326F4FE8327C4FE83C70700E39607FCD7 -:1001B40093070000138507008320C10103248101F4 -:0801C400130101026780000035 -:1001CC00130101FD232611022324810213040103D0 -:1001DC00232EA4FC232CB4FC232604FE032784FD2D -:1001EC009307100063C6E700930700006F008009B7 -:1001FC00EFF0DFF02324A4FE032784FE9307F0FF27 -:10020C00E308F7FE8327C4FE138717002326E4FEBA -:10021C00138707008327C4FDB387E700032784FEF9 -:10022C001377F70F2380E70013000000032584FEEB -:10023C00EFF05FE6130705009307F0FFE308F7FE06 -:10024C00832784FD9387F7FF0327C4FE6350F702CF -:10025C00032784FE9307A000630CF700032784FE9A -:10026C009307D0006306F7006FF09FF813000000AF -:10027C008327C4FE0327C4FDB307F70023800700C0 -:10028C008327C4FE138507008320C1020324810247 -:08029C0013010103678000005B -:1002A400130101FC232E8102130401042326A4FC60 -:1002B4002324B4FC232404FE232204FE832784FC89 -:1002C40063DA0700832784FCB307F0402324F4FC9B -:1002D400232204FE832784FC63960706832784FE77 -:1002E400138717002324E4FE138707008327C4FC25 -:1002F400B387E700130700032380E7006F0080073C -:10030400032784FC9307A000B367F70213F7F70FE2 -:10031400832784FE938617002324D4FE9386070044 -:100324008327C4FCB387D700130707031377F70F9A -:100334002380E700032784FC9307A000B347F70258 -:100344002324F4FC832784FCE34CF0FA832744FE43 -:1003540063820702832784FE138717002324E4FEA5 -:10036400138707008327C4FCB387E7001307D00271 -:100374002380E700232604FE6F00C006832784FE43 -:100384001387F7FF8327C4FEB307F7402320F4FE47 -:100394008327C4FE0327C4FCB307F70083C7070001 -:1003A400A30FF4FC832704FE0327C4FC3307F700E0 -:1003B4008327C4FE8326C4FCB387F60003470700E3 -:1003C4002380E700832704FE0327C4FCB307F70058 -:1003D4000347F4FD2380E7008327C4FE93871700B7 -:1003E4002326F4FE832784FE13D7F701B307F7000F -:1003F40093D71740138707008327C4FEE3C0E7F8A9 -:10040400832784FE0327C4FCB307F7002380070077 -:10041400832784FE138507000324C1031301010409 -:0404240067800000ED -:10042800130101FB23268104130401052326A4FCE0 -:100438002320B4FC2322C4FC2324D4FC9307070004 -:10044800A30FF4FA232404FE6F000009832704FC99 -:1004580093F7F700232EF4FC0327C4FD93079000BD -:1004680063C4E7028327C4FD13F7F70F832784FECD -:100478008326C4FCB387F600130707031377F70F27 -:100488002380E7006F0040028327C4FD13F7F70FAE -:10049800832784FE8326C4FCB387F60013077705F9 -:1004A8001377F70F2380E700832744FC9397C7014E -:1004B800032704FC1358470033E80701832744FC4B -:1004C80093D84700232004FD232214FD832784FEAC -:1004D800938717002324F4FE832704FC032744FC96 -:1004E800B3E7E700E39407F66F004002832784FE32 -:1004F800138717002324E4FE138707008327C4FC0F -:10050800B387E7000347F4FB2380E700032784FE53 -:10051800832784FCE34CF7FC232604FE6F00C00607 -:10052800832784FE1387F7FF8327C4FEB307F740AA -:100538002322F4FE8327C4FE0327C4FCB307F70075 -:1005480083C70700A301F4FE832744FE0327C4FCE6 -:100558003307F7008327C4FE8326C4FCB387F6005D -:10056800034707002380E700832744FE0327C4FCD2 -:10057800B307F700034734FE2380E7008327C4FE50 -:10058800938717002326F4FE832784FE13D7F701E9 -:10059800B307F70093D71740138707008327C4FED4 -:1005A800E3C0E7F8832784FE0327C4FCB307F700FA -:1005B80023800700832784FE138507000324C104D2 -:0805C80013010105678000002A -:1005D000130101FD2326810213040103232EA4FC31 -:1005E000232CB4FC232604FE232404FE93071000CE -:1005F0002322F4FE6F00C0088327C4FD83C70700D1 -:100600002320F4FE032704FE9307F00263D2E704DD -:10061000032704FE9307900363CCE702032784FEBD -:100620009307070093972700B387E7009397170076 -:1006300013870700832704FEB307F700938707FD9E -:100640002324F4FE930710002326F4FE6F0080029B -:100650008327C4FE639E0702032704FE9307D0028C -:10066000631AF7009307F0FF2322F4FE93071000AC -:100670002326F4FE8327C4FD93871700232EF4FC62 -:100680008327C4FD83C70700E39807F66F00800047 -:1006900013000000032784FE832744FEB307F702FC -:1006A0002324F4FE832784FD63880700832784FDC9 -:1006B0000327C4FD23A0E700832784FE13850700DA -:0C06C0000324C102130101036780000045 -:1006CC00130101FD2326810213040103232EA4FC34 -:1006DC00232CB4FC232604FE232404FE6F00000EFE -:1006EC008327C4FD83C707002322F4FE032744FE9F -:1006FC009307F00263DAE702032744FE93079003A3 -:10070C0063C4E702930710002326F4FE832784FEBC -:10071C0013974700832744FEB307F700938707FD21 -:10072C002324F4FE6F00C008032744FE9307000641 -:10073C0063DAE702032744FE9307600663C4E7020B -:10074C00930710002326F4FE832784FE139747009B -:10075C00832744FEB307F700938797FA2324F4FE0C -:10076C006F000005032744FE9307000463DAE702D9 -:10077C00032744FE9307600463C4E7029307100049 -:10078C002326F4FE832784FE13974700832744FE19 -:10079C00B307F700938797FC2324F4FE6F00400106 -:1007AC008327C4FE63940702930710002326F4FEEC -:1007BC008327C4FD93871700232EF4FC8327C4FDE5 -:1007CC0083C70700E39E07F06F0080001300000052 -:1007DC00832784FD63880700832784FD0327C4FDDA -:1007EC0023A0E700832784FE138507000324C1029E -:0807FC001301010367800000F6 -:10080400130101FB2326110423248104232221053F -:1008140023203105232E4103232C51031304010506 -:10082400B717000083A787EE93F707FF232AF4FC8A -:10083400232C04FC6F00C01B832744FD138907008D -:10084400930900009307C4FB130700039306800079 -:10085400930509001386090013850700EFF09FBC78 -:100864009307C4FB13850700EFF09F8FB7170000B1 -:10087400138587E4EFF0DF8E232E04FC6F00400A1B -:10088400832744FD2326F4FC0327C4FD832744FD6A -:100894003307F700B717000083A787EE637AF700E2 -:1008A400B71700001385C7E4EFF09F8B6F000005B6 -:1008B4008327C4FD0327C4FCB307F70083C70700DD -:1008C400138A0700930A00009307C4FB130700036D -:1008D4009306200093050A0013860A001385070077 -:1008E400EFF05FB49307C4FB13850700EFF05F8755 -:1008F400B7170000138507E5EFF09F860327C4FDB3 -:10090400930770006318F700B7170000138547E5D5 -:10091400EFF01F858327C4FD93871700232EF4FC73 -:100924000327C4FD9307F000E3DCE7F4B7170000E6 -:10093400138587E5EFF0DF82232E04FC6F00800728 -:10094400832744FD2328F4FC8327C4FD032704FDE7 -:10095400B307F70003C707009307F00163FAE70240 -:100964008327C4FD032704FDB307F70003C707006B -:100974009307E00763EEE7008327C4FD032704FD24 -:10098400B307F70083C70700230EF4FA6F00C00013 -:100994009307E002230EF4FAA30E04FA9307C4FBB0 -:1009A40013850700EFF0CFFB8327C4FD938717005F -:1009B400232EF4FC0327C4FD9307F000E3D2E7F8E9 -:1009C400B71700001385C7E5EFF08FF9832744FDBF -:1009D40093870701232AF4FC832744FD93F7F70F39 -:1009E40063800702832784FD93871700232CF4FC7C -:1009F400032784FD9307F000E3D0E7E46F00800051 -:100A040013000000B7170000138507E6EFF04FF559 -:100A1400B7170000032744FD23A4E7EE13000000EA -:100A24008320C1040324810403294104832901048C -:100A3400032AC103832A810313010105678000008F -:100A4400130101FF23261100232481001304010153 -:100A5400B7170000138547E6EFF08FF0B7170000D3 -:100A6400138547E7EFF0CFEFB7170000138587E84A -:100A7400EFF00FEFB71700001385C7E9EFF04FEE63 -:100A8400130000008320C10003248100130101012D -:040A94006780000077 -:100A9800130101F8232E1106232C8106232A21078E -:100AA800232831072326410723245107130401086B -:100AB8002326A4F82324B4F8B70700F09387070186 -:100AC80037073F3F1307777023A0E700B7170000E9 -:100AD80083A747EE938707011307201B23A0E7008E -:100AE800EFF04FD29307050063880700B71700009F -:100AF800138587EBEFF08FE6EFF04FD593070500EE -:100B0800E38C07FE930704F9930570021385070029 -:100B1800EFF04FEB13000000B71700001385C7EB89 -:100B2800EFF0CFE3930704F913850700EFF00FE325 -:100B3800B7170000138507E6EFF04FE2034704F903 -:100B4800930720066318F704930704F9938727008F -:100B58009305000013850700EFF01FA72320A4FCCE -:100B6800832704FC6354F002B7F7FA0213870708D7 -:100B7800832704FC3347F702B717000083A747EE23 -:100B88009387070123A0E7006F00402AEFF01FEBCF -:100B98006F00C029034704F993074006631CF70256 -:100BA800930704F99387270093050000138507002E -:100BB800EFF05FB12322A4FC832744FC6358F000C4 -:100BC800032744FCB717000023A4E7EEEFF01FC388 -:100BD8006F00C025034704F993077007631CF70AE1 -:100BE800930704F9938727001307C4FB93050700AD -:100BF80013850700EFF01FAD2328A4FC8327C4FB4F -:100C08001307C4FB9305070013850700EFF09FAB9C -:100C18002326A4FC8327C4FB1307C4FB9305070002 -:100C280013850700EFF01FAA2324A4FC032784FCE4 -:100C380093071000631CF700832704FD0327C4FCF7 -:100C48001377F70F2380E7006F00401E032784FC0B -:100C580093072000631EF700832704FD0327C4FCC5 -:100C680013170701135707412390E7006F00001C73 -:100C7800032784FC93074000631AF700832704FDC9 -:100C88000327C4FC23A0E7006F00401AEFF01FDB26 -:100C98006F00C019034704F9930720076318F71872 -:100CA800232E04FC930704F993872700130784FB7A -:100CB8009305070013850700EFF0DFA0232CA4FCA1 -:100CC800832784FB130784FB93050700138507001C -:100CD800EFF05F9F232AA4FC032744FD930710002D -:100CE8006310F702832784FD83C70700232EF4FCD3 -:100CF800B7170000138507ECEFF04FC66F008005AB -:100D0800032744FD930720006310F702832784FD1F -:100D180083970700232EF4FCB7170000138587EC90 -:100D2800EFF0CFC36F000003032744FD9307400093 -:100D38006310F702832784FD83A70700232EF4FCA2 -:100D4800B7170000138507EDEFF04FC16F00800063 -:100D5800EFF0DFCE032744FD93071000630EF70082 -:100D6800032744FD930720006308F700032744FD89 -:100D780093074000631CF70A832784FD1389070043 -:100D880093D7F74193890700930704F913070003E2 -:100D98009306800093050900138609001385070050 -:100DA800EFF00FE8930704F913850700EFF00FBB86 -:100DB800B7170000138587EDEFF04FBA930704F9D2 -:100DC8008325C4FD13850700EFF04FCD930704F981 -:100DD80013850700EFF08FB8B71700001385C7ED2C -:100DE800EFF0CFB78327C4FD138A070093D7F741E5 -:100DF800938A0700832744FD93961700930704F905 -:100E08001307000393050A0013860A0013850700D9 -:100E1800EFF00FE1930704F913850700EFF00FB423 -:100E2800B7170000138507EEEFF04FB3130000006B -:100E3800EFF04F9D93070500E38C07FE6FF05FCA44 -:100E48002020000020202000200000002D2000008D -:100E580020207C007C0A00000A0D0000202064206D -:100E68003C616464723E200A000000002020622079 -:100E78003C62617564726174653E200A000000007E -:100E8800202072203C616464723E203C776964745F -:100E9800683E0A00202077203C616464723E203C52 -:100EA80076616C75653E203C77696474683E0A001B -:100EB8003E3E00000A0D3A0063686172204000005F -:100EC80073686F7274204000696E742040000000DF -:0C0ED800203D200028000000290A0D0029 -:040EE400000100F019 -:040EE8000100000005 -:00000001FF diff --git a/examples/hdl4se_riscv/test_code/test.mif b/examples/hdl4se_riscv/test_code/test.mif deleted file mode 100644 index a7e231d3e38d5e8e444f2f0ea7cd9431782fdd5c..0000000000000000000000000000000000000000 --- a/examples/hdl4se_riscv/test_code/test.mif +++ /dev/null @@ -1,1031 +0,0 @@ -DEPTH = 1024; -WIDTH = 32; -ADDRESS_RADIX = HEX; -DATA_RADIX = HEX; -CONTENT -BEGIN -0000 : 00001137; -0001 : 295000EF; -0002 : FF9FF06F; -0003 : FF010113; -0004 : 00812623; -0005 : 01010413; -0006 : 000017B7; -0007 : EE47A783; -0008 : 00878793; -0009 : 0007A703; -000A : 000017B7; -000B : EEE7A623; -000C : 000017B7; -000D : EEC7A783; -000E : 0017F793; -000F : 0017B793; -0010 : 0FF7F793; -0011 : 00078513; -0012 : 00C12403; -0013 : 01010113; -0014 : 00008067; -0015 : FF010113; -0016 : 00812623; -0017 : 01010413; -0018 : 000017B7; -0019 : EE47A783; -001A : 00878793; -001B : 0007A703; -001C : 000017B7; -001D : EEE7A623; -001E : 000017B7; -001F : EEC7A703; -0020 : 000107B7; -0021 : 00F777B3; -0022 : 0017B793; -0023 : 0FF7F793; -0024 : 00078513; -0025 : 00C12403; -0026 : 01010113; -0027 : 00008067; -0028 : FE010113; -0029 : 00812E23; -002A : 02010413; -002B : FEA42623; -002C : 000017B7; -002D : EE47A783; -002E : 00878793; -002F : 0007A703; -0030 : 000017B7; -0031 : EEE7A623; -0032 : 000017B7; -0033 : EEC7A783; -0034 : 0017F793; -0035 : 02079063; -0036 : 000017B7; -0037 : EE47A783; -0038 : 00478793; -0039 : FEC42703; -003A : 00E7A023; -003B : 00000793; -003C : 0080006F; -003D : FFF00793; -003E : 00078513; -003F : 01C12403; -0040 : 02010113; -0041 : 00008067; -0042 : FF010113; -0043 : 00812623; -0044 : 01010413; -0045 : 000017B7; -0046 : EE47A783; -0047 : 00878793; -0048 : 0007A703; -0049 : 000017B7; -004A : EEE7A623; -004B : 000017B7; -004C : EEC7A703; -004D : 000107B7; -004E : 00F777B3; -004F : 00079A63; -0050 : 000017B7; -0051 : EE47A783; -0052 : 0007A783; -0053 : 0080006F; -0054 : FFF00793; -0055 : 00078513; -0056 : 00C12403; -0057 : 01010113; -0058 : 00008067; -0059 : FE010113; -005A : 00112E23; -005B : 00812C23; -005C : 02010413; -005D : FEA42623; -005E : 0300006F; -005F : 00000013; -0060 : FEC42783; -0061 : 0007C783; -0062 : 00078513; -0063 : F15FF0EF; -0064 : 00050713; -0065 : FFF00793; -0066 : FEF704E3; -0067 : FEC42783; -0068 : 00178793; -0069 : FEF42623; -006A : FEC42783; -006B : 0007C783; -006C : FC0796E3; -006D : 00000793; -006E : 00078513; -006F : 01C12083; -0070 : 01812403; -0071 : 02010113; -0072 : 00008067; -0073 : FD010113; -0074 : 02112623; -0075 : 02812423; -0076 : 03010413; -0077 : FCA42E23; -0078 : FCB42C23; -0079 : FE042623; -007A : FD842703; -007B : 00100793; -007C : 00E7C663; -007D : 00000793; -007E : 0980006F; -007F : F0DFF0EF; -0080 : FEA42423; -0081 : FE842703; -0082 : FFF00793; -0083 : FEF708E3; -0084 : FEC42783; -0085 : 00178713; -0086 : FEE42623; -0087 : 00078713; -0088 : FDC42783; -0089 : 00E787B3; -008A : FE842703; -008B : 0FF77713; -008C : 00E78023; -008D : 00000013; -008E : FE842503; -008F : E65FF0EF; -0090 : 00050713; -0091 : FFF00793; -0092 : FEF708E3; -0093 : FD842783; -0094 : FFF78793; -0095 : FEC42703; -0096 : 02F75063; -0097 : FE842703; -0098 : 00A00793; -0099 : 00F70C63; -009A : FE842703; -009B : 00D00793; -009C : 00F70663; -009D : F89FF06F; -009E : 00000013; -009F : FEC42783; -00A0 : FDC42703; -00A1 : 00F707B3; -00A2 : 00078023; -00A3 : FEC42783; -00A4 : 00078513; -00A5 : 02C12083; -00A6 : 02812403; -00A7 : 03010113; -00A8 : 00008067; -00A9 : FC010113; -00AA : 02812E23; -00AB : 04010413; -00AC : FCA42623; -00AD : FCB42423; -00AE : FE042423; -00AF : FE042223; -00B0 : FC842783; -00B1 : 0007DA63; -00B2 : FC842783; -00B3 : 40F007B3; -00B4 : FCF42423; -00B5 : FE042223; -00B6 : FC842783; -00B7 : 06079663; -00B8 : FE842783; -00B9 : 00178713; -00BA : FEE42423; -00BB : 00078713; -00BC : FCC42783; -00BD : 00E787B3; -00BE : 03000713; -00BF : 00E78023; -00C0 : 0780006F; -00C1 : FC842703; -00C2 : 00A00793; -00C3 : 02F767B3; -00C4 : 0FF7F713; -00C5 : FE842783; -00C6 : 00178693; -00C7 : FED42423; -00C8 : 00078693; -00C9 : FCC42783; -00CA : 00D787B3; -00CB : 03070713; -00CC : 0FF77713; -00CD : 00E78023; -00CE : FC842703; -00CF : 00A00793; -00D0 : 02F747B3; -00D1 : FCF42423; -00D2 : FC842783; -00D3 : FAF04CE3; -00D4 : FE442783; -00D5 : 02078263; -00D6 : FE842783; -00D7 : 00178713; -00D8 : FEE42423; -00D9 : 00078713; -00DA : FCC42783; -00DB : 00E787B3; -00DC : 02D00713; -00DD : 00E78023; -00DE : FE042623; -00DF : 06C0006F; -00E0 : FE842783; -00E1 : FFF78713; -00E2 : FEC42783; -00E3 : 40F707B3; -00E4 : FEF42023; -00E5 : FEC42783; -00E6 : FCC42703; -00E7 : 00F707B3; -00E8 : 0007C783; -00E9 : FCF40FA3; -00EA : FE042783; -00EB : FCC42703; -00EC : 00F70733; -00ED : FEC42783; -00EE : FCC42683; -00EF : 00F687B3; -00F0 : 00074703; -00F1 : 00E78023; -00F2 : FE042783; -00F3 : FCC42703; -00F4 : 00F707B3; -00F5 : FDF44703; -00F6 : 00E78023; -00F7 : FEC42783; -00F8 : 00178793; -00F9 : FEF42623; -00FA : FE842783; -00FB : 01F7D713; -00FC : 00F707B3; -00FD : 4017D793; -00FE : 00078713; -00FF : FEC42783; -0100 : F8E7C0E3; -0101 : FE842783; -0102 : FCC42703; -0103 : 00F707B3; -0104 : 00078023; -0105 : FE842783; -0106 : 00078513; -0107 : 03C12403; -0108 : 04010113; -0109 : 00008067; -010A : FB010113; -010B : 04812623; -010C : 05010413; -010D : FCA42623; -010E : FCB42023; -010F : FCC42223; -0110 : FCD42423; -0111 : 00070793; -0112 : FAF40FA3; -0113 : FE042423; -0114 : 0900006F; -0115 : FC042783; -0116 : 00F7F793; -0117 : FCF42E23; -0118 : FDC42703; -0119 : 00900793; -011A : 02E7C463; -011B : FDC42783; -011C : 0FF7F713; -011D : FE842783; -011E : FCC42683; -011F : 00F687B3; -0120 : 03070713; -0121 : 0FF77713; -0122 : 00E78023; -0123 : 0240006F; -0124 : FDC42783; -0125 : 0FF7F713; -0126 : FE842783; -0127 : FCC42683; -0128 : 00F687B3; -0129 : 05770713; -012A : 0FF77713; -012B : 00E78023; -012C : FC442783; -012D : 01C79793; -012E : FC042703; -012F : 00475813; -0130 : 0107E833; -0131 : FC442783; -0132 : 0047D893; -0133 : FD042023; -0134 : FD142223; -0135 : FE842783; -0136 : 00178793; -0137 : FEF42423; -0138 : FC042783; -0139 : FC442703; -013A : 00E7E7B3; -013B : F60794E3; -013C : 0240006F; -013D : FE842783; -013E : 00178713; -013F : FEE42423; -0140 : 00078713; -0141 : FCC42783; -0142 : 00E787B3; -0143 : FBF44703; -0144 : 00E78023; -0145 : FE842703; -0146 : FC842783; -0147 : FCF74CE3; -0148 : FE042623; -0149 : 06C0006F; -014A : FE842783; -014B : FFF78713; -014C : FEC42783; -014D : 40F707B3; -014E : FEF42223; -014F : FEC42783; -0150 : FCC42703; -0151 : 00F707B3; -0152 : 0007C783; -0153 : FEF401A3; -0154 : FE442783; -0155 : FCC42703; -0156 : 00F70733; -0157 : FEC42783; -0158 : FCC42683; -0159 : 00F687B3; -015A : 00074703; -015B : 00E78023; -015C : FE442783; -015D : FCC42703; -015E : 00F707B3; -015F : FE344703; -0160 : 00E78023; -0161 : FEC42783; -0162 : 00178793; -0163 : FEF42623; -0164 : FE842783; -0165 : 01F7D713; -0166 : 00F707B3; -0167 : 4017D793; -0168 : 00078713; -0169 : FEC42783; -016A : F8E7C0E3; -016B : FE842783; -016C : FCC42703; -016D : 00F707B3; -016E : 00078023; -016F : FE842783; -0170 : 00078513; -0171 : 04C12403; -0172 : 05010113; -0173 : 00008067; -0174 : FD010113; -0175 : 02812623; -0176 : 03010413; -0177 : FCA42E23; -0178 : FCB42C23; -0179 : FE042623; -017A : FE042423; -017B : 00100793; -017C : FEF42223; -017D : 08C0006F; -017E : FDC42783; -017F : 0007C783; -0180 : FEF42023; -0181 : FE042703; -0182 : 02F00793; -0183 : 04E7D263; -0184 : FE042703; -0185 : 03900793; -0186 : 02E7CC63; -0187 : FE842703; -0188 : 00070793; -0189 : 00279793; -018A : 00E787B3; -018B : 00179793; -018C : 00078713; -018D : FE042783; -018E : 00F707B3; -018F : FD078793; -0190 : FEF42423; -0191 : 00100793; -0192 : FEF42623; -0193 : 0280006F; -0194 : FEC42783; -0195 : 02079E63; -0196 : FE042703; -0197 : 02D00793; -0198 : 00F71A63; -0199 : FFF00793; -019A : FEF42223; -019B : 00100793; -019C : FEF42623; -019D : FDC42783; -019E : 00178793; -019F : FCF42E23; -01A0 : FDC42783; -01A1 : 0007C783; -01A2 : F60798E3; -01A3 : 0080006F; -01A4 : 00000013; -01A5 : FE842703; -01A6 : FE442783; -01A7 : 02F707B3; -01A8 : FEF42423; -01A9 : FD842783; -01AA : 00078863; -01AB : FD842783; -01AC : FDC42703; -01AD : 00E7A023; -01AE : FE842783; -01AF : 00078513; -01B0 : 02C12403; -01B1 : 03010113; -01B2 : 00008067; -01B3 : FD010113; -01B4 : 02812623; -01B5 : 03010413; -01B6 : FCA42E23; -01B7 : FCB42C23; -01B8 : FE042623; -01B9 : FE042423; -01BA : 0E00006F; -01BB : FDC42783; -01BC : 0007C783; -01BD : FEF42223; -01BE : FE442703; -01BF : 02F00793; -01C0 : 02E7DA63; -01C1 : FE442703; -01C2 : 03900793; -01C3 : 02E7C463; -01C4 : 00100793; -01C5 : FEF42623; -01C6 : FE842783; -01C7 : 00479713; -01C8 : FE442783; -01C9 : 00F707B3; -01CA : FD078793; -01CB : FEF42423; -01CC : 08C0006F; -01CD : FE442703; -01CE : 06000793; -01CF : 02E7DA63; -01D0 : FE442703; -01D1 : 06600793; -01D2 : 02E7C463; -01D3 : 00100793; -01D4 : FEF42623; -01D5 : FE842783; -01D6 : 00479713; -01D7 : FE442783; -01D8 : 00F707B3; -01D9 : FA978793; -01DA : FEF42423; -01DB : 0500006F; -01DC : FE442703; -01DD : 04000793; -01DE : 02E7DA63; -01DF : FE442703; -01E0 : 04600793; -01E1 : 02E7C463; -01E2 : 00100793; -01E3 : FEF42623; -01E4 : FE842783; -01E5 : 00479713; -01E6 : FE442783; -01E7 : 00F707B3; -01E8 : FC978793; -01E9 : FEF42423; -01EA : 0140006F; -01EB : FEC42783; -01EC : 02079463; -01ED : 00100793; -01EE : FEF42623; -01EF : FDC42783; -01F0 : 00178793; -01F1 : FCF42E23; -01F2 : FDC42783; -01F3 : 0007C783; -01F4 : F0079EE3; -01F5 : 0080006F; -01F6 : 00000013; -01F7 : FD842783; -01F8 : 00078863; -01F9 : FD842783; -01FA : FDC42703; -01FB : 00E7A023; -01FC : FE842783; -01FD : 00078513; -01FE : 02C12403; -01FF : 03010113; -0200 : 00008067; -0201 : FB010113; -0202 : 04112623; -0203 : 04812423; -0204 : 05212223; -0205 : 05312023; -0206 : 03412E23; -0207 : 03512C23; -0208 : 05010413; -0209 : 000017B7; -020A : EE87A783; -020B : FF07F793; -020C : FCF42A23; -020D : FC042C23; -020E : 1BC0006F; -020F : FD442783; -0210 : 00078913; -0211 : 00000993; -0212 : FBC40793; -0213 : 03000713; -0214 : 00800693; -0215 : 00090593; -0216 : 00098613; -0217 : 00078513; -0218 : BC9FF0EF; -0219 : FBC40793; -021A : 00078513; -021B : 8F9FF0EF; -021C : 000017B7; -021D : E4878513; -021E : 8EDFF0EF; -021F : FC042E23; -0220 : 0A40006F; -0221 : FD442783; -0222 : FCF42623; -0223 : FDC42703; -0224 : FD442783; -0225 : 00F70733; -0226 : 000017B7; -0227 : EE87A783; -0228 : 00F77A63; -0229 : 000017B7; -022A : E4C78513; -022B : 8B9FF0EF; -022C : 0500006F; -022D : FDC42783; -022E : FCC42703; -022F : 00F707B3; -0230 : 0007C783; -0231 : 00078A13; -0232 : 00000A93; -0233 : FBC40793; -0234 : 03000713; -0235 : 00200693; -0236 : 000A0593; -0237 : 000A8613; -0238 : 00078513; -0239 : B45FF0EF; -023A : FBC40793; -023B : 00078513; -023C : 875FF0EF; -023D : 000017B7; -023E : E5078513; -023F : 869FF0EF; -0240 : FDC42703; -0241 : 00700793; -0242 : 00F71863; -0243 : 000017B7; -0244 : E5478513; -0245 : 851FF0EF; -0246 : FDC42783; -0247 : 00178793; -0248 : FCF42E23; -0249 : FDC42703; -024A : 00F00793; -024B : F4E7DCE3; -024C : 000017B7; -024D : E5878513; -024E : 82DFF0EF; -024F : FC042E23; -0250 : 0780006F; -0251 : FD442783; -0252 : FCF42823; -0253 : FDC42783; -0254 : FD042703; -0255 : 00F707B3; -0256 : 0007C703; -0257 : 01F00793; -0258 : 02E7FA63; -0259 : FDC42783; -025A : FD042703; -025B : 00F707B3; -025C : 0007C703; -025D : 07E00793; -025E : 00E7EE63; -025F : FDC42783; -0260 : FD042703; -0261 : 00F707B3; -0262 : 0007C783; -0263 : FAF40E23; -0264 : 00C0006F; -0265 : 02E00793; -0266 : FAF40E23; -0267 : FA040EA3; -0268 : FBC40793; -0269 : 00078513; -026A : FBCFF0EF; -026B : FDC42783; -026C : 00178793; -026D : FCF42E23; -026E : FDC42703; -026F : 00F00793; -0270 : F8E7D2E3; -0271 : 000017B7; -0272 : E5C78513; -0273 : F98FF0EF; -0274 : FD442783; -0275 : 01078793; -0276 : FCF42A23; -0277 : FD442783; -0278 : 0FF7F793; -0279 : 02078063; -027A : FD842783; -027B : 00178793; -027C : FCF42C23; -027D : FD842703; -027E : 00F00793; -027F : E4E7D0E3; -0280 : 0080006F; -0281 : 00000013; -0282 : 000017B7; -0283 : E6078513; -0284 : F54FF0EF; -0285 : 000017B7; -0286 : FD442703; -0287 : EEE7A423; -0288 : 00000013; -0289 : 04C12083; -028A : 04812403; -028B : 04412903; -028C : 04012983; -028D : 03C12A03; -028E : 03812A83; -028F : 05010113; -0290 : 00008067; -0291 : FF010113; -0292 : 00112623; -0293 : 00812423; -0294 : 01010413; -0295 : 000017B7; -0296 : E6478513; -0297 : F08FF0EF; -0298 : 000017B7; -0299 : E7478513; -029A : EFCFF0EF; -029B : 000017B7; -029C : E8878513; -029D : EF0FF0EF; -029E : 000017B7; -029F : E9C78513; -02A0 : EE4FF0EF; -02A1 : 00000013; -02A2 : 00C12083; -02A3 : 00812403; -02A4 : 01010113; -02A5 : 00008067; -02A6 : F8010113; -02A7 : 06112E23; -02A8 : 06812C23; -02A9 : 07212A23; -02AA : 07312823; -02AB : 07412623; -02AC : 07512423; -02AD : 08010413; -02AE : F8A42623; -02AF : F8B42423; -02B0 : F00007B7; -02B1 : 01078793; -02B2 : 3F3F0737; -02B3 : 70770713; -02B4 : 00E7A023; -02B5 : 000017B7; -02B6 : EE47A783; -02B7 : 01078793; -02B8 : 1B200713; -02B9 : 00E7A023; -02BA : D24FF0EF; -02BB : 00050793; -02BC : 00078863; -02BD : 000017B7; -02BE : EB878513; -02BF : E68FF0EF; -02C0 : D54FF0EF; -02C1 : 00050793; -02C2 : FE078CE3; -02C3 : F9040793; -02C4 : 02700593; -02C5 : 00078513; -02C6 : EB4FF0EF; -02C7 : 00000013; -02C8 : 000017B7; -02C9 : EBC78513; -02CA : E3CFF0EF; -02CB : F9040793; -02CC : 00078513; -02CD : E30FF0EF; -02CE : 000017B7; -02CF : E6078513; -02D0 : E24FF0EF; -02D1 : F9044703; -02D2 : 06200793; -02D3 : 04F71863; -02D4 : F9040793; -02D5 : 00278793; -02D6 : 00000593; -02D7 : 00078513; -02D8 : A71FF0EF; -02D9 : FCA42023; -02DA : FC042783; -02DB : 02F05463; -02DC : 02FAF7B7; -02DD : 08078713; -02DE : FC042783; -02DF : 02F74733; -02E0 : 000017B7; -02E1 : EE47A783; -02E2 : 01078793; -02E3 : 00E7A023; -02E4 : 2A40006F; -02E5 : EB1FF0EF; -02E6 : 29C0006F; -02E7 : F9044703; -02E8 : 06400793; -02E9 : 02F71C63; -02EA : F9040793; -02EB : 00278793; -02EC : 00000593; -02ED : 00078513; -02EE : B15FF0EF; -02EF : FCA42223; -02F0 : FC442783; -02F1 : 00F05863; -02F2 : FC442703; -02F3 : 000017B7; -02F4 : EEE7A423; -02F5 : C31FF0EF; -02F6 : 25C0006F; -02F7 : F9044703; -02F8 : 07700793; -02F9 : 0AF71C63; -02FA : F9040793; -02FB : 00278793; -02FC : FBC40713; -02FD : 00070593; -02FE : 00078513; -02FF : AD1FF0EF; -0300 : FCA42823; -0301 : FBC42783; -0302 : FBC40713; -0303 : 00070593; -0304 : 00078513; -0305 : AB9FF0EF; -0306 : FCA42623; -0307 : FBC42783; -0308 : FBC40713; -0309 : 00070593; -030A : 00078513; -030B : AA1FF0EF; -030C : FCA42423; -030D : FC842703; -030E : 00100793; -030F : 00F71C63; -0310 : FD042783; -0311 : FCC42703; -0312 : 0FF77713; -0313 : 00E78023; -0314 : 1E40006F; -0315 : FC842703; -0316 : 00200793; -0317 : 00F71E63; -0318 : FD042783; -0319 : FCC42703; -031A : 01071713; -031B : 41075713; -031C : 00E79023; -031D : 1C00006F; -031E : FC842703; -031F : 00400793; -0320 : 00F71A63; -0321 : FD042783; -0322 : FCC42703; -0323 : 00E7A023; -0324 : 1A40006F; -0325 : DB1FF0EF; -0326 : 19C0006F; -0327 : F9044703; -0328 : 07200793; -0329 : 18F71863; -032A : FC042E23; -032B : F9040793; -032C : 00278793; -032D : FB840713; -032E : 00070593; -032F : 00078513; -0330 : A0DFF0EF; -0331 : FCA42C23; -0332 : FB842783; -0333 : FB840713; -0334 : 00070593; -0335 : 00078513; -0336 : 9F5FF0EF; -0337 : FCA42A23; -0338 : FD442703; -0339 : 00100793; -033A : 02F71063; -033B : FD842783; -033C : 0007C783; -033D : FCF42E23; -033E : 000017B7; -033F : EC078513; -0340 : C64FF0EF; -0341 : 0580006F; -0342 : FD442703; -0343 : 00200793; -0344 : 02F71063; -0345 : FD842783; -0346 : 00079783; -0347 : FCF42E23; -0348 : 000017B7; -0349 : EC878513; -034A : C3CFF0EF; -034B : 0300006F; -034C : FD442703; -034D : 00400793; -034E : 02F71063; -034F : FD842783; -0350 : 0007A783; -0351 : FCF42E23; -0352 : 000017B7; -0353 : ED078513; -0354 : C14FF0EF; -0355 : 0080006F; -0356 : CEDFF0EF; -0357 : FD442703; -0358 : 00100793; -0359 : 00F70E63; -035A : FD442703; -035B : 00200793; -035C : 00F70863; -035D : FD442703; -035E : 00400793; -035F : 0AF71C63; -0360 : FD842783; -0361 : 00078913; -0362 : 41F7D793; -0363 : 00078993; -0364 : F9040793; -0365 : 03000713; -0366 : 00800693; -0367 : 00090593; -0368 : 00098613; -0369 : 00078513; -036A : E80FF0EF; -036B : F9040793; -036C : 00078513; -036D : BB0FF0EF; -036E : 000017B7; -036F : ED878513; -0370 : BA4FF0EF; -0371 : F9040793; -0372 : FDC42583; -0373 : 00078513; -0374 : CD4FF0EF; -0375 : F9040793; -0376 : 00078513; -0377 : B88FF0EF; -0378 : 000017B7; -0379 : EDC78513; -037A : B7CFF0EF; -037B : FDC42783; -037C : 00078A13; -037D : 41F7D793; -037E : 00078A93; -037F : FD442783; -0380 : 00179693; -0381 : F9040793; -0382 : 03000713; -0383 : 000A0593; -0384 : 000A8613; -0385 : 00078513; -0386 : E10FF0EF; -0387 : F9040793; -0388 : 00078513; -0389 : B40FF0EF; -038A : 000017B7; -038B : EE078513; -038C : B34FF0EF; -038D : 00000013; -038E : 9D4FF0EF; -038F : 00050793; -0390 : FE078CE3; -0391 : CA5FF06F; -0392 : 00002020; -0393 : 00202020; -0394 : 00000020; -0395 : 0000202D; -0396 : 007C2020; -0397 : 00000A7C; -0398 : 00000D0A; -0399 : 20642020; -039A : 6464613C; -039B : 0A203E72; -039C : 00000000; -039D : 20622020; -039E : 7561623C; -039F : 74617264; -03A0 : 0A203E65; -03A1 : 00000000; -03A2 : 20722020; -03A3 : 6464613C; -03A4 : 3C203E72; -03A5 : 74646977; -03A6 : 000A3E68; -03A7 : 20772020; -03A8 : 6464613C; -03A9 : 3C203E72; -03AA : 756C6176; -03AB : 3C203E65; -03AC : 74646977; -03AD : 000A3E68; -03AE : 00003E3E; -03AF : 003A0D0A; -03B0 : 72616863; -03B1 : 00004020; -03B2 : 726F6873; -03B3 : 00402074; -03B4 : 20746E69; -03B5 : 00000040; -03B6 : 00203D20; -03B7 : 00000028; -03B8 : 000D0A29; -03B9 : F0000100; -03BA : 00000001; -03BB : 00000001; -03BC : CDCDCDCD; -03BD : CDCDCDCD; -03BE : CDCDCDCD; -03BF : CDCDCDCD; -03C0 : CDCDCDCD; -03C1 : CDCDCDCD; -03C2 : CDCDCDCD; -03C3 : CDCDCDCD; -03C4 : CDCDCDCD; -03C5 : CDCDCDCD; -03C6 : CDCDCDCD; -03C7 : CDCDCDCD; -03C8 : CDCDCDCD; -03C9 : CDCDCDCD; -03CA : CDCDCDCD; -03CB : CDCDCDCD; -03CC : CDCDCDCD; -03CD : CDCDCDCD; -03CE : CDCDCDCD; -03CF : CDCDCDCD; -03D0 : CDCDCDCD; -03D1 : CDCDCDCD; -03D2 : CDCDCDCD; -03D3 : CDCDCDCD; -03D4 : CDCDCDCD; -03D5 : CDCDCDCD; -03D6 : CDCDCDCD; -03D7 : CDCDCDCD; -03D8 : CDCDCDCD; -03D9 : CDCDCDCD; -03DA : CDCDCDCD; -03DB : CDCDCDCD; -03DC : CDCDCDCD; -03DD : CDCDCDCD; -03DE : CDCDCDCD; -03DF : CDCDCDCD; -03E0 : CDCDCDCD; -03E1 : CDCDCDCD; -03E2 : CDCDCDCD; -03E3 : CDCDCDCD; -03E4 : CDCDCDCD; -03E5 : CDCDCDCD; -03E6 : CDCDCDCD; -03E7 : CDCDCDCD; -03E8 : CDCDCDCD; -03E9 : CDCDCDCD; -03EA : CDCDCDCD; -03EB : CDCDCDCD; -03EC : CDCDCDCD; -03ED : CDCDCDCD; -03EE : CDCDCDCD; -03EF : CDCDCDCD; -03F0 : CDCDCDCD; -03F1 : CDCDCDCD; -03F2 : CDCDCDCD; -03F3 : CDCDCDCD; -03F4 : CDCDCDCD; -03F5 : CDCDCDCD; -03F6 : CDCDCDCD; -03F7 : CDCDCDCD; -03F8 : CDCDCDCD; -03F9 : CDCDCDCD; -03FA : CDCDCDCD; -03FB : CDCDCDCD; -03FC : CDCDCDCD; -03FD : CDCDCDCD; -03FE : CDCDCDCD; -03FF : CDCDCDCD; -END; diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/gui_handlers.wdf b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000000000000000000000000000000000000..36c04d57fd53a1081b252755838a035bb8f95c47 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/gui_handlers.wdf @@ -0,0 +1,22 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6577697077697a6172645f6372656174655f6e65775f617869345f69705f6372656174655f61786934:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f69705f7061636b616765725f77697a617264:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73796e74685f73657474696e6773:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f637573746f6d5f636f6d6d616e6473:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f73657474696e6773:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72746c6f7074696f6e7370616e656c5f73656c6563745f746f705f6d6f64756c655f6f665f796f75725f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73656c656374746f706d6f64756c656469616c6f675f73656c6563745f746f705f6d6f64756c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:32:00:00 +eof:2001440325 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/java_command_handlers.wdf b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/java_command_handlers.wdf new file mode 100644 index 0000000000000000000000000000000000000000..a4e895a4946b9c22a5a2a28be7d9d2849e29daf4 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/java_command_handlers.wdf @@ -0,0 +1,8 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637265617465626c6f636b64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657277697a61726468616e646c6572:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:32:00:00 +eof:944231214 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/project.wpc b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/project.wpc new file mode 100644 index 0000000000000000000000000000000000000000..9b342093142bd1b298b4af63bdebdead3a3ef56e --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/synthesis.wdf b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/synthesis.wdf new file mode 100644 index 0000000000000000000000000000000000000000..f5035ed2c8426eae3e42c5aeb81df8171e07739d --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/synthesis.wdf @@ -0,0 +1,43 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b3730746662763438342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:72697363765f636f7265:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c:00:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313873:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313133342e3932324d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:302e3030304d42:00:00 +eof:3660370712 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/synthesis_details.wdf b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/synthesis_details.wdf new file mode 100644 index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/webtalk_pa.xml b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000000000000000000000000000000000000..266ab9b245539ced9b1fb0b77c96e8f379fa4076 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/webtalk_pa.xml @@ -0,0 +1,56 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.hw/project_2.lpr b/examples/hdl4se_riscv/z7/project_2/project_2.hw/project_2.lpr new file mode 100644 index 0000000000000000000000000000000000000000..e265fe105938e52b36b341502956af28128becc6 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.hw/project_2.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/.jobs/vrs_config_1.xml b/examples/hdl4se_riscv/z7/project_2/project_2.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000000000000000000000000000000000000..a6879f4df102d7e97ea7179b7f6a15445bdb83c0 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/.jobs/vrs_config_2.xml b/examples/hdl4se_riscv/z7/project_2/project_2.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000000000000000000000000000000000000..a797caa13b2add548b86a19380f446da2449f315 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.Vivado_Implementation.queue.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.init_design.begin.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000000000000000000000000000000000000..25078e8469132e72d60b814cc19f3c0f9a46e011 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.init_design.end.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.opt_design.begin.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000000000000000000000000000000000000..25078e8469132e72d60b814cc19f3c0f9a46e011 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.opt_design.end.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.phys_opt_design.begin.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.phys_opt_design.begin.rst new file mode 100644 index 0000000000000000000000000000000000000000..25078e8469132e72d60b814cc19f3c0f9a46e011 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.phys_opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.phys_opt_design.end.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.phys_opt_design.end.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.place_design.begin.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000000000000000000000000000000000000..25078e8469132e72d60b814cc19f3c0f9a46e011 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.place_design.end.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.route_design.begin.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000000000000000000000000000000000000..25078e8469132e72d60b814cc19f3c0f9a46e011 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.route_design.end.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.vivado.begin.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000000000000000000000000000000000000..202671704c1a7c40575cbdf64a60666f42041fba --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.vivado.end.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/ISEWrap.js b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000000000000000000000000000000000000..db0a51077cfb3a198d0bcb1b84080b9210b5b593 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/ISEWrap.js @@ -0,0 +1,269 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/ISEWrap.sh b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000000000000000000000000000000000000..4fa5b5cbed982e5033e8d24e5538095bdd6fc003 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/ISEWrap.sh @@ -0,0 +1,73 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/gen_run.xml b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/gen_run.xml new file mode 100644 index 0000000000000000000000000000000000000000..4eea60b3446ea15037b2dc9874606561b5e5fde7 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/gen_run.xml @@ -0,0 +1,148 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/htr.txt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/htr.txt new file mode 100644 index 0000000000000000000000000000000000000000..732a0131ab8f1a7a221665d9a025b0b4e622ec93 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log riscv_core.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/init_design.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/init_design.pb new file mode 100644 index 0000000000000000000000000000000000000000..9e7dfdd3182ba7d19a0d757c9ef698c110bb935b Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/init_design.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/opt_design.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/opt_design.pb new file mode 100644 index 0000000000000000000000000000000000000000..f8eff16bc9d21b60c39a49d21013163ab37c414d Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/opt_design.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/phys_opt_design.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/phys_opt_design.pb new file mode 100644 index 0000000000000000000000000000000000000000..f1642b032b6ad7b30f6aae9a857f19f56e519287 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/phys_opt_design.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/place_design.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/place_design.pb new file mode 100644 index 0000000000000000000000000000000000000000..705045e18aa9f0822a3c1774e1d0c95a05649de5 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/place_design.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/project.wdf b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/project.wdf new file mode 100644 index 0000000000000000000000000000000000000000..af7d5b62849f64fef438cd3f81ed2eb47fe9c574 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3764356431346564313833653430343962656265633534323531626437333330:506172656e742050412070726f6a656374204944:00 +eof:254497829 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.tcl b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.tcl new file mode 100644 index 0000000000000000000000000000000000000000..ec9c17a168147f0413087c6706c45a93a86f516f --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.tcl @@ -0,0 +1,296 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +namespace eval ::optrace { + variable script "D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.tcl" + variable category "vivado_impl" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } elseif { [info exist ::env(HOST)] } { + set host $::env(HOST) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +OPTRACE "impl_1" END { } +} + + +OPTRACE "impl_1" START { ROLLUP_1 } +OPTRACE "Phase: Init Design" START { ROLLUP_AUTO } +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 5 +OPTRACE "create in-memory project" START { } + create_project -in_memory -part xc7k70tfbv484-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 +OPTRACE "create in-memory project" END { } +OPTRACE "set parameters" START { } + set_property webtalk.parent_dir D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt [current_project] + set_property parent.project_path D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.xpr [current_project] + set_property ip_output_repo D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] +OPTRACE "set parameters" END { } +OPTRACE "add files" START { } + add_files -quiet D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.dcp +OPTRACE "read constraints: implementation" START { } +OPTRACE "read constraints: implementation" END { } +OPTRACE "add files" END { } +OPTRACE "link_design" START { } + link_design -top riscv_core -part xc7k70tfbv484-1 +OPTRACE "link_design" END { } +OPTRACE "gray box cells" START { } +OPTRACE "gray box cells" END { } +OPTRACE "init_design_reports" START { REPORT } +OPTRACE "init_design_reports" END { } +OPTRACE "init_design_write_hwdef" START { } +OPTRACE "init_design_write_hwdef" END { } + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Init Design" END { } +OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO } +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb +OPTRACE "read constraints: opt_design" START { } +OPTRACE "read constraints: opt_design" END { } +OPTRACE "opt_design" START { } + opt_design +OPTRACE "opt_design" END { } +OPTRACE "read constraints: opt_design_post" START { } +OPTRACE "read constraints: opt_design_post" END { } +OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force riscv_core_opt.dcp +OPTRACE "Opt Design: write_checkpoint" END { } +OPTRACE "opt_design reports" START { REPORT } + create_report "impl_1_opt_report_drc_0" "report_drc -file riscv_core_drc_opted.rpt -pb riscv_core_drc_opted.pb -rpx riscv_core_drc_opted.rpx" +OPTRACE "opt_design reports" END { } + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Opt Design" END { } +OPTRACE "Phase: Place Design" START { ROLLUP_AUTO } +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb +OPTRACE "read constraints: place_design" START { } +OPTRACE "read constraints: place_design" END { } + if { [llength [get_debug_cores -quiet] ] > 0 } { +OPTRACE "implement_debug_core" START { } + implement_debug_core +OPTRACE "implement_debug_core" END { } + } +OPTRACE "place_design" START { } + place_design +OPTRACE "place_design" END { } +OPTRACE "read constraints: place_design_post" START { } +OPTRACE "read constraints: place_design_post" END { } +OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force riscv_core_placed.dcp +OPTRACE "Place Design: write_checkpoint" END { } +OPTRACE "place_design reports" START { REPORT } + create_report "impl_1_place_report_io_0" "report_io -file riscv_core_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file riscv_core_utilization_placed.rpt -pb riscv_core_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file riscv_core_control_sets_placed.rpt" +OPTRACE "place_design reports" END { } + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Place Design" END { } +OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO } +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb +OPTRACE "read constraints: phys_opt_design" START { } +OPTRACE "read constraints: phys_opt_design" END { } +OPTRACE "phys_opt_design" START { } + phys_opt_design +OPTRACE "phys_opt_design" END { } +OPTRACE "read constraints: phys_opt_design_post" START { } +OPTRACE "read constraints: phys_opt_design_post" END { } +OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force riscv_core_physopt.dcp +OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { } +OPTRACE "phys_opt_design report" START { REPORT } +OPTRACE "phys_opt_design report" END { } + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +OPTRACE "Phase: Physical Opt Design" END { } +OPTRACE "Phase: Route Design" START { ROLLUP_AUTO } +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb +OPTRACE "read constraints: route_design" START { } +OPTRACE "read constraints: route_design" END { } +OPTRACE "route_design" START { } + route_design +OPTRACE "route_design" END { } +OPTRACE "read constraints: route_design_post" START { } +OPTRACE "read constraints: route_design_post" END { } +OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT } + write_checkpoint -force riscv_core_routed.dcp +OPTRACE "Route Design: write_checkpoint" END { } +OPTRACE "route_design reports" START { REPORT } + create_report "impl_1_route_report_drc_0" "report_drc -file riscv_core_drc_routed.rpt -pb riscv_core_drc_routed.pb -rpx riscv_core_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file riscv_core_methodology_drc_routed.rpt -pb riscv_core_methodology_drc_routed.pb -rpx riscv_core_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file riscv_core_power_routed.rpt -pb riscv_core_power_summary_routed.pb -rpx riscv_core_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file riscv_core_route_status.rpt -pb riscv_core_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file riscv_core_timing_summary_routed.rpt -pb riscv_core_timing_summary_routed.pb -rpx riscv_core_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file riscv_core_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file riscv_core_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file riscv_core_bus_skew_routed.rpt -pb riscv_core_bus_skew_routed.pb -rpx riscv_core_bus_skew_routed.rpx" +OPTRACE "route_design reports" END { } +OPTRACE "route_design misc" START { } + close_msg_db -file route_design.pb +OPTRACE "route_design write_checkpoint" START { CHECKPOINT } +OPTRACE "route_design write_checkpoint" END { } +} RESULT] +if {$rc} { + write_checkpoint -force riscv_core_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +OPTRACE "route_design misc" END { } +OPTRACE "Phase: Route Design" END { } +OPTRACE "impl_1" END { } diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.vdi b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.vdi new file mode 100644 index 0000000000000000000000000000000000000000..6b9b3c2d8e2a71d4d36cd722ac7ff991d37d3d09 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.vdi @@ -0,0 +1,511 @@ +#----------------------------------------------------------- +# Vivado v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Sep 7 20:35:31 2021 +# Process ID: 15884 +# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1 +# Command line: vivado.exe -log riscv_core.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace +# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.vdi +# Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source riscv_core.tcl -notrace +Command: link_design -top riscv_core -part xc7k70tfbv484-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7k70tfbv484-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1135.523 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 169 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2021.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1135.523 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k70t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k70t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1135.523 ; gain = 0.000 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 11b2de1dc + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1375.836 ; gain = 240.312 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 16f024db4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.134 . Memory (MB): peak = 1591.191 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1069a2a66 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.155 . Memory (MB): peak = 1591.191 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 162c11486 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.188 . Memory (MB): peak = 1591.191 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 162c11486 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.246 . Memory (MB): peak = 1591.191 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 162c11486 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.251 . Memory (MB): peak = 1591.191 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 162c11486 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1591.191 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 3 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1591.191 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1a2960240 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.323 . Memory (MB): peak = 1591.191 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1a2960240 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1591.191 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1a2960240 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1591.191 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1591.191 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1a2960240 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1591.191 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1591.191 ; gain = 455.668 +INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file riscv_core_drc_opted.rpt -pb riscv_core_drc_opted.pb -rpx riscv_core_drc_opted.rpx +Command: report_drc -file riscv_core_drc_opted.rpt -pb riscv_core_drc_opted.pb -rpx riscv_core_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.1/data/ip'. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k70t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k70t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ce1ca451 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 61c476bd + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 141f6b4c5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 141f6b4c5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 141f6b4c5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 141f6b4c5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 141f6b4c5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 141f6b4c5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 2.4 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.4 Global Placement Core | Checksum: f80ce2ca + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Phase 2 Global Placement | Checksum: f80ce2ca + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: f80ce2ca + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16fc92988 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 169c00e58 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 169c00e58 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 88bdbfa3 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 88bdbfa3 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 88bdbfa3 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 88bdbfa3 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 88bdbfa3 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 88bdbfa3 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 1x1| +|___________|___________________|___________________| +| South| 1x1| 1x1| +|___________|___________________|___________________| +| East| 1x1| 1x1| +|___________|___________________|___________________| +| West| 1x1| 1x1| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 88bdbfa3 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Phase 4.3 Placer Reporting | Checksum: 88bdbfa3 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1639.297 ; gain = 0.000 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 7e21387d + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Ending Placer Task | Checksum: 5be77aa1 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1639.297 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.228 . Memory (MB): peak = 1639.297 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file riscv_core_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.108 . Memory (MB): peak = 1639.297 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file riscv_core_utilization_placed.rpt -pb riscv_core_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file riscv_core_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1639.297 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k70t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k70t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +48 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.182 . Memory (MB): peak = 1647.164 ; gain = 7.867 +INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k70t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k70t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 4ab5d701 ConstDB: 0 ShapeSum: 1131a3a0 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1a2851448 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1774.625 ; gain = 117.348 +Post Restoration Checksum: NetGraph: f4398e94 NumContArr: ae4b85b4 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1a2851448 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1780.652 ; gain = 123.375 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1a2851448 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1780.652 ; gain = 123.375 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 94c50b78 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1803.363 ; gain = 146.086 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 2695 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 2695 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing + +Phase 3.1 Global Routing +Phase 3.1 Global Routing | Checksum: 94c50b78 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1803.363 ; gain = 146.086 +Phase 3 Initial Routing | Checksum: a376a008 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1803.363 ; gain = 146.086 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 298 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: b2c111be + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1803.363 ; gain = 146.086 +Phase 4 Rip-up And Reroute | Checksum: b2c111be + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1803.363 ; gain = 146.086 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: b2c111be + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1803.363 ; gain = 146.086 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: b2c111be + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1803.363 ; gain = 146.086 +Phase 6 Post Hold Fix | Checksum: b2c111be + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1803.363 ; gain = 146.086 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 1.48523 % + Global Horizontal Routing Utilization = 1.25409 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 47.7477%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 54.955%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 50%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 48.5294%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: b2c111be + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1803.363 ; gain = 146.086 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: b2c111be + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1803.363 ; gain = 146.086 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 8efedea6 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1803.363 ; gain = 146.086 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1803.363 ; gain = 146.086 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +57 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 1803.363 ; gain = 156.199 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.248 . Memory (MB): peak = 1810.332 ; gain = 6.969 +INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file riscv_core_drc_routed.rpt -pb riscv_core_drc_routed.pb -rpx riscv_core_drc_routed.rpx +Command: report_drc -file riscv_core_drc_routed.rpt -pb riscv_core_drc_routed.pb -rpx riscv_core_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file riscv_core_methodology_drc_routed.rpt -pb riscv_core_methodology_drc_routed.pb -rpx riscv_core_methodology_drc_routed.rpx +Command: report_methodology -file riscv_core_methodology_drc_routed.rpt -pb riscv_core_methodology_drc_routed.pb -rpx riscv_core_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file riscv_core_power_routed.rpt -pb riscv_core_power_summary_routed.pb -rpx riscv_core_power_routed.rpx +Command: report_power -file riscv_core_power_routed.rpt -pb riscv_core_power_summary_routed.pb -rpx riscv_core_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +68 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file riscv_core_route_status.rpt -pb riscv_core_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file riscv_core_timing_summary_routed.rpt -pb riscv_core_timing_summary_routed.pb -rpx riscv_core_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file riscv_core_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file riscv_core_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file riscv_core_bus_skew_routed.rpt -pb riscv_core_bus_skew_routed.pb -rpx riscv_core_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Tue Sep 7 20:36:12 2021... diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..198f9dd3dc4b1e1d6546d607bab43664a2d1af5e --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:36:12 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file riscv_core_bus_skew_routed.rpt -pb riscv_core_bus_skew_routed.pb -rpx riscv_core_bus_skew_routed.rpx +| Design : riscv_core +| Device : 7k70t-fbv484 +| Speed File : -1 PRODUCTION 1.12 2017-02-17 +--------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.rpx b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.rpx new file mode 100644 index 0000000000000000000000000000000000000000..57979ce2fc87aa07bee39534c89cb9c946d0643a Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.rpx differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_clock_utilization_routed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_clock_utilization_routed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..8ec5b99902d07a27888f187ab21b1a5601411b59 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_clock_utilization_routed.rpt @@ -0,0 +1,178 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:36:12 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_clock_utilization -file riscv_core_clock_utilization_routed.rpt +| Design : riscv_core +| Device : 7k70t-fbv484 +| Speed File : -1 PRODUCTION 1.12 2017-02-17 +| Design State : Routed +---------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y0 +8. Clock Region Cell Placement per Global Clock: Region X0Y1 +9. Clock Region Cell Placement per Global Clock: Region X0Y2 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 96 | 0 | 0 | 0 | +| BUFIO | 0 | 24 | 0 | 0 | 0 | +| BUFMR | 0 | 12 | 0 | 0 | 0 | +| BUFR | 0 | 24 | 0 | 0 | 0 | +| MMCM | 0 | 6 | 0 | 0 | 0 | +| PLL | 0 | 6 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 3 | 600 | 0 | | | wClk_IBUF_BUFG_inst/O | wClk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+ +| src0 | g0 | IBUF/O | None | IOB_X0Y178 | X0Y3 | 1 | 0 | | | wClk_IBUF_inst/O | wClk_IBUF | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 125 | 1800 | 57 | 500 | 0 | 40 | 0 | 20 | 0 | 40 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1300 | 0 | 400 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 468 | 1200 | 202 | 500 | 0 | 40 | 0 | 20 | 0 | 40 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1300 | 0 | 400 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 7 | 1200 | 0 | 500 | 0 | 40 | 0 | 20 | 0 | 40 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 750 | 0 | 250 | 0 | 10 | 0 | 5 | 0 | 20 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 500 | 0 | 40 | 0 | 20 | 0 | 40 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 900 | 0 | 300 | 0 | 20 | 0 | 10 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 1 | 0 | +| Y1 | 1 | 0 | +| Y0 | 1 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+ +| g0 | BUFG/O | n/a | | | | 600 | 0 | 0 | 0 | wClk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+------+----+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+------+----+-----------------------+ +| Y3 | 0 | 0 | 0 | +| Y2 | 7 | 0 | 0 | +| Y1 | 468 | 0 | 0 | +| Y0 | 125 | 0 | 0 | ++----+------+----+-----------------------+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ +| g0 | n/a | BUFG/O | None | 125 | 0 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +8. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ +| g0 | n/a | BUFG/O | None | 468 | 0 | 468 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +9. Clock Region Cell Placement per Global Clock: Region X0Y2 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------+ +| g0 | n/a | BUFG/O | None | 7 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y16 [get_cells wClk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y178 [get_ports wClk] + +# Clock net "wClk_IBUF_BUFG" driven by instance "wClk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" +#startgroup +create_pblock {CLKAG_wClk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_wClk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="wClk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_wClk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2} +#endgroup diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_control_sets_placed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_control_sets_placed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..e1461141e86d351ccb58403de0ad2c81fbfbd2a6 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_control_sets_placed.rpt @@ -0,0 +1,100 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:35:58 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file riscv_core_control_sets_placed.rpt +| Design : riscv_core +| Device : xc7k70t +--------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 22 | +| Minimum number of control sets | 22 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 48 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 22 | +| >= 0 to < 4 | 2 | +| >= 4 to < 6 | 1 | +| >= 6 to < 8 | 2 | +| >= 8 to < 10 | 1 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 16 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 1 | 1 | +| Yes | No | No | 349 | 171 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 250 | 117 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++-----------------+-------------------------+---------------------------------+------------------+----------------+--------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | ++-----------------+-------------------------+---------------------------------+------------------+----------------+--------------+ +| wClk_IBUF_BUFG | | FSM_sequential_state[3]_i_1_n_0 | 1 | 1 | 1.00 | +| wClk_IBUF_BUFG | writedata[31]_i_1_n_0 | writemask[3]_i_1_n_0 | 1 | 1 | 1.00 | +| wClk_IBUF_BUFG | mul/E[0] | FSM_sequential_state[3]_i_1_n_0 | 2 | 5 | 2.50 | +| wClk_IBUF_BUFG | div/count[5]_i_1_n_0 | mul/wStart0 | 2 | 6 | 3.00 | +| wClk_IBUF_BUFG | imm | imm[10]_i_1_n_0 | 2 | 6 | 3.00 | +| wClk_IBUF_BUFG | lastv | lastv[31]_i_1_n_0 | 5 | 8 | 1.60 | +| wClk_IBUF_BUFG | lastv | | 17 | 24 | 1.41 | +| wClk_IBUF_BUFG | imm | | 16 | 26 | 1.62 | +| wClk_IBUF_BUFG | writeaddr[31]_i_1_n_0 | | 9 | 30 | 3.33 | +| wClk_IBUF_BUFG | mul/wStart0 | FSM_sequential_state[3]_i_1_n_0 | 25 | 32 | 1.28 | +| wClk_IBUF_BUFG | mul/bbuf | mul/abuf[63]_i_1_n_0 | 10 | 32 | 3.20 | +| wClk_IBUF_BUFG | div/abuf[31]_i_1__0_n_0 | | 22 | 32 | 1.45 | +| wClk_IBUF_BUFG | div/abuf[31]_i_1__0_n_0 | mul/wStart0 | 9 | 32 | 3.56 | +| wClk_IBUF_BUFG | csr_r | csr_r[31]_i_1_n_0 | 20 | 32 | 1.60 | +| wClk_IBUF_BUFG | lastaddr | | 15 | 32 | 2.13 | +| wClk_IBUF_BUFG | misa | FSM_sequential_state[3]_i_1_n_0 | 25 | 32 | 1.28 | +| wClk_IBUF_BUFG | csr_r | | 16 | 34 | 2.12 | +| wClk_IBUF_BUFG | mul/wStart0 | | 21 | 35 | 1.67 | +| wClk_IBUF_BUFG | writedata[31]_i_1_n_0 | | 18 | 35 | 1.94 | +| wClk_IBUF_BUFG | ldaddr[31]_i_1_n_0 | | 12 | 37 | 3.08 | +| wClk_IBUF_BUFG | mul/result | mul/wStart0 | 16 | 64 | 4.00 | +| wClk_IBUF_BUFG | mul/bbuf | | 25 | 64 | 2.56 | ++-----------------+-------------------------+---------------------------------+------------------+----------------+--------------+ + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.pb new file mode 100644 index 0000000000000000000000000000000000000000..0158a2ad826bcd75c8436a6a29252340aee67559 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.rpt new file mode 100644 index 0000000000000000000000000000000000000000..85744a14e55782e91dd768704f48c2bae552b694 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.rpt @@ -0,0 +1,67 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:35:51 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_drc -file riscv_core_drc_opted.rpt -pb riscv_core_drc_opted.pb -rpx riscv_core_drc_opted.rpx +| Design : riscv_core +| Device : xc7k70tfbv484-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +284 out of 284 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: bReadAddr[31:0], bReadData[31:0], bWriteAddr[31:0], bWriteData[31:0], +bWriteMask[3:0], nwReset, regena2[3:0], regena[3:0], regno2[4:0], +regno[4:0], regrddata2[31:0], regrddata[31:0], regwrdata2[31:0], +regwrdata[31:0], regwren (the first 15 of 19 listed). +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +284 out of 284 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: bReadAddr[31:0], bReadData[31:0], bWriteAddr[31:0], bWriteData[31:0], +bWriteMask[3:0], nwReset, regena2[3:0], regena[3:0], regno2[4:0], +regno[4:0], regrddata2[31:0], regrddata[31:0], regwrdata2[31:0], +regwrdata[31:0], regwren (the first 15 of 19 listed). +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.rpx b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.rpx new file mode 100644 index 0000000000000000000000000000000000000000..4162029bd8316581c6c13742b6f7042fb16d535b Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.rpx differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..0158a2ad826bcd75c8436a6a29252340aee67559 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..140780bda9cc8ca6748977fa26e0f1f076aa9834 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.rpt @@ -0,0 +1,67 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:36:09 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_drc -file riscv_core_drc_routed.rpt -pb riscv_core_drc_routed.pb -rpx riscv_core_drc_routed.rpx +| Design : riscv_core +| Device : xc7k70tfbv484-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +284 out of 284 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: bReadAddr[31:0], bReadData[31:0], bWriteAddr[31:0], bWriteData[31:0], +bWriteMask[3:0], nwReset, regena2[3:0], regena[3:0], regno2[4:0], +regno[4:0], regrddata2[31:0], regrddata[31:0], regwrdata2[31:0], +regwrdata[31:0], regwren (the first 15 of 19 listed). +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +284 out of 284 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: bReadAddr[31:0], bReadData[31:0], bWriteAddr[31:0], bWriteData[31:0], +bWriteMask[3:0], nwReset, regena2[3:0], regena[3:0], regno2[4:0], +regno[4:0], regrddata2[31:0], regrddata[31:0], regwrdata2[31:0], +regwrdata[31:0], regwren (the first 15 of 19 listed). +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.rpx b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.rpx new file mode 100644 index 0000000000000000000000000000000000000000..37891237d3a6e73c9c31dd1750b3b7c310666e16 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.rpx differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_io_placed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_io_placed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..e5be9c87a578836f8712b3a1b4b0c92e13dd3c50 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_io_placed.rpt @@ -0,0 +1,526 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:35:58 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_io -file riscv_core_io_placed.rpt +| Design : riscv_core +| Device : xc7k70t +| Speed File : -1 +| Package : fbv484 +| Package Version : FINAL 2012-06-26 +| Package Pin Delay Version : VERS. 2.0 2012-06-26 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 284 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+----------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+----------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | bWriteData[5] | High Range | IO_L21N_T3_DQS_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| A9 | bWriteData[6] | High Range | IO_L21P_T3_DQS_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| A10 | bWriteData[1] | High Range | IO_L23N_T3_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| A11 | bWriteData[2] | High Range | IO_L23P_T3_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | regrddata2[24] | High Range | IO_L4P_T0_AD9P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| A14 | regrddata2[23] | High Range | IO_L4N_T0_AD9N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| A15 | regrddata2[13] | High Range | IO_L9N_T1_DQS_AD11N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| A16 | regrddata2[15] | High Range | IO_L8N_T1_AD3N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| A18 | regrddata2[11] | High Range | IO_L10N_T1_AD4N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| A19 | regwrdata2[27] | High Range | IO_L20N_T3_A19_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| A20 | regwrdata2[24] | High Range | IO_L22P_T3_A17_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| A21 | regwrdata2[23] | High Range | IO_L22N_T3_A16_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | bWriteAddr[6] | High Performance | IO_L22P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | bWriteAddr[4] | High Performance | IO_L23P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA4 | bWriteAddr[2] | High Performance | IO_L24P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA5 | bReadData[16] | High Performance | IO_L1P_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AA6 | bReadData[12] | High Performance | IO_L3P_T0_DQS_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 1.80 | | | | | | | | | +| AA8 | bReadData[7] | High Performance | IO_L5N_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AA9 | bReadData[8] | High Performance | IO_L5P_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AA10 | bReadData[10] | High Performance | IO_L4P_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AA11 | bReadAddr[10] | High Performance | IO_L20P_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | bReadAddr[7] | High Performance | IO_L21N_T3_DQS_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA14 | regwrdata[14] | High Range | IO_L18P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA15 | regwrdata[13] | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA16 | regwrdata[16] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| AA18 | regwrdata[20] | High Range | IO_L15P_T2_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA19 | regwrdata[30] | High Range | IO_L10P_T1_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA20 | regno[2] | High Range | IO_L8P_T1_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA21 | regno[0] | High Range | IO_L9P_T1_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | bWriteAddr[5] | High Performance | IO_L22N_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB2 | bWriteAddr[3] | High Performance | IO_L23N_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB3 | bWriteAddr[1] | High Performance | IO_L24N_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| AB5 | bReadData[15] | High Performance | IO_L1N_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AB6 | bReadData[11] | High Performance | IO_L3N_T0_DQS_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AB7 | bReadData[13] | High Performance | IO_L2N_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AB8 | bReadData[14] | High Performance | IO_L2P_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | bReadData[9] | High Performance | IO_L4N_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| AB11 | bReadAddr[9] | High Performance | IO_L20N_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB12 | bReadAddr[5] | High Performance | IO_L22N_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB13 | bReadAddr[6] | High Performance | IO_L22P_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| AB15 | regwrdata[18] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB16 | regwrdata[17] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB17 | regwrdata[15] | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB18 | regwrdata[19] | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | regwrdata[29] | High Range | IO_L10N_T1_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB21 | regno[1] | High Range | IO_L8N_T1_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| AB22 | regwrdata[31] | High Range | IO_L9N_T1_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | bWriteData[3] | High Range | IO_L22N_T3_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B10 | bWriteData[7] | High Range | IO_L20N_T3_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| B11 | bWriteData[8] | High Range | IO_L20P_T3_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| B12 | regrddata2[27] | High Range | IO_L2N_T0_AD8N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| B13 | regrddata2[21] | High Range | IO_L5N_T0_AD2N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| B15 | regrddata2[14] | High Range | IO_L9P_T1_DQS_AD11P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| B16 | regrddata2[16] | High Range | IO_L8P_T1_AD3P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| B17 | regrddata2[12] | High Range | IO_L10P_T1_AD4P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| B18 | regwrdata2[28] | High Range | IO_L20P_T3_A20_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | regwrdata2[20] | High Range | IO_L24P_T3_RS1_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| B21 | regwrdata2[19] | High Range | IO_L24N_T3_RS0_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| B22 | regwrdata2[25] | High Range | IO_L21N_T3_DQS_A18_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C8 | bWriteData[4] | High Range | IO_L22P_T3_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| C9 | bWriteData[9] | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| C10 | bWriteData[31] | High Range | IO_L7N_T1_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | +| C12 | regrddata2[28] | High Range | IO_L2P_T0_AD8P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C13 | regrddata2[22] | High Range | IO_L5P_T0_AD2P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C14 | regrddata2[18] | High Range | IO_L7P_T1_AD10P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C15 | regrddata2[17] | High Range | IO_L7N_T1_AD10N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | regrddata2[8] | High Range | IO_L12P_T1_MRCC_AD5P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C18 | regrddata2[7] | High Range | IO_L12N_T1_MRCC_AD5N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C19 | regwrdata2[30] | High Range | IO_L19P_T3_A22_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| C20 | regwrdata2[29] | High Range | IO_L19N_T3_A21_VREF_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| C22 | regwrdata2[26] | High Range | IO_L21P_T3_DQS_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | | +| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | +| D9 | bWriteData[10] | High Range | IO_L19P_T3_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| D10 | nwReset | High Range | IO_L7P_T1_16 | INPUT | LVCMOS18* | 16 | | | | NONE | | UNFIXED | | | | NONE | | | | +| D11 | bWriteData[22] | High Range | IO_L12N_T1_MRCC_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| D12 | regrddata2[31] | High Range | IO_0_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | regrddata2[19] | High Range | IO_L6N_T0_VREF_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| D15 | regrddata2[10] | High Range | IO_L11P_T1_SRCC_AD12P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| D16 | regrddata2[9] | High Range | IO_L11N_T1_SRCC_AD12N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| D17 | regrddata2[3] | High Range | IO_L14N_T2_SRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| D19 | regena2[0] | High Range | IO_L18P_T2_A24_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| D20 | regwrdata2[31] | High Range | IO_L18N_T2_A23_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| D21 | regwrdata2[22] | High Range | IO_L23P_T3_FOE_B_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| D22 | regwrdata2[21] | High Range | IO_L23N_T3_FWE_B_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | bWriteData[0] | High Range | IO_24_T3_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| E9 | bWriteData[16] | High Range | IO_L15N_T2_DQS_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E11 | bWriteData[23] | High Range | IO_L12P_T1_MRCC_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| E12 | bWriteData[25] | High Range | IO_L10N_T1_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| E13 | bWriteData[26] | High Range | IO_L10P_T1_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| E14 | regrddata2[20] | High Range | IO_L6P_T0_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| E16 | regrddata2[4] | High Range | IO_L14P_T2_SRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E17 | regrddata2[6] | High Range | IO_L13P_T2_MRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E18 | regrddata2[5] | High Range | IO_L13N_T2_MRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E19 | regena2[1] | High Range | IO_L17N_T2_A25_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | regrddata[18] | High Range | IO_L7P_T1_D09_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E22 | regrddata[17] | High Range | IO_L7N_T1_D10_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | | +| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | bWriteData[12] | High Range | IO_L17N_T2_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| F9 | bWriteData[17] | High Range | IO_L15P_T2_DQS_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| F10 | bWriteData[24] | High Range | IO_L11N_T1_SRCC_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| F11 | wClk | High Range | IO_L11P_T1_SRCC_16 | INPUT | LVCMOS18* | 16 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | +| F13 | bWriteData[29] | High Range | IO_L8N_T1_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | regrddata2[26] | High Range | IO_L3P_T0_DQS_AD1P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F16 | regrddata2[25] | High Range | IO_L3N_T0_DQS_AD1N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | regena2[2] | High Range | IO_L17P_T2_A26_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| F19 | regrddata[27] | High Range | IO_L2N_T0_D03_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F20 | regrddata[23] | High Range | IO_L4N_T0_D05_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F21 | regrddata[13] | High Range | IO_L9N_T1_DQS_D13_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| G8 | bWriteData[13] | High Range | IO_L17P_T2_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | +| G10 | bWriteData[20] | High Range | IO_L13N_T2_MRCC_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| G11 | bWriteData[21] | High Range | IO_L13P_T2_MRCC_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| G12 | bWriteData[18] | High Range | IO_L14N_T2_SRCC_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| G13 | bWriteData[30] | High Range | IO_L8P_T1_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | regrddata2[30] | High Range | IO_L1P_T0_AD0P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G16 | regrddata2[29] | High Range | IO_L1N_T0_AD0N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G17 | regrddata2[1] | High Range | IO_L15N_T2_DQS_ADV_B_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G18 | regrddata[28] | High Range | IO_L2P_T0_D02_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| G20 | regrddata[24] | High Range | IO_L4P_T0_D04_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G21 | regrddata[14] | High Range | IO_L9P_T1_DQS_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G22 | regrddata[15] | High Range | IO_L8N_T1_D12_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | | +| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| H8 | bWriteData[14] | High Range | IO_L16N_T2_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| H9 | bWriteData[15] | High Range | IO_L16P_T2_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| H10 | bWriteData[11] | High Range | IO_18_T2_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | bWriteData[19] | High Range | IO_L14P_T2_SRCC_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| H13 | bWriteData[27] | High Range | IO_L9N_T1_DQS_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| H14 | bWriteData[28] | High Range | IO_L9P_T1_DQS_16 | OUTPUT | LVCMOS18* | 16 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| H15 | regwrdata2[18] | High Range | IO_25_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| H17 | regrddata2[2] | High Range | IO_L15P_T2_DQS_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H18 | regrddata[30] | High Range | IO_L1P_T0_D00_MOSI_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H19 | regrddata[29] | High Range | IO_L1N_T0_D01_DIN_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H20 | regrddata[9] | High Range | IO_L11N_T1_SRCC_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | regrddata[16] | High Range | IO_L8P_T1_D11_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | | +| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J16 | regrddata2[0] | High Range | IO_L16P_T2_A28_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J17 | regena2[3] | High Range | IO_L16N_T2_A27_15 | OUTPUT | LVCMOS18* | 15 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | regrddata[25] | High Range | IO_L3N_T0_DQS_EMCCLK_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J20 | regrddata[10] | High Range | IO_L11P_T1_SRCC_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J21 | regrddata[12] | High Range | IO_L10P_T1_D14_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J22 | regrddata[11] | High Range | IO_L10N_T1_D15_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K1 | bReadData[28] | High Performance | IO_L2P_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K2 | bReadData[23] | High Performance | IO_L4N_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K3 | bReadData[24] | High Performance | IO_L4P_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K4 | bReadData[31] | High Performance | IO_0_VRN_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | regrddata[31] | High Range | IO_0_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K17 | regrddata[19] | High Range | IO_L6N_T0_D08_VREF_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K18 | regrddata[26] | High Range | IO_L3P_T0_DQS_PUDC_B_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K19 | regrddata[21] | High Range | IO_L5N_T0_D07_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| K21 | regrddata[0] | High Range | IO_L16P_T2_CSI_B_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K22 | regwrdata2[17] | High Range | IO_L16N_T2_A15_D31_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| L1 | bReadData[27] | High Performance | IO_L2N_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | bReadData[30] | High Performance | IO_L1P_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| L4 | bReadData[19] | High Performance | IO_L6N_T0_VREF_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| L5 | bReadData[20] | High Performance | IO_L6P_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L16 | regrddata[20] | High Range | IO_L6P_T0_FCS_B_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| L18 | regrddata[22] | High Range | IO_L5P_T0_D06_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| L19 | regrddata[8] | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| L20 | regrddata[7] | High Range | IO_L12N_T1_MRCC_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| L21 | regwrdata2[13] | High Range | IO_L18N_T2_A11_D27_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | bReadData[25] | High Performance | IO_L3N_T0_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| M2 | bReadData[26] | High Performance | IO_L3P_T0_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| M3 | bReadData[29] | High Performance | IO_L1N_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| M5 | regwren | High Performance | IO_L9P_T1_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | regwrdata2[0] | High Range | IO_25_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| M17 | regrddata[4] | High Range | IO_L14P_T2_SRCC_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| M18 | regrddata[3] | High Range | IO_L14N_T2_SRCC_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | regwrdata2[14] | High Range | IO_L18P_T2_A12_D28_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| M21 | regwrdata2[15] | High Range | IO_L17N_T2_A13_D29_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| M22 | regrddata[1] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| N2 | bReadData[21] | High Performance | IO_L5N_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| N3 | bReadData[22] | High Performance | IO_L5P_T0_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| N4 | bWriteAddr[31] | High Performance | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| N5 | bWriteAddr[14] | High Performance | IO_L18P_T2_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | regwrdata2[3] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| N18 | regrddata[6] | High Range | IO_L13P_T2_MRCC_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| N19 | regrddata[5] | High Range | IO_L13N_T2_MRCC_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| N20 | regwrdata2[16] | High Range | IO_L17P_T2_A14_D30_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| N22 | regrddata[2] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| P1 | wRead | High Performance | IO_L8P_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P2 | bReadData[18] | High Performance | IO_L7P_T1_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | bWriteAddr[28] | High Performance | IO_L11P_T1_SRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P5 | bWriteAddr[13] | High Performance | IO_L18N_T2_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P16 | regwrdata2[4] | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P17 | regwrdata2[7] | High Range | IO_L21N_T3_DQS_A06_D22_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| P19 | regwrdata2[10] | High Range | IO_L20P_T3_A08_D24_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P20 | regwrdata2[9] | High Range | IO_L20N_T3_A07_D23_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P21 | regwrdata2[6] | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P22 | regwrdata2[5] | High Range | IO_L22N_T3_A04_D20_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R1 | regwren2 | High Performance | IO_L8N_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R2 | wWrite | High Performance | IO_L7N_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R3 | bWriteAddr[26] | High Performance | IO_L12P_T1_MRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R4 | bWriteAddr[27] | High Performance | IO_L11N_T1_SRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| R6 | bReadData[1] | High Performance | IO_L8N_T1_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R7 | bReadData[2] | High Performance | IO_L8P_T1_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R16 | regwrdata[10] | High Range | IO_L20P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R17 | regwrdata2[8] | High Range | IO_L21P_T3_DQS_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R18 | regwrdata2[12] | High Range | IO_L19P_T3_A10_D26_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R19 | regwrdata2[11] | High Range | IO_L19N_T3_A09_D25_VREF_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | regwrdata2[2] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R22 | regwrdata2[1] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T1 | bWriteAddr[30] | High Performance | IO_L10P_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| T3 | bWriteAddr[25] | High Performance | IO_L12N_T1_MRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T4 | bWriteAddr[24] | High Performance | IO_L13P_T2_MRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T5 | bWriteAddr[18] | High Performance | IO_L16P_T2_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T6 | bReadData[17] | High Performance | IO_0_VRN_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | bReadAddr[13] | High Performance | IO_L18N_T2_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T9 | bReadAddr[14] | High Performance | IO_L18P_T2_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T10 | bReadAddr[17] | High Performance | IO_L16N_T2_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T11 | bReadAddr[18] | High Performance | IO_L16P_T2_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 1.80 | | | | | | | | | +| T13 | bReadAddr[2] | High Performance | IO_L24P_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T14 | bReadAddr[0] | High Performance | IO_25_VRP_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T15 | regwrdata[2] | High Range | IO_L24P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T16 | regwrdata[9] | High Range | IO_L20N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | bWriteMask[2] | High Range | IO_L3P_T0_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T19 | regena[3] | High Range | IO_0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T20 | regno2[1] | High Range | IO_L6P_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T21 | regena[2] | High Range | IO_L1P_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| U1 | bWriteAddr[29] | High Performance | IO_L10N_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U2 | bWriteAddr[20] | High Performance | IO_L15P_T2_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U3 | bWriteAddr[23] | High Performance | IO_L13N_T2_MRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | bWriteAddr[17] | High Performance | IO_L16N_T2_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U6 | bReadAddr[29] | High Performance | IO_L10N_T1_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U7 | bReadAddr[30] | High Performance | IO_L10P_T1_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U8 | bReadData[0] | High Performance | IO_L9P_T1_DQS_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 1.80 | | | | | | | | | +| U10 | bReadAddr[22] | High Performance | IO_L14P_T2_SRCC_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U11 | bReadAddr[15] | High Performance | IO_L17N_T2_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U12 | bReadAddr[16] | High Performance | IO_L17P_T2_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U13 | bReadAddr[1] | High Performance | IO_L24N_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | regwrdata[1] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U16 | regwrdata[12] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U17 | regno2[3] | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U18 | bWriteMask[1] | High Range | IO_L3N_T0_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| U20 | regno2[0] | High Range | IO_L6N_T0_VREF_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U21 | regena[1] | High Range | IO_L1N_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U22 | regena[0] | High Range | IO_L2P_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | bWriteAddr[19] | High Performance | IO_L15N_T2_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V3 | bWriteAddr[16] | High Performance | IO_L17P_T2_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V4 | bWriteAddr[22] | High Performance | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V5 | bWriteAddr[0] | High Performance | IO_25_VRP_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 1.80 | | | | | | | | | +| V7 | bReadAddr[28] | High Performance | IO_L11P_T1_SRCC_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V8 | bReadAddr[31] | High Performance | IO_L9N_T1_DQS_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V9 | bReadAddr[21] | High Performance | IO_L14N_T2_SRCC_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V10 | bReadAddr[20] | High Performance | IO_L15P_T2_DQS_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | bReadAddr[3] | High Performance | IO_L23N_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V13 | bReadAddr[4] | High Performance | IO_L23P_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V14 | regwrdata[0] | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V15 | regwrdata[4] | High Range | IO_L23P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| V17 | regwrdata[11] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V18 | regno2[2] | High Range | IO_L5N_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V19 | regwrdata[26] | High Range | IO_L12P_T1_MRCC_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V20 | regwrdata[28] | High Range | IO_L11P_T1_SRCC_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | bWriteMask[3] | High Range | IO_L2N_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W1 | bWriteAddr[10] | High Performance | IO_L20P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W2 | bWriteAddr[15] | High Performance | IO_L17N_T2_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| W4 | bWriteAddr[21] | High Performance | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W5 | bWriteAddr[12] | High Performance | IO_L19P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W6 | bReadData[4] | High Performance | IO_L7P_T1_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| W7 | bReadAddr[27] | High Performance | IO_L11N_T1_SRCC_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | bReadAddr[24] | High Performance | IO_L13P_T2_MRCC_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W10 | bReadAddr[19] | High Performance | IO_L15N_T2_DQS_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W11 | bReadData[6] | High Performance | IO_L6P_T0_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| W12 | bReadAddr[12] | High Performance | IO_L19P_T3_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 1.80 | | | | | | | | | +| W14 | regwrdata[6] | High Range | IO_L22P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W15 | regwrdata[3] | High Range | IO_L23N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W16 | regwrdata[8] | High Range | IO_L21P_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W17 | regwrdata[22] | High Range | IO_L14P_T2_SRCC_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | regwrdata[25] | High Range | IO_L12N_T1_MRCC_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W20 | regwrdata[27] | High Range | IO_L11N_T1_SRCC_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W21 | bWriteMask[0] | High Range | IO_L4P_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W22 | regno2[4] | High Range | IO_L4N_T0_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y1 | bWriteAddr[9] | High Performance | IO_L20N_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y2 | bWriteAddr[7] | High Performance | IO_L21N_T3_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y3 | bWriteAddr[8] | High Performance | IO_L21P_T3_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y4 | bWriteAddr[11] | High Performance | IO_L19N_T3_VREF_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | bReadData[3] | High Performance | IO_L7N_T1_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| Y7 | bReadAddr[25] | High Performance | IO_L12N_T1_MRCC_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y8 | bReadAddr[26] | High Performance | IO_L12P_T1_MRCC_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y9 | bReadAddr[23] | High Performance | IO_L13N_T2_MRCC_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 1.80 | | | | | | | | | +| Y11 | bReadData[5] | High Performance | IO_L6N_T0_VREF_33 | INPUT | LVCMOS18* | 33 | | | | NONE | | UNFIXED | | | | NONE | | | | +| Y12 | bReadAddr[11] | High Performance | IO_L19N_T3_VREF_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y13 | bReadAddr[8] | High Performance | IO_L21P_T3_DQS_33 | OUTPUT | LVCMOS18* | 33 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y14 | regwrdata[5] | High Range | IO_L22N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | regwrdata[7] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y17 | regwrdata[21] | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y18 | regwrdata[24] | High Range | IO_L13P_T2_MRCC_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y19 | regwrdata[23] | High Range | IO_L13N_T2_MRCC_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| Y21 | regno[4] | High Range | IO_L7P_T1_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| Y22 | regno[3] | High Range | IO_L7N_T1_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | ++------------+----------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..6f3115fdb409fc3ec3ba0f14cdcf6d876d7d34b6 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..2789057eee3ef1cfc64ccf2b6a62af94e641f30a --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.rpt @@ -0,0 +1,3035 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:36:10 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_methodology -file riscv_core_methodology_drc_routed.rpt -pb riscv_core_methodology_drc_routed.pb -rpx riscv_core_methodology_drc_routed.rpx +| Design : riscv_core +| Device : xc7k70tfbv484-1 +| Speed File : -1 +| Design State : Fully Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 600 ++-----------+------------------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+------------------+-----------------------------+------------+ +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 600 | ++-----------+------------------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Critical Warning +Non-clocked sequential cell +The clock pin FSM_sequential_state_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Critical Warning +Non-clocked sequential cell +The clock pin FSM_sequential_state_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Critical Warning +Non-clocked sequential cell +The clock pin FSM_sequential_state_reg[1]_rep/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Critical Warning +Non-clocked sequential cell +The clock pin FSM_sequential_state_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Critical Warning +Non-clocked sequential cell +The clock pin FSM_sequential_state_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#29 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#30 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#31 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#32 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#33 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#34 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#35 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#36 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#37 Critical Warning +Non-clocked sequential cell +The clock pin csr_r_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#38 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#39 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#40 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#41 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#42 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#43 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#44 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#45 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#46 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#47 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#48 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#49 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#50 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#51 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#52 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#53 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#54 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#55 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#56 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#57 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#58 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#59 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#60 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#61 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#62 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#63 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[32]/C is not reached by a timing clock +Related violations: + +TIMING-17#64 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[33]/C is not reached by a timing clock +Related violations: + +TIMING-17#65 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[34]/C is not reached by a timing clock +Related violations: + +TIMING-17#66 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[35]/C is not reached by a timing clock +Related violations: + +TIMING-17#67 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[36]/C is not reached by a timing clock +Related violations: + +TIMING-17#68 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[37]/C is not reached by a timing clock +Related violations: + +TIMING-17#69 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[38]/C is not reached by a timing clock +Related violations: + +TIMING-17#70 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[39]/C is not reached by a timing clock +Related violations: + +TIMING-17#71 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#72 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[40]/C is not reached by a timing clock +Related violations: + +TIMING-17#73 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[41]/C is not reached by a timing clock +Related violations: + +TIMING-17#74 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[42]/C is not reached by a timing clock +Related violations: + +TIMING-17#75 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[43]/C is not reached by a timing clock +Related violations: + +TIMING-17#76 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[44]/C is not reached by a timing clock +Related violations: + +TIMING-17#77 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[45]/C is not reached by a timing clock +Related violations: + +TIMING-17#78 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[46]/C is not reached by a timing clock +Related violations: + +TIMING-17#79 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[47]/C is not reached by a timing clock +Related violations: + +TIMING-17#80 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[48]/C is not reached by a timing clock +Related violations: + +TIMING-17#81 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[49]/C is not reached by a timing clock +Related violations: + +TIMING-17#82 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#83 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[50]/C is not reached by a timing clock +Related violations: + +TIMING-17#84 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[51]/C is not reached by a timing clock +Related violations: + +TIMING-17#85 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[52]/C is not reached by a timing clock +Related violations: + +TIMING-17#86 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[53]/C is not reached by a timing clock +Related violations: + +TIMING-17#87 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[54]/C is not reached by a timing clock +Related violations: + +TIMING-17#88 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[55]/C is not reached by a timing clock +Related violations: + +TIMING-17#89 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[56]/C is not reached by a timing clock +Related violations: + +TIMING-17#90 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[57]/C is not reached by a timing clock +Related violations: + +TIMING-17#91 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[58]/C is not reached by a timing clock +Related violations: + +TIMING-17#92 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[59]/C is not reached by a timing clock +Related violations: + +TIMING-17#93 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#94 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[60]/C is not reached by a timing clock +Related violations: + +TIMING-17#95 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[61]/C is not reached by a timing clock +Related violations: + +TIMING-17#96 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[62]/C is not reached by a timing clock +Related violations: + +TIMING-17#97 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[63]/C is not reached by a timing clock +Related violations: + +TIMING-17#98 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#99 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#100 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#101 Critical Warning +Non-clocked sequential cell +The clock pin div/abuf_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#102 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[32]/C is not reached by a timing clock +Related violations: + +TIMING-17#103 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[33]/C is not reached by a timing clock +Related violations: + +TIMING-17#104 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[34]/C is not reached by a timing clock +Related violations: + +TIMING-17#105 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[35]/C is not reached by a timing clock +Related violations: + +TIMING-17#106 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[36]/C is not reached by a timing clock +Related violations: + +TIMING-17#107 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[37]/C is not reached by a timing clock +Related violations: + +TIMING-17#108 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[38]/C is not reached by a timing clock +Related violations: + +TIMING-17#109 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[39]/C is not reached by a timing clock +Related violations: + +TIMING-17#110 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[40]/C is not reached by a timing clock +Related violations: + +TIMING-17#111 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[41]/C is not reached by a timing clock +Related violations: + +TIMING-17#112 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[42]/C is not reached by a timing clock +Related violations: + +TIMING-17#113 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[43]/C is not reached by a timing clock +Related violations: + +TIMING-17#114 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[44]/C is not reached by a timing clock +Related violations: + +TIMING-17#115 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[45]/C is not reached by a timing clock +Related violations: + +TIMING-17#116 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[46]/C is not reached by a timing clock +Related violations: + +TIMING-17#117 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[47]/C is not reached by a timing clock +Related violations: + +TIMING-17#118 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[48]/C is not reached by a timing clock +Related violations: + +TIMING-17#119 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[49]/C is not reached by a timing clock +Related violations: + +TIMING-17#120 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[50]/C is not reached by a timing clock +Related violations: + +TIMING-17#121 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[51]/C is not reached by a timing clock +Related violations: + +TIMING-17#122 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[52]/C is not reached by a timing clock +Related violations: + +TIMING-17#123 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[53]/C is not reached by a timing clock +Related violations: + +TIMING-17#124 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[54]/C is not reached by a timing clock +Related violations: + +TIMING-17#125 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[55]/C is not reached by a timing clock +Related violations: + +TIMING-17#126 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[56]/C is not reached by a timing clock +Related violations: + +TIMING-17#127 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[57]/C is not reached by a timing clock +Related violations: + +TIMING-17#128 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[58]/C is not reached by a timing clock +Related violations: + +TIMING-17#129 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[59]/C is not reached by a timing clock +Related violations: + +TIMING-17#130 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[60]/C is not reached by a timing clock +Related violations: + +TIMING-17#131 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[61]/C is not reached by a timing clock +Related violations: + +TIMING-17#132 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[62]/C is not reached by a timing clock +Related violations: + +TIMING-17#133 Critical Warning +Non-clocked sequential cell +The clock pin div/bbuf_reg[63]/C is not reached by a timing clock +Related violations: + +TIMING-17#134 Critical Warning +Non-clocked sequential cell +The clock pin div/count_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#135 Critical Warning +Non-clocked sequential cell +The clock pin div/count_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#136 Critical Warning +Non-clocked sequential cell +The clock pin div/count_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#137 Critical Warning +Non-clocked sequential cell +The clock pin div/count_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#138 Critical Warning +Non-clocked sequential cell +The clock pin div/count_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#139 Critical Warning +Non-clocked sequential cell +The clock pin div/count_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#140 Critical Warning +Non-clocked sequential cell +The clock pin div_s_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#141 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#142 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#143 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#144 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#145 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#146 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#147 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#148 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#149 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#150 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#151 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#152 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#153 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#154 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#155 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#156 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#157 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#158 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#159 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#160 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#161 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#162 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#163 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#164 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#165 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#166 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#167 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#168 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#169 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#170 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#171 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#172 Critical Warning +Non-clocked sequential cell +The clock pin imm_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#173 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#174 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#175 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#176 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[12]_rep/C is not reached by a timing clock +Related violations: + +TIMING-17#177 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[12]_rep__0/C is not reached by a timing clock +Related violations: + +TIMING-17#178 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[12]_rep__1/C is not reached by a timing clock +Related violations: + +TIMING-17#179 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[12]_rep__2/C is not reached by a timing clock +Related violations: + +TIMING-17#180 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#181 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[13]_rep/C is not reached by a timing clock +Related violations: + +TIMING-17#182 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[13]_rep__0/C is not reached by a timing clock +Related violations: + +TIMING-17#183 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[13]_rep__1/C is not reached by a timing clock +Related violations: + +TIMING-17#184 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[13]_rep__2/C is not reached by a timing clock +Related violations: + +TIMING-17#185 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#186 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[14]_rep/C is not reached by a timing clock +Related violations: + +TIMING-17#187 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#188 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#189 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#190 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#191 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#192 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#193 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#194 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#195 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#196 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#197 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#198 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#199 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#200 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#201 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#202 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#203 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#204 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#205 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#206 Critical Warning +Non-clocked sequential cell +The clock pin instr_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#207 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#208 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#209 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#210 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#211 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#212 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#213 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#214 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#215 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#216 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#217 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#218 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#219 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#220 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#221 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#222 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#223 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#224 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#225 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#226 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#227 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#228 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#229 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#230 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#231 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#232 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#233 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#234 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#235 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#236 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#237 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#238 Critical Warning +Non-clocked sequential cell +The clock pin lastaddr_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#239 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#240 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#241 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#242 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#243 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#244 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#245 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#246 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#247 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#248 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#249 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#250 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#251 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#252 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#253 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#254 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#255 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#256 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#257 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#258 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#259 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#260 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#261 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#262 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#263 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#264 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#265 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#266 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#267 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#268 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#269 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#270 Critical Warning +Non-clocked sequential cell +The clock pin lastv_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#271 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#272 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#273 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#274 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#275 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#276 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#277 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#278 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#279 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#280 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#281 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#282 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#283 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#284 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#285 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#286 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#287 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#288 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#289 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#290 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#291 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#292 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#293 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#294 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#295 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#296 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#297 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#298 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#299 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#300 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#301 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#302 Critical Warning +Non-clocked sequential cell +The clock pin ldaddr_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#303 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#304 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#305 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#306 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#307 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#308 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#309 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#310 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#311 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#312 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#313 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#314 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#315 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#316 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#317 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#318 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#319 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#320 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#321 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#322 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#323 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#324 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#325 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#326 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#327 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#328 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#329 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#330 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#331 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#332 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#333 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#334 Critical Warning +Non-clocked sequential cell +The clock pin misa_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#335 Critical Warning +Non-clocked sequential cell +The clock pin mod_s_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#336 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#337 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#338 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#339 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#340 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#341 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#342 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#343 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#344 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#345 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#346 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#347 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#348 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#349 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#350 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#351 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#352 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#353 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#354 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#355 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#356 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#357 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#358 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#359 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#360 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#361 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[32]/C is not reached by a timing clock +Related violations: + +TIMING-17#362 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[33]/C is not reached by a timing clock +Related violations: + +TIMING-17#363 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[34]/C is not reached by a timing clock +Related violations: + +TIMING-17#364 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[35]/C is not reached by a timing clock +Related violations: + +TIMING-17#365 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[36]/C is not reached by a timing clock +Related violations: + +TIMING-17#366 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[37]/C is not reached by a timing clock +Related violations: + +TIMING-17#367 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[38]/C is not reached by a timing clock +Related violations: + +TIMING-17#368 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[39]/C is not reached by a timing clock +Related violations: + +TIMING-17#369 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#370 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[40]/C is not reached by a timing clock +Related violations: + +TIMING-17#371 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[41]/C is not reached by a timing clock +Related violations: + +TIMING-17#372 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[42]/C is not reached by a timing clock +Related violations: + +TIMING-17#373 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[43]/C is not reached by a timing clock +Related violations: + +TIMING-17#374 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[44]/C is not reached by a timing clock +Related violations: + +TIMING-17#375 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[45]/C is not reached by a timing clock +Related violations: + +TIMING-17#376 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[46]/C is not reached by a timing clock +Related violations: + +TIMING-17#377 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[47]/C is not reached by a timing clock +Related violations: + +TIMING-17#378 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[48]/C is not reached by a timing clock +Related violations: + +TIMING-17#379 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[49]/C is not reached by a timing clock +Related violations: + +TIMING-17#380 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#381 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[50]/C is not reached by a timing clock +Related violations: + +TIMING-17#382 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[51]/C is not reached by a timing clock +Related violations: + +TIMING-17#383 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[52]/C is not reached by a timing clock +Related violations: + +TIMING-17#384 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[53]/C is not reached by a timing clock +Related violations: + +TIMING-17#385 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[54]/C is not reached by a timing clock +Related violations: + +TIMING-17#386 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[55]/C is not reached by a timing clock +Related violations: + +TIMING-17#387 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[56]/C is not reached by a timing clock +Related violations: + +TIMING-17#388 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[57]/C is not reached by a timing clock +Related violations: + +TIMING-17#389 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[58]/C is not reached by a timing clock +Related violations: + +TIMING-17#390 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[59]/C is not reached by a timing clock +Related violations: + +TIMING-17#391 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#392 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[60]/C is not reached by a timing clock +Related violations: + +TIMING-17#393 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[61]/C is not reached by a timing clock +Related violations: + +TIMING-17#394 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[62]/C is not reached by a timing clock +Related violations: + +TIMING-17#395 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[63]/C is not reached by a timing clock +Related violations: + +TIMING-17#396 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#397 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#398 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#399 Critical Warning +Non-clocked sequential cell +The clock pin mul/abuf_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#400 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#401 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#402 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#403 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#404 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#405 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#406 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#407 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#408 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#409 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#410 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#411 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#412 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#413 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#414 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#415 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#416 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#417 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#418 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#419 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#420 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#421 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#422 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#423 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#424 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#425 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#426 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#427 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#428 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#429 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#430 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#431 Critical Warning +Non-clocked sequential cell +The clock pin mul/bbuf_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#432 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#433 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#434 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#435 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#436 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#437 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#438 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#439 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#440 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#441 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#442 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#443 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#444 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#445 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#446 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#447 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#448 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#449 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#450 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#451 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#452 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#453 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#454 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#455 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#456 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#457 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[32]/C is not reached by a timing clock +Related violations: + +TIMING-17#458 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[33]/C is not reached by a timing clock +Related violations: + +TIMING-17#459 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[34]/C is not reached by a timing clock +Related violations: + +TIMING-17#460 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[35]/C is not reached by a timing clock +Related violations: + +TIMING-17#461 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[36]/C is not reached by a timing clock +Related violations: + +TIMING-17#462 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[37]/C is not reached by a timing clock +Related violations: + +TIMING-17#463 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[38]/C is not reached by a timing clock +Related violations: + +TIMING-17#464 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[39]/C is not reached by a timing clock +Related violations: + +TIMING-17#465 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#466 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[40]/C is not reached by a timing clock +Related violations: + +TIMING-17#467 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[41]/C is not reached by a timing clock +Related violations: + +TIMING-17#468 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[42]/C is not reached by a timing clock +Related violations: + +TIMING-17#469 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[43]/C is not reached by a timing clock +Related violations: + +TIMING-17#470 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[44]/C is not reached by a timing clock +Related violations: + +TIMING-17#471 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[45]/C is not reached by a timing clock +Related violations: + +TIMING-17#472 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[46]/C is not reached by a timing clock +Related violations: + +TIMING-17#473 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[47]/C is not reached by a timing clock +Related violations: + +TIMING-17#474 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[48]/C is not reached by a timing clock +Related violations: + +TIMING-17#475 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[49]/C is not reached by a timing clock +Related violations: + +TIMING-17#476 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#477 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[50]/C is not reached by a timing clock +Related violations: + +TIMING-17#478 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[51]/C is not reached by a timing clock +Related violations: + +TIMING-17#479 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[52]/C is not reached by a timing clock +Related violations: + +TIMING-17#480 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[53]/C is not reached by a timing clock +Related violations: + +TIMING-17#481 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[54]/C is not reached by a timing clock +Related violations: + +TIMING-17#482 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[55]/C is not reached by a timing clock +Related violations: + +TIMING-17#483 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[56]/C is not reached by a timing clock +Related violations: + +TIMING-17#484 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[57]/C is not reached by a timing clock +Related violations: + +TIMING-17#485 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[58]/C is not reached by a timing clock +Related violations: + +TIMING-17#486 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[59]/C is not reached by a timing clock +Related violations: + +TIMING-17#487 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#488 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[60]/C is not reached by a timing clock +Related violations: + +TIMING-17#489 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[61]/C is not reached by a timing clock +Related violations: + +TIMING-17#490 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[62]/C is not reached by a timing clock +Related violations: + +TIMING-17#491 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[63]/C is not reached by a timing clock +Related violations: + +TIMING-17#492 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#493 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#494 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#495 Critical Warning +Non-clocked sequential cell +The clock pin mul/result_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#496 Critical Warning +Non-clocked sequential cell +The clock pin mul_s_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#497 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#498 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#499 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#500 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#501 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#502 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#503 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#504 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#505 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#506 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#507 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#508 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#509 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#510 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#511 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#512 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#513 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#514 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#515 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#516 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#517 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#518 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#519 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#520 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#521 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#522 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#523 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#524 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#525 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#526 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#527 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#528 Critical Warning +Non-clocked sequential cell +The clock pin pc_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#529 Critical Warning +Non-clocked sequential cell +The clock pin readreg_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#530 Critical Warning +Non-clocked sequential cell +The clock pin readreg_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#531 Critical Warning +Non-clocked sequential cell +The clock pin readreg_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#532 Critical Warning +Non-clocked sequential cell +The clock pin readreg_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#533 Critical Warning +Non-clocked sequential cell +The clock pin readreg_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#534 Critical Warning +Non-clocked sequential cell +The clock pin write_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#535 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#536 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#537 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#538 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#539 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#540 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#541 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#542 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#543 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#544 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#545 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#546 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#547 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#548 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#549 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#550 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#551 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#552 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#553 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#554 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#555 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#556 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#557 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#558 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#559 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#560 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#561 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#562 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#563 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#564 Critical Warning +Non-clocked sequential cell +The clock pin writeaddr_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#565 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#566 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#567 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#568 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#569 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#570 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#571 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#572 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#573 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#574 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#575 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#576 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#577 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#578 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#579 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#580 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#581 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#582 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#583 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#584 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#585 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#586 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#587 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#588 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#589 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#590 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#591 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#592 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#593 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#594 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#595 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#596 Critical Warning +Non-clocked sequential cell +The clock pin writedata_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#597 Critical Warning +Non-clocked sequential cell +The clock pin writemask_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#598 Critical Warning +Non-clocked sequential cell +The clock pin writemask_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#599 Critical Warning +Non-clocked sequential cell +The clock pin writemask_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#600 Critical Warning +Non-clocked sequential cell +The clock pin writemask_reg[3]/C is not reached by a timing clock +Related violations: + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.rpx b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.rpx new file mode 100644 index 0000000000000000000000000000000000000000..ceebe31ad59751dffe8d075a0f88497d15d6435b Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_methodology_drc_routed.rpx differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_opt.dcp b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_opt.dcp new file mode 100644 index 0000000000000000000000000000000000000000..87972ae7824050c3347d0d57027e74f234d155f4 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_opt.dcp differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_physopt.dcp b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_physopt.dcp new file mode 100644 index 0000000000000000000000000000000000000000..933c327543954edecff599b72b706bfc01ec55ec Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_physopt.dcp differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_placed.dcp b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_placed.dcp new file mode 100644 index 0000000000000000000000000000000000000000..3c15a697b1593be5bae3966ffafa8e409b75cbaf Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_placed.dcp differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_routed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_routed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..b6cd8afb0996d3892012d304639405ffb9f9819b --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_routed.rpt @@ -0,0 +1,148 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:36:11 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_power -file riscv_core_power_routed.rpt -pb riscv_core_power_summary_routed.pb -rpx riscv_core_power_routed.rpx +| Design : riscv_core +| Device : xc7k70tfbv484-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+----------------------------------+ +| Total On-Chip Power (W) | 79.599 (Junction temp exceeded!) | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 78.569 | +| Device Static (W) | 1.029 | +| Effective TJA (C/W) | 2.5 | +| Max Ambient (C) | 0.0 | +| Junction Temperature (C) | 125.0 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+----------------------------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 10.889 | 3279 | --- | --- | +| LUT as Logic | 10.003 | 2121 | 41000 | 5.17 | +| CARRY4 | 0.624 | 166 | 10250 | 1.62 | +| Register | 0.255 | 600 | 82000 | 0.73 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| F7/F8 Muxes | <0.001 | 3 | 41000 | <0.01 | +| Others | 0.000 | 5 | --- | --- | +| Signals | 13.775 | 2697 | --- | --- | +| I/O | 53.905 | 284 | 285 | 99.65 | +| Static Power | 1.029 | | | | +| Total | 79.599 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 25.927 | 25.053 | 0.874 | NA | Unspecified | NA | +| Vccaux | 1.800 | 4.424 | 4.373 | 0.051 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 25.359 | 25.358 | 0.001 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.025 | 0.000 | 0.025 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.5 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.2 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------------+-----------+ +| Name | Power (W) | ++------------+-----------+ +| riscv_core | 78.569 | +| div | 5.037 | +| mul | 5.937 | ++------------+-----------+ + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_routed.rpx b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_routed.rpx new file mode 100644 index 0000000000000000000000000000000000000000..ed1ee453e1d108b5367af3daa22b11bf2357bffc Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_routed.rpx differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_summary_routed.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_summary_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..d2c6ddc326665e972a66ffca0a436fd85b30a192 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_summary_routed.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_route_status.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_route_status.pb new file mode 100644 index 0000000000000000000000000000000000000000..3c8c93c574f381651423665d05823c8e2df0c8ee Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_route_status.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_route_status.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_route_status.rpt new file mode 100644 index 0000000000000000000000000000000000000000..e40d308a9d1b63c4eaa7b52a9c9ca53bdadf0828 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 4147 : + # of nets not needing routing.......... : 1448 : + # of internally routed nets........ : 1448 : + # of routable nets..................... : 2699 : + # of fully routed nets............. : 2699 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_routed.dcp b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_routed.dcp new file mode 100644 index 0000000000000000000000000000000000000000..d77038e197aa03461465186a465654a96f613c85 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_routed.dcp differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..4526e931ea09401a4ac23b3ff63beaccf3b3ae95 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..70acab42710e9fb161b896632e455ce56f2c0844 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.rpt @@ -0,0 +1,187 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:36:11 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file riscv_core_timing_summary_routed.rpt -pb riscv_core_timing_summary_routed.pb -rpx riscv_core_timing_summary_routed.rpx -warn_on_violation +| Design : riscv_core +| Device : 7k70t-fbv484 +| Speed File : -1 PRODUCTION 1.12 2017-02-17 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +Rule Severity Description Violations +--------- ---------------- --------------------------- ---------- +TIMING-17 Critical Warning Non-clocked sequential cell 600 + +Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (600) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (1450) +5. checking no_input_delay (95) +6. checking no_output_delay (184) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (600) +-------------------------- + There are 600 register/latch pins with no clock driven by root clock pin: wClk (HIGH) + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (1450) +--------------------------------------------------- + There are 1450 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (95) +------------------------------- + There are 95 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (184) +--------------------------------- + There are 184 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.rpx b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.rpx new file mode 100644 index 0000000000000000000000000000000000000000..36dfac0754357859d581573c23d4bc6f4aabfe75 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.rpx differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_utilization_placed.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_utilization_placed.pb new file mode 100644 index 0000000000000000000000000000000000000000..034f6c999c0196a4f98c64536a161aea8a84e3af Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_utilization_placed.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_utilization_placed.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_utilization_placed.rpt new file mode 100644 index 0000000000000000000000000000000000000000..a4621bbcb28d7c2607b9e5cb1240bf7a297fe492 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_utilization_placed.rpt @@ -0,0 +1,213 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:35:58 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_utilization -file riscv_core_utilization_placed.rpt -pb riscv_core_utilization_placed.pb +| Design : riscv_core +| Device : 7k70tfbv484-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs | 2121 | 0 | 0 | 41000 | 5.17 | +| LUT as Logic | 2121 | 0 | 0 | 41000 | 5.17 | +| LUT as Memory | 0 | 0 | 0 | 13400 | 0.00 | +| Slice Registers | 600 | 0 | 0 | 82000 | 0.73 | +| Register as Flip Flop | 600 | 0 | 0 | 82000 | 0.73 | +| Register as Latch | 0 | 0 | 0 | 82000 | 0.00 | +| F7 Muxes | 3 | 0 | 0 | 20500 | 0.01 | +| F8 Muxes | 0 | 0 | 0 | 10250 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 29 | Yes | Set | - | +| 571 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+------+-------+------------+-----------+-------+ +| Slice | 597 | 0 | 0 | 10250 | 5.82 | +| SLICEL | 347 | 0 | | | | +| SLICEM | 250 | 0 | | | | +| LUT as Logic | 2121 | 0 | 0 | 41000 | 5.17 | +| using O5 output only | 0 | | | | | +| using O6 output only | 1738 | | | | | +| using O5 and O6 | 383 | | | | | +| LUT as Memory | 0 | 0 | 0 | 13400 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | | +| LUT as Shift Register | 0 | 0 | | | | +| Slice Registers | 600 | 0 | 0 | 82000 | 0.73 | +| Register driven from within the Slice | 475 | | | | | +| Register driven from outside the Slice | 125 | | | | | +| LUT in front of the register is unused | 7 | | | | | +| LUT in front of the register is used | 118 | | | | | +| Unique Control Sets | 22 | | 0 | 10250 | 0.21 | ++--------------------------------------------+------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 | +| RAMB18 | 0 | 0 | 0 | 270 | 0.00 | ++----------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 240 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 284 | 0 | 0 | 285 | 99.65 | +| IOB Master Pads | 138 | | | | | +| IOB Slave Pads | 136 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 275 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 0 | 1 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT6 | 1047 | LUT | +| FDRE | 571 | Flop & Latch | +| LUT4 | 494 | LUT | +| LUT5 | 313 | LUT | +| LUT2 | 242 | LUT | +| LUT3 | 211 | LUT | +| LUT1 | 197 | LUT | +| OBUF | 186 | IO | +| CARRY4 | 166 | CarryLogic | +| IBUF | 98 | IO | +| FDSE | 29 | Flop & Latch | +| MUXF7 | 3 | MuxFx | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/route_design.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/route_design.pb new file mode 100644 index 0000000000000000000000000000000000000000..b111795716c26fdbcc5bde22ff452144d0a0b79f Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/route_design.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/rundef.js b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/rundef.js new file mode 100644 index 0000000000000000000000000000000000000000..6d2abc845a6365019ec524f3d6858d0d7f0ea75a --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.1/bin;"; +} else { + PathVal = "C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log riscv_core.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/runme.bat b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/runme.bat new file mode 100644 index 0000000000000000000000000000000000000000..6c4f290a63586cde498658f43547b8444ce510ef --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/runme.sh b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/runme.sh new file mode 100644 index 0000000000000000000000000000000000000000..df14bc7877c22650b9c0d7c5c2ddb48aa82cb23d --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.1/bin +else + PATH=C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log riscv_core.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/vivado.jou b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/vivado.jou new file mode 100644 index 0000000000000000000000000000000000000000..0aa9ceb28621bfc2724aa6210e4856645f9058d4 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Sep 7 20:35:31 2021 +# Process ID: 15884 +# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1 +# Command line: vivado.exe -log riscv_core.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace +# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.vdi +# Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source riscv_core.tcl -notrace diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/vivado.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..770adf5b5389ab2debafc4569a95ce40d2e2354d Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/vivado.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/.Vivado_Synthesis.queue.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/.vivado.begin.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000000000000000000000000000000000000..9d86ce314c1385484bc26a9dcdf07d00a21417c2 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/.vivado.end.rst b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/ISEWrap.js b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000000000000000000000000000000000000..db0a51077cfb3a198d0bcb1b84080b9210b5b593 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/ISEWrap.js @@ -0,0 +1,269 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/ISEWrap.sh b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000000000000000000000000000000000000..4fa5b5cbed982e5033e8d24e5538095bdd6fc003 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/ISEWrap.sh @@ -0,0 +1,73 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/__synthesis_is_complete__ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/gen_run.xml b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/gen_run.xml new file mode 100644 index 0000000000000000000000000000000000000000..b07ad22bda431490a1d143cc2682951bbf53833c --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/gen_run.xml @@ -0,0 +1,74 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/htr.txt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/htr.txt new file mode 100644 index 0000000000000000000000000000000000000000..aaa9c52a3bf8dd0c9ce9e519fa4a4c5315ef5053 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log riscv_core.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source riscv_core.tcl diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/project.wdf b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/project.wdf new file mode 100644 index 0000000000000000000000000000000000000000..af7d5b62849f64fef438cd3f81ed2eb47fe9c574 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3764356431346564313833653430343962656265633534323531626437333330:506172656e742050412070726f6a656374204944:00 +eof:254497829 diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.dcp b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.dcp new file mode 100644 index 0000000000000000000000000000000000000000..d02b1f948e5b5822223e5e86875a320b953262e7 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.dcp differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.tcl b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c2c8e312c0d3eef03b48cb29b0c3087f9b2355af --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.tcl @@ -0,0 +1,122 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "synth_1" START { ROLLUP_AUTO } +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7k70tfbv484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt [current_project] +set_property parent.project_path D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_verilog -library xil_defaultlib { + D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/div32.v + D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/mul32.v + D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v +} +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top riscv_core -part xc7k70tfbv484-1 +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef riscv_core.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "synth_1_synth_report_utilization_0" "report_utilization -file riscv_core_utilization_synth.rpt -pb riscv_core_utilization_synth.pb" +OPTRACE "synth reports" END { } +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "synth_1" END { } diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.vds b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.vds new file mode 100644 index 0000000000000000000000000000000000000000..6f33d92826c315c6955ce8ef80b6aa4609c85bb4 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.vds @@ -0,0 +1,272 @@ +#----------------------------------------------------------- +# Vivado v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Sep 7 20:34:47 2021 +# Process ID: 4436 +# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1 +# Command line: vivado.exe -log riscv_core.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source riscv_core.tcl +# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.vds +# Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source riscv_core.tcl -notrace +Command: synth_design -top riscv_core -part xc7k70tfbv484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k70t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k70t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 11312 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'riscv_core' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:60] +INFO: [Synth 8-6157] synthesizing module 'mul32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/mul32.v:34] +INFO: [Synth 8-6155] done synthesizing module 'mul32' (1#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/mul32.v:34] +WARNING: [Synth 8-689] width (32) of port connection 'wStart' does not match port width (1) of module 'mul32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:191] +INFO: [Synth 8-6157] synthesizing module 'div32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/div32.v:34] +INFO: [Synth 8-6155] done synthesizing module 'div32' (2#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/div32.v:34] +WARNING: [Synth 8-689] width (32) of port connection 'wStart' does not match port width (1) of module 'div32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:270] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:371] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:440] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:449] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:438] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:478] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:554] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:649] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:791] +INFO: [Synth 8-226] default block is never used [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:925] +INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:788] +WARNING: [Synth 8-567] referenced signal 'csr_r' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:777] +WARNING: [Synth 8-567] referenced signal 'imm_s' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:777] +INFO: [Synth 8-6155] done synthesizing module 'riscv_core' (3#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:60] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k70tfbv484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7k70tfbv484-1 +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'riscv_core' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE4 | 0000 | 0000 + iSTATE3 | 0001 | 0001 + iSTATE0 | 0010 | 0011 + iSTATE | 0011 | 0100 + iSTATE9 | 0100 | 0101 + iSTATE7 | 0101 | 0110 + iSTATE6 | 0110 | 0111 + iSTATE8 | 0111 | 1000 + iSTATE5 | 1000 | 1001 + iSTATE2 | 1001 | 1010 + iSTATE1 | 1010 | 0010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'riscv_core' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 3 Input 64 Bit Adders := 1 + 2 Input 64 Bit Adders := 1 + 2 Input 32 Bit Adders := 9 + 3 Input 32 Bit Adders := 1 + 2 Input 6 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 2 + 2 Input 1 Bit XORs := 1 ++---Registers : + 64 Bit Registers := 3 + 32 Bit Registers := 11 + 6 Bit Registers := 1 + 5 Bit Registers := 1 + 4 Bit Registers := 1 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 64 Bit Muxes := 4 + 2 Input 32 Bit Muxes := 30 + 10 Input 32 Bit Muxes := 1 + 4 Input 32 Bit Muxes := 12 + 3 Input 32 Bit Muxes := 2 + 8 Input 32 Bit Muxes := 2 + 5 Input 32 Bit Muxes := 2 + 6 Input 32 Bit Muxes := 1 + 3 Input 24 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 2 + 4 Input 8 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 7 + 8 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 1 + 6 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 2 + 4 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 6 Input 4 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 9 + 11 Input 4 Bit Muxes := 1 + 3 Input 4 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 1 + 8 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 26 + 3 Input 1 Bit Muxes := 6 + 4 Input 1 Bit Muxes := 3 + 7 Input 1 Bit Muxes := 2 + 10 Input 1 Bit Muxes := 1 + 5 Input 1 Bit Muxes := 2 + 11 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 166| +|3 |LUT1 | 200| +|4 |LUT2 | 242| +|5 |LUT3 | 211| +|6 |LUT4 | 494| +|7 |LUT5 | 313| +|8 |LUT6 | 1047| +|9 |MUXF7 | 3| +|10 |FDRE | 571| +|11 |FDSE | 29| +|12 |IBUF | 98| +|13 |OBUF | 186| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 3561| +|2 | div |div32 | 589| +|3 | mul |mul32 | 672| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 4 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1134.922 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 169 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1134.922 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete, checksum: e32a7290 +INFO: [Common 17-83] Releasing license: Synthesis +30 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1134.922 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file riscv_core_utilization_synth.rpt -pb riscv_core_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Tue Sep 7 20:35:12 2021... diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core_utilization_synth.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..5bfbba3ada932759abdc985ab7249713e61ad95d Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core_utilization_synth.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core_utilization_synth.rpt b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core_utilization_synth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..020691c5ffbd6c014a72e837d0828743f659b72a --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core_utilization_synth.rpt @@ -0,0 +1,185 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021 +| Date : Tue Sep 7 20:35:12 2021 +| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200) +| Command : report_utilization -file riscv_core_utilization_synth.rpt -pb riscv_core_utilization_synth.pb +| Design : riscv_core +| Device : 7k70tfbv484-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 2123 | 0 | 0 | 41000 | 5.18 | +| LUT as Logic | 2123 | 0 | 0 | 41000 | 5.18 | +| LUT as Memory | 0 | 0 | 0 | 13400 | 0.00 | +| Slice Registers | 600 | 0 | 0 | 82000 | 0.73 | +| Register as Flip Flop | 600 | 0 | 0 | 82000 | 0.73 | +| Register as Latch | 0 | 0 | 0 | 82000 | 0.00 | +| F7 Muxes | 3 | 0 | 0 | 20500 | 0.01 | +| F8 Muxes | 0 | 0 | 0 | 10250 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 29 | Yes | Set | - | +| 571 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 | +| RAMB18 | 0 | 0 | 0 | 270 | 0.00 | ++----------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 240 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 284 | 0 | 0 | 285 | 99.65 | +| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 275 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 0 | 1 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT6 | 1047 | LUT | +| FDRE | 571 | Flop & Latch | +| LUT4 | 494 | LUT | +| LUT5 | 313 | LUT | +| LUT2 | 242 | LUT | +| LUT3 | 211 | LUT | +| LUT1 | 200 | LUT | +| OBUF | 186 | IO | +| CARRY4 | 166 | CarryLogic | +| IBUF | 98 | IO | +| FDSE | 29 | Flop & Latch | +| MUXF7 | 3 | MuxFx | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/rundef.js b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/rundef.js new file mode 100644 index 0000000000000000000000000000000000000000..7d7a976ca325d31f36f3f875a34bd740f05236e3 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.1/bin;"; +} else { + PathVal = "C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log riscv_core.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source riscv_core.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/runme.bat b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/runme.bat new file mode 100644 index 0000000000000000000000000000000000000000..6c4f290a63586cde498658f43547b8444ce510ef --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/runme.sh b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/runme.sh new file mode 100644 index 0000000000000000000000000000000000000000..bf5c875adee4c0dc759f4ec8f56f1e54671e0294 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.1/bin +else + PATH=C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log riscv_core.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source riscv_core.tcl diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/vivado.jou b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/vivado.jou new file mode 100644 index 0000000000000000000000000000000000000000..94ec18bc64eabd7df089d26bb800cfd5697d8711 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Sep 7 20:34:47 2021 +# Process ID: 4436 +# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1 +# Command line: vivado.exe -log riscv_core.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source riscv_core.tcl +# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.vds +# Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source riscv_core.tcl -notrace diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/vivado.pb b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..fec5d460620cefc8d6c919e719dd92fe29243ae6 Binary files /dev/null and b/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/vivado.pb differ diff --git a/examples/hdl4se_riscv/z7/project_2/project_2.xpr b/examples/hdl4se_riscv/z7/project_2/project_2.xpr new file mode 100644 index 0000000000000000000000000000000000000000..f7619fefffbc6ed5f73232c93b686c238b8031f6 --- /dev/null +++ b/examples/hdl4se_riscv/z7/project_2/project_2.xpr @@ -0,0 +1,246 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +