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提交 5a9a84a9 编写于 作者: 饶先宏's avatar 饶先宏
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202109151549 watch dog

上级 259f8d21
展开全部 隐藏空白更改
内联 并排
Showing with 523879 addition and 55747 deletion
examples/hdl4se_riscv/doc/xilinx_readme.txt 0 → 100644
浏览文件 @ 5a9a84a9
1.生成工程
2.增加设计文件riscv，led-key
3.增加顶层block生成端口
4.生成顶层HDL包装，设置为工程顶层模型
5.增加ram4KB IP，
module name : ram4KB
Byte Write Enable(on), byte size=8
Width=32, Depth=1024, Primitive Output Register(off)
Load Init File(on), coe file
Synthesis Option: Global(on)
Generate
6.增加module riscv，led-key
7.增加UART IP
8.自动连接各个IP
9.修改Adress Map
uart: f0001000, 4KB
led_key: f0000000, 4KB
其他可以使用00100000开始的任何地址（内存部分预留了1MB地址空间）
10.设置端口管脚
11.生成烧写文件
应用修改：
1.RISCV编译工具链
2.软件修改
3.ram大小跟硬件的关系
\ No newline at end of file
examples/hdl4se_riscv/test_code/console.c
浏览文件 @ 5a9a84a9
#define UARTADDRESS (unsigned int *)0xf0001000
#define REFFREQ 50000000
#define WATCHDOGSET watchdog_set(REFFREQ)
extern void watchdog_set(unsigned long long food);
static int _canputchar()
{
......@@ -41,7 +44,7 @@ static int _puts(const char* s)
{
while (*s) {
while (_putchar(*s) == -1)
;
WATCHDOGSET;
s++;
}
return 0;
......@@ -58,12 +61,13 @@ static int _gets(char* s, int buflen)
if (ch != -1) {
s[ind++] = ch;
while(_putchar(ch) == -1) /* */
;
WATCHDOGSET;
if (ind >= buflen - 1)
break;
if (ch == '\n' || ch == '\r')
break;
}
WATCHDOGSET;
} while (1);
s[ind] = 0;
return ind;
......@@ -197,31 +201,35 @@ static int _s2d(char* buf, char** next)
return ret;
}
static int _s2h(char* buf, char** next)
static unsigned int _s2h(char* buf, char** next)
{
int state;
int ret;
unsigned int ret;
state = 0;
ret = 0;
ret = 0xffffffff;
while (*buf) {
int ch;
unsigned int ch;
ch = *buf;
if (ch >= '0' && ch <= '9') {
if (state == 0)
ret = 0;
state = 1;
ret = (ret << 4) + ch - '0';
ret = (ret << 4) | (ch - '0');
}
else if (ch >= 'a' && ch <= 'f') {
if (state == 0)
ret = 0;
state = 1;
ret = (ret << 4) + ch - 'a' + 10;
ret = (ret << 4) | (ch - 'a' + 10);
}
else if (ch >= 'A' && ch <= 'F') {
if (state == 0)
ret = 0;
state = 1;
ret = (ret << 4) + ch - 'A' + 10;
ret = (ret << 4) | (ch - 'A' + 10);
}
else {
if (state == 0)
state = 1;
else
if (state == 1)
break;
}
buf++;
......@@ -289,7 +297,7 @@ do { \
_uartaddr[3] = REFFREQ / (baud); \
} while (0)
static unsigned int displayaddr = 0x1;
static unsigned int displayaddr;
static void dispmem()
{
int i, j, len;
......@@ -324,7 +332,7 @@ static void dispmem()
buf[1] = 0;
_puts(buf);
}
_puts("|\n");
_puts("|\n\r");
startaddr += 16;
if ( (startaddr & 0xff) == 0)
break;
......@@ -333,7 +341,6 @@ static void dispmem()
displayaddr = startaddr;
}
static void printhelp()
{
/*
......@@ -356,11 +363,12 @@ int main(int argc, char* argv[])
} while (1);
#else
_buadrateset(115200);
displayaddr = 0;
do {
char buf[40];
WATCHDOGSET;
if (_canputchar()) {
_puts(">>");
_puts("riscv>>");
}
count = count + 1;
*(unsigned int*)0xf0000004 = count;
......@@ -371,31 +379,31 @@ int main(int argc, char* argv[])
}
count = count + 1;
*(unsigned int*)0xf0000004 = count;
WATCHDOGSET;
} while (1);
_puts("\n\r:");
_puts(buf);
_puts("\n\r");
if (buf[0] == 'b') {
int baud = _s2d(buf+2, 0);
if (baud > 0) {
_buadrateset(baud);
}
else {
printhelp();
}
}
else if (buf[0] == 'd') {
int addr = _s2h(buf + 2, 0);
if (addr > 0) {
if (buf[0] == 'd') {
unsigned int addr = _s2h(buf + 2, 0);
if (addr != 0xffffffff) {
displayaddr = addr;
}
dispmem();
}
else if (buf[0] == 'w') {
else if (buf[0] == 'f') {
char* next;
int addr = _s2h(buf + 2, &next);
int value = _s2h(next, &next);
int width = _s2h(next, &next);
unsigned int addr = _s2h(buf + 2, &next);
unsigned int value = _s2h(next, &next);
unsigned int len = _s2h(next, &next);
unsigned char* baddr = (unsigned char*)addr;
while (len-- > 0)
*baddr++ = value;
} else if (buf[0] == 'w') {
char* next;
unsigned int addr = _s2h(buf + 2, &next);
unsigned int value = _s2h(next, &next);
unsigned int width = _s2h(next, &next);
if (width == 1) {
*(char*)addr = value;
}
......
examples/hdl4se_riscv/test_code/csr.S
浏览文件 @ 5a9a84a9
.macro DEFINECSRGET1 csrname, csrno
.macro DEFINECSRGET csrname, csrno
.global \csrname
.align 2
.type \csrname, @function
......@@ -10,7 +10,18 @@
.size \csrname, .-\csrname
.endm
.macro DEFINECSRGETCLEAR1 csrname, csrno
.macro DEFINECSRSET csrname, csrno
.global \csrname
.align 2
.type \csrname, @function
\csrname:
csrrw a1, \csrno+0x80, a1
csrrw a0, \csrno, a0
jr ra
.size \csrname, .-\csrname
.endm
.macro DEFINECSRGETCLEAR csrname, csrno
.global \csrname
.align 2
.type \csrname, @function
......@@ -22,10 +33,10 @@
.endm
.macro DEFINECSRGETCLEAR csrname, csrno
.macro DEFINECSRGETCLEAR1 csrname, csrno
.endm
.macro DEFINECSRGET csrname, csrno
.macro DEFINECSRGET1 csrname, csrno
.endm
.text
......@@ -39,29 +50,30 @@ __start:
.size __start, .-__start
DEFINECSRGET cycle, 0xc00
DEFINECSRGETCLEAR cycle_clear, 0xc00
DEFINECSRGET instrcount, 0xc02
DEFINECSRGETCLEAR instrcount_clear, 0xc02
DEFINECSRGET get_counter_addsub, 0xc20
DEFINECSRGETCLEAR get_counter_addsub_clear, 0xc20
DEFINECSRGET get_counter_mul, 0xc21
DEFINECSRGETCLEAR get_counter_mul_clear, 0xc21
DEFINECSRGET get_counter_div, 0xc22
DEFINECSRGETCLEAR get_counter_div_clear, 0xc22
DEFINECSRGET get_counter_ld, 0xc23
DEFINECSRGETCLEAR get_counter_ld_clear, 0xc23
DEFINECSRGET get_counter_st, 0xc24
DEFINECSRGETCLEAR get_counter_st_clear, 0xc24
DEFINECSRGET get_counter_jmp, 0xc25
DEFINECSRGETCLEAR get_counter_jmp_clear, 0xc25
DEFINECSRGET get_counter_j, 0xc26
DEFINECSRGETCLEAR get_counter_j_clear, 0xc26
DEFINECSRGET get_counter_alui, 0xc27
DEFINECSRGETCLEAR get_counter_alui_clear, 0xc27
DEFINECSRGET get_counter_alu, 0xc28
DEFINECSRGETCLEAR get_counter_alu_clear, 0xc28
DEFINECSRGET clear_all_counter, 0xc40
DEFINECSRGET stop_all_counter, 0xc41
DEFINECSRSET watchdog_set, 0xb20
DEFINECSRGET1 cycle, 0xc00
DEFINECSRGETCLEAR1 cycle_clear, 0xc00
DEFINECSRGET1 instrcount, 0xc02
DEFINECSRGETCLEAR1 instrcount_clear, 0xc02
DEFINECSRGET1 get_counter_addsub, 0xc20
DEFINECSRGETCLEAR1 get_counter_addsub_clear, 0xc20
DEFINECSRGET1 get_counter_mul, 0xc21
DEFINECSRGETCLEAR1 get_counter_mul_clear, 0xc21
DEFINECSRGET1 get_counter_div, 0xc22
DEFINECSRGETCLEAR1 get_counter_div_clear, 0xc22
DEFINECSRGET1 get_counter_ld, 0xc23
DEFINECSRGETCLEAR1 get_counter_ld_clear, 0xc23
DEFINECSRGET1 get_counter_st, 0xc24
DEFINECSRGETCLEAR1 get_counter_st_clear, 0xc24
DEFINECSRGET1 get_counter_jmp, 0xc25
DEFINECSRGETCLEAR1 get_counter_jmp_clear, 0xc25
DEFINECSRGET1 get_counter_j, 0xc26
DEFINECSRGETCLEAR1 get_counter_j_clear, 0xc26
DEFINECSRGET1 get_counter_alui, 0xc27
DEFINECSRGETCLEAR1 get_counter_alui_clear, 0xc27
DEFINECSRGET1 get_counter_alu, 0xc28
DEFINECSRGETCLEAR1 get_counter_alu_clear, 0xc28
DEFINECSRGET1 clear_all_counter, 0xc40
DEFINECSRGET1 stop_all_counter, 0xc41
examples/hdl4se_riscv/test_code/test.cod
浏览文件 @ 5a9a84a9
@00000000
37 11 00 00 EF 00 10 23 6F F0 9F FF
@0000000C
37 11 00 00 EF 00 10 19 6F F0 9F FF F3 95 05 BA
73 15 05 B2 67 80 00 00
@00000018
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 17 00 F0
23 26 F4 FE 83 27 C4 FE 93 87 87 00 83 A7 07 00
23 24 F4 FE 83 27 84 FE 93 F7 87 00 93 B7 17 00
93 F7 F7 0F 13 85 07 00 03 24 C1 01 13 01 01 02
67 80 00 00
@00000050
@0000005C
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 17 00 F0
23 26 F4 FE 83 27 C4 FE 93 87 87 00 83 A7 07 00
23 24 F4 FE 83 27 84 FE 93 F7 17 00 93 87 F7 FF
93 B7 17 00 93 F7 F7 0F 13 85 07 00 03 24 C1 01
13 01 01 02 67 80 00 00
@00000098
@000000A4
13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03
23 2E A4 FC B7 17 00 F0 23 26 F4 FE EF F0 9F F5
93 07 05 00 63 8E 07 00 83 27 C4 FE 93 87 47 00
03 27 C4 FD 23 A0 E7 00 93 07 00 00 6F 00 80 00
93 07 F0 FF 13 85 07 00 83 20 C1 02 03 24 81 02
13 01 01 03 67 80 00 00
@000000F0
@000000FC
13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02
B7 17 00 F0 23 26 F4 FE EF F0 9F F4 93 07 05 00
63 88 07 00 83 27 C4 FE 83 A7 07 00 6F 00 80 00
93 07 F0 FF 13 85 07 00 83 20 C1 01 03 24 81 01
13 01 01 02 67 80 00 00
@00000138
@00000144
13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02
23 26 A4 FE 6F 00 00 03 13 00 00 00 83 27 C4 FE
83 C7 07 00 13 85 07 00 EF F0 9F F3 13 07 05 00
93 07 F0 FF E3 04 F7 FE 83 27 C4 FE 93 87 17 00
23 26 F4 FE 83 27 C4 FE 83 C7 07 00 E3 96 07 FC
93 07 00 00 13 85 07 00 83 20 C1 01 03 24 81 01
13 01 01 02 67 80 00 00
@000001A0
23 26 A4 FE 6F 00 C0 03 37 F5 FA 02 13 05 05 08
93 05 00 00 EF F0 5F EA 83 27 C4 FE 83 C7 07 00
13 85 07 00 EF F0 DF F2 13 07 05 00 93 07 F0 FF
E3 0C F7 FC 83 27 C4 FE 93 87 17 00 23 26 F4 FE
83 27 C4 FE 83 C7 07 00 E3 98 07 FC 93 07 00 00
13 85 07 00 83 20 C1 01 03 24 81 01 13 01 01 02
67 80 00 00
@000001B8
13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03
23 2E A4 FC 23 2C B4 FC 23 26 04 FE 03 27 84 FD
93 07 10 00 63 C6 E7 00 93 07 00 00 6F 00 80 09
EF F0 1F F2 23 24 A4 FE 03 27 84 FE 93 07 F0 FF
E3 08 F7 FE 83 27 C4 FE 13 87 17 00 23 26 E4 FE
93 07 10 00 63 C6 E7 00 93 07 00 00 6F 00 80 0B
EF F0 5F F1 23 24 A4 FE 03 27 84 FE 93 07 F0 FF
63 0C F7 06 83 27 C4 FE 13 87 17 00 23 26 E4 FE
13 87 07 00 83 27 C4 FD B3 87 E7 00 03 27 84 FE
13 77 F7 0F 23 80 E7 00 13 00 00 00 03 25 84 FE
EF F0 9F E8 13 07 05 00 93 07 F0 FF E3 08 F7 FE
83 27 84 FD 93 87 F7 FF 03 27 C4 FE 63 50 F7 02
03 27 84 FE 93 07 A0 00 63 0C F7 00 03 27 84 FE
93 07 D0 00 63 06 F7 00 6F F0 9F F8 13 00 00 00
13 77 F7 0F 23 80 E7 00 6F 00 40 01 37 F5 FA 02
13 05 05 08 93 05 00 00 EF F0 DF DD 03 25 84 FE
EF F0 DF E6 13 07 05 00 93 07 F0 FF E3 00 F7 FE
83 27 84 FD 93 87 F7 FF 03 27 C4 FE 63 58 F7 02
03 27 84 FE 93 07 A0 00 63 04 F7 02 03 27 84 FE
93 07 D0 00 63 0E F7 00 37 F5 FA 02 13 05 05 08
93 05 00 00 EF F0 1F D9 6F F0 9F F6 13 00 00 00
83 27 C4 FE 03 27 C4 FD B3 07 F7 00 23 80 07 00
83 27 C4 FE 13 85 07 00 83 20 C1 02 03 24 81 02
13 01 01 03 67 80 00 00
@00000278
@000002B0
13 01 01 FC 23 2E 81 02 13 04 01 04 23 26 A4 FC
23 24 B4 FC 23 24 04 FE 23 22 04 FE 83 27 84 FC
63 DA 07 00 83 27 84 FC B3 07 F0 40 23 24 F4 FC
......@@ -74,7 +78,7 @@ A3 0F F4 FC 83 27 04 FE 03 27 C4 FC 33 07 F7 00
83 27 84 FE 03 27 C4 FC B3 07 F7 00 23 80 07 00
83 27 84 FE 13 85 07 00 03 24 C1 03 13 01 01 04
67 80 00 00
@000003FC
@00000434
13 01 01 FB 23 26 81 04 13 04 01 05 23 26 A4 FC
23 20 B4 FC 23 22 C4 FC 23 24 D4 FC 93 07 07 00
A3 0F F4 FA 23 24 04 FE 6F 00 00 09 83 27 04 FC
......@@ -102,154 +106,143 @@ B3 07 F7 00 93 D7 17 40 13 87 07 00 83 27 C4 FE
E3 C0 E7 F8 83 27 84 FE 03 27 C4 FC B3 07 F7 00
23 80 07 00 83 27 84 FE 13 85 07 00 03 24 C1 04
13 01 01 05 67 80 00 00
@000005A4
@000005DC
13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC
23 2C B4 FC 23 26 04 FE 23 24 04 FE 93 07 10 00
23 22 F4 FE 6F 00 C0 08 83 27 C4 FD 83 C7 07 00
23 20 F4 FE 03 27 04 FE 93 07 F0 02 63 D2 E7 04
03 27 04 FE 93 07 90 03 63 CC E7 02 03 27 84 FE
93 07 07 00 93 97 27 00 B3 87 E7 00 93 97 17 00
13 87 07 00 83 27 04 FE B3 07 F7 00 93 87 07 FD
23 24 F4 FE 93 07 10 00 23 26 F4 FE 6F 00 80 02
83 27 C4 FE 63 9E 07 02 03 27 04 FE 93 07 D0 02
63 1A F7 00 93 07 F0 FF 23 22 F4 FE 93 07 10 00
23 26 F4 FE 83 27 C4 FD 93 87 17 00 23 2E F4 FC
83 27 C4 FD 83 C7 07 00 E3 98 07 F6 6F 00 80 00
13 00 00 00 03 27 84 FE 83 27 44 FE B3 07 F7 02
23 24 F4 FE 83 27 84 FD 63 88 07 00 83 27 84 FD
23 2C B4 FC 23 26 04 FE 93 07 F0 FF 23 24 F4 FE
6F 00 00 10 83 27 C4 FD 83 C7 07 00 23 22 F4 FE
03 27 44 FE 93 07 F0 02 63 F0 E7 04 03 27 44 FE
93 07 90 03 63 EA E7 02 83 27 C4 FE 63 94 07 00
23 24 04 FE 93 07 10 00 23 26 F4 FE 83 27 84 FE
13 97 47 00 83 27 44 FE 93 87 07 FD B3 67 F7 00
23 24 F4 FE 6F 00 00 0A 03 27 44 FE 93 07 00 06
63 F0 E7 04 03 27 44 FE 93 07 60 06 63 EA E7 02
83 27 C4 FE 63 94 07 00 23 24 04 FE 93 07 10 00
23 26 F4 FE 83 27 84 FE 13 97 47 00 83 27 44 FE
93 87 97 FA B3 67 F7 00 23 24 F4 FE 6F 00 80 05
03 27 44 FE 93 07 00 04 63 F0 E7 04 03 27 44 FE
93 07 60 04 63 EA E7 02 83 27 C4 FE 63 94 07 00
23 24 04 FE 93 07 10 00 23 26 F4 FE 83 27 84 FE
13 97 47 00 83 27 44 FE 93 87 97 FC B3 67 F7 00
23 24 F4 FE 6F 00 00 01 03 27 C4 FE 93 07 10 00
63 00 F7 02 83 27 C4 FD 93 87 17 00 23 2E F4 FC
83 27 C4 FD 83 C7 07 00 E3 9E 07 EE 6F 00 80 00
13 00 00 00 83 27 84 FD 63 88 07 00 83 27 84 FD
03 27 C4 FD 23 A0 E7 00 83 27 84 FE 13 85 07 00
03 24 C1 02 13 01 01 03 67 80 00 00
@000006A0
13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC
23 2C B4 FC 23 26 04 FE 23 24 04 FE 6F 00 00 0E
83 27 C4 FD 83 C7 07 00 23 22 F4 FE 03 27 44 FE
93 07 F0 02 63 DA E7 02 03 27 44 FE 93 07 90 03
63 C4 E7 02 93 07 10 00 23 26 F4 FE 83 27 84 FE
13 97 47 00 83 27 44 FE B3 07 F7 00 93 87 07 FD
23 24 F4 FE 6F 00 C0 08 03 27 44 FE 93 07 00 06
63 DA E7 02 03 27 44 FE 93 07 60 06 63 C4 E7 02
93 07 10 00 23 26 F4 FE 83 27 84 FE 13 97 47 00
83 27 44 FE B3 07 F7 00 93 87 97 FA 23 24 F4 FE
6F 00 00 05 03 27 44 FE 93 07 00 04 63 DA E7 02
03 27 44 FE 93 07 60 04 63 C4 E7 02 93 07 10 00
23 26 F4 FE 83 27 84 FE 13 97 47 00 83 27 44 FE
B3 07 F7 00 93 87 97 FC 23 24 F4 FE 6F 00 40 01
83 27 C4 FE 63 94 07 02 93 07 10 00 23 26 F4 FE
83 27 C4 FD 93 87 17 00 23 2E F4 FC 83 27 C4 FD
83 C7 07 00 E3 9E 07 F0 6F 00 80 00 13 00 00 00
83 27 84 FD 63 88 07 00 83 27 84 FD 03 27 C4 FD
23 A0 E7 00 83 27 84 FE 13 85 07 00 03 24 C1 02
13 01 01 03 67 80 00 00
@000007D8
@00000738
13 01 01 FB 23 26 11 04 23 24 81 04 23 22 21 05
23 20 31 05 23 2E 41 03 23 2C 51 03 13 04 01 05
B7 17 00 00 83 A7 07 E7 93 F7 07 FF 23 2A F4 FC
B7 17 00 00 83 A7 47 E3 93 F7 07 FF 23 2A F4 FC
23 2C 04 FC 6F 00 C0 1B 83 27 44 FD 13 89 07 00
93 09 00 00 93 07 C4 FB 13 07 00 03 93 06 80 00
93 05 09 00 13 86 09 00 13 85 07 00 EF F0 9F BC
93 07 C4 FB 13 85 07 00 EF F0 9F 8F B7 17 00 00
13 85 87 E2 EF F0 DF 8E 23 2E 04 FC 6F 00 40 0A
93 05 09 00 13 86 09 00 13 85 07 00 EF F0 1F CA
93 07 C4 FB 13 85 07 00 EF F0 5F 9A B7 17 00 00
13 85 87 DE EF F0 9F 99 23 2E 04 FC 6F 00 40 0A
83 27 44 FD 23 26 F4 FC 03 27 C4 FD 83 27 44 FD
33 07 F7 00 B7 17 00 00 83 A7 07 E7 63 7A F7 00
B7 17 00 00 13 85 C7 E2 EF F0 9F 8B 6F 00 00 05
33 07 F7 00 B7 17 00 00 83 A7 47 E3 63 7A F7 00
B7 17 00 00 13 85 C7 DE EF F0 5F 96 6F 00 00 05
83 27 C4 FD 03 27 C4 FC B3 07 F7 00 83 C7 07 00
13 8A 07 00 93 0A 00 00 93 07 C4 FB 13 07 00 03
93 06 20 00 93 05 0A 00 13 86 0A 00 13 85 07 00
EF F0 5F B4 93 07 C4 FB 13 85 07 00 EF F0 5F 87
B7 17 00 00 13 85 07 E3 EF F0 9F 86 03 27 C4 FD
93 07 70 00 63 18 F7 00 B7 17 00 00 13 85 47 E3
EF F0 1F 85 83 27 C4 FD 93 87 17 00 23 2E F4 FC
EF F0 DF C1 93 07 C4 FB 13 85 07 00 EF F0 1F 92
B7 17 00 00 13 85 07 DF EF F0 5F 91 03 27 C4 FD
93 07 70 00 63 18 F7 00 B7 17 00 00 13 85 47 DF
EF F0 DF 8F 83 27 C4 FD 93 87 17 00 23 2E F4 FC
03 27 C4 FD 93 07 F0 00 E3 DC E7 F4 B7 17 00 00
13 85 87 E3 EF F0 DF 82 23 2E 04 FC 6F 00 80 07
13 85 87 DF EF F0 9F 8D 23 2E 04 FC 6F 00 80 07
83 27 44 FD 23 28 F4 FC 83 27 C4 FD 03 27 04 FD
B3 07 F7 00 03 C7 07 00 93 07 F0 01 63 FA E7 02
83 27 C4 FD 03 27 04 FD B3 07 F7 00 03 C7 07 00
93 07 E0 07 63 EE E7 00 83 27 C4 FD 03 27 04 FD
B3 07 F7 00 83 C7 07 00 23 0E F4 FA 6F 00 C0 00
93 07 E0 02 23 0E F4 FA A3 0E 04 FA 93 07 C4 FB
13 85 07 00 EF F0 CF FB 83 27 C4 FD 93 87 17 00
13 85 07 00 EF F0 9F 86 83 27 C4 FD 93 87 17 00
23 2E F4 FC 03 27 C4 FD 93 07 F0 00 E3 D2 E7 F8
B7 17 00 00 13 85 C7 E3 EF F0 8F F9 83 27 44 FD
B7 17 00 00 13 85 C7 DF EF F0 5F 84 83 27 44 FD
93 87 07 01 23 2A F4 FC 83 27 44 FD 93 F7 F7 0F
63 80 07 02 83 27 84 FD 93 87 17 00 23 2C F4 FC
03 27 84 FD 93 07 F0 00 E3 D0 E7 E4 6F 00 80 00
13 00 00 00 B7 17 00 00 13 85 07 E4 EF F0 4F F5
B7 17 00 00 03 27 44 FD 23 A8 E7 E6 13 00 00 00
13 00 00 00 B7 17 00 00 13 85 07 E0 EF F0 1F 80
B7 17 00 00 03 27 44 FD 23 AA E7 E2 13 00 00 00
83 20 C1 04 03 24 81 04 03 29 41 04 83 29 01 04
03 2A C1 03 83 2A 81 03 13 01 01 05 67 80 00 00
@00000A18
@00000978
13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00
03 24 C1 00 13 01 01 01 67 80 00 00
@00000A34
13 01 01 F7 23 26 11 08 23 24 81 08 23 22 21 09
23 20 31 09 23 2E 41 07 23 2C 51 07 13 04 01 09
23 2E A4 F6 23 2C B4 F6 93 07 10 00 23 2E F4 FC
B7 17 00 F0 23 2A F4 FC 83 27 44 FD 93 87 C7 00
13 07 20 1B 23 A0 E7 00 EF F0 0F D9 93 07 05 00
63 88 07 00 B7 17 00 00 13 85 47 E4 EF F0 8F EA
83 27 C4 FD 93 87 17 00 23 2E F4 FC B7 07 00 F0
93 87 47 00 03 27 C4 FD 23 A0 E7 00 EF F0 0F DA
93 07 05 00 63 86 07 04 93 07 44 F8 93 05 70 02
13 85 07 00 EF F0 8F ED 13 00 00 00 B7 17 00 00
13 85 87 E4 EF F0 0F E6 93 07 44 F8 13 85 07 00
EF F0 4F E5 B7 17 00 00 13 85 07 E4 EF F0 8F E4
03 47 44 F8 93 07 20 06 63 1C F7 06 6F 00 40 02
83 27 C4 FD 93 87 17 00 23 2E F4 FC B7 07 00 F0
93 87 47 00 03 27 C4 FD 23 A0 E7 00 6F F0 1F F9
93 07 44 F8 93 87 27 00 93 05 00 00 13 85 07 00
EF F0 1F A7 23 2C A4 FA 83 27 84 FB 63 56 F0 02
B7 17 00 F0 23 2A F4 FA B7 F7 FA 02 13 87 07 08
83 27 84 FB 33 47 F7 02 83 27 44 FB 93 87 C7 00
23 A0 E7 00 6F 00 C0 2A EF F0 DF EA 6F 00 40 2A
03 47 44 F8 93 07 40 06 63 1C F7 02 93 07 44 F8
93 87 27 00 93 05 00 00 13 85 07 00 EF F0 1F B1
23 2E A4 FA 83 27 C4 FB 63 58 F0 00 03 27 C4 FB
B7 17 00 00 23 A8 E7 E6 EF F0 DF C2 6F 00 40 26
03 47 44 F8 93 07 70 07 63 1C F7 0A 93 07 44 F8
93 87 27 00 13 07 04 FB 93 05 07 00 13 85 07 00
EF F0 DF AC 23 24 A4 FC 83 27 04 FB 13 07 04 FB
93 05 07 00 13 85 07 00 EF F0 5F AB 23 22 A4 FC
83 27 04 FB 13 07 04 FB 93 05 07 00 13 85 07 00
EF F0 DF A9 23 20 A4 FC 03 27 04 FC 93 07 10 00
63 1C F7 00 83 27 84 FC 03 27 44 FC 13 77 F7 0F
23 80 E7 00 6F 00 C0 1E 03 27 04 FC 93 07 20 00
63 1E F7 00 83 27 84 FC 03 27 44 FC 13 17 07 01
13 57 07 41 23 90 E7 00 6F 00 80 1C 03 27 04 FC
93 07 40 00 63 1A F7 00 83 27 84 FC 03 27 44 FC
23 A0 E7 00 6F 00 C0 1A EF F0 DF DA 6F 00 40 1A
03 47 44 F8 93 07 20 07 63 1A F7 18 23 2C 04 FC
93 07 44 F8 93 87 27 00 13 07 C4 FA 93 05 07 00
13 85 07 00 EF F0 9F A0 93 07 05 00 23 28 F4 FC
83 27 C4 FA 13 07 C4 FA 93 05 07 00 13 85 07 00
EF F0 DF 9E 23 26 A4 FC 03 27 C4 FC 93 07 10 00
63 10 F7 02 83 27 04 FD 83 C7 07 00 23 2C F4 FC
B7 17 00 00 13 85 C7 E4 EF F0 CF C5 6F 00 80 05
03 27 C4 FC 93 07 20 00 63 10 F7 02 83 27 04 FD
83 D7 07 00 23 2C F4 FC B7 17 00 00 13 85 47 E5
EF F0 4F C3 6F 00 00 03 03 27 C4 FC 93 07 40 00
63 10 F7 02 83 27 04 FD 83 A7 07 00 23 2C F4 FC
B7 17 00 00 13 85 C7 E5 EF F0 CF C0 6F 00 80 00
EF F0 5F CE 03 27 C4 FC 93 07 10 00 63 0E F7 00
03 27 C4 FC 93 07 20 00 63 08 F7 00 03 27 C4 FC
93 07 40 00 63 1E F7 0A 83 27 04 FD 13 89 07 00
93 09 00 00 93 07 44 F8 13 07 00 03 93 06 80 00
93 05 09 00 13 86 09 00 13 85 07 00 EF F0 CF E7
93 07 44 F8 13 85 07 00 EF F0 CF BA B7 17 00 00
13 85 47 E6 EF F0 0F BA 03 27 84 FD 93 07 44 F8
93 05 07 00 13 85 07 00 EF F0 CF CC 93 07 44 F8
13 85 07 00 EF F0 0F B8 B7 17 00 00 13 85 87 E6
EF F0 4F B7 83 27 84 FD 13 8A 07 00 93 0A 00 00
83 27 C4 FC 93 96 17 00 93 07 44 F8 13 07 00 03
93 05 0A 00 13 86 0A 00 13 85 07 00 EF F0 CF E0
93 07 44 F8 13 85 07 00 EF F0 CF B3 B7 17 00 00
13 85 C7 E6 EF F0 0F B3 6F 00 80 00 EF F0 9F C0
13 00 00 00 EF F0 4F 9F 93 07 05 00 E3 8C 07 FE
6F F0 9F C5
@00000E28
@00000994
13 01 01 F6 23 2E 11 08 23 2C 81 08 23 2A 21 09
23 28 31 09 23 26 41 09 23 24 51 09 13 04 01 0A
23 26 A4 F6 23 24 B4 F6 93 07 10 00 23 2E F4 FC
B7 17 00 F0 23 26 F4 FC 83 27 C4 FC 93 87 C7 00
13 07 20 1B 23 A0 E7 00 B7 17 00 00 23 AA 07 E2
37 F5 FA 02 13 05 05 08 93 05 00 00 EF F0 CF E1
EF F0 4F E2 93 07 05 00 63 88 07 00 B7 17 00 00
13 85 47 E0 EF F0 CF F3 83 27 C4 FD 93 87 17 00
23 2E F4 FC B7 07 00 F0 93 87 47 00 03 27 C4 FD
23 A0 E7 00 EF F0 4F E3 93 07 05 00 63 86 07 04
93 07 84 F7 93 05 70 02 13 85 07 00 EF F0 8F F7
13 00 00 00 B7 17 00 00 13 85 C7 E0 EF F0 4F EF
93 07 84 F7 13 85 07 00 EF F0 8F EE B7 17 00 00
13 85 07 E0 EF F0 CF ED 03 47 84 F7 93 07 40 06
63 18 F7 06 6F 00 40 03 83 27 C4 FD 93 87 17 00
23 2E F4 FC B7 07 00 F0 93 87 47 00 03 27 C4 FD
23 A0 E7 00 37 F5 FA 02 13 05 05 08 93 05 00 00
EF F0 8F D6 6F F0 1F F8 93 07 84 F7 93 87 27 00
93 05 00 00 13 85 07 00 EF F0 1F B2 23 26 A4 FA
03 27 C4 FA 93 07 F0 FF 63 08 F7 00 B7 17 00 00
03 27 C4 FA 23 AA E7 E2 EF F0 DF C5 6F 00 40 2F
03 47 84 F7 93 07 60 06 63 14 F7 08 93 07 84 F7
93 87 27 00 13 07 84 FA 93 05 07 00 13 85 07 00
EF F0 9F AD 23 2A A4 FA 83 27 84 FA 13 07 84 FA
93 05 07 00 13 85 07 00 EF F0 1F AC 23 28 A4 FA
83 27 84 FA 13 07 84 FA 93 05 07 00 13 85 07 00
EF F0 9F AA 23 2C A4 FC 83 27 44 FB 23 2A F4 FC
6F 00 C0 01 83 27 44 FD 13 87 17 00 23 2A E4 FC
03 27 04 FB 13 77 F7 0F 23 80 E7 00 83 27 84 FD
13 87 F7 FF 23 2C E4 FC E3 9E 07 FC 6F 00 40 26
03 47 84 F7 93 07 70 07 63 1C F7 0A 93 07 84 F7
93 87 27 00 13 07 44 FA 93 05 07 00 13 85 07 00
EF F0 9F A4 23 20 A4 FC 83 27 44 FA 13 07 44 FA
93 05 07 00 13 85 07 00 EF F0 1F A3 23 2E A4 FA
83 27 44 FA 13 07 44 FA 93 05 07 00 13 85 07 00
EF F0 9F A1 23 2C A4 FA 03 27 84 FB 93 07 10 00
63 1C F7 00 83 27 04 FC 03 27 C4 FB 13 77 F7 0F
23 80 E7 00 6F 00 C0 1E 03 27 84 FB 93 07 20 00
63 1E F7 00 83 27 04 FC 03 27 C4 FB 13 17 07 01
13 57 07 41 23 90 E7 00 6F 00 80 1C 03 27 84 FB
93 07 40 00 63 1A F7 00 83 27 04 FC 03 27 C4 FB
23 A0 E7 00 6F 00 C0 1A EF F0 DF D4 6F 00 40 1A
03 47 84 F7 93 07 20 07 63 1A F7 18 23 28 04 FC
93 07 84 F7 93 87 27 00 13 07 04 FA 93 05 07 00
13 85 07 00 EF F0 5F 98 23 24 A4 FC 83 27 04 FA
13 07 04 FA 93 05 07 00 13 85 07 00 EF F0 DF 96
93 07 05 00 23 22 F4 FC 03 27 44 FC 93 07 10 00
63 10 F7 02 83 27 84 FC 83 C7 07 00 23 28 F4 FC
B7 17 00 00 13 85 07 E1 EF F0 8F CA 6F 00 80 05
03 27 44 FC 93 07 20 00 63 10 F7 02 83 27 84 FC
83 D7 07 00 23 28 F4 FC B7 17 00 00 13 85 87 E1
EF F0 0F C8 6F 00 00 03 03 27 44 FC 93 07 40 00
63 10 F7 02 83 27 84 FC 83 A7 07 00 23 28 F4 FC
B7 17 00 00 13 85 07 E2 EF F0 8F C5 6F 00 80 00
EF F0 5F C8 03 27 44 FC 93 07 10 00 63 0E F7 00
03 27 44 FC 93 07 20 00 63 08 F7 00 03 27 44 FC
93 07 40 00 63 1E F7 0A 83 27 84 FC 13 89 07 00
93 09 00 00 93 07 84 F7 13 07 00 03 93 06 80 00
93 05 09 00 13 86 09 00 13 85 07 00 EF F0 4F EF
93 07 84 F7 13 85 07 00 EF F0 8F BF B7 17 00 00
13 85 87 E2 EF F0 CF BE 03 27 04 FD 93 07 84 F7
93 05 07 00 13 85 07 00 EF F0 4F D4 93 07 84 F7
13 85 07 00 EF F0 CF BC B7 17 00 00 13 85 C7 E2
EF F0 0F BC 83 27 04 FD 13 8A 07 00 93 0A 00 00
83 27 44 FC 93 96 17 00 93 07 84 F7 13 07 00 03
93 05 0A 00 13 86 0A 00 13 85 07 00 EF F0 4F E8
93 07 84 F7 13 85 07 00 EF F0 8F B8 B7 17 00 00
13 85 07 E3 EF F0 CF B7 6F 00 80 00 EF F0 9F BA
13 00 00 00 EF F0 0F A4 93 07 05 00 E3 8C 07 FE
6F F0 1F C0
@00000DE8
20 20 00 00 20 20 20 00 20 00 00 00 2D 20 00 00
20 20 7C 00 7C 0A 00 00 0A 0D 00 00 3E 3E 00 00
0A 0D 3A 00 63 68 61 72 20 40 00 00 73 68 6F 72
74 20 40 00 69 6E 74 20 40 00 00 00 20 3D 20 00
28 00 00 00 29 0A 0D 00
@00000E70
01 00 00 00
20 20 7C 00 7C 0A 0D 00 0A 0D 00 00 72 69 73 63
76 3E 3E 00 0A 0D 3A 00 63 68 61 72 20 40 00 00
73 68 6F 72 74 20 40 00 69 6E 74 20 40 00 00 00
20 3D 20 00 28 00 00 00 29 0A 0D 00
examples/hdl4se_riscv/test_code/test.coe
浏览文件 @ 5a9a84a9
memory_initialization_radix = 16;
memory_initialization_vector =
1137,
231000EF,
191000EF,
FF9FF06F,
BA0595F3,
B2051573,
8067,
FE010113,
812E23,
2010413,
......@@ -83,21 +86,24 @@ FE010113,
812C23,
2010413,
FEA42623,
300006F,
13,
3C0006F,
2FAF537,
8050513,
593,
EA5FF0EF,
FEC42783,
7C783,
78513,
F39FF0EF,
F2DFF0EF,
50713,
FFF00793,
FEF704E3,
FCF70CE3,
FEC42783,
178793,
FEF42623,
FEC42783,
7C783,
FC0796E3,
FC0798E3,
793,
78513,
1C12083,
......@@ -115,12 +121,12 @@ FD842703,
100793,
E7C663,
793,
980006F,
F21FF0EF,
B80006F,
F15FF0EF,
FEA42423,
FE842703,
FFF00793,
FEF708E3,
6F70C63,
FEC42783,
178713,
FEE42623,
......@@ -130,23 +136,31 @@ E787B3,
FE842703,
FF77713,
E78023,
13,
140006F,
2FAF537,
8050513,
593,
DDDFF0EF,
FE842503,
E89FF0EF,
E6DFF0EF,
50713,
FFF00793,
FEF708E3,
FEF700E3,
FD842783,
FFF78793,
FEC42703,
2F75063,
2F75863,
FE842703,
A00793,
F70C63,
2F70463,
FE842703,
D00793,
F70663,
F89FF06F,
F70E63,
2FAF537,
8050513,
593,
D91FF0EF,
F69FF06F,
13,
FEC42783,
FDC42703,
......@@ -367,129 +381,75 @@ FD010113,
FCA42E23,
FCB42C23,
FE042623,
FE042423,
100793,
FEF42223,
8C0006F,
FDC42783,
7C783,
FEF42023,
FE042703,
2F00793,
4E7D263,
FE042703,
3900793,
2E7CC63,
FE842703,
70793,
279793,
E787B3,
179793,
78713,
FE042783,
F707B3,
FD078793,
FEF42423,
100793,
FEF42623,
280006F,
FEC42783,
2079E63,
FE042703,
2D00793,
F71A63,
FFF00793,
FEF42223,
100793,
FEF42623,
FDC42783,
178793,
FCF42E23,
FDC42783,
7C783,
F60798E3,
80006F,
13,
FE842703,
FE442783,
2F707B3,
FEF42423,
FD842783,
78863,
FD842783,
FDC42703,
E7A023,
FE842783,
78513,
2C12403,
3010113,
8067,
FD010113,
2812623,
3010413,
FCA42E23,
FCB42C23,
FE042623,
FE042423,
E00006F,
1000006F,
FDC42783,
7C783,
FEF42223,
FE442703,
2F00793,
2E7DA63,
4E7F063,
FE442703,
3900793,
2E7C463,
2E7EA63,
FEC42783,
79463,
FE042423,
100793,
FEF42623,
FE842783,
479713,
FE442783,
F707B3,
FD078793,
F767B3,
FEF42423,
8C0006F,
A00006F,
FE442703,
6000793,
2E7DA63,
4E7F063,
FE442703,
6600793,
2E7C463,
2E7EA63,
FEC42783,
79463,
FE042423,
100793,
FEF42623,
FE842783,
479713,
FE442783,
F707B3,
FA978793,
F767B3,
FEF42423,
500006F,
580006F,
FE442703,
4000793,
2E7DA63,
4E7F063,
FE442703,
4600793,
2E7C463,
2E7EA63,
FEC42783,
79463,
FE042423,
100793,
FEF42623,
FE842783,
479713,
FE442783,
F707B3,
FC978793,
F767B3,
FEF42423,
140006F,
FEC42783,
2079463,
100006F,
FEC42703,
100793,
FEF42623,
2F70063,
FDC42783,
178793,
FCF42E23,
FDC42783,
7C783,
F0079EE3,
EE079EE3,
80006F,
13,
FD842783,
......@@ -511,7 +471,7 @@ FB010113,
3512C23,
5010413,
17B7,
E707A783,
E347A783,
FF07F793,
FCF42A23,
FC042C23,
......@@ -525,13 +485,13 @@ FBC40793,
90593,
98613,
78513,
BC9FF0EF,
CA1FF0EF,
FBC40793,
78513,
8F9FF0EF,
9A5FF0EF,
17B7,
E2878513,
8EDFF0EF,
DE878513,
999FF0EF,
FC042E23,
A40006F,
FD442783,
......@@ -540,11 +500,11 @@ FDC42703,
FD442783,
F70733,
17B7,
E707A783,
E347A783,
F77A63,
17B7,
E2C78513,
8B9FF0EF,
DEC78513,
965FF0EF,
500006F,
FDC42783,
FCC42703,
......@@ -558,19 +518,19 @@ FBC40793,
A0593,
A8613,
78513,
B45FF0EF,
C1DFF0EF,
FBC40793,
78513,
875FF0EF,
921FF0EF,
17B7,
E3078513,
869FF0EF,
DF078513,
915FF0EF,
FDC42703,
700793,
F71863,
17B7,
E3478513,
851FF0EF,
DF478513,
8FDFF0EF,
FDC42783,
178793,
FCF42E23,
......@@ -578,8 +538,8 @@ FDC42703,
F00793,
F4E7DCE3,
17B7,
E3878513,
82DFF0EF,
DF878513,
8D9FF0EF,
FC042E23,
780006F,
FD442783,
......@@ -607,7 +567,7 @@ FAF40E23,
FA040EA3,
FBC40793,
78513,
FBCFF0EF,
869FF0EF,
FDC42783,
178793,
FCF42E23,
......@@ -615,8 +575,8 @@ FDC42703,
F00793,
F8E7D2E3,
17B7,
E3C78513,
F98FF0EF,
DFC78513,
845FF0EF,
FD442783,
1078793,
FCF42A23,
......@@ -632,11 +592,11 @@ E4E7D0E3,
80006F,
13,
17B7,
E4078513,
F54FF0EF,
E0078513,
801FF0EF,
17B7,
FD442703,
E6E7A823,
E2E7AA23,
13,
4C12083,
4812403,
......@@ -653,30 +613,36 @@ FF010113,
C12403,
1010113,
8067,
F7010113,
8112623,
8812423,
9212223,
9312023,
7412E23,
7512C23,
9010413,
F6A42E23,
F6B42C23,
F6010113,
8112E23,
8812C23,
9212A23,
9312823,
9412623,
9512423,
A010413,
F6A42623,
F6B42423,
100793,
FCF42E23,
F00017B7,
FCF42A23,
FD442783,
FCF42623,
FCC42783,
C78793,
1B200713,
E7A023,
D90FF0EF,
17B7,
E207AA23,
2FAF537,
8050513,
593,
E1CFF0EF,
E24FF0EF,
50793,
78863,
17B7,
E4478513,
EA8FF0EF,
E0478513,
F3CFF0EF,
FDC42783,
178793,
FCF42E23,
......@@ -684,27 +650,27 @@ F00007B7,
478793,
FDC42703,
E7A023,
DA0FF0EF,
E34FF0EF,
50793,
4078663,
F8440793,
F7840793,
2700593,
78513,
ED8FF0EF,
F78FF0EF,
13,
17B7,
E4878513,
E60FF0EF,
F8440793,
E0C78513,
EF4FF0EF,
F7840793,
78513,
E54FF0EF,
EE8FF0EF,
17B7,
E4078513,
E48FF0EF,
F8444703,
6200793,
6F71C63,
240006F,
E0078513,
EDCFF0EF,
F7844703,
6400793,
6F71863,
340006F,
FDC42783,
178793,
FCF42E23,
......@@ -712,208 +678,227 @@ F00007B7,
478793,
FDC42703,
E7A023,
F91FF06F,
F8440793,
278793,
2FAF537,
8050513,
593,
78513,
A71FF0EF,
FAA42C23,
FB842783,
2F05663,
F00017B7,
FAF42A23,
2FAF7B7,
8078713,
FB842783,
2F74733,
FB442783,
C78793,
E7A023,
2AC0006F,
EADFF0EF,
2A40006F,
F8444703,
6400793,
2F71C63,
F8440793,
D68FF0EF,
F81FF06F,
F7840793,
278793,
593,
78513,
B11FF0EF,
FAA42E23,
FBC42783,
F05863,
FBC42703,
B21FF0EF,
FAA42623,
FAC42703,
FFF00793,
F70863,
17B7,
E6E7A823,
C2DFF0EF,
FAC42703,
E2E7AA23,
C5DFF0EF,
2F40006F,
F7844703,
6600793,
8F71463,
F7840793,
278793,
FA840713,
70593,
78513,
AD9FF0EF,
FAA42A23,
FA842783,
FA840713,
70593,
78513,
AC1FF0EF,
FAA42823,
FA842783,
FA840713,
70593,
78513,
AA9FF0EF,
FCA42C23,
FB442783,
FCF42A23,
1C0006F,
FD442783,
178713,
FCE42A23,
FB042703,
FF77713,
E78023,
FD842783,
FFF78713,
FCE42C23,
FC079EE3,
2640006F,
F8444703,
F7844703,
7700793,
AF71C63,
F8440793,
F7840793,
278793,
FB040713,
FA440713,
70593,
78513,
ACDFF0EF,
FCA42423,
FB042783,
FB040713,
A49FF0EF,
FCA42023,
FA442783,
FA440713,
70593,
78513,
AB5FF0EF,
FCA42223,
FB042783,
FB040713,
A31FF0EF,
FAA42E23,
FA442783,
FA440713,
70593,
78513,
A9DFF0EF,
FCA42023,
FC042703,
A19FF0EF,
FAA42C23,
FB842703,
100793,
F71C63,
FC842783,
FC442703,
FC042783,
FBC42703,
FF77713,
E78023,
1EC0006F,
FC042703,
FB842703,
200793,
F71E63,
FC842783,
FC442703,
FC042783,
FBC42703,
1071713,
41075713,
E79023,
1C80006F,
FC042703,
FB842703,
400793,
F71A63,
FC842783,
FC442703,
FC042783,
FBC42703,
E7A023,
1AC0006F,
DADFF0EF,
D4DFF0EF,
1A40006F,
F8444703,
F7844703,
7200793,
18F71A63,
FC042C23,
F8440793,
FC042823,
F7840793,
278793,
FAC40713,
FA040713,
70593,
78513,
A09FF0EF,
50793,
FCF42823,
FAC42783,
FAC40713,
985FF0EF,
FCA42423,
FA042783,
FA040713,
70593,
78513,
9EDFF0EF,
FCA42623,
FCC42703,
96DFF0EF,
50793,
FCF42223,
FC442703,
100793,
2F71063,
FD042783,
FC842783,
7C783,
FCF42C23,
FCF42823,
17B7,
E4C78513,
C5CFF0EF,
E1078513,
CA8FF0EF,
580006F,
FCC42703,
FC442703,
200793,
2F71063,
FD042783,
FC842783,
7D783,
FCF42C23,
FCF42823,
17B7,
E5478513,
C34FF0EF,
E1878513,
C80FF0EF,
300006F,
FCC42703,
FC442703,
400793,
2F71063,
FD042783,
FC842783,
7A783,
FCF42C23,
FCF42823,
17B7,
E5C78513,
C0CFF0EF,
E2078513,
C58FF0EF,
80006F,
CE5FF0EF,
FCC42703,
C85FF0EF,
FC442703,
100793,
F70E63,
FCC42703,
FC442703,
200793,
F70863,
FCC42703,
FC442703,
400793,
AF71E63,
FD042783,
FC842783,
78913,
993,
F8440793,
F7840793,
3000713,
800693,
90593,
98613,
78513,
E7CFF0EF,
F8440793,
EF4FF0EF,
F7840793,
78513,
BACFF0EF,
BF8FF0EF,
17B7,
E6478513,
BA0FF0EF,
FD842703,
F8440793,
E2878513,
BECFF0EF,
FD042703,
F7840793,
70593,
78513,
CCCFF0EF,
F8440793,
D44FF0EF,
F7840793,
78513,
B80FF0EF,
BCCFF0EF,
17B7,
E6878513,
B74FF0EF,
FD842783,
E2C78513,
BC0FF0EF,
FD042783,
78A13,
A93,
FCC42783,
FC442783,
179693,
F8440793,
F7840793,
3000713,
A0593,
A8613,
78513,
E0CFF0EF,
F8440793,
E84FF0EF,
F7840793,
78513,
B3CFF0EF,
B88FF0EF,
17B7,
E6C78513,
B30FF0EF,
E3078513,
B7CFF0EF,
80006F,
C09FF0EF,
BA9FF0EF,
13,
9F4FF0EF,
A40FF0EF,
50793,
FE078CE3,
C59FF06F,
C01FF06F,
2020,
202020,
20,
202D,
7C2020,
A7C,
D0A7C,
D0A,
3E3E,
63736972,
3E3E76,
3A0D0A,
72616863,
4020,
......@@ -924,8 +909,23 @@ D0A,
203D20,
28,
D0A29,
1,
1,
203D20,
28,
D0A29,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
......
examples/hdl4se_riscv/test_code/test.info
浏览文件 @ 5a9a84a9
......@@ -10,39 +10,38 @@ ELF Header:
Version: 0x1
Entry point address: 0x0
Start of program headers: 52 (bytes into file)
Start of section headers: 8816 (bytes into file)
Start of section headers: 8724 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 1
Size of section headers: 40 (bytes)
Number of section headers: 22
Section header string table index: 21
Number of section headers: 21
Section header string table index: 20
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 00000000 001000 00000c 00 AX 0 0 4
[ 2] .text._canputchar PROGBITS 0000000c 00100c 000044 00 AX 0 0 4
[ 3] .text._haschar PROGBITS 00000050 001050 000048 00 AX 0 0 4
[ 4] .text._putchar PROGBITS 00000098 001098 000058 00 AX 0 0 4
[ 5] .text._getchar PROGBITS 000000f0 0010f0 000048 00 AX 0 0 4
[ 6] .text._puts PROGBITS 00000138 001138 000068 00 AX 0 0 4
[ 7] .text._gets PROGBITS 000001a0 0011a0 0000d8 00 AX 0 0 4
[ 8] .text._i2s PROGBITS 00000278 001278 000184 00 AX 0 0 4
[ 9] .text._h2s PROGBITS 000003fc 0013fc 0001a8 00 AX 0 0 4
[10] .text._s2d PROGBITS 000005a4 0015a4 0000fc 00 AX 0 0 4
[11] .text._s2h PROGBITS 000006a0 0016a0 000138 00 AX 0 0 4
[12] .text.dispmem PROGBITS 000007d8 0017d8 000240 00 AX 0 0 4
[13] .text.printhelp PROGBITS 00000a18 001a18 00001c 00 AX 0 0 4
[14] .text.main PROGBITS 00000a34 001a34 0003f4 00 AX 0 0 4
[15] .rodata PROGBITS 00000e28 001e28 000048 00 A 0 0 4
[16] .sdata.displ[...] PROGBITS 00000e70 001e70 000004 00 WA 0 0 4
[17] .comment PROGBITS 00000000 001e74 000012 01 MS 0 0 1
[18] .riscv.attributes RISCV_ATTRIBUTE 00000000 001e86 000021 00 0 0 1
[19] .symtab SYMTAB 00000000 001ea8 000240 10 20 33 4
[20] .strtab STRTAB 00000000 0020e8 000082 00 0 0 1
[21] .shstrtab STRTAB 00000000 00216a 000103 00 0 0 1
[ 1] .text PROGBITS 00000000 001000 000018 00 AX 0 0 4
[ 2] .text._canputchar PROGBITS 00000018 001018 000044 00 AX 0 0 4
[ 3] .text._haschar PROGBITS 0000005c 00105c 000048 00 AX 0 0 4
[ 4] .text._putchar PROGBITS 000000a4 0010a4 000058 00 AX 0 0 4
[ 5] .text._getchar PROGBITS 000000fc 0010fc 000048 00 AX 0 0 4
[ 6] .text._puts PROGBITS 00000144 001144 000074 00 AX 0 0 4
[ 7] .text._gets PROGBITS 000001b8 0011b8 0000f8 00 AX 0 0 4
[ 8] .text._i2s PROGBITS 000002b0 0012b0 000184 00 AX 0 0 4
[ 9] .text._h2s PROGBITS 00000434 001434 0001a8 00 AX 0 0 4
[10] .text._s2h PROGBITS 000005dc 0015dc 00015c 00 AX 0 0 4
[11] .text.dispmem PROGBITS 00000738 001738 000240 00 AX 0 0 4
[12] .text.printhelp PROGBITS 00000978 001978 00001c 00 AX 0 0 4
[13] .text.main PROGBITS 00000994 001994 000454 00 AX 0 0 4
[14] .rodata PROGBITS 00000de8 001de8 00004c 00 A 0 0 4
[15] .sbss NOBITS 00000e34 001e34 000004 00 WA 0 0 4
[16] .comment PROGBITS 00000000 001e34 000012 01 MS 0 0 1
[17] .riscv.attributes RISCV_ATTRIBUTE 00000000 001e46 000025 00 0 0 1
[18] .symtab SYMTAB 00000000 001e6c 000230 10 19 31 4
[19] .strtab STRTAB 00000000 00209c 00008a 00 0 0 1
[20] .shstrtab STRTAB 00000000 002126 0000eb 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
......@@ -53,11 +52,11 @@ There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x00000000 0x00000000 0x00e74 0x00e74 RWE 0x1000
LOAD 0x001000 0x00000000 0x00000000 0x00e34 0x00e38 RWE 0x1000
Section to Segment mapping:
Segment Sections...
00 .text .text._canputchar .text._haschar .text._putchar .text._getchar .text._puts .text._gets .text._i2s .text._h2s .text._s2d .text._s2h .text.dispmem .text.printhelp .text.main .rodata .sdata.displayaddr
00 .text .text._canputchar .text._haschar .text._putchar .text._getchar .text._puts .text._gets .text._i2s .text._h2s .text._s2h .text.dispmem .text.printhelp .text.main .rodata .sbss
There is no dynamic section in this file.
......@@ -65,47 +64,48 @@ There are no relocations in this file.
The decoding of unwind sections for machine type RISC-V is not currently supported.
Symbol table '.symtab' contains 36 entries:
Symbol table '.symtab' contains 35 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 SECTION LOCAL DEFAULT 1 .text
2: 0000000c 0 SECTION LOCAL DEFAULT 2 .text._canputchar
3: 00000050 0 SECTION LOCAL DEFAULT 3 .text._haschar
4: 00000098 0 SECTION LOCAL DEFAULT 4 .text._putchar
5: 000000f0 0 SECTION LOCAL DEFAULT 5 .text._getchar
6: 00000138 0 SECTION LOCAL DEFAULT 6 .text._puts
7: 000001a0 0 SECTION LOCAL DEFAULT 7 .text._gets
8: 00000278 0 SECTION LOCAL DEFAULT 8 .text._i2s
9: 000003fc 0 SECTION LOCAL DEFAULT 9 .text._h2s
10: 000005a4 0 SECTION LOCAL DEFAULT 10 .text._s2d
11: 000006a0 0 SECTION LOCAL DEFAULT 11 .text._s2h
12: 000007d8 0 SECTION LOCAL DEFAULT 12 .text.dispmem
13: 00000a18 0 SECTION LOCAL DEFAULT 13 .text.printhelp
14: 00000a34 0 SECTION LOCAL DEFAULT 14 .text.main
15: 00000e28 0 SECTION LOCAL DEFAULT 15 .rodata
16: 00000e70 0 SECTION LOCAL DEFAULT 16 .sdata.displayaddr
17: 00000000 0 SECTION LOCAL DEFAULT 17 .comment
18: 00000000 0 SECTION LOCAL DEFAULT 18 .riscv.attributes
19: 00000000 0 FILE LOCAL DEFAULT ABS console.c
20: 0000000c 68 FUNC LOCAL DEFAULT 2 _canputchar
21: 00000050 72 FUNC LOCAL DEFAULT 3 _haschar
22: 00000098 88 FUNC LOCAL DEFAULT 4 _putchar
23: 000000f0 72 FUNC LOCAL DEFAULT 5 _getchar
24: 00000138 104 FUNC LOCAL DEFAULT 6 _puts
25: 000001a0 216 FUNC LOCAL DEFAULT 7 _gets
26: 00000278 388 FUNC LOCAL DEFAULT 8 _i2s
27: 000003fc 424 FUNC LOCAL DEFAULT 9 _h2s
28: 000005a4 252 FUNC LOCAL DEFAULT 10 _s2d
29: 000006a0 312 FUNC LOCAL DEFAULT 11 _s2h
30: 00000e70 4 OBJECT LOCAL DEFAULT 16 displayaddr
31: 000007d8 576 FUNC LOCAL DEFAULT 12 dispmem
32: 00000a18 28 FUNC LOCAL DEFAULT 13 printhelp
33: 00000000 12 FUNC GLOBAL DEFAULT 1 __start
34: 00000a34 1012 FUNC GLOBAL DEFAULT 14 main
35: 00000e74 0 NOTYPE GLOBAL DEFAULT 16 _end
2: 00000018 0 SECTION LOCAL DEFAULT 2 .text._canputchar
3: 0000005c 0 SECTION LOCAL DEFAULT 3 .text._haschar
4: 000000a4 0 SECTION LOCAL DEFAULT 4 .text._putchar
5: 000000fc 0 SECTION LOCAL DEFAULT 5 .text._getchar
6: 00000144 0 SECTION LOCAL DEFAULT 6 .text._puts
7: 000001b8 0 SECTION LOCAL DEFAULT 7 .text._gets
8: 000002b0 0 SECTION LOCAL DEFAULT 8 .text._i2s
9: 00000434 0 SECTION LOCAL DEFAULT 9 .text._h2s
10: 000005dc 0 SECTION LOCAL DEFAULT 10 .text._s2h
11: 00000738 0 SECTION LOCAL DEFAULT 11 .text.dispmem
12: 00000978 0 SECTION LOCAL DEFAULT 12 .text.printhelp
13: 00000994 0 SECTION LOCAL DEFAULT 13 .text.main
14: 00000de8 0 SECTION LOCAL DEFAULT 14 .rodata
15: 00000e34 0 SECTION LOCAL DEFAULT 15 .sbss
16: 00000000 0 SECTION LOCAL DEFAULT 16 .comment
17: 00000000 0 SECTION LOCAL DEFAULT 17 .riscv.attributes
18: 00000000 0 FILE LOCAL DEFAULT ABS console.c
19: 00000018 68 FUNC LOCAL DEFAULT 2 _canputchar
20: 0000005c 72 FUNC LOCAL DEFAULT 3 _haschar
21: 000000a4 88 FUNC LOCAL DEFAULT 4 _putchar
22: 000000fc 72 FUNC LOCAL DEFAULT 5 _getchar
23: 00000144 116 FUNC LOCAL DEFAULT 6 _puts
24: 000001b8 248 FUNC LOCAL DEFAULT 7 _gets
25: 000002b0 388 FUNC LOCAL DEFAULT 8 _i2s
26: 00000434 424 FUNC LOCAL DEFAULT 9 _h2s
27: 000005dc 348 FUNC LOCAL DEFAULT 10 _s2h
28: 00000e34 4 OBJECT LOCAL DEFAULT 15 displayaddr
29: 00000738 576 FUNC LOCAL DEFAULT 11 dispmem
30: 00000978 28 FUNC LOCAL DEFAULT 12 printhelp
31: 00000000 12 FUNC GLOBAL DEFAULT 1 __start
32: 0000000c 12 FUNC GLOBAL DEFAULT 1 watchdog_set
33: 00000994 1108 FUNC GLOBAL DEFAULT 13 main
34: 00000e38 0 NOTYPE GLOBAL DEFAULT 15 _end
No version information found in this file.
Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: "rv32i2p0_m2p0"
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 11
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v
浏览文件 @ 5a9a84a9
......@@ -43,6 +43,7 @@
`define RAMSIZE 1024
`define WATCHDOG
`define CSROPCOUNTER_
`define CSRBASECOUNTER_
`define USE3MUL_
......@@ -96,7 +97,10 @@ module riscv_core_v5(
reg [31:0] lastaddr;
/* CSR register */
reg [31:0] misa; /*0301*/
reg [31:0] misa; /* 0301 */
`ifdef WATCHDOG
reg [31:0] watchdog; /* 0b20 */
`endif
`ifdef CSRBASECOUNTER
reg [63:0] ucycle64; /*0c00/0c80*/
reg [63:0] utime64; /*0c01/0c81*/
......@@ -121,6 +125,9 @@ module riscv_core_v5(
if (state == `RISCVSTATE_READ_REGS && wReadReady)
case (bReadData[31:20])
12'h301: csr_r <= misa;
`ifdef WATCHDOG
12'hb20: csr_r <= watchdog[31:0];
`endif
`ifdef CSRBASECOUNTER
12'hc00: csr_r <= ucycle64[31:0];
12'hc80: csr_r <= ucycle64[63:32];
......@@ -340,8 +347,12 @@ module riscv_core_v5(
//DEFINE_FUNC(riscv_core_reg_gen_pc, "nwReset, state, instr, pc, rs1, imm, regrddata") {
always @(posedge wClk)
if (!nwReset) begin
pc <= 0;//32'h00000074;
if (~nwReset
`ifdef WATCHDOG
|| (watchdog == 0)
`endif
) begin
pc <= 0;
end else begin
if (state == `RISCVSTATE_EXEC_INST) begin
pc <= newpc;
......@@ -504,7 +515,11 @@ module riscv_core_v5(
//DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset") {
always @(posedge wClk)
if (!nwReset) begin
if (~nwReset
`ifdef WATCHDOG
|| (watchdog == 0)
`endif
) begin
state <= `RISCVSTATE_READ_INST;
end else begin
case (state)
......@@ -623,6 +638,9 @@ module riscv_core_v5(
always @(posedge wClk)
if (nwReset == 0) begin
misa <= 32'b0100_0000_0001_0000_0001_0001_0000_0000;// RV32IM
`ifdef WATCHDOG
watchdog <= 100000000;
`endif
`ifdef CSRBASECOUNTER
ucycle64 <= 0;
mcycle64 <= 0;
......@@ -644,6 +662,9 @@ module riscv_core_v5(
`endif
end
else begin
`ifdef WATCHDOG
watchdog <= watchdog - 1;
`endif
`ifdef CSROPCOUNTER
if (opcounter_doit)
`endif
......@@ -688,6 +709,9 @@ module riscv_core_v5(
if (csr_op) begin
case (instr[31:20])
12'h301: misa <= csr_v;
`ifdef WATCHDOG
12'hb20: watchdog[31:0] <= csr_v;
`endif
`ifdef CSRBASECOUNTER
12'hc00: ucycle64[31:0] <= csr_v;
12'hc80: ucycle64[63:32] <= csr_v;
......
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v
浏览文件 @ 5a9a84a9
......@@ -68,15 +68,12 @@ module riscv_core_with_axi_master (
lastread <= wRead;
end
assign bReadData =
((lastreadaddr & 32'hf000_0000) == 32'hf000_0000) ? m00_axi_rdata : (
((lastreadaddr & 32'hff00_0000) == 32'h0000_0000) ? bReadDataRam : (32'h0)
);
assign wReadReady = ((lastreadaddr & 32'hf000_0000) == 32'hf000_0000) ? m00_axi_rvalid : (
((lastreadaddr & 32'hfff0_0000) == 32'h0000_0000) ? lastread : (0)
);
wire isramaddr = (lastreadaddr & 32'hfff0_0000) == 32'h0000_0000; /* 1MB ram addr */
assign bReadData = isramaddr ? bReadDataRam : m00_axi_rdata;
assign wReadReady = isramaddr ? lastread : m00_axi_rvalid;
wire isramwriteaddr = (bWriteAddr & 32'hfff0_0000) == 32'h0000_0000; /* 1MB ram addr */
wire isramreadaddr = (bReadAddr & 32'hfff0_0000) == 32'h0000_0000; /* 1MB ram addr */
wire [29:0] ramaddr;
assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];
......@@ -92,12 +89,12 @@ module riscv_core_with_axi_master (
regfile regs(regno, regena, m00_axi_aclk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, m00_axi_aclk, regwrdata2, regwren2, regrddata2);
`define ALTERA
`define ALTERA_
`ifdef ALTERA
ram4kB ram(.clock(m00_axi_aclk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0), .q(bReadDataRam));
ram4kB ram(.clock(m00_axi_aclk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(isramwriteaddr ? wWrite : 1'b0), .q(bReadDataRam));
`else
ram4KB ram(.clka(m00_axi_aclk), .ena(1'b1), .addra(ramaddr), .wea(((bWriteAddr & 32'hff000000) == 0 && wWrite)?(~bWriteMask):4'b0), .dina(bWriteData) , .douta(bReadDataRam));
ram4KB ram(.clka(m00_axi_aclk), .ena(1'b1), .addra(ramaddr), .wea((isramwriteaddr && wWrite)?(~bWriteMask):4'b0), .dina(bWriteData) , .douta(bReadDataRam));
`endif
riscv_core_v5 core(
m00_axi_aclk,
......@@ -125,7 +122,7 @@ module riscv_core_with_axi_master (
//Write Address
wire writeaxi = (wWrite && ((bWriteAddr & 32'hfff00000) != 0));
wire writeaxi = (wWrite && ~isramwriteaddr);
reg [31:0] awaddr;
reg awvalid;
always @(posedge m00_axi_aclk)
......@@ -145,23 +142,41 @@ module riscv_core_with_axi_master (
end
/* Write Data */
reg [31:0] waddr;
reg [31:0] wdata;
reg [3:0] wstrb;
reg wvalid;
reg write_local;
always @(posedge m00_axi_aclk)
begin
if (~m00_axi_aresetn) begin
wvalid <= 1'b0;
end if (writeaxi) begin
end else if (writeaxi) begin
waddr <= bWriteAddr;
wdata <= bWriteData;
wstrb <= ~bWriteMask;
wvalid <= 1'b1;
end if (m00_axi_wready) begin
wvalid <= 1'b0;
end
if (~m00_axi_aresetn) begin
write_local <= 1'b0;
end else if (wWrite) begin
if (isramwriteaddr) begin
write_local <= 1;
end else begin
write_local <= 0;
end
end
end
assign wWriteReady = ((wWrite || wvalid) && m00_axi_wready) || writeaxi;
reg writeready;
assign wWriteReady = writeready;
always @(posedge m00_axi_aclk)
if (~m00_axi_aresetn)
writeready <= 1'b0;
else
writeready <= m00_axi_wready || write_local || isramwriteaddr;
always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb)
begin
......@@ -170,7 +185,7 @@ module riscv_core_with_axi_master (
axi_wstrb = writeaxi ? ~bWriteMask : wstrb;
end
wire readaxi = wRead && ((bReadAddr & 32'hfff00000) != 0);
wire readaxi = wRead && ~isramreadaddr;
//Read Address
reg [31:0] araddr;
reg arvalid;
......
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/mref/riscv_core_with_axi_master/component.xml
浏览文件 @ 5a9a84a9
......@@ -234,7 +234,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>5364fb93</spirit:value>
<spirit:value>8949d99b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -247,7 +247,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>5364fb93</spirit:value>
<spirit:value>8949d99b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -637,7 +637,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2021-09-14T09:53:38Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2021-09-15T07:21:51Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
......
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/hdl/riscv_top_wrapper.v
浏览文件 @ 5a9a84a9
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
//Date : Tue Sep 14 18:04:05 2021
//Date : Wed Sep 15 15:22:11 2021
//Host : RG6MXLMTA6KAGXI running 64-bit Service Pack 1 (build 7601)
//Command : generate_target riscv_top_wrapper.bd
//Design : riscv_top_wrapper
......
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/hw_handoff/riscv_top_bd.tcl
浏览文件 @ 5a9a84a9
......@@ -174,6 +174,14 @@ proc create_root_design { parentCell } {
CONFIG.FREQ_HZ {50000000} \
] $wClk
# Create instance: axi_bram_ctrl_0, and set properties
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
set_property -dict [ list \
CONFIG.ECC_TYPE {0} \
CONFIG.PROTOCOL {AXI4LITE} \
CONFIG.SINGLE_PORT_BRAM {1} \
] $axi_bram_ctrl_0
# Create instance: axi_uartlite_0, and set properties
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
set_property -dict [ list \
......@@ -182,6 +190,9 @@ proc create_root_design { parentCell } {
CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {50} \
] $axi_uartlite_0
# Create instance: blk_mem_gen_0, and set properties
set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
# Create instance: led_key_0, and set properties
set block_name led_key
set block_cell_name led_key_0
......@@ -207,15 +218,17 @@ proc create_root_design { parentCell } {
# Create instance: riscv_core_with_axi_0_axi_periph, and set properties
set riscv_core_with_axi_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 riscv_core_with_axi_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {2} \
CONFIG.NUM_MI {3} \
] $riscv_core_with_axi_0_axi_periph
# Create instance: rst_wClk_50M, and set properties
set rst_wClk_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_wClk_50M ]
# Create interface connections
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M01_AXI [get_bd_intf_pins led_key_0/s00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M02_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_m00_axi [get_bd_intf_pins riscv_core_with_axi_0/m00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/S00_AXI]
# Create port connections
......@@ -223,11 +236,12 @@ proc create_root_design { parentCell } {
connect_bd_net -net key_1 [get_bd_ports key] [get_bd_pins led_key_0/key]
connect_bd_net -net led_key_0_led [get_bd_ports led] [get_bd_pins led_key_0/led]
connect_bd_net -net nwReset_1 [get_bd_ports nwReset] [get_bd_pins rst_wClk_50M/ext_reset_in]
connect_bd_net -net rst_wClk_50M_peripheral_aresetn [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins led_key_0/s00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0/m00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0_axi_periph/ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ARESETN] [get_bd_pins rst_wClk_50M/peripheral_aresetn]
connect_bd_net -net rst_wClk_50M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins led_key_0/s00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0/m00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0_axi_periph/ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M02_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ARESETN] [get_bd_pins rst_wClk_50M/peripheral_aresetn]
connect_bd_net -net uart_rx_1 [get_bd_ports uart_rx] [get_bd_pins axi_uartlite_0/rx]
connect_bd_net -net wClk_1 [get_bd_ports wClk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins led_key_0/s00_axi_aclk] [get_bd_pins riscv_core_with_axi_0/m00_axi_aclk] [get_bd_pins riscv_core_with_axi_0_axi_periph/ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ACLK] [get_bd_pins rst_wClk_50M/slowest_sync_clk]
connect_bd_net -net wClk_1 [get_bd_ports wClk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins led_key_0/s00_axi_aclk] [get_bd_pins riscv_core_with_axi_0/m00_axi_aclk] [get_bd_pins riscv_core_with_axi_0_axi_periph/ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M02_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ACLK] [get_bd_pins rst_wClk_50M/slowest_sync_clk]
# Create address segments
create_bd_addr_seg -range 0x00008000 -offset 0xF0010000 [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
create_bd_addr_seg -range 0x00001000 -offset 0xF0001000 [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
create_bd_addr_seg -range 0x00001000 -offset 0xF0000000 [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs led_key_0/s00_axi/reg0] SEG_led_key_0_reg0
......
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/ip/riscv_top_riscv_core_with_axi_0_axi_periph_0/riscv_top_riscv_core_with_axi_0_axi_periph_0.xci
浏览文件 @ 5a9a84a9
......@@ -268,7 +268,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M63_HAS_REGSLICE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M63_ISSUANCE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M63_SECURE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_MI">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_MI">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_SI">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCHK_MAX_RD_BURSTS">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCHK_MAX_WR_BURSTS">2</spirit:configurableElementValue>
......
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