From 48e2955c385e85c0d2653ae921c7c19e1bd01fc4 Mon Sep 17 00:00:00 2001
From: m0_56903617 <raoxianhong@jingjiamicro.com>
Date: Sat, 26 Jun 2021 10:08:30 +0800
Subject: [PATCH] 202106261008

---
 bignumber/src/bignumber.c                 | 216 ++++-----
 examples/terris/src/copylines.c           |   4 +-
 examples/terris/src/flushtodisp.c         |   2 +-
 examples/terris/src/main.c                |   9 +-
 examples/terris/src/terris_ctrl.c         |  86 +---
 examples/terris/src/terris_main_module.c  | 457 ++++++++----------
 examples/terris/verilog/canblocksetto.v   |   8 +-
 examples/terris/verilog/checkline.v       |   2 +-
 examples/terris/verilog/copylines.v       |  17 +-
 examples/terris/verilog/flushtodisp.v     |   6 +-
 examples/terris/verilog/panelinit.v       |   4 +-
 examples/terris/verilog/terris_ctrl.v     |  49 +-
 examples/terris/verilog/terris_main.v     |  15 +-
 examples/terris/verilog/terris_main_asm.v | 541 +++++++++++-----------
 parser/verilog_expr.c                     |  13 +-
 15 files changed, 674 insertions(+), 755 deletions(-)

diff --git a/bignumber/src/bignumber.c b/bignumber/src/bignumber.c
index 02d7d8c..bb6fa4c 100644
--- a/bignumber/src/bignumber.c
+++ b/bignumber/src/bignumber.c
@@ -543,6 +543,7 @@ static int bigint_bn_AssignStr(HOBJECT object, const char* str, const char **nst
 					if (nstr != NULL)
 						*nstr = strt;
 				}
+				objwidth = width;
 				numvalid = 0;
 			}
 			else {
@@ -710,7 +711,7 @@ lastnum:
 		}
 		if (width == 0)
 			width = 1;
-		if (pobj->isunsigned == 0)
+	//	if (pobj->isunsigned == 0)
 			width++;
 	}
 	else {
@@ -793,15 +794,27 @@ static int bigint_bn_AddInt32(HOBJECT object, HOBJECT src, int value)
 { 
 	unsigned long long temp;
 	int ind;
-	unsigned int v, vs, widthsrc;
+	unsigned int v, vs, widthsrc, width;
+	int objunsigned, srcunsigned;
 	sBigInteger* pobj;
 	IBigNumber** numsrc;
 	pobj = (sBigInteger*)objectThis(object);
 	if (EIID_OK != objectQueryInterface(src, IID_BIGNUMBER, (void**)&numsrc))
 		return -1;
 	widthsrc = objectCall0(numsrc, GetWidth);
-	objectCall1(numsrc, SetWidth, widthsrc);
-	bigint_bn_SetWidth(object, pobj->width);
+	srcunsigned = objectCall0(numsrc, IsUnsigned);
+	objunsigned = pobj->isunsigned;
+
+	width = pobj->width;
+	if (width < widthsrc)
+		width = widthsrc;
+	
+	objectCall1(numsrc, SetUnsigned, 0);
+	objectCall1(numsrc, SetWidth, width);
+	
+	bigint_bn_SetUnsigned(object, 0);
+	bigint_bn_SetWidth(object, width);
+
 	objectCall2(numsrc, GetBits32, 0, &vs);
 	temp = vs;
 	temp += *(unsigned int*)&value;
@@ -820,6 +833,10 @@ static int bigint_bn_AddInt32(HOBJECT object, HOBJECT src, int value)
 		temp >>= CELL_WIDTH;
 		ind++;
 	}
+	objectCall1(numsrc, SetUnsigned, srcunsigned);
+	objectCall1(numsrc, SetWidth, widthsrc);
+	bigint_bn_SetUnsigned(object, objunsigned);
+	bigint_bn_SetWidth(object, pobj->width);
 	return 0;
 }
 
@@ -832,6 +849,7 @@ static int bigint_bn_MulInt32(HOBJECT object, HOBJECT src, int value)
 {
 	IBigNumber ** temp;
 	temp = bigintegerCreate(32);
+	bigint_bn_SetUnsigned(temp, 0);
 	bigint_bn_AssignInt32(temp, value);
 	bigint_bn_Mul(object, src, temp);
 	objectRelease(temp);
@@ -842,6 +860,7 @@ static int bigint_bn_DivInt32(HOBJECT object, HOBJECT src, int value)
 {
 	IBigNumber** temp;
 	temp = bigintegerCreate(32);
+	bigint_bn_SetUnsigned(temp, 0);
 	bigint_bn_AssignInt32(temp, value);
 	bigint_bn_Div(object, src, temp);
 	objectRelease(temp);
@@ -852,6 +871,7 @@ static int bigint_bn_ModInt32(HOBJECT object, HOBJECT src, int value)
 {
 	IBigNumber** temp;
 	temp = bigintegerCreate(32);
+	bigint_bn_SetUnsigned(temp, 0);
 	bigint_bn_AssignInt32(temp, value);
 	bigint_bn_Mod(object, src, temp);
 	objectRelease(temp);
@@ -862,6 +882,7 @@ static int bigint_bn_PowInt32(HOBJECT object, HOBJECT src, int value)
 {
 	IBigNumber** temp;
 	temp = bigintegerCreate(32);
+	bigint_bn_SetUnsigned(temp, 0);
 	bigint_bn_AssignInt32(temp, value);
 	bigint_bn_Pow(object, src, temp);
 	objectRelease(temp);
@@ -870,32 +891,7 @@ static int bigint_bn_PowInt32(HOBJECT object, HOBJECT src, int value)
 
 static int bigint_bn_AddUint32(HOBJECT object, HOBJECT src, unsigned int value)
 {
-	unsigned long long temp;
-	int ind;
-	unsigned int vs, widthsrc;
-	sBigInteger* pobj;
-	IBigNumber** numsrc;
-	pobj = (sBigInteger*)objectThis(object);
-	if (EIID_OK != objectQueryInterface(src, IID_BIGNUMBER, (void**)&numsrc))
-		return -1;
-	widthsrc = objectCall0(numsrc, GetWidth);
-	objectCall1(numsrc, SetWidth, widthsrc);
-	bigint_bn_SetWidth(object, pobj->width);
-	objectCall2(numsrc, GetBits32, 0, &vs);
-	temp = vs;
-	temp += *(unsigned int*)&value;
-	pobj->buf[0] = temp & CELL_MASK;
-	temp >>= CELL_WIDTH;
-	ind = 1;
-	while (ind < pobj->buflen) {
-		if (0 != objectCall2(numsrc, GetBits32, ind, &vs))
-			vs = 0;
-		temp += vs;
-		pobj->buf[ind] = temp & CELL_MASK;
-		temp >>= CELL_WIDTH;
-		ind++;
-	}
-	return 0;
+	return bigint_bn_AddInt32(object, src, value);
 }
 
 static int bigint_bn_SubUint32(HOBJECT object, HOBJECT src, unsigned int value)
@@ -910,6 +906,7 @@ static int bigint_bn_MulUint32(HOBJECT object, HOBJECT src, unsigned int value)
 {
 	IBigNumber** temp;
 	temp = bigintegerCreate(32);
+	bigint_bn_SetUnsigned(temp, 1);
 	bigint_bn_AssignUint32(temp, value);
 	bigint_bn_Mul(object, src, temp);
 	objectRelease(temp);
@@ -920,6 +917,7 @@ static int bigint_bn_DivUint32(HOBJECT object, HOBJECT src, unsigned int value)
 {
 	IBigNumber** temp;
 	temp = bigintegerCreate(32);
+	bigint_bn_SetUnsigned(temp, 1);
 	bigint_bn_AssignUint32(temp, value);
 	bigint_bn_Div(object, src, temp);
 	objectRelease(temp);
@@ -930,6 +928,7 @@ static int bigint_bn_ModUint32(HOBJECT object, HOBJECT src, unsigned int value)
 {
 	IBigNumber** temp;
 	temp = bigintegerCreate(32);
+	bigint_bn_SetUnsigned(temp, 1);
 	bigint_bn_AssignUint32(temp, value);
 	bigint_bn_Mod(object, src, temp);
 	objectRelease(temp);
@@ -940,20 +939,21 @@ static int bigint_bn_PowUint32(HOBJECT object, HOBJECT src, unsigned int value)
 {
 	IBigNumber** temp;
 	temp = bigintegerCreate(32);
+	bigint_bn_SetUnsigned(temp, 1);
 	bigint_bn_AssignUint32(temp, value);
 	bigint_bn_Pow(object, src, temp);
 	objectRelease(temp);
 	return 0;
 }
 
-
-static int bigint_bn_AddFunc(HOBJECT object, HOBJECT src0, HOBJECT src1)
-{ 
+static int bigint_bn_Add(HOBJECT object, HOBJECT src0, HOBJECT src1)
+{
 	unsigned long long temp;
 	sBigInteger* pobj;
 	IBigNumber** psrc0;
 	IBigNumber** psrc1;
-	int widthobj, widthsrc0, widthsrc1;
+	int widthobj, widthsrc0, widthsrc1, width;
+	int objunsigned, src0unsigned, src1unsigned;
 	int i;
 	pobj = (sBigInteger*)objectThis(object);
 	if (EIID_OK != objectQueryInterface(src0, IID_BIGNUMBER, (void**)&psrc0)) {
@@ -966,18 +966,23 @@ static int bigint_bn_AddFunc(HOBJECT object, HOBJECT src0, HOBJECT src1)
 	widthobj = pobj->width;
 	widthsrc0 = objectCall0(psrc0, GetWidth);
 	widthsrc1 = objectCall0(psrc1, GetWidth);
-	if (widthsrc0 < widthobj) {
-		objectCall1(psrc0, SetWidth, widthobj);
-	}
-	else {
-		objectCall1(psrc0, SetWidth, widthsrc0);
-	}
-	if (widthsrc1 < widthobj) {
-		objectCall1(psrc1, SetWidth, widthobj);
-	}
-	else {
-		objectCall1(psrc1, SetWidth, widthsrc1);
-	}
+
+	objunsigned = pobj->isunsigned;
+	src0unsigned = objectCall0(psrc0, IsUnsigned);
+	src1unsigned = objectCall0(psrc1, IsUnsigned);
+
+	bigint_bn_SetUnsigned(object, 0);
+	objectCall1(psrc0, SetUnsigned, 0);
+	objectCall1(psrc1, SetUnsigned, 0);
+
+	width = widthsrc0;
+	if (width < widthsrc1)
+		width = widthsrc1;
+	if (width < widthobj)
+		width = widthobj;
+	objectCall1(psrc0, SetWidth, width);
+	objectCall1(psrc1, SetWidth, width);
+	bigint_bn_SetWidth(object, width);
 	temp = 0;
 	for (i = 0; i < pobj->buflen; i++) {
 		unsigned int src0value, src1value;
@@ -988,64 +993,38 @@ static int bigint_bn_AddFunc(HOBJECT object, HOBJECT src0, HOBJECT src1)
 		pobj->buf[i] = temp & CELL_MASK;
 		temp >>= CELL_WIDTH;
 	}
+	bigint_bn_SetUnsigned(object, objunsigned);
+	objectCall1(psrc0, SetUnsigned, src0unsigned);
+	objectCall1(psrc1, SetUnsigned, src1unsigned);
 	bigint_bn_SetWidth(object, widthobj);
-	if (widthsrc0 < widthobj) {
-		objectCall1(psrc0, SetWidth, widthsrc0);
-	}
-	if (widthsrc1 < widthobj) {
-		objectCall1(psrc1, SetWidth, widthsrc1);
-	}
+	objectCall1(psrc0, SetWidth, widthsrc0);
+	objectCall1(psrc1, SetWidth, widthsrc1);
 	objectRelease(psrc0);
 	objectRelease(psrc1);
 	return 0;
 }
 
-static int bigint_bn_Add(HOBJECT object, HOBJECT src0, HOBJECT src1)
-{
-	return bigint_bn_AddFunc(object, src0, src1);
-}
-
 static int bigint_bn_Sub(HOBJECT object, HOBJECT src0, HOBJECT src1)
 { 
-	sBigInteger* pobj;
 	IBigNumber** temp = NULL;
-	IBigNumber** psrc0 = NULL;
-	IBigNumber** psrc1 = NULL;
 	int ret;
-	int width0, width1, width;
-	pobj = (sBigInteger*)objectThis(object);
-	if (0 != objectQueryInterface(src0, IID_BIGNUMBER, &psrc0)) {
-		ret = -1;
-		goto retresult;
-	}
-	if (0 != objectQueryInterface(src1, IID_BIGNUMBER, &psrc1)) {
-		ret = -1;
-		goto retresult;
-	}	
-	width0 = objectCall0(psrc0, GetWidth);
-	width1 = objectCall0(psrc1, GetWidth);
-	width = pobj->width;
 	temp = bigintegerCreate(32);
 	objectCall1(temp, Clone, src1);
-	if (width1 < width0)
-		objectCall1(temp, SetWidth, width0);
 	if (EIID_OK != bigint_bn_Neg(temp, temp))
 		return -1;
 	ret = bigint_bn_Add(object, src0, temp);
 retresult:
-	objectRelease(psrc0);
-	objectRelease(psrc1);
-	objectRelease(temp);
 	return ret;
 }
 
-static int bigint_bn_MulFunc(HOBJECT object, HOBJECT src0, HOBJECT src1)
-{ 
+static int bigint_bn_Mul(HOBJECT object, HOBJECT src0, HOBJECT src1)
+{
 	sBigInteger* pobj;
 	IBigNumber** psrc0;
 	IBigNumber** psrc1;
 	unsigned int* buf;
-	int widthobj, widthsrc0, widthsrc1;
+	int widthobj, widthsrc0, widthsrc1, width;
+	int objunsigned, src0unsigned, src1unsigned;
 	int i, j;
 	pobj = (sBigInteger*)objectThis(object);
 	if (EIID_OK != objectQueryInterface(src0, IID_BIGNUMBER, (void**)&psrc0)) {
@@ -1054,31 +1033,32 @@ static int bigint_bn_MulFunc(HOBJECT object, HOBJECT src0, HOBJECT src1)
 	if (EIID_OK != objectQueryInterface(src1, IID_BIGNUMBER, (void**)&psrc1)) {
 		objectRelease(psrc0);
 		return -1;
-	} 
+	}
 	widthobj = pobj->width;
 	widthsrc0 = objectCall0(psrc0, GetWidth);
 	widthsrc1 = objectCall0(psrc1, GetWidth);
-	if (widthsrc0 < widthobj) {
-		objectCall1(psrc0, SetWidth, widthobj);
-	}
-	else {
-		objectCall1(psrc0, SetWidth, widthsrc0);
-	}
-	if (widthsrc1 < widthobj) {
-		objectCall1(psrc1, SetWidth, widthobj);
-	} 
-	else {
-		objectCall1(psrc1, SetWidth, widthsrc1);
-	}
-	pobj->buflen = (pobj->width + CELL_WIDTH - 1) / CELL_WIDTH;
-	if (pobj->buflen < 2)
-		pobj->buflen = 2;
-	buf = (unsigned int*)malloc(pobj->buflen * CELL_WIDTH / 8);
-	if (buf == NULL) {
-		objectRelease(psrc0);
-		objectRelease(psrc1);
+
+	objunsigned = pobj->isunsigned;
+	src0unsigned = objectCall0(psrc0, IsUnsigned);
+	src1unsigned = objectCall0(psrc1, IsUnsigned);
+
+	bigint_bn_SetUnsigned(object, 0);
+	objectCall1(psrc0, SetUnsigned, 0);
+	objectCall1(psrc1, SetUnsigned, 0);
+
+	width = widthobj;
+	if (width < widthsrc0)
+		width = widthsrc0;
+	if (width < widthsrc1)
+		width = widthsrc1;
+
+	objectCall1(psrc0, SetWidth, width);
+	objectCall1(psrc1, SetWidth, width);
+	bigint_bn_SetWidth(object,width);
+	
+	buf = (unsigned int *)malloc(pobj->buflen * sizeof(unsigned int));
+	if (buf == NULL)
 		return -1;
-	}
 
 	for (i = 0; i < pobj->buflen; i++)
 		buf[i] = 0;
@@ -1092,30 +1072,26 @@ static int bigint_bn_MulFunc(HOBJECT object, HOBJECT src0, HOBJECT src1)
 		for (j = 0; j < pobj->buflen - i; j++) {
 			objectCall2(psrc1, GetBits32, j, &m1s);
 			m1 = m1s;
-			m1 = m0 * m1 + addin + buf[i+j];
+			m1 = m0 * m1 + addin + buf[i + j];
 			buf[i + j] = m1 & CELL_MASK;
 			addin = m1 >> CELL_WIDTH;
 		}
 	}
 	free(pobj->buf);
 	pobj->buf = buf;
+
+	bigint_bn_SetUnsigned(object, objunsigned);
+	objectCall1(psrc0, SetUnsigned, src0unsigned);
+	objectCall1(psrc1, SetUnsigned, src1unsigned);
+
 	bigint_bn_SetWidth(object, widthobj);
-	if (widthsrc0 < widthobj) {
-		objectCall1(psrc0, SetWidth, widthsrc0);
-	}
-	if (widthsrc1 < widthobj) {
-		objectCall1(psrc1, SetWidth, widthsrc1);
-	}
+	objectCall1(psrc0, SetWidth, widthsrc0);
+	objectCall1(psrc1, SetWidth, widthsrc1);
 	objectRelease(psrc0);
 	objectRelease(psrc1);
 	return 0;
 }
 
-static int bigint_bn_Mul(HOBJECT object, HOBJECT src0, HOBJECT src1)
-{
-	return bigint_bn_MulFunc(object, src0, src1);
-}
-
 static int bigint_bn_Div(HOBJECT object, HOBJECT src0, HOBJECT src1)
 { 
 	sBigInteger* pobj;
@@ -1383,8 +1359,8 @@ static int bigint_bn_IsNotZero(HOBJECT object)
 	pobj = (sBigInteger*)objectThis(object);
 	for (i = 0; i < pobj->buflen; i++)
 		if (pobj->buf[i] != 0)
-			return 0;
-	return 1;
+			return 1;
+	return 0;
 }
 
 static int bigint_bn_IsNeg(HOBJECT object)
@@ -1661,8 +1637,10 @@ static int bigint_bn_SHL(HOBJECT object, HOBJECT src, int bits)
 	int ifrom, ito, i;
 	unsigned long long current, next;
 
-	if (bits == 0)
+	if (bits == 0) {
+		bigint_bn_Assign(object, src);
 		return 0;
+	}
 
 	if (bits < 0)
 		return bigint_bn_SHR(object, src, -bits);
@@ -1713,8 +1691,10 @@ static int bigint_bn_SHR(HOBJECT object, HOBJECT src, int bits)
 	int ifrom, ito, i, zerolen;
 	unsigned long long current, next;
 	pobj = (sBigInteger*)objectThis(object);
-	if (bits == 0)
+	if (bits == 0) {
+		bigint_bn_Assign(object, src);
 		return 0;
+	}
 	if (bits < 0)
 		return bigint_bn_SHL(object, src, -bits);
 	if (EIID_OK != objectQueryInterface(src, IID_BIGNUMBER, (void**)&psrc)) {
diff --git a/examples/terris/src/copylines.c b/examples/terris/src/copylines.c
index 9ff94b2..47f3f38 100644
--- a/examples/terris/src/copylines.c
+++ b/examples/terris/src/copylines.c
@@ -196,7 +196,7 @@ static int terris_copylines_hdl4se_unit_GetValue(HOBJECT object, int index, int
 {
 	sTerrisCopyLines* pobj;
 	pobj = (sTerrisCopyLines*)objectThis(object);
-	int y;
+	unsigned int y;
 	y = pobj->readindex_1 + pobj->fromline_reg;
 	if (index == 2) { /* wCtrlStateComplete */
 		objectCall1(value, AssignUint32, (y > YCOUNT)?1:0);
@@ -205,7 +205,7 @@ static int terris_copylines_hdl4se_unit_GetValue(HOBJECT object, int index, int
 		objectCall1(value, AssignUint32, pobj->readindex + pobj->fromline_reg);
 	}
 	else if (index == 5) {/* wWrite */
-		if (pobj->readindex_1 >= 0 && pobj->fromline_reg >= 0 && (y >= 1) && (y <= YCOUNT))
+		if ((y >= 1) && (y <= YCOUNT))
 			objectCall1(value, AssignUint32, 1);
 		else
 			objectCall1(value, AssignUint32, 0);
diff --git a/examples/terris/src/flushtodisp.c b/examples/terris/src/flushtodisp.c
index 2f23608..0a9b6b3 100644
--- a/examples/terris/src/flushtodisp.c
+++ b/examples/terris/src/flushtodisp.c
@@ -217,7 +217,7 @@ static unsigned int terris_flushtodisp_hdl4se_unit_GetWriteData(sTerrisFlushToDi
 		unsigned int blockx, blocky;
 		int i;
 
-		int y = pobj->flushreadaddr_last >> 1;
+		unsigned int y = pobj->flushreadaddr_last >> 1;
 		
 		objectCall3(pobj->input_unit[7], GetValue, pobj->input_index[7], 16, pobj->inputdata);
 		objectCall1(pobj->inputdata, GetUint32, &blockpos);
diff --git a/examples/terris/src/main.c b/examples/terris/src/main.c
index 77a52b3..2d1521f 100644
--- a/examples/terris/src/main.c
+++ b/examples/terris/src/main.c
@@ -100,7 +100,14 @@ int main(int argc, char* argv[])
 	objectCall2(vcdfile, AddSignal, "/simulator/main/bram_WriteAddr", "out");
 	objectCall2(vcdfile, AddSignal, "/simulator/main/wram_Write", "out");
 	objectCall2(vcdfile, AddSignal, "/simulator/main/wCtrlStateComplete", "out");
-	objectCall2(vcdfile, AddSignal, "/simulator/main/wInitCtrlStateComplete", "out");
+	objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/wirein_readaddr", "out");
+	objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/wireout_readaddr", "out");
+	objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/wireout_readaddr_delay_1", "out");
+	objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/bWriteDataSel", "out");
+	objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/curblockline", "out");
+	objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/line", "out");
+	objectCall2(vcdfile, AddSignal, "/simulator/main/wFlushCtrlStateComplete", "out");
+	objectCall2(vcdfile, AddSignal, "/simulator/main/bram_ReadData", "out");
 	objectCall1(vcdfile, SetTopModule, sim);
 	objectCall0(vcdfile, StartRecord);
 #endif
diff --git a/examples/terris/src/terris_ctrl.c b/examples/terris/src/terris_ctrl.c
index 59c946d..bbab05c 100644
--- a/examples/terris/src/terris_ctrl.c
+++ b/examples/terris/src/terris_ctrl.c
@@ -47,21 +47,16 @@
 /*
 0: input           wClk,
 1: input           nwReset,
-2: output          wWrite,
-3: output[5:0]    bWriteAddr,
-4: output[63:0]   bWriteData,
-5: output[5:0]    bReadAddr,
-6: input[63:0]   bReadData,
-7: input[31:0]   bKeyData,
-8: input           wStateComplete,
-9: output[3:0]    bState,
-10: output[31:0]   bScore,
-11: output[31:0]   bSpeed,
-12: output[31:0]   bLevel,
-13: output [63:0]   bNextBlock,
-14: output [63:0]   bCurBlock;
-15: output [15:0]    bCurBlockPos;
-16: intput [31:0]    bResult
+2: input[31:0]   bKeyData,
+3: input           wStateComplete,
+4: output[3:0]    bState,
+5: output[31:0]   bScore,
+6: output[31:0]   bSpeed,
+7: output[31:0]   bLevel,
+8: output [63:0]   bNextBlock,
+9: output [63:0]   bCurBlock;
+10: output [15:0]    bCurBlockPos;
+11: intput [31:0]    bResult
 */
 
 struct _sTerrisCtrl1;
@@ -75,10 +70,6 @@ struct _sTerrisCtrl1 {
 	IHDL4SEModule** parent;
 	char* name;
 
-	IHDL4SEUnit** readdata_unit;
-	int           readdata_index;
-	IBigNumber**  readdata;
-
 	IHDL4SEUnit** keydata_unit;
 	IBigNumber**  keydata;
 	IBigNumber**  lastkeydata;
@@ -94,15 +85,6 @@ struct _sTerrisCtrl1 {
 	int           resultindex;
 	IBigNumber**  resultdata;
 
-	unsigned int write;
-	unsigned int writeaddr;
-	unsigned long long writedata;
-	unsigned int readaddr;
-	unsigned int write_reg;
-	unsigned int writeaddr_reg;
-	unsigned long long writedata_reg;
-	unsigned int readaddr_reg;
-
 	struct tagGenContext {
 		int index;
 		int complete;
@@ -163,8 +145,6 @@ static int terrisctrl1Create(const PARAMITEM* pParams, int paramcount, HOBJECT*
 	pobj->statecompletedata = bigintegerCreate(1);
 	pobj->resultunit = NULL;
 	pobj->resultdata = bigintegerCreate(32);
-	pobj->readdata_unit = NULL;
-	pobj->readdata = bigintegerCreate(64);
 	for (i = 0; i < paramcount; i++) {
 		if (pParams[i].name == PARAMID_HDL4SE_UNIT_NAME) {
 			if (pobj->name != NULL)
@@ -176,7 +156,6 @@ static int terrisctrl1Create(const PARAMITEM* pParams, int paramcount, HOBJECT*
 		}
 	}
 	pobj->genContext.index = 0;
-	pobj->write = 0;
 	pobj->state = -1;
 	terrisInit();
 	/* 返回生成的对象 */
@@ -215,28 +194,21 @@ static int terrisctrl1_hdl4se_unit_Connect(HOBJECT object, int index, HOBJECT fr
 	sTerrisCtrl1* pobj;
 	IHDL4SEUnit** unit = NULL;
 	pobj = (sTerrisCtrl1*)objectThis(object);
-	if (index == 6) {
-		if (0 == objectQueryInterface(from, IID_HDL4SEUNIT, (void**)&unit)) {
-			objectRelease(pobj->readdata_unit);
-			pobj->readdata_unit = unit;
-			pobj->readdata_index = fromindex;
-		}
-	}
-	else if (index == 7) {
+	if (index == 2) {
 		if (0 == objectQueryInterface(from, IID_HDL4SEUNIT, (void**)&unit)) {
 			objectRelease(pobj->keydata_unit);
 			pobj->keydata_unit = unit;
 			pobj->keydata_index = fromindex;
 		}
 	} 
-	else if (index == 8) {
+	else if (index == 3) {
 		if (0 == objectQueryInterface(from, IID_HDL4SEUNIT, (void**)&unit)) {
 			objectRelease(pobj->statecomplete_unit);
 			pobj->statecomplete_unit = unit;
 			pobj->statecomplete_index = fromindex;
 		}
 	}
-	else if (index == 16) {
+	else if (index == 11) {
 		if (0 == objectQueryInterface(from, IID_HDL4SEUNIT, (void**)&unit)) {
 			objectRelease(pobj->resultunit);
 			pobj->resultunit = unit;
@@ -260,31 +232,19 @@ static int terrisctrl1_hdl4se_unit_GetValue(HOBJECT object, int index, int width
 	int i;
 	sTerrisCtrl1* pobj;
 	pobj = (sTerrisCtrl1*)objectThis(object);
-	if (index == 2) {
-		objectCall1(value, AssignUint32, pobj->write_reg);
-	}
-	else if (index == 3) {
-		objectCall1(value, AssignUint32, pobj->writeaddr_reg);
-	}
-	else if (index == 4) {
-		objectCall1(value, AssignUint64, pobj->writedata_reg);
-	}
-	else if (index == 5) {
-		objectCall1(value, AssignUint32, pobj->readaddr_reg);
-	}
-	else if (index == 9) {
+	if (index == 4) {
 		objectCall1(value, AssignUint32, pobj->state_reg);
 	}
-	else if (index == 10) {
+	else if (index == 5) {
 		objectCall1(value, AssignUint32, gameScore);
 	}
-	else if (index == 11) {
+	else if (index == 6) {
 		objectCall1(value, AssignUint32, MAXSPPED - currentspeed);
 	}
-	else if (index == 12) {
+	else if (index == 7) {
 		objectCall1(value, AssignUint32, gameLevel);
 	}
-	else if (index == 13) {
+	else if (index == 8) {
 		unsigned long long data;
 		int i, j;
 		data = 0;
@@ -296,7 +256,7 @@ static int terrisctrl1_hdl4se_unit_GetValue(HOBJECT object, int index, int width
 		}
 		objectCall1(value, AssignUint64, data);
 	}
-	else if (index == 14) {
+	else if (index == 9) {
 		unsigned long long data;
 		int i, j;
 		data = 0;
@@ -308,7 +268,7 @@ static int terrisctrl1_hdl4se_unit_GetValue(HOBJECT object, int index, int width
 		}
 		objectCall1(value, AssignUint64, data);
 	}
-	else if (index == 15) {
+	else if (index == 10) {
 		if (pobj->state == ST_CHECKBLOCKCANSETTO) {
 			objectCall1(value, AssignUint32, ((pobj->blockCanSetToContext.x + 1) & 0xff) | (((YCOUNT + 1 - pobj->blockCanSetToContext.y) & 0xff) << 8));
 		}
@@ -453,7 +413,6 @@ static int terrisctrl1_hdl4se_unit_ClkTick(HOBJECT object)
 
 	pobj = (sTerrisCtrl1*)objectThis(object);
 
-	pobj->write = 0;
 	if (pobj->state == ST_INIT) {
 		objectCall3(pobj->statecomplete_unit, GetValue, pobj->statecomplete_index, 32, pobj->statecompletedata);
 		objectCall1(pobj->statecompletedata, GetUint32, &statecomplete);
@@ -514,7 +473,6 @@ static int terrisctrl1_hdl4se_unit_ClkTick(HOBJECT object)
 			objectCall1(pobj->resultdata, GetUint32, &pobj->genContext.index);
 			if (pobj->genContext.index < YCOUNT) {
 				pobj->genContext.startindex = pobj->genContext.index;
-				pobj->readaddr = pobj->genContext.index + 1;
 				pobj->state = ST_COPYLINES;
 				pobj->genContext.count++;
 			} else {
@@ -567,10 +525,6 @@ static int terrisctrl1_hdl4se_unit_Setup(HOBJECT object)
 	sTerrisCtrl1* pobj;
 	pobj = (sTerrisCtrl1*)objectThis(object);
 	pobj->state_reg = pobj->state;
-	pobj->write_reg = pobj->write;
-	pobj->writeaddr_reg = pobj->writeaddr;
-	pobj->writedata_reg = pobj->writedata;
-	pobj->readaddr_reg = pobj->readaddr;
 	pobj->lastkey = pobj->key;
 	return 0;
 }
diff --git a/examples/terris/src/terris_main_module.c b/examples/terris/src/terris_main_module.c
index b19b026..8ca0778 100644
--- a/examples/terris/src/terris_main_module.c
+++ b/examples/terris/src/terris_main_module.c
@@ -31,7 +31,7 @@
 
 
 /*
-*  Created by HDL4SE @ Fri Jun 25 17:13:15 2021
+*  Created by HDL4SE @ Sat Jun 26 10:06:29 2021
 *  Don't edit it.
 */
 
@@ -47,98 +47,12 @@
 #include "verilog_parsetree.h"
 
 
-IHDL4SEUnit** hdl4seCreate_0015(IHDL4SEModule** parent, const char* instanceparam, const char* name)
-{ /* module panelinit */
-	IHDL4SEModule**	module;
-	IHDL4SEUnit**	unit;
-	IHDL4SEUnit**	nets[2];
-	int	__netswidth[2];
-	IHDL4SEUnit**	modules[1];
-	int __portswidth[6];
-	char __instparam[128];
-
-	/* 生成模块对象 */
-	unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name);
-	/* 得到对象的IHDL4SEModule 接口 */
-	objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module);
-
-	/* 端口 */
-	/*  0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT );
-	/*  0*/ __portswidth[0] = 1;
-	/*  1*/ objectCall4(module, AddPort, "bCtrlState",   4, 1, PORT_DIRECT_INPUT );
-	/*  1*/ __portswidth[1] = 4;
-	/*  2*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT);
-	/*  2*/ __portswidth[2] = 1;
-	/*  3*/ objectCall4(module, AddPort, "wInitWrite", 1, 1, PORT_DIRECT_OUTPUT);
-	/*  3*/ __portswidth[3] = 1;
-	/*  4*/ objectCall4(module, AddPort, "bInitWriteAddr",   6, 1, PORT_DIRECT_OUTPUT);
-	/*  4*/ __portswidth[4] = 6;
-	/*  5*/ objectCall4(module, AddPort, "bInitWriteData",  64, 1, PORT_DIRECT_OUTPUT);
-	/*  5*/ __portswidth[5] = 64;
-
-	/* 线网 */
-	nets[  0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  8", "wirein_writeaddr");
-	__netswidth[0] = 8;
-	nets[  1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  8", "wireout_writeaddr");
-	__netswidth[1] = 8;
-
-/* 模块实例化 */
-	modules[  0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramwriteaddr");
-	objectCall3(modules[0], Connect, 0, unit, 0);
-	objectCall3(modules[0], Connect, 1, nets[0], 0);
-	objectCall3(nets[1], Connect, 0, modules[0], 2);
-
-	/* 持续性赋值 */
-	/* assign bInitWriteData = 32'h0; */
-	IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h0", "tempvar_0");
-	objectCall3(unit, Connect, 5, tempvar_0, 0);
-	/* assign wirein_writeaddr = bCtrlState==0?wireout_writeaddr+1:0; */
-	IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_3");
-	sprintf(__instparam, "%d, %d, %d, %d", __portswidth[1], 1, 1, BINOP_EQ);
-	IHDL4SEUnit **tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_2");
-	objectCall3(tempvar_2, Connect, 0, unit, 1);
-	objectCall3(tempvar_2, Connect, 1, tempvar_3, 0);
-	IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_5");
-	sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 1, 0, BINOP_ADD);
-	IHDL4SEUnit **tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_4");
-	objectCall3(tempvar_4, Connect, 0, nets[1], 0);
-	objectCall3(tempvar_4, Connect, 1, tempvar_5, 0);
-	IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_6");
-	IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "0", "tempvar_1");
-	objectCall3(tempvar_1, Connect, 0, tempvar_2, 2);
-	objectCall3(tempvar_1, Connect, 1, tempvar_6, 0);
-	objectCall3(tempvar_1, Connect, 2, tempvar_4, 2);
-	objectCall3(nets[0], Connect, 0, tempvar_1, 3);
-	/* assign wInitWrite = wireout_writeaddr<=24; */
-	IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_8");
-	sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 5, 1, BINOP_LE);
-	IHDL4SEUnit **tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_7");
-	objectCall3(tempvar_7, Connect, 0, nets[1], 0);
-	objectCall3(tempvar_7, Connect, 1, tempvar_8, 0);
-	objectCall3(unit, Connect, 3, tempvar_7, 2);
-	/* assign wCtrlStateComplete = wireout_writeaddr>24; */
-	IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 24", "tempvar_10");
-	sprintf(__instparam, "%d, %d, %d, %d", __netswidth[1], 6, 1, BINOP_GT);
-	IHDL4SEUnit **tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, __instparam, "tempvar_9");
-	objectCall3(tempvar_9, Connect, 0, nets[1], 0);
-	objectCall3(tempvar_9, Connect, 1, tempvar_10, 0);
-	objectCall3(unit, Connect, 2, tempvar_9, 2);
-	/* assign bInitWriteAddr = wireout_writeaddr; */
-	objectCall3(unit, Connect, 4, nets[1], 0);
-
-	/*释放module接口*/
-	objectRelease(module);
-	/*返回unit接口*/
-	return unit;
-}
-
-
 IHDL4SEUnit** hdl4seCreate_0017(IHDL4SEModule** parent, const char* instanceparam, const char* name)
 { /* module main */
 	IHDL4SEModule**	module;
 	IHDL4SEUnit**	unit;
-	IHDL4SEUnit**	nets[41];
-	int	__netswidth[41];
+	IHDL4SEUnit**	nets[37];
+	int	__netswidth[37];
 	IHDL4SEUnit**	modules[14];
 	int __portswidth[9];
 	char __instparam[128];
@@ -179,78 +93,70 @@ IHDL4SEUnit** hdl4seCreate_0017(IHDL4SEModule** parent, const char* instancepara
 	__netswidth[3] = 6;
 	nets[  4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bram_ReadData");
 	__netswidth[4] = 64;
-	nets[  5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCtrlWrite");
-	__netswidth[5] = 1;
-	nets[  6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCtrlWriteAddr");
-	__netswidth[6] = 6;
-	nets[  7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCtrlWriteData");
-	__netswidth[7] = 64;
-	nets[  8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCtrlReadAddr");
-	__netswidth[8] = 6;
-	nets[  9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlKeyData");
+	nets[  5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlKeyData");
+	__netswidth[5] = 32;
+	nets[  6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCtrlStateComplete");
+	__netswidth[6] = 1;
+	nets[  7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  4", "bCtrlState");
+	__netswidth[7] = 4;
+	nets[  8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlSpeed");
+	__netswidth[8] = 32;
+	nets[  9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlLevel");
 	__netswidth[9] = 32;
-	nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCtrlStateComplete");
-	__netswidth[10] = 1;
-	nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  4", "bCtrlState");
-	__netswidth[11] = 4;
-	nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlSpeed");
-	__netswidth[12] = 32;
-	nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlLevel");
-	__netswidth[13] = 32;
-	nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlScore");
+	nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlScore");
+	__netswidth[10] = 32;
+	nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bNextBlock");
+	__netswidth[11] = 64;
+	nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCurBlock");
+	__netswidth[12] = 64;
+	nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "bCurBlockPos");
+	__netswidth[13] = 16;
+	nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bResult");
 	__netswidth[14] = 32;
-	nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bNextBlock");
-	__netswidth[15] = 64;
-	nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCurBlock");
-	__netswidth[16] = 64;
-	nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "bCurBlockPos");
-	__netswidth[17] = 16;
-	nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bResult");
-	__netswidth[18] = 32;
-	nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bFlushReadAddr");
-	__netswidth[19] = 6;
-	nets[ 20] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wFlushCtrlStateComplete");
+	nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bFlushReadAddr");
+	__netswidth[15] = 6;
+	nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wFlushCtrlStateComplete");
+	__netswidth[16] = 1;
+	nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bBWReadAddr");
+	__netswidth[17] = 6;
+	nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bBWWriteAddr");
+	__netswidth[18] = 6;
+	nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bBWWriteData");
+	__netswidth[19] = 64;
+	nets[ 20] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wBWCtrlStateComplete");
 	__netswidth[20] = 1;
-	nets[ 21] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bBWReadAddr");
-	__netswidth[21] = 6;
-	nets[ 22] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bBWWriteAddr");
+	nets[ 21] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wBWWrite");
+	__netswidth[21] = 1;
+	nets[ 22] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCBWReadAddr");
 	__netswidth[22] = 6;
-	nets[ 23] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bBWWriteData");
-	__netswidth[23] = 64;
-	nets[ 24] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wBWCtrlStateComplete");
+	nets[ 23] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCBWCtrlStateComplete");
+	__netswidth[23] = 1;
+	nets[ 24] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCBWCanSetTo");
 	__netswidth[24] = 1;
-	nets[ 25] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wBWWrite");
-	__netswidth[25] = 1;
-	nets[ 26] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCBWReadAddr");
-	__netswidth[26] = 6;
-	nets[ 27] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCBWCtrlStateComplete");
-	__netswidth[27] = 1;
-	nets[ 28] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCBWCanSetTo");
-	__netswidth[28] = 1;
-	nets[ 29] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCKLReadAddr");
-	__netswidth[29] = 6;
-	nets[ 30] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCKLCtrlStateComplete");
+	nets[ 25] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCKLReadAddr");
+	__netswidth[25] = 6;
+	nets[ 26] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCKLCtrlStateComplete");
+	__netswidth[26] = 1;
+	nets[ 27] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCKLResult");
+	__netswidth[27] = 32;
+	nets[ 28] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bInitWriteAddr");
+	__netswidth[28] = 6;
+	nets[ 29] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bInitWriteData");
+	__netswidth[29] = 64;
+	nets[ 30] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wInitCtrlStateComplete");
 	__netswidth[30] = 1;
-	nets[ 31] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCKLResult");
-	__netswidth[31] = 32;
-	nets[ 32] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bInitWriteAddr");
+	nets[ 31] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wInitWrite");
+	__netswidth[31] = 1;
+	nets[ 32] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCLReadAddr");
 	__netswidth[32] = 6;
-	nets[ 33] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bInitWriteData");
-	__netswidth[33] = 64;
-	nets[ 34] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wInitCtrlStateComplete");
-	__netswidth[34] = 1;
-	nets[ 35] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wInitWrite");
+	nets[ 33] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCLWriteAddr");
+	__netswidth[33] = 6;
+	nets[ 34] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCLWriteData");
+	__netswidth[34] = 64;
+	nets[ 35] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCLCtrlStateComplete");
 	__netswidth[35] = 1;
-	nets[ 36] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCLReadAddr");
-	__netswidth[36] = 6;
-	nets[ 37] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  6", "bCLWriteAddr");
-	__netswidth[37] = 6;
-	nets[ 38] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCLWriteData");
-	__netswidth[38] = 64;
-	nets[ 39] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCLCtrlStateComplete");
-	__netswidth[39] = 1;
-	nets[ 40] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCLWrite");
-	__netswidth[40] = 1;
+	nets[ 36] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, "  1", "wCLWrite");
+	__netswidth[36] = 1;
 
 /* 模块实例化 */
 	modules[  0] = hdl4seCreateUnit2(module, "dffb1080-8b92-4b42-a607-d1b377c27bb1", "64, 5", "ram_0");
@@ -263,178 +169,177 @@ IHDL4SEUnit** hdl4seCreate_0017(IHDL4SEModule** parent, const char* instancepara
 	modules[  1] = hdl4seCreateUnit2(module, "158fa52-ca8b-4551-9b87-fc7cff466e2a", "", "ctrl");
 	objectCall3(modules[1], Connect, 0, unit, 0);
 	objectCall3(modules[1], Connect, 1, unit, 1);
-	objectCall3(nets[5], Connect, 0, modules[1], 2);
-	objectCall3(nets[6], Connect, 0, modules[1], 3);
+	objectCall3(modules[1], Connect, 2, nets[5], 0);
+	objectCall3(modules[1], Connect, 3, nets[6], 0);
 	objectCall3(nets[7], Connect, 0, modules[1], 4);
-	objectCall3(nets[8], Connect, 0, modules[1], 5);
-	objectCall3(modules[1], Connect, 6, nets[4], 0);
-	objectCall3(modules[1], Connect, 7, nets[9], 0);
-	objectCall3(modules[1], Connect, 8, nets[10], 0);
-	objectCall3(nets[11], Connect, 0, modules[1], 9);
-	objectCall3(nets[14], Connect, 0, modules[1], 10);
-	objectCall3(nets[12], Connect, 0, modules[1], 11);
-	objectCall3(nets[13], Connect, 0, modules[1], 12);
-	objectCall3(nets[15], Connect, 0, modules[1], 13);
-	objectCall3(nets[16], Connect, 0, modules[1], 14);
-	objectCall3(nets[17], Connect, 0, modules[1], 15);
-	objectCall3(modules[1], Connect, 16, nets[18], 0);
+	objectCall3(nets[10], Connect, 0, modules[1], 5);
+	objectCall3(nets[8], Connect, 0, modules[1], 6);
+	objectCall3(nets[9], Connect, 0, modules[1], 7);
+	objectCall3(nets[11], Connect, 0, modules[1], 8);
+	objectCall3(nets[12], Connect, 0, modules[1], 9);
+	objectCall3(nets[13], Connect, 0, modules[1], 10);
+	objectCall3(modules[1], Connect, 11, nets[14], 0);
 	modules[  2] = hdl4seCreateUnit2(module, "d588064-fcd3-43cc-b131-1a64c74d9e86", "", "flusher");
 	objectCall3(modules[2], Connect, 0, unit, 0);
-	objectCall3(modules[2], Connect, 1, nets[11], 0);
-	objectCall3(nets[20], Connect, 0, modules[2], 2);
-	objectCall3(nets[19], Connect, 0, modules[2], 3);
+	objectCall3(modules[2], Connect, 1, nets[7], 0);
+	objectCall3(nets[16], Connect, 0, modules[2], 2);
+	objectCall3(nets[15], Connect, 0, modules[2], 3);
 	objectCall3(modules[2], Connect, 4, nets[4], 0);
 	objectCall3(unit, Connect, 2, modules[2], 5);
 	objectCall3(unit, Connect, 3, modules[2], 6);
 	objectCall3(unit, Connect, 4, modules[2], 7);
-	objectCall3(modules[2], Connect, 8, nets[12], 0);
-	objectCall3(modules[2], Connect, 9, nets[13], 0);
-	objectCall3(modules[2], Connect, 10, nets[14], 0);
-	objectCall3(modules[2], Connect, 11, nets[15], 0);
-	objectCall3(modules[2], Connect, 12, nets[16], 0);
-	objectCall3(modules[2], Connect, 13, nets[17], 0);
+	objectCall3(modules[2], Connect, 8, nets[8], 0);
+	objectCall3(modules[2], Connect, 9, nets[9], 0);
+	objectCall3(modules[2], Connect, 10, nets[10], 0);
+	objectCall3(modules[2], Connect, 11, nets[11], 0);
+	objectCall3(modules[2], Connect, 12, nets[12], 0);
+	objectCall3(modules[2], Connect, 13, nets[13], 0);
 	modules[  3] = hdl4seCreateUnit2(module, "b0d75037-0831-49e5-bbd0-f6b5e07cbb51", "", "blockwriter");
 	objectCall3(modules[3], Connect, 0, unit, 0);
-	objectCall3(modules[3], Connect, 1, nets[11], 0);
-	objectCall3(nets[24], Connect, 0, modules[3], 2);
-	objectCall3(nets[21], Connect, 0, modules[3], 3);
+	objectCall3(modules[3], Connect, 1, nets[7], 0);
+	objectCall3(nets[20], Connect, 0, modules[3], 2);
+	objectCall3(nets[17], Connect, 0, modules[3], 3);
 	objectCall3(modules[3], Connect, 4, nets[4], 0);
-	objectCall3(nets[25], Connect, 0, modules[3], 5);
-	objectCall3(nets[22], Connect, 0, modules[3], 6);
-	objectCall3(nets[23], Connect, 0, modules[3], 7);
-	objectCall3(modules[3], Connect, 8, nets[16], 0);
-	objectCall3(modules[3], Connect, 9, nets[17], 0);
+	objectCall3(nets[21], Connect, 0, modules[3], 5);
+	objectCall3(nets[18], Connect, 0, modules[3], 6);
+	objectCall3(nets[19], Connect, 0, modules[3], 7);
+	objectCall3(modules[3], Connect, 8, nets[12], 0);
+	objectCall3(modules[3], Connect, 9, nets[13], 0);
 	modules[  4] = hdl4seCreateUnit2(module, "90e0e478-1b32-417e-ab32-e5bdec608431", "", "blocksetto");
 	objectCall3(modules[4], Connect, 0, unit, 0);
-	objectCall3(modules[4], Connect, 1, nets[11], 0);
-	objectCall3(nets[27], Connect, 0, modules[4], 2);
-	objectCall3(nets[26], Connect, 0, modules[4], 3);
+	objectCall3(modules[4], Connect, 1, nets[7], 0);
+	objectCall3(nets[23], Connect, 0, modules[4], 2);
+	objectCall3(nets[22], Connect, 0, modules[4], 3);
 	objectCall3(modules[4], Connect, 4, nets[4], 0);
-	objectCall3(modules[4], Connect, 5, nets[16], 0);
-	objectCall3(modules[4], Connect, 6, nets[17], 0);
-	objectCall3(nets[28], Connect, 0, modules[4], 7);
+	objectCall3(modules[4], Connect, 5, nets[12], 0);
+	objectCall3(modules[4], Connect, 6, nets[13], 0);
+	objectCall3(nets[24], Connect, 0, modules[4], 7);
 	modules[  5] = hdl4seCreateUnit2(module, "e39fa78d-7faa-4278-a27f-07b68a99afff", "", "checkliner");
 	objectCall3(modules[5], Connect, 0, unit, 0);
-	objectCall3(modules[5], Connect, 1, nets[11], 0);
-	objectCall3(nets[30], Connect, 0, modules[5], 2);
-	objectCall3(nets[29], Connect, 0, modules[5], 3);
+	objectCall3(modules[5], Connect, 1, nets[7], 0);
+	objectCall3(nets[26], Connect, 0, modules[5], 2);
+	objectCall3(nets[25], Connect, 0, modules[5], 3);
 	objectCall3(modules[5], Connect, 4, nets[4], 0);
-	objectCall3(nets[31], Connect, 0, modules[5], 5);
-	modules[  6] = hdl4seCreate_0015(module, "", "initor");
+	objectCall3(nets[27], Connect, 0, modules[5], 5);
+	modules[  6] = hdl4seCreateUnit2(module, "d6ef2a03-4c58-4b50-a966-44e156694304", "", "initor");
 	objectCall3(modules[6], Connect, 0, unit, 0);
-	objectCall3(modules[6], Connect, 1, nets[11], 0);
-	objectCall3(nets[34], Connect, 0, modules[6], 2);
-	objectCall3(nets[35], Connect, 0, modules[6], 3);
-	objectCall3(nets[32], Connect, 0, modules[6], 4);
-	objectCall3(nets[33], Connect, 0, modules[6], 5);
+	objectCall3(modules[6], Connect, 1, nets[7], 0);
+	objectCall3(nets[30], Connect, 0, modules[6], 2);
+	objectCall3(nets[31], Connect, 0, modules[6], 3);
+	objectCall3(nets[28], Connect, 0, modules[6], 4);
+	objectCall3(nets[29], Connect, 0, modules[6], 5);
 	modules[  7] = hdl4seCreateUnit2(module, "abaa9033-f807-4279-93dc-636fd22dcb90", "", "lineclear");
 	objectCall3(modules[7], Connect, 0, unit, 0);
-	objectCall3(modules[7], Connect, 1, nets[11], 0);
-	objectCall3(nets[39], Connect, 0, modules[7], 2);
-	objectCall3(nets[36], Connect, 0, modules[7], 3);
+	objectCall3(modules[7], Connect, 1, nets[7], 0);
+	objectCall3(nets[35], Connect, 0, modules[7], 2);
+	objectCall3(nets[32], Connect, 0, modules[7], 3);
 	objectCall3(modules[7], Connect, 4, nets[4], 0);
-	objectCall3(nets[40], Connect, 0, modules[7], 5);
-	objectCall3(nets[37], Connect, 0, modules[7], 6);
-	objectCall3(nets[38], Connect, 0, modules[7], 7);
-	objectCall3(modules[7], Connect, 8, nets[17], 0);
+	objectCall3(nets[36], Connect, 0, modules[7], 5);
+	objectCall3(nets[33], Connect, 0, modules[7], 6);
+	objectCall3(nets[34], Connect, 0, modules[7], 7);
+	objectCall3(modules[7], Connect, 8, nets[13], 0);
 	modules[  8] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "32", "mux_Result");
-	objectCall3(modules[8], Connect, 0, nets[11], 0);
+	objectCall3(modules[8], Connect, 0, nets[7], 0);
 	IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_0");
 	objectCall3(modules[8], Connect, 1, tempvar_0, 0);
 	IHDL4SEUnit** tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_1");
 	objectCall3(modules[8], Connect, 2, tempvar_1, 0);
 	IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_2");
 	objectCall3(modules[8], Connect, 3, tempvar_2, 0);
-	objectCall3(modules[8], Connect, 4, nets[28], 0);
+	objectCall3(modules[8], Connect, 4, nets[24], 0);
 	IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_3");
 	objectCall3(modules[8], Connect, 5, tempvar_3, 0);
-	objectCall3(modules[8], Connect, 6, nets[31], 0);
+	objectCall3(modules[8], Connect, 6, nets[27], 0);
 	IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_4");
 	objectCall3(modules[8], Connect, 7, tempvar_4, 0);
 	IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_5");
 	objectCall3(modules[8], Connect, 8, tempvar_5, 0);
-	objectCall3(nets[18], Connect, 0, modules[8], 9);
+	objectCall3(nets[14], Connect, 0, modules[8], 9);
 	modules[  9] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "1", "mux_Complete");
-	objectCall3(modules[9], Connect, 0, nets[11], 0);
-	objectCall3(modules[9], Connect, 1, nets[34], 0);
-	objectCall3(modules[9], Connect, 2, nets[20], 0);
-	IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_6");
+	objectCall3(modules[9], Connect, 0, nets[7], 0);
+	objectCall3(modules[9], Connect, 1, nets[30], 0);
+	objectCall3(modules[9], Connect, 2, nets[16], 0);
+	IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_6");
 	objectCall3(modules[9], Connect, 3, tempvar_6, 0);
-	objectCall3(modules[9], Connect, 4, nets[27], 0);
-	objectCall3(modules[9], Connect, 5, nets[24], 0);
-	objectCall3(modules[9], Connect, 6, nets[30], 0);
-	objectCall3(modules[9], Connect, 7, nets[39], 0);
-	IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_7");
+	objectCall3(modules[9], Connect, 4, nets[23], 0);
+	objectCall3(modules[9], Connect, 5, nets[20], 0);
+	objectCall3(modules[9], Connect, 6, nets[26], 0);
+	objectCall3(modules[9], Connect, 7, nets[35], 0);
+	IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_7");
 	objectCall3(modules[9], Connect, 8, tempvar_7, 0);
-	objectCall3(nets[10], Connect, 0, modules[9], 9);
+	objectCall3(nets[6], Connect, 0, modules[9], 9);
 	modules[ 10] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "1", "mux_ramWrite");
-	objectCall3(modules[10], Connect, 0, nets[11], 0);
-	objectCall3(modules[10], Connect, 1, nets[35], 0);
-	IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_8");
+	objectCall3(modules[10], Connect, 0, nets[7], 0);
+	objectCall3(modules[10], Connect, 1, nets[31], 0);
+	IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_8");
 	objectCall3(modules[10], Connect, 2, tempvar_8, 0);
-	objectCall3(modules[10], Connect, 3, nets[5], 0);
-	IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_9");
-	objectCall3(modules[10], Connect, 4, tempvar_9, 0);
-	objectCall3(modules[10], Connect, 5, nets[25], 0);
-	IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_10");
-	objectCall3(modules[10], Connect, 6, tempvar_10, 0);
-	objectCall3(modules[10], Connect, 7, nets[40], 0);
-	IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_11");
-	objectCall3(modules[10], Connect, 8, tempvar_11, 0);
+	IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_9");
+	objectCall3(modules[10], Connect, 3, tempvar_9, 0);
+	IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_10");
+	objectCall3(modules[10], Connect, 4, tempvar_10, 0);
+	objectCall3(modules[10], Connect, 5, nets[21], 0);
+	IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_11");
+	objectCall3(modules[10], Connect, 6, tempvar_11, 0);
+	objectCall3(modules[10], Connect, 7, nets[36], 0);
+	IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_12");
+	objectCall3(modules[10], Connect, 8, tempvar_12, 0);
 	objectCall3(nets[0], Connect, 0, modules[10], 9);
 	modules[ 11] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "6", "mux_ramWriteAddr");
-	objectCall3(modules[11], Connect, 0, nets[11], 0);
-	objectCall3(modules[11], Connect, 1, nets[32], 0);
-	IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_12");
-	objectCall3(modules[11], Connect, 2, tempvar_12, 0);
-	objectCall3(modules[11], Connect, 3, nets[6], 0);
-	IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_13");
-	objectCall3(modules[11], Connect, 4, tempvar_13, 0);
-	objectCall3(modules[11], Connect, 5, nets[22], 0);
-	IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_14");
-	objectCall3(modules[11], Connect, 6, tempvar_14, 0);
-	objectCall3(modules[11], Connect, 7, nets[37], 0);
-	IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_15");
-	objectCall3(modules[11], Connect, 8, tempvar_15, 0);
+	objectCall3(modules[11], Connect, 0, nets[7], 0);
+	objectCall3(modules[11], Connect, 1, nets[28], 0);
+	IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_13");
+	objectCall3(modules[11], Connect, 2, tempvar_13, 0);
+	IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_14");
+	objectCall3(modules[11], Connect, 3, tempvar_14, 0);
+	IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_15");
+	objectCall3(modules[11], Connect, 4, tempvar_15, 0);
+	objectCall3(modules[11], Connect, 5, nets[18], 0);
+	IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_16");
+	objectCall3(modules[11], Connect, 6, tempvar_16, 0);
+	objectCall3(modules[11], Connect, 7, nets[33], 0);
+	IHDL4SEUnit** tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_17");
+	objectCall3(modules[11], Connect, 8, tempvar_17, 0);
 	objectCall3(nets[1], Connect, 0, modules[11], 9);
 	modules[ 12] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "64", "mux_ramWriteData");
-	objectCall3(modules[12], Connect, 0, nets[11], 0);
-	objectCall3(modules[12], Connect, 1, nets[33], 0);
-	IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_16");
-	objectCall3(modules[12], Connect, 2, tempvar_16, 0);
-	objectCall3(modules[12], Connect, 3, nets[7], 0);
-	IHDL4SEUnit** tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_17");
-	objectCall3(modules[12], Connect, 4, tempvar_17, 0);
-	objectCall3(modules[12], Connect, 5, nets[23], 0);
-	IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_18");
-	objectCall3(modules[12], Connect, 6, tempvar_18, 0);
-	objectCall3(modules[12], Connect, 7, nets[38], 0);
-	IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_19");
-	objectCall3(modules[12], Connect, 8, tempvar_19, 0);
+	objectCall3(modules[12], Connect, 0, nets[7], 0);
+	objectCall3(modules[12], Connect, 1, nets[29], 0);
+	IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_18");
+	objectCall3(modules[12], Connect, 2, tempvar_18, 0);
+	IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_19");
+	objectCall3(modules[12], Connect, 3, tempvar_19, 0);
+	IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_20");
+	objectCall3(modules[12], Connect, 4, tempvar_20, 0);
+	objectCall3(modules[12], Connect, 5, nets[19], 0);
+	IHDL4SEUnit** tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_21");
+	objectCall3(modules[12], Connect, 6, tempvar_21, 0);
+	objectCall3(modules[12], Connect, 7, nets[34], 0);
+	IHDL4SEUnit** tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "64, 64'h000000000", "tempvar_22");
+	objectCall3(modules[12], Connect, 8, tempvar_22, 0);
 	objectCall3(nets[2], Connect, 0, modules[12], 9);
 	modules[ 13] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "6", "mux_ramReadAddr");
-	objectCall3(modules[13], Connect, 0, nets[11], 0);
-	IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_20");
-	objectCall3(modules[13], Connect, 1, tempvar_20, 0);
-	objectCall3(modules[13], Connect, 2, nets[19], 0);
-	objectCall3(modules[13], Connect, 3, nets[8], 0);
-	objectCall3(modules[13], Connect, 4, nets[26], 0);
-	objectCall3(modules[13], Connect, 5, nets[21], 0);
-	objectCall3(modules[13], Connect, 6, nets[29], 0);
-	objectCall3(modules[13], Connect, 7, nets[36], 0);
-	IHDL4SEUnit** tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_21");
-	objectCall3(modules[13], Connect, 8, tempvar_21, 0);
+	objectCall3(modules[13], Connect, 0, nets[7], 0);
+	IHDL4SEUnit** tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_23");
+	objectCall3(modules[13], Connect, 1, tempvar_23, 0);
+	objectCall3(modules[13], Connect, 2, nets[15], 0);
+	IHDL4SEUnit** tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_24");
+	objectCall3(modules[13], Connect, 3, tempvar_24, 0);
+	objectCall3(modules[13], Connect, 4, nets[22], 0);
+	objectCall3(modules[13], Connect, 5, nets[17], 0);
+	objectCall3(modules[13], Connect, 6, nets[25], 0);
+	objectCall3(modules[13], Connect, 7, nets[32], 0);
+	IHDL4SEUnit** tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "6, 0", "tempvar_25");
+	objectCall3(modules[13], Connect, 8, tempvar_25, 0);
 	objectCall3(nets[3], Connect, 0, modules[13], 9);
 
 	/* 持续性赋值 */
-	/* assign wRead = 32'h1; */
-	IHDL4SEUnit** tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h1", "tempvar_22");
-	objectCall3(unit, Connect, 6, tempvar_22, 0);
+	/* assign wRead = 1; */
+	IHDL4SEUnit** tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_26");
+	objectCall3(unit, Connect, 6, tempvar_26, 0);
 	/* assign bReadAddr = 32'hf0000000; */
-	IHDL4SEUnit** tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hf0000000", "tempvar_23");
-	objectCall3(unit, Connect, 7, tempvar_23, 0);
+	IHDL4SEUnit** tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hf0000000", "tempvar_27");
+	objectCall3(unit, Connect, 7, tempvar_27, 0);
 	/* assign bCtrlKeyData = bReadData; */
-	objectCall3(nets[9], Connect, 0, unit, 8);
+	objectCall3(nets[5], Connect, 0, unit, 8);
 
 	/*释放module接口*/
 	objectRelease(module);
diff --git a/examples/terris/verilog/canblocksetto.v b/examples/terris/verilog/canblocksetto.v
index 0dc7b36..85f617e 100644
--- a/examples/terris/verilog/canblocksetto.v
+++ b/examples/terris/verilog/canblocksetto.v
@@ -60,7 +60,7 @@ module canblocksetto(
     assign wirein_readaddr = (bCtrlState == `ST_CHECKBLOCKCANSETTO)? (wireout_readaddr + 1) : 0;
 
     assign wCanSet = wireout_cansetto;
-    assign bCBWReadAddr = wireout_readaddr + blocky - 2;
+    assign bCBWReadAddr = wireout_readaddr + blocky - 4;
     assign wCtrlStateComplete = wireout_readaddr_delay_1 > 4 || wireout_cansetto == 0;
 
     wire wCanSetCurrent, wCanSetCurrentPre;
@@ -70,14 +70,14 @@ module canblocksetto(
     
     assign wCanSetCurrentPre = ((wireout_readaddr > 0) && (wCanSetCurrent==0)) ? 0 : wireout_cansetto;
 
-	wire [7:0] y = wireout_readaddr_delay_1 + blocky - 2;
+	wire [7:0] y = wireout_readaddr_delay_1 + blocky;
 	wire wCanSetCurrent_1, wCanSetCurrent_2, wCanSetCurrent_3;
 	
 	wire [63:0] curblockline = (bCurBlock >> ((3 - wireout_readaddr_delay_1) * 16)) & 16'hffff;
 
-	assign wCanSetCurrent = (wireout_readaddr_delay_1 > 3 || y >= `YCOUNT || curblockline == 0) ? 1 : wCanSetCurrent_1;
+	assign wCanSetCurrent = ((wireout_readaddr_delay_1 > 4) || (y >= (`YCOUNT+4)) || (curblockline == 0)) ? 1 : wCanSetCurrent_1;
 
-	assign wCanSetCurrent_1 = (curblockline != 0 && y < 0) ? 0 : wCanSetCurrent_2;
+	assign wCanSetCurrent_1 = (curblockline != 0 && y < 4) ? 0 : wCanSetCurrent_2;
 
     wire [63:0] curblockline_0, curblockline_1, curblockline_2, curblockline_3, curblockline_mask, curblockline_mask_1;
 	assign curblockline_0 = (curblockline & 64'hf)?64'hf:64'h0;
diff --git a/examples/terris/verilog/checkline.v b/examples/terris/verilog/checkline.v
index c2af25f..53ce236 100644
--- a/examples/terris/verilog/checkline.v
+++ b/examples/terris/verilog/checkline.v
@@ -50,7 +50,7 @@ module checkline(
     assign wirein_readaddr = (bCtrlState == `ST_CHECKLINE)? (wireout_readaddr + 1) : 0;
     assign bCKLReadAddr = wireout_readaddr;
     assign bFindLine = wireout_readaddr_delay_1;
-    assign wCtrlStateComplete = (wireout_readaddr_delay_1 > `YCOUNT) || blockline;
+    assign wCtrlStateComplete = (wireout_readaddr_delay_1 > `YCOUNT) || (blockline && (wireout_readaddr > 0));
     wire block_0 = bCKLReadData[3:0] != 4'b0;
     wire block_1 = bCKLReadData[7:4] != 4'b0;
     wire block_2 = bCKLReadData[11:8] != 4'b0;
diff --git a/examples/terris/verilog/copylines.v b/examples/terris/verilog/copylines.v
index a72e8d2..8839d1e 100644
--- a/examples/terris/verilog/copylines.v
+++ b/examples/terris/verilog/copylines.v
@@ -49,13 +49,18 @@ module copylines(
 );
 
     wire [7:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1;
-    hdl4se_reg  #(6) ramreadaddr(wClk, wirein_readaddr, wireout_readaddr);
-    hdl4se_reg  #(6) ramreadaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1);
+    hdl4se_reg  #(6) reg_readaddr(wClk, wirein_readaddr, wireout_readaddr);
+    hdl4se_reg  #(6) reg_readaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1);
+
+    wire [15:0] wirein_fromline, wireout_fromline;
+    hdl4se_reg  #(6) reg_fromline(wClk, wirein_fromline, wireout_fromline);
+
     assign wirein_readaddr = (bCtrlState == `ST_COPYLINES)? (wireout_readaddr + 1) : 0;
-    wire [7:0] y = bFromLine + wireout_readaddr_delay_1;
+    assign wirein_fromline = (bCtrlState == `ST_COPYLINES)? bFromLine : 0;
+    wire [7:0] y = wireout_fromline + wireout_readaddr_delay_1;
     assign bWriteAddr = y - 1;
     assign bWriteData = bReadData;
-    assign wWrite = (wireout_readaddr_delay_1 < (`YCOUNT + 1)) && (y>=1) && (y<`YCOUNT+1);
-    assign wCtrlStateComplete = y >= `YCOUNT;
-    assign bReadAddr = bFromLine + wireout_readaddr;
+    assign wWrite = (y>=1) && (y<=`YCOUNT);
+    assign wCtrlStateComplete = y > `YCOUNT;
+    assign bReadAddr = wireout_fromline + wireout_readaddr;
 endmodule
diff --git a/examples/terris/verilog/flushtodisp.v b/examples/terris/verilog/flushtodisp.v
index 786d78b..5022222 100644
--- a/examples/terris/verilog/flushtodisp.v
+++ b/examples/terris/verilog/flushtodisp.v
@@ -37,7 +37,7 @@
     这一行如果存在，连接的就是c语言版本。
 */
 (* 
-  HDL4SE="LCOM", 
+  //HDL4SE="LCOM", 
   CLSID="d588064-fcd3-43cc-b131-1a64c74d9e86", 
   softmodule="hdl4se" 
 *)
@@ -72,10 +72,10 @@ module flushtodisp(
     hdl4se_reg  #(6) ramreadaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1);
     assign wirein_readaddr = (bCtrlState == `ST_FLUSHTODISP) ? wireout_readaddr + 1 : 6'b0;
     assign bFlushReadAddr = wireout_readaddr[6:1];
-    assign wCtrlStateComplete = wireout_readaddr == 6'd60; 
+    assign wCtrlStateComplete = wireout_readaddr == 8'd60; 
     assign bWriteAddr = 32'hf000_0010 + wireout_readaddr_delay_1 * 4;
     assign wWrite = (bCtrlState == `ST_FLUSHTODISP) ? 1 : 0;
-    wire [2:0] bWriteDataSel =  (wireout_readaddr_delay_1 < 6'd52)?3'd7:(wireout_readaddr_delay_1 - 6'd52);
+    wire [2:0] bWriteDataSel =  (wireout_readaddr_delay_1 < 8'd52)?3'd7:(wireout_readaddr_delay_1 - 8'd52);
     /* 
         0 -- 47，面板内容，    --> 7
         52, 53:  nextblock0, 1 --> 0, 1
diff --git a/examples/terris/verilog/panelinit.v b/examples/terris/verilog/panelinit.v
index 3b520a6..9c328e0 100644
--- a/examples/terris/verilog/panelinit.v
+++ b/examples/terris/verilog/panelinit.v
@@ -30,9 +30,9 @@
 ** THE POSSIBILITY OF SUCH DAMAGE.
 */
 /* panelinit.v */
-
+ 
 (* 
-  //HDL4SE="LCOM", 
+  HDL4SE="LCOM", 
   CLSID="d6ef2a03-4c58-4b50-a966-44e156694304",
   softmodule="hdl4se" 
 *)
diff --git a/examples/terris/verilog/terris_ctrl.v b/examples/terris/verilog/terris_ctrl.v
index 72318bf..3dc6871 100644
--- a/examples/terris/verilog/terris_ctrl.v
+++ b/examples/terris/verilog/terris_ctrl.v
@@ -31,7 +31,7 @@
 */
 /* terris_ctrl.v */
 
-/* 用c写的俄罗斯方块控制器V1 */
+/* 俄罗斯方块控制器V1 */
 (* 
   HDL4SE="LCOM", 
   CLSID="158fa52-ca8b-4551-9b87-fc7cff466e2a", 
@@ -41,11 +41,6 @@ module teris_ctrl
   (
     input           wClk,
     input           nwReset,
-    output          wWrite,
-    output [5:0]    bWriteAddr,
-    output [63:0]   bWriteData,
-    output [5:0]    bReadAddr,
-    input  [63:0]   bReadData,
     input  [31:0]   bKeyData,
     input           wStateComplete,
     output [3:0]    bState,
@@ -57,4 +52,46 @@ module teris_ctrl
     output [15:0]   bCurBlockPos,
     input  [31:0]   wResult
   );
+
+  wire [3:0] wirein_state, wireout_state;
+  hdl4se_reg  #(4) terris_ctrlstate(wClk, wirein_state, wireout_state);
+  assign bState = wireout_state;
+
+  wire [31:0] wirein_score, wireout_score;
+  hdl4se_reg  #(32) terris_score(wClk, wirein_score, wireout_score);
+  assign bScore = wireout_score;
+
+  wire [31:0] wirein_level, wireout_level;
+  hdl4se_reg  #(32) terris_level(wClk, wirein_level, wireout_level);
+  assign bLevel = wireout_level;
+
+  wire [31:0] wirein_speed, wireout_speed;
+  hdl4se_reg  #(32) terris_speed(wClk, wirein_speed, wireout_speed);
+  assign bSpeed = wireout_speed;
+
+  wire [15:0] wirein_curpos, wireout_curpos;
+  hdl4se_reg  #(15) terris_curpos(wClk, wirein_curpos, wireout_curpos);
+  assign bCurBlockPos = wireout_curpos;
+
+  wire [63:0] wirein_curblock, wireout_curblock;
+  hdl4se_reg  #(64) terris_curblock(wClk, wirein_curblock, wireout_curblock);
+  assign bCurBlock = wireout_curblock;
+
+  wire [63:0] wirein_nextblock, wireout_nextblock;
+  hdl4se_reg  #(64) terris_nextblock(wClk, wirein_nextblock, wireout_nextblock);
+  assign bNextBlock = wireout_nextblock;
+
+  hdl4se_mux8 #(32) mux_nextstate(
+        wireout_state,
+        `ST_FLUSHTODISP,             // 0: ST_INIT
+	    `ST_CHECKKEY,                // 1: ST_FLUSHTODISP,
+	    32'b0,                       // 2: ST_CHECKKEY,
+	    wCBWCanSetTo,                // 3: ST_CHECKBLOCKCANSETTO,
+	    32'b0,                       // 4: ST_BLOCKWRITE,
+	    bCKLResult,                  // 5: ST_CHECKLINE,
+        32'b0,                       // 6: ST_COPYLINES
+        32'b0,                       // 7: empty
+        bResult
+        );
+
 endmodule
\ No newline at end of file
diff --git a/examples/terris/verilog/terris_main.v b/examples/terris/verilog/terris_main.v
index be526a1..73f3e9e 100644
--- a/examples/terris/verilog/terris_main.v
+++ b/examples/terris/verilog/terris_main.v
@@ -79,10 +79,6 @@ module main(
     );
 
 /* 游戏控制器 */
-    wire          wCtrlWrite;
-    wire [5:0]    bCtrlWriteAddr;
-    wire [63:0]   bCtrlWriteData;
-    wire [5:0]    bCtrlReadAddr;
     wire [31:0]   bCtrlKeyData;
     wire          wCtrlStateComplete;
     wire [3:0]    bCtrlState;
@@ -94,8 +90,7 @@ module main(
     wire [15:0]   bCurBlockPos;
     wire [31:0]   bResult;
 
-	teris_ctrl ctrl(wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData, 
-                    bCtrlReadAddr,bram_ReadData, bCtrlKeyData,
+	teris_ctrl ctrl(wClk, nwReset, bCtrlKeyData,
                     wCtrlStateComplete, bCtrlState,
                     bCtrlScore, bCtrlSpeed, bCtrlLevel, 
                     bNextBlock, bCurBlock, bCurBlockPos,
@@ -194,7 +189,7 @@ module main(
         bCtrlState,
         wInitWrite,     // 0: ST_INIT
 	    1'b0,           // 1: ST_FLUSHTODISP,
-	    wCtrlWrite,     // 2: ST_CHECKKEY,
+	    1'b0,     // 2: ST_CHECKKEY,
 	    1'b0,           // 3: ST_CHECKBLOCKCANSETTO,
 	    wBWWrite,       // 4: ST_BLOCKWRITE,
 	    1'b0,           // 5: ST_CHECKLINE,
@@ -207,7 +202,7 @@ module main(
         bCtrlState,
         bInitWriteAddr, // 0: ST_INIT
 	    6'b0,           // 1: ST_FLUSHTODISP,
-	    bCtrlWriteAddr, // 2: ST_CHECKKEY,
+	    6'b0, // 2: ST_CHECKKEY,
 	    6'b0,           // 3: ST_CHECKBLOCKCANSETTO,
 	    bBWWriteAddr,   // 4: ST_BLOCKWRITE,
 	    6'b0,           // 5: ST_CHECKLINE,
@@ -220,7 +215,7 @@ module main(
         bCtrlState,
         bInitWriteData, // 0: ST_INIT
 	    64'b0,          // 1: ST_FLUSHTODISP,
-	    bCtrlWriteData, // 2: ST_CHECKKEY,
+	    64'b0, // 2: ST_CHECKKEY,
 	    64'b0,          // 3: ST_CHECKBLOCKCANSETTO,
 	    bBWWriteData,   // 4: ST_BLOCKWRITE,
 	    64'b0,          // 5: ST_CHECKLINE,
@@ -233,7 +228,7 @@ module main(
         bCtrlState,
         6'b0,           // 0: ST_INIT
 	    bFlushReadAddr,// 1: ST_FLUSHTODISP,
-	    bCtrlReadAddr, // 2: ST_CHECKKEY,
+	    6'b0, // 2: ST_CHECKKEY,
 	    bCBWReadAddr,  // 3: ST_CHECKBLOCKCANSETTO,
 	    bBWReadAddr,   // 4: ST_BLOCKWRITE,
 	    bCKLReadAddr,  // 5: ST_CHECKLINE,
diff --git a/examples/terris/verilog/terris_main_asm.v b/examples/terris/verilog/terris_main_asm.v
index dcacb82..50a4640 100644
--- a/examples/terris/verilog/terris_main_asm.v
+++ b/examples/terris/verilog/terris_main_asm.v
@@ -9,14 +9,14 @@ module hdl4se_mux2
 )
 (
   input  sel,
-  input  [WIDTH-1:0]  in0,
-  input  [WIDTH-1:0]  in1,
-  output  [WIDTH-1:0]  data
+  input  [(WIDTH-1):0]  in0,
+  input  [(WIDTH-1):0]  in1,
+  output  [(WIDTH-1):0]  data
 )
 ;
   wire sel;
-  wire [WIDTH-1:0]  in0;
-  wire [WIDTH-1:0]  in1;
+  wire [(WIDTH-1):0]  in0;
+  wire [(WIDTH-1):0]  in1;
 endmodule
 
 
@@ -31,18 +31,18 @@ module hdl4se_mux4
 )
 (
   input  [1:0]  sel,
-  input  [WIDTH-1:0]  in0,
-  input  [WIDTH-1:0]  in1,
-  input  [WIDTH-1:0]  in2,
-  input  [WIDTH-1:0]  in3,
-  output  [WIDTH-1:0]  data
+  input  [(WIDTH-1):0]  in0,
+  input  [(WIDTH-1):0]  in1,
+  input  [(WIDTH-1):0]  in2,
+  input  [(WIDTH-1):0]  in3,
+  output  [(WIDTH-1):0]  data
 )
 ;
   wire [1:0]  sel;
-  wire [WIDTH-1:0]  in0;
-  wire [WIDTH-1:0]  in1;
-  wire [WIDTH-1:0]  in2;
-  wire [WIDTH-1:0]  in3;
+  wire [(WIDTH-1):0]  in0;
+  wire [(WIDTH-1):0]  in1;
+  wire [(WIDTH-1):0]  in2;
+  wire [(WIDTH-1):0]  in3;
 endmodule
 
 
@@ -57,26 +57,26 @@ module hdl4se_mux8
 )
 (
   input  [2:0]  sel,
-  input  [WIDTH-1:0]  in0,
-  input  [WIDTH-1:0]  in1,
-  input  [WIDTH-1:0]  in2,
-  input  [WIDTH-1:0]  in3,
-  input  [WIDTH-1:0]  in4,
-  input  [WIDTH-1:0]  in5,
-  input  [WIDTH-1:0]  in6,
-  input  [WIDTH-1:0]  in7,
-  output  [WIDTH-1:0]  data
+  input  [(WIDTH-1):0]  in0,
+  input  [(WIDTH-1):0]  in1,
+  input  [(WIDTH-1):0]  in2,
+  input  [(WIDTH-1):0]  in3,
+  input  [(WIDTH-1):0]  in4,
+  input  [(WIDTH-1):0]  in5,
+  input  [(WIDTH-1):0]  in6,
+  input  [(WIDTH-1):0]  in7,
+  output  [(WIDTH-1):0]  data
 )
 ;
   wire [2:0]  sel;
-  wire [WIDTH-1:0]  in0;
-  wire [WIDTH-1:0]  in1;
-  wire [WIDTH-1:0]  in2;
-  wire [WIDTH-1:0]  in3;
-  wire [WIDTH-1:0]  in4;
-  wire [WIDTH-1:0]  in5;
-  wire [WIDTH-1:0]  in6;
-  wire [WIDTH-1:0]  in7;
+  wire [(WIDTH-1):0]  in0;
+  wire [(WIDTH-1):0]  in1;
+  wire [(WIDTH-1):0]  in2;
+  wire [(WIDTH-1):0]  in3;
+  wire [(WIDTH-1):0]  in4;
+  wire [(WIDTH-1):0]  in5;
+  wire [(WIDTH-1):0]  in6;
+  wire [(WIDTH-1):0]  in7;
 endmodule
 
 
@@ -91,42 +91,42 @@ module hdl4se_mux16
 )
 (
   input  [3:0]  sel,
-  input  [WIDTH-1:0]  in0,
-  input  [WIDTH-1:0]  in1,
-  input  [WIDTH-1:0]  in2,
-  input  [WIDTH-1:0]  in3,
-  input  [WIDTH-1:0]  in4,
-  input  [WIDTH-1:0]  in5,
-  input  [WIDTH-1:0]  in6,
-  input  [WIDTH-1:0]  in7,
-  input  [WIDTH-1:0]  in8,
-  input  [WIDTH-1:0]  in9,
-  input  [WIDTH-1:0]  in10,
-  input  [WIDTH-1:0]  in11,
-  input  [WIDTH-1:0]  in12,
-  input  [WIDTH-1:0]  in13,
-  input  [WIDTH-1:0]  in14,
-  input  [WIDTH-1:0]  in15,
-  output  [WIDTH-1:0]  data
+  input  [(WIDTH-1):0]  in0,
+  input  [(WIDTH-1):0]  in1,
+  input  [(WIDTH-1):0]  in2,
+  input  [(WIDTH-1):0]  in3,
+  input  [(WIDTH-1):0]  in4,
+  input  [(WIDTH-1):0]  in5,
+  input  [(WIDTH-1):0]  in6,
+  input  [(WIDTH-1):0]  in7,
+  input  [(WIDTH-1):0]  in8,
+  input  [(WIDTH-1):0]  in9,
+  input  [(WIDTH-1):0]  in10,
+  input  [(WIDTH-1):0]  in11,
+  input  [(WIDTH-1):0]  in12,
+  input  [(WIDTH-1):0]  in13,
+  input  [(WIDTH-1):0]  in14,
+  input  [(WIDTH-1):0]  in15,
+  output  [(WIDTH-1):0]  data
 )
 ;
   wire [3:0]  sel;
-  wire [WIDTH-1:0]  in0;
-  wire [WIDTH-1:0]  in1;
-  wire [WIDTH-1:0]  in2;
-  wire [WIDTH-1:0]  in3;
-  wire [WIDTH-1:0]  in4;
-  wire [WIDTH-1:0]  in5;
-  wire [WIDTH-1:0]  in6;
-  wire [WIDTH-1:0]  in7;
-  wire [WIDTH-1:0]  in8;
-  wire [WIDTH-1:0]  in9;
-  wire [WIDTH-1:0]  in10;
-  wire [WIDTH-1:0]  in11;
-  wire [WIDTH-1:0]  in12;
-  wire [WIDTH-1:0]  in13;
-  wire [WIDTH-1:0]  in14;
-  wire [WIDTH-1:0]  in15;
+  wire [(WIDTH-1):0]  in0;
+  wire [(WIDTH-1):0]  in1;
+  wire [(WIDTH-1):0]  in2;
+  wire [(WIDTH-1):0]  in3;
+  wire [(WIDTH-1):0]  in4;
+  wire [(WIDTH-1):0]  in5;
+  wire [(WIDTH-1):0]  in6;
+  wire [(WIDTH-1):0]  in7;
+  wire [(WIDTH-1):0]  in8;
+  wire [(WIDTH-1):0]  in9;
+  wire [(WIDTH-1):0]  in10;
+  wire [(WIDTH-1):0]  in11;
+  wire [(WIDTH-1):0]  in12;
+  wire [(WIDTH-1):0]  in13;
+  wire [(WIDTH-1):0]  in14;
+  wire [(WIDTH-1):0]  in15;
 endmodule
 
 
@@ -144,16 +144,16 @@ module hdl4se_split2
   parameter OUTPUTFROM1 = 8
 )
 (
-  input  [INPUTWIDTH-1:0]  wirein,
-  output  [OUTPUTWIDTH0-1:0]  wireout0,
-  output  [OUTPUTWIDTH1-1:0]  wireout1
+  input  [(INPUTWIDTH-1):0]  wirein,
+  output  [(OUTPUTWIDTH0-1):0]  wireout0,
+  output  [(OUTPUTWIDTH1-1):0]  wireout1
 )
 ;
-  wire [INPUTWIDTH-1:0]  wirein;
-  wire [OUTPUTWIDTH0-1:0]  wireout0;
-  wire [OUTPUTWIDTH1-1:0]  wireout1;
-  assign wireout0 = wirein [OUTPUTWIDTH0+OUTPUTFROM0-1:OUTPUTFROM0] ;
-  assign wireout1 = wirein [OUTPUTWIDTH1+OUTPUTFROM1-1:OUTPUTFROM1] ;
+  wire [(INPUTWIDTH-1):0]  wirein;
+  wire [(OUTPUTWIDTH0-1):0]  wireout0;
+  wire [(OUTPUTWIDTH1-1):0]  wireout1;
+  assign wireout0 = wirein [(OUTPUTWIDTH0+(OUTPUTFROM0-1)):OUTPUTFROM0] ;
+  assign wireout1 = wirein [(OUTPUTWIDTH1+(OUTPUTFROM1-1)):OUTPUTFROM1] ;
 endmodule
 
 
@@ -169,13 +169,13 @@ module hdl4se_split1
   parameter OUTPUTFROM0 = 0
 )
 (
-  input  [INPUTWIDTH-1:0]  wirein,
-  output  [OUTPUTWIDTH0-1:0]  wireout0
+  input  [(INPUTWIDTH-1):0]  wirein,
+  output  [(OUTPUTWIDTH0-1):0]  wireout0
 )
 ;
-  wire [INPUTWIDTH-1:0]  wirein;
-  wire [OUTPUTWIDTH0-1:0]  wireout0;
-  assign wireout0 = wirein [OUTPUTWIDTH0+OUTPUTFROM0-1:OUTPUTFROM0] ;
+  wire [(INPUTWIDTH-1):0]  wirein;
+  wire [(OUTPUTWIDTH0-1):0]  wireout0;
+  assign wireout0 = wirein [(OUTPUTWIDTH0+(OUTPUTFROM0-1)):OUTPUTFROM0] ;
 endmodule
 
 
@@ -197,22 +197,22 @@ module hdl4se_split4
   parameter OUTPUTFROM3 = 24
 )
 (
-  input  [INPUTWIDTH-1:0]  wirein,
-  output  [OUTPUTWIDTH0-1:0]  wireout0,
-  output  [OUTPUTWIDTH1-1:0]  wireout1,
-  output  [OUTPUTWIDTH2-1:0]  wireout2,
-  output  [OUTPUTWIDTH3-1:0]  wireout3
+  input  [(INPUTWIDTH-1):0]  wirein,
+  output  [(OUTPUTWIDTH0-1):0]  wireout0,
+  output  [(OUTPUTWIDTH1-1):0]  wireout1,
+  output  [(OUTPUTWIDTH2-1):0]  wireout2,
+  output  [(OUTPUTWIDTH3-1):0]  wireout3
 )
 ;
-  wire [INPUTWIDTH-1:0]  wirein;
-  wire [OUTPUTWIDTH0-1:0]  wireout0;
-  wire [OUTPUTWIDTH1-1:0]  wireout1;
-  wire [OUTPUTWIDTH2-1:0]  wireout2;
-  wire [OUTPUTWIDTH3-1:0]  wireout3;
-  assign wireout0 = wirein [OUTPUTWIDTH0+OUTPUTFROM0-1:OUTPUTFROM0] ;
-  assign wireout1 = wirein [OUTPUTWIDTH1+OUTPUTFROM1-1:OUTPUTFROM1] ;
-  assign wireout2 = wirein [OUTPUTWIDTH2+OUTPUTFROM2-1:OUTPUTFROM2] ;
-  assign wireout3 = wirein [OUTPUTWIDTH3+OUTPUTFROM3-1:OUTPUTFROM3] ;
+  wire [(INPUTWIDTH-1):0]  wirein;
+  wire [(OUTPUTWIDTH0-1):0]  wireout0;
+  wire [(OUTPUTWIDTH1-1):0]  wireout1;
+  wire [(OUTPUTWIDTH2-1):0]  wireout2;
+  wire [(OUTPUTWIDTH3-1):0]  wireout3;
+  assign wireout0 = wirein [(OUTPUTWIDTH0+(OUTPUTFROM0-1)):OUTPUTFROM0] ;
+  assign wireout1 = wirein [(OUTPUTWIDTH1+(OUTPUTFROM1-1)):OUTPUTFROM1] ;
+  assign wireout2 = wirein [(OUTPUTWIDTH2+(OUTPUTFROM2-1)):OUTPUTFROM2] ;
+  assign wireout3 = wirein [(OUTPUTWIDTH3+(OUTPUTFROM3-1)):OUTPUTFROM3] ;
 endmodule
 
 
@@ -227,14 +227,14 @@ module hdl4se_bind2
   parameter INPUTWIDTH1 = 8
 )
 (
-  input  [INPUTWIDTH0-1:0]  wirein0,
-  input  [INPUTWIDTH1-1:0]  wirein1,
-  output  [INPUTWIDTH0+INPUTWIDTH1-1:0]  wireout
+  input  [(INPUTWIDTH0-1):0]  wirein0,
+  input  [(INPUTWIDTH1-1):0]  wirein1,
+  output  [(INPUTWIDTH0+(INPUTWIDTH1-1)):0]  wireout
 )
 ;
-  wire [INPUTWIDTH0-1:0]  wirein0;
-  wire [INPUTWIDTH1-1:0]  wirein1;
-  wire [INPUTWIDTH0+INPUTWIDTH1-1:0]  wireout;
+  wire [(INPUTWIDTH0-1):0]  wirein0;
+  wire [(INPUTWIDTH1-1):0]  wirein1;
+  wire [(INPUTWIDTH0+(INPUTWIDTH1-1)):0]  wireout;
 endmodule
 
 
@@ -250,16 +250,16 @@ module hdl4se_bind3
   parameter INPUTWIDTH2 = 8
 )
 (
-  input  [INPUTWIDTH0-1:0]  wirein0,
-  input  [INPUTWIDTH1-1:0]  wirein1,
-  input  [INPUTWIDTH2-1:0]  wirein2,
-  output  [INPUTWIDTH0+INPUTWIDTH1+INPUTWIDTH2-1:0]  wireout
+  input  [(INPUTWIDTH0-1):0]  wirein0,
+  input  [(INPUTWIDTH1-1):0]  wirein1,
+  input  [(INPUTWIDTH2-1):0]  wirein2,
+  output  [(INPUTWIDTH0+(INPUTWIDTH1+(INPUTWIDTH2-1))):0]  wireout
 )
 ;
-  wire [INPUTWIDTH0-1:0]  wirein0;
-  wire [INPUTWIDTH1-1:0]  wirein1;
-  wire [INPUTWIDTH2-1:0]  wirein2;
-  wire [INPUTWIDTH0+INPUTWIDTH1+INPUTWIDTH2-1:0]  wireout;
+  wire [(INPUTWIDTH0-1):0]  wirein0;
+  wire [(INPUTWIDTH1-1):0]  wirein1;
+  wire [(INPUTWIDTH2-1):0]  wirein2;
+  wire [(INPUTWIDTH0+(INPUTWIDTH1+(INPUTWIDTH2-1))):0]  wireout;
 endmodule
 
 
@@ -276,18 +276,18 @@ module hdl4se_bind4
   parameter WIDTH3 = 8
 )
 (
-  input  [WIDTH0-1:0]  wirein0,
-  input  [WIDTH1-1:0]  wirein1,
-  input  [WIDTH2-1:0]  wirein2,
-  input  [WIDTH3-1:0]  wirein3,
-  output  [WIDTH0+WIDTH1+WIDTH2+WIDTH3-1:0]  wireout
+  input  [(WIDTH0-1):0]  wirein0,
+  input  [(WIDTH1-1):0]  wirein1,
+  input  [(WIDTH2-1):0]  wirein2,
+  input  [(WIDTH3-1):0]  wirein3,
+  output  [(WIDTH0+(WIDTH1+(WIDTH2+(WIDTH3-1)))):0]  wireout
 )
 ;
-  wire [WIDTH0-1:0]  wirein0;
-  wire [WIDTH1-1:0]  wirein1;
-  wire [WIDTH2-1:0]  wirein2;
-  wire [WIDTH3-1:0]  wirein3;
-  wire [WIDTH0+WIDTH1+WIDTH2+WIDTH3-1:0]  wireout;
+  wire [(WIDTH0-1):0]  wirein0;
+  wire [(WIDTH1-1):0]  wirein1;
+  wire [(WIDTH2-1):0]  wirein2;
+  wire [(WIDTH3-1):0]  wirein3;
+  wire [(WIDTH0+(WIDTH1+(WIDTH2+(WIDTH3-1)))):0]  wireout;
 endmodule
 
 
@@ -304,10 +304,10 @@ module hdl4se_ram1p
 (
   input  wClk,
   input  wWrite,
-  input  [ADDRWIDTH-1:0]  bWriteAddr,
-  input  [WIDTH-1:0]  bWriteData,
-  input  [ADDRWIDTH-1:0]  bReadAddr,
-  output  [WIDTH-1:0]  bReadData
+  input  [(ADDRWIDTH-1):0]  bWriteAddr,
+  input  [(WIDTH-1):0]  bWriteData,
+  input  [(ADDRWIDTH-1):0]  bReadAddr,
+  output  [(WIDTH-1):0]  bReadData
 )
 ;
 endmodule
@@ -326,15 +326,15 @@ module hdl4se_ram2p
 (
   input  wClk,
   input  wWrite1,
-  input  [ADDRWIDTH-1:0]  bWriteAddr1,
-  input  [WIDTH-1:0]  bWriteData1,
-  input  [ADDRWIDTH-1:0]  bReadAddr1,
-  output  [WIDTH-1:0]  bReadData1,
+  input  [(ADDRWIDTH-1):0]  bWriteAddr1,
+  input  [(WIDTH-1):0]  bWriteData1,
+  input  [(ADDRWIDTH-1):0]  bReadAddr1,
+  output  [(WIDTH-1):0]  bReadData1,
   input  wWrite2,
-  input  [ADDRWIDTH-1:0]  bWriteAddr2,
-  input  [WIDTH-1:0]  bWriteData2,
-  input  [ADDRWIDTH-1:0]  bReadAddr2,
-  output  [WIDTH-1:0]  bReadData2
+  input  [(ADDRWIDTH-1):0]  bWriteAddr2,
+  input  [(WIDTH-1):0]  bWriteData2,
+  input  [(ADDRWIDTH-1):0]  bReadAddr2,
+  output  [(WIDTH-1):0]  bReadData2
 )
 ;
 endmodule
@@ -351,10 +351,10 @@ module hdl4se_const
   parameter VALUE = 8'b0
 )
 (
-  output  [WIDTH-1:0]  data
+  output  [(WIDTH-1):0]  data
 )
 ;
-  wire [WIDTH-1:0]  data;
+  wire [(WIDTH-1):0]  data;
   assign data = VALUE;
 endmodule
 
@@ -372,14 +372,14 @@ module hdl4se_binop
   parameter OP = 0
 )
 (
-  input  [INPUTWIDTH0-1:0]  wirein0,
-  input  [INPUTWIDTH1-1:0]  wirein1,
-  output  [OUTPUTWIDTH-1:0]  wireout
+  input  [(INPUTWIDTH0-1):0]  wirein0,
+  input  [(INPUTWIDTH1-1):0]  wirein1,
+  output  [(OUTPUTWIDTH-1):0]  wireout
 )
 ;
-  wire [INPUTWIDTH0-1:0]  wirein0;
-  wire [INPUTWIDTH1-1:0]  wirein1;
-  wire [OUTPUTWIDTH-1:0]  wireout;
+  wire [(INPUTWIDTH0-1):0]  wirein0;
+  wire [(INPUTWIDTH1-1):0]  wirein1;
+  wire [(OUTPUTWIDTH-1):0]  wireout;
 endmodule
 
 
@@ -395,12 +395,12 @@ module hdl4se_unop
   parameter OP = 0
 )
 (
-  input  [INPUTWIDTH-1:0]  wirein,
-  output  [OUTPUTWIDTH-1:0]  wireout
+  input  [(INPUTWIDTH-1):0]  wirein,
+  output  [(OUTPUTWIDTH-1):0]  wireout
 )
 ;
-  wire [INPUTWIDTH-1:0]  wirein;
-  wire [OUTPUTWIDTH-1:0]  wireout;
+  wire [(INPUTWIDTH-1):0]  wirein;
+  wire [(OUTPUTWIDTH-1):0]  wireout;
 endmodule
 
 
@@ -415,11 +415,11 @@ module hdl4se_reg
 )
 (
   input  wClk,
-  input  [WIDTH-1:0]  wirein,
-  output  [WIDTH-1:0]  wireout
+  input  [(WIDTH-1):0]  wirein,
+  output  [(WIDTH-1):0]  wireout
 )
 ;
-  wire [WIDTH-1:0]  wirein;
+  wire [(WIDTH-1):0]  wirein;
 endmodule
 
 
@@ -432,11 +432,6 @@ module teris_ctrl
 (
   input  wClk,
   input  nwReset,
-  output  wWrite,
-  output  [5:0]  bWriteAddr,
-  output  [63:0]  bWriteData,
-  output  [5:0]  bReadAddr,
-  input  [63:0]  bReadData,
   input  [31:0]  bKeyData,
   input  wStateComplete,
   output  [3:0]  bState,
@@ -449,6 +444,36 @@ module teris_ctrl
   input  [31:0]  wResult
 )
 ;
+  wire [3:0]  wirein_state;
+  wire [3:0]  wireout_state;
+  wire [31:0]  wirein_score;
+  wire [31:0]  wireout_score;
+  wire [31:0]  wirein_level;
+  wire [31:0]  wireout_level;
+  wire [31:0]  wirein_speed;
+  wire [31:0]  wireout_speed;
+  wire [15:0]  wirein_curpos;
+  wire [15:0]  wireout_curpos;
+  wire [63:0]  wirein_curblock;
+  wire [63:0]  wireout_curblock;
+  wire [63:0]  wirein_nextblock;
+  wire [63:0]  wireout_nextblock;
+  assign bState = wireout_state;
+  assign bScore = wireout_score;
+  assign bLevel = wireout_level;
+  assign bSpeed = wireout_speed;
+  assign bCurBlockPos = wireout_curpos;
+  assign bCurBlock = wireout_curblock;
+  assign bNextBlock = wireout_nextblock;
+  hdl4se_reg #( 4 ) terris_ctrlstate( wClk, wirein_state, wireout_state );
+  hdl4se_reg #( 32 ) terris_score( wClk, wirein_score, wireout_score );
+  hdl4se_reg #( 32 ) terris_level( wClk, wirein_level, wireout_level );
+  hdl4se_reg #( 32 ) terris_speed( wClk, wirein_speed, wireout_speed );
+  hdl4se_reg #( 15 ) terris_curpos( wClk, wirein_curpos, wireout_curpos );
+  hdl4se_reg #( 64 ) terris_curblock( wClk, wirein_curblock, wireout_curblock );
+  hdl4se_reg #( 64 ) terris_nextblock( wClk, wirein_nextblock, wireout_nextblock );
+  hdl4se_mux8 #( 32 ) mux_nextstate( wireout_state, 1, 2, 32'h0, wCBWCanSetTo, 32'h0
+  , bCKLResult, 32'h0, 32'h0, bResult );
 endmodule
 
 
@@ -522,64 +547,64 @@ module flushtodisp
   wire [31:0]  rightline9;
   wire [31:0]  rightline10;
   wire [5:0]  blockx_3;
-  assign wirein_readaddr = bCtrlState==1?wireout_readaddr+1:6'b0;
+  assign wirein_readaddr = (((bCtrlState==1))?((wireout_readaddr+1)):(6'b0));
   assign bFlushReadAddr = wireout_readaddr [6:1] ;
-  assign wCtrlStateComplete = wireout_readaddr==6'd60;
-  assign bWriteAddr = 32'hf0000010+wireout_readaddr_delay_1*4;
-  assign wWrite = bCtrlState==1?1:0;
-  assign bWriteData = curblockline!=16'b0?right?rightline:leftline:selecteddata;
+  assign wCtrlStateComplete = (wireout_readaddr==8'd60);
+  assign bWriteAddr = (32'hf0000010+(wireout_readaddr_delay_1*4));
+  assign wWrite = (((bCtrlState==1))?(1):(0));
+  assign bWriteData = (((curblockline!=16'b0))?(((right)?(rightline):(leftline))):(selecteddata));
   assign bNextBlockLo = bNextBlock [31:0] ;
   assign bNextBlockHi = bNextBlock [63:32] ;
   assign bCurBlockLo = bCurBlock [31:0] ;
   assign bCurBlockHi = bCurBlock [63:32] ;
   assign bCurBlockX = bCurBlockPos [4:0] ;
   assign bCurBlockY = bCurBlockPos [12:8] ;
-  assign bWriteDataSel = wireout_readaddr_delay_1<6'd52?3'd7:wireout_readaddr_delay_1-6'd52;
+  assign bWriteDataSel = (((wireout_readaddr_delay_1<8'd52))?(3'd7):((wireout_readaddr_delay_1-8'd52)));
   assign line = wireout_readaddr_delay_1 [5:1] ;
   assign right = wireout_readaddr_delay_1 [0] ;
-  assign line3 = line+2==bCurBlockY?16'hffff:16'b0;
-  assign line2 = line+1==bCurBlockY?16'hffff:16'b0;
-  assign line1 = line==bCurBlockY?16'hffff:16'b0;
-  assign line0 = line==bCurBlockY+1?16'hffff:16'b0;
-  assign curblockline = line0&bCurBlock [15:0] |line1&bCurBlock [31:16] |line2&bCurBlock [47:32] |line3&bCurBlock [63:48] ;
-  assign leftline = bCurBlockX [5:4] ?selecteddata:leftline_0_15|selecteddata;
-  assign rightline = bCurBlockX [5:0] >=3?rightline_3_18|selecteddata:selecteddata;
-  assign blockx_3 = bCurBlockX [5:0] -6'd3;
+  assign line3 = ((((line+2)==bCurBlockY))?(16'hffff):(16'b0));
+  assign line2 = ((((line+1)==bCurBlockY))?(16'hffff):(16'b0));
+  assign line1 = (((line==bCurBlockY))?(16'hffff):(16'b0));
+  assign line0 = (((line==(bCurBlockY+1)))?(16'hffff):(16'b0));
+  assign curblockline = ((line0&bCurBlock [15:0] )|((line1&bCurBlock [31:16] )|((line2&bCurBlock [47:32] )|(line3&bCurBlock [63:48] ))));
+  assign leftline = ((bCurBlockX [5:4] )?(selecteddata):((leftline_0_15|selecteddata)));
+  assign rightline = (((bCurBlockX [5:0] >=3))?((rightline_3_18|selecteddata)):(selecteddata));
+  assign blockx_3 = (bCurBlockX [5:0] -6'd3);
   hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
   hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
   hdl4se_bind2 #( 16, 16 ) curlinebind( curblockline, selecteddata [31:16] , curline );
-  hdl4se_bind2 #( 4, 28 ) leftline_1_gen( curblockline [15:12] , 32'h0, leftline_1 );
-  hdl4se_bind2 #( 8, 24 ) leftline0_gen( curblockline [15:8] , 32'h0, leftline0 );
-  hdl4se_bind2 #( 12, 20 ) leftline1_gen( curblockline [15:4] , 32'h0, leftline1 );
-  hdl4se_bind2 #( 16, 16 ) leftline2_gen( curblockline [15:0] , 32'h0, leftline2 );
-  hdl4se_bind3 #( 4, 16, 12 ) leftline3_gen( 32'h0, curblockline [15:0] , 32'h0, leftline3 );
-  hdl4se_bind3 #( 8, 16, 8 ) leftline4_gen( 32'h0, curblockline [15:0] , 32'h0, leftline4 );
-  hdl4se_bind3 #( 12, 16, 4 ) leftline5_gen( 32'h0, curblockline [15:0] , 32'h0, leftline5 );
-  hdl4se_bind2 #( 16, 16 ) leftline6_gen( 32'h0, curblockline [15:0] , leftline6 );
-  hdl4se_bind2 #( 20, 12 ) leftline7_gen( 32'h0, curblockline [11:0] , leftline7 );
-  hdl4se_bind2 #( 24, 8 ) leftline8_gen( 32'h0, curblockline [7:0] , leftline8 );
-  hdl4se_bind2 #( 28, 4 ) leftline9_gen( 32'h0, curblockline [3:0] , leftline9 );
+  hdl4se_bind2 #( 4, 28 ) leftline_1_gen( curblockline [15:12] , 0, leftline_1 );
+  hdl4se_bind2 #( 8, 24 ) leftline0_gen( curblockline [15:8] , 0, leftline0 );
+  hdl4se_bind2 #( 12, 20 ) leftline1_gen( curblockline [15:4] , 0, leftline1 );
+  hdl4se_bind2 #( 16, 16 ) leftline2_gen( curblockline [15:0] , 0, leftline2 );
+  hdl4se_bind3 #( 4, 16, 12 ) leftline3_gen( 0, curblockline [15:0] , 0, leftline3 );
+  hdl4se_bind3 #( 8, 16, 8 ) leftline4_gen( 0, curblockline [15:0] , 0, leftline4 );
+  hdl4se_bind3 #( 12, 16, 4 ) leftline5_gen( 0, curblockline [15:0] , 0, leftline5 );
+  hdl4se_bind2 #( 16, 16 ) leftline6_gen( 0, curblockline [15:0] , leftline6 );
+  hdl4se_bind2 #( 20, 12 ) leftline7_gen( 0, curblockline [11:0] , leftline7 );
+  hdl4se_bind2 #( 24, 8 ) leftline8_gen( 0, curblockline [7:0] , leftline8 );
+  hdl4se_bind2 #( 28, 4 ) leftline9_gen( 0, curblockline [3:0] , leftline9 );
   hdl4se_mux16 #( 32 ) selectleftline( bCurBlockX [3:0] , leftline_1, leftline0, leftline1, leftline2, leftline3
   , leftline4, leftline5, leftline6, leftline7, leftline8
   , leftline9, selecteddata, selecteddata, selecteddata, selecteddata
   , selecteddata, leftline_0_15 );
-  hdl4se_bind2 #( 4, 28 ) rightline0_gen( curblockline [15:12] , 32'h0, rightline0 );
-  hdl4se_bind2 #( 8, 24 ) rightline1_gen( curblockline [15:8] , 32'h0, rightline1 );
-  hdl4se_bind2 #( 12, 20 ) rightline2_gen( curblockline [15:4] , 32'h0, rightline2 );
-  hdl4se_bind2 #( 16, 16 ) rightline3_gen( curblockline [15:0] , 32'h0, rightline3 );
-  hdl4se_bind3 #( 4, 16, 12 ) rightline4_gen( 32'h0, curblockline [15:0] , 32'h0, rightline4 );
-  hdl4se_bind3 #( 8, 16, 8 ) rightline5_gen( 32'h0, curblockline [15:0] , 32'h0, rightline5 );
-  hdl4se_bind3 #( 12, 16, 4 ) rightline6_gen( 32'h0, curblockline [15:0] , 32'h0, rightline6 );
-  hdl4se_bind2 #( 16, 16 ) rightline7_gen( 32'h0, curblockline [15:0] , rightline7 );
-  hdl4se_bind2 #( 20, 12 ) rightline8_gen( 32'h0, curblockline [11:0] , rightline8 );
-  hdl4se_bind2 #( 24, 8 ) rightline9_gen( 32'h0, curblockline [7:0] , rightline9 );
-  hdl4se_bind2 #( 28, 4 ) rightline10_gen( 32'h0, curblockline [3:0] , rightline10 );
+  hdl4se_bind2 #( 4, 28 ) rightline0_gen( curblockline [15:12] , 0, rightline0 );
+  hdl4se_bind2 #( 8, 24 ) rightline1_gen( curblockline [15:8] , 0, rightline1 );
+  hdl4se_bind2 #( 12, 20 ) rightline2_gen( curblockline [15:4] , 0, rightline2 );
+  hdl4se_bind2 #( 16, 16 ) rightline3_gen( curblockline [15:0] , 0, rightline3 );
+  hdl4se_bind3 #( 4, 16, 12 ) rightline4_gen( 0, curblockline [15:0] , 0, rightline4 );
+  hdl4se_bind3 #( 8, 16, 8 ) rightline5_gen( 0, curblockline [15:0] , 0, rightline5 );
+  hdl4se_bind3 #( 12, 16, 4 ) rightline6_gen( 0, curblockline [15:0] , 0, rightline6 );
+  hdl4se_bind2 #( 16, 16 ) rightline7_gen( 0, curblockline [15:0] , rightline7 );
+  hdl4se_bind2 #( 20, 12 ) rightline8_gen( 0, curblockline [11:0] , rightline8 );
+  hdl4se_bind2 #( 24, 8 ) rightline9_gen( 0, curblockline [7:0] , rightline9 );
+  hdl4se_bind2 #( 28, 4 ) rightline10_gen( 0, curblockline [3:0] , rightline10 );
   hdl4se_mux16 #( 32 ) selectrightline( blockx_3 [3:0] , selecteddata, selecteddata, selecteddata, selecteddata, selecteddata
   , rightline0, rightline1, rightline2, rightline3, rightline4
   , rightline5, rightline6, rightline7, rightline8, rightline9
   , rightline10, rightline_3_18 );
   hdl4se_mux8 #( 32 ) writedatasel( bWriteDataSel, bNextBlockLo, bNextBlockHi, 32'h0, 32'h0, bCtrlScore
-  , bCtrlLevel, bCtrlSpeed, right?bFlushReadData [63:32] :bFlushReadData [31:0] , selecteddata );
+  , bCtrlLevel, bCtrlSpeed, ((right)?(bFlushReadData [63:32] ):(bFlushReadData [31:0] )), selecteddata );
 endmodule
 
 
@@ -609,14 +634,14 @@ module blockwrite
   wire [7:0]  blocky;
   wire [63:0]  curblockline;
   wire [63:0]  curblockline_1;
-  assign wirein_readaddr = bCtrlState==4?wireout_readaddr+1:0;
-  assign curblockline_1 = bCurBlock>>3-wireout_readaddr_delay_1*16&64'hffff;
-  assign curblockline = blockx<3?curblockline_1>>3-blockx*4:curblockline_1<<blockx-3*4;
-  assign wCtrlStateComplete = wireout_readaddr_delay_1>=4;
-  assign bBWReadAddr = wireout_readaddr+blocky-4;
-  assign wBWWrite = wireout_readaddr>0&&wireout_readaddr_delay_1>=0&&wireout_readaddr_delay_1<=3;
-  assign bBWWriteAddr = wireout_readaddr_delay_1+blocky-4;
-  assign bBWWriteData = bBWReadData|curblockline;
+  assign wirein_readaddr = (((bCtrlState==4))?((wireout_readaddr+1)):(0));
+  assign curblockline_1 = ((bCurBlock>>((3-wireout_readaddr_delay_1)*16))&64'hffff);
+  assign curblockline = (((blockx<3))?((curblockline_1>>((3-blockx)*4))):((curblockline_1<<((blockx-3)*4))));
+  assign wCtrlStateComplete = (wireout_readaddr_delay_1>=4);
+  assign bBWReadAddr = (wireout_readaddr+(blocky-4));
+  assign wBWWrite = ((wireout_readaddr>0)&&((wireout_readaddr_delay_1>=0)&&(wireout_readaddr_delay_1<=3)));
+  assign bBWWriteAddr = (wireout_readaddr_delay_1+(blocky-4));
+  assign bBWWriteData = (bBWReadData|curblockline);
   assign blockx = bCurBlockPos [7:0] ;
   assign blocky = bCurBlockPos [15:8] ;
   hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
@@ -661,27 +686,27 @@ module canblocksetto
   wire [63:0]  curblockline_3;
   wire [63:0]  curblockline_mask;
   wire [63:0]  curblockline_mask_1;
-  assign wirein_readaddr = bCtrlState==3?wireout_readaddr+1:0;
+  assign wirein_readaddr = (((bCtrlState==3))?((wireout_readaddr+1)):(0));
   assign wCanSet = wireout_cansetto;
-  assign bCBWReadAddr = wireout_readaddr+blocky-2;
-  assign wCtrlStateComplete = wireout_readaddr_delay_1>4||wireout_cansetto==0;
-  assign wirein_readaddr = bCtrlState==3?wireout_readaddr+1:0;
-  assign wirein_cansetto = bCtrlState==3?wCanSetCurrentPre:1;
-  assign wCanSetCurrentPre = wireout_readaddr>0&&wCanSetCurrent==0?0:wireout_cansetto;
-  assign wCanSetCurrent = wireout_readaddr_delay_1>3||y>=24||curblockline==0?1:wCanSetCurrent_1;
-  assign wCanSetCurrent_1 = curblockline!=0&&y<0?0:wCanSetCurrent_2;
-  assign curblockline_0 = curblockline&64'hf?64'hf:64'h0;
-  assign curblockline_1 = curblockline&64'hf0?64'hf0:64'h0;
-  assign curblockline_2 = curblockline&64'hf00?64'hf00:64'h0;
-  assign curblockline_3 = curblockline&64'hf000?64'hf000:64'h0;
-  assign curblockline_mask = curblockline_0|curblockline_1|curblockline_2|curblockline_3;
-  assign wCanSetCurrent_2 = blockx<3?curblockline_mask&64'hffffffff_ffffffff>>64-3-blockx*4!=0?0:wCanSetCurrent_3:curblockline_mask&64'hffffffff_ffffffff<<64-blockx-3*4!=0&&blockx>3?0:wCanSetCurrent_3;
-  assign curblockline_mask_1 = blockx<3?curblockline_mask>>3-blockx*4:curblockline_mask<<blockx-3*4;
-  assign wCanSetCurrent_3 = bCBWReadData&curblockline_mask_1==0;
+  assign bCBWReadAddr = (wireout_readaddr+(blocky-4));
+  assign wCtrlStateComplete = (wireout_readaddr_delay_1>(4||(wireout_cansetto==0)));
+  assign wirein_readaddr = (((bCtrlState==3))?((wireout_readaddr+1)):(0));
+  assign wirein_cansetto = (((bCtrlState==3))?(wCanSetCurrentPre):(1));
+  assign wCanSetCurrentPre = ((((wireout_readaddr>0)&&(wCanSetCurrent==0)))?(0):(wireout_cansetto));
+  assign wCanSetCurrent = ((((wireout_readaddr_delay_1>4)||((y>=(24+4))||(curblockline==0))))?(1):(wCanSetCurrent_1));
+  assign wCanSetCurrent_1 = (((curblockline!=(0&&(y<4))))?(0):(wCanSetCurrent_2));
+  assign curblockline_0 = (((curblockline&64'hf))?(64'hf):(64'h0));
+  assign curblockline_1 = (((curblockline&64'hf0))?(64'hf0):(64'h0));
+  assign curblockline_2 = (((curblockline&64'hf00))?(64'hf00):(64'h0));
+  assign curblockline_3 = (((curblockline&64'hf000))?(64'hf000):(64'h0));
+  assign curblockline_mask = (curblockline_0|(curblockline_1|(curblockline_2|curblockline_3)));
+  assign wCanSetCurrent_2 = (((blockx<3))?(((((curblockline_mask&(64'hffffffff_ffffffff>>(64-((3-blockx)*4))))!=0))?(0):(wCanSetCurrent_3))):((((((curblockline_mask&(64'hffffffff_ffffffff<<(64-((blockx-3)*4))))!=0)&&(blockx>3)))?(0):(wCanSetCurrent_3))));
+  assign curblockline_mask_1 = (((blockx<3))?((curblockline_mask>>((3-blockx)*4))):((curblockline_mask<<((blockx-3)*4))));
+  assign wCanSetCurrent_3 = ((bCBWReadData&curblockline_mask_1)==0);
   assign blockx = bSetToPos [7:0] ;
   assign blocky = bSetToPos [15:8] ;
-  assign y = wireout_readaddr_delay_1+blocky-2;
-  assign curblockline = bCurBlock>>3-wireout_readaddr_delay_1*16&16'hffff;
+  assign y = (wireout_readaddr_delay_1+blocky);
+  assign curblockline = ((bCurBlock>>((3-wireout_readaddr_delay_1)*16))&16'hffff);
   hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
   hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
   hdl4se_reg #( 1 ) cansetto( wClk, wirein_cansetto, wireout_cansetto );
@@ -723,33 +748,34 @@ module checkline
   wire block_e;
   wire block_f;
   wire blockline;
-  assign wirein_readaddr = bCtrlState==5?wireout_readaddr+1:0;
+  assign wirein_readaddr = (((bCtrlState==5))?((wireout_readaddr+1)):(0));
   assign bCKLReadAddr = wireout_readaddr;
   assign bFindLine = wireout_readaddr_delay_1;
-  assign wCtrlStateComplete = wireout_readaddr_delay_1>24||blockline;
-  assign block_0 = bCKLReadData [3:0] !=4'b0;
-  assign block_1 = bCKLReadData [7:4] !=4'b0;
-  assign block_2 = bCKLReadData [11:8] !=4'b0;
-  assign block_3 = bCKLReadData [15:12] !=4'b0;
-  assign block_4 = bCKLReadData [19:16] !=4'b0;
-  assign block_5 = bCKLReadData [23:20] !=4'b0;
-  assign block_6 = bCKLReadData [27:24] !=4'b0;
-  assign block_7 = bCKLReadData [31:28] !=4'b0;
-  assign block_8 = bCKLReadData [35:32] !=4'b0;
-  assign block_9 = bCKLReadData [39:36] !=4'b0;
-  assign block_a = bCKLReadData [43:40] !=4'b0;
-  assign block_b = bCKLReadData [47:44] !=4'b0;
-  assign block_c = bCKLReadData [51:48] !=4'b0;
-  assign block_d = bCKLReadData [55:52] !=4'b0;
-  assign block_e = bCKLReadData [59:56] !=4'b0;
-  assign block_f = bCKLReadData [63:60] !=4'b0;
-  assign blockline = block_0&block_1&block_2&block_3&block_4&block_5&block_6&block_7&block_8&block_9&block_a&block_b&block_c&block_d&block_e&block_f;
+  assign wCtrlStateComplete = ((wireout_readaddr_delay_1>24)||(blockline&&(wireout_readaddr>0)));
+  assign block_0 = (bCKLReadData [3:0] !=4'b0);
+  assign block_1 = (bCKLReadData [7:4] !=4'b0);
+  assign block_2 = (bCKLReadData [11:8] !=4'b0);
+  assign block_3 = (bCKLReadData [15:12] !=4'b0);
+  assign block_4 = (bCKLReadData [19:16] !=4'b0);
+  assign block_5 = (bCKLReadData [23:20] !=4'b0);
+  assign block_6 = (bCKLReadData [27:24] !=4'b0);
+  assign block_7 = (bCKLReadData [31:28] !=4'b0);
+  assign block_8 = (bCKLReadData [35:32] !=4'b0);
+  assign block_9 = (bCKLReadData [39:36] !=4'b0);
+  assign block_a = (bCKLReadData [43:40] !=4'b0);
+  assign block_b = (bCKLReadData [47:44] !=4'b0);
+  assign block_c = (bCKLReadData [51:48] !=4'b0);
+  assign block_d = (bCKLReadData [55:52] !=4'b0);
+  assign block_e = (bCKLReadData [59:56] !=4'b0);
+  assign block_f = (bCKLReadData [63:60] !=4'b0);
+  assign blockline = (block_0&(block_1&(block_2&(block_3&(block_4&(block_5&(block_6&(block_7&(block_8&(block_9&(block_a&(block_b&(block_c&(block_d&(block_e&block_f)))))))))))))));
   hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
   hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
 endmodule
 
 
 (* 
+  HDL4SE = "LCOM",
   CLSID = "d6ef2a03-4c58-4b50-a966-44e156694304",
   softmodule = "hdl4se"
 *)
@@ -765,10 +791,10 @@ module panelinit
 ;
   wire [7:0]  wirein_writeaddr;
   wire [7:0]  wireout_writeaddr;
-  assign bInitWriteData = 32'h0;
-  assign wirein_writeaddr = bCtrlState==0?wireout_writeaddr+1:0;
-  assign wInitWrite = wireout_writeaddr<=24;
-  assign wCtrlStateComplete = wireout_writeaddr>24;
+  assign bInitWriteData = 64'h000000000;
+  assign wirein_writeaddr = (((bCtrlState==0))?((wireout_writeaddr+1)):(0));
+  assign wInitWrite = (wireout_writeaddr<=24);
+  assign wCtrlStateComplete = (wireout_writeaddr>24);
   assign bInitWriteAddr = wireout_writeaddr;
   hdl4se_reg #( 6 ) ramwriteaddr( wClk, wirein_writeaddr, wireout_writeaddr );
 endmodule
@@ -795,16 +821,20 @@ module copylines
   wire [7:0]  wirein_readaddr;
   wire [7:0]  wireout_readaddr;
   wire [7:0]  wireout_readaddr_delay_1;
+  wire [15:0]  wirein_fromline;
+  wire [15:0]  wireout_fromline;
   wire [7:0]  y;
-  assign wirein_readaddr = bCtrlState==6?wireout_readaddr+1:0;
-  assign bWriteAddr = y-1;
+  assign wirein_readaddr = (((bCtrlState==6))?((wireout_readaddr+1)):(0));
+  assign wirein_fromline = (((bCtrlState==6))?(bFromLine):(0));
+  assign bWriteAddr = (y-1);
   assign bWriteData = bReadData;
-  assign wWrite = wireout_readaddr_delay_1<24+1&&y>=1&&y<24+1;
-  assign wCtrlStateComplete = y>=24;
-  assign bReadAddr = bFromLine+wireout_readaddr;
-  assign y = bFromLine+wireout_readaddr_delay_1;
-  hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
-  hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
+  assign wWrite = ((y>=1)&&(y<=24));
+  assign wCtrlStateComplete = (y>24);
+  assign bReadAddr = (wireout_fromline+wireout_readaddr);
+  assign y = (wireout_fromline+wireout_readaddr_delay_1);
+  hdl4se_reg #( 6 ) reg_readaddr( wClk, wirein_readaddr, wireout_readaddr );
+  hdl4se_reg #( 6 ) reg_readaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
+  hdl4se_reg #( 6 ) reg_fromline( wClk, wirein_fromline, wireout_fromline );
 endmodule
 
 
@@ -826,10 +856,6 @@ module main
   wire [63:0]  bram_WriteData;
   wire [5:0]  bram_ReadAddr;
   wire [63:0]  bram_ReadData;
-  wire wCtrlWrite;
-  wire [5:0]  bCtrlWriteAddr;
-  wire [63:0]  bCtrlWriteData;
-  wire [5:0]  bCtrlReadAddr;
   wire [31:0]  bCtrlKeyData;
   wire wCtrlStateComplete;
   wire [3:0]  bCtrlState;
@@ -862,13 +888,12 @@ module main
   wire [63:0]  bCLWriteData;
   wire wCLCtrlStateComplete;
   wire wCLWrite;
-  assign wRead = 32'h1;
+  assign wRead = 1;
   assign bReadAddr = 32'hf0000000;
   assign bCtrlKeyData = bReadData;
   hdl4se_ram1p #( 64, 5 ) ram_0( wClk, wram_Write, bram_WriteAddr, bram_WriteData, bram_ReadAddr, bram_ReadData
    );
-  teris_ctrl ctrl( wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData, bCtrlReadAddr
-  , bram_ReadData, bCtrlKeyData, wCtrlStateComplete, bCtrlState, bCtrlScore
+  teris_ctrl ctrl( wClk, nwReset, bCtrlKeyData, wCtrlStateComplete, bCtrlState, bCtrlScore
   , bCtrlSpeed, bCtrlLevel, bNextBlock, bCurBlock, bCurBlockPos
   , bResult );
   flushtodisp flusher( wClk, bCtrlState, wFlushCtrlStateComplete, bFlushReadAddr, bram_ReadData, wWrite
@@ -886,14 +911,14 @@ module main
   , bCLWriteAddr, bCLWriteData, bCurBlockPos );
   hdl4se_mux8 #( 32 ) mux_Result( bCtrlState, 32'h0, 32'h0, 32'h0, wCBWCanSetTo, 32'h0
   , bCKLResult, 32'h0, 32'h0, bResult );
-  hdl4se_mux8 #( 1 ) mux_Complete( bCtrlState, wInitCtrlStateComplete, wFlushCtrlStateComplete, 32'h0, wCBWCtrlStateComplete, wBWCtrlStateComplete
-  , wCKLCtrlStateComplete, wCLCtrlStateComplete, 32'h0, wCtrlStateComplete );
-  hdl4se_mux8 #( 1 ) mux_ramWrite( bCtrlState, wInitWrite, 32'h0, wCtrlWrite, 32'h0, wBWWrite
-  , 32'h0, wCLWrite, 32'h0, wram_Write );
-  hdl4se_mux8 #( 6 ) mux_ramWriteAddr( bCtrlState, bInitWriteAddr, 32'h0, bCtrlWriteAddr, 32'h0, bBWWriteAddr
-  , 32'h0, bCLWriteAddr, 32'h0, bram_WriteAddr );
-  hdl4se_mux8 #( 64 ) mux_ramWriteData( bCtrlState, bInitWriteData, 32'h0, bCtrlWriteData, 32'h0, bBWWriteData
-  , 32'h0, bCLWriteData, 32'h0, bram_WriteData );
-  hdl4se_mux8 #( 6 ) mux_ramReadAddr( bCtrlState, 32'h0, bFlushReadAddr, bCtrlReadAddr, bCBWReadAddr, bBWReadAddr
-  , bCKLReadAddr, bCLReadAddr, 32'h0, bram_ReadAddr );
+  hdl4se_mux8 #( 1 ) mux_Complete( bCtrlState, wInitCtrlStateComplete, wFlushCtrlStateComplete, 0, wCBWCtrlStateComplete, wBWCtrlStateComplete
+  , wCKLCtrlStateComplete, wCLCtrlStateComplete, 0, wCtrlStateComplete );
+  hdl4se_mux8 #( 1 ) mux_ramWrite( bCtrlState, wInitWrite, 0, 0, 0, wBWWrite
+  , 0, wCLWrite, 0, wram_Write );
+  hdl4se_mux8 #( 6 ) mux_ramWriteAddr( bCtrlState, bInitWriteAddr, 0, 0, 0, bBWWriteAddr
+  , 0, bCLWriteAddr, 0, bram_WriteAddr );
+  hdl4se_mux8 #( 64 ) mux_ramWriteData( bCtrlState, bInitWriteData, 64'h000000000, 64'h000000000, 64'h000000000, bBWWriteData
+  , 64'h000000000, bCLWriteData, 64'h000000000, bram_WriteData );
+  hdl4se_mux8 #( 6 ) mux_ramReadAddr( bCtrlState, 0, bFlushReadAddr, 0, bCBWReadAddr, bBWReadAddr
+  , bCKLReadAddr, bCLReadAddr, 0, bram_ReadAddr );
 endmodule
diff --git a/parser/verilog_expr.c b/parser/verilog_expr.c
index 157f76e..f9263b2 100644
--- a/parser/verilog_expr.c
+++ b/parser/verilog_expr.c
@@ -376,23 +376,34 @@ static int expr_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 			fprintf(pFile, conststringFromVar(pobj->data.name));
 			break;
 		case EXPRTYPE_BINOP:
+			fprintf(pFile, "(");
 			objectCall2(pobj->data.expr0, dump, pFile, opt);
 			output_operator(pFile, opt, pobj->data.op);
 			output_attributes(pFile, opt, pobj);
 			objectCall2(pobj->data.expr1, dump, pFile, opt);
+			fprintf(pFile, ")");
 			break;
 		case EXPRTYPE_UNOP:
+			fprintf(pFile, "(");
 			output_operator(pFile, opt, pobj->data.op);
 			output_attributes(pFile, opt, pobj);
+			fprintf(pFile, "(");
 			objectCall2(pobj->data.expr, dump, pFile, opt);
+			fprintf(pFile, "))");
 			break;
 		case EXPRTYPE_IFOP:
+			fprintf(pFile, "((");
 			objectCall2(pobj->data.expr0, dump, pFile, opt);
+			fprintf(pFile, ")");
 			fprintf(pFile, "?");
 			output_attributes(pFile, opt, pobj);
+			fprintf(pFile, "(");
 			objectCall2(pobj->data.expr1, dump, pFile, opt);
+			fprintf(pFile, ")");
 			fprintf(pFile, ":");
+			fprintf(pFile, "(");
 			objectCall2(pobj->data.expr2, dump, pFile, opt);
+			fprintf(pFile, "))");
 			break;
 		case EXPRTYPE_HIERARCHICAL_IDENT:
 			if (dlistItemCount(pobj->data.hierarchical_identifier) > 0) {
@@ -1209,7 +1220,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
 		expr_verilognode_gencode(pobj->data.expr0, pFile, module, &expr_results[0]);
 		expr_verilognode_gencode(pobj->data.expr1, pFile, module, &expr_results[2]); /*注意?:的结果和mux的顺序不同，所以结果位置不同*/
 		expr_verilognode_gencode(pobj->data.expr2, pFile, module, &expr_results[1]);
-		if (expr_result[1].width == 0 || expr_result[2].width == 0) {
+		if (expr_results[1].width == 0 || expr_results[2].width == 0) {
 			width = 0;
 		}
 		else {
-- 
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