From 93a2121e51b65608f54858c958d913d402d52f69 Mon Sep 17 00:00:00 2001 From: Ramdas M Date: Sat, 4 Feb 2017 16:02:02 +0530 Subject: [PATCH] Update with SystemVerilog FREE courses (#2248) * Update with SystemVerilog FREE courses SystemVerilog is IEEE1800 standard and most widely used Hardware Description language * Update with SystemVerilog FREE course Update with SystemVerilog (IEEE1800 standard and commonly used Hardware Description Language) --- free-courses-en.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/free-courses-en.md b/free-courses-en.md index 793603a0..3a362158 100644 --- a/free-courses-en.md +++ b/free-courses-en.md @@ -34,6 +34,7 @@ * [Scala](#scala) * [Software Engineering](#software-engineering) * [Swift](#swift) +* [SystemVerilog](#systemverilog) * [Theory](#theory) * [Web Development](#web-development) @@ -284,6 +285,12 @@ * [Swiftris - Build an iOS Tetris app from scratch](https://www.bloc.io/swiftris-build-your-first-ios-game-with-swift) +### SystemVerilog + +* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog) +* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm) + + ### Theory * [Automata Theory](https://lagunita.stanford.edu/courses/course-v1:ComputerScience+Automata+Fall2016/about) -- GitLab