diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/lpc43xx/Libraries/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000000000000000000000000000000000..7a59b5923e9edcfc684691f70cb06360d20ddfff
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/arm_math.h b/bsp/lpc43xx/Libraries/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000000000000000000000000000000000..65304c127d6c5ad0a49cab6b0c30be220035a16a
--- /dev/null
+++ b/bsp/lpc43xx/Libraries/CMSIS/Include/arm_math.h
@@ -0,0 +1,7306 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib
folder.
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ *
+ * The library functions are declared in the public file arm_math.h
which is placed in the Include
folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h
for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ *
+ * The library has been developed and tested with MDK-ARM version 4.60.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ *
+ * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM
folder.
+ * - arm_cortexM0b_math.uvproj
+ * - arm_cortexM0l_math.uvproj
+ * - arm_cortexM3b_math.uvproj
+ * - arm_cortexM3l_math.uvproj
+ * - arm_cortexM4b_math.uvproj
+ * - arm_cortexM4l_math.uvproj
+ * - arm_cortexM4bf_math.uvproj
+ * - arm_cortexM4lf_math.uvproj
+ *
+ *
+ * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * Copyright Notice
+ *
+ * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct + * { + * uint16_t numRows; // number of rows of the matrix. + * uint16_t numCols; // number of columns of the matrix. + * float32_t *pData; // points to the data of the matrix. + * } arm_matrix_instance_f32; + *+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size
numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * + * pData[i*numCols + j] + *+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function
arm_mat_init_f32()
, arm_mat_init_q31()
+ * and arm_mat_init_q15()
for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * + *+ * wherearm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ *arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ *arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
nRows
specifies the number of rows, nColumns
+ * specifies the number of columns, and pData
points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * + * ARM_MATH_SIZE_MISMATCH + *+ * Otherwise the functions return + *
+ * ARM_MATH_SUCCESS + *+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ * ARM_MATH_MATRIX_CHECK + *+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return
ARM_MATH_SUCCESS
.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x800000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) y)) +
+ ((short) x * (short) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps
is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal
is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S
points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * + * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] + * A0 = Kp + Ki + Kd + * A1 = (-Kp ) - (2 * Kd ) + * A2 = Kd+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents
Ia, Ib and Ic
to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha
and Ibeta
.
+ * When Ialpha
is superposed with Ia
as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0
, in this condition Ialpha
and Ibeta
+ * can be calculated using only Ia
and Ib
.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia
and Ib
are the instantaneous stator phases and
+ * pIalpha
and pIbeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa
and pIb
are the instantaneous stator phases and
+ * Ialpha
and Ibeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ */
+
+
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha
and the Ibeta
currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha
and Ibeta
are the stator vector components,
+ * pId
and pIq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha
and pIbeta
are the stator vector components,
+ * Id
and Iq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * + * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)) + * where x0, x1 are nearest values of input x + * y0, y1 are nearest values to output y + *+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + *
S
points to an instance of the Linear Interpolate function data structure.
+ * x
is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * + * x1 = x0 - f(x0)/f'(x0) + *+ * where
x1
is the current estimate,
+ * x0
is the previous estimate, and
+ * f'(x0)
is the derivative of f()
evaluated at x0
.
+ * For the square root function, the algorithm reduces to:
+ * + * x0 = in/2 [initial guess] + * x1 = 1/2 * ( x0 + in / x0) [each iteration] + *+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + *
in
is negative value and returns zero output for negative values.
+ */
+
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y)
is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * + * typedef struct + * { + * uint16_t numRows; + * uint16_t numCols; + * float32_t *pData; + * } arm_bilinear_interp_instance_f32; + *+ * + * \par + * where
numRows
specifies the number of rows in the table;
+ * numCols
specifies the number of columns in the table;
+ * and pData
points to an array of size numRows*numCols
values.
+ * The data table pTable
is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols]
where x and y are integers.
+ *
+ * \par
+ * Let (x, y)
specify the desired interpolation point. Then define:
+ * + * XF = floor(x) + * YF = floor(y) + *+ * \par + * The interpolated output point is computed as: + *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF)) + * + f(XF+1, YF) * (x-XF)*(1-(y-YF)) + * + f(XF, YF+1) * (1-(x-XF))*(y-YF) + * + f(XF+1, YF+1) * (x-XF)*(y-YF) + *+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR + #define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR + #define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0.h b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..ab31de0ee87f9cb566cef040364c80c1f09bbf86 --- /dev/null +++ b/bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,682 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
Lib
folder.
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ *
+ * The library functions are declared in the public file arm_math.h
which is placed in the Include
folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h
for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ *
+ * The library has been developed and tested with MDK-ARM version 4.60.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ *
+ * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM
folder.
+ * - arm_cortexM0b_math.uvproj
+ * - arm_cortexM0l_math.uvproj
+ * - arm_cortexM3b_math.uvproj
+ * - arm_cortexM3l_math.uvproj
+ * - arm_cortexM4b_math.uvproj
+ * - arm_cortexM4l_math.uvproj
+ * - arm_cortexM4bf_math.uvproj
+ * - arm_cortexM4lf_math.uvproj
+ *
+ *
+ * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * Copyright Notice
+ *
+ * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * + * typedef struct + * { + * uint16_t numRows; // number of rows of the matrix. + * uint16_t numCols; // number of columns of the matrix. + * float32_t *pData; // points to the data of the matrix. + * } arm_matrix_instance_f32; + *+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size
numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * + * pData[i*numCols + j] + *+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function
arm_mat_init_f32()
, arm_mat_init_q31()
+ * and arm_mat_init_q15()
for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * + *+ * wherearm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ *arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ *arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
nRows
specifies the number of rows, nColumns
+ * specifies the number of columns, and pData
points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * + * ARM_MATH_SIZE_MISMATCH + *+ * Otherwise the functions return + *
+ * ARM_MATH_SUCCESS + *+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ * ARM_MATH_MATRIX_CHECK + *+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return
ARM_MATH_SUCCESS
.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x800000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) y)) +
+ ((short) x * (short) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps
is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH
or ARM_MATH_SUCCESS
based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal
is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N
is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize
is not a multiple of M
.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps
is not a multiple of the interpolation factor L
.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S
points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * + * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] + * A0 = Kp + Ki + Kd + * A1 = (-Kp ) - (2 * Kd ) + * A2 = Kd+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents
Ia, Ib and Ic
to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha
and Ibeta
.
+ * When Ialpha
is superposed with Ia
as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0
, in this condition Ialpha
and Ibeta
+ * can be calculated using only Ia
and Ib
.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia
and Ib
are the instantaneous stator phases and
+ * pIalpha
and pIbeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa
and pIb
are the instantaneous stator phases and
+ * Ialpha
and Ibeta
are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ */
+
+
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha
and the Ibeta
currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha
and Ibeta
are the stator vector components,
+ * pId
and pIq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha
and pIbeta
are the stator vector components,
+ * Id
and Iq
are rotor vector components and cosVal
and sinVal
are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * + * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)) + * where x0, x1 are nearest values of input x + * y0, y1 are nearest values to output y + *+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + *
S
points to an instance of the Linear Interpolate function data structure.
+ * x
is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x
is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * + * x1 = x0 - f(x0)/f'(x0) + *+ * where
x1
is the current estimate,
+ * x0
is the previous estimate, and
+ * f'(x0)
is the derivative of f()
evaluated at x0
.
+ * For the square root function, the algorithm reduces to:
+ * + * x0 = in/2 [initial guess] + * x1 = 1/2 * ( x0 + in / x0) [each iteration] + *+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + *
in
is negative value and returns zero output for negative values.
+ */
+
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in
is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y)
is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * + * typedef struct + * { + * uint16_t numRows; + * uint16_t numCols; + * float32_t *pData; + * } arm_bilinear_interp_instance_f32; + *+ * + * \par + * where
numRows
specifies the number of rows in the table;
+ * numCols
specifies the number of columns in the table;
+ * and pData
points to an array of size numRows*numCols
values.
+ * The data table pTable
is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols]
where x and y are integers.
+ *
+ * \par
+ * Let (x, y)
specify the desired interpolation point. Then define:
+ * + * XF = floor(x) + * YF = floor(y) + *+ * \par + * The interpolated output point is computed as: + *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF)) + * + f(XF+1, YF) * (x-XF)*(1-(y-YF)) + * + f(XF, YF+1) * (1-(x-XF))*(y-YF) + * + f(XF+1, YF+1) * (x-XF)*(y-YF) + *+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR + #define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR + #define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0.h b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..ab31de0ee87f9cb566cef040364c80c1f09bbf86 --- /dev/null +++ b/bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,682 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
- * DEBUG_UART:
- * - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0
- * CRYSTAL_MAIN_FREQ_IN:
- * - This define specifies the crystal input clock into the chip, example: 12000000
- * CRYSTAL_32K_FREQ_IN:
- * - This define specifies the RTC crystal input clock into the chip, example: 32768
- * EXTERNAL_CLKIN_FREQ_IN:
- * - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000
- * MAX_CLOCK_FREQ:
- * - When defined, this will be used to configure the CPU clock rate, example: 150000000
- * - When not defined, the system will use the maximum CPU clokc rate
- * USE_RMII:
- * - When defined, the system will be configured for RMII mode for Ethernet
- * - When not defined, the system will be configured for MII mode for Ethernet
- * BOARD_HITEX_EVA_18504350:
- * - When building for Hitex boards, BOARD_HITEX_EVA_18504350 is defined
- *
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * HITEX board defintion, can be used in examples for board specific code
- */
-#define BOARD_HITEX_EVA_18504350
-
-/* For USBLIB examples */
-#define LEDS_LED1 0x01
-#define LEDS_LED2 0x02
-#define LEDS_LED3 0x04
-#define LEDS_LED4 0x08
-#define LEDS_NO_LEDS 0x00
-#define BUTTONS_BUTTON1 0x01
-#define JOY_UP 0x01
-#define JOY_DOWN 0x02
-#define JOY_LEFT 0x04
-#define JOY_RIGHT 0x08
-#define JOY_PRESS 0x10
-#define NO_BUTTON_PRESSED 0x00
-
-#define BUTTONS_BUTTON1_GPIO_PORT_NUM 6
-#define BUTTONS_BUTTON1_GPIO_BIT_NUM 21
-
-#define I2CDEV_PCA9502_ADDR (0x9A >> 1)
-#define PCA9502_REG_IODIR 0x0A
-#define PCA9502_REG_IOSTATE 0x0B
-#define PCA9502_REG_IOINTENA 0x0C
-#define PCA9502_REG_IOCONTROL 0x0E
-#define PCA9502_REG_ADDR(x) (((x) & 0x0F) << 3)
-
-/**
- * Address of I2C device (UDA1380 CODEC) on board
- */
-#define I2CDEV_UDA1380_ADDR (0x34 >> 1)
-
-/**
- * Default location of LCD buffer is in DRAM
- */
-#define FRAMEBUFFER_ADDR 0x28000000
-
-/**
- * LCD configuration data
- */
-extern const LCD_Config_Type EA320x240;
-
-/**
- * Default LCD configuration data for examples
- */
-#define BOARD_LCD EA320x240
-
-/**
- * CODEC audio input sources
- */
-typedef enum {
- MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
- MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
-} Board_Audio_Input_Sel_Type;
-
-/**
- * @brief Initialize pin muxing for a UART
- * @param UARTx : Pointer to UART register block for UART pins to init
- * @return Nothing
- */
-void Board_UART_Init(LPC_USART_Type *UARTx);
-
-/**
- * @brief Initialize button(s) interface on board
- * @return Nothing
- */
-void Board_Buttons_Init(void);
-
-/**
- * @brief Returns button(s) state on board
- * @return Returns BUTTONS_BUTTON1 if button1 is pressed
- */
-uint32_t Buttons_GetStatus(void);
-
-/**
- * @brief Initialize joystick interface on board
- * @return Nothing
- */
-void Board_Joystick_Init(void);
-
-/**
- * @brief Returns joystick states on board
- * @return Returns a JOY_* value, ir JOY_PRESS or JOY_UP
- */
-uint8_t Joystick_GetStatus(void);
-
-/**
- * @brief Returns the MAC address assigned to this board
- * @param mcaddr : Pointer to 6-byte character array to populate with MAC address
- * @return Nothing
- */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr);
-
-/**
- * @brief Sets up board specific ADC interface
- * @return Nothing
- */
-void Board_ADC_Init(void);
-
-/**
- * @brief Sets up board specific I2C interface
- * @param I2Cx : Pointer to I2C interface to initialize
- * @return Nothing
- */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Initialize the LCD interface
- * @return Nothing
- */
-void Board_LCD_Init(void);
-
-/**
- * @brief Initialize TSC2046 touchscreen controller
- * @return Nothing
- */
-void Init_Touch_Controller(void);
-
-/**
- * @brief Get Touch coordinates
- * @param pX : Pointer to x-Coord to populate
- * @param pY : Pointer to y-Coord to populate
- * @return Nothing
- */
-bool GetTouchPos(int16_t *pX, int16_t *pY);
-
-/**
- * @brief Initialize pin muxing for SDMMC interface
- * @return Nothing
- */
-void Board_SDMMC_Init(void);
-
-/**
- * @brief Initialize pin muxing for SSP interface
- * @param SSPx : Pointer to SSP interface to initialize
- * @return Nothing
- */
-void Board_SSP_Init(LPC_SSP_Type *SSPx);
-
-/**
- * @brief Initialize I2S interface for the board and UDA1380
- * @param I2Sx : Pointer to I2S register interface used on this board
- * @param audio_in_sel : Audio input selection
- * @return Nothing
- */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
-
-/**
- * @brief FIXME
- * @param Stream : FIXME
- * @return Nothing
- */
-void Serial_CreateStream(void *Stream);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_HITEX_EVA_18504350_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h
deleted file mode 100644
index eb70ce6328fd00bdc881be37390ce4e560d9000f..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-// #define USE_RMII
-#define CHIP_LPC18XX
-
-/* Enable DEBUG for IO support via the UART */
-#define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
- via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (180000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h
deleted file mode 100644
index 543f956c8325ceabc65082627f5067d0293440f9..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-// #define USE_RMII
-#define CHIP_LPC43XX
-
-/* Enable DEBUG for IO support via the UART */
-#define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
- via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (204000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c
deleted file mode 100644
index 282fde8eb3dc35367bc3c2538de57d4e30e65e08..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-
-/** @defgroup BOARD_HITEX_EVA_18504350_SYSINIT LPC1850 and LPC4350 Hitex EVA board System Init code
- * @ingroup BOARD_HITEX_EVA_18504350
- * The System initialization code is called prior to the application and
- * initializes the board for run-time operation. Board initialization
- * for the Hitex EVA boards includes clock setup, default pin muxing, and
- * memory configuration.
- *
- * With the exception of stack space, no RW memory is used for this call.
- *
- * LPC1850 and LPC4350 Hitex EVA setup
- * Clocking:
- * All base clocks enabled by default (Save power by disabling un-needed clocks)
- * CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)
- * SPIFI FLASH clock setup for fastest speed
- * Pin muxing:
- * Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)
- * Sets up the external memory controller signals
- * Memory:
- * Sets up DRAM, static RAM, and NOR FLASH.
- * @{
- */
-
-#ifndef CORE_M0
-/* SCR pin definitions for pin muxing */
-typedef struct {
- uint8_t pingrp; /* Pin group */
- uint8_t pinnum; /* Pin number */
- uint8_t pincfg; /* Pin configuration for SCU */
- uint8_t funcnum;/* Function number */
-} PINMUX_GRP_T;
-
-/* Structure for initial base clock states */
-struct CLK_BASE_STATES {
- CGU_BASE_CLK_T clk; /* Base clock */
- CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
- bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
- bool powerdn; /* Set to true if the base clock is initially powered down */
-};
-
-/* Initial base clock states are mostly on */
-STATIC const struct CLK_BASE_STATES InitClkStates[] = {
- {CLK_BASE_SAFE, CLKIN_IRC, true, false},
- {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
- {CLK_BASE_USB0, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
-#endif
- {CLK_BASE_USB1, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
-#endif
- {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
-#if defined(USE_RMII)
- {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
-#else
- {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
-#endif
- {CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
-#endif
- {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
- {CLK_BASE_OUT, CLKINPUT_PD, true, false},
- {CLK_BASE_APLL, CLKINPUT_PD, true, false},
- {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
- {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
-};
-
-/* SPIFI high speed pin mode setup */
-STATIC const PINMUX_GRP_T spifipinmuxing[] = {
- {0x3, 3, (MD_PLN_FAST), FUNC3}, /* SPIFI CLK */
- {0x3, 4, (MD_PLN_FAST), FUNC3}, /* SPIFI D3 */
- {0x3, 5, (MD_PLN_FAST), FUNC3}, /* SPIFI D2 */
- {0x3, 6, (MD_PLN_FAST), FUNC3}, /* SPIFI D1 */
- {0x3, 7, (MD_PLN_FAST), FUNC3}, /* SPIFI D0 */
- {0x3, 8, (MD_PLN_FAST), FUNC3} /* SPIFI CS/SSEL */
-};
-
-/* Setup system clocking */
-STATIC void SystemSetupClocking(void)
-{
- int i;
-
- /* Switch main system clocking to crystal */
- Chip_Clock_EnableCrystal();
- Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
-
- /* Setup PLL for 100MHz and switch main system clocking */
- Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
- Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
-
- /* Setup PLL for maximum clock */
- Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
-
- /* Setup system base clocks and initial states. This won't enable and
- disable individual clocks, but sets up the base clock sources for
- each individual peripheral clock. */
- for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
- Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
- InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
- }
-
- /* Reset and enable 32Khz oscillator */
- LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
- LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
- /* SPIFI pin setup is done prior to setting up system clocking */
- for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
- Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
- spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
- }
-
- /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
- Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
- Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-}
-
-STATIC const PINMUX_GRP_T pinmuxing[] = {
-#if defined(USE_RMII)
- /* RMII pin group */
- {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0},
- {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6},
- {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
- {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
- {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
- {0xC, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
- {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7},
- {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
- {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2},
-#else
- /* MII pin group */
- {0x1, 19, (MD_PLN | MD_EZI), FUNC0},
- {0x0, 1, (MD_PLN), FUNC6},
- {0x1, 18, (MD_PLN), FUNC3},
- {0x1, 20, (MD_PLN), FUNC3},
- {0x1, 17, (MD_PLN | MD_EZI), FUNC3},
- {0xC, 1, (MD_PLN), FUNC3},
- {0x1, 16, (MD_PLN | MD_EZI), FUNC7},
- {0x1, 15, (MD_PLN | MD_EZI), FUNC3},
- {0x0, 0, (MD_PLN | MD_EZI), FUNC2},
- {0x9, 4, (MD_PLN), FUNC5},
- {0x9, 5, (MD_PLN), FUNC5},
- {0xC, 0, (MD_PLN | MD_EZI), FUNC3},
- {0x9, 0, (MD_PLN | MD_EZI), FUNC5},
- {0x9, 1, (MD_PLN | MD_EZI), FUNC5},
- {0x9, 6, (MD_PLN | MD_EZI), FUNC5},
- {0x9, 3, (MD_PLN | MD_EZI), FUNC5},
- {0x9, 2, (MD_PLN | MD_EZI), FUNC5},
- {0xC, 8, (MD_PLN | MD_EZI), FUNC4},
-#endif
- /* External data lines D0 .. D15 */
- {0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- /* Address lines A0 .. A23 */
- {0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
- {0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
- {0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- /* EMC control signals */
- {0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
- {0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {PINMUX_CLK, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
- {PINMUX_CLK, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
- {PINMUX_CLK, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
- {PINMUX_CLK, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
- {0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 3, MD_PLN_FAST, FUNC3},
- {0x1, 4, MD_PLN_FAST, FUNC3},
- {0x6, 6, MD_PLN_FAST, FUNC3},
- {0x1, 5, MD_PLN_FAST, FUNC3},
- /* LCD interface, 24bpp */
- {0x7, 7, MD_PUP, FUNC3},
- {0x4, 7, MD_PUP, FUNC0},
- {0x4, 5, MD_PUP, FUNC2},
- {0x4, 6, MD_PUP, FUNC2},
- {0x7, 6, MD_PUP, FUNC3},
- {0x4, 1, MD_PUP, FUNC2},
- {0x4, 4, MD_PUP, FUNC2},
- {0x4, 2, MD_PUP, FUNC2},
- {0x8, 7, MD_PUP, FUNC3},
- {0x8, 6, MD_PUP, FUNC3},
- {0x8, 5, MD_PUP, FUNC3},
- {0x8, 4, MD_PUP, FUNC3},
- {0x7, 5, MD_PUP, FUNC3},
- {0x4, 8, MD_PUP, FUNC2},
- {0x4, 10, MD_PUP, FUNC2},
- {0x4, 9, MD_PUP, FUNC2},
- {0x8, 3, MD_PUP, FUNC3},
- {0xB, 6, MD_PUP, FUNC2},
- {0xB, 5, MD_PUP, FUNC2},
- {0xB, 4, MD_PUP, FUNC2},
- {0x7, 4, MD_PUP, FUNC3},
- {0x7, 2, MD_PUP, FUNC3},
- {0x7, 1, MD_PUP, FUNC3},
- {0xB, 3, MD_PUP, FUNC2},
- {0xB, 2, MD_PUP, FUNC2},
- {0xB, 1, MD_PUP, FUNC2},
- {0xB, 0, MD_PUP, FUNC2},
- {0x7, 0, MD_PUP, FUNC3},
- {0x4, 4, MD_PUP, FUNC0},
- {0x7, 3, MD_PUP, FUNC0},
- {0x4, 1, MD_PUP, FUNC0},
- /* Board LEDs */
- {0x8, 1, MD_PDN, FUNC0},
- {0xE, 6, MD_PDN, FUNC4}, /* GPIO7.6, green */
- {0xE, 8, MD_PDN, FUNC4}, /* GPIO7.8, blue */
- {0xE, 5, MD_PDN, FUNC4}, /* GPIO7.5, red */
- /* Board ADC */
- {0xF, 9, MD_PLN, FUNC7},
- /* I2S */
- {0x3, 0, MD_PLN_FAST, FUNC2},
- {0x6, 0, MD_PLN_FAST, FUNC4},
- {0x7, 2, MD_PLN_FAST, FUNC2},
- {0x6, 2, MD_PLN_FAST, FUNC3},
- {0x7, 1, MD_PLN_FAST, FUNC2},
- {0x6, 1, MD_PLN_FAST, FUNC3},
-};
-
-/* Sets up system pin muxing */
-STATIC void SystemSetupMuxing(void)
-{
- int i;
-
- /* Setup system level pin muxing */
- for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
- Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
- pinmuxing[i].pincfg, pinmuxing[i].funcnum);
- }
-}
-
-/* EMC clock delay */
-#define CLK0_DELAY 7
-
-/* Hitex SDRAM timing and chip Config */
-STATIC const IP_EMC_DYN_CONFIG_Type IS42S16400_config = {
- EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */
- 0x01, /* Command Delayed */
- EMC_NANOSECOND(20),
- EMC_NANOSECOND(60),
- EMC_NANOSECOND(63),
- EMC_CLOCK(0x05),
- EMC_CLOCK(0x05),
- EMC_CLOCK(0x04),
- EMC_NANOSECOND(63),
- EMC_NANOSECOND(63),
- EMC_NANOSECOND(63),
- EMC_NANOSECOND(14),
- EMC_CLOCK(0x02),
- {
- {
- EMC_ADDRESS_DYCS0, /* Hitex Board uses DYCS0 for SDRAM */
- 3, /* RAS */
-
- EMC_DYN_MODE_WBMODE_PROGRAMMED |
- EMC_DYN_MODE_OPMODE_STANDARD |
- EMC_DYN_MODE_CAS_3 |
- EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
- EMC_DYN_MODE_BURST_LEN_8,
-
- EMC_DYN_CONFIG_DATA_BUS_16 |
- EMC_DYN_CONFIG_LPSDRAM |
- EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS |
- EMC_DYN_CONFIG_MD_SDRAM
- },
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0}
- }
-};
-
-/* Hitex Static RAM timing and chip Config */
-STATIC const IP_EMC_STATIC_CONFIG_Type IS62WV25616_config = {
- 2,
- EMC_STATIC_CONFIG_MEM_WIDTH_16 |
- EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
- EMC_STATIC_CONFIG_BLS_HIGH /* |
- EMC_CONFIG_BUFFER_ENABLE*/,
-
- EMC_NANOSECOND(0),
- EMC_NANOSECOND(30),
- EMC_NANOSECOND(90),
- EMC_NANOSECOND(55),
- EMC_NANOSECOND(55),
- EMC_NANOSECOND(55)
-};
-
-/* Hitex NorFlash timing and chip Config */
-STATIC const IP_EMC_STATIC_CONFIG_Type SST39VF320_config = {
- 0,
- EMC_STATIC_CONFIG_MEM_WIDTH_16 |
- EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
- EMC_STATIC_CONFIG_BLS_HIGH /* |
- EMC_CONFIG_BUFFER_ENABLE*/,
-
- EMC_NANOSECOND(0),
- EMC_NANOSECOND(35),
- EMC_NANOSECOND(70),
- EMC_NANOSECOND(70),
- EMC_NANOSECOND(40),
- EMC_CLOCK(4)
-};
-
-/* Setup external memories */
-STATIC void SystemSetupMemory(void)
-{
- /* Setup EMC Delays */
- /* Move all clock delays together */
- LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
-
- /* Setup EMC Clock Divider for divide by 2 */
- Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
- LPC_CREG->CREG6 |= (1 << 16);
- Chip_Clock_Enable(CLK_MX_EMC);
-
- /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
- Chip_EMC_Init(1, 0, 0);
- /* Init EMC Dynamic Controller */
- Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &IS42S16400_config);
- /* Init EMC Static Controller CS2 */
- Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &IS62WV25616_config);
- /* Init EMC Static Controller CS0 */
- Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &SST39VF320_config);
-
- /* Enable Buffer for External Flash */
- LPC_EMC->STATICCONFIG0 |= 1 << 19;
-}
-
-#endif
-
-/**
- * @brief Setup the system
- * SystemInit() is called prior to the application and sets up system
- * clocking, memory, and any resources needed prior to the application
- * starting.
- * @return none
- */
-void SystemInit(void)
-{
-#if defined(CORE_M3) || defined(CORE_M4)
- unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-
-#if defined(__IAR_SYSTEMS_ICC__)
- extern void *__vector_table;
-
- *pSCB_VTOR = (unsigned int) &__vector_table;
-#elif defined(__CODE_RED)
- extern void *g_pfnVectors;
-
- *pSCB_VTOR = (unsigned int) &g_pfnVectors;
-#elif defined(__ARMCC_VERSION)
- extern void *__Vectors;
-
- *pSCB_VTOR = (unsigned int) &__Vectors;
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
- fpuInit();
-#endif
-
- /* Setup system clocking and memory. This is done early to allow the
- application and tools to clear memory and use scatter loading to
- external memory. */
- SystemSetupClocking();
- SystemSetupMuxing();
- SystemSetupMemory();
-#endif
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h
deleted file mode 100644
index 921fe5d4197b258dfc96140913f7e51c3d9c0d15..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * @brief Keil MCB 1857/4357 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_H_
-#define __BOARD_H_
-
-#include "board_keil_mcb_18574357.h"
-
-#endif /* __BOARD_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c
deleted file mode 100644
index 085aff234331c6addd6d6fa8e586d082e2a12e34..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c
+++ /dev/null
@@ -1,841 +0,0 @@
-/*
- * @brief Keil MCB 1857/4357 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-#include "string.h"
-
-/* Keil board uses 83848 PHY and retarget */
-#include "lpc_phy_dp83848.c"
-#include "retarget.c"
-
-/** @ingroup BOARD_KEIL_MCB_18574357
- * @{
- */
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-/* Port and bit mapping for LEDs on GPIOs */
-static const uint8_t ledports[] = {6, 6, 6, 6, 6, 4, 4, 4};
-static const uint8_t ledbits[] = {24, 25, 26, 27, 28, 12, 13, 14};
-
-/** UDA specified variables */
-/* System Register Data Set */
-uint16_t UDA_sys_regs_dat[] = {
- UDA1380_REG_EVALCLK_DEFAULT_VALUE,
- UDA1380_REG_I2S_DEFAULT_VALUE,
- UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
- UDA1380_REG_ANAMIX_DEFAULT_VALUE,
- UDA1380_REG_HEADAMP_DEFAULT_VALUE
-};
-
-/* System Register Data Set */
-uint16_t UDA_interfil_regs_dat[] = {
- UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
- UDA1380_REG_MIXVOL_DEFAULT_VALUE,
- UDA1380_REG_MODEBBT_DEFAULT_VALUE,
- UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
- UDA1380_REG_MIXSDO_DEFAULT_VALUE
-};
-/* decimator Register Data Set */
-uint16_t UDA_decimator_regs_dat[] = {
- UDA1380_REG_DECVOL_DEFAULT_VALUE,
- UDA1380_REG_PGA_DEFAULT_VALUE,
- UDA1380_REG_ADC_DEFAULT_VALUE,
- UDA1380_REG_AGC_DEFAULT_VALUE
-};
-
-/** Private definitions for LCD */
-#define LCD_CS(x) ((x) ? (Chip_GPIO_WritePortBit(7, 16, true)) : (Chip_GPIO_WritePortBit(7, 16, false)))
-
-/** Private variables for LCD */
-uint32_t g_isPenDn;
-uint32_t g_isNewPenDn;
-const int32_t ad_left = 3813;
-const int32_t ad_top = 3805;// 237;
-const int32_t ad_right = 360;
-const int32_t ad_bottom = 237; // 3805;
-
-const LCD_Config_Type MCB4300_LCD = {
- 8, /*!< Horizontal back porch in clocks */
- 4, /*!< Horizontal front porch in clocks */
- 4, /*!< HSYNC pulse width in clocks */
- 240, /*!< Pixels per line */
- 4, /*!< Vertical back porch in clocks */
- 3, /*!< Vertical front porch in clocks */
- 4, /*!< VSYNC pulse width in clocks */
- 320, /*!< Lines per panel */
- 0, /*!< Invert output enable, 1 = invert */
- 1, /*!< Invert panel clock, 1 = invert */
- 1, /*!< Invert HSYNC, 1 = invert */
- 1, /*!< Invert VSYNC, 1 = invert */
- 1, /*!< AC bias frequency in clocks (not used) */
- 6, /*!< Maximum bits per pixel the display supports */
- LCD_TFT, /*!< LCD panel type */
- LCD_COLOR_FORMAT_RGB, /*!< BGR or RGB */
- 0 /*!< Dual panel, 1 = dual panel display */
-};
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock;
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Very simple (inaccurate) delay function */
-static void delay(uint32_t i) {
- while (i--) {}
-}
-
-/* Write data to UDA register */
-static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
-
- I2C_Config->tx_data[0] = reg;
- I2C_Config->tx_data[1] = value >> 8;
- I2C_Config->tx_data[2] = value & 0xFF;
- Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
- delay(10000);
-}
-
-/* Read data from UDA register */
-static uint16_t UDA_Reg_read(UDA1380_REG reg) {
- uint8_t rx_data[2];
- Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
- return rx_data[0] << 8 | rx_data[1];
-}
-
-/* Initializes default settings for UDA1380 */
-static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
-{
- uint16_t temp;
- uint8_t i;
- /* Reset UDA1380 on board Keil */
- Chip_SCU_PinMux(0x8, 0, MD_PUP, FUNC0);
- Chip_GPIO_WriteDirBit(4, 0, true);
- Chip_GPIO_WritePortBit(4, 0, true);
- /* delay 1us */
- delay(100000);
- Chip_GPIO_WritePortBit(4, 0, false);
- delay(100000);
- for (i = 0; i < 5; i++) {
- UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
- if (temp != UDA_sys_regs_dat[i]) {
- return ERROR;
- }
- }
-
- /* interfilter regs init */
- for (i = 0; i < 5; i++) {
- UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
- if (temp != UDA_interfil_regs_dat[i]) {
- return ERROR;
- }
- }
- /* decimator regs init */
- for (i = 0; i < 4; i++) {
- UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
- if (temp != UDA_decimator_regs_dat[i]) {
- return ERROR;
- }
- }
-
- if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
- /* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
- UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
- if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
- return ERROR;
- }
- UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
- UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
- I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
- if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
- return ERROR;
- }
- }
- return SUCCESS;
-
-}
-
-/** Private functions for LCD controller */
-/* Write to LCD controller, with A0 = 0 */
-static void LCD_X_Write00_16(uint16_t c) {
-
- uint8_t buf[1];
- LCD_CS(0);
- buf[0] = 0x70;
- Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1); // Start + WR Register
- buf[0] = (uint8_t) (c);
- Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
- LCD_CS(1);
-}
-
-/* Write to LCD controller, with A0 = 1 */
-static void LCD_X_Write01_16(uint16_t c) {
-
- uint8_t buf[1];
- LCD_CS(0);
- buf[0] = 0x72;
- Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1); /* Start + WR Data */
- buf[0] = (uint8_t) (c >> 8);
- Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
- buf[0] = (uint8_t) (c);
- Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1);
- LCD_CS(1);
-}
-
-/* Write to LCD controller's register */
-static void wr_reg(uint16_t reg, uint16_t dat) {
- LCD_X_Write00_16(reg);
- LCD_X_Write01_16(dat);
-}
-
-/* Pin configuration to communicate with LCD Controller */
-static void pinConfig(void)
-{
- /* (DC) */
- Chip_GPIO_WriteDirBit(7, 16, true);
- // Chip_Clock_EnableOpts(sspclk, true, true, 1);
-}
-
-/* Writes a value to the STMPE811 register */
-static uint32_t Board_TSC_WriteReg(IP_I2C_001_Type *I2Cx, uint8_t regAddr, uint8_t value)
-{
- return Chip_I2C_MasterWriteReg(I2Cx, TSC_I2C_ADDR, regAddr, &value, 1);
-}
-
-/* Reads a value to the STMPE811 register */
-static uint32_t Board_TSC_ReadReg(IP_I2C_001_Type *I2Cx, uint8_t regAddr, uint8_t *value)
-{
- return Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, regAddr, value, 1);
-}
-
-/* Check if touch is detected or not */
-static bool Board_TSC_TouchDetect(IP_I2C_001_Type *I2Cx)
-{
- uint8_t CtrRegVal = 0;
-
- if (Board_TSC_ReadReg(I2Cx, TSC_CTRL, &CtrRegVal) == 1) {
- if (CtrRegVal & (1 << 7)) {
- return true;
- }
- }
- return false;
-}
-
-/* Get the touch coordinates from STMPE811 registers */
-static Status Board_TSC_GetTouchCoord(IP_I2C_001_Type *I2Cx, int16_t *x, int16_t *y)
-{
- uint8_t fifo_size, tscData[4], i;
-
- /* Read all samples except the last one */
- Board_TSC_ReadReg(I2Cx, FIFO_SIZE, &fifo_size);
- for (i = 0; i < fifo_size; ++i)
- if (Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, DATA_XYZ, tscData, 4) == 0) {
- return ERROR;
- }
-
- /* Retrieve last taken sample */
- Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, DATA_XYZ, tscData, 4);
- *x = (tscData[0] << 4) | ((tscData[1] & 0xF0) >> 4);
- *y = ((tscData[1] & 0x0F) << 8) | tscData[2];
-
- /* Clear interrupt flags */
- Board_TSC_WriteReg(I2Cx, INT_STA, 0x1F);
-
- return SUCCESS;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Update system core clock rate, should be called if the system has
- a clock rate change */
-void SystemCoreClockUpdate(void)
-{
- /* CPU core speed */
- SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
-}
-
-/* Initialize UART pins */
-void Board_UART_Init(LPC_USART_Type *UARTx)
-{
- if (UARTx == LPC_USART0) {
- Chip_SCU_PinMux(0x2, 0, MD_PDN, FUNC1); /* P2.0 : UART0_TXD */
- Chip_SCU_PinMux(0x2, 1, MD_PLN | MD_EZI | MD_ZI, FUNC1); /* P2.1 : UART0_RXD */
- }
- else if (UARTx == LPC_USART3) {
- Chip_SCU_PinMux(0x2, 3, MD_PDN, FUNC2); /* P2.3 : UART3_TXD */
- Chip_SCU_PinMux(0x2, 4, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P2.4 : UART3_RXD */
- }
-}
-
-/* Initialize debug output via UART for board */
-void Board_Debug_Init(void)
-{
-#if defined(DEBUG_UART)
- Board_UART_Init(DEBUG_UART);
-
- Chip_UART_Init(DEBUG_UART);
- Chip_UART_SetBaud(DEBUG_UART, 115200);
- Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
-
- /* Enable UART Transmit */
- Chip_UART_TxCmd(DEBUG_UART, ENABLE);
-#endif
-}
-
-/* Sends a character on the UART */
-void Board_UARTPutChar(char ch)
-{
-#if defined(DEBUG_UART)
- while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
-#endif
-}
-
-/* Gets a character from the UART, returns EOF if no character is ready */
-int Board_UARTGetChar(void)
-{
-#if defined(DEBUG_UART)
- uint8_t data;
-
- if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
- return (int) data;
- }
-#endif
- return EOF;
-}
-
-/* Outputs a string on the debug UART */
-void Board_UARTPutSTR(char *str)
-{
-#if defined(DEBUG_UART)
- while (*str != '\0') {
- Board_UARTPutChar(*str++);
- }
-#endif
-}
-
-/* Initializes board LED(s) */
-void Board_LED_Init()
-{
- int i;
-
- /* Must make sure J21 is installed to enabled LEDs */
- /* PD.10 : LED 0 (leftmost) */
- /* PD.11 : LED 1 */
- /* PD.12 : LED 2 */
- /* PD.13 : LED 3 */
- /* PD.14 : LED 4 */
- /* P9.0 : LED 5 */
- /* P9.1 : LED 6 */
- /* P9.2 : LED 7 (rightmost) */
- for (i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) {
- Chip_GPIO_WriteDirBit(ledports[i], ledbits[i], true);
- }
-}
-
-#ifndef BOARD_LED_TEST_FUNCTION_WORKS
- /* FIXME: temporary code for toggle LED support only */
- static uint8_t LEDStates; /* shadow variable for LED states */
-#endif
-
-/* Sets the state of a board LED to on or off */
-void Board_LED_Set(uint8_t LEDNumber, bool On)
-{
- if (LEDNumber <= 7) {
- Chip_GPIO_WritePortBit(ledports[LEDNumber], ledbits[LEDNumber], On);
-#ifndef BOARD_LED_TEST_FUNCTION_WORKS
- if (On) {
- LEDStates |= (1 << LEDNumber); /* set the state */
- } else {
- LEDStates &= ~(1 << LEDNumber); /* clear the state */
- }
-#endif
- }
-}
-
-/* Returns the current state of a board LED */
-bool Board_LED_Test(uint8_t LEDNumber)
-{
- if (LEDNumber <= 7) {
-#ifndef BOARD_LED_TEST_FUNCTION_WORKS
- if (LEDStates & (1 << LEDNumber)) { /* LED is on */
- return true;
- } else { /* LED is off */
- return false;
- }
-#else
- return (bool)Chip_GPIO_ReadPortBit(ledports[LEDNumber], ledbits[LEDNumber]);
-#endif
- }
- return false;
-}
-
-/* Returns the MAC address assigned to this board */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr)
-{
- const uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
-
- memcpy(mcaddr, boardmac, 6);
-}
-
-/* Set up and initialize all required blocks and functions related to the
- board hardware */
-void Board_Init(void)
-{
- /* Sets up DEBUG UART */
- DEBUGINIT();
-
- /* Updates SystemCoreClock global var with current clock speed */
- SystemCoreClockUpdate();
-
- /* Initializes GPIO */
- Chip_GPIO_Init();
-
- /* Setup GPIOs for USB demos */
- Chip_SCU_PinMux(0x9, 5, (MD_PUP | MD_EZI), FUNC2); /* P9_5 USB1_VBUS_EN, USB1 VBus function */
- Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2); /* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */
- Chip_SCU_PinMux(0x6, 3, (MD_PUP | MD_EZI), FUNC1); /* P6_3 USB0_PWR_EN, USB0 VBus function */
-}
-
-/* Sets up board specific ADC interface */
-void Board_ADC_Init(void)
-{}
-
-/* Sets up board specific I2C interface */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx)
-{
- if (I2Cx == LPC_I2C1) {
- /* Configure pin function for I2C1 on PE.13 (I2C1_SDA) and PE.15 (I2C1_SCL) */
- Chip_SCU_PinMux(0xE, 13, MD_ZI | MD_EZI, FUNC2);
- Chip_SCU_PinMux(0xE, 15, MD_ZI | MD_EZI, FUNC2);
- }
-}
-
-/* Sets up board specific I2S interface and UDA1380 */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
-{
- uint8_t uda1380_tx_data_buf[3];
- Chip_I2S_Audio_Format_Type I2S_Config;
- I2C_M_SETUP_Type I2C_Config;
- I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
- I2C_Config.retransmissions_max = 5;
- I2C_Config.tx_length = 3;
- I2C_Config.tx_data = uda1380_tx_data_buf;
- I2C_Config.rx_length = 0;
- I2C_Config.rx_data = NULL;
-
- /* Initialize I2C peripheral ------------------------------------*/
- /* Init I2C */
- Chip_I2C_Init(LPC_I2C0);
- Chip_I2C_SetClockRate(LPC_I2C0, 100000);
-
- I2S_Config.SampleRate = 48000;
- I2S_Config.ChannelNumber = 2; /* 1 is mono, 2 is stereo */
- I2S_Config.WordWidth = 16; /* 8, 16 or 32 bits */
- Chip_I2S_Init(LPC_I2S0);
- Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
- /* Enable Slave I2C operation */
- Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
- /* Init UDA1380 CODEC */
- while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
-}
-
-/* Initialize the LCD interface */
-void Board_LCD_Init(void)
-{
- /* LCD with HX8347-D LCD Controller */
- SSP_ConfigFormat ssp_format1;
- /* Attach main PLL clock to divider A with a divider of 2 */
- Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 2);
-
- /* Route divider A output to LCD base clock and enable base clock */
- Chip_Clock_SetBaseClock(CLK_BASE_LCD, CLKIN_IDIVA, true, false);
-
- /* Reset LCD and wait for reset to complete */
- Chip_RGU_TriggerReset(RGU_LCD_RST);
- while (Chip_RGU_InReset(RGU_LCD_RST)) {}
-
- /* Set backlight GPIO as an output */
- Chip_GPIO_WriteDirBit(3, 8, true);
-
- delay(5);
-
- pinConfig();
- // Chip_Clock_EnablePeripheralMax(SSP_ID);
- /* TBD Externally */
- Chip_SSP_Init(SSP_ID);
- // NVIC_EnableIRQ(SSP_ID);
- Chip_SSP_Set_Master(SSP_ID, true);
- Chip_SSP_Set_BitRate(SSP_ID, 1000000);
-
- ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI;
- ssp_format1.bits = SSP_BITS_8;
- ssp_format1.clockFormat = SSP_CLOCK_MODE0;
-
- Chip_SSP_Set_Format(SSP_ID, &ssp_format1);
- Chip_SSP_Cmd(SSP_ID, ENABLE);
-
- delay(200);
-
- /* Driving ability settings ------------------------------------------------*/
- wr_reg(0xEA, 0x00); /* Power control internal used (1) */
- wr_reg(0xEB, 0x20); /* Power control internal used (2) */
- wr_reg(0xEC, 0x0C); /* Source control internal used (1) */
- wr_reg(0xED, 0xC7); /* Source control internal used (2) */
- wr_reg(0xE8, 0x38); /* Source output period Normal mode */
- wr_reg(0xE9, 0x10); /* Source output period Idle mode */
- wr_reg(0xF1, 0x01); /* RGB 18-bit interface ;0x0110 */
- wr_reg(0xF2, 0x10);
-
- /* Adjust the Gamma Curve --------------------------------------------------*/
- wr_reg(0x40, 0x01);
- wr_reg(0x41, 0x00);
- wr_reg(0x42, 0x00);
- wr_reg(0x43, 0x10);
- wr_reg(0x44, 0x0E);
- wr_reg(0x45, 0x24);
- wr_reg(0x46, 0x04);
- wr_reg(0x47, 0x50);
- wr_reg(0x48, 0x02);
- wr_reg(0x49, 0x13);
- wr_reg(0x4A, 0x19);
- wr_reg(0x4B, 0x19);
- wr_reg(0x4C, 0x16);
-
- wr_reg(0x50, 0x1B);
- wr_reg(0x51, 0x31);
- wr_reg(0x52, 0x2F);
- wr_reg(0x53, 0x3F);
- wr_reg(0x54, 0x3F);
- wr_reg(0x55, 0x3E);
- wr_reg(0x56, 0x2F);
- wr_reg(0x57, 0x7B);
- wr_reg(0x58, 0x09);
- wr_reg(0x59, 0x06);
- wr_reg(0x5A, 0x06);
- wr_reg(0x5B, 0x0C);
- wr_reg(0x5C, 0x1D);
- wr_reg(0x5D, 0xCC);
-
- /* Power voltage setting ---------------------------------------------------*/
- wr_reg(0x1B, 0x1B);
- wr_reg(0x1A, 0x01);
- wr_reg(0x24, 0x2F);
- wr_reg(0x25, 0x57);
- wr_reg(0x23, 0x88);
-
- /* Power on setting --------------------------------------------------------*/
- wr_reg(0x18, 0x36); /* Internal oscillator frequency adj */
- wr_reg(0x19, 0x01); /* Enable internal oscillator */
- wr_reg(0x01, 0x00); /* Normal mode, no scrool */
- wr_reg(0x1F, 0x88); /* Power control 6 - DDVDH Off */
- delay(20);
- wr_reg(0x1F, 0x82); /* Power control 6 - Step-up: 3 x VCI */
- delay(5);
- wr_reg(0x1F, 0x92); /* Power control 6 - Step-up: On */
- delay(5);
- wr_reg(0x1F, 0xD2); /* Power control 6 - VCOML active */
- delay(5);
-
- /* Color selection ---------------------------------------------------------*/
- wr_reg(0x17, 0x55); /* RGB, System interface: 16 Bit/Pixel*/
- wr_reg(0x00, 0x00); /* Scrolling off, no standby */
-
- /* Interface config --------------------------------------------------------*/
- wr_reg(0x2F, 0x11); /* LCD Drive: 1-line inversion */
- wr_reg(0x31, 0x02); /* Value for SPI: 0x00, RBG: 0x02 */
- wr_reg(0x32, 0x00); /* DPL=0, HSPL=0, VSPL=0, EPL=0 */
-
- /* Display on setting ------------------------------------------------------*/
- wr_reg(0x28, 0x38); /* PT(0,0) active, VGL/VGL */
- delay(20);
- wr_reg(0x28, 0x3C); /* Display active, VGL/VGL */
-
- wr_reg(0x16, 0x00); /* Mem Access Control (MX/Y/V/L,BGR) */
-
- /* Display scrolling settings ----------------------------------------------*/
- wr_reg(0x0E, 0x00); /* TFA MSB */
- wr_reg(0x0F, 0x00); /* TFA LSB */
- wr_reg(0x10, 320 >> 8); /* VSA MSB */
- wr_reg(0x11, 320 & 0xFF); /* VSA LSB */
- wr_reg(0x12, 0x00); /* BFA MSB */
- wr_reg(0x13, 0x00); /* BFA LSB */
-
-}
-
-/* Initializes the STMPE811 touch screen controller */
-void Init_Touch_Controller(void)
-{
- volatile int32_t i;
-
- /* Init I2C */
- Chip_I2C_Init(LPC_I2C0);
- Chip_I2C_SetClockRate(LPC_I2C0, 100000);
-
- /* Enable Slave I2C operation */
- Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
-
- /* Reset Touch-screen controller */
- Board_TSC_WriteReg(LPC_I2C0, SYS_CTRL1, 0x02);
-
- for (i = 0; i < 200000; i++) {}
-
- /* Enable TSC and ADC */
- Board_TSC_WriteReg(LPC_I2C0, SYS_CTRL2, 0x0C);
- /* Enable Touch detect, FIFO */
- Board_TSC_WriteReg(LPC_I2C0, INT_EN, 0x07);
- /* Set sample time , 12-bit mode */
- Board_TSC_WriteReg(LPC_I2C0, ADC_CTRL1, 0x69);
-
- for (i = 0; i < 40000; i++) {}
-
- /* ADC frequency 3.25 MHz */
- Board_TSC_WriteReg(LPC_I2C0, ADC_CTRL2, 0x01);
- /* Tracking index: 8, operation mode : XY only */
- Board_TSC_WriteReg(LPC_I2C0, TSC_CTRL, 0x22);
- /* Detect delay 10us Settle time 500us*/
- Board_TSC_WriteReg(LPC_I2C0, TSC_CFG, 0xC2);
- /* Threshold for FIFO */
- Board_TSC_WriteReg(LPC_I2C0, FIFO_TH, 0x01);
- /* FIFO reset */
- Board_TSC_WriteReg(LPC_I2C0, FIFO_STA, 0x01);
- /* FIFO not reset */
- Board_TSC_WriteReg(LPC_I2C0, FIFO_STA, 0x00);
- /* Drive 50 mA typical */
- Board_TSC_WriteReg(LPC_I2C0, TSC_I_DRIVE, 0x01);
- /* Pins are used for touchscreen */
- Board_TSC_WriteReg(LPC_I2C0, GPIO_ALT_FUNCT, 0x00);
- /* Enable TSC */
- Board_TSC_WriteReg(LPC_I2C0, TSC_CTRL, 0x01);
- /* Clear interrupt status */
- Board_TSC_WriteReg(LPC_I2C0, INT_STA, 0xFF);
-}
-
-/* Get touch screen position */
-bool GetTouchPos(int16_t *pX, int16_t *pY)
-{
- int16_t x, y, rng;
- if (Board_TSC_TouchDetect(LPC_I2C0)) {
- Board_TSC_GetTouchCoord(LPC_I2C0, &x, &y);
- g_isPenDn = 1;
- g_isNewPenDn = 1;
-
- /* calibrate X */
- rng = ad_right - ad_left;
- if (rng < 0) {
- rng = -rng;
- }
- x -= (ad_right < ad_left) ? ad_right : ad_left;
- *pX = (x * C_GLCD_H_SIZE) / rng;
- if (ad_left > ad_right) {
- *pX = C_GLCD_H_SIZE - *pX;
- }
-
- /* calibrate Y */
- rng = ad_bottom - ad_top;
- if (rng < 0) {
- rng = -rng;
- }
- y -= (ad_bottom < ad_top) ? ad_bottom : ad_top;
- *pY = (y * C_GLCD_V_SIZE) / rng;
- if (ad_top > ad_bottom) {
- *pY = C_GLCD_V_SIZE - *pY;
- }
- }
- else {
- g_isPenDn = 0;
- }
-
- if (g_isNewPenDn) {
- g_isNewPenDn = 0;
- if (*pX < 0) {
- *pX = -*pX;
- }
- if (*pY < 0) {
- *pY = -*pY;
- }
- return true;
- }
- return false;
-}
-
-/* Turn on LCD backlight */
-void Board_LCD_Set_Backlight(uint8_t Intensity)
-{
- bool OnOff = (bool) (Intensity != 0);
-
- Chip_GPIO_WritePortBit(3, 8, OnOff);
-}
-
-/* Interrupt handler for GPIO0 */
-void GPIO0_IRQHandler(void)
-{
- static bool On;
-
- if (Chip_GPIO_IntGetStatus(0, 0, 0)) {
- Chip_GPIO_IntClear(0, 0);
- On = (bool) !On;
- Board_LED_Set(1, On);
- }
-}
-
-/* Initializes board specific GPIO Interrupt */
-void Board_GPIO_Int_Init()
-{
- Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0); /* PF.9 : POTI button */
- Chip_GPIO_WriteDirBit(7, 23, false); /* PF.9 -> GPIO7[23] : input */
- Chip_SCU_GPIOIntPinSel(0, 7, 23);
- Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE); /* Configure GPIO0[7] to interrupt pin (SW2 switch) */
-
- NVIC_EnableIRQ(PIN_INT0_IRQn); /* enable GPIO interrupt 0 */
-}
-
-/* Initializes SDMMC interface */
-void Board_SDMMC_Init(void)
-{
- Chip_SCU_PinMux(0xC, 4, MD_PLN_FAST, FUNC7); /* PC.4 connected to SDIO_D0 */
- Chip_SCU_PinMux(0xC, 5, MD_PLN_FAST, FUNC7); /* PC.5 connected to SDIO_D1 */
- Chip_SCU_PinMux(0xC, 6, MD_PLN_FAST, FUNC7); /* PC.6 connected to SDIO_D2 */
- Chip_SCU_PinMux(0xC, 7, MD_PLN_FAST, FUNC7); /* PC.7 connected to SDIO_D3 */
-
- Chip_SCU_PinMux(0xC, 8, MD_PLN | MD_EZI, FUNC7);/* PC.4 connected to SDIO_CD */
- Chip_SCU_PinMux(0xC, 10, MD_PLN_FAST, FUNC7); /* PC.10 connected to SDIO_CMD */
- Chip_SCU_PinMux(0xC, 0, MD_PLN | MD_EHS, FUNC7);/* PC.0 connected to SDIO_CLK */
-}
-
-/* Initializes SSP interface */
-void Board_SSP_Init(LPC_SSP_Type *SSPx)
-{
- if (SSPx == LPC_SSP0) {
- /* Set up clock and power for SSP0 module */
- /* Configure SSP0 pins*/
- Chip_SCU_PinMux(0x3, 3, MD_PLN_FAST, FUNC2); /* P3.3 connected to SCL/SCLK func2=SSP0 SCK0 */
- Chip_SCU_PinMux(0x3, 6, MD_PLN_FAST, FUNC2); /* P3.6 connected to nCS func2=SSP0 SSEL0 */
- Chip_SCU_PinMux(0x3, 7, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P3.7 connected to SO func2=SSP0 MISO0 */
- Chip_SCU_PinMux(0x3, 8, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P3.8 connected to nSI func2=SSP0 MOSI0 */
-
- Chip_Clock_EnableOpts(CLK_MX_SSP0, true, true, 1);
- }
- else if (SSPx == LPC_SSP1) {
- /* Set up clock and power for SSP1 module */
- /* Configure SSP1 pins*/
- Chip_SCU_PinMux(0xF, 4, MD_PLN_FAST, FUNC0); /* PF.4 connected to SCL/SCLK func0 = SSP1 SCK1 */
- Chip_SCU_PinMux(0xF, 5, MD_PLN_FAST, FUNC2); /* PF.5 connected to nCS func2 = SSP1 SSEL1 */
- Chip_SCU_PinMux(0xF, 6, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* PF.6 connected to SO func2 = SSP1 MISO1 */
- Chip_SCU_PinMux(0xF, 7, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* PF.7 connected to nSI func2 = SSP1 MOSI1 */
-
- Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1);
- }
- else {
- return;
- }
-}
-
-/* Initializes board specific buttons */
-void Board_Buttons_Init(void)
-{
- Chip_SCU_PinMux(0x4, 0, MD_PUP | MD_EZI | MD_ZI, FUNC0); /* P9.1 : LED 6 */
- Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM, false);
-}
-
-/* Sets up default states for joystick */
-void Board_Joystick_Init(void)
-{
- Chip_SCU_PinMux(0xC, 9, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_9 as GPIO6[8] */
- Chip_SCU_PinMux(0xC, 11, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_11 as GPIO6[10] */
- Chip_SCU_PinMux(0xC, 12, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_12 as GPIO6[11] */
- Chip_SCU_PinMux(0xC, 13, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_13 as GPIO6[12] */
- Chip_SCU_PinMux(0xC, 14, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_14 as GPIO6[13] */
-
- Chip_GPIO_WriteDirBit(JOYSTICK_UP_GPIO_PORT_NUM, JOYSTICK_UP_GPIO_BIT_NUM, false); /* input */
- Chip_GPIO_WriteDirBit(JOYSTICK_DOWN_GPIO_PORT_NUM, JOYSTICK_DOWN_GPIO_BIT_NUM, false); /* input */
- Chip_GPIO_WriteDirBit(JOYSTICK_LEFT_GPIO_PORT_NUM, JOYSTICK_LEFT_GPIO_BIT_NUM, false); /* input */
- Chip_GPIO_WriteDirBit(JOYSTICK_RIGHT_GPIO_PORT_NUM, JOYSTICK_RIGHT_GPIO_BIT_NUM, false); /* input */
- Chip_GPIO_WriteDirBit(JOYSTICK_PRESS_GPIO_PORT_NUM, JOYSTICK_PRESS_GPIO_BIT_NUM, false); /* input */
-}
-
-/* Gets joystick status */
-uint8_t Joystick_GetStatus(void)
-{
-
- uint8_t ret = NO_BUTTON_PRESSED;
-
- if (Chip_GPIO_ReadPortBit(JOYSTICK_UP_GPIO_PORT_NUM, JOYSTICK_UP_GPIO_BIT_NUM) == 0) {
- ret |= JOY_UP;
- }
- else if (Chip_GPIO_ReadPortBit(JOYSTICK_DOWN_GPIO_PORT_NUM, JOYSTICK_DOWN_GPIO_BIT_NUM) == 0) {
- ret |= JOY_DOWN;
- }
- else if (Chip_GPIO_ReadPortBit(JOYSTICK_LEFT_GPIO_PORT_NUM, JOYSTICK_LEFT_GPIO_BIT_NUM) == 0) {
- ret |= JOY_LEFT;
- }
- else if (Chip_GPIO_ReadPortBit(JOYSTICK_RIGHT_GPIO_PORT_NUM, JOYSTICK_RIGHT_GPIO_BIT_NUM) == 0) {
- ret |= JOY_RIGHT;
- }
- else if (Chip_GPIO_ReadPortBit(JOYSTICK_PRESS_GPIO_PORT_NUM, JOYSTICK_PRESS_GPIO_BIT_NUM) == 0) {
- ret |= JOY_PRESS;
- }
-
- return ret;
-}
-
-/* Gets buttons status */
-uint32_t Buttons_GetStatus(void)
-{
- uint8_t ret = NO_BUTTON_PRESSED;
-
- if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
- ret |= BUTTONS_BUTTON1;
- }
- return ret;
-}
-
-/* FIXME Should we remove this function? */
-void Serial_CreateStream(void *Stream)
-{
- // implement later
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h
deleted file mode 100644
index 3e464a14d4500e75b2a0789e24e4c6500a367a4e..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * @brief Keil MCB 1857/4357 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_KEIL_MCB_18574357_H_
-#define __BOARD_KEIL_MCB_18574357_H_
-
-#include "chip.h"
-#include "board_api.h"
-#include "lpc_phy.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_KEIL_MCB_18574357 LPC1857 and LPC4357 Keil MCB board support functions
- * @ingroup BOARDS_18XX_43XX
- * @{
- */
-
-/** @defgroup BOARD_KEIL_MCB_18574357_OPTIONS BOARD: LPC1857 and LPC4357 Keil MCB board builds options
- * The NGX board has options that configure it's operation at build-time.
- * CHIP_LPC*
- * - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
- * DEBUG:
- * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART
- * - When not defined, DEBUGOUT and DEBUGSTR are null functions
- * DEBUG_UART:
- * - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0
- * CRYSTAL_MAIN_FREQ_IN:
- * - This define specifies the crystal input clock into the chip, example: 12000000
- * CRYSTAL_32K_FREQ_IN:
- * - This define specifies the RTC crystal input clock into the chip, example: 32768
- * EXTERNAL_CLKIN_FREQ_IN:
- * - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000
- * MAX_CLOCK_FREQ:
- * - When defined, this will be used to configure the CPU clock rate, example: 150000000
- * - When not defined, the system will use the maximum CPU clokc rate
- * BOARD_HITEX_EVA_18504350:
- * - When building for Keil boards, BOARD_KEIL_MCB_18574357 is defined
- *
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
- * @{
- */
-
-/**
- * @}
- */
-
-#define BOARD_KEIL_MCB_18574357
-
-#define LED_NUMBER_OF 1
-
-#define BUTTONS_BUTTON1_GPIO_PORT_NUM 2
-#define BUTTONS_BUTTON1_GPIO_BIT_NUM 0
-#define JOYSTICK_UP_GPIO_PORT_NUM 6
-#define JOYSTICK_UP_GPIO_BIT_NUM 10
-#define JOYSTICK_DOWN_GPIO_PORT_NUM 6
-#define JOYSTICK_DOWN_GPIO_BIT_NUM 11
-#define JOYSTICK_LEFT_GPIO_PORT_NUM 6
-#define JOYSTICK_LEFT_GPIO_BIT_NUM 12
-#define JOYSTICK_RIGHT_GPIO_PORT_NUM 6
-#define JOYSTICK_RIGHT_GPIO_BIT_NUM 13
-#define JOYSTICK_PRESS_GPIO_PORT_NUM 6
-#define JOYSTICK_PRESS_GPIO_BIT_NUM 8
-
-#define JOY_UP 0x01
-#define JOY_DOWN 0x02
-#define JOY_LEFT 0x04
-#define JOY_RIGHT 0x08
-#define JOY_PRESS 0x10
-#define NO_BUTTON_PRESSED 0x00
-
-#define BUTTONS_BUTTON1 0x01
-
-#define LEDS_LED1 0x01
-#define LEDS_LED2 0x02
-#define LEDS_LED3 0x04
-#define LEDS_LED4 0x08
-#define LEDS_NO_LEDS 0x00
-
-/** UDA1380 register values */
-#define UDA1380_REG_EVALCLK_DEFAULT_VALUE (0xF << 8 | 0x3 << 4 | 1 << 1)
-#define UDA1380_REG_I2S_DEFAULT_VALUE 0x0000
-
-#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
-#define UDA1380_REG_ANAMIX_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_HEADAMP_DEFAULT_VALUE ( 1 << 9 | 2)
-
-#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MIXVOL_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MODEBBT_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE (2 << 8 | 2)
-#define UDA1380_REG_MIXSDO_DEFAULT_VALUE 0x0000
-
-#define UDA1380_REG_DECVOL_DEFAULT_VALUE 0xE4E4 /* Decrease Volume -28dB */
-#define UDA1380_REG_PGA_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_ADC_DEFAULT_VALUE 0x0001 /* Apply 0bB VGA Gain, enable DC Filter */
-#define UDA1380_REG_AGC_DEFAULT_VALUE 0x0000
-
-#define UDA1380_REG_L3_DEFAULT_VALUE 0x0000
-
-/* UDA1380 address */
-#define I2CDEV_UDA1380_ADDR (0x34 >> 1)
-
-/* UDA1380 Register Address */
-typedef enum {
- UDA_EVALM_CLK = 0x00,
- UDA_BUS_CTRL,
- UDA_POWER_CTRL,
- UDA_ANALOG_CTRL,
- UDA_HPAMP_CTRL,
- UDA_MASTER_VOL_CTRL = 0x10,
- UDA_MIXER_VOL_CTRL,
- UDA_MODE_CTRL,
- UDA_MUTE_CTRL,
- UDA_MIXER_FILTER_CTRL,
- UDA_DEC_VOL_CTRL = 0x20,
- UDA_PGA_CTRL,
- UDA_ADC_CTRL,
- UDA_AGC_CTRL,
- UDA_TOTAL_REG
-} UDA1380_REG;
-
-/* Frame buffer address for lcd */
-#define FRAMEBUFFER_ADDR 0x28000000
-
-extern const LCD_Config_Type MCB4300_LCD;
-#define BOARD_LCD MCB4300_LCD
-
-/** Audio input select structure */
-typedef enum {
- MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
- MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
-} Board_Audio_Input_Sel_Type;
-
-/** LCD controller definitions */
-#define SSP_ID LPC_SSP0
-#define C_GLCD_H_SIZE 240
-#define C_GLCD_V_SIZE 320
-
-/** Private types/definitions for touch screen controller (STMPE811) */
-
-#define TSC_I2C_ADDR (0x82 >> 1) /* Touchscreen 7-bit I2C address */
-
-/** STMPE811 Register addresses */
-#define SYS_CTRL1 0x03
-#define SYS_CTRL2 0x04
-#define INT_CTRL 0x09
-#define INT_EN 0x0A
-#define INT_STA 0x0B
-#define GPIO_ALT_FUNCT 0x17
-#define ADC_CTRL1 0x20
-#define ADC_CTRL2 0x21
-#define TSC_CTRL 0x40
-#define TSC_CFG 0x41
-#define FIFO_TH 0x4A
-#define FIFO_STA 0x4B
-#define FIFO_SIZE 0x4C
-#define DATA_X 0x4D
-#define DATA_Y 0x4F
-#define DATA_Z 0x51
-#define TSC_FRACTION_Z 0x56
-#define TSC_I_DRIVE 0x58
-#define TSC_SHIELD 0x59
-#define DATA_XYZ 0xD7
-
-/**
- * @brief Sets up board specific ADC interface
- * @return Nothing
- */
-void Board_ADC_Init(void);
-
-/**
- * @brief Sets up board specific I2C interface
- * @param I2Cx : Pointer to I2C interface to initialize
- * @return Nothing
- */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Initializes board specific GPIO Interrupt
- * @return Nothing
- */
-void Board_GPIO_Int_Init(void);
-
-/**
- * @brief Sets up board specific SDMMC interface
- * @return Nothing
- */
-void Board_SDMMC_Init(void);
-
-/**
- * @brief Sets up board specific SSP interface
- * @param SSPx : Pointer to SSP interface to initialize
- * @return Nothing
- */
-void Board_SSP_Init(LPC_SSP_Type *SSPx);
-
-/**
- * @brief Returns the MAC address assigned to this board
- * @param mcaddr : Pointer to 6-byte character array to populate with MAC address
- * @return Nothing
- */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr);
-
-/**
- * @brief Initialize pin muxing for a UART
- * @param UARTx : Pointer to UART register block for UART pins to init
- * @return Nothing
- */
-void Board_UART_Init(LPC_USART_Type *UARTx);
-
-/**
- * @brief Initialize the LCD interface
- * @return Nothing
- */
-void Board_LCD_Init(void);
-
-/**
- * @brief Initializes the STMPE811 touch screen controller
- * @return Nothing
- */
-void Init_Touch_Controller(void);
-
-/**
- * @brief Get touch screen position
- * @param pX : pointer to X position
- * @param pY : pointer to Y position
- * @return true if touch is detected or false if otherwise
- */
-bool GetTouchPos(int16_t *pX, int16_t *pY);
-
-/**
- * @brief Initializes board specific buttons
- * @return Nothing
- */
-void Board_Buttons_Init (void);
-
-/**
- * @brief Initializes board specific joystick
- * @return Nothing
- */
-void Board_Joystick_Init (void);
-
-/**
- * @brief Initialize joystick interface on board
- * @return joystick status: up, down, left or right
- */
-uint8_t Joystick_GetStatus (void);
-
-/**
- * @brief Returns button(s) state on board
- * @return Returns BUTTONS_BUTTON1 if button1 is pressed
- */
-uint32_t Buttons_GetStatus(void);
-
-/**
- * @brief Sets up board specific I2S interface and UDA1380
- * @param I2Sx : Pointer to I2S interface to initialize
- * @param audio_in_sel : audio input selection
- * @return Nothing
- */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
-
-//FIXME Should we remove this function?
-void Serial_CreateStream(void *Stream);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_KEIL_MCB_18574357_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h
deleted file mode 100644
index 1bf1605fbc25a2414b61ae9c5ebf805e31267bb5..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-#define USE_RMII
-#define CHIP_LPC18XX
-
-/* Enable DEBUG for IO support via the UART */
-#define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
- via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART3
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (180000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h
deleted file mode 100644
index 79d27bd36cc73844c0b95c11761a46b79ebf81af..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-#define USE_RMII
-#define CHIP_LPC43XX
-
-/* Enable DEBUG for IO support via the UART */
-#define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
- via semihosting */
-// #define DEBUG_SEMIHOSTING'
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART3
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (204000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c
deleted file mode 100644
index 1e40430b2ccd701ec7f3b5e1491485afbb2fe766..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-
-/** @defgroup BOARD_KEIL_MCB_18574357_SYSINIT LPC1857 and LPC4357 Keil MCB board System Init code
- * @ingroup BOARD_KEIL_MCB_18574357
- * The System initialization code is called prior to the application and
- * initializes the board for run-time operation. Board initialization
- * for the Keil MCB boards includes clock setup, default pin muxing, and
- * memory configuration.
- *
- * With the exception of stack space, no RW memory is used for this call.
- *
- * LPC1857 and LPC4357 Keil MCB setup
- * Clocking:
- * All base clocks enabled by default (Save power by disabling un-needed clocks)
- * CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)
- * SPIFI FLASH clock setup for fastest speed
- * Pin muxing:
- * Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)
- * Sets up the external memory controller signals
- * Memory:
- * Sets up DRAM and NOR FLASH.
- * @{
- */
-
-#ifndef CORE_M0
-/* SCR pin definitions for pin muxing */
-typedef struct {
- uint8_t pingrp; /* Pin group */
- uint8_t pinnum; /* Pin number */
- uint8_t pincfg; /* Pin configuration for SCU */
- uint8_t funcnum;/* Function number */
-} PINMUX_GRP_T;
-
-/* Structure for initial base clock states */
-struct CLK_BASE_STATES {
- CGU_BASE_CLK_T clk; /* Base clock */
- CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
- bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
- bool powerdn; /* Set to true if the base clock is initially powered down */
-};
-
-/* Initial base clock states are mostly on */
-STATIC const struct CLK_BASE_STATES InitClkStates[] = {
- {CLK_BASE_SAFE, CLKIN_IRC, true, false},
- {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
- {CLK_BASE_USB0, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
-#endif
- {CLK_BASE_USB1, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
-#endif
- {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
-#if defined(USE_RMII)
- {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
-#else
- {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
-#endif
- {CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
-#endif
- {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
- {CLK_BASE_OUT, CLKINPUT_PD, true, false},
- {CLK_BASE_APLL, CLKINPUT_PD, true, false},
- {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
- {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
-};
-
-/* SPIFI high speed pin mode setup */
-STATIC const PINMUX_GRP_T spifipinmuxing[] = {
- {0x3, 3, (MD_PLN_FAST), FUNC3},
- {0x3, 4, (MD_PLN_FAST), FUNC3},
- {0x3, 5, (MD_PLN_FAST), FUNC3},
- {0x3, 6, (MD_PLN_FAST), FUNC3},
- {0x3, 7, (MD_PLN_FAST), FUNC3},
- {0x3, 8, (MD_PLN_FAST), FUNC3}
-};
-
-/* Setup system clocking */
-STATIC void SystemSetupClocking(void)
-{
- int i;
-
- /* Setup FLASH acceleration to target clock rate prior to clock switch */
- Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);
-
- /* Switch main system clocking to crystal */
- Chip_Clock_EnableCrystal();
- Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
-
- /* Setup PLL for 100MHz and switch main system clocking */
- Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
- Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
-
- /* Setup PLL for maximum clock */
- Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
-
- /* Setup system base clocks and initial states. This won't enable and
- disable individual clocks, but sets up the base clock sources for
- each individual peripheral clock. */
- for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
- Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
- InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
- }
-
- /* Reset and enable 32Khz oscillator */
- LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
- LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
- /* SPIFI pin setup is done prior to setting up system clocking */
- for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
- Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
- spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
- }
-
- /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
- Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
- Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-}
-
-STATIC const PINMUX_GRP_T pinmuxing[] = {
- /* RMII pin group */
- {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0},
- {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6},
- {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
- {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
- {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
- {0xC, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
- {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7},
- {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
- {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2},
- /* External data lines D0 .. D15 */
- {0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- /* Address lines A0 .. A23 */
- {0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
- {0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
- {0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- /* EMC control signals */
- {0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
- {0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {PINMUX_CLK, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
- {PINMUX_CLK, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
- {PINMUX_CLK, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
- {PINMUX_CLK, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
- {0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
- {0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
- {0x1, 3, MD_PLN_FAST, FUNC3},
- {0x1, 4, MD_PLN_FAST, FUNC3},
- {0x6, 6, MD_PLN_FAST, FUNC1},
- {0x1, 5, MD_PLN_FAST, FUNC3},
- {0x1, 6, MD_PLN_FAST, FUNC3},
- /* Board LEDs */
- {0xD, 10, (MD_PLN), FUNC4},
- {0xD, 11, (MD_PLN), FUNC4},
- {0xD, 12, (MD_PLN), FUNC4},
- {0xD, 13, (MD_PLN), FUNC4},
- {0xD, 14, (MD_PLN), FUNC4},
- {0x9, 0, (MD_PLN), FUNC0},
- {0x9, 1, (MD_PLN), FUNC0},
- {0x9, 2, (MD_PLN), FUNC0},
- /* SSP0 */
- {0xF, 0, (MD_PLN_FAST), FUNC0},
- {0xF, 1, (MD_PLN_FAST), FUNC4},
- {0xF, 2, (MD_PLN_FAST), FUNC2},
- {0xF, 3, (MD_PLN_FAST), FUNC2},
- /* LCD interface, 16bpp */
- {0x4, 1, MD_PUP, FUNC5},
- {0x4, 2, MD_PUP, FUNC2},
- {0x4, 5, MD_PUP, FUNC2},
- {0x4, 6, MD_PUP, FUNC2},
- {0x4, 7, MD_PUP, FUNC0},
- {0x4, 9, MD_PUP, FUNC2},
- {0x4, 10, MD_PUP, FUNC2},
- {0x7, 0, MD_PUP, FUNC0},
- {0x7, 6, MD_PUP, FUNC3},
- {0x8, 3, MD_PUP, FUNC3},
- {0x8, 4, MD_PUP, FUNC3},
- {0x8, 5, MD_PUP, FUNC3},
- {0x8, 6, MD_PUP, FUNC3},
- {0x8, 7, MD_PUP, FUNC3},
- {0xB, 0, MD_PUP, FUNC2},
- {0xB, 1, MD_PUP, FUNC2},
- {0xB, 2, MD_PUP, FUNC2},
- {0xB, 3, MD_PUP, FUNC2},
- {0xB, 4, MD_PUP, FUNC2},
- {0xB, 5, MD_PUP, FUNC2},
- {0xB, 6, MD_PUP, FUNC2},
- /* I2S */
- {0x3, 0, MD_PLN_FAST, FUNC2},
- {0x6, 0, MD_PLN_FAST, FUNC4},
- {0x7, 2, MD_PLN_FAST, FUNC2},
- {0x6, 2, MD_PLN_FAST, FUNC3},
- {0x7, 1, MD_PLN_FAST, FUNC2},
- {0x6, 1, MD_PLN_FAST, FUNC3},
-};
-
-/* Sets up system pin muxing */
-STATIC void SystemSetupMuxing(void)
-{
- int i;
-
- /* Setup system level pin muxing */
- for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
- Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
- pinmuxing[i].pincfg, pinmuxing[i].funcnum);
- }
-}
-
-/* EMC clock delay */
-#define CLK0_DELAY 7
-
-/* Keil SDRAM timing and chip Config */
-STATIC const IP_EMC_DYN_CONFIG_Type MT48LC4M32_config = {
- EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */
- 0x01, /* Command Delayed */
- EMC_NANOSECOND(18),
- EMC_NANOSECOND(42),
- EMC_NANOSECOND(70),
- EMC_CLOCK(0x01),
- EMC_CLOCK(0x05),
- EMC_NANOSECOND(12),
- EMC_NANOSECOND(60),
- EMC_NANOSECOND(60),
- EMC_NANOSECOND(70),
- EMC_NANOSECOND(12),
- EMC_CLOCK(0x02),
- {
- {
- EMC_ADDRESS_DYCS0, /* Keil Board uses DYCS0 for SDRAM */
- 3, /* RAS */
-
- EMC_DYN_MODE_WBMODE_PROGRAMMED |
- EMC_DYN_MODE_OPMODE_STANDARD |
- EMC_DYN_MODE_CAS_3 |
- EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
- EMC_DYN_MODE_BURST_LEN_4,
-
- EMC_DYN_CONFIG_DATA_BUS_32 |
- EMC_DYN_CONFIG_LPSDRAM |
- EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS |
- EMC_DYN_CONFIG_MD_SDRAM
- },
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0}
- }
-};
-
-/* Keil NorFlash timing and chip Config */
-/* FIXME : Keil NOR FLASH not yet tested */
-STATIC const IP_EMC_STATIC_CONFIG_Type S29GL64N90_config = {
- 0,
- EMC_STATIC_CONFIG_MEM_WIDTH_32 |
- EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
- EMC_STATIC_CONFIG_BLS_HIGH /* |
- EMC_CONFIG_BUFFER_ENABLE*/,
-
- EMC_NANOSECOND(0),
- EMC_NANOSECOND(65),
- EMC_NANOSECOND(90),
- EMC_NANOSECOND(90),
- EMC_NANOSECOND(35),
- EMC_CLOCK(4)
-};
-
-/* Setup external memories */
-STATIC void SystemSetupMemory(void)
-{
- /* Setup EMC Delays */
- /* Move all clock delays together */
- LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
-
- /* Setup EMC Clock Divider for divide by 2 */
- Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
- LPC_CREG->CREG6 |= (1 << 16);
- Chip_Clock_Enable(CLK_MX_EMC);
-
- /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
- Chip_EMC_Init(1, 0, 0);
- /* Init EMC Dynamic Controller */
- Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &MT48LC4M32_config);
- /* Init EMC Static Controller CS0 */
- Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &S29GL64N90_config);
-
- /* Enable Buffer for External Flash */
- LPC_EMC->STATICCONFIG0 |= 1 << 19;
-}
-
-#endif
-
-/**
- * @brief Setup the system
- * SystemInit() is called prior to the application and sets up system
- * clocking, memory, and any resources needed prior to the application
- * starting.
- * @return none
- */
-void SystemInit(void)
-{
-#if defined(CORE_M3) || defined(CORE_M4)
- unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-
-#if defined(__IAR_SYSTEMS_ICC__)
- extern void *__vector_table;
-
- *pSCB_VTOR = (unsigned int) &__vector_table;
-#elif defined(__CODE_RED)
- extern void *g_pfnVectors;
-
- *pSCB_VTOR = (unsigned int) &g_pfnVectors;
-#elif defined(__ARMCC_VERSION)
- extern void *__Vectors;
-
- *pSCB_VTOR = (unsigned int) &__Vectors;
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
- fpuInit();
-#endif
-
- /* Setup system clocking and memory. This is done early to allow the
- application and tools to clear memory and use scatter loading to
- external memory. */
- SystemSetupClocking();
- SystemSetupMuxing();
- SystemSetupMemory();
-#endif
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h
deleted file mode 100644
index f23c8b21bc2fa6a221faf689712268ee0c250b27..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * @brief NGX Xplorer 1830/4330 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_H_
-#define __BOARD_H_
-
-#include "board_ngx_xplorer_18304330.h"
-
-#endif /* __BOARD_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c
deleted file mode 100644
index 79834b7bce61e1c6db7a8cb0147e28d0f260529a..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-#include "string.h"
-
-#include "lpc_phy_smsc87x0.c"
-#include "retarget.c"
-
-/** @ingroup BOARD_NGX_XPLORER_18304330
- * @{
- */
-
-void Board_UART_Init(LPC_USART_Type *UARTx)
-{
- if (UARTx == LPC_USART0) {
- Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2); /* P6.5 : UART0_TXD */
- Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P6.4 : UART0_RXD */
- }
- else if (UARTx == LPC_UART1) {
- Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2); /* P1.13 : UART1_TXD */
- Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P1.14 : UART1_RX */
- }
-}
-
-/* Initialize debug output via UART for board */
-void Board_Debug_Init(void)
-{
-#if defined(DEBUG_UART)
- Board_UART_Init(DEBUG_UART);
-
- Chip_UART_Init(DEBUG_UART);
- Chip_UART_SetBaud(DEBUG_UART, 115200);
- Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
-
- /* Enable UART Transmit */
- Chip_UART_TxCmd(DEBUG_UART, ENABLE);
-#endif
-}
-
-/* Sends a character on the UART */
-void Board_UARTPutChar(char ch)
-{
-#if defined(DEBUG_UART)
- while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
-#endif
-}
-
-/* Gets a character from the UART, returns EOF if no character is ready */
-int Board_UARTGetChar(void)
-{
-#if defined(DEBUG_UART)
- uint8_t data;
-
- if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
- return (int) data;
- }
-#endif
- return EOF;
-}
-
-/* Outputs a string on the debug UART */
-void Board_UARTPutSTR(char *str)
-{
-#if defined(DEBUG_UART)
- while (*str != '\0') {
- Board_UARTPutChar(*str++);
- }
-#endif
-}
-
-void Board_LED_Init()
-{
- /* P2.12 : LED D2 as output */
- Chip_GPIO_WriteDirBit(1, 12, true);
-
- /* P2.11 : LED D3 as output */
- Chip_GPIO_WriteDirBit(1, 11, true);
-
- /* Set initial states to off (true to disable) */
- Chip_GPIO_WritePortBit(1, 12, (bool) true);
- Chip_GPIO_WritePortBit(1, 11, (bool) true);
-}
-
-void Board_LED_Set(uint8_t LEDNumber, bool On)
-{
- if (LEDNumber == 0) {
- Chip_GPIO_WritePortBit(1, 12, (bool) !On);
- }
- else if (LEDNumber == 1) {
- Chip_GPIO_WritePortBit(1, 11, (bool) !On);
- }
-}
-
-bool Board_LED_Test(uint8_t LEDNumber)
-{
- if (LEDNumber == 0) {
- return (bool) !Chip_GPIO_ReadPortBit(1, 12);
- }
- else if (LEDNumber == 1) {
- return (bool) !Chip_GPIO_ReadPortBit(1, 11);
- }
-
- return false;
-}
-
-void Board_Buttons_Init(void) // FIXME not functional ATM
-{
- Chip_SCU_PinMux(0x2, 7, MD_PUP | MD_EZI | MD_ZI, FUNC0); // P2_7 as GPIO0[7]
- Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, (1 << BUTTONS_BUTTON1_GPIO_BIT_NUM), false); // input
-}
-
-uint32_t Buttons_GetStatus(void)
-{
- uint8_t ret = NO_BUTTON_PRESSED;
- if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
- ret |= BUTTONS_BUTTON1;
- }
- return ret;
-}
-
-void Board_Joystick_Init(void)
-{}
-
-uint8_t Joystick_GetStatus(void)
-{
- return NO_BUTTON_PRESSED;
-}
-
-/*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock;
-
-/* Update system core clock rate, should be called if the system has
- a clock rate change */
-void SystemCoreClockUpdate(void)
-{
- /* CPU core speed */
- SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
-}
-
-/* Returns the MAC address assigned to this board */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr)
-{
- uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
-
- memcpy(mcaddr, boardmac, 6);
-}
-
-/* Set up and initialize all required blocks and functions related to the
- board hardware */
-void Board_Init(void)
-{
- /* Sets up DEBUG UART */
- DEBUGINIT();
-
- /* Updates SystemCoreClock global var with current clock speed */
- SystemCoreClockUpdate();
-
- /* Initializes GPIO */
- Chip_GPIO_Init();
-
- /* Setup GPIOs for USB demos */
- Chip_SCU_PinMux(0x2, 6, (MD_PUP | MD_EZI), FUNC4); /* P2_6 USB1_PWR_EN, USB1 VBus function */
- Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2); /* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */
- Chip_SCU_PinMux(0x1, 7, (MD_PUP | MD_EZI), FUNC4); /* P1_7 USB0_PWR_EN, USB0 VBus function Xplorer */
- Chip_GPIO_WriteDirBit(5, 6, true); /* GPIO5[6] = USB1_PWR_EN */
- Chip_GPIO_WritePortBit(5, 6, true); /* GPIO5[6] output high */
-}
-
-void Board_I2C_Init(LPC_I2C_Type *I2Cx)
-{
- if (I2Cx == LPC_I2C1) {
- /* Configure pin function for I2C1*/
- Chip_SCU_PinMux(0x2, 3, MD_ZI | MD_EZI, FUNC1); /* P2.3 : I2C1_SDA */
- Chip_SCU_PinMux(0x2, 4, MD_ZI | MD_EZI, FUNC1); /* P2.4 : I2C1_SCL */
- }
-}
-
-void GPIO0_IRQHandler(void)
-{
- static bool On;
-
- if (Chip_GPIO_IntGetStatus(0, 0, 0)) {
- Chip_GPIO_IntClear(0, 0);
- On = (bool) !On;
- Board_LED_Set(1, On);
- }
-}
-
-void Board_GPIO_Int_Init()
-{
- Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0); /* PF.9 : POTI button */
- Chip_GPIO_WriteDirBit(7, 23, false); /* PF.9 -> GPIO7[23] : input */
- Chip_SCU_GPIOIntPinSel(0, 7, 23);
- Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE); /* Configure GPIO0[7] to interrupt pin (SW2 switch) */
-
- NVIC_EnableIRQ(PIN_INT0_IRQn); /* enable GPIO interrupt 0 */
-}
-
-void Board_SDMMC_Init(void)
-{
- Chip_SCU_PinMux(0x1, 9, MD_PLN_FAST, FUNC7); /* P1.9 connected to SDIO_D0 */
- Chip_SCU_PinMux(0x1, 10, MD_PLN_FAST, FUNC7); /* P1.10 connected to SDIO_D1 */
- Chip_SCU_PinMux(0x1, 11, MD_PLN_FAST, FUNC7); /* P1.11 connected to SDIO_D2 */
- Chip_SCU_PinMux(0x1, 12, MD_PLN_FAST, FUNC7); /* P1.12 connected to SDIO_D3 */
-
- Chip_SCU_PinMux(PINMUX_CLK, 2, MD_PLN | MD_EZI, FUNC4); /* CLK2 connected to SDIO_CLK */
- Chip_SCU_PinMux(0x1, 6, MD_PLN_FAST, FUNC7); /* P1.6 connected to SDIO_CMD */
-}
-
-void Board_SSP_Init(LPC_SSP_Type *SSPx)
-{
- if (SSPx == LPC_SSP1) {
- /* Set up clock and power for SSP1 module */
- /* Configure SSP1 pins*/
- /* SCLK comes out pin CLK0 */
- Chip_SCU_PinMux(PINMUX_CLK, 0, MD_PLN_FAST, FUNC6); /* CLK0 connected to CLK func6=SSP1 CLK1 */
- Chip_SCU_PinMux(0x1, 5, MD_PLN_FAST, FUNC5); /* P1.5 connected to nCS func5=SSP1 SSEL1 */
- Chip_SCU_PinMux(0x1, 3, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.3 connected to SO func5=SSP1 MISO1 */
- Chip_SCU_PinMux(0x1, 4, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.4 connected to nSI func5=SSP1 MOSI1 */
- Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1);
- }
- else {
- return;
- }
-}
-
-/* System Register Data Set */
-uint16_t UDA_sys_regs_dat[] = {
- UDA1380_REG_EVALCLK_DEFAULT_VALUE,
- UDA1380_REG_I2S_DEFAULT_VALUE,
- UDA1380_REG_PWRCTRL_DEFAULT_VALUE,
- UDA1380_REG_ANAMIX_DEFAULT_VALUE,
- UDA1380_REG_HEADAMP_DEFAULT_VALUE
-};
-
-/* System Register Data Set */
-uint16_t UDA_interfil_regs_dat[] = {
- UDA1380_REG_MSTRVOL_DEFAULT_VALUE,
- UDA1380_REG_MIXVOL_DEFAULT_VALUE,
- UDA1380_REG_MODEBBT_DEFAULT_VALUE,
- UDA1380_REG_MSTRMUTE_DEFAULT_VALUE,
- UDA1380_REG_MIXSDO_DEFAULT_VALUE
-};
-/* decimator Register Data Set */
-uint16_t UDA_decimator_regs_dat[] = {
- UDA1380_REG_DECVOL_DEFAULT_VALUE,
- UDA1380_REG_PGA_DEFAULT_VALUE,
- UDA1380_REG_ADC_DEFAULT_VALUE,
- UDA1380_REG_AGC_DEFAULT_VALUE
-};
-static void delay(uint32_t i) {
- while (i--) {}
-}
-
-static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) {
-
- I2C_Config->tx_data[0] = reg;
- I2C_Config->tx_data[1] = value >> 8;
- I2C_Config->tx_data[2] = value & 0xFF;
- Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING);
- delay(10000);
-}
-
-static uint16_t UDA_Reg_read(UDA1380_REG reg) {
- uint8_t rx_data[2];
- Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2);
- return rx_data[0] << 8 | rx_data[1];
-}
-
-static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel)
-{
- uint16_t temp;
- uint8_t i;
- /* Reset UDA1380 on board NGX Xplorer */
- Chip_SCU_PinMux(0x2, 10, MD_PUP, FUNC0);
- Chip_GPIO_WriteDirBit(0, 14, true);
- Chip_GPIO_WritePortBit(0, 14, true);
- // delay 1us
- delay(100000);
- Chip_GPIO_WritePortBit(0, 14, false);
- delay(100000);
- for (i = 0; i < 5; i++) {
- UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i));
- if (temp != UDA_sys_regs_dat[i]) {
- return ERROR;
- }
- }
-
- /* interfilter regs init */
- for (i = 0; i < 5; i++) {
- UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i));
- if (temp != UDA_interfil_regs_dat[i]) {
- return ERROR;
- }
- }
- /* decimator regs init */
- for (i = 0; i < 4; i++) {
- UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i));
- if (temp != UDA_decimator_regs_dat[i]) {
- return ERROR;
- }
- }
-
- if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) {
- /* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */
- UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
- if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
- return ERROR;
- }
- UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL),
- UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT,
- I2C_Config);
- temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL));
- if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) {
- return ERROR;
- }
- }
- return SUCCESS;
-
-}
-
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel)
-{
- uint8_t uda1380_tx_data_buf[3];
- Chip_I2S_Audio_Format_Type I2S_Config;
- I2C_M_SETUP_Type I2C_Config;
- I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR;
- I2C_Config.retransmissions_max = 5;
- I2C_Config.tx_length = 3;
- I2C_Config.tx_data = uda1380_tx_data_buf;
- I2C_Config.rx_length = 0;
- I2C_Config.rx_data = NULL;
-
- /* Initialize I2C peripheral ------------------------------------*/
- /* Init I2C */
- Chip_I2C_Init(LPC_I2C0);
- Chip_I2C_SetClockRate(LPC_I2C0, 100000);
-
- I2S_Config.SampleRate = 48000;
- I2S_Config.ChannelNumber = 2; /* 1 is mono, 2 is stereo */
- I2S_Config.WordWidth = 16; /* 8, 16 or 32 bits */
- Chip_I2S_Init(LPC_I2S0);
- Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config);
- /* Enable Slave I2C operation */
- Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE);
- /* Init UDA1380 CODEC */
- while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {}
-
-}
-
-/* FIXME Should we remove this function? */
-void Serial_CreateStream(void *Stream)
-{}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h
deleted file mode 100644
index ee9fa0cf903e1c20b146f30901896e041834eeda..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * @brief NGX Xplorer 1830/4330 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_NGX_XPLORER_18304330_H_
-#define __BOARD_NGX_XPLORER_18304330_H_
-
-#include "chip.h"
-#include "board_api.h"
-#include "lpc_phy.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_NGX_XPLORER_18304330 LPC1830 and LPC4330 NGX Xplorer board support functions
- * @ingroup BOARDS_18XX_43XX
- * @{
- */
-
-/** @defgroup BOARD_NGX_XPLORER_18304330_OPTIONS BOARD: LPC1830 and LPC4330 NGX Xplorer board builds options
- * The NGX board has options that configure it's operation at build-time.
- * CHIP_LPC*
- * - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board
- * DEBUG:
- * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART
- * - When not defined, DEBUGOUT and DEBUGSTR are null functions
- * DEBUG_UART:
- * - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0
- * CRYSTAL_MAIN_FREQ_IN:
- * - This define specifies the crystal input clock into the chip, example: 12000000
- * CRYSTAL_32K_FREQ_IN:
- * - This define specifies the RTC crystal input clock into the chip, example: 32768
- * EXTERNAL_CLKIN_FREQ_IN:
- * - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000
- * MAX_CLOCK_FREQ:
- * - When defined, this will be used to configure the CPU clock rate, example: 150000000
- * - When not defined, the system will use the maximum CPU clokc rate
- * BOARD_HITEX_EVA_18504350:
- * - When building for NGX boards, BOARD_NGX_XPLORER_18304330 is defined
- *
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
- * @{
- */
-
-/**
- * @}
- */
-
-#define BOARD_NGX_XPLORER_18304330
-
-#define I2CDEV_UDA1380_ADDR (0x34 >> 1)
-
-#define UDA1380_REG_EVALCLK_DEFAULT_VALUE (0xF << 8 | 0x3 << 4 | 1 << 1)
-#define UDA1380_REG_I2S_DEFAULT_VALUE 0x0000
-
-#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
-#define UDA1380_REG_ANAMIX_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_HEADAMP_DEFAULT_VALUE ( 1 << 9 | 2)
-
-#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MIXVOL_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MODEBBT_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE (2 << 8 | 2)
-#define UDA1380_REG_MIXSDO_DEFAULT_VALUE 0x0000
-
-#define UDA1380_REG_DECVOL_DEFAULT_VALUE 0xE4E4 /* Decrease Volume -28dB */
-#define UDA1380_REG_PGA_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_ADC_DEFAULT_VALUE 0x0001 /* Apply 0bB VGA Gain, enable DC Filter */
-#define UDA1380_REG_AGC_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_L3_DEFAULT_VALUE 0x0000
-
-/* For USBLIB examples */
-#define LEDS_LED1 0x01
-#define LEDS_LED2 0x02
-#define LEDS_LED3 0x04
-#define LEDS_LED4 0x08
-#define LEDS_NO_LEDS 0x00
-#define BUTTONS_BUTTON1 0x01
-#define JOY_UP 0x01
-#define JOY_DOWN 0x02
-#define JOY_LEFT 0x04
-#define JOY_RIGHT 0x08
-#define JOY_PRESS 0x10
-#define NO_BUTTON_PRESSED 0x00
-
-#define BUTTONS_BUTTON1_GPIO_PORT_NUM 0
-#define BUTTONS_BUTTON1_GPIO_BIT_NUM 7
-#define LED1_GPIO_PORT_NUM 1
-#define LED1_GPIO_BIT_NUM 11
-#define LED2_GPIO_PORT_NUM 1
-#define LED2_GPIO_BIT_NUM 12
-
-typedef enum {
- MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3,
- MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00,
-} Board_Audio_Input_Sel_Type;
-
-/* UDA1380 Register Address */
-typedef enum {
- UDA_EVALM_CLK = 0x00,
- UDA_BUS_CTRL,
- UDA_POWER_CTRL,
- UDA_ANALOG_CTRL,
- UDA_HPAMP_CTRL,
- UDA_MASTER_VOL_CTRL = 0x10,
- UDA_MIXER_VOL_CTRL,
- UDA_MODE_CTRL,
- UDA_MUTE_CTRL,
- UDA_MIXER_FILTER_CTRL,
- UDA_DEC_VOL_CTRL = 0x20,
- UDA_PGA_CTRL,
- UDA_ADC_CTRL,
- UDA_AGC_CTRL,
- UDA_TOTAL_REG
-} UDA1380_REG;
-
-/**
- * @brief Sets up board specific I2C interface
- * @param I2Cx : Pointer to I2C interface to initialize
- * @return Nothing
- */
-void Board_I2C_Init(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Initializes board specific GPIO Interrupt
- * @return Nothing
- */
-void Board_GPIO_Int_Init(void);
-
-/**
- * @brief Initialize pin muxing for SSP interface
- * @param SSPx : Pointer to SSP interface to initialize
- * @return Nothing
- */
-void Board_SSP_Init(LPC_SSP_Type *SSPx);
-
-/**
- * @brief Returns the MAC address assigned to this board
- * @param mcaddr : Pointer to 6-byte character array to populate with MAC address
- * @return Nothing
- */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr);
-
-/**
- * @brief Initialize pin muxing for a UART
- * @param UARTx : Pointer to UART register block for UART pins to init
- * @return Nothing
- */
-void Board_UART_Init(LPC_USART_Type *UARTx);
-
-/**
- * @brief Initialize pin muxing for SDMMC interface
- * @return Nothing
- */
-void Board_SDMMC_Init(void);
-
-/**
- * @brief Initialize button(s) interface on board
- * @return Nothing
- */
-void Board_Buttons_Init(void);
-
-/**
- * @brief Initialize joystick interface on board
- * @return Nothing
- */
-void Board_Joystick_Init(void);
-
-/**
- * @brief Returns joystick states on board
- * @return Returns a JOY_* value, ir JOY_PRESS or JOY_UP
- */
-uint8_t Joystick_GetStatus(void);
-
-/**
- * @brief Returns button(s) state on board
- * @return Returns BUTTONS_BUTTON1 if button1 is pressed
- */
-uint32_t Buttons_GetStatus (void);
-
-/**
- * @brief Initialize I2S interface for the board and UDA1380
- * @param I2Sx : Pointer to I2S register interface used on this board
- * @param audio_in_sel : Audio input selection
- * @return Nothing
- */
-void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel);
-
-/**
- * @brief FIXME
- * @param Stream : FIXME
- * @return Nothing
- */
-void Serial_CreateStream(void *Stream);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_NGX_XPLORER_18304330_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h
deleted file mode 100644
index 387e8620f0ea4e3d7c676d04bf3c24ed9f04d3ca..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-#define USE_RMII
-#define CHIP_LPC18XX
-
-/* Enable DEBUG for IO support via the UART */
-// #define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
- via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0 /* No port on Xplorer */
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (180000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h
deleted file mode 100644
index 13b676019f30d36001fe804afeed889cfceb20e9..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-#define USE_RMII
-#define CHIP_LPC43XX
-
-/* Enable DEBUG for IO support via the UART */
-// #define DEBUG
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
- via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0 /* No port on Xplorer */
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (204000000)
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c
deleted file mode 100644
index 7668a7c2c42ea09e3a4baebc1a8c4bad409933aa..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-
-/** @defgroup BOARD_NGX_XPLORER_18304330_SYSINIT LPC1830 and LPC4330 NGX Xplorer board System Init code
- * @ingroup BOARD_NGX_XPLORER_18304330
- * The System initialization code is called prior to the application and
- * initializes the board for run-time operation. Board initialization
- * for the NGX Xplorer boards includes clock setup and default pin muxing
- * configuration.
- *
- * With the exception of stack space, no RW memory is used for this call.
- *
- * LPC1830 and LPC4330 NGX Xplorer setup
- * Clocking:
- * All base clocks enabled by default (Save power by disabling un-needed clocks)
- * CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)
- * SPIFI FLASH clock setup for fastest speed
- * Pin muxing:
- * Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)
- * Memory:
- * There is no memory setup for this board.
- * @{
- */
-
-#ifndef CORE_M0
-/* SCR pin definitions for pin muxing */
-typedef struct {
- uint8_t pingrp; /* Pin group */
- uint8_t pinnum; /* Pin number */
- uint8_t pincfg; /* Pin configuration for SCU */
- uint8_t funcnum;/* Function number */
-} PINMUX_GRP_T;
-
-/* Structure for initial base clock states */
-struct CLK_BASE_STATES {
- CGU_BASE_CLK_T clk; /* Base clock */
- CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
- bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
- bool powerdn; /* Set to true if the base clock is initially powered down */
-};
-
-/* Initial base clock states are mostly on */
-STATIC const struct CLK_BASE_STATES InitClkStates[] = {
- {CLK_BASE_SAFE, CLKIN_IRC, true, false},
- {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
- {CLK_BASE_USB0, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
-#endif
- {CLK_BASE_USB1, CLKIN_USBPLL, true, false},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
-#endif
- {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
-#if defined(USE_RMII)
- {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
-#else
- {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
-#endif
- {CLK_BASE_LCD, CLKIN_MAINPLL, false, true},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
-#endif
- {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
- {CLK_BASE_OUT, CLKINPUT_PD, true, false},
- {CLK_BASE_APLL, CLKINPUT_PD, true, false},
- {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
- {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
-};
-
-/* SPIFI high speed pin mode setup */
-STATIC const PINMUX_GRP_T spifipinmuxing[] = {
- {0x3, 3, (MD_PLN_FAST), FUNC3}, /* SPIFI CLK */
- {0x3, 4, (MD_PLN_FAST), FUNC3}, /* SPIFI D3 */
- {0x3, 5, (MD_PLN_FAST), FUNC3}, /* SPIFI D2 */
- {0x3, 6, (MD_PLN_FAST), FUNC3}, /* SPIFI D1 */
- {0x3, 7, (MD_PLN_FAST), FUNC3}, /* SPIFI D0 */
- {0x3, 8, (MD_PLN_FAST), FUNC3} /* SPIFI CS/SSEL */
-};
-
-/* Setup system clocking */
-STATIC void SystemSetupClocking(void)
-{
- int i;
-
- /* Switch main system clocking to crystal */
- Chip_Clock_EnableCrystal();
- Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
-
- /* Setup PLL for 100MHz and switch main system clocking */
- Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
- Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
-
- /* Setup PLL for maximum clock */
- Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
-
- /* Setup system base clocks and initial states. This won't enable and
- disable individual clocks, but sets up the base clock sources for
- each individual peripheral clock. */
- for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
- Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
- InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
- }
-
- /* Reset and enable 32Khz oscillator */
- LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
- LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
- /* SPIFI pin setup is done prior to setting up system clocking */
- for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
- Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
- spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
- }
-
- /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
- Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
- Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-}
-
-STATIC const PINMUX_GRP_T pinmuxing[] = {
- /* RMII pin group */
- {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
- {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2},
- {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7},
- {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6},
- {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0},
- {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
- {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
- {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
- {0x2, 0, (MD_EHS | MD_PLN | MD_ZI), FUNC7},
- /* Board LEDs */
- {0x2, 11, MD_PDN, FUNC0},
- {0x2, 12, MD_PDN, FUNC0},
- /* I2S */
- {0x3, 0, MD_PLN_FAST, FUNC2},
- {0x6, 0, MD_PLN_FAST, FUNC4},
- {0x7, 2, MD_PLN_FAST, FUNC2},
- {0x6, 2, MD_PLN_FAST, FUNC3},
- {0x7, 1, MD_PLN_FAST, FUNC2},
- {0x6, 1, MD_PLN_FAST, FUNC3},
-};
-
-/* Sets up system pin muxing */
-STATIC void SystemSetupMuxing(void)
-{
- int i;
-
- /* Setup system level pin muxing */
- for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
- Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
- pinmuxing[i].pincfg, pinmuxing[i].funcnum);
- }
-}
-
-/* Nothing to do for the Xplorer board */
-STATIC void SystemSetupMemory(void)
-{}
-
-#endif
-
-/**
- * @brief Setup the system
- * @return none
- * SystemInit() is called prior to the application and sets up system
- * clocking, memory, and any resources needed prior to the application
- * starting.
- */
-void SystemInit(void)
-{
-#if defined(CORE_M3) || defined(CORE_M4)
- volatile unsigned int *pSCB_VTOR = (volatile unsigned int *) 0xE000ED08;
-
-#if defined(__IAR_SYSTEMS_ICC__)
- extern void *__vector_table;
-
- *pSCB_VTOR = (unsigned int) &__vector_table;
-#elif defined(__CODE_RED)
- extern void *g_pfnVectors;
-
- *pSCB_VTOR = (unsigned int) &g_pfnVectors;
-#elif defined(__ARMCC_VERSION)
- extern void *__Vectors;
-
- *pSCB_VTOR = (unsigned int) &__Vectors;
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
- fpuInit();
-#endif
-
- /* Setup system clocking and memory. This is done early to allow the
- application and tools to clear memory and use scatter loading to
- external memory. */
- SystemSetupClocking();
- SystemSetupMuxing();
- SystemSetupMemory();
-#endif
-}
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/SConscript b/bsp/xplorer4330/libraries/lpc_chip/SConscript
deleted file mode 100644
index a3b3fe12df1d985c2a105befcd67e2f92dc0f908..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/SConscript
+++ /dev/null
@@ -1,15 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd = GetCurrentDir()
-
-src = Glob('chip_18xx_43xx/*.c')
-src += Glob('chip_common/*.c')
-
-path = [cwd + '/chip_18xx_43xx',
- cwd + '/chip_common']
-
-group = DefineGroup('lpc_chip', src, depend = [], CPPPATH = path)
-
-Return('group')
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c
deleted file mode 100644
index 38f2ba0cd79ccfb3985368ff2bb228cef2764841..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * @brief LPC18xx/43xx A/D conversion driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "adc_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*The channel to be operated on */
-static uint8_t active_channel;
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Returns the clock for the selected ADC */
-static CCU_CLK_T Chip_ADC_GetClk(LPC_ADC_Type *pADC)
-{
- CCU_CLK_T adcclk;
-
- if (pADC == LPC_ADC0) {
- adcclk = CLK_APB3_ADC0;
- }
- else {
- adcclk = CLK_APB3_ADC1;
- }
-
- return adcclk;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the ADC peripheral and the ADC setup structure to default value */
-void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup)
-{
- CCU_CLK_T adcclk = Chip_ADC_GetClk(pADC);
-
- /* Enable ADC clocking */
- Chip_Clock_EnableOpts(adcclk, true, true, 1);
- ADCSetup->adcPerClock = Chip_Clock_GetRate(adcclk);
-
- ADCSetup->adcRate = 400000;
- ADCSetup->bitsAccuracy = ADC_10BITS;
- IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
-}
-
-/* Select the mode starting the AD conversion */
-void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption)
-{
- if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
- IP_ADC_EdgeStartConfig(pADC, (uint8_t) EdgeOption);
- }
- IP_ADC_SetStartMode(pADC, (uint8_t) mode);
-}
-
-/* Set the ADC Sample rate */
-void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate)
-{
- ADCSetup->adcRate = rate;
- IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
-
-}
-
-/* Set the ADC accuracy bits */
-void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution)
-{
- ADCSetup->bitsAccuracy = resolution;
- IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy);
-}
-
-/* Enable or disable the ADC channel on ADC peripheral */
-void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState)
-{
- IP_ADC_SetChannelNumber(pADC, channel, NewState);
- active_channel = channel;
-}
-
-/* Enable burst mode */
-void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
-{
- IP_ADC_SetStartMode(pADC, ADC_NO_START);
- IP_ADC_SetBurstMode(pADC, NewState);
-}
-
-/* Read the ADC value and convert it to 8bits value */
-Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data)
-{
- uint16_t temp;
- Status rt;
-
- rt = IP_ADC_Get_Val(pADC, active_channel, &temp);
- *data = (uint8_t) temp;
-
- return rt;
-}
-
-/* Set a channel to be read A/D data */
-void Chip_ADC_Active_Channel(uint8_t channel)
-{
- active_channel = channel;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h
deleted file mode 100644
index f71df0a32135895e6063b97b95a3f20a781b51e8..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * @brief LPC18xx/43xx A/D conversion driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ADC_18XX_43XX_H_
-#define __ADC_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup ADC_18XX_43XX CHIP: LPC18xx/43xx A/D conversion driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** The channels on one ADC peripheral*/
-typedef enum ADC_Channel {
- ADC_CH0 = 0, /**< ADC channel 0 */
- ADC_CH1, /**< ADC channel 1 */
- ADC_CH2, /**< ADC channel 2 */
- ADC_CH3, /**< ADC channel 3 */
- ADC_CH4, /**< ADC channel 4 */
- ADC_CH5, /**< ADC channel 5 */
- ADC_CH6, /**< ADC channel 6 */
- ADC_CH7, /**< ADC channel 7 */
-} ADC_Channel;
-
-/** The number of bits of accuracy of the result in the LS bits of ADDR*/
-typedef enum ADC_Resolution {
- ADC_10BITS = 0, /**< ADC 10 bits */
- ADC_9BITS, /**< ADC 9 bits */
- ADC_8BITS, /**< ADC 8 bits */
- ADC_7BITS, /**< ADC 7 bits */
- ADC_6BITS, /**< ADC 6 bits */
- ADC_5BITS, /**< ADC 5 bits */
- ADC_4BITS, /**< ADC 4 bits */
- ADC_3BITS, /**< ADC 3 bits */
-} ADC_Resolution;
-
-/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
-typedef enum ADC_EdgeCfg {
- ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */
- ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */
-} ADC_EdgeCfg;
-
-/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
-typedef enum ADC_StartMode {
- ADC_NO_START = 0,
- ADC_START_NOW, /*!< Start conversion now */
- ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
- ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
- ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
- ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
- ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
-} ADC_StartMode;
-
-/** Clock setup structure for ADC controller passed to the initialize function */
-typedef struct {
- uint32_t adcPerClock; /*!< ADC peripheral Clock */
- uint32_t adcRate; /*!< ADC rate */
- uint8_t bitsAccuracy; /*!< ADC bit accuracy */
-} ADC_Clock_Setup_Type;
-
-/**
- * @brief Read the ADC value from a channel
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : ADC channel to read
- * @param data : Pointer to where to put data
- * @return SUCCESS or ERROR if no conversion is ready
- */
-STATIC INLINE Status Chip_ADC_Read_Value(LPC_ADC_Type *pADC, uint8_t channel, uint16_t *data)
-{
- return IP_ADC_Get_Val(pADC, channel, data);
-}
-
-/**
- * @brief Read the ADC channel status
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : ADC channel to read
- * @param StatusType : Status type of ADC_DR_*
- * @return SET or RESET
- */
-STATIC INLINE FlagStatus Chip_ADC_Read_Status(LPC_ADC_Type *pADC, uint8_t channel, uint32_t StatusType)
-{
- return IP_ADC_GetStatus(pADC, channel, StatusType);
-}
-
-/**
- * @brief Enable/Disable interrupt for ADC channel
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : ADC channel to read
- * @param NewState : New state, ENABLE or DISABLE
- * @return SET or RESET
- */
-STATIC INLINE void Chip_ADC_Channel_Int_Cmd(LPC_ADC_Type *pADC, uint8_t channel, FunctionalState NewState)
-{
- IP_ADC_Int_Enable(pADC, channel, NewState);
-}
-
-/**
- * @brief Enable/Disable global interrupt for ADC channel
- * @param pADC : The base of ADC peripheral on the chip
- * @param NewState : New state, ENABLE or DISABLE
- * @return Nothing
- */
-STATIC INLINE void Chip_ADC_Global_Int_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState)
-{
- IP_ADC_Int_Enable(pADC, 8, NewState);
-}
-
-/**
- * @brief Shutdown ADC
- * @param pADC : The base of ADC peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_ADC_DeInit(LPC_ADC_Type *pADC)
-{
- IP_ADC_DeInit(pADC);
-}
-
-/**
- * @brief Initialize the ADC peripheral and the ADC setup structure to default value
- * @param pADC : The base of ADC peripheral on the chip
- * @param ADCSetup : ADC setup structure to be set
- * @return Nothing
- * Default setting for ADC is 400kHz - 10bits
- */
-void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup);
-
-/**
- * @brief Select the mode starting the AD conversion
- * @param pADC : The base of ADC peripheral on the chip
- * @param mode : Stating mode, should be :
- * - ADC_NO_START : Must be set for Burst mode
- * - ADC_START_NOW : Start conversion now
- * - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15
- * - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8
- * - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
- * - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
- * - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
- * @param EdgeOption : Stating Edge Condition, should be :
- * - ADC_TRIGGERMODE_RISING : Trigger event on rising edge
- * - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge
- * @return Nothing
- */
-void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption);
-
-/**
- * @brief Set the ADC Sample rate
- * @param pADC : The base of ADC peripheral on the chip
- * @param ADCSetup : ADC setup structure to be modified
- * @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
- * @return Nothing
- */
-void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate);
-
-/**
- * @brief Set the ADC accuracy bits
- * @param pADC : The base of ADC peripheral on the chip
- * @param ADCSetup : ADC setup structure to be modified
- * @param resolution : The resolution, should be ADC_10BITS -> ADC_3BITS
- * @return Nothing
- */
-void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution);
-
-/**
- * @brief Enable or disable the ADC channel on ADC peripheral
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : Channel to be enable or disable
- * @param NewState : New state, should be:
- * - ENABLE
- * - DISABLE
- * @return Nothing
- */
-void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState);
-
-/**
- * @brief Enable burst mode
- * @param pADC : The base of ADC peripheral on the chip
- * @param NewState : New state, should be:
- * - ENABLE
- * - DISABLE
- * @return Nothing
- */
-void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState);
-
-/**
- * @brief Read the ADC value and convert it to 8bits value
- * @param pADC : The base of ADC peripheral on the chip
- * @param data : Storage for data
- * @return Status : ERROR or SUCCESS
- */
-Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data);
-
-/**
- * @brief Set a channel to be read A/D data
- * @param channel : Channel to be active
- * @return Nothing
- */
-void Chip_ADC_Active_Channel(uint8_t channel);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ADC_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c
deleted file mode 100644
index 0fe1b6cae5d6d64e3635bd541385ac2b637ab493..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * @brief LPC18xx/43xx ATimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "atimer_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize Alarm Timer */
-void Chip_ATIMER_Init(uint32_t PresetValue)
-{
- Chip_ATIMER_UpdatePresetValue(PresetValue);
- Chip_ATIMER_ClearIntStatus();
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h
deleted file mode 100644
index 230efc144fa6ca1e6834284d75a6c5967c095a35..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * @brief LPC18xx/43xx ATimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ATIMER_18XX_43XX_H_
-#define __ATIMER_18XX_43XX_H_
-
-#include "chip.h"
-
-/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx ATimer Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize Alarm Timer
- * @param PresetValue Count of 1 to 1024s for Alarm
- * @return None
- */
-void Chip_ATIMER_Init(uint32_t PresetValue);
-
-/**
- * @brief Close ATIMER device
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_DeInit(void)
-{
- IP_ATIMER_DeInit(LPC_ATIMER);
-}
-
-/**
- * @brief Enable ATIMER Interrupt
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_IntEnable(void)
-{
- IP_ATIMER_IntEnable(LPC_ATIMER);
-}
-
-/**
- * @brief Disable ATIMER Interrupt
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_IntDisable(void)
-{
- IP_ATIMER_IntDisable(LPC_ATIMER);
-}
-
-/**
- * @brief Clear ATIMER Interrupt Status
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_ClearIntStatus(void)
-{
- IP_ATIMER_ClearIntStatus(LPC_ATIMER);
-}
-
-/**
- * @brief Set ATIMER Interrupt Status
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_SetIntStatus(void)
-{
- IP_ATIMER_SetIntStatus(LPC_ATIMER);
-}
-
-/**
- * @brief Update Preset value
- * @param PresetValue : updated preset value
- * @return Nothing
- */
-STATIC INLINE void Chip_ATIMER_UpdatePresetValue(uint32_t PresetValue)
-{
- IP_ATIMER_UpdatePresetValue(LPC_ATIMER, PresetValue);
-}
-
-/**
- * @brief Read value of preset register
- * @return Value of capture register
- */
-STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(void)
-{
- return IP_ATIMER_GetPresetValue(LPC_ATIMER);
-}
-
-/**
- * @}
- */
-
- #endif /* __ATIMER_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h
deleted file mode 100644
index 0881405f3974952344bf1611d45f7401032dfc90..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * @brief CGU/CCU registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CGUCCU_18XX_43XX_H_
-#define __CGUCCU_18XX_43XX_H_
-
-#include "cmsis.h"
-#include "chip_clocks.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @ingroup CLOCK_18XX_43XX
- * @{
- */
-
-/**
- * @brief LPC18XX/43XX CGU register block structure
- */
-typedef struct { /*!< (@ 0x40050000) CGU Structure */
- __I uint32_t RESERVED0[5];
- __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */
- __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */
- __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0 (USB) status register */
- __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0 (USB) control register */
- __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0 (USB) M-divider register */
- __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
- __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0 (audio) status register */
- __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0 (audio) control register */
- __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0 (audio) M-divider register */
- __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
- __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */
- __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */
- __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */
- __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */
- __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /*!< (@ 0x4005005C) Start of base clock registers */
-} LPC_CGU_T;
-
-/**
- * @brief CCU clock config/status register pair
- */
-typedef struct {
- __IO uint32_t CFG; /*!< CCU clock configuration register */
- __I uint32_t STAT; /*!< CCU clock status register */
-} CCU_CFGSTAT_T;
-
-/**
- * @brief CCU1 register block structure
- */
-typedef struct { /*!< (@ 0x40051000) CCU1 Structure */
- __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */
- __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */
- __I uint32_t RESERVED0[62];
- CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /*!< (@ 0x40051100) Start of CCU1 clock registers */
-} LPC_CCU1_Type;
-
-/**
- * @brief CCU2 register block structure
- */
-typedef struct { /*!< (@ 0x40052000) CCU2 Structure */
- __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */
- __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */
- __I uint32_t RESERVED0[62];
- CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /*!< (@ 0x40052100) Start of CCU2 clock registers */
-} LPC_CCU2_Type;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CGUCCU_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h
deleted file mode 100644
index acbe37a68326589c554fed5e32f06f2dca330f3a..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * @brief Chip inclusion selector file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_H_
-#define __CHIP_H_
-
-#include "sys_config.h"
-
-#if defined(CHIP_LPC18XX)
-#include "chip_lpc18xx.h"
-
-#elif defined(CHIP_LPC43XX)
-#include "chip_lpc43xx.h"
-
-#else
-#error CHIP_LPC18XX or CHIP_LPC43XX must be defined
-#endif
-
-#endif /* __CHIP_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox
deleted file mode 100644
index 3af83bda0ad511544c111607812b8399c5c027e5..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * @brief LPCOpen 18xx/43xx chip group page
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-/** @defgroup CHIP_18XX_43XX_Drivers LPC18XX/43XX chip specific drivers
- * @ingroup Chip_Drivers
- * @{
- */
-
-/** @defgroup CHIP_18XX_43XX_DRIVER_OPTIONS CHIP: LPC18XX/43XX Chip driver build time options
- * Some chip drivers require build-time configuration. Using a build-time
- * configuration option allows the driver to be smaller and faster. A
- * build-time option is configured by the use of a definition passed to
- * the compiler during the build.
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h
deleted file mode 100644
index aeb51f7354ee79a0853fcb55aae878919fb6e0d3..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * @brief LPC18xx/43xx chip clock list used by CGU and CCU drivers
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_CLOCKS_H_
-#define __CHIP_CLOCKS_H_
-
-#include "sys_config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @ingroup CLOCK_18XX_43XX
- * @{
- */
-
-/**
- * @brief CGU clock input list
- * These are possible input clocks for the CGU and can come
- * from both external (crystal) and internal (PLL) sources. These
- * clock inputs can be routed to the base clocks (@ref CGU_BASE_CLK_T).
- */
-typedef enum {
- CLKIN_32K, /*!< External 32KHz input */
- CLKIN_IRC, /*!< Internal IRC (12MHz) input */
- CLKIN_ENET_RX, /*!< External ENET_RX pin input */
- CLKIN_ENET_TX, /*!< External ENET_TX pin input */
- CLKIN_CLKIN, /*!< External GPCLKIN pin input */
- CLKIN_RESERVED1,
- CLKIN_CRYSTAL, /*!< External (main) crystal pin input */
- CLKIN_USBPLL, /*!< Internal USB PLL input */
- CLKIN_AUDIOPLL, /*!< Internal Audio PLL input */
- CLKIN_MAINPLL, /*!< Internal Main PLL input */
- CLKIN_RESERVED2,
- CLKIN_RESERVED3,
- CLKIN_IDIVA, /*!< Internal divider A input */
- CLKIN_IDIVB, /*!< Internal divider B input */
- CLKIN_IDIVC, /*!< Internal divider C input */
- CLKIN_IDIVD, /*!< Internal divider D input */
- CLKIN_IDIVE, /*!< Internal divider E input */
- CLKINPUT_PD /*!< External 32KHz input */
-} CGU_CLKIN_T;
-
-/**
- * @brief CGU base clocks
- * CGU base clocks are clocks that are associated with a single input clock
- * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
- * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
- * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
- * CLK_PERIPH_SGPIO periphral clocks.
- */
-typedef enum {
- CLK_BASE_SAFE, /*!< Base clock for WDT oscillator, IRC input only */
- CLK_BASE_USB0, /*!< Base USB clock for USB0, USB PLL input only */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_PERIPH, /*!< Base clock for SGPIO */
-#else
- CLK_BASE_RESERVED1,
-#endif
- CLK_BASE_USB1, /*!< Base USB clock for USB1 */
- CLK_BASE_MX, /*!< Base clock for CPU core */
- CLK_BASE_SPIFI, /*!< Base clock for SPIFI */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_SPI, /*!< Base clock for SPI */
-#else
- CLK_BASE_RESERVED2,
-#endif
- CLK_BASE_PHY_RX, /*!< Base clock for PHY RX */
- CLK_BASE_PHY_TX, /*!< Base clock for PHY TX */
- CLK_BASE_APB1, /*!< Base clock for APB1 group */
- CLK_BASE_APB3, /*!< Base clock for APB3 group */
- CLK_BASE_LCD, /*!< Base clock for LCD pixel clock */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_VADC, /*!< Base clock for VADC */
-#else
- CLK_BASE_RESERVED3,
-#endif
- CLK_BASE_SDIO, /*!< Base clock for SDIO */
- CLK_BASE_SSP0, /*!< Base clock for SSP0 */
- CLK_BASE_SSP1, /*!< Base clock for SSP1 */
- CLK_BASE_UART0, /*!< Base clock for UART0 */
- CLK_BASE_UART1, /*!< Base clock for UART1 */
- CLK_BASE_UART2, /*!< Base clock for UART2 */
- CLK_BASE_UART3, /*!< Base clock for UART3 */
- CLK_BASE_OUT, /*!< Base clock for CLKOUT pin */
- CLK_BASE_RESERVED4,
- CLK_BASE_RESERVED5,
- CLK_BASE_RESERVED6,
- CLK_BASE_RESERVED7,
- CLK_BASE_APLL, /*!< Base clock for audio PLL */
- CLK_BASE_CGU_OUT0, /*!< Base clock for CGUOUT0 pin */
- CLK_BASE_CGU_OUT1, /*!< Base clock for CGUOUT1 pin */
- CLK_BASE_LAST,
- CLK_BASE_NONE = CLK_BASE_LAST
-} CGU_BASE_CLK_T;
-
-/**
- * @brief CGU dividers
- * CGU dividers provide an extra clock state where a specific clock can be
- * divided before being routed to a peripheral group. A divider accepts an
- * input clock and then divides it. To use the divided clock for a base clock
- * group, use the divider as the input clock for the base clock (for example,
- * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
- */
-typedef enum {
- CLK_IDIV_A, /*!< CGU clock divider A */
- CLK_IDIV_B, /*!< CGU clock divider B */
- CLK_IDIV_C, /*!< CGU clock divider A */
- CLK_IDIV_D, /*!< CGU clock divider D */
- CLK_IDIV_E, /*!< CGU clock divider E */
- CLK_IDIV_LAST
-} CGU_IDIV_T;
-
-/**
- * @brief Peripheral clocks
- * Peripheral clocks are individual clocks routed to peripherals. Although
- * multiple peripherals may share a same base clock, each peripheral's clock
- * can be enabled or disabled individually. Some peripheral clocks also have
- * additional dividers associated with them.
- */
-typedef enum {
- /* CCU1 clocks */
- CLK_APB3_BUS, /*!< APB3 bus clock from base clock CLK_BASE_APB3 */
- CLK_APB3_I2C1, /*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_DAC, /*!< DAC peripheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_ADC0, /*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_ADC1, /*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_CAN0, /*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB1_BUS = 32, /*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */
- CLK_APB1_MOTOCON, /*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_I2C0, /*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_I2S, /*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_CAN1, /*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_SPIFI = 64, /*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
- CLK_MX_BUS = 96, /*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */
- CLK_MX_SPIFI, /*!< SPIFI register clock from base clock CLK_BASE_MX */
- CLK_MX_GPIO, /*!< GPIO register clock from base clock CLK_BASE_MX */
- CLK_MX_LCD, /*!< LCD register clock from base clock CLK_BASE_MX */
- CLK_MX_ETHERNET, /*!< ETHERNET register clock from base clock CLK_BASE_MX */
- CLK_MX_USB0, /*!< USB0 register clock from base clock CLK_BASE_MX */
- CLK_MX_EMC, /*!< EMC clock from base clock CLK_BASE_MX */
- CLK_MX_SDIO, /*!< SDIO register clock from base clock CLK_BASE_MX */
- CLK_MX_DMA, /*!< DMA register clock from base clock CLK_BASE_MX */
- CLK_MX_MXCORE, /*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */
- RESERVED_ALIGN = CLK_MX_MXCORE + 3,
- CLK_MX_SCT, /*!< SCT register clock from base clock CLK_BASE_MX */
- CLK_MX_USB1, /*!< USB1 register clock from base clock CLK_BASE_MX */
- CLK_MX_EMC_DIV, /*!< ENC divider clock from base clock CLK_BASE_MX */
- CLK_MX_FLASHA, /*!< FLASHA bank clock from base clock CLK_BASE_MX */
- CLK_MX_FLASHB, /*!< FLASHB bank clock from base clock CLK_BASE_MX */
-#if defined(CHIP_LPC43XX)
- CLK_M4_M0APP, /*!< M0 app CPU core clock from base clock CLK_BASE_MX */
- CLK_MX_VADC, /*!< VADC clock from base clock CLK_BASE_MX */
-#else
- CLK_RESERVED1,
- CLK_RESERVED2,
-#endif
- CLK_MX_EEPROM, /*!< EEPROM clock from base clock CLK_BASE_MX */
- CLK_MX_WWDT = 128, /*!< WWDT register clock from base clock CLK_BASE_MX */
- CLK_MX_UART0, /*!< UART0 register clock from base clock CLK_BASE_MX */
- CLK_MX_UART1, /*!< UART1 register clock from base clock CLK_BASE_MX */
- CLK_MX_SSP0, /*!< SSP0 register clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER0, /*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER1, /*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_SCU, /*!< SCU register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_CREG, /*!< CREG clock from base clock CLK_BASE_MX */
- CLK_MX_RITIMER = 160, /*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_UART2, /*!< UART3 register clock from base clock CLK_BASE_MX */
- CLK_MX_UART3, /*!< UART4 register clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER2, /*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER3, /*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_SSP1, /*!< SSP1 register clock from base clock CLK_BASE_MX */
- CLK_MX_QEI, /*!< QEI register/perigheral clock from base clock CLK_BASE_MX */
-#if defined(CHIP_LPC43XX)
- CLK_PERIPH_BUS = 192, /*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */
- CLK_RESERVED3,
- CLK_PERIPH_CORE, /*!< Peripheral core clock from base clock CLK_BASE_PERIPH */
- CLK_PERIPH_SGPIO, /*!< SGPIO clock from base clock CLK_BASE_PERIPH */
-#else
- CLK_RESERVED3 = 192,
- CLK_RESERVED3A,
- CLK_RESERVED4,
- CLK_RESERVED5,
-#endif
- CLK_USB0 = 224, /*!< USB0 clock from base clock CLK_BASE_USB0 */
- CLK_USB1 = 256, /*!< USB1 clock from base clock CLK_BASE_USB1 */
-#if defined(CHIP_LPC43XX)
- CLK_SPI = 288, /*!< SPI clock from base clock CLK_BASE_SPI */
- CLK_VADC, /*!< VADC clock from base clock CLK_BASE_VADC */
-#else
- CLK_RESERVED7 = 320,
- CLK_RESERVED8,
-#endif
- CLK_CCU1_LAST,
-
- /* CCU2 clocks */
- CLK_CCU2_START,
- CLK_APLL = CLK_CCU2_START, /*!< Audio PLL clock from base clock CLK_BASE_APLL */
- RESERVED_ALIGNB = CLK_CCU2_START + 31,
- CLK_APB2_UART3, /*!< UART3 clock from base clock CLK_BASE_UART3 */
- RESERVED_ALIGNC = CLK_CCU2_START + 63,
- CLK_APB2_UART2, /*!< UART2 clock from base clock CLK_BASE_UART2 */
- RESERVED_ALIGND = CLK_CCU2_START + 95,
- CLK_APB0_UART1, /*!< UART1 clock from base clock CLK_BASE_UART1 */
- RESERVED_ALIGNE = CLK_CCU2_START + 127,
- CLK_APB0_UART0, /*!< UART0 clock from base clock CLK_BASE_UART0 */
- RESERVED_ALIGNF = CLK_CCU2_START + 159,
- CLK_APB2_SSP1, /*!< SSP1 clock from base clock CLK_BASE_SSP1 */
- RESERVED_ALIGNG = CLK_CCU2_START + 191,
- CLK_APB0_SSP0, /*!< SSP0 clock from base clock CLK_BASE_SSP0 */
- RESERVED_ALIGNH = CLK_CCU2_START + 223,
- CLK_APB2_SDIO, /*!< SDIO clock from base clock CLK_BASE_SDIO */
- CLK_CCU2_LAST
-} CCU_CLK_T;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_CLOCKS_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h
deleted file mode 100644
index 74ff85346c3bf18bd128dd1b244b7aef553ffd18..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * @brief LPC18xx basic chip inclusion file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_LPC18XX_H_
-#define __CHIP_LPC18XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "lpc_types.h"
-#include "sys_config.h"
-
-#ifndef CORE_M3
-#error CORE_M3 is not defined for the LPC18xx architecture
-#error CORE_M3 should be defined as part of your compiler define list
-#endif
-
-#ifndef CHIP_LPC18XX
-#error The LPC18XX Chip include path is used for this build, but
-#error CHIP_LPC18XX is not defined!
-#endif
-
-#include "adc_001.h"
-#include "atimer_001.h"
-#include "ccan_001.h"
-#include "dac_001.h"
-#include "emc_001.h"
-#include "enet_001.h"
-#include "gima_001.h"
-#include "gpdma_001.h"
-#include "gpiogrpint_001.h"
-#include "gpiopinint_001.h"
-#include "gpio_001.h"
-#include "i2c_001.h"
-#include "i2s_001.h"
-#include "lcd_001.h"
-#include "mcpwm_001.h"
-#include "pmc_001.h"
-#include "qei_001.h"
-#include "regfile_001.h"
-#include "ritimer_001.h"
-#include "rtc_001.h"
-#include "sct_001.h"
-#include "sdmmc_001.h"
-#include "ssp_001.h"
-#include "timer_001.h"
-#include "usart_001.h"
-#include "usbhs_001.h"
-#include "wwdt_001.h"
-#include "spifi_001.h"
-#include "rgu_18xx_43xx.h"
-#include "cguccu_18xx_43xx.h"
-
-/** @defgroup PERIPH_18XX_BASE CHIP: LPC18xx Peripheral addresses and register set declarations
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define LPC_SCT_BASE 0x40000000
-#define LPC_GPDMA_BASE 0x40002000
-#define LPC_SDMMC_BASE 0x40004000
-#define LPC_EMC_BASE 0x40005000
-#define LPC_USB0_BASE 0x40006000
-#define LPC_USB1_BASE 0x40007000
-#define LPC_LCD_BASE 0x40008000
-#define LPC_ETHERNET_BASE 0x40010000
-#define LPC_ATIMER_BASE 0x40040000
-#define LPC_REGFILE_BASE 0x40041000
-#define LPC_PMC_BASE 0x40042000
-#define LPC_CREG_BASE 0x40043000
-#define LPC_EVRT_BASE 0x40044000
-#define LPC_RTC_BASE 0x40046000
-#define LPC_CGU_BASE 0x40050000
-#define LPC_CCU1_BASE 0x40051000
-#define LPC_CCU2_BASE 0x40052000
-#define LPC_RGU_BASE 0x40053000
-#define LPC_WWDT_BASE 0x40080000
-#define LPC_USART0_BASE 0x40081000
-#define LPC_USART2_BASE 0x400C1000
-#define LPC_USART3_BASE 0x400C2000
-#define LPC_UART1_BASE 0x40082000
-#define LPC_SSP0_BASE 0x40083000
-#define LPC_SSP1_BASE 0x400C5000
-#define LPC_TIMER0_BASE 0x40084000
-#define LPC_TIMER1_BASE 0x40085000
-#define LPC_TIMER2_BASE 0x400C3000
-#define LPC_TIMER3_BASE 0x400C4000
-#define LPC_SCU_BASE 0x40086000
-#define LPC_GPIO_PIN_INT_BASE 0x40087000
-#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
-#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
-#define LPC_MCPWM_BASE 0x400A0000
-#define LPC_I2C0_BASE 0x400A1000
-#define LPC_I2C1_BASE 0x400E0000
-#define LPC_I2S0_BASE 0x400A2000
-#define LPC_I2S1_BASE 0x400A3000
-#define LPC_C_CAN1_BASE 0x400A4000
-#define LPC_RITIMER_BASE 0x400C0000
-#define LPC_QEI_BASE 0x400C6000
-#define LPC_GIMA_BASE 0x400C7000
-#define LPC_DAC_BASE 0x400E1000
-#define LPC_C_CAN0_BASE 0x400E2000
-#define LPC_ADC0_BASE 0x400E3000
-#define LPC_ADC1_BASE 0x400E4000
-#define LPC_GPIO_PORT_BASE 0x400F4000
-#define LPC_SPI_BASE 0x40100000
-#define LPC_SGPIO_BASE 0x40101000
-
-/* Normalize types */
-typedef IP_SCT_001_Type LPC_SCT_Type;
-typedef IP_GPDMA_001_Type LPC_GPDMA_Type;
-typedef IP_SDMMC_001_Type LPC_SDMMC_Type;
-typedef IP_EMC_001_Type LPC_EMC_Type;
-typedef IP_USBHS_001_Type LPC_USBHS_Type;
-typedef IP_ENET_001_Type LPC_ENET_Type;
-typedef IP_ATIMER_001_Type LPC_ATIMER_Type;
-typedef IP_REGFILE_001_T LPC_REGFILE_T;
-typedef IP_PMC_001_Type LPC_PMC_Type;
-typedef IP_RTC_001_T LPC_RTC_Type;
-typedef IP_WWDT_001_Type LPC_WWDT_Type;
-typedef IP_USART_001_Type LPC_USART_Type;
-typedef IP_SSP_001_Type LPC_SSP_Type;
-typedef IP_TIMER_001_Type LPC_TIMER_Type;
-typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type;
-typedef IP_MCPWM_001_Type LPC_MCPWM_Type;
-typedef IP_I2C_001_Type LPC_I2C_Type;
-typedef IP_I2S_001_Type LPC_I2S_Type;
-typedef IP_CCAN_001_Type LPC_CCAN_Type;
-typedef IP_RITIMER_001_Type LPC_RITIMER_Type;
-typedef IP_QEI_001_Type LPC_QEI_Type;
-typedef IP_GIMA_001_Type LPC_GIMA_Type;
-typedef IP_DAC_001_Type LPC_DAC_Type;
-typedef IP_ADC_001_Type LPC_ADC_Type;
-typedef IP_GPIO_001_Type LPC_GPIO_Type;
-typedef IP_LCD_001_Type LPC_LCD_Type;
-
-#define LPC_SCT ((IP_SCT_001_Type *) LPC_SCT_BASE)
-#define LPC_GPDMA ((IP_GPDMA_001_Type *) LPC_GPDMA_BASE)
-#define LPC_SDMMC ((IP_SDMMC_001_Type *) LPC_SDMMC_BASE)
-#define LPC_EMC ((IP_EMC_001_Type *) LPC_EMC_BASE)
-#define LPC_USB0 ((IP_USBHS_001_Type *) LPC_USB0_BASE)
-#define LPC_USB1 ((IP_USBHS_001_Type *) LPC_USB1_BASE)
-#define LPC_LCD ((IP_LCD_001_Type *) LPC_LCD_BASE)
-#define LPC_ETHERNET ((IP_ENET_001_Type *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER ((IP_ATIMER_001_Type *) LPC_ATIMER_BASE)
-#define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE)
-#define LPC_PMC ((IP_PMC_001_Type *) LPC_PMC_BASE)
-#define LPC_EVRT ((LPC_EVRT_Type *) LPC_EVRT_BASE)
-#define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE)
-#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
-#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE)
-#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE)
-#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
-#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
-#define LPC_WWDT ((IP_WWDT_001_Type *) LPC_WWDT_BASE)
-#define LPC_USART0 ((IP_USART_001_Type *) LPC_USART0_BASE)
-#define LPC_USART2 ((IP_USART_001_Type *) LPC_USART2_BASE)
-#define LPC_USART3 ((IP_USART_001_Type *) LPC_USART3_BASE)
-#define LPC_UART1 ((IP_USART_001_Type *) LPC_UART1_BASE)
-#define LPC_SSP0 ((IP_SSP_001_Type *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((IP_SSP_001_Type *) LPC_SSP1_BASE)
-#define LPC_TIMER0 ((IP_TIMER_001_Type *) LPC_TIMER0_BASE)
-#define LPC_TIMER1 ((IP_TIMER_001_Type *) LPC_TIMER1_BASE)
-#define LPC_TIMER2 ((IP_TIMER_001_Type *) LPC_TIMER2_BASE)
-#define LPC_TIMER3 ((IP_TIMER_001_Type *) LPC_TIMER3_BASE)
-#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_Type *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_Type *) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_Type *) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM ((IP_MCPWM_001_Type *) LPC_MCPWM_BASE)
-#define LPC_I2C0 ((IP_I2C_001_Type *) LPC_I2C0_BASE)
-#define LPC_I2C1 ((IP_I2C_001_Type *) LPC_I2C1_BASE)
-#define LPC_I2S0 ((IP_I2S_001_Type *) LPC_I2S0_BASE)
-#define LPC_I2S1 ((IP_I2S_001_Type *) LPC_I2S1_BASE)
-#define LPC_C_CAN1 ((IP_CCAN_001_Type *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER ((IP_RITIMER_001_Type *) LPC_RITIMER_BASE)
-#define LPC_QEI ((IP_QEI_001_Type *) LPC_QEI_BASE)
-#define LPC_GIMA ((IP_GIMA_001_Type *) LPC_GIMA_BASE)
-#define LPC_DAC ((IP_DAC_001_Type *) LPC_DAC_BASE)
-#define LPC_C_CAN0 ((IP_CCAN_001_Type *) LPC_C_CAN0_BASE)
-#define LPC_ADC0 ((IP_ADC_001_Type *) LPC_ADC0_BASE)
-#define LPC_ADC1 ((IP_ADC_001_Type *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT ((IP_GPIO_001_Type *) LPC_GPIO_PORT_BASE)
-
-/**
- * @}
- */
-
-#include "clock_18xx_43xx.h"
-#include "gpio_18xx_43xx.h"
-#include "uart_18xx_43xx.h"
-#include "gpdma_18xx_43xx.h"
-#include "enet_18xx_43xx.h"
-#include "i2c_18xx_43xx.h"
-#include "i2s_18xx_43xx.h"
-#include "ssp_18xx_43xx.h"
-#include "rtc_18xx_43xx.h"
-#include "evrt_18xx_43xx.h"
-#include "atimer_18xx_43xx.h"
-#include "wwdt_18xx_43xx.h"
-#include "ritimer_18xx_43xx.h"
-#include "emc_18xx_43xx.h"
-#include "lcd_18xx_43xx.h"
-#include "adc_18xx_43xx.h"
-#include "sdmmc_18xx_43xx.h"
-#include "timer_18xx_43xx.h"
-#include "creg_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_LPC18XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h
deleted file mode 100644
index 757d7bb0a139379b256ab612a4371d187d34aab5..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * @brief LPC43xx basic chip inclusion file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_LPC43XX_H_
-#define __CHIP_LPC43XX_H_
-
-#include "lpc_types.h"
-#include "sys_config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(CORE_M4) && !defined(CORE_M0)
-#error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture
-#error CORE_M4 or CORE_M0 should be defined as part of your compiler define list
-#endif
-
-#ifndef CHIP_LPC43XX
-#error The LPC43XX Chip include path is used for this build, but
-#error CHIP_LPC43XX is not defined!
-#endif
-
-#include "adc_001.h"
-#include "atimer_001.h"
-#include "ccan_001.h"
-#include "dac_001.h"
-#include "emc_001.h"
-#include "enet_001.h"
-#include "gima_001.h"
-#include "gpdma_001.h"
-#include "gpiogrpint_001.h"
-#include "gpiopinint_001.h"
-#include "gpio_001.h"
-#include "i2c_001.h"
-#include "i2s_001.h"
-#include "lcd_001.h"
-#include "mcpwm_001.h"
-#include "pmc_001.h"
-#include "qei_001.h"
-#include "regfile_001.h"
-#include "ritimer_001.h"
-#include "rtc_001.h"
-#include "sct_001.h"
-#include "sdmmc_001.h"
-#include "sgpio_001.h"
-#include "spi_001.h"
-#include "ssp_001.h"
-#include "timer_001.h"
-#include "usart_001.h"
-#include "usbhs_001.h"
-#include "wwdt_001.h"
-#include "spifi_001.h"
-#include "rgu_18xx_43xx.h"
-#include "cguccu_18xx_43xx.h"
-
-/** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define LPC_SCT_BASE 0x40000000
-#define LPC_GPDMA_BASE 0x40002000
-#define LPC_SDMMC_BASE 0x40004000
-#define LPC_EMC_BASE 0x40005000
-#define LPC_USB0_BASE 0x40006000
-#define LPC_USB1_BASE 0x40007000
-#define LPC_LCD_BASE 0x40008000
-#define LPC_ETHERNET_BASE 0x40010000
-#define LPC_ATIMER_BASE 0x40040000
-#define LPC_REGFILE_BASE 0x40041000
-#define LPC_PMC_BASE 0x40042000
-#define LPC_CREG_BASE 0x40043000
-#define LPC_EVRT_BASE 0x40044000
-#define LPC_RTC_BASE 0x40046000
-#define LPC_CGU_BASE 0x40050000
-#define LPC_CCU1_BASE 0x40051000
-#define LPC_CCU2_BASE 0x40052000
-#define LPC_RGU_BASE 0x40053000
-#define LPC_WWDT_BASE 0x40080000
-#define LPC_USART0_BASE 0x40081000
-#define LPC_USART2_BASE 0x400C1000
-#define LPC_USART3_BASE 0x400C2000
-#define LPC_UART1_BASE 0x40082000
-#define LPC_SSP0_BASE 0x40083000
-#define LPC_SSP1_BASE 0x400C5000
-#define LPC_TIMER0_BASE 0x40084000
-#define LPC_TIMER1_BASE 0x40085000
-#define LPC_TIMER2_BASE 0x400C3000
-#define LPC_TIMER3_BASE 0x400C4000
-#define LPC_SCU_BASE 0x40086000
-#define LPC_GPIO_PIN_INT_BASE 0x40087000
-#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
-#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
-#define LPC_MCPWM_BASE 0x400A0000
-#define LPC_I2C0_BASE 0x400A1000
-#define LPC_I2C1_BASE 0x400E0000
-#define LPC_I2S0_BASE 0x400A2000
-#define LPC_I2S1_BASE 0x400A3000
-#define LPC_C_CAN1_BASE 0x400A4000
-#define LPC_RITIMER_BASE 0x400C0000
-#define LPC_QEI_BASE 0x400C6000
-#define LPC_GIMA_BASE 0x400C7000
-#define LPC_DAC_BASE 0x400E1000
-#define LPC_C_CAN0_BASE 0x400E2000
-#define LPC_ADC0_BASE 0x400E3000
-#define LPC_ADC1_BASE 0x400E4000
-#define LPC_GPIO_PORT_BASE 0x400F4000
-#define LPC_SPI_BASE 0x40100000
-#define LPC_SGPIO_BASE 0x40101000
-
-/* Normalize types */
-typedef IP_SCT_001_Type LPC_SCT_Type;
-typedef IP_GPDMA_001_Type LPC_GPDMA_Type;
-typedef IP_SDMMC_001_Type LPC_SDMMC_Type;
-typedef IP_EMC_001_Type LPC_EMC_Type;
-typedef IP_USBHS_001_Type LPC_USBHS_Type;
-typedef IP_ENET_001_Type LPC_ENET_Type;
-typedef IP_ATIMER_001_Type LPC_ATIMER_Type;
-typedef IP_REGFILE_001_T LPC_REGFILE_Type;
-typedef IP_PMC_001_Type LPC_PMC_Type;
-typedef IP_RTC_001_T LPC_RTC_Type;
-typedef IP_WWDT_001_Type LPC_WWDT_Type;
-typedef IP_USART_001_Type LPC_USART_Type;
-typedef IP_SSP_001_Type LPC_SSP_Type;
-typedef IP_TIMER_001_Type LPC_TIMER_Type;
-typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type;
-typedef IP_MCPWM_001_Type LPC_MCPWM_Type;
-typedef IP_I2C_001_Type LPC_I2C_Type;
-typedef IP_I2S_001_Type LPC_I2S_Type;
-typedef IP_CCAN_001_Type LPC_CCAN_Type;
-typedef IP_RITIMER_001_Type LPC_RITIMER_Type;
-typedef IP_QEI_001_Type LPC_QEI_Type;
-typedef IP_GIMA_001_Type LPC_GIMA_Type;
-typedef IP_DAC_001_Type LPC_DAC_Type;
-typedef IP_ADC_001_Type LPC_ADC_Type;
-typedef IP_GPIO_001_Type LPC_GPIO_Type;
-typedef IP_SPI_001_Type LPC_SPI_Type;
-typedef IP_SGPIO_001_Type LPC_SGPIO_Type;
-typedef IP_LCD_001_Type LPC_LCD_Type;
-
-#define LPC_SCT ((IP_SCT_001_Type *) LPC_SCT_BASE)
-#define LPC_GPDMA ((IP_GPDMA_001_Type *) LPC_GPDMA_BASE)
-#define LPC_SDMMC ((IP_SDMMC_001_Type *) LPC_SDMMC_BASE)
-#define LPC_EMC ((IP_EMC_001_Type *) LPC_EMC_BASE)
-#define LPC_USB0 ((IP_USBHS_001_Type *) LPC_USB0_BASE)
-#define LPC_USB1 ((IP_USBHS_001_Type *) LPC_USB1_BASE)
-#define LPC_LCD ((IP_LCD_001_Type *) LPC_LCD_BASE)
-#define LPC_ETHERNET ((IP_ENET_001_Type *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER ((IP_ATIMER_001_Type *) LPC_ATIMER_BASE)
-#define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE)
-#define LPC_PMC ((IP_PMC_001_Type *) LPC_PMC_BASE)
-#define LPC_EVRT ((LPC_EVRT_Type *) LPC_EVRT_BASE)
-#define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE)
-#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
-#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE)
-#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE)
-#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
-#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
-#define LPC_WWDT ((IP_WWDT_001_Type *) LPC_WWDT_BASE)
-#define LPC_USART0 ((IP_USART_001_Type *) LPC_USART0_BASE)
-#define LPC_USART2 ((IP_USART_001_Type *) LPC_USART2_BASE)
-#define LPC_USART3 ((IP_USART_001_Type *) LPC_USART3_BASE)
-#define LPC_UART1 ((IP_USART_001_Type *) LPC_UART1_BASE)
-#define LPC_SSP0 ((IP_SSP_001_Type *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((IP_SSP_001_Type *) LPC_SSP1_BASE)
-#define LPC_TIMER0 ((IP_TIMER_001_Type *) LPC_TIMER0_BASE)
-#define LPC_TIMER1 ((IP_TIMER_001_Type *) LPC_TIMER1_BASE)
-#define LPC_TIMER2 ((IP_TIMER_001_Type *) LPC_TIMER2_BASE)
-#define LPC_TIMER3 ((IP_TIMER_001_Type *) LPC_TIMER3_BASE)
-#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_Type *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_Type *) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_Type *) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM ((IP_MCPWM_001_Type *) LPC_MCPWM_BASE)
-#define LPC_I2C0 ((IP_I2C_001_Type *) LPC_I2C0_BASE)
-#define LPC_I2C1 ((IP_I2C_001_Type *) LPC_I2C1_BASE)
-#define LPC_I2S0 ((IP_I2S_001_Type *) LPC_I2S0_BASE)
-#define LPC_I2S1 ((IP_I2S_001_Type *) LPC_I2S1_BASE)
-#define LPC_C_CAN1 ((IP_CCAN_001_Type *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER ((IP_RITIMER_001_Type *) LPC_RITIMER_BASE)
-#define LPC_QEI ((IP_QEI_001_Type *) LPC_QEI_BASE)
-#define LPC_GIMA ((IP_GIMA_001_Type *) LPC_GIMA_BASE)
-#define LPC_DAC ((IP_DAC_001_Type *) LPC_DAC_BASE)
-#define LPC_C_CAN0 ((IP_CCAN_001_Type *) LPC_C_CAN0_BASE)
-#define LPC_ADC0 ((IP_ADC_001_Type *) LPC_ADC0_BASE)
-#define LPC_ADC1 ((IP_ADC_001_Type *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT ((IP_GPIO_001_Type *) LPC_GPIO_PORT_BASE)
-#define LPC_SPI ((IP_SPI_001_Type *) LPC_SPI_BASE)
-#define LPC_SGPIO ((IP_SGPIO_001_Type *) LPC_SGPIO_BASE)
-
-/**
- * @}
- */
-
-#include "clock_18xx_43xx.h"
-#include "gpio_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-#include "uart_18xx_43xx.h"
-#include "gpdma_18xx_43xx.h"
-#include "enet_18xx_43xx.h"
-#include "rgu_18xx_43xx.h"
-#include "i2c_18xx_43xx.h"
-#include "i2s_18xx_43xx.h"
-#include "ssp_18xx_43xx.h"
-#include "rtc_18xx_43xx.h"
-#include "evrt_18xx_43xx.h"
-#include "atimer_18xx_43xx.h"
-#include "wwdt_18xx_43xx.h"
-#include "ritimer_18xx_43xx.h"
-#include "emc_18xx_43xx.h"
-#include "lcd_18xx_43xx.h"
-#include "adc_18xx_43xx.h"
-#include "timer_18xx_43xx.h"
-#include "sdmmc_18xx_43xx.h"
-#include "fpu_init.h"
-#include "creg_18xx_43xx.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_LPC43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c
deleted file mode 100644
index 9f9a58930de63a35229c57e11c0cfb17df55173b..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*
- * @brief LPC18xx/43xx clock driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licenser disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "clock_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Maps a peripheral clock to it's base clock */
-typedef struct {
- CCU_CLK_T clkstart;
- CCU_CLK_T clkend;
- CGU_BASE_CLK_T clkbase;
-} CLK_PERIPH_TO_BASE_T;
-static const CLK_PERIPH_TO_BASE_T periph_to_base[] = {
- {CLK_APB3_BUS, CLK_APB3_CAN0, CLK_BASE_APB3},
- {CLK_APB1_BUS, CLK_APB1_CAN1, CLK_BASE_APB1},
- {CLK_SPIFI, CLK_SPIFI, CLK_BASE_SPIFI},
- {CLK_MX_BUS, CLK_MX_QEI, CLK_BASE_MX},
-#if 0
-#if defined(CHIP_LPC43XX)
- {CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH},
-#endif
- {CLK_USB0, CLK_USB0, CLK_BASE_USB0},
- {CLK_USB1, CLK_USB1, CLK_BASE_USB1},
-#if defined(CHIP_LPC43XX)
- {CLK_SPI, CLK_SPI, CLK_BASE_SPI},
- {CLK_VADC, CLK_VADC, CLK_BASE_VADC},
-#endif
- {CLK_APLL, CLK_APLL, CLK_BASE_APLL},
- {CLK_APB2_UART3, CLK_APB2_UART3, CLK_BASE_UART3},
- {CLK_APB2_UART2, CLK_APB2_UART2, CLK_BASE_UART2},
- {CLK_APB2_UART1, CLK_APB2_UART1, CLK_BASE_UART1},
- {CLK_APB2_UART0, CLK_APB2_UART0, CLK_BASE_UART0},
- {CLK_APB2_SSP1, CLK_APB2_SSP1, CLK_BASE_SSP1},
- {CLK_APB2_SSP0, CLK_APB2_SSP0, CLK_BASE_SSP0},
- {CLK_APB2_SDIO, CLK_APB2_SDIO, CLK_BASE_SDIO},
- {CLK_CCU2_LAST, CLK_CCU2_LAST, CLK_BASE_NONE}
-#endif
-};
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Test PLL input values for a specific frequency range */
-static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t TestMult, uint32_t MinHz, uint32_t MaxHz)
-{
- uint32_t TestHz = TestMult * InputHz;
-
- if ((TestHz < MinHz) || (TestHz > MAX_CLOCK_FREQ) || (TestHz > MaxHz)) {
- TestHz = 0;
- }
-
- return TestHz;
-}
-
-/* Returns clock rate out of a divider */
-static uint32_t Chip_Clock_GetDivRate(CGU_CLKIN_T clock, CGU_IDIV_T divider)
-{
- CGU_CLKIN_T input;
- uint32_t div;
-
- input = Chip_Clock_GetDividerSource(divider);
- div = Chip_Clock_GetDividerDivisor(divider);
- return Chip_Clock_GetClockInputHz(input) / (div + 1);
-}
-
-/* Finds the base clock for the peripheral clock */
-static CGU_BASE_CLK_T Chip_Clock_FindBseClock(CCU_CLK_T clk)
-{
- CGU_BASE_CLK_T baseclk = CLK_BASE_NONE;
- int i = 0;
-
- while ((baseclk == CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) {
- if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) {
- baseclk = periph_to_base[i].clkbase;
- }
- else {
- i++;
- }
- }
-
- return baseclk;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Enables the crystal oscillator */
-void Chip_Clock_EnableCrystal(void)
-{
- uint32_t OldCrystalConfig = LPC_CGU->XTAL_OSC_CTRL;
-
- /* Clear bypass mode */
- OldCrystalConfig &= (~2);
- if (OldCrystalConfig != LPC_CGU->XTAL_OSC_CTRL) {
- LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
- }
-
- /* Enable crystal oscillator */
- OldCrystalConfig &= (~1);
- if (CRYSTAL_MAIN_FREQ_IN >= 20000000) {
- OldCrystalConfig |= 4; /* Set high frequency mode */
-
- }
- LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
-}
-
-/* Disables the crystal oscillator */
-void IP_Clock_DisableCrystal(void)
-{
- /* Disable crystal oscillator */
- LPC_CGU->XTAL_OSC_CTRL &= (~1);
-}
-
-/* Configures the main PLL */
-uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz)
-{
- uint32_t freqin = Chip_Clock_GetClockInputHz(Input);
- uint32_t Mult, LastMult, MultEnd;
- uint32_t freqout, freqout2;
-
- if (DesiredHz != 0xFFFFFFFF) {
- /* Test DesiredHz rounded down */
- Mult = DesiredHz / freqin;
- freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
- /* Test DesiredHz rounded up */
- Mult++;
- freqout2 = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
- if (freqout && !freqout2) { /* rounding up is no good? set first multiplier */
- Mult--;
- return Chip_Clock_SetupMainPLLMult(Input, Mult);
- }
- if (!freqout && freqout2) { /* didn't work until rounded up? set 2nd multiplier */
- return Chip_Clock_SetupMainPLLMult(Input, Mult);
- }
-
- if (freqout && freqout2) { /* either multiplier okay? choose closer one */
- if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) {
- Mult--;
- return Chip_Clock_SetupMainPLLMult(Input, Mult);
- }
- else {
- return Chip_Clock_SetupMainPLLMult(Input, Mult);
- }
- }
- }
-
- /* Neither multiplier okay? Try to start at MinHz and increment.
- This should find the highest multiplier that is still good */
- Mult = MinHz / freqin;
- MultEnd = MaxHz / freqin;
- LastMult = 0;
- while (1) {
- freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
- if (freqout) {
- LastMult = Mult;
- }
-
- if (Mult >= MultEnd) {
- break;
- }
- Mult++;
- }
-
- if (LastMult) {
- return Chip_Clock_SetupMainPLLMult(Input, LastMult);
- }
-
- return 0;
-}
-
-/* Directly set the PLL multipler */
-uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult)
-{
- uint32_t freq = Chip_Clock_GetClockInputHz(Input);
- uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;
- uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
-
- freq *= mult;
- msel = mult - 1;
-
- PLLReg &= ~(0x1F << 24);/* clear input source bits */
- PLLReg |= Input << 24; /* set input source bits to parameter */
-
- /* Clear other PLL input bits */
- PLLReg &= ~((1 << 6) | /* FBSEL */
- (1 << 1) | /* BYPASS */
- (1 << 7) | /* DIRECT */
- (0x03 << 8) | (0xFF << 16) | (0x03 << 12)); /* PSEL, MSEL, NSEL- divider ratios */
-
- if (freq < 156000000) {
- /* psel is encoded such that 0=1, 1=2, 2=4, 3=8 */
- while ((2 * (pval) * freq) < 156000000) {
- psel++;
- pval *= 2;
- }
-
- PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6); /* dividers + FBSEL */
- }
- else if (freq < 320000000) {
- PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6); /* dividers + DIRECT + FBSEL */
- }
- else {
- Chip_Clock_DisableMainPLL();
- return 0;
- }
- LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0);
-
- return freq;
-}
-
-/* Returns the frequency of the main PLL */
-uint32_t Chip_Clock_GetMainPLLHz(void)
-{
- uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
- uint32_t freq = Chip_Clock_GetClockInputHz((CGU_CLKIN_T) ((PLLReg >> 24) & 0xF));
- uint32_t msel, nsel, psel, direct, fbsel;
- uint32_t m, n, p;
- const uint8_t ptab[] = {1, 2, 4, 8};
-
- /* No lock? */
- if (!(LPC_CGU->PLL1_STAT & 1)) {
- return 0;
- }
-
- msel = (PLLReg >> 16) & 0xFF;
- nsel = (PLLReg >> 12) & 0x3;
- psel = (PLLReg >> 8) & 0x3;
- direct = (PLLReg >> 7) & 0x1;
- fbsel = (PLLReg >> 6) & 0x1;
-
- m = msel + 1;
- n = nsel + 1;
- p = ptab[psel];
-
- if (direct || fbsel) {
- return m * (freq / n);
- }
-
- return (m / (2 * p)) * (freq / n);
-}
-
-/* Disables the main PLL */
-void Chip_Clock_DisableMainPLL(void)
-{
- /* power down main PLL */
- LPC_CGU->PLL1_CTRL |= 1;
-}
-
-/* Returns the lock status of the main PLL */
-bool Chip_Clock_MainPLLLocked(void)
-{
- /* Return true if locked */
- return (bool) (LPC_CGU->PLL1_STAT & 1);
-}
-
-/* Sets up a CGU clock divider and it's input clock */
-void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor)
-{
- uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];
-
- Divisor--;
-
- if (Input != CLKINPUT_PD) {
- /* Mask off bits that need to changes */
- reg &= ~((0x1F << 24) | 1 | (0xF << 2));
-
- /* Enable autoblocking, clear PD, and set clock source & divisor */
- LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2);
- }
- else {
- LPC_CGU->IDIV_CTRL[Divider] = reg | 1; /* Power down this divider */
- }
-}
-
-/* Gets a CGU clock divider source */
-CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider)
-{
- uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];
-
- if (reg & 1) { /* divider is powered down */
- return CLKINPUT_PD;
- }
-
- return (CGU_CLKIN_T) ((reg >> 24) & 0x1F);
-}
-
-/* Gets a CGU clock divider divisor */
-uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider)
-{
- return (CGU_CLKIN_T) ((LPC_CGU->IDIV_CTRL[Divider] >> 2) & 0xF);
-}
-
-/* Returns the frequency of the specified input clock source */
-uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input)
-{
- uint32_t rate = 0;
-
- switch (input) {
- case CLKIN_32K:
- rate = CRYSTAL_32K_FREQ_IN;
- break;
-
- case CLKIN_IRC:
- rate = CGU_IRC_FREQ;
- break;
-
- case CLKIN_ENET_RX:
-#if defined(USE_RMII)
- /* In RMII mode, this clock is not attached */
-#else
- /* MII mode requires 25MHz clock */
- rate = 25000000;
-#endif
- break;
-
- case CLKIN_ENET_TX:
-#if defined(USE_RMII)
- /* MII mode requires 50MHz clock */
- rate = 50000000;
-#else
- /* MII mode requires 25MHz clock */
- rate = 25000000;
-#endif
- break;
-
- case CLKIN_CLKIN:
-#if defined(EXTERNAL_CLKIN_FREQ_IN)
- rate = EXTERNAL_CLKIN_FREQ_IN;
-#else
- /* Assume no clock in if a rate wasn't defined */
-#endif
- break;
-
- case CLKIN_CRYSTAL:
- rate = CRYSTAL_MAIN_FREQ_IN;
- break;
-
- case CLKIN_USBPLL:
- rate = 0; // FIXME
- break;
-
- case CLKIN_AUDIOPLL:
- rate = 0; // FIXME
- break;
-
- case CLKIN_MAINPLL:
- rate = Chip_Clock_GetMainPLLHz();
- break;
-
- case CLKIN_IDIVA:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_A);
- break;
-
- case CLKIN_IDIVB:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_B);
- break;
-
- case CLKIN_IDIVC:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_C);
- break;
-
- case CLKIN_IDIVD:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_D);
- break;
-
- case CLKIN_IDIVE:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_E);
- break;
-
- case CLKINPUT_PD:
- rate = 0;
- break;
-
- default:
- break;
- }
-
- return rate;
-}
-
-/* Returns the frequency of the specified base clock source */
-uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock)
-{
- return Chip_Clock_GetClockInputHz(Chip_Clock_GetBaseClock(clock));
-}
-
-/* Sets a CGU Base Clock clock source */
-void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn)
-{
- uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];
-
- if (BaseClock < CLK_BASE_NONE) {
- if (Input != CLKINPUT_PD) {
- /* Mask off fields we plan to update */
- reg &= ~((0x1F << 24) | 1 | (1 << 11));
-
- if (autoblocken) {
- reg |= (1 << 11);
- }
- if (powerdn) {
- reg |= (1 << 0);
- }
-
- /* Set clock source */
- reg |= (Input << 24);
-
- LPC_CGU->BASE_CLK[BaseClock] = reg;
- }
- }
- else {
- LPC_CGU->BASE_CLK[BaseClock] = reg | 1; /* Power down this base clock */
- }
-}
-
-/*Enables a base clock source */
-void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock)
-{
- if (BaseClock < CLK_BASE_NONE) {
- LPC_CGU->BASE_CLK[BaseClock] &= ~1;
- }
-}
-
-/* Disables a base clock source */
-void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock)
-{
- if (BaseClock < CLK_BASE_NONE) {
- LPC_CGU->BASE_CLK[BaseClock] |= 1;
- }
-}
-
-/* Gets a CGU Base Clock clock source */
-CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock)
-{
- uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];
-
- if (BaseClock >= CLK_BASE_NONE) {
- return CLKINPUT_PD;
- }
-
- /* base clock is powered down? */
- if (reg & 1) {
- return CLKINPUT_PD;
- }
-
- return (CGU_CLKIN_T) ((reg >> 24) & 0x1F);
-}
-
-/* Enables a peripheral clock and sets clock states */
-void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div)
-{
- uint32_t reg = 1;
-
- if (autoen) {
- reg |= (1 << 1);
- }
- if (wakeupen) {
- reg |= (1 << 2);
- }
-
- /* Not all clocks support a divider, but we won't check that here. Only
- dividers of 1 and 2 are allowed. Assume 1 if not 2 */
- if (div == 2) {
- reg |= (1 << 5);
- }
-
- /* Setup peripheral clock and start running */
- if (clk >= CLK_CCU2_START) {
- LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG = reg;
- }
- else {
- LPC_CCU1->CLKCCU[clk].CFG = reg;
- }
-}
-
-/* Enables a peripheral clock */
-void Chip_Clock_Enable(CCU_CLK_T clk)
-{
- /* Start peripheral clock running */
- if (clk >= CLK_CCU2_START) {
- LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG |= 1;
- }
- else {
- LPC_CCU1->CLKCCU[clk].CFG |= 1;
- }
-}
-
-/* Disables a peripheral clock */
-void Chip_Clock_Disable(CCU_CLK_T clk)
-{
- /* Stop peripheral clock */
- if (clk >= CLK_CCU2_START) {
- LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG &= ~1;
- }
- else {
- LPC_CCU1->CLKCCU[clk].CFG &= ~1;
- }
-}
-
-/* Returns a peripheral clock rate */
-uint32_t Chip_Clock_GetRate(CCU_CLK_T clk)
-{
- CGU_BASE_CLK_T baseclk;
- uint32_t reg, div, rate;
-
- /* Get CCU config register for clock */
- if (clk >= CLK_CCU2_START) {
- reg = LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG;
- }
- else {
- reg = LPC_CCU1->CLKCCU[clk].CFG;
- }
-
- /* Is the clock enabled? */
- if (reg & 1) {
- /* Get base clock for this peripheral clock */
- baseclk = Chip_Clock_FindBseClock(clk);
-
- /* Get base clock rate */
- rate = Chip_Clock_GetBaseClocktHz(baseclk);
-
- /* Get divider for this clock */
- if (((reg >> 5) & 0x7) == 0) {
- div = 1;
- }
- else {
- div = 2;/* No other dividers supported */
-
- }
- rate = rate / div;
- }
- else {
- rate = 0;
- }
-
- return rate;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h
deleted file mode 100644
index a8f1f8680d8b2fac64d80e0050a2fe62e6e4ae95..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * @brief LPC18xx/43xx clock driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licenser disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CLOCK_18XX_43XX_H_
-#define __CLOCK_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CLOCK_18XX_43XX CHIP: LPC18xx/43xx Clock Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** @defgroup CLOCK_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Clock Driver driver options
- * @ingroup CLOCK_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS
- * The clock driver has options that configure it's operation at build-time.
- * MAX_CLOCK_FREQ:
- * - This define, when set, identifies the maximumCPU clock rate of the system (change this to alter running CPU speed)
- * - When this is not defined, The maximum clock rate for the CPU is used
- *
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
- * @{
- */
-
-/**
- * @}
- */
-
-/* Internal oscillator frequency */
-#define CGU_IRC_FREQ (12000000)
-
-#ifndef MAX_CLOCK_FREQ
-#if defined(CHIP_LPC43XX)
-#define MAX_CLOCK_FREQ (204000000)
-#else
-#define MAX_CLOCK_FREQ (180000000)
-#endif
-#endif /* MAX_CLOCK_FREQ */
-
-/**
- * @brief Enables the crystal oscillator
- * @return Nothing
- */
-void Chip_Clock_EnableCrystal(void);
-
-/**
- * @brief Disables the crystal oscillator
- * @return Nothing
- */
-void Chip_Clock_DisableCrystal(void);
-
-/**
- * @brief Configures the main PLL
- * @param Input : Which clock input to use as the PLL input
- * @param MinHz : Minimum allowable PLL output frequency
- * @param DesiredHz : Desired PLL output frequency
- * @param MaxHz : Maximum allowable PLL output frequency
- * @return Frequency of the PLL in Hz
- * Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz
- * and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if
- * the PLL is locked.
- */
-uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);
-
-/**
- * @brief Directly set the PLL multipler
- * @param Input : Which clock input to use as the PLL input
- * @param mult : How many times to multiply the input clock
- * @return Frequency of the PLL in Hz
- */
-uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult);
-
-/**
- * @brief Returns the frequency of the main PLL
- * @return Frequency of the PLL in Hz
- * Returns zero if the main PLL is not running.
- */
-uint32_t Chip_Clock_GetMainPLLHz(void);
-
-/**
- * @brief Disables the main PLL
- * @return none
- * Make sure the main PLL is not needed to clock the part before disabling it.
- * Saves power if the main PLL is not needed.
- */
-void Chip_Clock_DisableMainPLL(void);
-
-/**
- * @brief Returns the lock status of the main PLL
- * @return true if the PLL is locked, otherwise false
- * The main PLL should be locked prior to using it as a clock input for a base clock.
- */
-bool Chip_Clock_MainPLLLocked(void);
-
-/**
- * @brief Sets up a CGU clock divider and it's input clock
- * @param Divider : CGU_IDIV_T value indicating which divider to configure
- * @param Input : CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider
- * @param Divisor : value to divide Input clock by
- * @return Nothing
- */
-void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor);
-
-/**
- * @brief Gets a CGU clock divider source
- * @param Divider : CGU_IDIV_T value indicating which divider to get the source of
- * @return CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
- */
-CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider);
-
-/**
- * @brief Gets a CGU clock divider divisor
- * @param Divider : CGU_IDIV_T value indicating which divider to get the source of
- * @return the divider value for the divider
- */
-uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider);
-
-/**
- * @brief Returns the frequency of the specified input clock source
- * @param input : Which clock input to return the frequency of
- * @return Frequency of input source in Hz
- * This function returns an ideal frequency and not the actual frequency. Returns
- * zero if the clock source is disabled.
- */
-uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input);
-
-/**
- * @brief Returns the frequency of the specified base clock source
- * @param clock : which base clock to return the frequency of.
- * @return Frequency of base source in Hz
- * This function returns an ideal frequency and not the actual frequency. Returns
- * zero if the clock source is disabled.
- */
-uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock);
-
-/**
- * @brief Sets a CGU Base Clock clock source
- * @param BaseClock : CGU_BASE_CLK_T value indicating which base clock to set
- * @param Input : CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock
- * @param autoblocken : Enables autoblocking during frequency change if true
- * @param powerdn : The clock base is setup, but powered down if true
- * @return Nothing
- */
-void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn);
-
-/**
- * @brief Gets a CGU Base Clock clock source
- * @param BaseClock : CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for
- * @return CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
- */
-CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief Enables a base clock source
- * @param BaseClock : CGU_BASE_CLK_T value indicating which base clock to enable
- * @return Nothing
- */
-void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief Disables a base clock source
- * @param BaseClock : CGU_BASE_CLK_T value indicating which base clock to disable
- * @return Nothing
- */
-void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief Enables a peripheral clock and sets clock states
- * @param clk : CCU_CLK_T value indicating which clock to enable
- * @param autoen : true to enable autoblocking on a clock rate change, false to disable
- * @param wakeupen : true to enable wakeup mechanism, false to disable
- * @param div : Divider for the clock, must be 1 for most clocks, 2 supported on others
- * @return Nothing
- */
-void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div);
-
-/**
- * @brief Enables a peripheral clock
- * @param clk : CCU_CLK_T value indicating which clock to enable
- * @return Nothing
- */
-void Chip_Clock_Enable(CCU_CLK_T clk);
-
-/**
- * @brief Disables a peripheral clock
- * @param clk : CCU_CLK_T value indicating which clock to disable
- * @return Nothing
- */
-void Chip_Clock_Disable(CCU_CLK_T clk);
-
-/**
- * @brief Returns a peripheral clock rate
- * @param clk : CCU_CLK_T value indicating which clock to get rate for
- * @return 0 if the clock is disabled, or the rate of the clock
- */
-uint32_t Chip_Clock_GetRate(CCU_CLK_T clk);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CLOCK_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h
deleted file mode 100644
index 2cbada5c27fc527b83b5d442eee56894c8325b93..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * @brief Basic CMSIS include file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CMSIS_H_
-#define __CMSIS_H_
-
-#include "lpc_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CMSIS_18XX_43XX CHIP: LPC18xx/43xx CMSIS include file
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#if defined(__ARMCC_VERSION)
-// Kill warning "#pragma push with no matching #pragma pop"
- #pragma diag_suppress 2525
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__GNUC__)
-/* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
-// #pragma push // FIXME not usable for IAR
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-#if defined(CORE_M4)
-/** @defgroup CMSIS_43XX CHIP: LPC43xx Cortex CMSIS definitions
- * @{
- */
-
-#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#ifdef CHIP_LPC43XX
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-#else
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
- /* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5,/*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4,/*!< 12 Debug Monitor */
- PendSV_IRQn = -2,/*!< 14 Pendable request for system service */
- SysTick_IRQn = -1,/*!< 15 System Tick Timer */
-
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- M0CORE_IRQn = 1,/*!< 1 M0a */
- DMA_IRQn = 2,/*!< 2 DMA */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 RITIMER */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- TIMER1_IRQn = 13,/*!< 13 TIMER1 */
- TIMER2_IRQn = 14,/*!< 14 TIMER2 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 I2C0 */
- I2C1_IRQn = 19,/*!< 19 I2C1 */
- SPI_INT_IRQn = 20,/*!< 20 SPI_INT */
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 SSP0 */
- SSP1_IRQn = 23,/*!< 23 SSP1 */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 I2S0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED4_IRQn = 30,
- SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */
- PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */
- GINT0_IRQn = 40,/*!< 40 GINT0 */
- GINT1_IRQn = 41,/*!< 41 GINT1 */
- EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/*!< 45 VADC */
- ATIMER_IRQn = 46,/*!< 46 ATIMER */
- RTC_IRQn = 47,/*!< 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/*!< 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */
- QEI_IRQn = 52,/*!< 52 QEI */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
-
-#elif defined(CORE_M3)
-/** @defgroup CMSIS_18XX CHIP: LPC18xx Cortex CMSIS definitions
- * @{
- */
-
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
- /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- RESERVED0_IRQn = 1,
- DMA_IRQn = 2,/*!< 2 DMA */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 RITIMER */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- TIMER1_IRQn = 13,/*!< 13 TIMER1 */
- TIMER2_IRQn = 14,/*!< 14 TIMER2 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 I2C0 */
- I2C1_IRQn = 19,/*!< 19 I2C1 */
- RESERVED3_IRQn = 20,
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 SSP0 */
- SSP1_IRQn = 23,/*!< 23 SSP1 */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 I2S0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED4_IRQn = 30,
- RESERVED5_IRQn = 31,
- PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */
- GINT0_IRQn = 40,/*!< 40 GINT0 */
- GINT1_IRQn = 41,/*!< 41 GINT1 */
- EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/*!< 45 VADC */
- ATIMER_IRQn = 46,/*!< 46 ATIMER */
- RTC_IRQn = 47,/*!< 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/*!< 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */
- QEI_IRQn = 52,/*!< 52 QEI */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
-
-#elif defined(CORE_M0)
-/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions
- * @{
- */
-
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
- /* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- M0_M4CORE_IRQn = 1,/*!< 1 M0a */
- DMA_IRQn = 2,/*!< 2 DMA */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 RITIMER */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- TIMER1_IRQn = 13,/*!< 13 TIMER1 */
- TIMER2_IRQn = 14,/*!< 14 TIMER2 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 I2C0 */
- I2C1_IRQn = 19,/*!< 19 I2C1 */
- SPI_INT_IRQn = 20,/*!< 20 SPI_INT */
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 SSP0 */
- SSP1_IRQn = 23,/*!< 23 SSP1 */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 I2S0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED4_IRQn = 30,
- SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */
- PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */
- GINT0_IRQn = 40,/*!< 40 GINT0 */
- GINT1_IRQn = 41,/*!< 41 GINT1 */
- EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/*!< 45 VADC */
- ATIMER_IRQn = 46,/*!< 46 ATIMER */
- RTC_IRQn = 47,/*!< 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/*!< 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */
- QEI_IRQn = 52,/*!< 52 QEI */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm0.h" /*!< Cortex-M4 processor and core peripherals */
-#else
-#error Please #define CORE_M0, CORE_M3, or CORE_M4
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMSIS_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h
deleted file mode 100644
index 1b855c5b953eed543413777f2a9c35a544ebd12c..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * @brief LPC18XX/43XX CREG control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CREG_18XX_43XX_H_
-#define __CREG_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief CREG Register Block
- */
-typedef struct { /*!< CREG Structure */
- __I uint32_t RESERVED0;
- __IO uint32_t CREG0; /*!< Chip configuration register 32 kHz oscillator output and BOD control register. */
- __I uint32_t RESERVED1[62];
- __IO uint32_t MXMEMMAP; /*!< ARM Cortex-M3/M4 memory mapping */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED2[5];
-#else
- __I uint32_t RESERVED2;
- __I uint32_t CREG1; /*!< Configuration Register 1 */
- __I uint32_t CREG2; /*!< Configuration Register 2 */
- __I uint32_t CREG3; /*!< Configuration Register 3 */
- __I uint32_t CREG4; /*!< Configuration Register 4 */
-#endif
- __IO uint32_t CREG5; /*!< Chip configuration register 5. Controls JTAG access. */
- __IO uint32_t DMAMUX; /*!< DMA muxing control */
- __IO uint32_t FLASHCFGA; /*!< Flash accelerator configuration register for flash bank A */
- __IO uint32_t FLASHCFGB; /*!< Flash accelerator configuration register for flash bank B */
- __IO uint32_t ETBCFG; /*!< ETB RAM configuration */
- __IO uint32_t CREG6; /*!< Chip configuration register 6. */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED4[52];
-#else
- __IO uint32_t M4TXEVENT; /*!< M4 IPC event register */
- __I uint32_t RESERVED4[51];
-#endif
- __I uint32_t CHIPID; /*!< Part ID */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED5[191];
-#else
- __I uint32_t RESERVED5[127];
- __IO uint32_t M0TXEVENT; /*!< M0 IPC Event register */
- __IO uint32_t M0APPMEMMAP; /*!< ARM Cortex M0 memory mapping */
- __I uint32_t RESERVED6[62];
-#endif
- __IO uint32_t USB0FLADJ; /*!< USB0 frame length adjust register */
- __I uint32_t RESERVED7[63];
- __IO uint32_t USB1FLADJ; /*!< USB1 frame length adjust register */
-} LPC_CREG_T;
-
-/**
- * @brief Identifies whether on-chip flash is present
- * @return true if on chip flash is available, otherwise false
- */
-STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)
-{
- return LPC_CREG->CHIPID != 0x3284E02B;
-}
-
-/**
- * @brief Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts.
- * @param Hz : Current frequency in Hz of the CPU
- * @return Nothing
- * This function should be called with the higher frequency before the clock frequency is
- * increased and it should be called with the new lower value after the clock frequency is
- * decreased.
- */
-STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)
-{
- uint32_t FAValue = Hz / 21510000;
-
- LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
- LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
-}
-
-/**
- * @brief Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts
- * @param Enable : true to enable PHY, false to disable
- * @return Nothing
- * The USB0 PLL & clock should be configured before calling this function. This function
- * should be called before the USB0 registers are accessed.
- */
-STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable)
-{
- if (Enable) {
- LPC_CREG->CREG0 &= ~(1 << 5);
- }
- else {
- LPC_CREG->CREG0 |= (1 << 5);
- }
-}
-
-/**
- * @brief Configures the BOD and Reset on LPC18xx/LPC43xx parts.
- * @param BODVL : Brown-Out Detect voltage level (0-3)
- * @param BORVL : Brown-Out Reset voltage level (0-3)
- * @return Nothing
- */
-STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
-{
- LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
-}
-
-#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
-/**
- * @brief Configures base address of image to be run in the Cortex M0 Core.
- * @param memaddr : Address of the image (must be aligned to 4K)
- * @return Nothing
- */
-STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
-{
- LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
-}
-
-/**
- * @brief Clear M4 IPC Event
- * @return Nothing
- */
-STATIC INLINE void Chip_CREG_ClearM4Event(void)
-{
- LPC_CREG->M4TXEVENT = 0;
-}
-
-/**
- * @brief Clear M0 IPC Event
- * @return Nothing
- */
-STATIC INLINE void Chip_CREG_ClearM0Event(void)
-{
- LPC_CREG->M0TXEVENT = 0;
-}
-
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CREG_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c
deleted file mode 100644
index 216f1c14e8c888a9d128486cc61c36a1828c0c5f..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * @brief LPC18xx/43xx EMC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "emc_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Dyanmic memory setup */
-void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config)
-{
- uint32_t ClkFreq;
- uint32_t EMCDiv;
-
- /* Note clocks must be enabled prior to this call */
- ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
-
- /* EMC Divider readback at pos 27
- TODO: just checked but dont mention in UM */
- EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
-
- /* Check EMC Divider to get real EMC clock out */
- if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
- ClkFreq >>= 1;
- }
-
- IP_EMC_Dynamic_Init(LPC_EMC, Dynamic_Config, ClkFreq);
-}
-
-/* Static memory setup */
-void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config)
-{
- uint32_t ClkFreq;
- uint32_t EMCDiv;
-
- /* Note clocks must be enabled prior to this call */
- ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC);
-
- /* EMC Divider readback at pos 27 */
- EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07;
-
- /* Check EMC Divider to get real EMC clock out */
- if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) {
- ClkFreq >>= 1;
- }
-
- IP_EMC_Static_Init(LPC_EMC, Static_Config, ClkFreq);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h
deleted file mode 100644
index eaa95899b04650b01617baa014a5cbf359fb02d6..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * @brief LPC18xx/43xx EMC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EMC_18XX_43XX_H_
-#define __EMC_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup EMC_18XX_43XX CHIP: LPC18xx/43xx EMC Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * Dynamic Chip Select Address
- */
-#define EMC_ADDRESS_DYCS0 (0x28000000)
-#define EMC_ADDRESS_DYCS1 (0x30000000)
-#define EMC_ADDRESS_DYCS2 (0x60000000)
-#define EMC_ADDRESS_DYCS3 (0x70000000)
-
-/**
- * Static Chip Select Address
- */
-#define EMC_ADDRESS_CS0 (0x1C000000)
-#define EMC_ADDRESS_CS1 (0x1D000000)
-#define EMC_ADDRESS_CS2 (0x1E000000)
-#define EMC_ADDRESS_CS3 (0x1F000000)
-
-/**
- * @brief Dyanmic memory setup
- * @param Dynamic_Config : Pointer to dynamic memory setup data
- * @return None
- */
-void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config);
-
-/**
- * @brief Static memory setup
- * @param Static_Config : Pointer to static memory setup data
- * @return None
- */
-void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config);
-
-/**
- * @brief Set Deep Sleep Mode for Dynamic Memory Controller
- * @param Enable : 1 = enter DeepSleep Mode, 0 = Normal Mode
- * @return None
- */
-STATIC INLINE void Chip_EMC_Dynamic_DeepSleepMode(uint32_t Enable)
-{
- IP_EMC_Dynamic_DeepSleepMode(LPC_EMC, Enable);
-}
-
-/**
- * @brief Enable Dynamic Memory Controller
- * @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable
- * @return None
- */
-STATIC INLINE void Chip_EMC_Dynamic_Enable(uint8_t Enable)
-{
- IP_EMC_Dynamic_Enable(LPC_EMC, Enable);
-}
-
-/**
- * @brief Mirror CS1 to CS0 and DYCS0
- * @param Enable : 1 = Mirror, 0 = Normal Memory Map
- * @return None
- */
-STATIC INLINE void Chip_EMC_Mirror(uint8_t Enable)
-{
- IP_EMC_Mirror(LPC_EMC, Enable);
-}
-
-/**
- * @brief Enable EMC
- * @param Enable : 1 = Enable, 0 = Disable
- * @return None
- */
-STATIC INLINE void Chip_EMC_Enable(uint8_t Enable)
-{
- IP_EMC_Enable(LPC_EMC, Enable);
-}
-
-/**
- * @brief Set EMC LowPower Mode
- * @param Enable : 1 = Enable, 0 = Disable
- * @return None
- */
-STATIC INLINE void Chip_EMC_LowPowerMode(uint8_t Enable)
-{
- IP_EMC_LowPowerMode(LPC_EMC, Enable);
-}
-
-/**
- * @brief Initialize EMC
- * @param Enable : 1 = Enable, 0 = Disable
- * @param ClockRatio : clock out ratio, 0 = 1:1, 1 = 1:2
- * @param EndianMode : Endian Mode, 0 = Little, 1 = Big
- * @return None
- */
-STATIC INLINE void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
-{
- IP_EMC_Init(LPC_EMC, Enable, ClockRatio, EndianMode);
-}
-
-/**
- * @brief Set Static Memory Extended Wait in Clock
- * @param Wait16Clks : Number of '16 clock' delay cycles
- * @return None
- */
-STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)
-{
- IP_EMC_SetStaticExtendedWait(LPC_EMC, Wait16Clks);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EMC_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c
deleted file mode 100644
index dd08fb8c340147da3ab18de04f2370358bd439cf..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * @brief LPC18xx/43xx ethernet driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "enet_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Basic Ethernet interface initialization */
-void Chip_ENET_Init(void)
-{
- LPC_CREG->CREG6 &= ~0x7;
-
- /* Enable ethernet clock */
- Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);
-
- /* PHY TX/RX base clock routing is setup as part of SystemInit() */
-
-#if defined(USE_RMII)
- LPC_CREG->CREG6 |= 0x4;
-#endif
-
- /* Reset ethernet and wait for reset to complete */
- Chip_RGU_TriggerReset(RGU_ETHERNET_RST);
- while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {}
-
- /* Reset ethernet peripheral */
- Chip_ENET_Reset();
-
- /* Setup MII link divider to /102 and PHY address 1 */
- Chip_ENET_Setup_MII(4, 1);
-
- IP_ENET_Init(LPC_ETHERNET);
-}
-
-/* Ethernet interface shutdown */
-void Chip_ENET_DeInit(void)
-{
- IP_ENET_DeInit(LPC_ETHERNET);
- Chip_Clock_Disable(CLK_MX_ETHERNET);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h
deleted file mode 100644
index 09f536ddee7ea01ee4197c08338f20dc3afd65df..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * @brief LPC18xx/43xx ethernet driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ENET_18XX_43XX_H_
-#define __ENET_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup ENET_18XX_43XX CHIP: LPC18xx/43xx Ethernet driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** @defgroup ENET_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Ethernet driver build options
- * @ingroup ENET_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS
- * The ethernet driver has options that configure it's operation at build-time.
- * USE_RMII:
- * - When defined, the driver will be built for RMII operation.
- * - When not defined, the driver will be built for MII operation.
- *
- * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @brief Initialize ethernet interface
- * @return Nothing
- * Performs basic initialization of the ethernet interface in a default
- * state. This is enough to place the interface in a usable state, but
- * may require more setup outside this function.
- */
-void Chip_ENET_Init(void);
-
-/**
- * @brief De-initialize the ethernet interface
- * @return Nothing
- */
-void Chip_ENET_DeInit(void);
-
-/**
- * @brief Resets the ethernet interface
- * @return Nothing
- * Resets the ethernet interface. This should be called prior to
- * Chip_ENET_Init with a small delay after this call.
- */
-STATIC INLINE void Chip_ENET_Reset(void)
-{
- IP_ENET_Reset(LPC_ETHERNET);
-}
-
-/**
- * @brief Sets the address of the interface
- * @param macAddr : Pointer to the 6 bytes used for the MAC address
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_SetADDR(const uint8_t *macAddr)
-{
- IP_ENET_SetADDR(LPC_ETHERNET, macAddr);
-}
-
-/**
- * @brief Sets up the PHY link clock divider and PHY address
- * @param div : Divider value, may vary per chip
- * @param addr : PHY address, used with MII read and write
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_Setup_MII(uint32_t div, uint8_t addr)
-{
- IP_ENET_SetupMII(LPC_ETHERNET, div, addr);
-}
-
-/**
- * @brief Starts a PHY write via the MII
- * @param reg : PHY register to write
- * @param data : Data to write to PHY register
- * @return Nothing
- * Start a PHY write operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when write is complete.
- */
-STATIC INLINE void Chip_ENET_Start_MII_Write(uint8_t reg, uint16_t data)
-{
- IP_ENET_StartMIIWrite(LPC_ETHERNET, reg, data);
-}
-
-/**
- * @brief Starts a PHY read via the MII
- * @param reg : PHY register to read
- * @return Nothing
- * Start a PHY read operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when read is complete and calling
- * IP_ENET_ReadMIIData to get the data.
- */
-STATIC INLINE void Chip_ENET_Start_MII_Read(uint8_t reg)
-{
- IP_ENET_StartMIIRead(LPC_ETHERNET, reg);
-}
-
-/**
- * @brief Returns MII link (PHY) busy status
- * @return Returns true if busy, otherwise false
- */
-STATIC INLINE bool Chip_ENET_Is_MII_Busy(void)
-{
- return IP_ENET_IsMIIBusy(LPC_ETHERNET);
-}
-
-/**
- * @brief Returns the value read from the PHY
- * @return Read value from PHY
- */
-STATIC INLINE uint16_t Chip_ENET_Read_MII_Data(void)
-{
- return IP_ENET_ReadMIIData(LPC_ETHERNET);
-}
-
-/**
- * @brief Enables or disables ethernet transmit
- * @param Enable : true to enable transmit, false to disable
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_TX_Enable(bool Enable)
-{
- IP_ENET_TXEnable(LPC_ETHERNET, Enable);
-}
-
-/**
- * @brief Enables or disables ethernet packet reception
- * @param Enable : true to enable receive, false to disable
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_RX_Enable(bool Enable)
-{
- IP_ENET_RXEnable(LPC_ETHERNET, Enable);
-}
-
-/**
- * @brief Sets full or half duplex for the interface
- * @param full : true to selected full duplex, false for half
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_Set_Duplex(bool full)
-{
- IP_ENET_SetDuplex(LPC_ETHERNET, full);
-}
-
-/**
- * @brief Sets speed for the interface
- * @param speed100 : true to select 100Mbps mode, false for 10Mbps
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_Set_Speed(bool speed100)
-{
- IP_ENET_SetSpeed(LPC_ETHERNET, speed100);
-}
-
-/**
- * @brief Configures the initial ethernet descriptors
- * @param pTXDescs : Pointer to TX descriptor list
- * @param pRXDescs : Pointer to RX descriptor list
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_InitDescriptors(
- IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs)
-{
- IP_ENET_InitDescriptors(LPC_ETHERNET, pTXDescs, pRXDescs);
-}
-
-/**
- * @brief Starts receive polling of RX descriptors
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_RXStart(void)
-{
- IP_ENET_RXStart(LPC_ETHERNET);
-}
-
-/**
- * @brief Starts transmit polling of TX descriptors
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_TXStart(void)
-{
- IP_ENET_TXStart(LPC_ETHERNET);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ENET_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c
deleted file mode 100644
index 050fdaffbb4ee0f90112152d4e8839db8f75598a..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * @brief LPC18xx/43xx event router driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "evrt_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the EVRT */
-void Chip_EVRT_Init(void)
-{
- uint8_t i = 0;
- // Clear all register to be default
- LPC_EVRT->HILO = 0x0000;
- LPC_EVRT->EDGE = 0x0000;
- LPC_EVRT->CLR_EN = 0xFFFF;
- do {
- i++;
- LPC_EVRT->CLR_STAT = 0xFFFFF;
- } while ((LPC_EVRT->STATUS != 0) && (i < 10));
-}
-
-/* Set up the type of interrupt type for a source to EVRT */
-void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type)
-{
- switch (type) {
- case EVRT_SRC_ACTIVE_LOW_LEVEL:
- LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src);
- LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src);
- break;
-
- case EVRT_SRC_ACTIVE_HIGH_LEVEL:
- LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src);
- LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src);
- break;
-
- case EVRT_SRC_ACTIVE_FALLING_EDGE:
- LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src);
- LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src);
- break;
-
- case EVRT_SRC_ACTIVE_RISING_EDGE:
- LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src);
- LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src);
- break;
-
- default:
- break;
- }
-}
-
-/* Enable or disable interrupt sources to EVRT */
-void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state)
-{
- if (state == ENABLE) {
- LPC_EVRT->SET_EN = (1 << (uint8_t) EVRT_Src);
- }
- else {
- LPC_EVRT->CLR_EN = (1 << (uint8_t) EVRT_Src);
- }
-}
-
-/* Check if a source is sending interrupt to EVRT */
-IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src)
-{
- if (LPC_EVRT->STATUS & (1 << (uint8_t) EVRT_Src)) {
- return SET;
- }
- else {return RESET; }
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h
deleted file mode 100644
index 7db552be6b916fd92ee02204c2b44175b4b9cc1a..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * @brief LPC18xx/43xx event router driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EVRT_18XX_43XX_H_
-#define __EVRT_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup EVRT_18XX_43XX CHIP: LPC18xx/43xx Event router driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Event Router register structure
- */
-typedef struct { /*!< EVENTROUTER Structure */
- __IO uint32_t HILO; /*!< Level configuration register */
- __IO uint32_t EDGE; /*!< Edge configuration */
- __I uint32_t RESERVED0[1012];
- __O uint32_t CLR_EN; /*!< Event clear enable register */
- __O uint32_t SET_EN; /*!< Event set enable register */
- __I uint32_t STATUS; /*!< Status register */
- __I uint32_t ENABLE; /*!< Enable register */
- __O uint32_t CLR_STAT; /*!< Clear register */
- __O uint32_t SET_STAT; /*!< Set register */
-} LPC_EVRT_Type;
-
-/**
- * @brief EVRT input sources
- */
-typedef enum {
- EVRT_SRC_WAKEUP0, /*!< WAKEUP0 event router source */
- EVRT_SRC_WAKEUP1, /*!< WAKEUP1 event router source */
- EVRT_SRC_WAKEUP2, /*!< WAKEUP2 event router source */
- EVRT_SRC_WAKEUP3, /*!< WAKEUP3 event router source */
- EVRT_SRC_ATIMER, /*!< Alarm timer event router source */
- EVRT_SRC_RTC, /*!< RTC event router source */
- EVRT_SRC_BOD1, /*!< BOD event router source */
- EVRT_SRC_WWDT, /*!< WWDT event router source */
- EVRT_SRC_ETHERNET, /*!< Ethernet event router source */
- EVRT_SRC_USB0, /*!< USB0 event router source */
- EVRT_SRC_USB1, /*!< USB1 event router source */
- EVRT_SRC_SDIO, /*!< Reserved */
- EVRT_SRC_CCAN, /*!< C_CAN event router source */
- EVRT_SRC_COMBINE_TIMER2, /*!< Combined timer 2 event router source */
- EVRT_SRC_COMBINE_TIMER6, /*!< Combined timer 6 event router source */
- EVRT_SRC_QEI, /*!< QEI event router source */
- EVRT_SRC_COMBINE_TIMER14, /*!< Combined timer 14 event router source */
- EVRT_SRC_RESERVED1, /*!< Reserved */
- EVRT_SRC_RESERVED2, /*!< Reserved */
- EVRT_SRC_RESET /*!< Reset event router source */
-} Chip_EVRT_SRC_ENUM;
-
-/**
- * @brief Macro for checking for a valid EVRT source
- */
-#define PARAM_EVRT_SOURCE(n) ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1) \
- || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \
- || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \
- || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \
- || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \
- || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \
- || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \
- || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \
- || (n == EVRT_SRC_RESET)) \
-
-/**
- * @brief EVRT input state detecting type
- */
-typedef enum {
- EVRT_SRC_ACTIVE_LOW_LEVEL, /*!< Active low level */
- EVRT_SRC_ACTIVE_HIGH_LEVEL, /*!< Active high level */
- EVRT_SRC_ACTIVE_FALLING_EDGE, /*!< Active falling edge */
- EVRT_SRC_ACTIVE_RISING_EDGE /*!< Active rising edge */
-} EVRT_SRC_ACTIVE_TYPE;
-
-/**
- * @brief Macro for checking for a valid EVRT state type
- */
-#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL) \
- || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE))
-
-/**
- * @brief Initialize the EVRT
- * @return Nothing
- */
-void Chip_EVRT_Init (void);
-
-/**
- * @brief Set up the type of interrupt type for a source to EVRT
- * @param EVRT_Src : EVRT source, should be one of Chip_EVRT_SRC_ENUM type
- * @param type : EVRT type, should be one of EVRT_SRC_ACTIVE_TYPE type
- * @return Nothing
- */
-void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type);
-
-/**
- * @brief Check if a source is sending interrupt to EVRT
- * @param EVRT_Src : EVRT source, should be one of Chip_EVRT_SRC_ENUM type
- * @return true if the interrupt from the source is pending, otherwise false
- */
-IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src);
-
-/**
- * @brief Enable or disable interrupt sources to EVRT
- * @param EVRT_Src : EVRT source, should be one of Chip_EVRT_SRC_ENUM type
- * @param state : ENABLE or DISABLE to enable or disable event router source
- * @return Nothing
- */
-void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state);
-
-/**
- * @brief De-initializes the EVRT peripheral
- * @return Nothing
- */
-STATIC INLINE void Chip_EVRT_DeInit(void)
-{
- LPC_EVRT->CLR_EN = 0xFFFF;
- LPC_EVRT->CLR_STAT = 0xFFFF;
-}
-
-/**
- * @brief Clear pending interrupt EVRT source
- * @param EVRT_Src : EVRT source, should be one of Chip_EVRT_SRC_ENUM type
- * @return Nothing
- */
-STATIC INLINE void Chip_EVRT_ClrPendIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src)
-{
- LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EVRT_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c
deleted file mode 100644
index ff9f9782ebaeb1a8008c66f127b6963f24a333e5..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * @brief LPC18xx/43xx DMA driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "gpdma_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Channel array to monitor free channel */
-static DMA_ChannelHandle_t ChannelHandlerArray[GPDMA_NUMBER_CHANNELS];
-
-/* Optimized Peripheral Source and Destination burst size (18xx,43xx) */
-static const uint8_t GPDMA_LUTPerBurst[] = {
- GPDMA_BSIZE_4, /* MEMORY */
- GPDMA_BSIZE_1, /* MAT0.0 */
- GPDMA_BSIZE_1, /* UART0 Tx */
- GPDMA_BSIZE_1, /* MAT0.1 */
- GPDMA_BSIZE_1, /* UART0 Rx */
- GPDMA_BSIZE_1, /* MAT1.0 */
- GPDMA_BSIZE_1, /* UART1 Tx */
- GPDMA_BSIZE_1, /* MAT1.1 */
- GPDMA_BSIZE_1, /* UART1 Rx */
- GPDMA_BSIZE_1, /* MAT2.0 */
- GPDMA_BSIZE_1, /* UART2 Tx */
- GPDMA_BSIZE_1, /* MAT2.1 */
- GPDMA_BSIZE_1, /* UART2 Rx */
- GPDMA_BSIZE_1, /* MAT3.0 */
- GPDMA_BSIZE_1, /* UART3 Tx */
- 0, /* SCT timer channel 0*/
- GPDMA_BSIZE_1, /* MAT3.1 */
- GPDMA_BSIZE_1, /* UART3 Rx */
- 0, /* SCT timer channel 1*/
- GPDMA_BSIZE_4, /* SSP0 Rx */
- GPDMA_BSIZE_32, /* I2S channel 0 */
- GPDMA_BSIZE_4, /* SSP0 Tx */
- GPDMA_BSIZE_32, /* I2S channel 1 */
- GPDMA_BSIZE_4, /* SSP1 Rx */
- GPDMA_BSIZE_4, /* SSP1 Tx */
- GPDMA_BSIZE_4, /* ADC 0 */
- GPDMA_BSIZE_4, /* ADC 1 */
- GPDMA_BSIZE_1, /* DAC */
- GPDMA_BSIZE_32, /* I2S channel 0 */
- GPDMA_BSIZE_32 /* I2S channel 0 */
-};
-
-/* Optimized Peripheral Source and Destination transfer width (18xx,43xx) */
-static const uint8_t GPDMA_LUTPerWid[] = {
- GPDMA_WIDTH_WORD, /* MEMORY */
- GPDMA_WIDTH_WORD, /* MAT0.0 */
- GPDMA_WIDTH_BYTE, /* UART0 Tx */
- GPDMA_WIDTH_WORD, /* MAT0.1 */
- GPDMA_WIDTH_BYTE, /* UART0 Rx */
- GPDMA_WIDTH_WORD, /* MAT1.0 */
- GPDMA_WIDTH_BYTE, /* UART1 Tx */
- GPDMA_WIDTH_WORD, /* MAT1.1 */
- GPDMA_WIDTH_BYTE, /* UART1 Rx */
- GPDMA_WIDTH_WORD, /* MAT2.0 */
- GPDMA_WIDTH_BYTE, /* UART2 Tx */
- GPDMA_WIDTH_WORD, /* MAT2.1 */
- GPDMA_WIDTH_BYTE, /* UART2 Rx */
- GPDMA_WIDTH_WORD, /* MAT3.0 */
- GPDMA_WIDTH_BYTE, /* UART3 Tx */
- 0, /* SCT timer channel 0*/
- GPDMA_WIDTH_WORD, /* MAT3.1 */
- GPDMA_WIDTH_BYTE, /* UART3 Rx */
- 0, /* SCT timer channel 1*/
- GPDMA_WIDTH_BYTE, /* SSP0 Rx */
- GPDMA_WIDTH_WORD, /* I2S channel 0 */
- GPDMA_WIDTH_BYTE, /* SSP0 Tx */
- GPDMA_WIDTH_WORD, /* I2S channel 1 */
- GPDMA_WIDTH_BYTE, /* SSP1 Rx */
- GPDMA_WIDTH_BYTE, /* SSP1 Tx */
- GPDMA_WIDTH_WORD, /* ADC 0 */
- GPDMA_WIDTH_WORD, /* ADC 1 */
- GPDMA_WIDTH_WORD, /* DAC */
- GPDMA_WIDTH_WORD, /* I2S channel 0 */
- GPDMA_WIDTH_WORD/* I2S channel 0 */
-};
-
-/* Lookup Table of Connection Type matched with (18xx,43xx) Peripheral Data (FIFO) register base address */
-volatile static const void *GPDMA_LUTPerAddr[] = {
- NULL, /* MEMORY */
- (&LPC_TIMER0->MR), /* MAT0.0 */
- (&LPC_USART0-> /*RBTHDLR.*/ THR), /* UART0 Tx */
- ((uint32_t *) &LPC_TIMER0->MR + 1), /* MAT0.1 */
- (&LPC_USART0-> /*RBTHDLR.*/ RBR), /* UART0 Rx */
- (&LPC_TIMER1->MR), /* MAT1.0 */
- (&LPC_UART1-> /*RBTHDLR.*/ THR),/* UART1 Tx */
- ((uint32_t *) &LPC_TIMER1->MR + 1), /* MAT1.1 */
- (&LPC_UART1-> /*RBTHDLR.*/ RBR),/* UART1 Rx */
- (&LPC_TIMER2->MR), /* MAT2.0 */
- (&LPC_USART2-> /*RBTHDLR.*/ THR), /* UART2 Tx */
- ((uint32_t *) &LPC_TIMER2->MR + 1), /* MAT2.1 */
- (&LPC_USART2-> /*RBTHDLR.*/ RBR), /* UART2 Rx */
- (&LPC_TIMER3->MR), /* MAT3.0 */
- (&LPC_USART3-> /*RBTHDLR.*/ THR), /* UART3 Tx */
- 0, /* SCT timer channel 0*/
- ((uint32_t *) &LPC_TIMER3->MR + 1), /* MAT3.1 */
- (&LPC_USART3-> /*RBTHDLR.*/ RBR), /* UART3 Rx */
- 0, /* SCT timer channel 1*/
- (&LPC_SSP0->DR), /* SSP0 Rx */
- (&LPC_I2S0->TXFIFO), /* I2S channel 0 */
- (&LPC_SSP0->DR), /* SSP0 Tx */
- (&LPC_I2S0->RXFIFO), /* I2S channel 1 */
- (&LPC_SSP1->DR), /* SSP1 Rx */
- (&LPC_SSP1->DR), /* SSP1 Tx */
- (&LPC_ADC0->GDR), /* ADC 0 */
- (&LPC_ADC1->GDR), /* ADC 1 */
- (&LPC_DAC->CR), /* DAC */
- (&LPC_I2S0->TXFIFO), /* I2S channel 0 */
- (&LPC_I2S0->RXFIFO) /* I2S channel 0 */
-};
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Control which set of peripherals is connected to the DMA controller */
-static uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number)
-{
- uint8_t function, channel;
-
- switch (gpdma_peripheral_connection_number) {
- case GPDMA_CONN_MAT0_0:
- function = 0;
- channel = 1;
- break;
-
- case GPDMA_CONN_UART0_Tx:
- function = 1;
- channel = 1;
- break;
-
- case GPDMA_CONN_MAT0_1:
- function = 0;
- channel = 2;
- break;
-
- case GPDMA_CONN_UART0_Rx:
- function = 1;
- channel = 2;
- break;
-
- case GPDMA_CONN_MAT1_0:
- function = 0;
- channel = 3;
- break;
-
- case GPDMA_CONN_UART1_Tx:
- function = 1;
- channel = 3;
- break;
-
- case GPDMA_CONN_MAT1_1:
- function = 0;
- channel = 4;
- break;
-
- case GPDMA_CONN_UART1_Rx:
- function = 1;
- channel = 4;
- break;
-
- case GPDMA_CONN_MAT2_0:
- function = 0;
- channel = 5;
- break;
-
- case GPDMA_CONN_UART2_Tx:
- function = 1;
- channel = 5;
- break;
-
- case GPDMA_CONN_MAT2_1:
- function = 0;
- channel = 6;
- break;
-
- case GPDMA_CONN_UART2_Rx:
- function = 1;
- channel = 6;
- break;
-
- case GPDMA_CONN_MAT3_0:
- function = 0;
- channel = 7;
- break;
-
- case GPDMA_CONN_UART3_Tx:
- function = 1;
- channel = 7;
- break;
-
- case GPDMA_CONN_SCT_0:
- function = 2;
- channel = 7;
- break;
-
- case GPDMA_CONN_MAT3_1:
- function = 0;
- channel = 8;
- break;
-
- case GPDMA_CONN_UART3_Rx:
- function = 1;
- channel = 8;
- break;
-
- case GPDMA_CONN_SCT_1:
- function = 2;
- channel = 8;
- break;
-
- case GPDMA_CONN_SSP0_Rx:
- function = 0;
- channel = 9;
- break;
-
- case GPDMA_CONN_I2S_Tx_Channel_0:
- case GPDMA_CONN_I2S_Rx_Channel_0:
- function = 1;
- channel = 9;
- break;
-
- case GPDMA_CONN_SSP0_Tx:
- function = 0;
- channel = 10;
- break;
-
- case GPDMA_CONN_I2S_Tx_Channel_1:
- case GPDMA_CONN_I2S_Rx_Channel_1:
- function = 1;
- channel = 10;
- break;
-
- case GPDMA_CONN_SSP1_Rx:
- function = 0;
- channel = 11;
- break;
-
- case GPDMA_CONN_SSP1_Tx:
- function = 0;
- channel = 12;
- break;
-
- case GPDMA_CONN_ADC_0:
- function = 0;
- channel = 13;
- break;
-
- case GPDMA_CONN_ADC_1:
- function = 0;
- channel = 14;
- break;
-
- case GPDMA_CONN_DAC:
- function = 0;
- channel = 15;
- break;
-
- default:
- function = 3;
- channel = 15;
- break;
- }
- /* Set select function to dmamux register */
- if (0 != gpdma_peripheral_connection_number) {
- LPC_CREG->DMAMUX &= ~(0x03 << (2 * channel));
- LPC_CREG->DMAMUX |= (function << (2 * channel));
- }
- return channel;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the GPDMA */
-void Chip_GPDMA_Init(void)
-{
- uint8_t i;
- IP_GPDMA_Init(LPC_GPDMA);
- /* Reset all channels are free */
- for (i = 0; i < GPDMA_NUMBER_CHANNELS; i++)
- ChannelHandlerArray[i].ChannelStatus = DISABLE;
-}
-
-/* Stop a stream DMA transfer */
-void Chip_DMA_Stop(uint8_t ChannelNum)
-{
- IP_GPDMA_ChannelCmd(LPC_GPDMA, (ChannelNum), DISABLE);
- if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTTC, ChannelNum)) {
- /* Clear terminate counter Interrupt pending */
- Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, ChannelNum);
- }
- if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTERR, ChannelNum)) {
- /* Clear terminate counter Interrupt pending */
- Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, ChannelNum);
- }
- ChannelHandlerArray[ChannelNum].ChannelStatus = DISABLE;
-}
-
-/* The GPDMA stream interrupt status checking */
-Status Chip_DMA_Interrupt(uint8_t ChannelNum)
-{
-
- if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INT, ChannelNum)) {
- /* Check counter terminal status */
- if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTTC, ChannelNum)) {
- /* Clear terminate counter Interrupt pending */
- Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, ChannelNum);
- return SUCCESS;
- }
- /* Check error terminal status */
- if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTERR, ChannelNum)) {
- /* Clear error counter Interrupt pending */
-
- Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, ChannelNum);
- return ERROR;
- }
- }
- return ERROR;
-}
-
-/* Do a DMA transfer M2M, M2P,P2M or P2P */
-void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size)
-{
- GPDMA_Channel_CFG_Type GPDMACfg;
- uint8_t SrcPeripheral = 0, DstPeripheral = 0;
-
- GPDMACfg.ChannelNum = ChannelNum;
- GPDMACfg.TransferType = TransferType;
- GPDMACfg.TransferSize = Size;
-
- switch (TransferType) {
- case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
- GPDMACfg.SrcAddr = (uint32_t) src;
- GPDMACfg.DstAddr = (uint32_t) dst;
- src = 0; dst = 0;
- GPDMACfg.TransferWidth = GPDMA_WIDTH_BYTE;
- break;
-
- case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
- case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
- GPDMACfg.SrcAddr = (uint32_t) src;
- src = 0;
- GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
- DstPeripheral = DMAMUX_Config(dst);
- break;
-
- case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
- case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
- GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
- GPDMACfg.DstAddr = (uint32_t) dst;
- SrcPeripheral = DMAMUX_Config(src);
- dst = 0;
- break;
-
- case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
- case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
- case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
- GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
- GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
- SrcPeripheral = DMAMUX_Config(src);
- DstPeripheral = DMAMUX_Config(dst);
- break;
-
- default:
- break;
- }
-
- IP_GPDMA_Setup(LPC_GPDMA, &GPDMACfg, (uint32_t) GPDMA_LUTPerBurst[src], (uint32_t) GPDMA_LUTPerBurst[dst],
- (uint32_t) GPDMA_LUTPerWid[src], (uint32_t) GPDMA_LUTPerWid[dst], (uint32_t) GPDMA_LUTPerAddr[src],
- (uint32_t) GPDMA_LUTPerAddr[dst], SrcPeripheral, DstPeripheral);
-
- /* Start the Channel */
- IP_GPDMA_ChannelCmd(LPC_GPDMA, ChannelNum, ENABLE);
-}
-
-/* Get a free GPDMA channel for one DMA connection */
-uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID)
-{
- uint8_t temp = 0;
- for (temp = 0; temp < GPDMA_NUMBER_CHANNELS; temp++)
- if (!Chip_GPDMA_IntGetStatus(GPDMA_STAT_ENABLED_CH,
- temp) && (ChannelHandlerArray[temp].ChannelStatus == DISABLE)) {
- ChannelHandlerArray[temp].ChannelStatus = ENABLE;
- return temp;
- }
- return 0;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h
deleted file mode 100644
index d96b0768471186728cdf282b095b35eb03c6aec5..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * @brief LPC18xx/43xx DMA driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPDMA_18XX_43XX_H_
-#define __GPDMA_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** Number of channels on GPDMA */
-#define GPDMA_NUMBER_CHANNELS 8
-
-/** DMA Connection number definitions */
-#define GPDMA_CONN_MEMORY ((0UL)) /**< MEMORY */
-#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */
-#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */
-#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */
-#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */
-#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */
-#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */
-#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */
-#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */
-#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */
-#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */
-#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */
-#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */
-#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */
-#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
-#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/
-#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */
-#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */
-#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/
-#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */
-#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL)) /**< I2S channel 0 */
-#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */
-#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL)) /**< I2S channel 1 */
-#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */
-#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */
-#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */
-#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */
-#define GPDMA_CONN_DAC ((27UL)) /**< DAC */
-#define GPDMA_CONN_I2S_Tx_Channel_1 ((28UL)) /**< I2S channel 0 */
-#define GPDMA_CONN_I2S_Rx_Channel_0 ((29UL)) /**< I2S channel 0 */
-
-/** Burst size in Source and Destination definitions */
-#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
-#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
-#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
-#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
-#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
-#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
-#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
-#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
-
-/** Width in Source transfer width and Destination transfer width definitions */
-#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
-#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
-#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
-
-/** Flow control definitions */
-#define DMA_CONTROLLER 0 /**< Flow control is DMA controller*/
-#define SRC_PER_CONTROLLER 1 /**< Flow control is Source peripheral controller*/
-#define DST_PER_CONTROLLER 2 /**< Flow control is Destination peripheral controller*/
-
-typedef struct {
- FunctionalState ChannelStatus;
-} DMA_ChannelHandle_t;
-
-#define Chip_GPDMA_IntGetStatus(type, channel) IP_GPDMA_IntGetStatus(LPC_GPDMA, type, channel)
-
-#define Chip_GPDMA_ClearIntPending(type, channel) IP_GPDMA_ClearIntPending(LPC_GPDMA, type, channel)
-
-#define Chip_GPDMA_ChannelCmd(channelNum, NewState) IP_GPDMA_ChannelCmd(LPC_GPDMA, channelNum, NewState)
-
-/**
- * @brief Initialize the GPDMA
- * @return Nothing
- */
-void Chip_GPDMA_Init(void);
-
-/**
- * @brief Stop a stream DMA transfer
- * @param ChannelNum : Channel Number to be closed
- * @return Nothing
- */
-void Chip_DMA_Stop(uint8_t ChannelNum);
-
-/**
- * @brief The GPDMA stream interrupt status checking
- * @param ChannelNum : Channel Number to be checked on interruption
- * @return Status:
- * - SUCCESS : DMA transfer success
- * - ERROR : DMA transfer failed
- */
-Status Chip_DMA_Interrupt(uint8_t ChannelNum);
-
-/**
- * @brief Get a free GPDMA channel for one DMA connection
- * @param PeripheralConnection_ID : Some chip fix each peripheral DMA connection on a specified channel ( have not used in 18xx/43xx )
- * @return The channel number which is selected
- */
-uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID);
-
-/**
- * @brief Do a DMA transfer M2M, M2P,P2M or P2P
- * @param ChannelNum : Channel used for transfer
- * @param src : Address of Memory or PeripheralConnection_ID which is the source
- * @param dst : Address of Memory or PeripheralConnection_ID which is the destination
- * @param TransferType : Select the transfer controller and the type of transfer. Should be:
- * - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
- * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
- * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
- * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
- * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
- * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
- * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
- * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
- * @param Size : The number of DMA transfers
- * @return Nothing
- */
-void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPDMA_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c
deleted file mode 100644
index ca28b96ddfa71e773573b1b4f4b3d69c51c63e18..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/** @brief LPC18xx/43xx GPIO driver** Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "gpio_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Set Direction for a GPIO port */
-void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out)
-{
- if (out) {
- LPC_GPIO_PORT->DIR[portNum] |= bitValue;
- }
- else {
- LPC_GPIO_PORT->DIR[portNum] &= ~bitValue;
- }
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h
deleted file mode 100644
index 96c10d7bdddda496fde7752663fd03e87d2f0434..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * @brief LPC18xx/43xx GPIO driver
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIO_18XX_43XX_H_
-#define __GPIO_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup GPIO_18XX_43XX CHIP: LPC18xx/43xx GPIO Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize GPIO block
- * @return Nothing
- */
-STATIC INLINE void Chip_GPIO_Init(void)
-{
- IP_GPIO_Init(LPC_GPIO_PORT);
-}
-
-/**
- * @brief Set a GPIO port/bit state
- * @param Port : GPIO port to set
- * @param Bit : GPIO bit to set
- * @param Setting : true for high, false for low
- * @return Nothing
- */
-STATIC INLINE void Chip_GPIO_WritePortBit(uint32_t Port, uint8_t Bit, bool Setting)
-{
- IP_GPIO_WritePortBit(LPC_GPIO_PORT, Port, Bit, Setting);
-}
-
-/**
- * @brief Seta GPIO direction
- * @param Port : GPIO port to set
- * @param Bit : GPIO bit to set
- * @param Setting : true for output, false for input
- * @return Nothing
- */
-STATIC INLINE void Chip_GPIO_WriteDirBit(uint32_t Port, uint8_t Bit, bool Setting)
-{
- IP_GPIO_WriteDirBit(LPC_GPIO_PORT, Port, Bit, Setting);
-}
-
-/**
- * @brief Read a GPIO state
- * @param Port : GPIO port to read
- * @param Bit : GPIO bit to read
- * @return true of the GPIO is high, false if low
- */
-STATIC INLINE bool Chip_GPIO_ReadPortBit(uint32_t Port, uint8_t Bit)
-{
- return IP_GPIO_ReadPortBit(LPC_GPIO_PORT, Port, Bit);
-}
-
-/**
- * @brief Read a GPIO direction (out ot in)
- * @param Port : GPIO port to read
- * @param Bit : GPIO bit to read
- * @return true of the GPIO is an output, false if input
- */
-STATIC INLINE bool Chip_GPIO_ReadDirBit(uint32_t Port, uint8_t Bit)
-{
- return IP_GPIO_ReadDirBit(LPC_GPIO_PORT, Port, Bit);
-}
-
-/**
- * @brief Enable GPIO Interrupt
- * @param PortNum : GPIO port number interrupt, should be: 0 to 7
- * @param BitValue : GPIO bit to enable (Not used)
- * @param IntMode : Interrupt mode, should be:
- * 0: Rising edge interrupt mode
- * 1: Falling edge interrupt mode
- * 2: Active-High interrupt mode
- * 3: Active-Low interrupt mode
- * @return None
- */
-STATIC INLINE void Chip_GPIO_IntCmd(uint8_t PortNum, uint8_t BitValue, Gpio_PinInt_Mode_Enum IntMode)
-{
- IP_GPIOPININT_IntCmd(LPC_GPIO_PIN_INT, PortNum, IntMode);
-}
-
-/**
- * @brief Get GPIO Interrupt Status
- * @param PortNum : GPIO port number interrupt, should be: 0 to 7
- * @param PinNum : GPIO pin to check (Not used)
- * @param IntMode : Interrupt mode (Not used)
- * @return true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool Chip_GPIO_IntGetStatus(uint8_t PortNum, uint8_t PinNum, uint8_t IntMode)
-{
- return IP_GPIOPININT_IntGetStatus(LPC_GPIO_PIN_INT, PortNum);
-}
-
-/**
- * @brief Clear GPIO Interrupt (Edge interrupt cases only)
- * @param PortNum : GPIO port number interrupt, should be: 0 to 7
- * @param BitValue : GPIO bit to clear (Not used)
- * @return None
- */
-STATIC INLINE void Chip_GPIO_IntClear(uint8_t PortNum, uint8_t BitValue)
-{
- IP_GPIOPININT_IntClear(LPC_GPIO_PIN_INT, PortNum);
-}
-
-/**
- * @brief GPIO Group Interrupt Pin Initialization
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortComb : GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality)
- * @param PortTrigger : GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered)
- * @return None
- */
-STATIC INLINE void Chip_GPIOGP_IntInit(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger)
-{
- IP_GPIOGP_IntInit(pGPIOGPINT, PortComb, PortTrigger);
-}
-
-/**
- * @brief GPIO Group Interrupt Pin Add to Group
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortNum : GPIO port number, should be 0 to 7
- * @param PinNum : GPIO pin number, should be 0 to 31
- * @param ActiveMode : GPIO active mode, should be 0 (active LOW) and 1 (active HIGH)
- * @return None
- */
-STATIC INLINE void Chip_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_Type *pGPIOGPINT,
- uint8_t PortNum,
- uint8_t PinNum,
- bool ActiveMode)
-{
- IP_GPIOGP_IntPinAdd(pGPIOGPINT, PortNum, PinNum, ActiveMode);
-}
-
-/**
- * @brief GPIO Group Interrupt Pin Remove from Group
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortNum : GPIO port number, should be 0 to 7
- * @param PinNum : GPIO pin number, should be 0 to 31
- * @return None
- */
-STATIC INLINE void Chip_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum)
-{
- IP_GPIOGP_IntPinRemove(pGPIOGPINT, PortNum, PinNum);
-}
-
-/**
- * @brief Get GPIO Group Interrupt Get Status
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @return true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool Chip_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_Type *pGPIOGPINT)
-{
- return IP_GPIOGP_IntGetStatus(pGPIOGPINT);
-}
-
-/**
- * @brief Clear GPIO Group Interrupt
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @return None
- */
-STATIC INLINE void Chip_GPIOGP_IntClear(IP_GPIOGROUPINT_001_Type *pGPIOGPINT)
-{
- IP_GPIOGP_IntClear(pGPIOGPINT);
-}
-
-/**
- * @brief Set Direction for a GPIO port
- * @param portNum : Port Number
- * @param bitValue : GPIO bit to set
- * @param out : Direction value, 0 = input, !0 = output
- * @return None
- * Bits set to '0' are not altered.
- */
-void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out);
-
-/**
- * @brief Set Direction for a GPIO port
- * @param portNum : Port Number
- * @param bitValue : GPIO bit to set
- * @param out : Direction value, 0 = input, !0 = output
- * @return None
- * Bits set to '0' are not altered.
- */
-STATIC INLINE void Chip_FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out)
-{
- /* Same with Chip_GPIO_SetDir() */
- Chip_GPIO_SetDir(portNum, bitValue, out);
-}
-
-/**
- * @brief Set a GPIO port/bit to the high state
- * @param portNum : Port number
- * @param bitValue : Bit(s) in the port to set high
- * @return None
- * Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_FIO_SetValue(uint8_t portNum, uint32_t bitValue)
-{
- /* Same with GPIO_SetValue() */
- LPC_GPIO_PORT->SET[portNum] = bitValue;
-}
-
-/**
- * @brief Set a GPIO port/bit to the low state
- * @param portNum : Port number
- * @param bitValue : Bit(s) in the port to set low
- * @return None
- * Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_FIO_ClearValue(uint8_t portNum, uint32_t bitValue)
-{
- /* Same with GPIO_ClearValue() */
- LPC_GPIO_PORT->CLR[portNum] = bitValue;
-}
-
-/**
- * @brief Read current bit states for the selected port
- * @param portNum : Port number to read
- * @return Current value of GPIO port
- * The current states of the bits for the port are read, regardless of
- * whether the GPIO port bits are input or output.
- */
-STATIC INLINE uint32_t Chip_FIO_ReadValue(uint8_t portNum)
-{
- /* Same with GPIO_ReadValue() */
- return LPC_GPIO_PORT->PIN[portNum];
-}
-
-/**
- * @brief Set a GPIO port/bit to the high state
- * @param portNum : Port number
- * @param bitValue : Bit(s) in the port to set high
- * @return None
- * Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_GPIO_SetValue(uint8_t portNum, uint32_t bitValue)
-{
- LPC_GPIO_PORT->SET[portNum] = bitValue;
-}
-
-/**
- * @brief Set a GPIO port/bit to the low state
- * @param portNum : Port number
- * @param bitValue : Bit(s) in the port to set low
- * @return None
- * Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_GPIO_ClearValue(uint8_t portNum, uint32_t bitValue)
-{
- LPC_GPIO_PORT->CLR[portNum] = bitValue;
-}
-
-/**
- * @brief Read current bit states for the selected port
- * @param portNum : Port number to read
- * @return Current value of GPIO port
- * The current states of the bits for the port are read, regardless of
- * whether the GPIO port bits are input or output.
- */
-STATIC INLINE uint32_t Chip_GPIO_ReadValue(uint8_t portNum)
-{
- return LPC_GPIO_PORT->PIN[portNum];
-}
-
-/**
- * @}
- */
-
- #ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIO_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c
deleted file mode 100644
index 3504ac3c67fce38d2b91d14fdb6669d5a87b95bb..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2C driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "i2c_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-#define MAX_TX_BUFFER_SIZE 10 /* Maximum transmit buffer size in Chip_I2C_MasterWriteReg() function */
-
-static uint32_t i2cClockrate[2];
-static I2C_M_SETUP_Type TransferMCfg;
-static uint8_t p_regAddr;
-static uint8_t tx_buffer[MAX_TX_BUFFER_SIZE];
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Determine clock for uart BASED ON SELECTED uart */
-static CCU_CLK_T Chip_I2C_DetermineClk(LPC_I2C_Type *I2Cx) {
-
- CCU_CLK_T i2cclk;
-
- /* Pick clock for uart BASED ON SELECTED uart */
- if (I2Cx == LPC_I2C0) {
- i2cclk = CLK_APB1_I2C0;
- }
- else {
- i2cclk = CLK_APB3_I2C1;
- }
-
- return i2cclk;
-}
-
-/* Get UART bus number BASED ON SELECTED uart */
-static I2C_ID_Type Chip_I2C_Get_BusNum(LPC_I2C_Type *I2Cx)
-{
- if (I2Cx == LPC_I2C1) {
- return I2C1;
- }
-
- return I2C0;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initializes the LPC_I2C peripheral with specified parameter */
-void Chip_I2C_Init(LPC_I2C_Type *I2Cx)
-{
- /* Enable I2C Clocking */
- // Chip_Clock_EnableOpts(Chip_I2C_DetermineClk(I2Cx), false, false, 1);
- Chip_Clock_Enable(Chip_I2C_DetermineClk(I2Cx));
-
- IP_I2C_Init(I2Cx);
-}
-
-/* De-initializes the I2C peripheral registers to their default reset values */
-void Chip_I2C_DeInit(LPC_I2C_Type *I2Cx)
-{
- IP_I2C_DeInit(I2Cx);
-
- /* Disable UART clocking */
- Chip_Clock_Disable(Chip_I2C_DetermineClk(I2Cx));
-}
-
-/* Set up clock rate for LPC_I2C peripheral */
-void Chip_I2C_SetClockRate(LPC_I2C_Type *I2Cx, uint32_t clockrate)
-{
- if (I2Cx == LPC_I2C0) {
- i2cClockrate[0] = clockrate;
- /* Select weather standard, fast, fast plus mode*/
- if (clockrate >= 1000000) { /* Fast mode plus: 1MHz, high speed 3.4MHz */
- Chip_SCU_I2C0PinConfig(I2C0_FAST_MODE_PLUS);
- }
- else { /* standard 100KHz, fast 400KHz */
- Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
- }
- }
- else if (I2Cx == LPC_I2C1) {
- i2cClockrate[1] = clockrate;
- /* Check if I2C1 run fast mode*/
- if (clockrate > 400000) {
- return;
- }
- }
- else {return; }
-
- /* Set clock rate */
- if (clockrate < 1000) { /* make sure SCLH,SCLL not exceed its 16bit value */
- return;
- }
-
- IP_I2C_SetClockRate(I2Cx, (Chip_Clock_GetRate(Chip_I2C_DetermineClk(I2Cx)) / clockrate));
-}
-
-/* Get current clock rate for LPC_I2C peripheral */
-uint32_t Chip_I2C_GetClockRate(LPC_I2C_Type *I2Cx)
-{
- if (I2Cx == LPC_I2C0) {
- return i2cClockrate[0];
- }
- else if (I2Cx == LPC_I2C1) {
- return i2cClockrate[1];
- }
- return 0;
-}
-
-/* Transmit and Receive data in master mode */
-Status Chip_I2C_MasterTransferData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- TransferCfg->retransmissions_max = 3;
- TransferCfg->tx_count = 0;
- TransferCfg->rx_count = 0;
- TransferCfg->retransmissions_count = 0;
-
- return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Transmit an array of bytes in Master mode */
-Status Chip_I2C_MasterTransmitData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- TransferCfg->rx_data = NULL;
- TransferCfg->rx_length = 0;
- TransferCfg->retransmissions_max = 3;
- TransferCfg->tx_count = 0;
- TransferCfg->rx_count = 0;
- TransferCfg->retransmissions_count = 0;
-
- return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Receive an array of bytes in Master mode */
-Status Chip_I2C_MasterReceiveData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- TransferCfg->tx_data = NULL;
- TransferCfg->tx_length = 0;
- TransferCfg->retransmissions_max = 3;
- TransferCfg->tx_count = 0;
- TransferCfg->rx_count = 0;
- TransferCfg->retransmissions_count = 0;
-
- return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Transmit one byte and continue to send an array of bytes
- * after a repeated start condition is generated in Master mode
- */
-uint32_t Chip_I2C_MasterWriteReg(LPC_I2C_Type *I2Cx,
- uint32_t SlaveAddr,
- uint8_t regAddr,
- uint8_t *buffer,
- uint8_t buffer_len)
-{
- uint8_t i = 0;
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- tx_buffer[0] = regAddr;
-
- for (i = 0; i < buffer_len; i++)
- tx_buffer[i + 1] = *(buffer + i);
-
- TransferMCfg.sl_addr7bit = SlaveAddr;
- TransferMCfg.tx_data = tx_buffer;
- TransferMCfg.tx_length = buffer_len + 1;
- TransferMCfg.rx_data = NULL;
- TransferMCfg.rx_length = 0;
- TransferMCfg.retransmissions_max = 3;
- TransferMCfg.tx_count = 0;
- TransferMCfg.rx_count = 0;
- TransferMCfg.retransmissions_count = 0;
- IP_I2C_MasterTransferData(I2Cx, I2C_Num, &TransferMCfg, I2C_TRANSFER_POLLING);
-
- return TransferMCfg.tx_count;
-}
-
-/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
- * This function is useful for communicating with the I2C slave registers
- */
-uint32_t Chip_I2C_MasterReadReg(LPC_I2C_Type *I2Cx,
- uint32_t SlaveAddr,
- uint8_t regAddr,
- uint8_t *buffer,
- uint8_t buffer_len)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- p_regAddr = regAddr;
-
- TransferMCfg.sl_addr7bit = SlaveAddr;
- TransferMCfg.tx_data = &p_regAddr;
- TransferMCfg.tx_length = 1;
- TransferMCfg.rx_data = buffer;
- TransferMCfg.rx_length = buffer_len;
- TransferMCfg.retransmissions_max = 3;
- TransferMCfg.tx_count = 0;
- TransferMCfg.rx_count = 0;
- TransferMCfg.retransmissions_count = 0;
- IP_I2C_MasterTransferData(I2Cx, I2C_Num, &TransferMCfg, I2C_TRANSFER_POLLING);
-
- return TransferMCfg.rx_count;
-}
-
-/* General Master Interrupt handler for I2C peripheral */
-void Chip_I2C_Interrupt_MasterHandler(LPC_I2C_Type *I2Cx)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- IP_I2C_Interrupt_MasterHandler(I2Cx, I2C_Num);
-}
-
-/* Get status of Master Transfer */
-bool Chip_I2C_Interrupt_MasterTransferComplete(LPC_I2C_Type *I2Cx)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- return IP_I2C_Interrupt_MasterTransferComplete(I2C_Num);
-}
-
-/* Receive and Transmit data in slave mode */
-Status Chip_I2C_SlaveTransferData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- TransferCfg->tx_count = 0;
- TransferCfg->rx_count = 0;
-
- return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Transmit an array of bytes in Slave mode */
-Status Chip_I2C_SlaveTransmitData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- TransferCfg->tx_count = 0;
- TransferCfg->rx_data = NULL;
- TransferCfg->rx_length = 0;
- TransferCfg->rx_count = 0;
-
- return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* Receive an array of bytes in Slave mode */
-Status Chip_I2C_SlaveReceiveData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- TransferCfg->tx_data = NULL;
- TransferCfg->tx_length = 0;
- TransferCfg->tx_count = 0;
- TransferCfg->rx_count = 0;
-
- return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt);
-}
-
-/* General Slave Interrupt handler for I2C peripheral */
-void Chip_I2C_Interrupt_SlaveHandler(LPC_I2C_Type *I2Cx)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- IP_I2C_Interrupt_SlaveHandler(I2Cx, I2C_Num);
-}
-
-/* Get status of Slave Transfer */
-bool Chip_I2C_Interrupt_SlaveTransferComplete(LPC_I2C_Type *I2Cx)
-{
- I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx);
-
- return IP_I2C_Interrupt_SlaveTransferComplete(I2C_Num);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h
deleted file mode 100644
index 460bb7a0835cf627e9d675cf3647a544405c8bb3..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2C driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef I2C_18XX_43XX_H_
-#define I2C_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup I2C_18XX_43XX CHIP: LPC18xx/43xx I2C Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initializes the LPC_I2C peripheral with specified parameter.
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return Nothing
- */
-void Chip_I2C_Init(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief De-initializes the I2C peripheral registers to their default reset values
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return Nothing
- */
-void Chip_I2C_DeInit(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Set up clock rate for LPC_I2C peripheral.
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param clockrate : Target clock rate value to initialized I2C peripheral (Hz)
- * @return Nothing
- */
-void Chip_I2C_SetClockRate(LPC_I2C_Type *I2Cx, uint32_t clockrate);
-
-/**
- * @brief Get current clock rate for LPC_I2C peripheral.
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return the current I2Cx clock rate
- */
-uint32_t Chip_I2C_GetClockRate(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Transmit and Receive data in master mode
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param TransferCfg : Pointer to a I2C_M_SETUP_Type structure that contains specified
- * information about the configuration for master transfer.
- * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode
- * @return SUCCESS or ERROR
- */
-Status Chip_I2C_MasterTransferData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief Transmit an array of bytes in Master mode
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param TransferCfg : Pointer to a I2C_M_SETUP_Type structure that contains specified
- * information about the configuration for master transfer
- * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode
- * @return SUCCESS or ERROR
- */
-Status Chip_I2C_MasterTransmitData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief Receive an array of bytes in Master mode
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param TransferCfg : Pointer to a I2C_M_SETUP_Type structure that contains specified
- * information about the configuration for master transfer.
- * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return SUCCESS or ERROR
- */
-Status Chip_I2C_MasterReceiveData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief Write byte(s) to slave register
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param SlaveAddr : Slave address in 7-bit mode
- * @param regAddr : Slave register address
- * @param buffer : pointer to data array needed to send
- * @param buffer_len : data length (number of bytes)
- * @return Number of bytes sent
- * Transmit one byte and an array of bytes after a repeated start condition is generated in Master mode.
- * This function is useful for communicating with the I2C slave registers.
- */
-uint32_t Chip_I2C_MasterWriteReg(LPC_I2C_Type *I2Cx,
- uint32_t SlaveAddr,
- uint8_t regAddr,
- uint8_t *buffer,
- uint8_t buffer_len);
-
-/**
- * @brief Read slave register content
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param SlaveAddr : Slave address in 7-bit mode
- * @param regAddr : Slave register address
- * @param buffer : pointer to data array needed to receive
- * @param buffer_len : data length (number of bytes)
- * @return Number of bytes received
- * Transmit one byte and continue to receive an array of bytes after a repeated start condition is
- * generated in Master mode. This function is useful for communicating with the I2C slave registers.
- */
-uint32_t Chip_I2C_MasterReadReg(LPC_I2C_Type *I2Cx,
- uint32_t SlaveAddr,
- uint8_t regAddr,
- uint8_t *buffer,
- uint8_t buffer_len);
-
-/**
- * @brief General Master Interrupt handler for I2C peripheral
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return Nothing
- */
-void Chip_I2C_Interrupt_MasterHandler (LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Get status of Master Transfer
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return Master transfer status: TRUE (transfer completed) or FALSE (not completed yet)
- */
-bool Chip_I2C_Interrupt_MasterTransferComplete(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Receive and Transmit data in slave mode
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param TransferCfg : Pointer to a I2C_S_SETUP_Type structure that contains specified
- * information about the configuration for master transfer.
- * @param Opt : I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return SUCCESS or ERROR
- */
-Status Chip_I2C_SlaveTransferData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief Transmit an array of bytes in Slave mode
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param TransferCfg : Pointer to a I2C_S_SETUP_Type structure that contains specified
- * information about the configuration for slave transfer.
- * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return SUCCESS or ERROR
- */
-Status Chip_I2C_SlaveTransmitData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief Receive an array of bytes in Slave mode
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param TransferCfg : Pointer to a I2C_S_SETUP_Type structure that contains specified
- * information about the configuration for slave transfer.
- * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
- * @return SUCCESS or ERROR
- */
-Status Chip_I2C_SlaveReceiveData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-
-/**
- * @brief General Slave Interrupt handler for I2C peripheral
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return Nothing
- */
-void Chip_I2C_Interrupt_SlaveHandler (LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Get status of Slave Transfer
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @return Slave transfer status: TRUE (transfer completed) or FALSE (not completed yet)
- */
-bool Chip_I2C_Interrupt_SlaveTransferComplete(LPC_I2C_Type *I2Cx);
-
-/**
- * @brief Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct.
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param OwnSlaveAddrConfigStruct : Pointer to a I2C_OWNSLAVEADDR_CFG_Type structure that contains the
- * configuration information for the specified I2C slave address.
- * @return Nothing
- */
-STATIC INLINE void Chip_I2C_SetOwnSlaveAddr(LPC_I2C_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct)
-{
- IP_I2C_SetOwnSlaveAddr(I2Cx, OwnSlaveAddrConfigStruct);
-}
-
-/**
- * @brief Enable or disable I2C peripheral's operation
- * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1
- * @param Mode : I2C mode, should be I2C_MASTER_MODE, I2C_SLAVE_MODE or I2C_GENERAL_MODE
- * @param NewState: New State of LPC_I2C peripheral's operation, should be ENABLE or DISABLE
- * @return Nothing
- */
-STATIC INLINE void Chip_I2C_Cmd(LPC_I2C_Type *I2Cx, I2C_Mode Mode, FunctionalState NewState)
-{
- IP_I2C_Cmd(I2Cx, Mode, NewState);
-}
-
-/**
- * @}
- */
-
- #ifdef __cplusplus
-}
-#endif
-
-#endif /* I2C_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c
deleted file mode 100644
index 4e0c8ba203aa8c09de370cb0fc7d430e02ee71ce..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2S driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "i2s_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Configure I2S for Audio Format input */
-Status Chip_I2S_Config(LPC_I2S_Type *I2Sx, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format)
-{
- uint32_t pClk;
- uint32_t x, y;
- uint64_t divider;
- uint16_t dif;
- uint16_t x_divide = 0, y_divide = 0;
- uint32_t N;
- uint16_t err, ErrorOptimal = 0xFFFF;
-
- pClk = (uint64_t)Chip_Clock_GetRate(CLK_APB1_I2S);
-
- /* divider is a fixed point number with 16 fractional bits */
- divider = (((uint64_t)(audio_format->SampleRate) * 2 * (audio_format->WordWidth) * 2) << 16) / pClk;
- /* find N that make x/y <= 1 -> divider <= 2^16 */
- for (N = 64; N > 0; N--) {
- if ((divider * N) < (1 << 16)) {
- break;
- }
- }
- if (N == 0) {
- return ERROR;
- }
- divider *= N;
- for (y = 255; y > 0; y--) {
- x = y * divider;
- if (x & (0xFF000000)) {
- continue;
- }
- dif = x & 0xFFFF;
- if (dif > 0x8000) {
- err = 0x10000 - dif;
- }
- else {
- err = dif;
- }
- if (err == 0) {
- y_divide = y;
- break;
- }
- else if (err < ErrorOptimal) {
- ErrorOptimal = err;
- y_divide = y;
- }
- }
- x_divide = ((uint64_t)y_divide * (audio_format->SampleRate) * 2 * (audio_format->WordWidth) * N * 2) / pClk;
- if (x_divide >= 256) {
- x_divide = 0xFF;
- }
- if (x_divide == 0) {
- x_divide = 1;
- }
- if (audio_format->WordWidth <= 8) {
- IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_8);
- }
- else if (audio_format->WordWidth <= 16) {
- IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_16);
- }
- else {
- IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_32);
- }
- IP_I2S_SetMono(I2Sx, TRMode, (audio_format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO);
- IP_I2S_SetMasterSlaveMode(I2Sx, TRMode, I2S_MASTER_MODE);
- IP_I2S_SetWS_Halfperiod(I2Sx, TRMode, audio_format->WordWidth - 1);
- IP_I2S_ModeConfig(I2Sx, TRMode, I2S_TXMODE_CLKSEL(0), !I2S_TXMODE_4PIN_ENABLE, !I2S_TXMODE_MCENA);
- IP_I2S_SetBitRate(I2Sx, TRMode, N - 1);
- IP_I2S_SetXYDivider(I2Sx, TRMode, x_divide, y_divide);
- return SUCCESS;
-}
-
-/* Enable/Disable Interrupt with a specific FIFO depth */
-void Chip_I2S_Int_Cmd(LPC_I2S_Type *I2Sx, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth)
-{
- IP_I2S_InterruptCmd(I2Sx, TRMode, NewState);
- IP_I2S_SetFIFODepthIRQ(I2Sx, TRMode, FIFO_Depth);
-}
-
-/* Enable/Disable DMA with a specific FIFO depth */
-void Chip_I2S_DMA_Cmd(LPC_I2S_Type *I2Sx,
- uint8_t TRMode,
- uint8_t DMANum,
- FunctionalState NewState,
- uint8_t FIFO_Depth)
-{
- IP_I2S_SetFIFODepthDMA(I2Sx, TRMode, (IP_I2S_DMARequestNumber_Type) DMANum, FIFO_Depth);
- IP_I2S_DMACmd(I2Sx, (IP_I2S_DMARequestNumber_Type) DMANum, TRMode, NewState);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h
deleted file mode 100644
index ab166396186a225f8f7709bdc2386c1abd315474..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2S driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __I2S_18XX_43XX_H_
-#define __I2S_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup I2S_18XX_43XX CHIP: LPC18xx/43xx I2S driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define I2S_DMA_REQUEST_NUMBER_1 IP_I2S_DMA_REQUEST_NUMBER_1
-#define I2S_DMA_REQUEST_NUMBER_2 IP_I2S_DMA_REQUEST_NUMBER_2
-
-/**
- * @brief I2S Audio Format Structure
- */
-typedef struct {
- uint32_t SampleRate; /*!< Sample Rate */
- uint8_t ChannelNumber; /*!< Channel Number - 1 is mono, 2 is stereo */
- uint8_t WordWidth; /*!< Word Width - 8, 16 or 32 bits */
-} Chip_I2S_Audio_Format_Type;
-
-/**
- * @brief Initialize for I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_I2S_Init(LPC_I2S_Type *pI2S)
-{
- IP_I2S_Init(pI2S);
-}
-
-/**
- * @brief Shutdown I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- * Reset all relative registers (DMA, transmit/receive control, interrupt) to default value
- */
-STATIC INLINE void Chip_I2S_DeInit(LPC_I2S_Type *pI2S)
-{
- IP_I2S_DeInit(pI2S);
-}
-
-/**
- * @brief Send a 32-bit data to TXFIFO for transmition
- * @param pI2S : The base of I2S peripheral on the chip
- * @param data : Data to be transmited
- * @return Nothing
- * The function writes to TXFIFO without checking any condition.
- */
-STATIC INLINE void Chip_I2S_Send(LPC_I2S_Type *pI2S, uint32_t data)
-{
- IP_I2S_Send(pI2S, data);
-}
-
-/**
- * @brief Get received data from RXFIFO
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Data received in RXFIFO
- * The function reads from RXFIFO without checking any condition.
- */
-STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_Type *pI2S)
-{
- return IP_I2S_Receive(pI2S);
-}
-
-/**
- * @brief Start the I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- */
-STATIC INLINE void Chip_I2S_Start(LPC_I2S_Type *pI2S, uint8_t TRMode)
-{
- IP_I2S_Start(pI2S, TRMode);
-}
-
-/**
- * @brief Disables accesses on FIFOs, places the transmit channel in mute mode
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- */
-STATIC INLINE void Chip_I2S_Pause(LPC_I2S_Type *pI2S, uint8_t TRMode)
-{
- IP_I2S_Pause(pI2S, TRMode);
-}
-
-/**
- * @brief Transmit channel sends only zeroes
- * @param pI2S : The base of I2S peripheral on the chip
- * @param NewState : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- * The data output from I2S transmit channel is always zeroes
- */
-STATIC INLINE void Chip_I2S_Mute(LPC_I2S_Type *pI2S, FunctionalState NewState)
-{
- IP_I2S_Mute(pI2S, NewState);
-}
-
-/**
- * @brief Stop I2S asynchronously
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- * Pause, resets the transmit channel and FIFO asynchronously
- */
-STATIC INLINE void Chip_I2S_Stop(LPC_I2S_Type *pI2S, uint8_t TRMode)
-{
- IP_I2S_Stop(pI2S, TRMode);
-}
-
-/**
- * @brief Set the I2S operating modes
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param clksel : Clock source selection for the receive bit clock divider
- * @param fpin : Receive 4-pin mode selection
- * @param mcena : Enable for the RX_MCLK output
- * @return Nothing
- * In addition to master and slave modes, which are independently configurable for
- * the transmitter and the receiver, several different clock sources are possible,
- * including variations that share the clock and/or WS between the transmitter and
- * receiver. It also allows using I2S with fewer pins, typically four.
- */
-STATIC INLINE void Chip_I2S_ModeConfig(LPC_I2S_Type *pI2S,
- uint8_t TRMode,
- uint32_t clksel,
- uint32_t fpin,
- uint32_t mcena)
-{
- IP_I2S_ModeConfig(pI2S, TRMode, clksel, fpin, mcena);
-}
-
-/**
- * @brief Get the current level of the Transmit/Receive FIFO
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Current level of the Transmit/Receive FIFO
- */
-STATIC INLINE uint8_t Chip_I2S_GetLevel(LPC_I2S_Type *pI2S, uint8_t TRMode)
-{
- return IP_I2S_GetLevel(pI2S, TRMode);
-}
-
-/**
- * @brief Configure I2S for Audio Format input
- * @param pI2S : The base I2S peripheral on the chip
- * @param TRMode : Mode Rx/Tx
- * @param audio_format : Audio Format
- * @return SUCCESS or ERROR
- */
-Status Chip_I2S_Config(LPC_I2S_Type *pI2S, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format);
-
-/**
- * @brief Enable/Disable Interrupt with a specific FIFO depth
- * @param pI2S : The base I2S peripheral on the chip
- * @param TRMode : Mode Rx/Tx
- * @param NewState : ENABLE or DISABLE interrupt
- * @param FIFO_Depth : FIFO level creating an irq request
- * @return Nothing
- */
-void Chip_I2S_Int_Cmd(LPC_I2S_Type *pI2S, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth);
-
-/**
- * @brief Enable/Disable DMA with a specific FIFO depth
- * @param pI2S : The base I2S peripheral on the chip
- * @param TRMode : Mode Rx/Tx
- * @param DMANum : Should be
- * - IP_I2S_DMA_REQUEST_NUMBER_1 : Using DMA1
- * - IP_I2S_DMA_REQUEST_NUMBER_2 : Using DMA2
- * @param NewState : ENABLE or DISABLE interrupt
- * @param FIFO_Depth : FIFO level creating an irq request
- * @return Nothing
- */
-void Chip_I2S_DMA_Cmd(LPC_I2S_Type *pI2S, uint8_t TRMode, uint8_t DMANum, FunctionalState NewState, uint8_t FIFO_Depth);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __I2S_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c
deleted file mode 100644
index e3b4443fd624549f36229f27b5871ab8eb97fd04..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * @brief LPC18xx/43xx LCD chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "lcd_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-static LCD_CURSOR_SIZE_OPT LCD_Cursor_Size = LCD_CURSOR_64x64;
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Configure Cursor */
-void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync)
-{
- LCD_Cursor_Size = cursor_size;
- IP_LCD_Cursor_Config(LPC_LCD, cursor_size, sync);
-}
-
-/* Write Cursor Image into Internal Cursor Image Buffer */
-void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image)
-{
- int i, j;
- uint32_t *fifoptr, *crsr_ptr = (uint32_t *) Image;
-
- /* Check if Cursor Size was configured as 32x32 or 64x64*/
- if (LCD_Cursor_Size == LCD_CURSOR_32x32) {
- i = cursor_num * 64;
- j = i + 64;
- }
- else {
- i = 0;
- j = 256;
- }
- fifoptr = IP_LCD_Cursor_GetImageBufferAddress(LPC_LCD, 0);
-
- /* Copy Cursor Image content to FIFO */
- for (; i < j; i++) {
-
- *fifoptr = *crsr_ptr;
- crsr_ptr++;
- fifoptr++;
- }
-}
-
-/* Load LCD Palette */
-void Chip_LCD_LoadPalette(void *palette) {
- LCD_PALETTE_ENTRY_Type pal_entry, *ptr_pal_entry;
- uint8_t i, *pal_ptr;
- /* This function supports loading of the color palette from
- the C file generated by the bmp2c utility. It expects the
- palette to be passed as an array of 32-bit BGR entries having
- the following format:
- 2:0 - Not used
- 7:3 - Blue
- 10:8 - Not used
- 15:11 - Green
- 18:16 - Not used
- 23:19 - Red
- 31:24 - Not used
- arg = pointer to input palette table address */
- ptr_pal_entry = &pal_entry;
- pal_ptr = (uint8_t *) palette;
-
- /* 256 entry in the palette table */
- for (i = 0; i < 256 / 2; i++) {
- pal_entry.Bl = (*pal_ptr++) >> 3; /* blue first */
- pal_entry.Gl = (*pal_ptr++) >> 3; /* get green */
- pal_entry.Rl = (*pal_ptr++) >> 3; /* get red */
- pal_ptr++; /* skip over the unused byte */
- /* do the most significant halfword of the palette */
- pal_entry.Bu = (*pal_ptr++) >> 3; /* blue first */
- pal_entry.Gu = (*pal_ptr++) >> 3; /* get green */
- pal_entry.Ru = (*pal_ptr++) >> 3; /* get red */
- pal_ptr++; /* skip over the unused byte */
-
- IP_LCD_Color_LoadPalette(LPC_LCD, (uint32_t *) &ptr_pal_entry, i);
- }
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h
deleted file mode 100644
index e7a08a419072140c3b8410636d4788b8ede51e4e..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * @brief LPC18xx/43xx LCD chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LCD_18XX_43XX_H_
-#define __LCD_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup LCD_18XX_43XX CHIP: LPC18xx/43xx LCD driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize the LCD controller
- * @param LCD_ConfigStruct : Pointer to LCD configuration
- * @return LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error
- */
-STATIC INLINE void Chip_LCD_Init(LCD_Config_Type *LCD_ConfigStruct)
-{
- IP_LCD_Init(LPC_LCD, LCD_ConfigStruct);
-}
-
-/**
- * @brief Power the LCD Panel (power pin)
- * @param OnOff : true to power on, false to power off
- * @return None
- */
-STATIC INLINE void Chip_LCD_Power(FunctionalState OnOff)
-{
- IP_LCD_Power(LPC_LCD, OnOff);
-}
-
-/**
- * @brief Enable/Disable the LCD Controller
- * @param EnDis : true to enable, false to disable
- * @return None
- */
-STATIC INLINE void Chip_LCD_Enable(FunctionalState EnDis)
-{
- IP_LCD_Enable(LPC_LCD, EnDis);
-}
-
-/**
- * @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame
- * Buffer for Dual Panel
- * @param buffer : address of buffer
- * @return None
- */
-STATIC INLINE void Chip_LCD_SetUPFrameBuffer(void *buffer)
-{
- IP_LCD_SetUPFrameBuffer(LPC_LCD, buffer);
-}
-
-/**
- * @brief Set LCD Lower Panel Frame Buffer for Dual Panel
- * @param buffer : address of buffer
- * @return None
- */
-STATIC INLINE void Chip_LCD_SetLPFrameBuffer(void *buffer)
-{
- IP_LCD_SetLPFrameBuffer(LPC_LCD, buffer);
-}
-
-/**
- * @brief Configure Cursor
- * @param cursor_size : specify size of cursor
- * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels
- * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels
- * @param sync : cursor sync mode
- * - TRUE :cursor sync to the frame sync pulse
- * - FALSE :cursor async mode
- * @return None
- */
-void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync);
-
-/**
- * @brief Enable Cursor
- * @param cursor_num : specify number of cursor is going to be written
- * this param must < 4
- * @param OnOff : true to turn on LCD, false to turn off
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_Enable(uint8_t cursor_num, FunctionalState OnOff)
-{
- IP_LCD_Cursor_Enable(LPC_LCD, cursor_num, OnOff);
-}
-
-/**
- * @brief Load Cursor Palette
- * @param palette_color : cursor palette 0 value
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(uint32_t palette_color)
-{
- IP_LCD_Cursor_LoadPalette0(LPC_LCD, palette_color);
-}
-
-/**
- * @brief Load Cursor Palette
- * @param palette_color : cursor palette 1 value
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(uint32_t palette_color)
-{
- IP_LCD_Cursor_LoadPalette1(LPC_LCD, palette_color);
-}
-
-/**
- * @brief Set Cursor Position
- * @param x : horizontal position
- * @param y : vertical position
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_SetPos(uint16_t x, uint16_t y)
-{
- IP_LCD_Cursor_SetPos(LPC_LCD, x, y);
-}
-
-/**
- * @brief Set Cursor Clipping Position
- * @param x : horizontal position, should be in range: 0..63
- * @param y : vertical position, should be in range: 0..63
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_SetClip(uint16_t x, uint16_t y)
-{
- IP_LCD_Cursor_SetClip(LPC_LCD, x, y);
-}
-
-/**
- * @brief Enable Controller Interrupt
- * @param ints : OR'ed interrupt bits to enable
- * @return None
- */
-STATIC INLINE void Chip_LCD_EnableInts(uint32_t ints)
-{
- IP_LCD_EnableInts(LPC_LCD, ints);
-}
-
-/**
- * @brief Disable Controller Interrupt
- * @param ints : OR'ed interrupt bits to disable
- * @return None
- */
-STATIC INLINE void Chip_LCD_DisableInts(uint32_t ints)
-{
- IP_LCD_DisableInts(LPC_LCD, ints);
-}
-
-/**
- * @brief Clear Controller Interrupt
- * @param ints : OR'ed interrupt bits to clear
- * @return None
- */
-STATIC INLINE void Chip_LCD_ClearInts(uint32_t ints)
-{
- IP_LCD_ClearInts(LPC_LCD, ints);
-}
-
-/**
- * @brief Write Cursor Image into Internal Cursor Image Buffer
- * @param cursor_num : Cursor index
- * @param Image : Pointer to image data
- * @return None
- */
-void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image);
-
-/**
- * @brief Load LCD Palette
- * @param palette : Address of palette table to load
- * @return None
- */
-void Chip_LCD_LoadPalette(void *palette);
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-
-#endif /* __LCD_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c
deleted file mode 100644
index e3977d6332a469748a9db1dff07e4aa3beef21c2..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * @brief LPC18xx/43xx Reset Generator Unit driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "rgu_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Trigger a peripheral reset for the selected peripheral */
-void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber)
-{
- volatile uint32_t *p;
-
- /* To trigger reset- write RESET_CTRLx with a 1 bit */
- p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
-
- /* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
- p += ResetNumber / 32;
-
- /* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
- after 1 clock cycle, so set the bit and return */
- *p = (1 << (ResetNumber % 32));
-}
-
-/* Clears reset for the selected peripheral */
-void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber)
-{
- volatile uint32_t *p;
-
- /* To trigger reset- write RESET_CTRLx with a 1 bit */
- p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
-
- /* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
- p += ResetNumber / 32;
-
- /* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
- after 1 clock cycle, so set the bit and return */
- *p = 0;
-}
-
-/* Checks the reset status of a peripheral */
-bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber)
-{
- volatile uint32_t *read;
-
- read = (volatile uint32_t *) &(LPC_RGU->RESET_ACTIVE_STATUS0);
- read += ResetNumber / 32;
-
- /* Reset not asserted if bit is set */
- return (bool) ((*read & (1 << (ResetNumber % 32))) == 0);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h
deleted file mode 100644
index 50a49efefa614d0f094158861151541c6f1d3c62..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * @brief LPC18xx/43xx Reset Generator Unit driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RGU_18XX_43XX_H_
-#define __RGU_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RGU_18XX_43XX CHIP: LPC18xx/43xx Reset Generator Unit (RGU) driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief RGU reset enumerations
- */
-typedef enum {
- RGU_CORE_RST,
- RGU_PERIPH_RST,
- RGU_MASTER_RST,
- RGU_WWDT_RST = 4,
- RGU_CREG_RST,
- RGU_BUS_RST = 8,
- RGU_SCU_RST,
- RGU_M3_RST = 13,
- RGU_LCD_RST = 16,
- RGU_USB0_RST,
- RGU_USB1_RST,
- RGU_DMA_RST,
- RGU_SDIO_RST,
- RGU_EMC_RST,
- RGU_ETHERNET_RST,
- RGU_FLASHA_RST = 25,
- RGU_EEPROM_RST = 27,
- RGU_GPIO_RST,
- RGU_FLASHB_RST,
- RGU_TIMER0_RST = 32,
- RGU_TIMER1_RST,
- RGU_TIMER2_RST,
- RGU_TIMER3_RST,
- RGU_RITIMER_RST,
- RGU_SCT_RST,
- RGU_MOTOCONPWM_RST,
- RGU_QEI_RST,
- RGU_ADC0_RST,
- RGU_ADC1_RST,
- RGU_DAC_RST,
- RGU_UART0_RST = 44,
- RGU_UART1_RST,
- RGU_UART2_RST,
- RGU_UART3_RST,
- RGU_I2C0_RST,
- RGU_I2C1_RST,
- RGU_SSP0_RST,
- RGU_SSP1_RST,
- RGU_I2S_RST,
- RGU_SPIFI_RST,
- RGU_CAN1_RST,
- RGU_CAN0_RST,
-#ifdef CHIP_LPC43XX
- RGU_M0APP_RST,
- RGU_SGPIO_RST,
- RGU_SPI_RST,
-#endif
- RGU_LAST_RST = 63,
-} RGU_RST_TYPE;
-
-/**
- * @brief RGU register structure
- */
-typedef struct { /*!< RGU Structure */
- __I uint32_t RESERVED0[64];
- __O uint32_t RESET_CTRL0; /*!< Reset control register 0 */
- __O uint32_t RESET_CTRL1; /*!< Reset control register 1 */
- __I uint32_t RESERVED1[2];
- __IO uint32_t RESET_STATUS0; /*!< Reset status register 0 */
- __IO uint32_t RESET_STATUS1; /*!< Reset status register 1 */
- __IO uint32_t RESET_STATUS2; /*!< Reset status register 2 */
- __IO uint32_t RESET_STATUS3; /*!< Reset status register 3 */
- __I uint32_t RESERVED2[12];
- __I uint32_t RESET_ACTIVE_STATUS0; /*!< Reset active status register 0 */
- __I uint32_t RESET_ACTIVE_STATUS1; /*!< Reset active status register 1 */
- __I uint32_t RESERVED3[170];
- __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */
-} LPC_RGU_T;
-
-/**
- * @brief Trigger a peripheral reset for the selected peripheral
- * @param ResetNumber : Peripheral reset number to trigger
- * @return Nothing
- */
-void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber);
-
-/**
- * @brief Checks the reset status of a peripheral
- * @param ResetNumber : Peripheral reset number to trigger
- * @return true if the periperal is still being reset
- */
-bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber);
-
-/**
- * @brief Clears reset for the selected peripheral
- * @param ResetNumber : Peripheral reset number to trigger
- * @return Nothing
- * Almost all peripherals will auto clear the reset bit. Only a few peripherals
- * like the Cortex M0 Core in LPC43xx will not auto clear the reset and require
- * this function to clear the reset bit.
- */
-void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RGU_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c
deleted file mode 100644
index a00796610f13d2947c37b48a9a0f00625ecfacf6..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * @brief LPC18xx/43xx RITimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "ritimer_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Set timer interval value */
-void Chip_RIT_SetTimerInterval(uint32_t time_interval)
-{
- uint32_t clock_rate, cmp_value;
-
- /* Get clock rate for RITimer */
- clock_rate = Chip_Clock_GetRate(CLK_MX_RITIMER);
-
- /* Determine aapproximate compare value based on clock rate and passed interval */
- cmp_value = (clock_rate / 1000) * time_interval;
-
- /* Set timer compare value */
- Chip_RIT_SetCOMPVAL(cmp_value);
-
- /* Set timer enable clear bit to clear timer to 0 whenever
- counter value equals the contents of RICOMPVAL */
- Chip_RIT_EnableCTRL(RIT_CTRL_ENCLR);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h
deleted file mode 100644
index 2ad32a57fe18c3179968afda90c67bb63756f11f..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * @brief LPC18xx/43xx RITimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RITIMER_18XX_43XX_H_
-#define __RITIMER_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RIT_18XX_43XX CHIP: LPC18xx/43xx RIT driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize the RIT
- * @return None
- */
-STATIC INLINE void Chip_RIT_Init(void)
-{
- IP_RIT_Init(LPC_RITIMER);
-}
-
-/**
- * @brief DeInitialize the RIT
- * @return None
- */
-STATIC INLINE void Chip_RIT_DeInit(void)
-{
- IP_RIT_DeInit(LPC_RITIMER);
-}
-
-/**
- * @brief Enable/Disable Timer
- * @param NewState : ENABLE to enable timer, DISABLE to stop timer
- * @return None
- */
-STATIC INLINE void Chip_RIT_Cmd(FunctionalState NewState)
-{
- IP_RIT_Enable(LPC_RITIMER, NewState);
-}
-
-/**
- * @brief Enable or disable timer debug
- * @param NewState : ENABLE to halt timer whenever a hardware break condition occurs
- * @return None
- */
-STATIC INLINE void Chip_RIT_TimerDebugCmd(FunctionalState NewState)
-{
- IP_RIT_TimerDebugCmd(LPC_RITIMER, NewState);
-}
-
-/**
- * @brief Check whether interrupt flag is set or not
- * @return Current interrupt status, either ET or UNSET
- */
-STATIC INLINE IntStatus Chip_RIT_GetIntStatus(void)
-{
- return IP_RIT_GetIntStatus(LPC_RITIMER);
-}
-
-/**
- * @brief Set a tick value for the interrupt to time out
- * @param val : value (in ticks) of the interrupt to be set
- * @return None
- */
-STATIC INLINE void Chip_RIT_SetCOMPVAL(uint32_t val)
-{
- IP_RIT_SetCOMPVAL(LPC_RITIMER, val);
-}
-
-/**
- * @brief Enables or clears the RIT or interrupt
- * @param val : RIT to be set, one or more RIT_CTRL_* values
- * @return None
- */
-STATIC INLINE void Chip_RIT_EnableCTRL(uint32_t val)
-{
- IP_RIT_EnableCTRL(LPC_RITIMER, val);
-}
-
-/**
- * @brief Clears the RIT interrupt
- * @return None
- */
-STATIC INLINE void Chip_RIT_ClearInt(void)
-{
- IP_RIT_EnableCTRL(LPC_RITIMER, RIT_CTRL_INT);
-}
-
-/**
- * @brief Returns the current RIT Counter value
- * @return the current timer counter value
- */
-STATIC INLINE uint32_t Chip_RIT_GetCounter(void)
-{
- return IP_RIT_GetCounter(LPC_RITIMER);
-}
-
-/**
- * @brief Set timer interval value
- * @param time_interval : timer interval value (ms)
- * @return None
- */
-void Chip_RIT_SetTimerInterval(uint32_t time_interval);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RITIMER_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c
deleted file mode 100644
index 9db49832eefc13f5d80466525714d189697d5e9e..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * @brief LPC18xx/43xx RTC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "rtc_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Initialize the RTC peripheral */
-void Chip_RTC_Init(void)
-{
- LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); /* Reset 32Khz oscillator */
- LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); /* Enable 32 kHz & 1 kHz on osc32k and release reset */
- LPC_SCU->SFSCLK[0] = 1 | (0x3 << 2);/* function 1; CGU clk out, pull down */
- IP_RTC_Init(LPC_RTC);
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h
deleted file mode 100644
index 1220c4c0d547b0242758c242cc64aefa4b060138..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * @brief LPC18xx/43xx RTC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RTC_18XX_43XX_H_
-#define __RTC_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RTC_18XX_43XX CHIP: LPC18xx/43xx RTC driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize the RTC peripheral
- * @return None
- */
-void Chip_RTC_Init(void);
-
-/**
- * @brief De-initialize the RTC peripheral
- * @return None
- */
-STATIC INLINE void Chip_RTC_DeInit(void)
-{
- IP_RTC_DeInit(LPC_RTC);
-}
-
-/**
- * @brief Reset clock tick counter in the RTC peripheral
- * @return None
- */
-STATIC INLINE void Chip_RTC_ResetClockTickCounter(void)
-{
- IP_RTC_ResetClockTickCounter(LPC_RTC);
-}
-
-/**
- * @brief Start/Stop RTC peripheral
- * @param NewState : New State of this function, should be:
- * - ENABLE :The time counters are enabled
- * - DISABLE :The time counters are disabled
- * @return None
- */
-STATIC INLINE void Chip_RTC_Enable(FunctionalState NewState)
-{
- IP_RTC_Enable(LPC_RTC, NewState);
-}
-
-/**
- * @brief Enable/Disable Counter increment interrupt for a time type
- * in the RTC peripheral
- * @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*)
- * @param NewState : ENABLE or DISABLE
- * @return None
- */
-STATIC INLINE void Chip_RTC_CntIncrIntConfig(uint32_t cntrMask, FunctionalState NewState)
-{
- IP_RTC_CntIncrIntConfig(LPC_RTC, cntrMask, NewState);
-}
-
-/**
- * @brief Enable/Disable Alarm interrupt for a time type
- * in the RTC peripheral
- * @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)
- * @param NewState : ENABLE or DISABLE
- * @return None
- */
-STATIC INLINE void Chip_RTC_AlarmIntConfig(uint32_t alarmMask, FunctionalState NewState)
-{
- IP_RTC_AlarmIntConfig(LPC_RTC, alarmMask, NewState);
-}
-
-/**
- * @brief Set current time value for a time type in the RTC peripheral
- * @param Timetype : time field index type to set
- * @param TimeValue : Value to palce in time field
- * @return None
- */
-STATIC INLINE void Chip_RTC_SetTime(IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)
-{
- IP_RTC_SetTime(LPC_RTC, Timetype, TimeValue);
-}
-
-/**
- * @brief Get current time value for a type time type
- * @param Timetype : Time field index type to get
- * @return Value of time field according to specified time type
- */
-STATIC INLINE uint32_t Chip_RTC_GetTime(IP_RTC_TIMEINDEX_T Timetype)
-{
- return IP_RTC_GetTime(LPC_RTC, Timetype);
-}
-
-/**
- * @brief Set full time in the RTC peripheral
- * @param pFullTime : Pointer to full time data
- * @return None
- */
-STATIC INLINE void Chip_RTC_SetFullTime(IP_RTC_TIME_T *pFullTime)
-{
- IP_RTC_SetFullTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief Get full time from the RTC peripheral
- * @param pFullTime : Pointer to full time record to fill
- * @return None
- */
-STATIC INLINE void Chip_RTC_GetFullTime(IP_RTC_TIME_T *pFullTime)
-{
- IP_RTC_GetFullTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief Set alarm time value for a time type
- * @param Timetype : Time index field to set
- * @param ALValue : Alarm time value to set
- * @return None
- */
-STATIC INLINE void Chip_RTC_SetAlarmTime(IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue)
-{
- IP_RTC_SetAlarmTime(LPC_RTC, Timetype, ALValue);
-}
-
-/**
- * @brief Get alarm time value for a time type
- * @param Timetype : Time index field to get
- * @return Value of Alarm time according to specified time type
- */
-STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(IP_RTC_TIMEINDEX_T Timetype)
-{
- return IP_RTC_GetAlarmTime(LPC_RTC, Timetype);
-}
-
-/**
- * @brief Set full alarm time in the RTC peripheral
- * @param pFullTime : Pointer to full time record to set alarm
- * @return None
- */
-STATIC INLINE void Chip_RTC_SetFullAlarmTime(IP_RTC_TIME_T *pFullTime)
-{
- IP_RTC_SetFullAlarmTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief Get full alarm time in the RTC peripheral
- * @param pFullTime : Pointer to full time record to fill
- * @return None
- */
-STATIC INLINE void Chip_RTC_GetFullAlarmTime(IP_RTC_TIME_T *pFullTime)
-{
- IP_RTC_GetFullAlarmTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief Write value to General purpose registers
- * @param index : General purpose register index
- * @param Value : Value to write
- * @return None
- * Note: These General purpose registers can be used to store important
-
- * information when the main power supply is off. The value in these
-
- * registers is not affected by chip reset. These registers are
-
- * powered in the RTC power domain.
- */
-STATIC INLINE void Chip_REGFILE_Write(uint8_t index, uint32_t Value)
-{
- IP_REGFILE_Write(LPC_REGFILE, index, Value);
-}
-
-/**
- * @brief Read value from General purpose registers
- * @param index : General purpose register index
- * @return Read Value
- * These General purpose registers can be used to store important
-
- * information when the main power supply is off. The value in these
-
- * registers is not affected by chip reset. These registers are
-
- * powered in the RTC power domain.
- */
-STATIC INLINE uint32_t Chip_REGFILE_Read(uint8_t index)
-{
- return IP_REGFILE_Read(LPC_REGFILE, index);
-}
-
-/**
- * @brief Enable/Disable calibration counter in the RTC peripheral
- * @param NewState : New State of this function, should be:
- * - ENABLE :The calibration counter is enabled and counting
- * - DISABLE :The calibration counter is disabled and reset to zero
- * @return None
- */
-STATIC INLINE void Chip_RTC_CalibCounterCmd(FunctionalState NewState)
-{
- IP_RTC_CalibCounterCmd(LPC_RTC, NewState);
-}
-
-/**
- * @brief Configures Calibration in the RTC peripheral
- * @param CalibValue : Calibration value, should be in range from 0 to 131,072
- * @param CalibDir : Calibration Direction, should be:
- * - RTC_CALIB_DIR_FORWARD :Forward calibration
- * - RTC_CALIB_DIR_BACKWARD :Backward calibration
- * @return None
- */
-STATIC INLINE void Chip_RTC_CalibConfig(uint32_t CalibValue, uint8_t CalibDir)
-{
- IP_RTC_CalibConfig(LPC_RTC, CalibValue, CalibDir);
-}
-
-/**
- * @brief Clear specified Location interrupt pending in the RTC peripheral
- * @param IntType : Interrupt location type, should be:
- * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending.
- * - RTC_INT_ALARM :Clear alarm interrupt pending
- * @return None
- */
-STATIC INLINE void Chip_RTC_ClearIntPending(uint32_t IntType)
-{
- IP_RTC_ClearIntPending(LPC_RTC, IntType);
-}
-
-/**
- * @brief Check whether if specified location interrupt in the
- * RTC peripheral is set or not
- * @param IntType : Interrupt location type, should be:
- * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
- * - RTC_INT_ALARM: Alarm generated an interrupt.
- * @return New state of specified Location interrupt in RTC peripheral, SET OR RESET
- */
-STATIC INLINE IntStatus Chip_RTC_GetIntPending(uint32_t IntType)
-{
- return IP_RTC_GetIntPending(LPC_RTC, IntType);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RTC_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c
deleted file mode 100644
index 091f5bd5f3f04dc0d3f9d4136b8615627c35ceab..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * @brief LPC18xx/43xx System Control Unit (SCU) control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "scu_18xx_43xx.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Configure pin function */
-void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)
-{
- if (port == PINMUX_CLK) {
- LPC_SCU_CLK(((uint32_t) LPC_SCU), pin) = mode + func;
- }
- else {
- LPC_SCU->SFSP[port][pin] = mode + func;
- }
-}
-
-/* GPIO Interrupt Pin Select */
-void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum)
-{
- uint8_t pinInt;
- volatile uint32_t pinSel;
-
- pinInt = ((PortNum & 0x7) << 5) | (PinNum & 0x1F);
- if (PortSel < 4) {
- pinSel = LPC_SCU->PINTSEL0;
- pinSel &= ~(0xFF << (PortSel * 8));
- pinSel |= (pinInt << (PortSel * 8));
- LPC_SCU->PINTSEL0 = pinSel;
- }
- else {
- pinSel = LPC_SCU->PINTSEL1;
- pinSel &= ~(0xFF << ((PortSel - 4) * 8));
- pinSel |= (pinInt << ((PortSel - 4) * 8));
- LPC_SCU->PINTSEL1 = pinSel;
- }
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h
deleted file mode 100644
index c11f0cc478e5c98d3158122525e5f5bdaa57529d..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SCU_18XX_43XX_H_
-#define __SCU_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SCU_18XX_43XX CHIP: LPC18xx/43xx SCU Driver (configures pin functions)
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief System Control Unit register block
- */
-typedef struct {
- __IO uint32_t SFSP[16][32];
- __I uint32_t RESERVED0[256];
- __IO uint32_t SFSCLK[4]; /*!< Pin configuration register for pins CLK0-3 */
- __I uint32_t RESERVED16[28];
- __IO uint32_t SFSUSB; /*!< Pin configuration register for USB */
- __IO uint32_t SFSI2C0; /*!< Pin configuration register for I2C0-bus pins */
- __IO uint32_t ENAIO[3]; /*!< Analog function select registerS */
- __I uint32_t RESERVED17[27];
- __IO uint32_t EMCDELAYCLK; /*!< EMC clock delay register */
- __I uint32_t RESERVED18[63];
- __IO uint32_t PINTSEL0; /*!< Pin interrupt select register for pin interrupts 0 to 3. */
- __IO uint32_t PINTSEL1; /*!< Pin interrupt select register for pin interrupts 4 to 7. */
-} LPC_SCU_Type;
-
-/** Port offset definition */
-#define PORT_OFFSET 0x80
-
-/** Pin offset definition */
-#define PIN_OFFSET 0x04
-
-/** Disable pull-down and pull-up resistor at resistor at pad */
-#define MD_PUP (0x0 << 3)
-
-/** Enable pull-down resistor at pad */
-#define MD_BUK (0x1 << 3)
-
-/** Enable pull-up resistor at pad */
-#define MD_PLN (0x2 << 3)
-
-/** Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
-#define MD_PDN (0x3 << 3)
-
-/** Enable fast slew rate */
-#define MD_EHS (0x1 << 5)
-
-/** Input buffer enable */
-#define MD_EZI (0x1 << 6)
-
-/** Disable input glitch filter */
-#define MD_ZI (0x1 << 7)
-
-/** EHD driver strength low bit */
-#define MD_EHD0 (0x1 << 8)
-
-/** EHD driver strength high bit */
-#define MD_EHD1 (0x1 << 8)
-
-#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
-
-/** Pin configuration for STANDARD/FAST mode I2C */
-#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11)
-
-/** Pin configuration for Fast-mode Plus I2C */
-#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11)
-
-#define FUNC0 0x0 /** Pin function 0 */
-#define FUNC1 0x1 /** Pin function 1 */
-#define FUNC2 0x2 /** Pin function 2 */
-#define FUNC3 0x3 /** Pin function 3 */
-#define FUNC4 0x4 /** Pin function 4 */
-#define FUNC5 0x5 /** Pin function 5 */
-#define FUNC6 0x6 /** Pin function 6 */
-#define FUNC7 0x7 /** Pin function 7 */
-
-/** Returns the SFSP register address in the SCU for a pin and port */
-#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
-
-/** Returns the address in the SCU for a SFSCLK clock register */
-#define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
-
-#define PINMUX_CLK 0xFF
-
-/**
- * @brief Configure pin function
- * @param port : Port number, should be: 0..15
- * @param pin : Pin number, should be: 0..31
- * @param mode : Pin mode, should be:
- * - MD_PUP :Pull-up enabled
- * - MD_BUK :Plain input
- * - MD_PLN :Repeater mode
- * - MD_PDN :Pull-down enabled
- * @param func : Function mode, should be: FUNC0 to FUNC7
- * @return None
- */
-void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
-
-/**
- * @brief GPIO Interrupt Pin Select
- * @param PortSel : GPIO PINTSEL interrupt, should be: 0 to 7
- * @param PortNum : GPIO port number interrupt, should be: 0 to 7
- * @param PinNum : GPIO pin number Interrupt , should be: 0 to 31
- * @return None
- */
-void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum);
-
-/**
- * @brief I2C Pin Configuration
- * @param I2C0Mode : I2C0 mode, should be:
- * - I2C0_STANDARD_FAST_MODE: Standard/Fast mode transmit
- * - I2C0_FAST_MODE_PLUS: Fast-mode Plus transmit
- * @return None
- */
-STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode)
-{
- LPC_SCU->SFSI2C0 = I2C0Mode;
-}
-
-/**
- * @brief ADC Pin Configuration
- * @param ADC_ID : ADC number
- * @param channel : ADC channel
- * @return None
- */
-STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)
-{
- LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SCU_18XX_43XX_H_ */
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c
deleted file mode 100644
index da7001311f7c10dfd4d1d53153f0b6a15175a0d9..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c
+++ /dev/null
@@ -1,597 +0,0 @@
-/*
- * @brief LPC18xx/43xx SD/SDIO driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "sdmmc_18xx_43xx.h"
-#include "string.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Global instance of the current card */
-static mci_card_struct *g_card_info;
-
-/* Helper definition: all SD error conditions in the status word */
-#define SD_INT_ERROR (MCI_INT_RESP_ERR | MCI_INT_RCRC | MCI_INT_DCRC | \
- MCI_INT_RTO | MCI_INT_DTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE | \
- MCI_INT_SBE | MCI_INT_EBE)
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Function to execute a command */
-static int32_t sdmmc_execute_command(uint32_t cmd, uint32_t arg, uint32_t wait_status)
-{
- int32_t step = (cmd & CMD_BIT_APP) ? 2 : 1;
- int32_t status = 0;
- uint32_t cmd_reg = 0;
-
- if (!wait_status) {
- wait_status = (cmd & CMD_MASK_RESP) ? MCI_INT_CMD_DONE : MCI_INT_DATA_OVER;
- }
-
- /* Clear the interrupts & FIFOs*/
- if (cmd & CMD_BIT_DATA) {
- IP_SDMMC_SetClearIntFifo(LPC_SDMMC);
- }
-
- /* also check error conditions */
- wait_status |= MCI_INT_EBE | MCI_INT_SBE | MCI_INT_HLE | MCI_INT_RTO | MCI_INT_RCRC | MCI_INT_RESP_ERR;
- if (wait_status & MCI_INT_DATA_OVER) {
- wait_status |= MCI_INT_FRUN | MCI_INT_HTO | MCI_INT_DTO | MCI_INT_DCRC;
- }
-
- while (step) {
- IP_SDMMC_SetClock(LPC_SDMMC, g_card_info->clk_rate, g_card_info->speed);
-
- /* Clear the interrupts */
- IP_SDMMC_SetRawIntStatus(LPC_SDMMC, 0xFFFFFFFF);
-
- g_card_info->evsetup_cb(wait_status);
-
- switch (step) {
- case 1: /* Execute command */
- cmd_reg = ((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) |
- ((cmd & CMD_BIT_INIT) ? MCI_CMD_INIT : 0) |
- ((cmd & CMD_BIT_DATA) ? (MCI_CMD_DAT_EXP | MCI_CMD_PRV_DAT_WAIT) : 0) |
- (((cmd & CMD_MASK_RESP) == CMD_RESP_R2) ? MCI_CMD_RESP_LONG : 0) |
- ((cmd & CMD_MASK_RESP) ? MCI_CMD_RESP_EXP : 0) |
- ((cmd & CMD_BIT_WRITE) ? MCI_CMD_DAT_WR : 0) |
- ((cmd & CMD_BIT_STREAM) ? MCI_CMD_STRM_MODE : 0) |
- ((cmd & CMD_BIT_BUSY) ? MCI_CMD_STOP : 0) |
- ((cmd & CMD_BIT_AUTO_STOP) ? MCI_CMD_SEND_STOP : 0) |
- MCI_CMD_START;
-
- /* wait for previos data finsh for select/deselect commands */
- if (((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) == MMC_SELECT_CARD) {
- cmd_reg |= MCI_CMD_PRV_DAT_WAIT;
- }
-
- /* wait for command to be accepted by CIU */
- if (IP_SDMMC_SendCmd(LPC_SDMMC, cmd_reg, arg) == 0) {
- --step;
- }
- break;
-
- case 0:
- return 0;
-
- case 2: /* APP prefix */
- cmd_reg = MMC_APP_CMD | MCI_CMD_RESP_EXP |
- ((cmd & CMD_BIT_INIT) ? MCI_CMD_INIT : 0) |
- MCI_CMD_START;
-
- if (IP_SDMMC_SendCmd(LPC_SDMMC, cmd_reg, g_card_info->rca << 16) == 0) {
- --step;
- }
- break;
- }
-
- /* wait for command response */
- status = g_card_info->waitfunc_cb();
-
- /* We return an error if there is a timeout, even if we've fetched a response */
- if (status & SD_INT_ERROR) {
- return status;
- }
-
- if (status & MCI_INT_CMD_DONE) {
- switch (cmd & CMD_MASK_RESP) {
- case 0:
- break;
-
- case CMD_RESP_R1:
- case CMD_RESP_R3:
- case CMD_RESP_R2:
- IP_SDMMC_GetResponse(LPC_SDMMC, &g_card_info->response[0]);
- break;
- }
- }
- }
-
- return 0;
-}
-
-/* Checks whether card is acquired properly or not */
-static int32_t prv_card_acquired(void)
-{
- return g_card_info->cid[0] != 0;
-}
-
-/* Helper function to get a bit field withing multi-word buffer. Used to get
- fields with-in CSD & EXT-CSD */
-static uint32_t prv_get_bits(int32_t start, int32_t end, uint32_t *data)
-{
- uint32_t v;
- uint32_t i = end >> 5;
- uint32_t j = start & 0x1f;
-
- if (i == (start >> 5)) {
- v = (data[i] >> j);
- }
- else {
- v = ((data[i] << (32 - j)) | (data[start >> 5] >> j));
- }
-
- return v & ((1 << (end - start + 1)) - 1);
-}
-
-/* Function to process the CSD & EXT-CSD of the card */
-static void prv_process_csd(void)
-{
- int32_t status = 0;
- int32_t c_size = 0;
- int32_t c_size_mult = 0;
- int32_t mult = 0;
-
- /* compute block length based on CSD response */
- g_card_info->block_len = 1 << prv_get_bits(80, 83, g_card_info->csd);
-
- if ((g_card_info->card_type & CARD_TYPE_HC) && (g_card_info->card_type & CARD_TYPE_SD)) {
- /* See section 5.3.3 CSD Register (CSD Version 2.0) of SD2.0 spec an explanation for the calculation of these values */
- c_size = prv_get_bits(48, 63, (uint32_t *) g_card_info->csd) + 1;
- g_card_info->blocknr = c_size << 10;/* 512 byte blocks */
- }
- else {
- /* See section 5.3 of the 4.1 revision of the MMC specs for an explanation for the calculation of these values */
- c_size = prv_get_bits(62, 73, (uint32_t *) g_card_info->csd);
- c_size_mult = prv_get_bits(47, 49, (uint32_t *) g_card_info->csd);
- mult = 1 << (c_size_mult + 2);
- g_card_info->blocknr = (c_size + 1) * mult;
-
- /* adjust blocknr to 512/block */
- if (g_card_info->block_len > MMC_SECTOR_SIZE) {
- g_card_info->blocknr = g_card_info->blocknr * (g_card_info->block_len >> 9);
- }
-
- /* get extended CSD for newer MMC cards CSD spec >= 4.0*/
- if (((g_card_info->card_type & CARD_TYPE_SD) == 0) &&
- (prv_get_bits(122, 125, (uint32_t *) g_card_info->csd) >= 4)) {
- /* put card in trans state */
- status = sdmmc_execute_command(CMD_SELECT_CARD, g_card_info->rca << 16, 0);
-
- /* set block size and byte count */
- IP_SDMMC_SetBlockSize(LPC_SDMMC, MMC_SECTOR_SIZE);
-
- /* send EXT_CSD command */
- IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) g_card_info->ext_csd, MMC_SECTOR_SIZE);
-
- status = sdmmc_execute_command(CMD_SEND_EXT_CSD, 0, 0 | MCI_INT_DATA_OVER);
- if ((status & SD_INT_ERROR) == 0) {
- /* check EXT_CSD_VER is greater than 1.1 */
- if ((g_card_info->ext_csd[48] & 0xFF) > 1) {
- g_card_info->blocknr = g_card_info->ext_csd[53];/* bytes 212:215 represent sec count */
-
- }
- /* switch to 52MHz clock if card type is set to 1 or else set to 26MHz */
- if ((g_card_info->ext_csd[49] & 0xFF) == 1) {
- /* for type 1 MMC cards high speed is 52MHz */
- g_card_info->speed = MMC_HIGH_BUS_MAX_CLOCK;
- }
- else {
- /* for type 0 MMC cards high speed is 26MHz */
- g_card_info->speed = MMC_LOW_BUS_MAX_CLOCK;
- }
- }
- }
- }
-
- g_card_info->device_size = g_card_info->blocknr << 9; /* blocknr * 512 */
-}
-
-/* Puts current selected card in trans state */
-static int32_t prv_set_trans_state(void)
-{
- uint32_t status;
-
- /* get current state of the card */
- status = sdmmc_execute_command(CMD_SEND_STATUS, g_card_info->rca << 16, 0);
- if (status & MCI_INT_RTO) {
- /* unable to get the card state. So return immediatly. */
- return -1;
- }
-
- /* check card state in response */
- status = R1_CURRENT_STATE(g_card_info->response[0]);
- switch (status) {
- case SDMMC_STBY_ST:
- /* put card in 'Trans' state */
- status = sdmmc_execute_command(CMD_SELECT_CARD, g_card_info->rca << 16, 0);
- if (status != 0) {
- /* unable to put the card in Trans state. So return immediatly. */
- return -1;
- }
- break;
-
- case SDMMC_TRAN_ST:
- /*do nothing */
- break;
-
- default:
- /* card shouldn't be in other states so return */
- return -1;
- }
-
- return 0;
-}
-
-/* Sets card data width and block size */
-static int32_t prv_set_card_params(void)
-{
- int32_t status;
-
-#if SDIO_BUS_WIDTH > 1
- if (g_card_info->card_type & CARD_TYPE_SD) {
- status = sdmmc_execute_command(CMD_SD_SET_WIDTH, 2, 0);
- if (status != 0) {
- return -1;
- }
-
- /* if positive response */
- IP_SDMMC_SetCardType(LPC_SDMMC, MCI_CTYPE_4BIT);
- LPC_SDMMC->CTYPE = MCI_CTYPE_4BIT;
- }
-#elif SDIO_BUS_WIDTH > 4
-#error 8-bit mode not supported yet!
-#endif
-
- /* set block length */
- IP_SDMMC_SetBlkSize(LPC_SDMMC, MMC_SECTOR_SIZE);
- status = sdmmc_execute_command(CMD_SET_BLOCKLEN, MMC_SECTOR_SIZE, 0);
- if (status != 0) {
- return -1;
- }
-
- return 0;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Returns the current SD status, clears pending ints, and disables all ints */
-uint32_t Chip_SDMMC_GetIntStatus(void)
-{
- uint32_t status;
-
- /* Get status and clear interrupts */
- status = IP_SDMMC_GetRawIntStatus(LPC_SDMMC);
- IP_SDMMC_SetRawIntStatus(LPC_SDMMC, status);
- IP_SDMMC_SetIntMask(LPC_SDMMC, 0);
-
- return status;
-}
-
-/* Get card's current state (idle, transfer, program, etc.) */
-int32_t Chip_SDMMC_GetState(void)
-{
- uint32_t status;
-
- /* get current state of the card */
- status = sdmmc_execute_command(CMD_SEND_STATUS, g_card_info->rca << 16, 0);
- if (status & MCI_INT_RTO) {
- return -1;
- }
-
- /* check card state in response */
- return (int32_t) R1_CURRENT_STATE(g_card_info->response[0]);
-}
-
-/* Function to enumerate the SD/MMC/SDHC/MMC+ cards */
-uint32_t Chip_SDMMC_Acquire(mci_card_struct *pcardinfo)
-{
- int32_t status;
- int32_t tries = 0;
- uint32_t ocr = OCR_VOLTAGE_RANGE_MSK;
- uint32_t r;
- int32_t state = 0;
- uint32_t command = 0;
-
- g_card_info = pcardinfo;
-
- /* clear card type */
- IP_SDMMC_SetCardType(LPC_SDMMC, 0);
-
- /* set high speed for the card as 20MHz */
- g_card_info->speed = MMC_MAX_CLOCK;
-
- status = sdmmc_execute_command(CMD_IDLE, 0, MCI_INT_CMD_DONE);
-
- while (state < 100) {
- switch (state) {
- case 0: /* Setup for SD */
- /* check if it is SDHC card */
- status = sdmmc_execute_command(CMD_SD_SEND_IF_COND, SD_SEND_IF_ARG, 0);
- if (!(status & MCI_INT_RTO)) {
- /* check response has same echo pattern */
- if ((g_card_info->response[0] & SD_SEND_IF_ECHO_MSK) == SD_SEND_IF_RESP) {
- ocr |= OCR_HC_CCS;
- }
- }
-
- ++state;
- command = CMD_SD_OP_COND;
- tries = INIT_OP_RETRIES;
-
- /* assume SD card */
- g_card_info->card_type |= CARD_TYPE_SD;
- g_card_info->speed = SD_MAX_CLOCK;
- break;
-
- case 10: /* Setup for MMC */
- /* start fresh for MMC crds */
- g_card_info->card_type &= ~CARD_TYPE_SD;
- status = sdmmc_execute_command(CMD_IDLE, 0, MCI_INT_CMD_DONE);
- command = CMD_MMC_OP_COND;
- tries = INIT_OP_RETRIES;
- ocr |= OCR_HC_CCS;
- ++state;
-
- /* for MMC cards high speed is 20MHz */
- g_card_info->speed = MMC_MAX_CLOCK;
- break;
-
- case 1:
- case 11:
- status = sdmmc_execute_command(command, 0, 0);
- if (status & MCI_INT_RTO) {
- state += 9; /* Mode unavailable */
- }
- else {
- ++state;
- }
- break;
-
- case 2: /* Initial OCR check */
- case 12:
- ocr = g_card_info->response[0] | (ocr & OCR_HC_CCS);
- if (ocr & OCR_ALL_READY) {
- ++state;
- }
- else {
- state += 2;
- }
- break;
-
- case 3: /* Initial wait for OCR clear */
- case 13:
- while ((ocr & OCR_ALL_READY) && --tries > 0) {
- g_card_info->msdelay_func(MS_ACQUIRE_DELAY);
- status = sdmmc_execute_command(command, 0, 0);
- ocr = g_card_info->response[0] | (ocr & OCR_HC_CCS);
- }
- if (ocr & OCR_ALL_READY) {
- state += 7;
- }
- else {
- ++state;
- }
- break;
-
- case 14:
- /* for MMC cards set high capacity bit */
- ocr |= OCR_HC_CCS;
-
- case 4: /* Assign OCR */
- tries = SET_OP_RETRIES;
- ocr &= OCR_VOLTAGE_RANGE_MSK | OCR_HC_CCS; /* Mask for the bits we care about */
- do {
- g_card_info->msdelay_func(MS_ACQUIRE_DELAY);
- status = sdmmc_execute_command(command, ocr, 0);
- r = g_card_info->response[0];
- } while (!(r & OCR_ALL_READY) && --tries > 0);
-
- if (r & OCR_ALL_READY) {
- /* is it high capacity card */
- g_card_info->card_type |= (r & OCR_HC_CCS);
- ++state;
- }
- else {
- state += 6;
- }
- break;
-
- case 5: /* CID polling */
- case 15:
- status = sdmmc_execute_command(CMD_ALL_SEND_CID, 0, 0);
- memcpy(&g_card_info->cid, &g_card_info->response[0], 16);
- ++state;
- break;
-
- case 6: /* RCA send, for SD get RCA */
- status = sdmmc_execute_command(CMD_SD_SEND_RCA, 0, 0);
- g_card_info->rca = (g_card_info->response[0]) >> 16;
- ++state;
- break;
-
- case 16: /* RCA assignment for MMC set to 1 */
- g_card_info->rca = 1;
- status = sdmmc_execute_command(CMD_MMC_SET_RCA, g_card_info->rca << 16, 0);
- ++state;
- break;
-
- case 7:
- case 17:
- status = sdmmc_execute_command(CMD_SEND_CSD, g_card_info->rca << 16, 0);
- memcpy(&g_card_info->csd, &g_card_info->response[0], 16);
- state = 100;
- break;
-
- default:
- state += 100; /* break from while loop */
- break;
- }
- }
-
- /* Compute card size, block size and no. of blocks based on CSD response recived. */
- if (prv_card_acquired()) {
- prv_process_csd();
-
- /* Setup card data width and block size (once) */
- if (prv_set_trans_state() != 0) {
- return 0;
- }
- if (prv_set_card_params() != 0) {
- return 0;
- }
- }
-
- return prv_card_acquired();
-}
-
-/* Get the device size of SD/MMC card (after enumeration) */
-int32_t Chip_SDMMC_GetDeviceSize(void)
-{
- return g_card_info->device_size;
-}
-
-/* Performs the read of data from the SD/MMC card */
-int32_t Chip_SDMMC_ReadBlocks(void *buffer, int32_t start_block, int32_t num_blocks)
-{
- int32_t cbRead = (num_blocks) * MMC_SECTOR_SIZE;
- int32_t status = 0;
- int32_t index;
-
- /* if card is not acquired return immediately */
- if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->blocknr) ) {
- return 0;
- }
-
- /* put card in trans state */
- if (prv_set_trans_state() != 0) {
- return 0;
- }
-
- /* set number of bytes to read */
- LPC_SDMMC->BYTCNT = cbRead;
-
- /* if high capacity card use block indexing */
- if (g_card_info->card_type & CARD_TYPE_HC) {
- index = start_block;
- }
- else { /*fix at 512 bytes*/
- index = start_block << 9; // \* g_card_info->block_len;
-
- }
- IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbRead);
-
- /* Select single or multiple read based on number of blocks */
- if (num_blocks == 1) {
- status = sdmmc_execute_command(CMD_READ_SINGLE, index, 0 | MCI_INT_DATA_OVER);
- }
- else {
- status = sdmmc_execute_command(CMD_READ_MULTIPLE, index, 0 | MCI_INT_DATA_OVER);
- }
-
- if (status != 0) {
- cbRead = 0;
- }
- /*Wait for card program to finish*/
- while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
-
- return cbRead;
-}
-
-/* Performs write of data to the SD/MMC card */
-int32_t Chip_SDMMC_WriteBlocks(void *buffer, int32_t start_block, int32_t num_blocks)
-{
- int32_t cbWrote = num_blocks * MMC_SECTOR_SIZE;
- int32_t status;
- int32_t index;
-
- /* if card is not acquired return immediately */
- if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->blocknr) ) {
- return 0;
- }
-
- /*Wait for card program to finish*/
- while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
-
- /* put card in trans state */
- if (prv_set_trans_state() != 0) {
- return 0;
- }
-
- /* set number of bytes to write */
- LPC_SDMMC->BYTCNT = cbWrote;
-
- /* if high capacity card use block indexing */
- if (g_card_info->card_type & CARD_TYPE_HC) {
- index = start_block;
- }
- else { /*fix at 512 bytes*/
- index = start_block << 9; // * g_card_info->block_len;
-
- }
- IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbWrote);
-
- /* Select single or multiple write based on number of blocks */
- if (num_blocks == 1) {
- status = sdmmc_execute_command(CMD_WRITE_SINGLE, index, 0 | MCI_INT_DATA_OVER);
- }
- else {
- status = sdmmc_execute_command(CMD_WRITE_MULTIPLE, index, 0 | MCI_INT_DATA_OVER);
- }
-
- /*Wait for card program to finish*/
- while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ;
-
- if (status != 0) {
- cbWrote = 0;
- }
-
- return cbWrote;
-}
diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h
deleted file mode 100644
index 70b4a02dc48b4f354cd713968d0f8ebba3871c5d..0000000000000000000000000000000000000000
--- a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h
+++ /dev/null
@@ -1,480 +0,0 @@
-/*
- * @brief LPC18xx/43xx SD/SDIO driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SDMMC_18XX_43XX_H_
-#define __SDMMC_18XX_43XX_H_
-
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SDMMC_18XX_43XX CHIP: LPC18xx/43xx SD/SDIO driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/* SD/MMC commands - this matrix shows the command, response types, and
- supported card type for that command.
- Command Number Resp SD MMC
- ----------------------- ------ ----- --- ---
- Reset (go idle) CMD0 NA x x
- Send op condition CMD1 R3 x
- All send CID CMD2 R2 x x
- Send relative address CMD3 R1 x
- Send relative address CMD3 R6 x
- Program DSR CMD4 NA x
- Select/deselect card CMD7 R1b x
- Select/deselect card CMD7 R1 x
- Send CSD CMD9 R2 x x
- Send CID CMD10 R2 x x
- Read data until stop CMD11 R1 x x
- Stop transmission CMD12 R1/b x x
- Send status CMD13 R1 x x
- Go inactive state CMD15 NA x x
- Set block length CMD16 R1 x x
- Read single block CMD17 R1 x x
- Read multiple blocks CMD18 R1 x x
- Write data until stop CMD20 R1 x
- Setblock count CMD23 R1 x
- Write single block CMD24 R1 x x
- Write multiple blocks CMD25 R1 x x
- Program CID CMD26 R1 x
- Program CSD CMD27 R1 x x
- Set write protection CMD28 R1b x x
- Clear write protection CMD29 R1b x x
- Send write protection CMD30 R1 x x
- Erase block start CMD32 R1 x
- Erase block end CMD33 R1 x
- Erase block start CMD35 R1 x
- Erase block end CMD36 R1 x
- Erase blocks CMD38 R1b x
- Fast IO CMD39 R4 x
- Go IRQ state CMD40 R5 x
- Lock/unlock CMD42 R1b x
- Application command CMD55 R1 x
- General command CMD56 R1b x
-
- *** SD card application commands - these must be preceded with ***
- *** MMC CMD55 application specific command first ***
- Set bus width ACMD6 R1 x
- Send SD status ACMD13 R1 x
- Send number WR blocks ACMD22 R1 x
- Set WR block erase cnt ACMD23 R1 x
- Send op condition ACMD41 R3 x
- Set clear card detect ACMD42 R1 x
- Send CSR ACMD51 R1 x */
-
-/** @brief SD/MMC command enumeration value.
- */
-typedef enum {
- SDMMC_IDLE, /*!< Put card in idle mode */
- MMC_SENDOP_COND, /*!< Send operating condition */
- SDMMC_ALL_SEND_CID, /*!< All cards send CID */
- SDMMC_SRA, /*!< Set relative address */
- MMC_PROGRAM_DSR, /*!< Program DSR */
- SDMMC_SELECT_CARD, /*!< Select card */
- SDMMC_SEND_CSD, /*!< Send CSD data */
- SDMMC_SEND_CID, /*!< Send CID register data (with rel. addr) */
- SDMMC_READ_UNTIL_STOP, /*!< Read data until stop */
- SDMMC_STOP_XFER, /*!< Stop current transmission */
- SDMMC_SSTAT, /*!< Send status */
- SDMMC_INACTIVE, /*!< Put card in inactive state */
- SDMMC_SET_BLEN, /*!< Set block transfer length */
- SDMMC_READ_SINGLE, /*!< Read single block */
- SDMMC_READ_MULTIPLE, /*!< Read multiple blocks */
- SDMMC_WRITE_UNTIL_STOP, /*!< Write data until stop */
- SDMMC_SET_BLOCK_COUNT, /*!< Set block count */
- SDMMC_WRITE_SINGLE, /*!< Write single block */
- SDMMC_WRITE_MULTIPLE, /*!< Write multiple blocks */
- MMC_PROGRAM_CID, /*!< Program CID */
- SDMMC_PROGRAM_CSD, /*!< Program CSD */
- SDMMC_SET_WR_PROT, /*!< Set write protection */
- SDMMC_CLEAR_WR_PROT, /*!< Clear write protection */
- SDMMC_SEND_WR_PROT, /*!< Send write protection */
- SD_ERASE_BLOCK_START, /*!< Set starting erase block */
- SD_ERASE_BLOCK_END, /*!< Set ending erase block */
- MMC_ERASE_BLOCK_START, /*!< Set starting erase block */
- MMC_ERASE_BLOCK_END, /*!< Set ending erase block */
- MMC_ERASE_BLOCKS, /*!< Erase blocks */
- MMC_FAST_IO, /*!< Fast IO */
- MMC_GO_IRQ_STATE, /*!< Go into IRQ state */
- MMC_LOCK_UNLOCK, /*!< Lock/unlock */
- SDMMC_APP_CMD, /*!< Application specific command */
- SDMMC_GEN_CMD, /*!< General purpose command */
- SDMMC_INVALID_CMD /*!< Invalid SDMMC command */
-} SDMMC_COMMAND_T;
-
-/** @brief SDMMC application specific commands for SD cards only - these
- must be preceded by the SDMMC CMD55 to work correctly.
- */
-typedef enum {
- SD_SET_BUS_WIDTH, /*!< Set the SD bus width */
- SD_SEND_STATUS, /*!< Send the SD card status */
- SD_SEND_WR_BLOCKS, /*!< Send the number of written clocks */
- SD_SET_ERASE_COUNT, /*!< Set the number of blocks to pre-erase */
- SD_SENDOP_COND, /*!< Send the OCR register (init) */
- SD_CLEAR_CARD_DET, /*!< Set or clear the 50K detect pullup */
- SD_SEND_SCR, /*!< Send the SD configuration register */
- SD_INVALID_APP_CMD /*!< Invalid SD application command */
-} SD_APP_CMD_T;
-
-/** @brief Possible SDMMC response types
- */
-typedef enum {
- SDMMC_RESPONSE_R1, /*!< Typical status */
- SDMMC_RESPONSE_R1B, /*!< Typical status with busy */
- SDMMC_RESPONSE_R2, /*!< CID/CSD registers (CMD2 and CMD10) */
- SDMMC_RESPONSE_R3, /*!< OCR register (CMD1, ACMD41) */
- SDMMC_RESPONSE_R4, /*!< Fast IO response word */
- SDMMC_RESPONSE_R5, /*!< Go IRQ state response word */
- SDMMC_RESPONSE_R6, /*!< Published RCA response */
- SDMMC_RESPONSE_NONE /*!< No response expected */
-} SDMMC_RESPONSE_T;
-
-/** @brief Possible SDMMC card state types
- */
-typedef enum {
- SDMMC_IDLE_ST = 0, /*!< Idle state */
- SDMMC_READY_ST, /*!< Ready state */
- SDMMC_IDENT_ST, /*!< Identification State */
- SDMMC_STBY_ST, /*!< standby state */
- SDMMC_TRAN_ST, /*!< transfer state */
- SDMMC_DATA_ST, /*!< Sending-data State */
- SDMMC_RCV_ST, /*!< Receive-data State */
- SDMMC_PRG_ST, /*!< Programming State */
- SDMMC_DIS_ST /*!< Disconnect State */
-} SDMMC_STATE_T;
-
-/* Standard MMC commands (3.1) type argument response */
-/* class 1 */
-#define MMC_GO_IDLE_STATE 0 /* bc */
-#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
-#define MMC_ALL_SEND_CID 2 /* bcr R2 */
-#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
-#define MMC_SET_DSR 4 /* bc [31:16] RCA */
-#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
-#define MMC_SEND_EXT_CSD 8 /* bc R1 */
-#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
-#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
-#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
-#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
-#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
-
-/* class 2 */
-#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
-#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
-#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
-
-/* class 3 */
-#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
-
-/* class 4 */
-#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
-#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
-#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
-#define MMC_PROGRAM_CID 26 /* adtc R1 */
-#define MMC_PROGRAM_CSD 27 /* adtc R1 */
-
-/* class 6 */
-#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
-#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
-#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
-
-/* class 5 */
-#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
-#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
-#define MMC_ERASE 37 /* ac R1b */
-
-/* class 9 */
-#define MMC_FAST_IO 39 /* ac