diff --git a/bsp/nuvoton_m05x/.gitignore b/bsp/nuvoton_m05x/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..bf905dfa309357f1518a66635f024d7dd85e5fc9
--- /dev/null
+++ b/bsp/nuvoton_m05x/.gitignore
@@ -0,0 +1,5 @@
+Nu_Link_Driver.ini
+*.uvoptx
+*.uvguix.*
+scons-cmd.bat
+obj
\ No newline at end of file
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/bsp/nuvoton_m05x/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..c8feab483c7aee07b235b93666803151e052e8c7
Binary files /dev/null and b/bsp/nuvoton_m05x/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf differ
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000000000000000000000000000000000..2d5fbce177982be13d13393baa8b73f58145084c
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,37 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date: 13/09/14 1:29p $Revision: V1.0.2
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.2 2010/11/11
+* Documentation updated.
+*
+* Version 1.0.1 2010/10/05
+* Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20
+* Production release and review comments incorporated.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef[6144];
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_math.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000000000000000000000000000000000..fbbe722d9576b210cbb63d2d57b26702be983b79
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * $Date: 13/09/14 1:29p $Revision: V1.1.0
+ *
+ * Project: CMSIS DSP Library
+ * Title: arm_math.h
+ *
+ * Description: Public header file for CMSIS DSP Library
+ *
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *
+ * Version 1.1.0 2012/02/15
+ * Updated with more optimizations, bug fixes and minor API changes.
+ *
+ * Version 1.0.10 2011/7/15
+ * Big Endian support added and Merged M0 and M3/M4 Source code.
+ *
+ * Version 1.0.3 2010/11/29
+ * Re-organized the CMSIS folders and updated documentation.
+ *
+ * Version 1.0.2 2010/11/11
+ * Documentation updated.
+ *
+ * Version 1.0.1 2010/10/05
+ * Production release and review comments incorporated.
+ *
+ * Version 1.0.0 2010/09/20
+ * Production release and review comments incorporated.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Pre-processor Macros
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * Toolchain Support
+ *
+ * The library has been developed and tested with MDK-ARM version 4.23.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Using the Library
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 depending on the target processor in the application.
+ *
+ * Examples
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Building the Library
+ *
+ * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM0b_math.uvproj
+ * - arm_cortexM0l_math.uvproj
+ * - arm_cortexM3b_math.uvproj
+ * - arm_cortexM3l_math.uvproj
+ * - arm_cortexM4b_math.uvproj
+ * - arm_cortexM4l_math.uvproj
+ * - arm_cortexM4bf_math.uvproj
+ * - arm_cortexM4lf_math.uvproj
+ *
+ *
+ * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above.
+ *
+ * Copyright Notice
+ *
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x800000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined (__GNUC__)
+ #define __SIMD32(addr) (*( int32_t **) & (addr))
+ #define _SIMD32_OFFSET(addr) (*( int32_t * ) (addr))
+#else
+ #define __SIMD32(addr) (*(__packed int32_t **) & (addr))
+ #define _SIMD32_OFFSET(addr) (*(__packed int32_t * ) (addr))
+#endif
+
+ #define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )
+/* No need to redefine __CLZ */
+#endif
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )
+
+ __STATIC_INLINE uint32_t __CLZ(q31_t data);
+
+
+ __STATIC_INLINE uint32_t __CLZ(q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+ */
+
+ __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+ */
+ __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0)
+
+ __STATIC_INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ __STATIC_INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) y)) +
+ ((short) x * (short) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Q15 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Initialization function for the Q15 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Q31 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Radix-2 Q31 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+
+ /**
+ * @brief Processing function for the floating-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Initialization function for the floating-point CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the floating-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Initialization function for the floating-point CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+
+ /*----------------------------------------------------------------------
+ * Internal functions prototypes FFT function
+ ----------------------------------------------------------------------*/
+
+ /**
+ * @brief Core function for the floating-point CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to the twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the floating-point CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @param[in] onebyfftLen value of 1/fftLen.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftSize length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+ * @param[in] *pBitRevTab points to the bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+ /**
+ * @brief Core function for the Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the f32 FFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of f32 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the f32 IFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of f32 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @param[in] onebyfftLen 1/fftLenfth
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+ /**
+ * @brief Core function for the Q31 CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+ /**
+ * @brief Core function for the Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+
+ /**
+ * @brief Core function for the Q15 CIFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ /**
+ * @brief Processing function for the Q15 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Initialization function for the Q15 RFFT/RIFFT.
+ * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+ */
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Q31 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Initialization function for the Q31 RFFT/RIFFT.
+ * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+ */
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Initialization function for the floating-point RFFT/RIFFT.
+ * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+ */
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the floating-point RFFT/RIFFT.
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+ __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+ __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+ __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+ /* Implementation of PID controller */
+
+#ifdef ARM_MATH_CM0
+
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+#else
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD(S->A0, in);
+
+#endif
+
+#ifdef ARM_MATH_CM0
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+
+#else
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc);
+
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ */
+
+
+ __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (x - S->x1) / xSpacing;
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if(i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+
+ __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+ #if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+ #elif (__FPU_USED == 1) && defined ( __TMS_740 )
+ *pOut = __builtin_sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+
+
+ __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+ || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20u);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20u);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return (acc << 2u);
+
+ }
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return (acc >> 36);
+
+ }
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return (acc >> 40);
+
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000000000000000000000000000000000..c048adebee3dce9fb1a6317c1c4fcd4fbf991d41
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 13. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** @addtogroup CMSIS_Definitions CMSIS
+ @{
+*/
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+/*@}*/ /* end of group CMSIS_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000000000000000000000000000000000..aa20e6879f203e09efdeefe12d96f3dfb07901c0
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,778 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
+ else {
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm3.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000000000000000000000000000000000..0173893fbd201ecdfe2a1d5bd18dc0118834dd01
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1612 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000000000000000000000000000000000..a9655374020c91e791fa60249f1e333616b709aa
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1757 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+#include /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4_simd.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000000000000000000000000000000000000..3bc7906152bdc3f578006cfe678ce1a60705c6e9
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,649 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmFunc.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3c3db5409a6eac23d06fe9df86a2af9af4dbc2ed
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,620 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+/** @addtogroup CMSIS_Definitions CMSIS
+ @{
+*/
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+/*@}*/ /* end of group CMSIS_Definitions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmInstr.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000000000000000000000000000000000..903703c74be37d9e51dcf7e99a76b0487b4f2674
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,624 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+/** @addtogroup CMSIS_Definitions CMSIS
+ @{
+*/
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+ return(op1);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+/*@}*/ /* end of group CMSIS_Definitions */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc000.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000000000000000000000000000000000..39ee60c5e526e2f01c525e1065b3afe774f3430c
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc000.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (0) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154];
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */
+ else {
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc300.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000000000000000000000000000000000..7e56b0f3322a7136ed47ee38ad024d08787703d3
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1583 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/M051Series.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/M051Series.h
new file mode 100644
index 0000000000000000000000000000000000000000..5517104abfdad149db9d388de35b9fde739f1453
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/M051Series.h
@@ -0,0 +1,6683 @@
+/**************************************************************************//**
+ * @file M051Series.h
+ * @version V3.0
+ * $Revision: 53 $
+ * $Date: 14/01/28 2:28p $
+ * @brief M051 Series Peripheral Access Layer Header File
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+
+/**
+ \mainpage Introduction
+ *
+ *
+ * This user manual describes the usage of M051DN/DE Series MCU device driver
+ *
+ * Disclaimer
+ *
+ * The Software is furnished "AS IS", without warranty as to performance or results, and
+ * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+ * warranties, express, implied or otherwise, with regard to the Software, its use, or
+ * operation, including without limitation any and all warranties of merchantability, fitness
+ * for a particular purpose, and non-infringement of intellectual property rights.
+ *
+ * Copyright Notice
+ *
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ */
+
+/**
+ * \page PG_DIR Directory Structure
+ * The BSP directory structure is shown in following figure.
+ *
+ * \image html dir.jpg "BSP Directory Structure"
+ * \image latex dir.jpg "BSP Directory Structure" width=12cm
+ *
+ * \page PG_REV Revision History
+ *
+ *
+ * Revision 3.00.001
+ * \li Initial release.
+*/
+
+#ifndef __M051Series_H__
+#define __M051Series_H__
+
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+/**
+ * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
+ */
+typedef enum IRQn
+{
+ /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+ /****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/
+ BOD_IRQn = 0, /*!< Brown-Out Low Voltage Detected Interrupt */
+ WDT_IRQn = 1, /*!< Watch Dog Timer Interrupt */
+ EINT0_IRQn = 2, /*!< EINT0 Interrupt */
+ EINT1_IRQn = 3, /*!< EINT1 Interrupt */
+ GPIO_P0P1_IRQn = 4, /*!< GPIO_P0P1 Interrupt */
+ GPIO_P2P3P4_IRQn = 5, /*!< GPIO_P2P3P4 Interrupt */
+ PWMA_IRQn = 6, /*!< PWMA Interrupt */
+ PWMB_IRQn = 7, /*!< PWMB Interrupt */
+ TMR0_IRQn = 8, /*!< TIMER0 Interrupt */
+ TMR1_IRQn = 9, /*!< TIMER1 Interrupt */
+ TMR2_IRQn = 10, /*!< TIMER2 Interrupt */
+ TMR3_IRQn = 11, /*!< TIMER3 Interrupt */
+ UART0_IRQn = 12, /*!< UART0 Interrupt */
+ UART1_IRQn = 13, /*!< UART1 Interrupt */
+ SPI0_IRQn = 14, /*!< SPI0 Interrupt */
+ SPI1_IRQn = 15, /*!< SPI1 Interrupt */
+ I2C0_IRQn = 18, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 19, /*!< I2C1 Interrupt */
+ ACMP01_IRQn = 25, /*!< ACMP0/1 Interrupt */
+ ACMP23_IRQn = 26, /*!< ACMP2/3 Interrupt */
+ PWRWU_IRQn = 28, /*!< Power Down Wake Up Interrupt */
+ ADC_IRQn = 29 /*!< ADC Interrupt */
+
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
+#include "system_M051Series.h" /*!< M051Series System */
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+/**
+ * Initialize the system clock
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system
+ * Initialize the PLL and update the SystemFrequency variable
+ */
+extern void SystemInit(void);
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+/** @addtogroup REGISTER Control Register
+
+ @{
+
+*/
+
+/*---------------------- Analog Comparator Controller -------------------------*/
+/** @addtogroup ACMP Analog Comparator Controller(ACMP)
+ Memory Mapped Structure for ACMP Controller
+ @{
+
+ */
+typedef struct
+{
+ __IO uint32_t CR[2];
+
+ __IO uint32_t SR;
+
+} ACMP_T;
+
+/** @addtogroup ACMP_CONST ACMP Bit Field Definition
+ Constant Definitions for ACMP Controller
+ @{
+ */
+
+/* ACMP_CR Bit Field Definitions */
+#define ACMP_CR_ACMPOINV_Pos 6 /*!< ACMP CR: ACMPOINV Position */
+#define ACMP_CR_ACMPOINV_Msk (1ul << ACMP_CR_ACMPOINV_Pos) /*!< ACMP CR: ACMPOINV Mask */
+
+#define ACMP_CR_NEGSEL_Pos 4 /*!< ACMP CR: NEGSEL Position */
+#define ACMP_CR_NEGSEL_Msk (1ul << ACMP_CR_NEGSEL_Pos) /*!< ACMP CR: NEGSEL Mask */
+
+#define ACMP_CR_HYSEN_Pos 2 /*!< ACMP CR: HYSEN Position */
+#define ACMP_CR_HYSEN_Msk (1ul << ACMP_CR_HYSEN_Pos) /*!< ACMP CR: HYSEN Mask */
+
+#define ACMP_CR_ACMPIE_Pos 1 /*!< ACMP CR: ACMPIE Position */
+#define ACMP_CR_ACMPIE_Msk (1ul << ACMP_CR_ACMPIE_Pos) /*!< ACMP CR: ACMPIE Mask */
+
+#define ACMP_CR_ACMPEN_Pos 0 /*!< ACMP CR: ACMPEN Position */
+#define ACMP_CR_ACMPEN_Msk (1ul << ACMP_CR_ACMPEN_Pos) /*!< ACMP CR: ACMPEN Mask */
+
+/* ACMP_SR01 Bit Field Definitions */
+#define ACMP_SR_ACMPO1_Pos 3 /*!< ACMP SR01: ACMPO1 Position */
+#define ACMP_SR_ACMPO1_Msk (1ul << ACMP_SR_ACMPO1_Pos) /*!< ACMP SR01: ACMPO1 Mask */
+
+#define ACMP_SR_ACMPO0_Pos 2 /*!< ACMP SR01: ACMPO0 Position */
+#define ACMP_SR_ACMPO0_Msk (1ul << ACMP_SR_ACMPO0_Pos) /*!< ACMP SR01: ACMPO0 Mask */
+
+#define ACMP_SR_ACMPF1_Pos 1 /*!< ACMP SR01: ACMPF1 Position */
+#define ACMP_SR_ACMPF1_Msk (1ul << ACMP_SR_ACMPF1_Pos) /*!< ACMP SR01: ACMPF1 Mask */
+
+#define ACMP_SR_ACMPF0_Pos 0 /*!< ACMP SR01: ACMPF0 Position */
+#define ACMP_SR_ACMPF0_Msk (1ul << ACMP_SR_ACMPF0_Pos) /*!< ACMP SR01: ACMPF0 Mask */
+
+/* ACMP_SR23 Bit Field Definitions */
+#define ACMP_SR_ACMPO3_Pos 3 /*!< ACMP SR23: ACMPO3 Position */
+#define ACMP_SR_ACMPO3_Msk (1ul << ACMP_SR_ACMPO3_Pos) /*!< ACMP SR23: ACMPO3 Mask */
+
+#define ACMP_SR_ACMPO2_Pos 2 /*!< ACMP SR23: ACMPO2 Position */
+#define ACMP_SR_ACMPO2_Msk (1ul << ACMP_SR_ACMPO2_Pos) /*!< ACMP SR23: ACMPO2 Mask */
+
+#define ACMP_SR_ACMPF3_Pos 1 /*!< ACMP SR23: ACMPF3 Position */
+#define ACMP_SR_ACMPF3_Msk (1ul << ACMP_SR_ACMPF3_Pos) /*!< ACMP SR23: ACMPF3 Mask */
+
+#define ACMP_SR_ACMPF2_Pos 0 /*!< ACMP SR23: ACMPF2 Position */
+#define ACMP_SR_ACMPF2_Msk (1ul << ACMP_SR_ACMPF2_Pos) /*!< ACMP SR23: ACMPF2 Mask */
+/**@}*/ /* ACMP_CONST */
+/**@}*/ /* ACMP_REG */
+
+
+/*----------------------------- ADC Controller -------------------------------*/
+/** @addtogroup ADC Analog to Digitial Converter(ADC)
+ Memory Mapped Structure for ADC Controller
+ @{
+ */
+typedef struct
+{
+ /**
+ * ADDR
+ * ===================================================================================================
+ * Offset: 0x00-0x1C A/D Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |RSLT |A/D Conversion Result
+ * | | |This field contains 12 bits conversion result.
+ * |[16] |OVERRUN |Over Run Flag
+ * | | |1 = Data in RSLT[11:0] is overwrite.
+ * | | |0 = Data in RSLT[11:0] is recent conversion result.
+ * | | |If converted data in RSLT[11:0] has not been read before new conversion result is
+ * | | |loaded to this register, OVERRUN is set to 1. It will be cleared by hardware after
+ * | | |ADDR register is read.
+ * |[17] |VALID |Valid Flag
+ * | | |1 = Data in RSLT[11:0] bits is valid.
+ * | | |0 = Data in RSLT[11:0] bits is not valid.
+ * | | |This bit is set to 1 when corresponding channel analog input conversion is completed
+ * | | |and cleared by hardware after ADDR register is read.
+ */
+ __I uint32_t ADDR[8];
+
+ /**
+ * ADCR
+ * ===================================================================================================
+ * Offset: 0x20 A/D Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADEN |A/D Converter Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * | | |Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to
+ * | | |disable A/D converter analog circuit for saving power consumption.
+ * |[1] |ADIE |A/D Interrupt Enable
+ * | | |1 = Enable A/D interrupt function
+ * | | |0 = Disable A/D interrupt function
+ * | | |A/D conversion end interrupt request is generated if ADIE bit is set to 1.
+ * |[3:2] |ADMD |A/D Converter Operation Mode
+ * | | |00 = Single conversion
+ * | | |01 = Burst conversion
+ * | | |10 = Single-cycle scan
+ * | | |11 = Continuous scan
+ * | | |When changing the operation mode, software should disable ADST bit firstly.
+ * | | |Note: In Burst Mode, the A/D result data always at Data Register 0.
+ * |[5:4] |TRGS |Hardware Trigger Source
+ * | | |00 = A/D conversion is started by external STADC pin.
+ * | | |Others = Reserved
+ * | | |Software should disable TRGE and ADST before change TRGS.
+ * | | |In hardware trigger mode, the ADST bit is set by the external trigger from STADC.
+ * |[7:6] |TRGCOND |External Trigger Condition
+ * | | |These two bits decide external pin STADC trigger event is level or edge. The signal
+ * | | |must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and
+ * | | |low state.
+ * | | |00 = Low level
+ * | | |01 = High level
+ * | | |10 = Falling edge
+ * | | |11 = Rising edge
+ * |[8] |TRGE |External Trigger Enable
+ * | | |Enable or disable triggering of A/D conversion by external STADC pin.
+ * | | |1= Enable
+ * | | |0= Disable
+ * |[10] |DIFFEN |A/D Differential Input Mode Enable
+ * | | |1 = A/D is in differential analog input mode
+ * | | |0 = A/D is in single-end analog input mode
+ * | | |Differential input voltage (Vdiff) = Vplus - Vminus
+ * | | |The Vplus of differential input paired channel 0 is from ADC0 pin; Vminus is from ADC1 pin.
+ * | | |The Vplus of differential input paired channel 1 is from ADC2 pin; Vminus is from ADC3 pin.
+ * | | |The Vplus of differential input paired channel 2 is from ADC4 pin; Vminus is from ADC5 pin.
+ * | | |The Vplus of differential input paired channel 3 is from ADC6 pin; Vminus is from ADC7 pin.
+ * | | |In differential input mode, only one of the two corresponding channels needs to be
+ * | | |enabled in ADCHER. The conversion result will be placed to the corresponding data
+ * | | |register of the enabled channel. If both channels of a differential input paired channel
+ * | | |are enabled, the ADC will convert it twice in scan mode. And then write the conversion
+ * | | |result to the two corresponding data registers.
+ * |[11] |ADST |A/D Conversion Start
+ * | | |1 = Conversion start.
+ * | | |0 = Conversion stopped and A/D converter enter idle state.
+ * | | |ADST bit can be controlled by two sources: software write and external pin STADC.
+ * | | |ADST is cleared to 0 by hardware automatically at the ends of single mode and single-
+ * | | |cycle scan mode on specified channels. In continuous scan mode, A/D conversion is
+ * | | |continuously performed sequentially until this bit is cleared to 0 or chip reset.
+ */
+ __IO uint32_t ADCR;
+
+ /**
+ * ADCHER
+ * ===================================================================================================
+ * Offset: 0x24 A/D Channel Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHEN0 |Analog Input Channel 0 Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * | | |This channel is the default enabled channel if CHEN0~7 are set as 0s.
+ * |[1] |CHEN1 |Analog Input Channel 1 Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[2] |CHEN2 |Analog Input Channel 2 Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[3] |CHEN3 |Analog Input Channel 3 Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[4] |CHEN4 |Analog Input Channel 4 Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[5] |CHEN5 |Analog Input Channel 5 Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[6] |CHEN6 |Analog Input Channel 6 Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[7] |CHEN7 |Analog Input Channel 7 Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[9:8] |PRESEL |Analog Input Channel 7 select
+ * | | |00: External analog input
+ * | | |01: Internal bandgap voltage
+ * | | |1x: Reserved
+ */
+ __IO uint32_t ADCHER;
+
+ /**
+ * ADCMPR
+ * ===================================================================================================
+ * Offset: 0x28,0x2C A/D Compare Register 0 & 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CMPEN |Compare Enable
+ * | | |1 = Enable compare.
+ * | | |0 = Disable compare.
+ * | | |Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion
+ * | | |result when converted data is loaded into ADDR register.
+ * |[1] |CMPIE |Compare Interrupt Enable
+ * | | |1 = Enable compare function interrupt.
+ * | | |0 = Disable compare function interrupt.
+ * | | |If the compare function is enabled and the compare condition matches the settings
+ * | | |of CMPCOND and CMPMATCNT, CMPF0 bit will be asserted. If CMPIE is set to
+ * | | |1, a compare interrupt request is generated.
+ * |[2] |CMPCOND |Compare Condition
+ * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is
+ * | | |greater or equal to the 12-bit CMPD(ADCMPR0[27:16]), the internal match
+ * | | |counter will increase one.
+ * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less
+ * | | |than the 12-bit CMPD(ADCMPR0[27:16]), the internal match counter will
+ * | | |increase one.
+ * | | |Note: When the internal counter reaches the value to (CMPMATCNT +1), the
+ * | | |CMPF0 bit will be set.
+ * |[5:3] |CMPCH |Compare Channel Selection
+ * | | |000 = Channel 0 conversion result is selected to be compared.
+ * | | |001 = Channel 1 conversion result is selected to be compared.
+ * | | |010 = Channel 2 conversion result is selected to be compared.
+ * | | |011 = Channel 3 conversion result is selected to be compared.
+ * | | |100 = Channel 4 conversion result is selected to be compared.
+ * | | |101 = Channel 5 conversion result is selected to be compared.
+ * | | |110 = Channel 6 conversion result is selected to be compared.
+ * | | |111 = Channel 7 conversion result is selected to be compared.
+ * |[11:8] |CMPMATCNT |Compare Match Count
+ * | | |When the specified A/D channel analog conversion result matches the compare
+ * | | |condition defined by CMPCOND[2], the internal match counter will increase 1.
+ * | | |When the internal counter reaches the value to (CMPMATCNT +1), the CMPF0 bit
+ * | | |will be set.
+ * |[27:16] |CMPD |Comparison Data
+ * | | |The 12 bits data is used to compare with conversion result of specified channel.
+ * | | |Software can use it to monitor the external analog input pin voltage transition in
+ * | | |scan mode without imposing a load on software.
+ */
+ __IO uint32_t ADCMPR[2];
+
+ /**
+ * ADSR
+ * ===================================================================================================
+ * Offset: 0x30 ADC Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADF |A/D Conversion End Flag
+ * | | |A status flag that indicates the end of A/D conversion.
+ * | | |ADF is set to 1 at these two conditions:
+ * | | |1. When A/D conversion ends in single mode
+ * | | |2. When A/D conversion ends on all specified channels in scan mode.
+ * | | |3. When more than 4 samples in FIFO in Burst mode.
+ * | | |This bit can be cleared by writing 1 to itself.
+ * |[1] |CMPF0 |Compare Flag
+ * | | |When the selected channel A/D conversion result meets the setting conditions of
+ * | | |ADCMPR0 then this bit will be set to 1. And it can be cleared by writing 1 to itself.
+ * | | |1 = Conversion result in ADDR meets ADCMPR0 setting
+ * | | |0 = Conversion result in ADDR does not meet ADCMPR0 setting
+ * |[2] |CMPF1 |Compare Flag
+ * | | |When the selected channel A/D conversion result meets the setting conditions of
+ * | | |ADCMPR1 then this bit will be set to 1. And it can be cleared by writing 1 to itself.
+ * | | |1 = Conversion result in ADDR meets ADCMPR1 setting
+ * | | |0 = Conversion result in ADDR does not meet ADCMPR1 setting
+ * |[3] |BUSY |BUSY/IDLE
+ * | | |1 = A/D converter is busy at conversion.
+ * | | |0 = A/D converter is in idle state.
+ * | | |This bit is mirror of as ADST bit in ADCR.
+ * | | |It is read only.
+ * |[6:4] |CHANNEL |Current Conversion Channel
+ * | | |This filed reflects current conversion channel when BUSY=1. When BUSY=0, it
+ * | | |shows the next channel will be converted.
+ * | | |It is read only.
+ * |[15:8] |VALID |Data Valid flag
+ * | | |It is a mirror of VALID bit in ADDRx
+ * | | |When ADC is in Burst Mode, and there is at least one valid conversion result in buffer,
+ * | | |VALID[7:0] will all set to 1.
+ * |[23:16] |OVERRUN |Over Run flag
+ * | | |It is a mirror to OVERRUN bit in ADDRx
+ * | | |When ADC is in Burst Mode, and the buffer is overrun, OVERRUN[7:0] will all set to
+ * | | |1.
+ */
+ __IO uint32_t ADSR;
+
+ __I uint32_t RESERVED0[4];
+
+ __IO uint32_t ADTDCR;
+
+} ADC_T;
+
+
+/** @addtogroup ADC_CONST ADC Bit Field Definition
+ Constant Definitions for ADC Controller
+ @{
+ */
+/* ADDR Bit Field Definitions */
+#define ADC_ADDR_VALID_Pos 17 /*!< ADC ADDR: VALID Position */
+#define ADC_ADDR_VALID_Msk (1ul << ADC_ADDR_VALID_Pos) /*!< ADC ADDR: VALID Mask */
+
+#define ADC_ADDR_OVERRUN_Pos 16 /*!< ADC ADDR: OVERRUN Position */
+#define ADC_ADDR_OVERRUN_Msk (1ul << ADC_ADDR_OVERRUN_Pos) /*!< ADC ADDR: OVERRUN Mask */
+
+#define ADC_ADDR_RSLT_Pos 0 /*!< ADC ADDR: RSLT Position */
+#define ADC_ADDR_RSLT_Msk (0xFFFFul << ADC_ADDR_RSLT_Pos) /*!< ADC ADDR: RSLT Mask */
+
+/* ADCR Bit Field Definitions */
+#define ADC_ADCR_DMOF_Pos 31 /*!< ADC ADCR: DMOF Position */
+#define ADC_ADCR_DMOF_Msk (1ul << ADC_ADCR_DMOF_Pos) /*!< ADC ADCR: DMOF Mask */
+
+#define ADC_ADCR_ADST_Pos 11 /*!< ADC ADCR: ADST Position */
+#define ADC_ADCR_ADST_Msk (1ul << ADC_ADCR_ADST_Pos) /*!< ADC ADCR: ADST Mask */
+
+#define ADC_ADCR_DIFFEN_Pos 10 /*!< ADC ADCR: DIFFEN Position */
+#define ADC_ADCR_DIFFEN_Msk (1ul << ADC_ADCR_DIFFEN_Pos) /*!< ADC ADCR: DIFFEN Mask */
+
+#define ADC_ADCR_TRGEN_Pos 8 /*!< ADC ADCR: TRGEN Position */
+#define ADC_ADCR_TRGEN_Msk (1ul << ADC_ADCR_TRGEN_Pos) /*!< ADC ADCR: TRGEN Mask */
+
+#define ADC_ADCR_TRGCOND_Pos 6 /*!< ADC ADCR: TRGCOND Position */
+#define ADC_ADCR_TRGCOND_Msk (3ul << ADC_ADCR_TRGCOND_Pos) /*!< ADC ADCR: TRGCOND Mask */
+
+#define ADC_ADCR_TRGS_Pos 4 /*!< ADC ADCR: TRGS Position */
+#define ADC_ADCR_TRGS_Msk (3ul << ADC_ADCR_TRGS_Pos) /*!< ADC ADCR: TRGS Mask */
+
+#define ADC_ADCR_ADMD_Pos 2 /*!< ADC ADCR: ADMD Position */
+#define ADC_ADCR_ADMD_Msk (3ul << ADC_ADCR_ADMD_Pos) /*!< ADC ADCR: ADMD Mask */
+
+#define ADC_ADCR_ADIE_Pos 1 /*!< ADC ADCR: ADIE Position */
+#define ADC_ADCR_ADIE_Msk (1ul << ADC_ADCR_ADIE_Pos) /*!< ADC ADCR: ADIE Mask */
+
+#define ADC_ADCR_ADEN_Pos 0 /*!< ADC ADCR: ADEN Position */
+#define ADC_ADCR_ADEN_Msk (1ul << ADC_ADCR_ADEN_Pos) /*!< ADC ADCR: ADEN Mask */
+
+/* ADCHER Bit Field Definitions */
+#define ADC_ADCHER_PRESEL_Pos 8 /*!< ADC ADCHER: PRESEL Position */
+#define ADC_ADCHER_PRESEL_Msk (3ul << ADC_ADCHER_PRESEL_Pos) /*!< ADC ADCHER: PRESEL Mask */
+
+#define ADC_ADCHER_CHEN_Pos 0 /*!< ADC ADCHER: CHEN Position */
+#define ADC_ADCHER_CHEN_Msk (0xFFul << ADC_ADCHER_CHEN_Pos) /*!< ADC ADCHER: CHEN Mask */
+
+/* ADCMPR Bit Field Definitions */
+#define ADC_ADCMPR_CMPD_Pos 16 /*!< ADC ADCMPR: CMPD Position */
+#define ADC_ADCMPR_CMPD_Msk (0xFFFul << ADC_ADCMPR_CMPD_Pos) /*!< ADC ADCMPR: CMPD Mask */
+
+#define ADC_ADCMPR_CMPMATCNT_Pos 8 /*!< ADC ADCMPR: CMPMATCNT Position */
+#define ADC_ADCMPR_CMPMATCNT_Msk (0xFul << ADC_ADCMPR_CMPMATCNT_Pos) /*!< ADC ADCMPR: CMPMATCNT Mask */
+
+#define ADC_ADCMPR_CMPCH_Pos 3 /*!< ADC ADCMPR: CMPCH Position */
+#define ADC_ADCMPR_CMPCH_Msk (7ul << ADC_ADCMPR_CMPCH_Pos) /*!< ADC ADCMPR: CMPCH Mask */
+
+#define ADC_ADCMPR_CMPCOND_Pos 2 /*!< ADC ADCMPR: CMPCOND Position */
+#define ADC_ADCMPR_CMPCOND_Msk (1ul << ADC_ADCMPR_CMPCOND_Pos) /*!< ADC ADCMPR: CMPCOND Mask */
+
+#define ADC_ADCMPR_CMPIE_Pos 1 /*!< ADC ADCMPR: CMPIE Position */
+#define ADC_ADCMPR_CMPIE_Msk (1ul << ADC_ADCMPR_CMPIE_Pos) /*!< ADC ADCMPR: CMPIE Mask */
+
+#define ADC_ADCMPR_CMPEN_Pos 0 /*!< ADC ADCMPR: CMPEN Position */
+#define ADC_ADCMPR_CMPEN_Msk (1ul << ADC_ADCMPR_CMPEN_Pos) /*!< ADC ADCMPR: CMPEN Mask */
+
+/* ADSR Bit Field Definitions */
+#define ADC_ADSR_OVERRUN_Pos 16 /*!< ADC ADSR: OVERRUN Position */
+#define ADC_ADSR_OVERRUN_Msk (0xFFul << ADC_ADSR_OVERRUN_Pos) /*!< ADC ADSR: OVERRUN Mask */
+
+#define ADC_ADSR_VALID_Pos 8 /*!< ADC ADSR: VALID Position */
+#define ADC_ADSR_VALID_Msk (0xFFul << ADC_ADSR_VALID_Pos) /*!< ADC ADSR: VALID Mask */
+
+#define ADC_ADSR_CHANNEL_Pos 4 /*!< ADC ADSR: CHANNEL Position */
+#define ADC_ADSR_CHANNEL_Msk (7ul << ADC_ADSR_CHANNEL_Pos) /*!< ADC ADSR: CHANNEL Mask */
+
+#define ADC_ADSR_BUSY_Pos 3 /*!< ADC ADSR: BUSY Position */
+#define ADC_ADSR_BUSY_Msk (1ul << ADC_ADSR_BUSY_Pos) /*!< ADC ADSR: BUSY Mask */
+
+#define ADC_ADSR_CMPF1_Pos 2 /*!< ADC ADSR: CMPF1 Position */
+#define ADC_ADSR_CMPF1_Msk (1ul << ADC_ADSR_CMPF1_Pos) /*!< ADC ADSR: CMPF1 Mask */
+
+#define ADC_ADSR_CMPF0_Pos 1 /*!< ADC ADSR: CMPF0 Position */
+#define ADC_ADSR_CMPF0_Msk (1ul << ADC_ADSR_CMPF0_Pos) /*!< ADC ADSR: CMPF0 Mask */
+
+#define ADC_ADSR_ADF_Pos 0 /*!< ADC ADSR: ADF Position */
+#define ADC_ADSR_ADF_Msk (1ul << ADC_ADSR_ADF_Pos) /*!< ADC ADSR: ADF Mask */
+
+/* ADTDCR Bit Field Definitions */
+#define ADC_ADTDCR_PTDT_Pos 0 /*!< ADC ADTDCR: PTDT Position */
+#define ADC_ADTDCR_PTDT_Msk (0xFFul << ADC_ADTDCR_PTDT_Pos) /*!< ADC ADTDCR: PTDT Mask */
+/**@}*/ /* ADC_CONST */
+/**@}*/ /* ADC */
+
+
+
+/*----------------------- Hardware Divider Interface Controller ------------------*/
+/** @addtogroup HDIV Hardware Divider(HDIV)
+ Memory Mapped Structure for Divider Interface Controller
+ @{
+ */
+typedef struct
+{
+ /**
+ * DIVIDEND
+ * ===================================================================================================
+ * Offset: 0x00 Dividend Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DIVIDEND |Dividend Source.
+ * | | |This register is given the dividend of divider before calculation starts.
+ */
+ __IO int32_t DIVIDEND;
+
+ /**
+ * DIVISOR
+ * ===================================================================================================
+ * Offset: 0x04 Divisor Source Resister
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DIVISOR |Divisor Source.
+ * | | |This register is given the divisor of divider before calculation starts.
+ * | | |Note: when this register is written, hardware divider will start calculate
+ */
+ __IO int32_t DIVISOR;
+
+ /**
+ * DIVQUO
+ * ===================================================================================================
+ * Offset: 0x08 Quotient Result Resister
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |QUOTIENT |Quotient Result
+ * | | |This register holds the quotient result of divider after calculation complete.
+ */
+ __IO int32_t DIVQUO;
+
+ /**
+ * DIVREM
+ * ===================================================================================================
+ * Offset: 0x08 Reminder Result Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |QUOTIENT |Reminder Result
+ * | | |This register holds the reminder result of divider after calculation complete.
+ */
+ __IO int32_t DIVREM;
+
+ /**
+ * DIVSTS
+ * ===================================================================================================
+ * Offset: 0x08 Divider Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DIV_FINISH|Divider operation finished.
+ * | | |0 = The divider calculation is not yet.
+ * | | |1 = The divider calculation is finished.
+ * | | |This register is read only.
+ * |[1] |DIV0 |Divisor zero warning.
+ * | | |0 = The divisor is not 0.
+ * | | |1 = The divisor is 0.
+ * | | |This register is read only.
+ */
+ __IO uint32_t DIVSTS;
+
+} HDIV_T;
+
+
+/** @addtogroup HDIV_CONST HDIV Bit Field Definition
+ Constant Definitions for HDIV Controller
+ @{
+ */
+
+#define HDIV_DIVSTS_DIV_FINISH_Pos 0
+#define HDIV_DIVSTS_DIV_FINISH_Msk (1ul << HDIV_DIVSTS_DIV_FINISH_Pos)
+
+#define HDIV_DIVSTS_DIV0_Pos 1
+#define HDIV_DIVSTS_DIV0_Msk (1ul << HDIV_DIVSTS_DIV0_Pos)
+
+/**@}*/ /* HDIV_CONST */
+/**@}*/ /* DIV */
+
+
+
+/*----------------------- External Bus Interface Controller ------------------*/
+/** @addtogroup EBI External Bus Interface(EBI)
+ Memory Mapped Structure for External Bus Interface Controller
+ @{
+ */
+typedef struct
+{
+ /**
+ * EBICON
+ * ===================================================================================================
+ * Offset: 0x00 EBI Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ExtEN |EBI Enable
+ * | | |This bit is the functional enable bit for EBI.
+ * | | |0 = EBI function is disabled
+ * | | |1 = EBI function is enabled
+ * |[1] |ExtBW16 |EBI data width 16 bit
+ * | | |This bit defines if the data bus is 8-bit or 16-bit.
+ * | | |0 = EBI data width is 8 bit
+ * | | |1 = EBI data width is 16 bit
+ * |[10:8] |MCLKDIV |External Output Clock Divider
+ * | | |The frequency of EBI output clock is controlled by MCLKDIV.
+ * | | |000 = HCLK/1
+ * | | |001 = HCLK/2
+ * | | |010 = HCLK/4
+ * | | |011 = HCLK/8
+ * | | |100 = HCLK/16
+ * | | |101 = HCKL/32
+ * | | |11X = default
+ * | | |Notice: Default value of output clock is HCLK/1
+ * |[18:16] |ExttALE |Expand Time of ALE
+ * | | |The ALE width (tALE) to latch the address can be controlled by ExttALE.
+ * | | |tALE = (ExttALE + 1) * MCLK
+ */
+ __IO uint32_t EBICON;
+
+ /**
+ * EXTIME
+ * ===================================================================================================
+ * Offset: 0x04 EBI Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:3] |ExttACC |EBI Data Accesss Time
+ * | | |ExttACC define data access time (tACC).
+ * | | |tACC = (ExttACC + 1) * MCLK
+ * |[10:8] |ExttAHD |EBI Data Access Hold Time
+ * | | |ExttAHD define data access hold time (tAHD).
+ * | | |tAHD = (ExttAHD + 1) * MCLK
+ * |[15:12] |ExtIW2X |Idle State Cycle After Write
+ * | | |When write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero.
+ * | | |Idle state cycle = (ExtIW2X * MCLK)
+ * |[27:24] |ExtIR2R |Idle State Cycle Between Read-Read
+ * | | |When read action is finish and next action is going to read, idle state is inserted and nCS return
+ * | | |to high if ExtIR2R is not zero.
+ * | | |Idle state cycle = (ExtIR2R * MCLK)
+ */
+ __IO uint32_t EXTIME;
+
+ /**
+ * EBICON2
+ * ===================================================================================================
+ * Offset: 0x08 External Bus Interface General Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __IO uint32_t EBICON2;
+} EBI_T;
+
+
+/** @addtogroup EBI_CONST EBI Bit Field Definition
+ Constant Definitions for EBI Controller
+ @{
+ */
+/* EBI EBICON Bit Field Definitions */
+#define EBI_EBICON_ExttALE_Pos 16 /*!< EBI EBICON: ExttALE Position */
+#define EBI_EBICON_ExttALE_Msk (0x7ul << EBI_EBICON_ExttALE_Pos) /*!< EBI EBICON: ExttALE Mask */
+
+#define EBI_EBICON_MCLKDIV_Pos 8 /*!< EBI EBICON: MCLKDIV Position */
+#define EBI_EBICON_MCLKDIV_Msk (0x7ul << EBI_EBICON_MCLKDIV_Pos) /*!< EBI EBICON: MCLKDIV Mask */
+
+#define EBI_EBICON_ExtBW16_Pos 1 /*!< EBI EBICON: ExtBW16 Position */
+#define EBI_EBICON_ExtBW16_Msk (1ul << EBI_EBICON_ExtBW16_Pos) /*!< EBI EBICON: ExtBW16 Mask */
+
+#define EBI_EBICON_ExtEN_Pos 0 /*!< EBI EBICON: ExtEN Position */
+#define EBI_EBICON_ExtEN_Msk (1ul << EBI_EBICON_ExtEN_Pos) /*!< EBI EBICON: ExtEN Mask */
+
+/* EBI EXTIME Bit Field Definitions */
+#define EBI_EXTIME_ExtIR2R_Pos 24 /*!< EBI EXTIME: ExtIR2R Position */
+#define EBI_EXTIME_ExtIR2R_Msk (0xFul << EBI_EXTIME_ExtIR2R_Pos) /*!< EBI EXTIME: ExtIR2R Mask */
+
+#define EBI_EXTIME_ExtIW2X_Pos 12 /*!< EBI EXTIME: ExtIW2X Position */
+#define EBI_EXTIME_ExtIW2X_Msk (0xFul << EBI_EXTIME_ExtIW2X_Pos) /*!< EBI EXTIME: ExtIW2X Mask */
+
+#define EBI_EXTIME_ExttAHD_Pos 8 /*!< EBI EXTIME: ExttAHD Position */
+#define EBI_EXTIME_ExttAHD_Msk (0x7ul << EBI_EXTIME_ExttAHD_Pos) /*!< EBI EXTIME: ExttAHD Mask */
+
+#define EBI_EXTIME_ExttACC_Pos 3 /*!< EBI EXTIME: ExttACC Position */
+#define EBI_EXTIME_ExttACC_Msk (0x1Ful << EBI_EXTIME_ExttACC_Pos) /*!< EBI EXTIME: ExttACC Mask */
+
+/* EBI EBICON2 Bit Field Definitions */
+#define EBI_EBICON2_WAHD_OFF_Pos 2 /*!< EBI EBICON2: WAHD_OFF Position */
+#define EBI_EBICON2_WAHD_OFF_Msk (1ul << EBI_EBICON2_WAHD_OFF_Pos) /*!< EBI EBICON2: WAHD_OFF Mask */
+
+#define EBI_EBICON2_RAHD_OFF_Pos 1 /*!< EBI EBICON2: RAHD_OFF Position */
+#define EBI_EBICON2_RAHD_OFF_Msk (1ul << EBI_EBICON2_RAHD_OFF_Pos) /*!< EBI EBICON2: RAHD_OFF Mask */
+
+#define EBI_EBICON2_WBUFF_EN_Pos 0 /*!< EBI EBICON2: WBUFF_EN Position */
+#define EBI_EBICON2_WBUFF_EN_Msk (1ul << EBI_EBICON2_WBUFF_EN_Pos) /*!< EBI EBICON2: WBUFF_EN Mask */
+/**@}*/ /* EBI_CONST */
+/**@}*/ /* EBI */
+
+
+
+
+/*-------------------------- FLASH Memory Controller -------------------------*/
+
+/** @addtogroup FMC Flash Memory Controller(FMC)
+ *
+ * Memory Mapped Structure for Flash Memory Controller
+ * @{
+ */
+typedef struct
+{
+ /**
+ * ISPCON
+ * ===================================================================================================
+ * Offset: 0x00 ISP Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPEN |ISP Enable
+ * | | |This bit is protected bit. ISP function enable bit. Set this bit to enable ISP function.
+ * | | |1 = Enable ISP function
+ * | | |0 = Disable ISP function
+ * |[1] |BS |Boot Select
+ * | | |This bit is protected bit. Set/clear this bit to select next booting from LDROM/APROM,
+ * | | |respectively. This bit also functions as MCU booting status flag, which can be used to check where
+ * | | |MCU booted from. This bit is initiated with the inversed value of CBS in Config0 after power-
+ * | | |on reset; It keeps the same value at other reset.
+ * | | |1 = boot from LDROM
+ * | | |0 = boot from APROM
+ * |[3] |APUEN |APROM Update Enable (write-protected)
+ * | | |1 = APROM can be updated when the chip runs in APROM
+ * | | |0 = APROM can not be updated when the chip runs in APROM
+ * |[4] |CFGUEN |Config Update Enable
+ * | | |Writing this bit to 1 enables s/w to update Config value by ISP procedure regardless of program
+ * | | |code is running in APROM or LDROM.
+ * | | |1 = Config update enable
+ * | | |0 = Config update disable
+ * |[5] |LDUEN |LDROM Update Enable
+ * | | |LDROM update enable bit.
+ * | | |1 = LDROM can be updated when the MCU runs in APROM.
+ * | | |0 = LDROM cannot be updated
+ * |[6] |ISPFF |ISP Fail Flag
+ * | | |(1) APROM writes to itself.
+ * | | |(2) LDROM writes to itself.
+ * | | |(3) CONFIG is erased/programmed when CFGUEN is set to 0
+ * | | |(4) Destination address is illegal, such as over an available range.
+ * | | |Write 1 to clear this bit.
+ */
+ __IO uint32_t ISPCON;
+
+ /**
+ * ISPADR
+ * ===================================================================================================
+ * Offset: 0x04 ISP Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPADR |ISP Address
+ * | | |NuMicro M051 series equips with a maximum 16kx32 embedded flash, it supports word program
+ * | | |only. ISPARD[1:0] must be kept 2'b00 for ISP operation.
+ */
+ __IO uint32_t ISPADR;
+
+ /**
+ * ISPDAT
+ * ===================================================================================================
+ * Offset: 0x08 ISP Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT |ISP Data
+ * | | |Write data to this register before ISP program operation
+ * | | |Read data from this register after ISP read operation
+ */
+ __IO uint32_t ISPDAT;
+
+ /**
+ * ISPCMD
+ * ===================================================================================================
+ * Offset: 0x0C ISP Command Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |FOEN_FCEN_FCTRL|ISP Command
+ * | | |ISP command table is shown below:
+ * | | |Operation Mode, FOEN, FCEN, FCTRL[3:0]
+ * | | |Read , 0, 0, 0000
+ * | | |Program , 1, 0, 0001
+ * | | |Page Erase , 1, 0, 0010
+ */
+ __IO uint32_t ISPCMD;
+
+ /**
+ * ISPTRG
+ * ===================================================================================================
+ * Offset: 0x10 IISP Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPGO |ISP start trigger
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP
+ * | | |operation is finish.
+ * | | |1 = ISP is on going
+ * | | |0 = ISP done
+ */
+ __IO uint32_t ISPTRG;
+
+ /**
+ * DFBADR
+ * ===================================================================================================
+ * Offset: 0x14 Data Flash Base Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DFBA |Data Flash Base Address
+ * | | |This register indicates data flash start address.
+ * | | |It is a read only register.
+ * | | |For 8/16/32/64kB flash memory device, the data flash size is 4kB and it start address is fixed at
+ * | | |0x01F000 by hardware internally.
+ */
+ __I uint32_t DFBADR;
+
+ /**
+ * FATCON
+ * ===================================================================================================
+ * Offset: 0x18 Flash Access Time Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4] |LFOM |Low Frequency Optimization Mode (write-protected)
+ * | | |1 = Flash access always no wait state (zero wait state)
+ * | | |0 = Insert wait state while Flash access discontinued address.
+ * | | |Note: Set this bit only when HCLK <= 25MHz. If HCLK > 25MHz, CPU will fetch wrong
+ * | | |code and cause fail result.
+ */
+ __IO uint32_t FATCON;
+
+ __I uint32_t Reserved[9];
+
+ /**
+ * ISPSTA
+ * ===================================================================================================
+ * Offset: 0x40 ISP Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPGO |ISP Start Trigger (Read Only)
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware
+ * | | |automatically when ISP operation is finished.
+ * | | |1 = ISP operation progressed.
+ * | | |0 = ISP operation finished.
+ * | | |Note: This bit is the same as ISPTRG bit0
+ * |[2:1] |CBS |Chip Boot Selection (Read Only)
+ * | | |This is a mirror of CBS in Config0.
+ * |[6] |ISPFF |ISP Fail Flag (Write-protection Bit)
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself.
+ * | | |(2) LDROM writes to itself.
+ * | | |(3) CONFIG is erased/programmed when CFGUEN is set to 0
+ * | | |(4) Destination address is illegal, such as over an available range.
+ * |[20:9] |VECMAP |Vector Page Mapping Address (Read Only)
+ * | | |The current flash address space 0x0000_0000~0x0000_01FF is mapping to the address
+ * | | |specified by the VECMAP * 512.
+ */
+ __IO uint32_t ISPSTA;
+
+} FMC_T;
+
+/** @addtogroup FMC_CONST FMC Bit Field Definition
+ Constant Definitions for FMC Controller
+ @{
+ */
+/* FMC ISPCON Bit Field Definitions */
+#define FMC_ISPCON_ISPFF_Pos 6 /*!< FMC ISPCON: ISPFF Position */
+#define FMC_ISPCON_ISPFF_Msk (1ul << FMC_ISPCON_ISPFF_Pos) /*!< FMC ISPCON: ISPFF Mask */
+
+#define FMC_ISPCON_LDUEN_Pos 5 /*!< FMC ISPCON: LDUEN Position */
+#define FMC_ISPCON_LDUEN_Msk (1ul << FMC_ISPCON_LDUEN_Pos) /*!< FMC ISPCON: LDUEN Mask */
+
+#define FMC_ISPCON_CFGUEN_Pos 4 /*!< FMC ISPCON: CFGUEN Position */
+#define FMC_ISPCON_CFGUEN_Msk (1ul << FMC_ISPCON_CFGUEN_Pos) /*!< FMC ISPCON: CFGUEN Mask */
+
+#define FMC_ISPCON_APUEN_Pos 3 /*!< FMC ISPCON: APUEN Position */
+#define FMC_ISPCON_APUEN_Msk (1ul << FMC_ISPCON_APUEN_Pos) /*!< FMC ISPCON: APUEN Mask */
+
+#define FMC_ISPCON_BS_Pos 1 /*!< FMC ISPCON: BS Position */
+#define FMC_ISPCON_BS_Msk (1ul << FMC_ISPCON_BS_Pos) /*!< FMC ISPCON: BS Mask */
+
+#define FMC_ISPCON_ISPEN_Pos 0 /*!< FMC ISPCON: ISPEN Position */
+#define FMC_ISPCON_ISPEN_Msk (1ul << FMC_ISPCON_ISPEN_Pos) /*!< FMC ISPCON: ISPEN Mask */
+
+
+/* FMC ISPCMD Bit Field Definitions */
+#define FMC_ISPCMD_FOEN_Pos 5 /*!< FMC ISPCMD: FOEN Position */
+#define FMC_ISPCMD_FOEN_Msk (1ul << FMC_ISPCMD_FOEN_Pos) /*!< FMC ISPCMD: FOEN Mask */
+
+#define FMC_ISPCMD_FCEN_Pos 4 /*!< FMC ISPCMD: FCEN Position */
+#define FMC_ISPCMD_FCEN_Msk (1ul << FMC_ISPCMD_FCEN_Pos) /*!< FMC ISPCMD: FCEN Mask */
+
+#define FMC_ISPCMD_FCTRL_Pos 0 /*!< FMC ISPCMD: FCTRL Position */
+#define FMC_ISPCMD_FCTRL_Msk (0xFul << FMC_ISPCMD_FCTRL_Pos) /*!< FMC ISPCMD: FCTRL Mask */
+
+/* FMC ISPTRG Bit Field Definitions */
+#define FMC_ISPTRG_ISPGO_Pos 0 /*!< FMC ISPTRG: ISPGO Position */
+#define FMC_ISPTRG_ISPGO_Msk (1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC ISPTRG: ISPGO Mask */
+
+/* FMC FATCON Bit Field Definitions */
+#define FMC_FATCON_LFOM_Pos 4 /*!< FMC FATCON: LFOM Position */
+#define FMC_FATCON_LFOM_Msk (1ul << FMC_FATCON_LFOM_Pos) /*!< FMC FATCON: LFOM Mask */
+
+/* FMC ISPSTA Bit Field Definitions */
+#define FMC_ISPSTA_ISPGO_Pos 0 /*!< FMC ISPSTA: ISPGO Position */
+#define FMC_ISPSTA_ISPGO_Msk (1ul << FMC_ISPSTA_ISPGO_Pos) /*!< FMC ISPSTA: ISPGO Mask */
+
+#define FMC_ISPSTA_CBS_Pos 1 /*!< FMC ISPSTA: CBS Position */
+#define FMC_ISPSTA_CBS_Msk (3ul << FMC_ISPSTA_CBS_Pos) /*!< FMC ISPSTA: CBS Mask */
+
+#define FMC_ISPSTA_ISPFF_Pos 6 /*!< FMC ISPSTA: ISPFF Position */
+#define FMC_ISPSTA_ISPFF_Msk (1ul << FMC_ISPSTA_ISPFF_Pos) /*!< FMC ISPSTA: ISPFF Mask */
+
+#define FMC_ISPSTA_VECMAP_Pos 9 /*!< FMC ISPSTA: VECMAP Position */
+#define FMC_ISPSTA_VECMAP_Msk (0xffful << FMC_ISPSTA_VECMAP_Pos) /*!< FMC ISPSTA: VECMAP Mask */
+/**@}*/ /* FMC_CONST */
+/**@}*/ /* FMC */
+
+/*---------------------------- Global Controller -----------------------------*/
+
+/** @addtogroup GCR System Global Contoller(SYS)
+ Memory Mapped Structure for System Global Controller
+ @{
+ */
+typedef struct
+{
+ /**
+ * PDID
+ * ===================================================================================================
+ * Offset: 0x00 Part Device Identification Number Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDID |This register reflects device part number code. S/W can read this register to identify which device is
+ * | | |used.
+ */
+ __I uint32_t PDID;
+
+ /**
+ * RSTSRC
+ * ===================================================================================================
+ * Offset: 0x04 System Reset Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:8] |Reserved |Reserved
+ * |[7] |RSTS_CPU |The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).
+ * | | |1 = The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1.
+ * | | |0 = No reset from CPU
+ * | | |Software can write 1 to clear this bit to zero.
+ * |[6] |Reserved |Reserved
+ * |[5] |RSTS_MCU |The RSTS_MCU flag is set by the "reset signal" from the MCU Cortex_M0 kernel to indicate the previous reset source.
+ * | | |1= The MCU Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel.
+ * | | |0= No reset from MCU
+ * | | |This bit is cleared by writing 1 to itself.
+ * |[4] |RSTS_BOD |The RSTS_BOD flag is set by the "reset signal" from the Brown-Out Detector to indicate the previous reset source.
+ * | | |1= The Brown-Out Detector module had issued the reset signal to reset the system.
+ * | | |0= No reset from BOD
+ * | | |Software can write 1 to clear this bit to zero.
+ * |[3] |RSTS_LVR |The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset controller to indicate the previous reset source.
+ * | | |1= The LVR module had issued the reset signal to reset the system.
+ * | | |0= No reset from LVR
+ * | | |Software can write 1 to clear this bit to zero.
+ * |[2] |RSTS_WDT |The RSTS_WDT flag is set by the "reset signal" from the Watchdog timer to indicate the previous reset source.
+ * | | |1= The Watchdog timer had issued the reset signal to reset the system.
+ * | | |0= No reset from Watchdog timer
+ * | | |Software can write 1 to clear this bit to zero.
+ * |[1] |RSTS_RESET|The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source.
+ * | | |1= The Pin /RESET had issued the reset signal to reset the system.
+ * | | |0= No reset from Pin /RESET
+ * | | |Software can write 1 to clear this bit to zero.
+ * |[0] |RSTS_POR |The RSTS_POR flag is set by the "reset signal", which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) is set, to indicate the previous reset source.
+ * | | |1= The Power-On-Reset (POR) or CHIP_RST had issued the reset signal to reset the system.
+ * | | |0= No reset from POR or CHIP_RST
+ * | | |Software can write 1 to clear this bit to zero.
+ */
+ __IO uint32_t RSTSRC;
+
+ /**
+ * IPRSTC1
+ * ===================================================================================================
+ * Offset: 0x08 Peripheral Reset Control Resister 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHIP_RST |CHIP one shot reset.
+ * | | |Set this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will
+ * | | |automatically return to "0" after the 2 clock cycles.
+ * | | |The CHIP_RST is same as the POR reset , all the chip module is reset and the chip setting from
+ * | | |flash are also reload
+ * | | |This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to
+ * | | |address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA
+ * | | |+ 0x100
+ * | | |0= Normal
+ * | | |1= Reset CHIP
+ * |[1] |CPU_RST |CPU kernel one shot reset.
+ * | | |Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit will
+ * | | |automatically return to "0" after the 2 clock cycles
+ * | | |This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to
+ * | | |address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA
+ * | | |+ 0x100
+ * | | |0= Normal
+ * | | |1= Reset CPU
+ * |[3] |EBI_RST |EBI Controller Reset
+ * | | |Set these bit "1" will generate a reset signal to the EBI. User need to set this bit to "0" to release
+ * | | |from the reset state
+ * | | |This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to
+ * | | |address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA
+ * | | |+ 0x100
+ * | | |0= Normal operation
+ * | | |1= EBI IP reset
+ */
+ __IO uint32_t IPRSTC1;
+
+ /**
+ * IPRSTC2
+ * ===================================================================================================
+ * Offset: 0x0C Peripheral Reset Control Resister 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |GPIO_RST |GPIO (P0~P4) controller Reset
+ * | | |0= GPIO controller normal operation
+ * | | |1= GPIO controller reset
+ * |[2] |TMR0_RST |Timer0 controller Reset
+ * | | |0= Timer0 controller normal operation
+ * | | |1= Timer0 controller reset
+ * |[3] |TMR1_RST |Timer1 controller Reset
+ * | | |0= Timer1 controller normal operation
+ * | | |1= Timer1 controller reset
+ * |[4] |TMR2_RST |Timer2 controller Reset
+ * | | |0= Timer2 controller normal operation
+ * | | |1= Timer2 controller reset
+ * |[5] |TMR3_RST |Timer3 controller Reset
+ * | | |0= Timer3 controller normal operation
+ * | | |1= Timer3 controller reset
+ * |[8] |I2C_RST |I2C controller Reset
+ * | | |0= I2C controller normal operation
+ * | | |1= I2C controller reset
+ * |[12] |SPI0_RST |SPI0 controller Reset
+ * | | |0= SPI0 controller normal operation
+ * | | |1= SPI0 controller reset
+ * |[13] |SPI1_RST |SPI1 controller Reset
+ * | | |0= SPI1 controller normal operation
+ * | | |1= SPI1 controller reset
+ * |[16] |UART0_RST |UART0 controller Reset
+ * | | |0= UART0 controller Normal operation
+ * | | |1= UART0 controller reset
+ * |[17] |UART1_RST |UART1 controller Reset
+ * | | |0 = UART1 controller normal operation
+ * | | |1 = UART1 controller reset
+ * |[20] |PWM03_RST |PWM0~3 controller Reset
+ * | | |0= PWM0~3 controller normal operation
+ * | | |1= PWM0~3 controller reset
+ * |[21] |PWM47_RST |PWM4~7 controller Reset
+ * | | |0= PWM4~7 controller normal operation
+ * | | |1= PWM4~7 controller reset
+ * |[28] |ADC_RST |ADC Controller Reset
+ * | | |0= ADC controller normal operation
+ * | | |1= ADC controller reset
+ */
+ __IO uint32_t IPRSTC2;
+
+ /**
+ * RESERVED0
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ uint32_t RESERVED0[2];
+
+ /**
+ * BODCR
+ * ===================================================================================================
+ * Offset: 0x18 Brown-Out Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BOD_EN |Brown Out Detector Enable (initiated & write-protected bit)
+ * | | |The default value is set by flash controller user configuration register config0 bit[23]
+ * | | |1= Brown Out Detector function is enabled
+ * | | |0= Brown Out Detector function is disabled
+ * |[2:1] |BOD_VL |Brown Out Detector Threshold Voltage Selection (initiated & write-protected bit)
+ * | | |The default value is set by flash controller user configuration register config0 bit[22:21]
+ * | | |CBOV[1]
+ * | | |CBOV[0]
+ * | | |Brown out voltage
+ * | | |11 = 4.5V
+ * | | |10 = 3.8V
+ * | | |01 = 2.7V
+ * | | |00 = 2.2V
+ * |[3] |BOD_RSTEN |Brown Out Reset Enable (initiated & write-protected bit)
+ * | | |1= Enable the Brown Out "RESET" function, when the Brown Out Detector function is enable
+ * | | |and the detected voltage is lower than the threshold then assert a signal to reset the chip
+ * | | |The default value is set by flash controller user configuration register config0 bit[20]
+ * | | |0= Enable the Brown Out "INTERRUPT" function, when the Brown Out Detector function is
+ * | | |enable and the detected voltage is lower than the threshold then assert a signal to interrupt
+ * | | |the MCU Cortex-M0
+ * | | |When the BOD_EN is enabled and the interrupt is assert, the interrupt will keep till to the
+ * | | |BOD_EN set to "0". The interrupt for CPU can be blocked by disable the NVIC in CPU for BOD
+ * | | |interrupt or disable the interrupt source by disable the BOD_EN and then re-enable the BOD_EN
+ * | | |function if the BOD function is required
+ * |[4] |BOD_INTF |Brown Out Detector Interrupt Flag
+ * | | |1= When Brown Out Detector detects the VDD is dropped through the voltage of BOD_VL setting
+ * | | |or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to "1" and the
+ * | | |brown out interrupt is requested if brown out interrupt is enabled.
+ * | | |0= Brown Out Detector does not detect any voltage draft at VDD down through or up through the
+ * | | |voltage of BOD_VL setting.
+ * |[5] |BOD_LPM |Brown Out Detector Low power Mode (write-protected bit)
+ * | | |1= Enable the BOD low power mode
+ * | | |0= BOD operate in normal mode (default)
+ * | | |The BOD consumes about 100uA in normal mode, the low power mode can reduce the current
+ * | | |to about 1/10 but slow the BOD response.
+ * |[6] |BOD_OUT |The status for Brown Out Detector output state
+ * | | |1= Brown Out Detector status output is 1, the detected voltage is lower than BOD_VL setting. If
+ * | | |the BOD_EN is "0"(disabled), this bit always response "0"
+ * | | |0= Brown Out Detector status output is 0, the detected voltage is higher than BOD_VL setting
+ * |[7] |LVR_EN |Low Voltage Reset Enable (write-protected bit)
+ * | | |The LVR function reset the chip when the input power voltage is lower than LVR circuit setting.
+ * | | |LVR function is enabled in default.
+ * | | |1= Enabled Low Voltage Reset function - After enable the bit, the LVR function will active with
+ * | | |100uS delay for LVR output stable.(default).
+ * | | |0= Disabled Low Voltage Reset function
+ */
+ __IO uint32_t BODCR;
+
+ /**
+ * TEMPCR
+ * ===================================================================================================
+ * Offset: 0x1C Temperature Sensor Control Register
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __IO uint32_t TEMPCR;
+
+ /**
+ * RESERVED1
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ uint32_t RESERVED1;
+
+ /**
+ * PORCR
+ * ===================================================================================================
+ * Offset: 0x24 Power-On-Reset Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |POR_DIS_CODE|The register is used for the Power-On-Reset enable control.
+ * | | |When power on, the POR circuit generates a reset signal to reset the whole chip function,
+ * | | |but noise on the power may cause the POR active again. If set the POR_DIS_CODE equal
+ * | | |to 0x5AA5, the POR reset function will be disabled and the POR function will re-active till
+ * | | |the power voltage is lower to set the POR_DIS_CODE to another value or reset by chip
+ * | | |other reset function. Include:
+ * | | |PIN reset, Watch dog, LVR reset BOD reset, ICE reset command and the software-chip
+ * | | |reset function
+ * | | |This register is the protected register, program this need an open lock sequence, write
+ * | | |"59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register
+ * | | |REGWRPROT at address GCR_BA + 0x100
+ */
+ __IO uint32_t PORCR;
+
+ /**
+ * RESERVED2
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ uint32_t RESERVED2[2];
+
+ /**
+ * P0_MFP
+ * ===================================================================================================
+ * Offset: 0x30 P0 Multiple Function and Input Type Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |P0_MFP |P0 multiple function Selection
+ * | | |The pin function of P0 is depending on P0_MFP and P0_ALT.
+ * | | |Refer to P0_ALT descriptions in detail.
+ * |[8] |P0_ALT0 |P0.0 alternate function Selection
+ * | | |The pin function of P0.0 is depend on P0_MFP[0] and P0_ALT[0].
+ * | | |P0_ALT[0]P0_MFP[0] = P0.0 Function
+ * | | |00 = P0.0
+ * | | |01 = AD0(EBI)
+ * | | |10 = CTS1(UART1)
+ * | | |11 = Reserved
+ * |[9] |P0_ALT1 |P0.1 alternate function Selection
+ * | | |The pin function of P0.1 is depend on P0_MFP[1] and P0_ALT[1].
+ * | | |P0_ALT[1] P0_MFP[1] = P0.1 Function
+ * | | |00 = P0.1
+ * | | |01 = AD1(EBI)
+ * | | |10 = RTS1(UART1)
+ * | | |11 = Reserved
+ * |[10] |P0_ALT2 |P0.2 alternate function Selection
+ * | | |The pin function of P0.2 is depend on P0_MFP[2] and P0_ALT[2].
+ * | | |P0_ALT[2] P0_MFP[2] = P0.2 Function
+ * | | |00 = P0.2
+ * | | |01 = AD2(EBI)
+ * | | |10 = CTS0(UART0)
+ * | | |11 = Reserved
+ * |[11] |P0_ALT3 |P0.3 alternate function Selection
+ * | | |The pin function of P0.3 is depend on P0_MFP[3] and P0_ALT[3].
+ * | | |P0_ALT[3] P0_MFP[3] = P0.3 Function
+ * | | |00 = P0.3
+ * | | |01 = AD3(EBI)
+ * | | |10 = RTS0(UART0)
+ * | | |11 = Reserved
+ * |[12] |P0_ALT4 |P0.4 alternate function Selection
+ * | | |The pin function of P0.4 is depend on P0_MFP[4] and P0_ALT[4].
+ * | | |P0_ALT[4] P0_MFP[4] = P0.4 Function
+ * | | |00 = P0.4
+ * | | |01 = AD4(EBI)
+ * | | |10 = SPISS1(SPI1)
+ * | | |11 = Reserved
+ * |[13] |P0_ALT5 |P0.5 alternate function Selection
+ * | | |The pin function of P0.5 is depend on P0_MFP[5] and P0_ALT[5].
+ * | | |P0_ALT[5] P0_MFP[5] = P0.5 Function
+ * | | |00 = P0.5
+ * | | |01 = AD5(EBI)
+ * | | |10 = MOSI_1(SPI1)
+ * | | |11 = Reserved
+ * |[14] |P0_ALT6 |P0.6 alternate function Selection
+ * | | |The pin function of P0.6 is depend on P0_MFP[6] and P0_ALT[6].
+ * | | |P0_ALT[6] P0_MFP[6] = P0.6 Function
+ * | | |00 = P0.6
+ * | | |01 = AD6(EBI)
+ * | | |10 = MISO_1(SPI1)
+ * | | |11 = Reserved
+ * |[15] |P0_ALT7 |P0.7 alternate function Selection
+ * | | |The pin function of P0.7 is depend on P0_MFP[7] and P0_ALT[7].
+ * | | |P0_ALT[7] P0_MFP[7] = P0.7 Function
+ * | | |00 = P0.7
+ * | | |01 = AD7(EBI)
+ * | | |10 = SPICLK1(SPI1)
+ * | | |11 = Reserved
+ * |[23:16] |P0_TYPEn |P0[7:0] input Schmitt Trigger function Enable
+ * | | |1= P0[7:0] I/O input Schmitt Trigger function enable
+ * | | |0= P0[7:0] I/O input Schmitt Trigger function disable
+ */
+ __IO uint32_t P0_MFP;
+
+ /**
+ * P1_MFP
+ * ===================================================================================================
+ * Offset: 0x34 P1 Multiple Function and Input Type Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |P1_MFP |P1 multiple function Selection
+ * | | |The pin function of P1 is depending on P1_MFP and P1_ALT.
+ * | | |Refer to P1_ALT descriptions in detail.
+ * |[8] |P1_ALT0 |P1.0 alternate function Selection
+ * | | |The pin function of P1.0 is depend on P1_MFP[0] and P1_ALT[0].
+ * | | |P1_ALT[0] P1_MFP[0] = P1.0 Function
+ * | | |00 = P1.0
+ * | | |01 = AIN0(ADC)
+ * | | |10 = T2(Timer2)
+ * | | |11 = Reserved
+ * |[9] |P1_ALT1 |P1.1 alternate function Selection
+ * | | |The pin function of P1.1 is depend on P1_MFP[1] and P1_ALT[1].
+ * | | |P1_ALT[1] P1_MFP[1] = P1.1 Function
+ * | | |00 = P1.1
+ * | | |01 = AIN1(ADC)
+ * | | |10 = T3(Timer3)
+ * | | |11 = Reserved
+ * |[10] |P1_ALT2 |P1.2 alternate function Selection
+ * | | |The pin function of P1.2 is depend on P1_MFP[2] and P1_ALT[2].
+ * | | |P1_ALT[2] P1_MFP[2] = P1.2 Function
+ * | | |00 = P1.2
+ * | | |01 = AIN2(ADC)
+ * | | |10 = RXD1(UART1)
+ * | | |11 = Reserved
+ * |[11] |P1_ALT3 |P1.3 alternate function Selection
+ * | | |The pin function of P1.3 is depend on P1_MFP[3] and P1_ALT[3].
+ * | | |P1_ALT[3] P1_MFP[3] = P1.3 Function
+ * | | |00 = P1.3
+ * | | |01 = AIN3(ADC)
+ * | | |10 = TXD1(UART1)
+ * | | |11 = Reserved
+ * |[12] |P1_ALT4 |P1.4 alternate function Selection
+ * | | |The pin function of P1.4 is depend on P1_MFP[4] and P1_ALT[4].
+ * | | |P1_ALT[4] P1_MFP[4] = P1.4 Function
+ * | | |00 = P1.4
+ * | | |01 = AIN4(ADC)
+ * | | |10 = SPISS0(SPI0)
+ * | | |11 = Reserved
+ * |[13] |P1_ALT5 |P1.5 alternate function Selection
+ * | | |The pin function of P1.5 is depend on P1_MFP[5] and P1_ALT[5].
+ * | | |P1_ALT[5] P1_MFP[5] = P1.5 Function
+ * | | |00 = P1.5
+ * | | |01 = AIN5(ADC)
+ * | | |10 = MOSI_0(SPI0)
+ * | | |11 = Reserved
+ * |[14] |P1_ALT6 |P1.6 alternate function Selection
+ * | | |The pin function of P1.6 is depend on P1_MFP[6] and P1_ALT[6].
+ * | | |P1_ALT[6] P1_MFP[6] = P1.6 Function
+ * | | |00 = P1.6
+ * | | |01 = AIN6(ADC)
+ * | | |10 = MISO_0(SPI0)
+ * | | |11 = Reserved
+ * |[15] |P1_ALT7 |P1.7 alternate function Selection
+ * | | |The pin function of P1.7 is depend on P1_MFP[7] and P1_ALT[7].
+ * | | |P1_ALT[7] P1_MFP[7] = P1.7 Function
+ * | | |00 = P1.7
+ * | | |01 = AIN7(ADC)
+ * | | |10 = SPICLK0(SPI0)
+ * | | |11 = Reserved
+ * |[23:16] |P1_TYPEn |P1[7:0] input Schmitt Trigger function Enable
+ * | | |1= P1[7:0] I/O input Schmitt Trigger function enable
+ * | | |0= P1[7:0] I/O input Schmitt Trigger function disable
+ */
+ __IO uint32_t P1_MFP;
+
+ /**
+ * P2_MFP
+ * ===================================================================================================
+ * Offset: 0x38 P2 Multiple Function and Input Type Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |P2_MFP |P2 multiple function Selection
+ * | | |The pin function of P2 is depending on P2_MFP and P2_ALT.
+ * | | |Refer to P2_ALT descriptions in detail.
+ * |[8] |P2_ALT0 |P2.0 alternate function Selection
+ * | | |The pin function of P2.0 is depend on P2_MFP[0] and P2_ALT[0].
+ * | | |P2_ALT[0] P2_MFP[0] = P2.0 Function
+ * | | |00 = P2.0
+ * | | |01 = AD8(EBI)
+ * | | |10 = PWM0(PWM generator 0)
+ * | | |11 = Reserved
+ * |[9] |P2_ALT1 |P2.1 alternate function Selection
+ * | | |The pin function of P2.1 is depend on P2_MFP[1] and P2_ALT[1].
+ * | | |P2_ALT[1] P2_MFP[1] = P2.1 Function
+ * | | |00 = P2.1
+ * | | |01 = AD9(EBI)
+ * | | |10 = PWM1(PWM generator 0)
+ * | | |11 = Reserved
+ * |[10] |P2_ALT2 |P2.2 alternate function Selection
+ * | | |The pin function of P2.2 is depend on P2_MFP[2] and P2_ALT[2].
+ * | | |P2_ALT[2] P2_MFP[2] = P2.2 Function
+ * | | |00 = P2.2
+ * | | |01 = AD10(EBI)
+ * | | |10 = PWM2(PWM generator 2)
+ * | | |11 = Reserved
+ * |[11] |P2_ALT3 |P2.3 alternate function Selection
+ * | | |The pin function of P2.3 is depend on P2_MFP[3] and P2_ALT[3].
+ * | | |P2_ALT[3] P2_MFP[3] = P2.3 Function
+ * | | |00 = P2.3
+ * | | |01 = AD11(EBI)
+ * | | |10 = PWM3(PWM generator 2)
+ * | | |11 = Reserved
+ * |[12] |P2_ALT4 |P2.4 alternate function Selection
+ * | | |The pin function of P2.4 is depend on P2_MFP[4] and P2_ALT[4].
+ * | | |P2_ALT[4] P2_MFP[4] = P0.4 Function
+ * | | |00 = P0.4
+ * | | |01 = AD12(EBI)
+ * | | |10 = PWM4(PWM generator 4)
+ * | | |11 = Reserved
+ * |[13] |P2_ALT5 |P2.5 alternate function Selection
+ * | | |The pin function of P2.5 is depend on P2_MFP[5] and P2_ALT[5].
+ * | | |P2_ALT[5] P2_MFP[5] = P2.5 Function
+ * | | |00 = P2.5
+ * | | |01 = AD13(EBI)
+ * | | |10 = PWM5(PWM generator 4)
+ * | | |11 = Reserved
+ * |[14] |P2_ALT6 |P2.6 alternate function Selection
+ * | | |The pin function of P2.6 is depend on P2_MFP[6] and P2_ALT[6].
+ * | | |P2_ALT[6] P2_MFP[6] = P2.6 Function
+ * | | |00 = P2.6
+ * | | |01 = AD14(EBI)
+ * | | |10 = PWM6(PWM generator 6)
+ * | | |11 = Reserved
+ * |[15] |P2_ALT7 |P2.7 alternate function Selection
+ * | | |The pin function of P2.7 is depend on P2_MFP[7] and P2_ALT[7].
+ * | | |P2_ALT[7] P2_MFP[7] = P2.7 Function
+ * | | |00 = P2.7
+ * | | |01 = AD15(EBI)
+ * | | |10 = PWM7(PWM generator 6)
+ * | | |11 = Reserved
+ * |[23:16] |P2_TYPEn |P2[7:0] input Schmitt Trigger function Enable
+ * | | |1= P2[7:0] I/O input Schmitt Trigger function enable
+ * | | |0= P2[7:0] I/O input Schmitt Trigger function disable
+ */
+ __IO uint32_t P2_MFP;
+
+ /**
+ * P3_MFP
+ * ===================================================================================================
+ * Offset: 0x3C P3 Multiple Function and Input Type Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |P3_MFP |P3 multiple function Selection
+ * | | |The pin function of P3 is depending on P3_MFP and P3_ALT.
+ * | | |Refer to P3_ALT descriptions in detail.
+ * |[8] |P3_ALT0 |P3.0 alternate function Selection
+ * | | |The pin function of P3.0 is depend on P3_MFP[0] and P3_ALT[0].
+ * | | |P3_ALT[0] P3_MFP[0] = P3.0 Function
+ * | | |00 = P3.0
+ * | | |01 = RXD(UART0)
+ * | | |1x = Reserved
+ * |[9] |P3_ALT1 |P3.1 alternate function Selection
+ * | | |The pin function of P3.1 is depend on P3_MFP[1] and P3_ALT[1].
+ * | | |P3_ALT[1] P3_MFP[1] = P3.1 Function
+ * | | |00 = P3.1
+ * | | |01 = TXD(UART0)
+ * | | |1x = Reserved
+ * |[10] |P3_ALT2 |P3.2 alternate function Selection
+ * | | |The pin function of P3.2 is depend on P3_MFP[2] and P3_ALT[2].
+ * | | |P3_ALT[2] P3_MFP[2] = P3.2 Function
+ * | | |00 = P3.2
+ * | | |01 = /INT0
+ * | | |11 = Reserved
+ * |[11] |P3_ALT3 |P3.3 alternate function Selection
+ * | | |The pin function of P3.3 is depend on P3_MFP[3] and P3_ALT[3].
+ * | | |P3_ALT[3] P3_MFP[3] = P3.3 Function
+ * | | |00 = P3.3
+ * | | |01 = /INT1
+ * | | |10 = MCLK(EBI)
+ * | | |1x = Reserved
+ * |[12] |P3_ALT4 |P3.4 alternate function Selection
+ * | | |The pin function of P3.4 is depend on P3_MFP[4] and P3_ALT[4].
+ * | | |P3_ALT[4] P3_MFP[4] = P3.4 Function
+ * | | |00 = P3.4
+ * | | |01 = T0(Timer0)
+ * | | |10 = SDA(I2C)
+ * | | |11 = Reserved
+ * |[13] |P3_ALT5 |P3.5 alternate function Selection
+ * | | |The pin function of P3.5 is depend on P3_MFP[5] and P3_ALT[5].
+ * | | |P3_ALT[5] P3_MFP[5] = P3.5 Function
+ * | | |00 = P3.5
+ * | | |01 = T1(Timer1)
+ * | | |10 = SCL(I2C)
+ * | | |11 = Reserved
+ * |[14] |P3_ALT6 |P3.6 alternate function Selection
+ * | | |The pin function of P3.6 is depend on P3_MFP[6] and P3_ALT[6].
+ * | | |P3_ALT[6] P3_MFP[6] = P3.6 Function
+ * | | |00 = P3.6
+ * | | |01 = WR(EBI)
+ * | | |10 = CKO(Clock Driver output)
+ * | | |11 = Reserved
+ * |[15] |P3_ALT7 |P3.7 alternate function Selection
+ * | | |The pin function of P3.7 is depend on P3_MFP[7] and P3_ALT[7].
+ * | | |P3_ALT[7] P3_MFP[7] = P3.7 Function
+ * | | |00 = P3.7
+ * | | |01 = RD(EBI)
+ * | | |1x = Reserved
+ * |[23:16] |P3_TYPEn |P3[7:0] input Schmitt Trigger function Enable
+ * | | |1= P3[7:0] I/O input Schmitt Trigger function enable
+ * | | |0= P3[7:0] I/O input Schmitt Trigger function disable
+ */
+ __IO uint32_t P3_MFP;
+
+ /**
+ * P4_MFP
+ * ===================================================================================================
+ * Offset: 0x40 P4 Multiple Function and Input Type Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |P4_MFP |P4 multiple function Selection
+ * | | |The pin function of P4 is depending on P4_MFP and P4_ALT.
+ * | | |Refer to P4_ALT descriptions in detail.
+ * |[8] |P4_ALT0 |P4.0 alternate function Selection
+ * | | |The pin function of P4.0 is depend on P4_MFP[0] and P4_ALT[0].
+ * | | |P4_ALT[0] P4_MFP[0] = P4.0 Function
+ * | | |00 = P4.0
+ * | | |01 = PWM0(PWM generator 0)
+ * | | |1x = Reserved
+ * |[9] |P4_ALT1 |P4.1 alternate function Selection
+ * | | |The pin function of P4.1 is depend on P4_MFP[1] and P4_ALT[1].
+ * | | |P4_ALT[1] P4_MFP[1] = P4.1 Function
+ * | | |00 = P4.1
+ * | | |01 = PWM1(PWM generator 0)
+ * | | |1x = Reserved
+ * |[10] |P4_ALT2 |P4.2 alternate function Selection
+ * | | |The pin function of P4.2 is depend on P4_MFP[2] and P4_ALT[2].
+ * | | |P4_ALT[2] P4_MFP[2] = P4.2 Function
+ * | | |00 = P4.2
+ * | | |01 = PWM2(PWM generator 2)
+ * | | |1x = Reserved
+ * |[11] |P4_ALT3 |P4.3 alternate function Selection
+ * | | |The pin function of P4.3 is depend on P4_MFP[3] and P4_ALT[3].
+ * | | |P4_ALT[3] P4_MFP[3] = P4.3 Function
+ * | | |00 = P4.3
+ * | | |01 = PWM3(PWM generator 2)
+ * | | |1x = Reserved
+ * |[12] |P4_ALT4 |P4.4 alternate function Selection
+ * | | |The pin function of P4.4 is depend on P4_MFP[4] and P4_ALT[4].
+ * | | |P4_ALT[4] P4_MFP[4] = P4.4 Function
+ * | | |00 = P4.4
+ * | | |01 = /CS(EBI)
+ * | | |1x = Reserved
+ * |[13] |P4_ALT5 |P4.5 alternate function Selection
+ * | | |The pin function of P4.5 is depend on P4_MFP[5] and P4_ALT[5].
+ * | | |P4_ALT[5] P4_MFP[5] = P4.5 Function
+ * | | |00 = P4.5
+ * | | |01 = ALE(EBI)
+ * | | |1x = Reserved
+ * |[14] |P4_ALT6 |P4.6 alternate function Selection
+ * | | |The pin function of P4.6 is depend on P4_MFP[6] and P4_ALT[6].
+ * | | |P4_ALT[6] P4_MFP[6] = P4.6 Function
+ * | | |00 = P4.6
+ * | | |01 = ICE_CLK(ICE)
+ * | | |1x = Reserved
+ * |[15] |P4_ALT7 |P4.7 alternate function Selection
+ * | | |The pin function of P4.7 is depend on P4_MFP[7] and P4_ALT[7].
+ * | | |P4_ALT[7] P4_MFP[7] = P4.7 Function
+ * | | |00 = P4.7
+ * | | |01 = ICE_DAT(ICE)
+ * | | |1x = Reserved
+ * |[23:16] |P4_TYPEn |P4[7:0] input Schmitt Trigger function Enable
+ * | | |1= P4[7:0] I/O input Schmitt Trigger function enable
+ * | | |0= P4[7:0] I/O input Schmitt Trigger function disable
+ */
+ __IO uint32_t P4_MFP;
+
+ /**
+ * RESERVED3
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ uint32_t RESERVED3[47];
+
+ /**
+ * REGWRPROT
+ * ===================================================================================================
+ * Offset: 0x100 Register Write-Protection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |REGWRPROT |Register Write-Protected Code (Write Only)
+ * | | |Some write-protected registers have to be disabled the protected function by writing the
+ * | | |sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the
+ * | | |REGPROTDIS bit will be set to 1 and write-protected registers can be normal write.
+ * |[0] |REGPROTDIS|Register Write-Protected Disable index (Read only)
+ * | | |1 = Protection is disabled for writing protected registers
+ * | | |0 = Protection is enabled for writing protected registers. Any write to the protected register is
+ * | | |ignored.
+ * | | |The Write-Protected registers list are below table:
+ * | | |Registers Address Note
+ * | | |IPRSTC1 0x5000_0008 None
+ * | | |BODCR 0x5000_0018 None
+ * | | |PORCR 0x5000_001C None
+ * | | |PWRCON 0x5000_0200 bit[6] is not protected for power, wake-up interrupt clear
+ * | | |APBCLK bit[0] 0x5000_0208 bit[0] is watch dog clock enable
+ * | | |CLKSEL0 0x5000_0210 HCLK and CPU STCLK clock source select
+ * | | |CLK_SEL1 bit[1:0] 0x5000_0214 Watch dog clock source select
+ * | | |ISPCON 0x5000_C000 Flash ISP Control register
+ * | | |WTCR 0x4000_4000 None
+ * | | |FATCON 0x5000_C018 None
+ */
+ __IO uint32_t REGWRPROT;
+
+} GCR_T;
+
+
+/** @addtogroup GCR_CONST GCR Bit Field Definition
+ Constant Definitions for GCR Controller
+ @{
+ */
+
+/* GCR RSTSRC Bit Field Definitions */
+#define SYS_RSTSRC_RSTS_CPU_Pos 7 /*!< GCR RSTSRC: RSTS_CPU Position */
+#define SYS_RSTSRC_RSTS_CPU_Msk (1ul << SYS_RSTSRC_RSTS_CPU_Pos) /*!< GCR RSTSRC: RSTS_CPU Mask */
+
+#define SYS_RSTSRC_RSTS_MCU_Pos 5 /*!< GCR RSTSRC: RSTS_MCU Position */
+#define SYS_RSTSRC_RSTS_MCU_Msk (1ul << SYS_RSTSRC_RSTS_MCU_Pos) /*!< GCR RSTSRC: RSTS_MCU Mask */
+
+#define SYS_RSTSRC_RSTS_BOD_Pos 4 /*!< GCR RSTSRC: RSTS_BOD Position */
+#define SYS_RSTSRC_RSTS_BOD_Msk (1ul << SYS_RSTSRC_RSTS_BOD_Pos) /*!< GCR RSTSRC: RSTS_BOD Mask */
+
+#define SYS_RSTSRC_RSTS_LVR_Pos 3 /*!< GCR RSTSRC: RSTS_LVR Position */
+#define SYS_RSTSRC_RSTS_LVR_Msk (1ul << SYS_RSTSRC_RSTS_LVR_Pos) /*!< GCR RSTSRC: RSTS_LVR Mask */
+
+#define SYS_RSTSRC_RSTS_WDT_Pos 2 /*!< GCR RSTSRC: RSTS_WDT Position */
+#define SYS_RSTSRC_RSTS_WDT_Msk (1ul << SYS_RSTSRC_RSTS_WDT_Pos) /*!< GCR RSTSRC: RSTS_WDT Mask */
+
+#define SYS_RSTSRC_RSTS_RESET_Pos 1 /*!< GCR RSTSRC: RSTS_RESET Position */
+#define SYS_RSTSRC_RSTS_RESET_Msk (1ul << SYS_RSTSRC_RSTS_RESET_Pos) /*!< GCR RSTSRC: RSTS_RESET Mask */
+
+#define SYS_RSTSRC_RSTS_POR_Pos 0 /*!< GCR RSTSRC: RSTS_POR Position */
+#define SYS_RSTSRC_RSTS_POR_Msk (1ul << SYS_RSTSRC_RSTS_POR_Pos) /*!< GCR RSTSRC: RSTS_POR Mask */
+
+/* GCR IPRSTC1 Bit Field Definitions */
+#define SYS_IPRSTC1_HDIV_RST_Pos 4 /*!< GCR IPRSTC1: DIV_RST Position */
+#define SYS_IPRSTC1_HDIV_RST_Msk (1ul << SYS_IPRSTC1_HDIV_RST_Pos) /*!< GCR IPRSTC1: DIV_RST Mask */
+
+#define SYS_IPRSTC1_EBI_RST_Pos 3 /*!< GCR IPRSTC1: EBI_RST Position */
+#define SYS_IPRSTC1_EBI_RST_Msk (1ul << SYS_IPRSTC1_EBI_RST_Pos) /*!< GCR IPRSTC1: EBI_RST Mask */
+
+#define SYS_IPRSTC1_CPU_RST_Pos 1 /*!< GCR IPRSTC1: CPU_RST Position */
+#define SYS_IPRSTC1_CPU_RST_Msk (1ul << SYS_IPRSTC1_CPU_RST_Pos) /*!< GCR IPRSTC1: CPU_RST Mask */
+
+#define SYS_IPRSTC1_CHIP_RST_Pos 0 /*!< GCR IPRSTC1: CHIP_RST Position */
+#define SYS_IPRSTC1_CHIP_RST_Msk (1ul << SYS_IPRSTC1_CHIP_RST_Pos) /*!< GCR IPRSTC1: CHIP_RST Mask */
+
+/* GCR IPRSTC2 Bit Field Definitions */
+#define SYS_IPRSTC2_ADC_RST_Pos 28 /*!< GCR IPRSTC2: ADC_RST Position */
+#define SYS_IPRSTC2_ADC_RST_Msk (1ul << SYS_IPRSTC2_ADC_RST_Pos) /*!< GCR IPRSTC2: ADC_RST Mask */
+
+#define SYS_IPRSTC2_ACMP23_RST_Pos 23 /*!< GCR IPRSTC2: ACMP23_RST Position */
+#define SYS_IPRSTC2_ACMP23_RST_Msk (1ul << SYS_IPRSTC2_ACMP23_RST_Pos) /*!< GCR IPRSTC2: ACMP23_RST Mask */
+
+#define SYS_IPRSTC2_ACMP01_RST_Pos 22 /*!< GCR IPRSTC2: ACMP01_RST Position */
+#define SYS_IPRSTC2_ACMP01_RST_Msk (1ul << SYS_IPRSTC2_ACMP01_RST_Pos) /*!< GCR IPRSTC2: ACMP01_RST Mask */
+
+#define SYS_IPRSTC2_PWM47_RST_Pos 21 /*!< GCR IPRSTC2: PWM47_RST Position */
+#define SYS_IPRSTC2_PWM47_RST_Msk (1ul << SYS_IPRSTC2_PWM47_RST_Pos) /*!< GCR IPRSTC2: PWM47_RST Mask */
+
+#define SYS_IPRSTC2_PWM03_RST_Pos 20 /*!< GCR IPRSTC2: PWM03_RST Position */
+#define SYS_IPRSTC2_PWM03_RST_Msk (1ul << SYS_IPRSTC2_PWM03_RST_Pos) /*!< GCR IPRSTC2: PWM03_RST Mask */
+
+#define SYS_IPRSTC2_UART1_RST_Pos 17 /*!< GCR IPRSTC2: UART1_RST Position */
+#define SYS_IPRSTC2_UART1_RST_Msk (1ul << SYS_IPRSTC2_UART1_RST_Pos) /*!< GCR IPRSTC2: UART1_RST Mask */
+
+#define SYS_IPRSTC2_UART0_RST_Pos 16 /*!< GCR IPRSTC2: UART0_RST Position */
+#define SYS_IPRSTC2_UART0_RST_Msk (1ul << SYS_IPRSTC2_UART0_RST_Pos) /*!< GCR IPRSTC2: UART0_RST Mask */
+
+#define SYS_IPRSTC2_SPI1_RST_Pos 13 /*!< GCR IPRSTC2: SPI1_RST Position */
+#define SYS_IPRSTC2_SPI1_RST_Msk (1ul << SYS_IPRSTC2_SPI1_RST_Pos) /*!< GCR IPRSTC2: SPI1_RST Mask */
+
+#define SYS_IPRSTC2_SPI0_RST_Pos 12 /*!< GCR IPRSTC2: SPI0_RST Position */
+#define SYS_IPRSTC2_SPI0_RST_Msk (1ul << SYS_IPRSTC2_SPI0_RST_Pos) /*!< GCR IPRSTC2: SPI0_RST Mask */
+
+#define SYS_IPRSTC2_I2C1_RST_Pos 9 /*!< GCR IPRSTC2: I2C1_RST Position */
+#define SYS_IPRSTC2_I2C1_RST_Msk (1ul << SYS_IPRSTC2_I2C1_RST_Pos) /*!< GCR IPRSTC2: I2C1_RST Mask */
+
+#define SYS_IPRSTC2_I2C0_RST_Pos 8 /*!< GCR IPRSTC2: I2C0_RST Position */
+#define SYS_IPRSTC2_I2C0_RST_Msk (1ul << SYS_IPRSTC2_I2C0_RST_Pos) /*!< GCR IPRSTC2: I2C0_RST Mask */
+#define SYS_IPRSTC2_I2C_RST_Pos 8 /*!< GCR IPRSTC2: I2C_RST Position */
+#define SYS_IPRSTC2_I2C_RST_Msk (1ul << SYS_IPRSTC2_I2C_RST_Pos) /*!< GCR IPRSTC2: I2C_RST Mask */
+
+#define SYS_IPRSTC2_TMR3_RST_Pos 5 /*!< GCR IPRSTC2: TMR3_RST Position */
+#define SYS_IPRSTC2_TMR3_RST_Msk (1ul << SYS_IPRSTC2_TMR3_RST_Pos) /*!< GCR IPRSTC2: TMR3_RST Mask */
+
+#define SYS_IPRSTC2_TMR2_RST_Pos 4 /*!< GCR IPRSTC2: TMR2_RST Position */
+#define SYS_IPRSTC2_TMR2_RST_Msk (1ul << SYS_IPRSTC2_TMR2_RST_Pos) /*!< GCR IPRSTC2: TMR2_RST Mask */
+
+#define SYS_IPRSTC2_TMR1_RST_Pos 3 /*!< GCR IPRSTC2: TMR1_RST Position */
+#define SYS_IPRSTC2_TMR1_RST_Msk (1ul << SYS_IPRSTC2_TMR1_RST_Pos) /*!< GCR IPRSTC2: TMR1_RST Mask */
+
+#define SYS_IPRSTC2_TMR0_RST_Pos 2 /*!< GCR IPRSTC2: TMR0_RST Position */
+#define SYS_IPRSTC2_TMR0_RST_Msk (1ul << SYS_IPRSTC2_TMR0_RST_Pos) /*!< GCR IPRSTC2: TMR0_RST Mask */
+
+#define SYS_IPRSTC2_GPIO_RST_Pos 1 /*!< GCR IPRSTC2: GPIO_RST Position */
+#define SYS_IPRSTC2_GPIO_RST_Msk (1ul << SYS_IPRSTC2_GPIO_RST_Pos) /*!< GCR IPRSTC2: GPIO_RST Mask */
+
+/* GCR BODCR Bit Field Definitions */
+#define SYS_BODCR_LVR_EN_Pos 7 /*!< GCR BODCR: LVR_EN Position */
+#define SYS_BODCR_LVR_EN_Msk (1ul << SYS_BODCR_LVR_EN_Pos) /*!< GCR BODCR: LVR_EN Mask */
+
+#define SYS_BODCR_BOD_OUT_Pos 6 /*!< GCR BODCR: BOD_OUT Position */
+#define SYS_BODCR_BOD_OUT_Msk (1ul << SYS_BODCR_BOD_OUT_Pos) /*!< GCR BODCR: BOD_OUT Mask */
+
+#define SYS_BODCR_BOD_LPM_Pos 5 /*!< GCR BODCR: BOD_LPM Position */
+#define SYS_BODCR_BOD_LPM_Msk (1ul << SYS_BODCR_BOD_LPM_Pos) /*!< GCR BODCR: BOD_LPM Mask */
+
+#define SYS_BODCR_BOD_INTF_Pos 4 /*!< GCR BODCR: BOD_INTF Position */
+#define SYS_BODCR_BOD_INTF_Msk (1ul << SYS_BODCR_BOD_INTF_Pos) /*!< GCR BODCR: BOD_INTF Mask */
+
+#define SYS_BODCR_BOD_RSTEN_Pos 3 /*!< GCR BODCR: BOD_RSTEN Position */
+#define SYS_BODCR_BOD_RSTEN_Msk (1ul << SYS_BODCR_BOD_RSTEN_Pos) /*!< GCR BODCR: BOD_RSTEN Mask */
+
+#define SYS_BODCR_BOD_VL_Pos 1 /*!< GCR BODCR: BOD_VL Position */
+#define SYS_BODCR_BOD_VL_Msk (3ul << SYS_BODCR_BOD_VL_Pos) /*!< GCR BODCR: BOD_VL Mask */
+
+#define SYS_BODCR_BOD_EN_Pos 0 /*!< GCR BODCR: BOD_EN Position */
+#define SYS_BODCR_BOD_EN_Msk (1ul << SYS_BODCR_BOD_EN_Pos) /*!< GCR BODCR: BOD_EN Mask */
+
+/* GCR TEMPCR Bit Field Definitions */
+#define SYS_TEMPCR_VTEMP_EN_Pos 0 /*!< GCR TEMPCR: VTEMP_EN Position */
+#define SYS_TEMPCR_VTEMP_EN_Msk (1ul << SYS_TEMPCR_VTEMP_EN_Pos) /*!< GCR TEMPCR: VTEMP_EN Mask */
+
+/* GCR PORCR Bit Field Definitions */
+#define SYS_PORCR_POR_DIS_CODE_Pos 0 /*!< GCR PORCR: POR_DIS_CODE Position */
+#define SYS_PORCR_POR_DIS_CODE_Msk (0xFFFFul << SYS_PORCR_POR_DIS_CODE_Pos)/*!< GCR PORCR: POR_DIS_CODE Mask */
+
+/* GCR P0_MFP Bit Field Definitions */
+#define SYS_P0_MFP_P0_ALT1_Pos 24 /*!< GCR P0_MFP: P0_ALT1 Position */
+#define SYS_P0_MFP_P0_ALT1_Msk (3ul << SYS_P0_MFP_P0_ALT1_Pos) /*!< GCR P0_MFP: P0_ALT1 Mask */
+
+#define SYS_P0_MFP_P0_TYPE_Pos 16 /*!< GCR P0_MFP: P0_TYPE Position */
+#define SYS_P0_MFP_P0_TYPE_Msk (0xFFul << SYS_P0_MFP_P0_TYPE_Pos) /*!< GCR P0_MFP: P0_TYPE Mask */
+
+#define SYS_P0_MFP_P0_ALT_Pos 8 /*!< GCR P0_MFP: P0_ALT Position */
+#define SYS_P0_MFP_P0_ALT_Msk (0xFFul << SYS_P0_MFP_P0_ALT_Pos) /*!< GCR P0_MFP: P0_ALT Mask */
+
+#define SYS_P0_MFP_P0_MFP_Pos 0 /*!< GCR P0_MFP: P0_MFP Position */
+#define SYS_P0_MFP_P0_MFP_Msk (0xFFul << SYS_P0_MFP_P0_MFP_Pos) /*!< GCR P0_MFP: P0_MFP Mask */
+
+/* GCR P1_MFP Bit Field Definitions */
+#define SYS_P1_MFP_P1_TYPE_Pos 16 /*!< GCR P1_MFP: P1_TYPE Position */
+#define SYS_P1_MFP_P1_TYPE_Msk (0xFFul << SYS_P1_MFP_P1_TYPE_Pos) /*!< GCR P1_MFP: P1_TYPE Mask */
+
+#define SYS_P1_MFP_P1_ALT_Pos 8 /*!< GCR P1_MFP: P1_ALT Position */
+#define SYS_P1_MFP_P1_ALT_Msk (0xFFul << SYS_P1_MFP_P1_ALT_Pos) /*!< GCR P1_MFP: P1_ALT Mask */
+
+#define SYS_P1_MFP_P1_MFP_Pos 0 /*!< GCR P1_MFP: P1_MFP Position */
+#define SYS_P1_MFP_P1_MFP_Msk (0xFFul << SYS_P1_MFP_P1_MFP_Pos) /*!< GCR P1_MFP: P1_MFP Mask */
+
+/* GCR P2_MFP Bit Field Definitions */
+#define SYS_P2_MFP_P2_TYPE_Pos 16 /*!< GCR P2_MFP: P2_TYPE Position */
+#define SYS_P2_MFP_P2_TYPE_Msk (0xFFul << SYS_P2_MFP_P2_TYPE_Pos) /*!< GCR P2_MFP: P2_TYPE Mask */
+
+#define SYS_P2_MFP_P2_ALT_Pos 8 /*!< GCR P2_MFP: P2_ALT Position */
+#define SYS_P2_MFP_P2_ALT_Msk (0xFFul << SYS_P2_MFP_P2_ALT_Pos) /*!< GCR P2_MFP: P2_ALT Mask */
+
+#define SYS_P2_MFP_P2_MFP_Pos 0 /*!< GCR P2_MFP: P2_MFP Position */
+#define SYS_P2_MFP_P2_MFP_Msk (0xFFul << SYS_P2_MFP_P2_MFP_Pos) /*!< GCR P2_MFP: P2_MFP Mask */
+
+/* GCR P3_MFP Bit Field Definitions */
+#define SYS_P3_MFP_P3_TYPE_Pos 16 /*!< GCR P3_MFP: P3_TYPE Position */
+#define SYS_P3_MFP_P3_TYPE_Msk (0xFFul << SYS_P3_MFP_P3_TYPE_Pos) /*!< GCR P3_MFP: P3_TYPE Mask */
+
+#define SYS_P3_MFP_P3_ALT_Pos 8 /*!< GCR P3_MFP: P3_ALT Position */
+#define SYS_P3_MFP_P3_ALT_Msk (0xFFul << SYS_P3_MFP_P3_ALT_Pos) /*!< GCR P3_MFP: P3_ALT Mask */
+
+#define SYS_P3_MFP_P3_MFP_Pos 0 /*!< GCR P3_MFP: P3_MFP Position */
+#define SYS_P3_MFP_P3_MFP_Msk (0xFFul << SYS_P3_MFP_P3_MFP_Pos) /*!< GCR P3_MFP: P3_MFP Mask */
+
+/* GCR P4_MFP Bit Field Definitions */
+#define SYS_P4_MFP_P4_TYPE_Pos 16 /*!< GCR P4_MFP: P4_TYPE Position */
+#define SYS_P4_MFP_P4_TYPE_Msk (0xFFul << SYS_P4_MFP_P4_TYPE_Pos) /*!< GCR P4_MFP: P4_TYPE Mask */
+
+#define SYS_P4_MFP_P4_ALT_Pos 8 /*!< GCR P4_MFP: P4_ALT Position */
+#define SYS_P4_MFP_P4_ALT_Msk (0xFFul << SYS_P4_MFP_P4_ALT_Pos) /*!< GCR P4_MFP: P4_ALT Mask */
+
+#define SYS_P4_MFP_P4_MFP_Pos 0 /*!< GCR P4_MFP: P4_MFP Position */
+#define SYS_P4_MFP_P4_MFP_Msk (0xFFul << SYS_P4_MFP_P4_MFP_Pos) /*!< GCR P4_MFP: P4_MFP Mask */
+
+/* GCR REGWRPROT Bit Field Definitions */
+#define SYS_REGWRPROT_REGWRPROT_Pos 0 /*!< GCR REGWRPROT: REGWRPROT Position */
+#define SYS_REGWRPROT_REGWRPROT_Msk (0xFFul << SYS_REGWRPROT_REGWRPROT_Pos) /*!< GCR REGWRPROT: REGWRPROT Mask */
+
+#define SYS_REGWRPROT_REGPROTDIS_Pos 0 /*!< GCR REGWRPROT: REGPROTDIS Position */
+#define SYS_REGWRPROT_REGPROTDIS_Msk (1ul << SYS_REGWRPROT_REGPROTDIS_Pos) /*!< GCR REGWRPROT: REGPROTDIS Mask */
+/**@}*/ /* GCR_CONST */
+
+
+typedef struct
+{
+ /**
+ * IRQSRC
+ * ===================================================================================================
+ * Offset: 0x00-0x7C MCU IRQn(n=0~31) Interrupt Source Identity Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |INT_SRC |Interrupt Source Identity
+ * | | |IRQSRC[0].0 - BOD INT
+ * | | |IRQSRC[0].1 - 0
+ * | | |IRQSRC[0].2 - 0
+ * | | |IRQSRC[1].0 - WDT INT
+ * | | |IRQSRC[1].1 - 0
+ * | | |IRQSRC[1].2 - 0
+ * | | |IRQSRC[2].0 - EINT0, external interrupt 0 from P3.2
+ * | | |IRQSRC[2].1 - 0
+ * | | |IRQSRC[2].2 - 0
+ * | | |IRQSRC[3].0 - EINT1, external interrupt 1 from P3.3
+ * | | |IRQSRC[3].1 - 0
+ * | | |IRQSRC[3].2 - 0
+ * | | |IRQSRC[4].0 - P0 INT
+ * | | |IRQSRC[4].1 - P1 INT
+ * | | |IRQSRC[4].2 - 0
+ * | | |IRQSRC[5].0 - P2 INT
+ * | | |IRQSRC[5].1 - P3 INT
+ * | | |IRQSRC[5].2 - P4 INT
+ * | | |IRQSRC[6].0 - PWM0 INT
+ * | | |IRQSRC[6].1 - PWM1 INT
+ * | | |IRQSRC[6].2 - PWM2 INT
+ * | | |IRQSRC[6].3 - PWM3 INT
+ * | | |IRQSRC[7].0 - PWM4 INT
+ * | | |IRQSRC[7].1 - PWM5 INT
+ * | | |IRQSRC[7].2 - PWM6 INT
+ * | | |IRQSRC[7].3 - PWM7 INT
+ * | | |IRQSRC[8].0 - TIMER0 INT
+ * | | |IRQSRC[8].1 - 0
+ * | | |IRQSRC[8].2 - 0
+ * | | |IRQSRC[9].0 - TIMER1 INT
+ * | | |IRQSRC[9].1 - 0
+ * | | |IRQSRC[9].2 - 0
+ * | | |IRQSRC[10].0 - TIMER2 INT
+ * | | |IRQSRC[10].1 - 0
+ * | | |IRQSRC[10].2 - 0
+ * | | |IRQSRC[11].0 - TIMER3 INT
+ * | | |IRQSRC[11].1 - 0
+ * | | |IRQSRC[11].2 - 0
+ * | | |IRQSRC[12].0 - UART0 INT
+ * | | |IRQSRC[12].1 - 0
+ * | | |IRQSRC[12].2 - 0
+ * | | |IRQSRC[13].0 - UART1 INT
+ * | | |IRQSRC[13].1 - 0
+ * | | |IRQSRC[13].2 - 0
+ * | | |IRQSRC[14].0 - SPI0 INT
+ * | | |IRQSRC[14].1 - 0
+ * | | |IRQSRC[14].2 - 0
+ * | | |IRQSRC[15].0 - SPI1 INT
+ * | | |IRQSRC[15].1 - 0
+ * | | |IRQSRC[15].2 - 0
+ * | | |IRQSRC[16].0 - 0
+ * | | |IRQSRC[16].1 - 0
+ * | | |IRQSRC[16].2 - 0
+ * | | |IRQSRC[17].0 - 0
+ * | | |IRQSRC[17].1 - 0
+ * | | |IRQSRC[17].2 - 0
+ * | | |IRQSRC[18].0 - I2C0 INT
+ * | | |IRQSRC[18].1 - 0
+ * | | |IRQSRC[18].2 - 0
+ * | | |IRQSRC[19].0 - I2C1 INT
+ * | | |IRQSRC[19].1 - 0
+ * | | |IRQSRC[19].2 - 0
+ * | | |IRQSRC[20].0 - 0
+ * | | |IRQSRC[20].1 - 0
+ * | | |IRQSRC[20].2 - 0
+ * | | |IRQSRC[21].0 - 0
+ * | | |IRQSRC[21].1 - 0
+ * | | |IRQSRC[21].2 - 0
+ * | | |IRQSRC[22].0 - 0
+ * | | |IRQSRC[22].1 - 0
+ * | | |IRQSRC[22].2 - 0
+ * | | |IRQSRC[23].0 - 0
+ * | | |IRQSRC[23].1 - 0
+ * | | |IRQSRC[23].2 - 0
+ * | | |IRQSRC[24].0 - 0
+ * | | |IRQSRC[24].1 - 0
+ * | | |IRQSRC[24].2 - 0
+ * | | |IRQSRC[25].0 - ACMP0 INT
+ * | | |IRQSRC[25].1 - 0
+ * | | |IRQSRC[25].2 - 0
+ * | | |IRQSRC[26].0 - ACMP1 INT
+ * | | |IRQSRC[26].1 - 0
+ * | | |IRQSRC[26].2 - 0
+ * | | |IRQSRC[27].0 - 0
+ * | | |IRQSRC[27].1 - 0
+ * | | |IRQSRC[27].2 - 0
+ * | | |IRQSRC[28].0 - Power Down Wake up INT
+ * | | |IRQSRC[28].1 - 0
+ * | | |IRQSRC[28].2 - 0
+ * | | |IRQSRC[29].0 - ADC INT
+ * | | |IRQSRC[29].1 - 0
+ * | | |IRQSRC[29].2 - 0
+ * | | |IRQSRC[30].0 - 0
+ * | | |IRQSRC[30].1 - 0
+ * | | |IRQSRC[30].2 - 0
+ * | | |IRQSRC[31].0 - 0
+ * | | |IRQSRC[31].1 - 0
+ * | | |IRQSRC[31].2 - 0
+ */
+ __I uint32_t IRQSRC[32];
+
+ /**
+ * NMISEL
+ * ===================================================================================================
+ * Offset: 0x80 NMI Interrupt Source Select Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |NMI_SEL |NMI interrupt source selection
+ * | | |The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]
+ * | | |The NMI_SEL bit[4:0] used to select the NMI interrupt source
+ * |[8] |NMI_EN |NMI interrupt enable (write-protection bit)
+ * | | |1 = Enable NMI interrupt
+ * | | |0 = Disable NMI interrupt
+ * | | |This bit is the protected bit.
+ * | | |It means programming this needs to write "59h", "16h", "88h"to address 0x5000_0100 to disable register protection.
+ * | | |Reference the register REGWRPROT at address GCR_BA+0x100
+ */
+ __IO uint32_t NMISEL;
+
+ /**
+ * MCUIRQ
+ * ===================================================================================================
+ * Offset: 0x84 MCU Interrupt Request Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |MCU_IRQ |MCU IRQ Source Register
+ * | | |The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core.
+ * | | |There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.
+ * | | |The MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.
+ * | | |When the MCU_IRQ[n] is "0", set MCU_IRQ[n] "1" will generate an interrupt to Cortex_M0 NVIC[n].
+ * | | |When the MCU_IRQ[n] is "1" (mean an interrupt is assert), set 1 to the MCU_IRQ[n] will clear the interrupt and set MCU_IRQ[n] "0" : no any effect
+ */
+ __IO uint32_t MCUIRQ;
+
+} GCR_INT_T;
+
+/** @addtogroup INT_CONST INT Bit Field Definition
+ Constant Definitions for INT Controller
+ @{
+ */
+
+/* INT NMI_SEL Bit Field Definitions */
+#define INT_NMI_SEL_NMI_EN_Pos 8 /*!< INT NMI_SEL: NMI_EN Position */
+#define INT_NMI_SEL_NMI_EN_Msk (1ul << INT_NMI_SEL_NMI_EN_Pos) /*!< INT NMI_SEL: NMI_EN Mask */
+
+#define INT_NMI_SEL_NMI_SEL_Pos 0 /*!< INT NMI_SEL: NMI_SEL Position */
+#define INT_NMI_SEL_NMI_SEL_Msk (0x1Ful << INT_NMI_SEL_NMI_SEL_Pos) /*!< INT NMI_SEL: NMI_SEL Mask */
+/**@}*/ /* INT_CONST */
+
+
+/**@}*/ /* GCR */
+
+
+/*--------------------- General Purpose Input and Ouptut ---------------------*/
+/** @addtogroup GPIO General Purpose Input and Ouptut(GPIO)
+ Memory Mapped Structure for General Purpose I/O
+ @{
+ */
+typedef struct
+{
+ /**
+ * PMD
+ * ===================================================================================================
+ * Offset: 0x00 Port 0-4 I/O Mode Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |PMD0 |P0 I/O Pin[0] Mode Control
+ * | | |Determine each I/O type of P0 pins
+ * | | |00 = P0[0] pin is in INPUT mode.
+ * | | |01 = P0[0] pin is in OUTPUT mode.
+ * | | |10 = P0[0] pin is in Open-Drain mode.
+ * | | |11 = P0[0] pin is in Quasi-bidirectional mode.
+ * |[3:2] |PMD1 |P0 I/O Pin[1] Mode Control
+ * | | |Determine each I/O type of P0 pins
+ * | | |00 = P0[1] pin is in INPUT mode.
+ * | | |01 = P0[1] pin is in OUTPUT mode.
+ * | | |10 = P0[1] pin is in Open-Drain mode.
+ * | | |11 = P0[1] pin is in Quasi-bidirectional mode.
+ * |[5:4] |PMD2 |P0 I/O Pin[2] Mode Control
+ * | | |Determine each I/O type of P0 pins
+ * | | |00 = P0[2] pin is in INPUT mode.
+ * | | |01 = P0[2] pin is in OUTPUT mode.
+ * | | |10 = P0[2] pin is in Open-Drain mode.
+ * | | |11 = P0[2] pin is in Quasi-bidirectional mode.
+ * |[7:6] |PMD3 |P0 I/O Pin[3] Mode Control
+ * | | |Determine each I/O type of P0 pins
+ * | | |00 = P0[3] pin is in INPUT mode.
+ * | | |01 = P0[3] pin is in OUTPUT mode.
+ * | | |10 = P0[3] pin is in Open-Drain mode.
+ * | | |11 = P0[3] pin is in Quasi-bidirectional mode.
+ * |[9:8] |PMD4 |P0 I/O Pin[4] Mode Control
+ * | | |Determine each I/O type of P0 pins
+ * | | |00 = P0[4] pin is in INPUT mode.
+ * | | |01 = P0[4] pin is in OUTPUT mode.
+ * | | |10 = P0[4] pin is in Open-Drain mode.
+ * | | |11 = P0[4] pin is in Quasi-bidirectional mode.
+ * |[11:10] |PMD5 |P0 I/O Pin[5] Mode Control
+ * | | |Determine each I/O type of P0 pins
+ * | | |00 = P0[5] pin is in INPUT mode.
+ * | | |01 = P0[5] pin is in OUTPUT mode.
+ * | | |10 = P0[5] pin is in Open-Drain mode.
+ * | | |11 = P0[5] pin is in Quasi-bidirectional mode.
+ * |[13:12] |PMD6 |P0 I/O Pin[6] Mode Control
+ * | | |Determine each I/O type of P0 pins
+ * | | |00 = P0[6] pin is in INPUT mode.
+ * | | |01 = P0[6] pin is in OUTPUT mode.
+ * | | |10 = P0[6] pin is in Open-Drain mode.
+ * | | |11 = P0[6] pin is in Quasi-bidirectional mode.
+ * |[15:14] |PMD7 |P0 I/O Pin[7] Mode Control
+ * | | |Determine each I/O type of P0 pins
+ * | | |00 = P0[7] pin is in INPUT mode.
+ * | | |01 = P0[7] pin is in OUTPUT mode.
+ * | | |10 = P0[7] pin is in Open-Drain mode.
+ * | | |11 = P0[7] pin is in Quasi-bidirectional mode.
+ */
+ __IO uint32_t PMD;
+
+ /**
+ * OFFD
+ * ===================================================================================================
+ * Port 0-4 Digital Input Path Disable Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |OFFD |OFFD: P0 Pin OFF digital input path Enable
+ * | | |1 = Disable IO digital input path (digital input tied to low)
+ * | | |0 = Enable IO digital input path
+ */
+ __IO uint32_t OFFD;
+
+ /**
+ * DOUT
+ * ===================================================================================================
+ * Port 0-4 Data Output Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DOUT0 |P0 Pin[0] Output Value
+ * | | |Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain
+ * | | |and quasi-mode.
+ * | | |1 = P0 Pin[0] will drive High if the corresponding output mode enabling bit is set.
+ * | | |0 = P0 Pin[0] will drive Low if the corresponding output mode enabling bit is set.
+ * |[1] |DOUT1 |P0 Pin[1] Output Value
+ * | | |Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain
+ * | | |and quasi-mode.
+ * | | |1 = P0 Pin[1] will drive High if the corresponding output mode enabling bit is set.
+ * | | |0 = P0 Pin[1] will drive Low if the corresponding output mode enabling bit is set.
+ * |[2] |DOUT2 |P0 Pin[2] Output Value
+ * | | |Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain
+ * | | |and quasi-mode.
+ * | | |1 = P0 Pin[2] will drive High if the corresponding output mode enabling bit is set.
+ * | | |0 = P0 Pin[2] will drive Low if the corresponding output mode enabling bit is set.
+ * |[3] |DOUT3 |P0 Pin[3] Output Value
+ * | | |Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain
+ * | | |and quasi-mode.
+ * | | |1 = P0 Pin[3] will drive High if the corresponding output mode enabling bit is set.
+ * | | |0 = P0 Pin[3] will drive Low if the corresponding output mode enabling bit is set.
+ * |[4] |DOUT4 |P0 Pin[4] Output Value
+ * | | |Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain
+ * | | |and quasi-mode.
+ * | | |1 = P0 Pin[4] will drive High if the corresponding output mode enabling bit is set.
+ * | | |0 = P0 Pin[4] will drive Low if the corresponding output mode enabling bit is set.
+ * |[5] |DOUT5 |P0 Pin[5] Output Value
+ * | | |Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain
+ * | | |and quasi-mode.
+ * | | |1 = P0 Pin[5] will drive High if the corresponding output mode enabling bit is set.
+ * | | |0 = P0 Pin[5] will drive Low if the corresponding output mode enabling bit is set.
+ * |[6] |DOUT6 |P0 Pin[6] Output Value
+ * | | |Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain
+ * | | |and quasi-mode.
+ * | | |1 = P0 Pin[6] will drive High if the corresponding output mode enabling bit is set.
+ * | | |0 = P0 Pin[6] will drive Low if the corresponding output mode enabling bit is set.
+ * |[7] |DOUT7 |P0 Pin[7] Output Value
+ * | | |Each of these bits control the status of a P0 pin when the P0 pin is configures as output, open-drain
+ * | | |and quasi-mode.
+ * | | |1 = P0 Pin[7] will drive High if the corresponding output mode enabling bit is set.
+ * | | |0 = P0 Pin[7] will drive Low if the corresponding output mode enabling bit is set.
+ */
+ __IO uint32_t DOUT;
+
+ /**
+ * DMASK
+ * ===================================================================================================
+ * Port0-4 Data Output Write Mask
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DMASK0 |P0 Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of P0_DOUT bit[0]. When set the
+ * | | |DMASK bit[0] to "1", the corresponding DOUT0 bit is protected. The write signal is masked, write
+ * | | |data to the protect bit is ignored
+ * | | |0 = The corresponding P0_DOUT[0] bit can be updated
+ * | | |1 = The corresponding P0_DOUT[0] bit is protected
+ * |[1] |DMASK1 |P0 Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of P0_DOUT bit[1]. When set the
+ * | | |DMASK bit[1] to "1", the corresponding DOUT1 bit is protected. The write signal is masked, write
+ * | | |data to the protect bit is ignored
+ * | | |0 = The corresponding P0_DOUT[1] bit can be updated
+ * | | |1 = The corresponding P0_DOUT[1] bit is protected
+ * |[2] |DMASK2 |P0 Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of P0_DOUT bit[2]. When set the
+ * | | |DMASK bit[2] to "1", the corresponding DOUT2 bit is protected. The write signal is masked, write
+ * | | |data to the protect bit is ignored
+ * | | |0 = The corresponding P0_DOUT[2] bit can be updated
+ * | | |1 = The corresponding P0_DOUT[2] bit is protected
+ * |[3] |DMASK3 |P0 Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of P0_DOUT bit[3]. When set the
+ * | | |DMASK bit[3] to "1", the corresponding DOUT3 bit is protected. The write signal is masked, write
+ * | | |data to the protect bit is ignored
+ * | | |0 = The corresponding P0_DOUT[3] bit can be updated
+ * | | |1 = The corresponding P0_DOUT[3] bit is protected
+ * |[4] |DMASK4 |P0 Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of P0_DOUT bit[4]. When set the
+ * | | |DMASK bit[4] to "1", the corresponding DOUT4 bit is protected. The write signal is masked, write
+ * | | |data to the protect bit is ignored
+ * | | |0 = The corresponding P0_DOUT[4] bit can be updated
+ * | | |1 = The corresponding P0_DOUT[4] bit is protected
+ * |[5] |DMASK5 |P0 Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the
+ * | | |DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write
+ * | | |data to the protect bit is ignored
+ * | | |0 = The corresponding P0_DOUT[6] bit can be updated
+ * | | |1 = The corresponding P0_DOUT[6] bit is protected
+ * |[6] |DMASK6 |P0 Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of P0_DOUT bit[6]. When set the
+ * | | |DMASK bit[6] to "1", the corresponding DOUT6 bit is protected. The write signal is masked, write
+ * | | |data to the protect bit is ignored
+ * | | |0 = The corresponding P0_DOUT[6] bit can be updated
+ * | | |1 = The corresponding P0_DOUT[6] bit is protected
+ * |[7] |DMASK7 |P0 Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of P0_DOUT bit[7]. When set the
+ * | | |DMASK bit[7] to "1", the corresponding DOUT7 bit is protected. The write signal is masked, write
+ * | | |data to the protect bit is ignored
+ * | | |0 = The corresponding P0_DOUT[7] bit can be updated
+ * | | |1 = The corresponding P0_DOUT[7] bit is protected
+ */
+ __IO uint32_t DMASK;
+
+ /**
+ * PIN;
+ * ===================================================================================================
+ * Port 0-4 Pin Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PIN0 |P0 Pin Values
+ * | | |The value read from each of these bit reflects the actual status of the respective P0 Pin[0].
+ * |[1] |PIN1 |P0 Pin Values
+ * | | |The value read from each of these bit reflects the actual status of the respective P0 Pin[1].
+ * |[2] |PIN2 |P0 Pin Values
+ * | | |The value read from each of these bit reflects the actual status of the respective P0 Pin[2].
+ * |[3] |PIN3 |P0 Pin Values
+ * | | |The value read from each of these bit reflects the actual status of the respective P0 Pin[3].
+ * |[4] |PIN4 |P0 Pin Values
+ * | | |The value read from each of these bit reflects the actual status of the respective P0 Pin[4].
+ * |[5] |PIN5 |P0 Pin Values
+ * | | |The value read from each of these bit reflects the actual status of the respective P0 Pin[5].
+ * |[6] |PIN6 |P0 Pin Values
+ * | | |The value read from each of these bit reflects the actual status of the respective P0 Pin[6].
+ * |[7] |PIN7 |P0 Pin Values
+ * | | |The value read from each of these bit reflects the actual status of the respective P0 Pin[7].
+ */
+ __IO uint32_t PIN;
+
+ /**
+ * DBEN
+ * ===================================================================================================
+ * Port 0-4 De-bounce Enable
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DBEN0 |P0 Input Signal De-bounce Enable
+ * | | |DBEN[0] used to enable the de-bounce function for each corresponding bit. if the input signal pulse
+ * | | |width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen
+ * | | |as the signal bounce and will not trigger the interrupt.
+ * | | |The DBEN[0] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The bit[0] de-bounce function is disabled
+ * | | |1 = The bit[0] de-bounce function is enabled
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered,
+ * | | |the de-bounce enable bit is ignored.
+ * |[1] |DBEN1 |P0 Input Signal De-bounce Enable
+ * | | |DBEN[1] used to enable the de-bounce function for each corresponding bit. if the input signal pulse
+ * | | |width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen
+ * | | |as the signal bounce and will not trigger the interrupt.
+ * | | |The DBEN[1] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The bit[1] de-bounce function is disabled
+ * | | |1 = The bit[1] de-bounce function is enabled
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered,
+ * | | |the de-bounce enable bit is ignored.
+ * |[2] |DBEN2 |P0 Input Signal De-bounce Enable
+ * | | |DBEN[2] used to enable the de-bounce function for each corresponding bit. if the input signal pulse
+ * | | |width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen
+ * | | |as the signal bounce and will not trigger the interrupt.
+ * | | |The DBEN[2] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The bit[2] de-bounce function is disabled
+ * | | |1 = The bit[2] de-bounce function is enabled
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered,
+ * | | |the de-bounce enable bit is ignored.
+ * |[3] |DBEN3 |P0 Input Signal De-bounce Enable
+ * | | |DBEN[3] used to enable the de-bounce function for each corresponding bit. if the input signal pulse
+ * | | |width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen
+ * | | |as the signal bounce and will not trigger the interrupt.
+ * | | |The DBEN[3] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The bit[3] de-bounce function is disabled
+ * | | |1 = The bit[3] de-bounce function is enabled
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered,
+ * | | |the de-bounce enable bit is ignored.
+ * |[4] |DBEN4 |P0 Input Signal De-bounce Enable
+ * | | |DBEN[4] used to enable the de-bounce function for each corresponding bit. if the input signal pulse
+ * | | |width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen
+ * | | |as the signal bounce and will not trigger the interrupt.
+ * | | |The DBEN[4] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The bit[4] de-bounce function is disabled
+ * | | |1 = The bit[4] de-bounce function is enabled
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered,
+ * | | |the de-bounce enable bit is ignored.
+ * |[5] |DBEN5 |P0 Input Signal De-bounce Enable
+ * | | |DBEN[5] used to enable the de-bounce function for each corresponding bit. if the input signal pulse
+ * | | |width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen
+ * | | |as the signal bounce and will not trigger the interrupt.
+ * | | |The DBEN[5] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The bit[5] de-bounce function is disabled
+ * | | |1 = The bit[5] de-bounce function is enabled
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered,
+ * | | |the de-bounce enable bit is ignored.
+ * |[6] |DBEN6 |P0 Input Signal De-bounce Enable
+ * | | |DBEN[6] used to enable the de-bounce function for each corresponding bit. if the input signal pulse
+ * | | |width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen
+ * | | |as the signal bounce and will not trigger the interrupt.
+ * | | |The DBEN[6] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The bit[6] de-bounce function is disabled
+ * | | |1 = The bit[6] de-bounce function is enabled
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered,
+ * | | |the de-bounce enable bit is ignored.
+ * |[7] |DBEN7 |P0 Input Signal De-bounce Enable
+ * | | |DBEN[7] used to enable the de-bounce function for each corresponding bit. if the input signal pulse
+ * | | |width can't be sampled by continuous two de-bounce sample cycle. The input signal transition is seen
+ * | | |as the signal bounce and will not trigger the interrupt.
+ * | | |The DBEN[7] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The bit[7] de-bounce function is disabled
+ * | | |1 = The bit[7] de-bounce function is enabled
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered,
+ * | | |the de-bounce enable bit is ignored.
+ */
+ __IO uint32_t DBEN;
+
+ /**
+ * IMD
+ * ===================================================================================================
+ * Port 0-4 Interrupt Mode Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IMD0 |Port 0 Interrupt Mode Control
+ * | | |IMD[0] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge
+ * | | |trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is
+ * | | |sampled by one clock and the generate the interrupt
+ * | | |0 = Edge trigger interrupt
+ * | | |1 = Level trigger interrupt
+ * | | |if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN.
+ * | | |if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the
+ * | | |de-bounce enable bit is ignored.
+ * |[1] |IMD1 |Port 0 Interrupt Mode Control
+ * | | |IMD[1] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge
+ * | | |trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is
+ * | | |sampled by one clock and the generate the interrupt
+ * | | |0 = Edge trigger interrupt
+ * | | |1 = Level trigger interrupt
+ * | | |if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN.
+ * | | |if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the
+ * | | |de-bounce enable bit is ignored.
+ * |[2] |IMD2 |Port 0 Interrupt Mode Control
+ * | | |IMD[2] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge
+ * | | |trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is
+ * | | |sampled by one clock and the generate the interrupt
+ * | | |0 = Edge trigger interrupt
+ * | | |1 = Level trigger interrupt
+ * | | |if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN.
+ * | | |if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the
+ * | | |de-bounce enable bit is ignored.
+ * |[3] |IMD3 |Port 0 Interrupt Mode Control
+ * | | |IMD[3] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge
+ * | | |trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is
+ * | | |sampled by one clock and the generate the interrupt
+ * | | |0 = Edge trigger interrupt
+ * | | |1 = Level trigger interrupt
+ * | | |if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN.
+ * | | |if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the
+ * | | |de-bounce enable bit is ignored.
+ * |[4] |IMD4 |Port 0 Interrupt Mode Control
+ * | | |IMD[4] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge
+ * | | |trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is
+ * | | |sampled by one clock and the generate the interrupt
+ * | | |0 = Edge trigger interrupt
+ * | | |1 = Level trigger interrupt
+ * | | |if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN.
+ * | | |if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the
+ * | | |de-bounce enable bit is ignored.
+ * |[5] |IMD5 |Port 0 Interrupt Mode Control
+ * | | |IMD[5] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge
+ * | | |trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is
+ * | | |sampled by one clock and the generate the interrupt
+ * | | |0 = Edge trigger interrupt
+ * | | |1 = Level trigger interrupt
+ * | | |if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN.
+ * | | |if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the
+ * | | |de-bounce enable bit is ignored.
+ * |[6] |IMD6 |Port 0 Interrupt Mode Control
+ * | | |IMD[6] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge
+ * | | |trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is
+ * | | |sampled by one clock and the generate the interrupt
+ * | | |0 = Edge trigger interrupt
+ * | | |1 = Level trigger interrupt
+ * | | |if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN.
+ * | | |if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the
+ * | | |de-bounce enable bit is ignored.
+ * |[7] |IMD7 |Port 0 Interrupt Mode Control
+ * | | |IMD[7] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge
+ * | | |trigger, the trigger souce is control de-bounce. If the interrupt is by level trigger, the input source is
+ * | | |sampled by one clock and the generate the interrupt
+ * | | |0 = Edge trigger interrupt
+ * | | |1 = Level trigger interrupt
+ * | | |if set pin as the level trigger interrupt, then only one level can be set on the registers P0_IEN.
+ * | | |if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the
+ * | | |de-bounce enable bit is ignored.
+ */
+ __IO uint32_t IMD;
+
+ /**
+ * IEN
+ * ===================================================================================================
+ * Port 0-4 Interrupt Enable Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IF_EN0 |Port0 Interrupt Enable by Input Falling Edge or Input Level Low
+ * | | |IF_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IF_EN[0] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[0] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[0] state change from "high-to-low" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[0] state low-level or high-to-low change interrupt
+ * | | |0 = Disable the P0[0] state low-level or high-to-low change interrupt
+ * |[1] |IF_EN1 |Port0 Interrupt Enable by Input Falling Edge or Input Level Low
+ * | | |IF_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IF_EN[1] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[1] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[1] state change from "high-to-low" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[1] state low-level or high-to-low change interrupt
+ * | | |0 = Disable the P0[1] state low-level or high-to-low change interrupt
+ * |[2] |IF_EN2 |Port0 Interrupt Enable by Input Falling Edge or Input Level Low
+ * | | |IF_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IF_EN[2] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[2] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[2] state change from "high-to-low" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[2] state low-level or high-to-low change interrupt
+ * | | |0 = Disable the P0[2] state low-level or high-to-low change interrupt
+ * |[3] |IF_EN3 |Port0 Interrupt Enable by Input Falling Edge or Input Level Low
+ * | | |IF_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IF_EN[3] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[3] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[3] state change from "high-to-low" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[3] state low-level or high-to-low change interrupt
+ * | | |0 = Disable the P0[3] state low-level or high-to-low change interrupt
+ * |[4] |IF_EN4 |Port0 Interrupt Enable by Input Falling Edge or Input Level Low
+ * | | |IF_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IF_EN[4] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[4] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[4] state change from "high-to-low" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[4] state low-level or high-to-low change interrupt
+ * | | |0 = Disable the P0[4] state low-level or high-to-low change interrupt
+ * |[5] |IF_EN5 |Port0 Interrupt Enable by Input Falling Edge or Input Level Low
+ * | | |IF_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IF_EN[5] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[5] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[5] state change from "high-to-low" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[5] state low-level or high-to-low change interrupt
+ * | | |0 = Disable the P0[5] state low-level or high-to-low change interrupt
+ * |[6] |IF_EN6 |Port0 Interrupt Enable by Input Falling Edge or Input Level Low
+ * | | |IF_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IF_EN[6] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[6] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[6] state change from "high-to-low" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[6] state low-level or high-to-low change interrupt
+ * | | |0 = Disable the P0[6] state low-level or high-to-low change interrupt
+ * |[7] |IF_EN7 |Port0 Interrupt Enable by Input Falling Edge or Input Level Low
+ * | | |IF_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IF_EN[7] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[7] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[7] state change from "high-to-low" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[7] state low-level or high-to-low change interrupt
+ * | | |0 = Disable the P0[7] state low-level or high-to-low change interrupt
+ * |[16] |IR_EN0 |Port 0 Interrupt Enable by Input Rising Edge or Input Level High
+ * | | |IR_EN[0] used to enable the interrupt for each of the corresponding input P0[0]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IR_EN[0] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[0] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[0] state change from "low-to-high" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[0] level-high or low-to-high interrupt
+ * | | |0 = Disable the P0[0] level-high or low-to-high interrupt
+ * |[17] |IR_EN1 |Port 0 Interrupt Enable by Input Rising Edge or Input Level High
+ * | | |IR_EN[1] used to enable the interrupt for each of the corresponding input P0[1]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IR_EN[1] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[1] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[1] state change from "low-to-high" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[1] level-high or low-to-high interrupt
+ * | | |0 = Disable the P0[1] level-high or low-to-high interrupt
+ * |[18] |IR_EN2 |Port 0 Interrupt Enable by Input Rising Edge or Input Level High
+ * | | |IR_EN[2] used to enable the interrupt for each of the corresponding input P0[2]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IR_EN[2] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[2] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[2] state change from "low-to-high" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[2] level-high or low-to-high interrupt
+ * | | |0 = Disable the P0[2] level-high or low-to-high interrupt
+ * |[19] |IR_EN3 |Port 0 Interrupt Enable by Input Rising Edge or Input Level High
+ * | | |IR_EN[3] used to enable the interrupt for each of the corresponding input P0[3]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IR_EN[3] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[3] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[3] state change from "low-to-high" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[3] level-high or low-to-high interrupt
+ * | | |0 = Disable the P0[3] level-high or low-to-high interrupt
+ * |[20] |IR_EN4 |Port 0 Interrupt Enable by Input Rising Edge or Input Level High
+ * | | |IR_EN[4] used to enable the interrupt for each of the corresponding input P0[4]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IR_EN[4] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[4] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[4] state change from "low-to-high" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[4] level-high or low-to-high interrupt
+ * | | |0 = Disable the P0[4] level-high or low-to-high interrupt
+ * |[21] |IR_EN5 |Port 0 Interrupt Enable by Input Rising Edge or Input Level High
+ * | | |IR_EN[5] used to enable the interrupt for each of the corresponding input P0[5]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IR_EN[5] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[5] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[5] state change from "low-to-high" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[5] level-high or low-to-high interrupt
+ * | | |0 = Disable the P0[5] level-high or low-to-high interrupt
+ * |[22] |IR_EN6 |Port 0 Interrupt Enable by Input Rising Edge or Input Level High
+ * | | |IR_EN[6] used to enable the interrupt for each of the corresponding input P0[6]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IR_EN[6] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[6] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[6] state change from "low-to-high" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[6] level-high or low-to-high interrupt
+ * | | |0 = Disable the P0[6] level-high or low-to-high interrupt
+ * |[23] |IR_EN7 |Port 0 Interrupt Enable by Input Rising Edge or Input Level High
+ * | | |IR_EN[7] used to enable the interrupt for each of the corresponding input P0[7]. Set bit "1" also
+ * | | |enable the pin wakeup function.
+ * | | |When set the IR_EN[7] bit "1":
+ * | | |If the interrupt is level mode trigger, the input P0[7] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input P0[7] state change from "low-to-high" will generate
+ * | | |the interrupt.
+ * | | |1 = Enable the P0[7] level-high or low-to-high interrupt
+ * | | |0 = Disable the P0[7] level-high or low-to-high interrupt
+ */
+ __IO uint32_t IEN;
+
+ /**
+ * ISRC
+ * ===================================================================================================
+ * Port 0-4 Interrupt Trigger Source
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISRC0 |Port 0 Interrupt Trigger Source Indicator
+ * | | |Read:
+ * | | |1 = Indicates P0[0] generate an interrupt
+ * | | |0 = No interrupt at P0[0]
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt
+ * | | |0 = No action
+ * |[1] |ISRC1 |Port 0 Interrupt Trigger Source Indicator
+ * | | |Read:
+ * | | |1 = Indicates P0[1] generate an interrupt
+ * | | |0 = No interrupt at P0[1]
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt
+ * | | |0 = No action
+ * |[2] |ISRC2 |Port 0 Interrupt Trigger Source Indicator
+ * | | |Read:
+ * | | |1 = Indicates P0[2] generate an interrupt
+ * | | |0 = No interrupt at P0[2]
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt
+ * | | |0 = No action
+ * |[3] |ISRC3 |Port 0 Interrupt Trigger Source Indicator
+ * | | |Read:
+ * | | |1 = Indicates P0[3] generate an interrupt
+ * | | |0 = No interrupt at P0[3]
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt
+ * | | |0 = No action
+ * |[4] |ISRC4 |Port 0 Interrupt Trigger Source Indicator
+ * | | |Read:
+ * | | |1 = Indicates P0[4] generate an interrupt
+ * | | |0 = No interrupt at P0[4]
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt
+ * | | |0 = No action
+ * |[5] |ISRC5 |Port 0 Interrupt Trigger Source Indicator
+ * | | |Read:
+ * | | |1 = Indicates P0[5] generate an interrupt
+ * | | |0 = No interrupt at P0[5]
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt
+ * | | |0 = No action
+ * |[6] |ISRC6 |Port 0 Interrupt Trigger Source Indicator
+ * | | |Read:
+ * | | |1 = Indicates P0[6] generate an interrupt
+ * | | |0 = No interrupt at P0[6]
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt
+ * | | |0 = No action
+ * |[7] |ISRC7 |Port 0 Interrupt Trigger Source Indicator
+ * | | |Read:
+ * | | |1 = Indicates P0[7] generate an interrupt
+ * | | |0 = No interrupt at P0[7]
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt
+ * | | |0 = No action
+ */
+ __IO uint32_t ISRC;
+} GPIO_T;
+
+typedef struct
+{
+ /**
+ * DBNCECON
+ * ===================================================================================================
+ * Offset: 0x180 Interrupt De-bounce Cycle Control
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DBCLKSEL |De-bounce sampling cycle selection
+ * | | |DBCLKSEL
+ * | | |Description
+ * | | |0 = Sample interrupt input once per 1 clocks
+ * | | |1 = Sample interrupt input once per 2 clocks
+ * | | |2 = Sample interrupt input once per 4 clocks
+ * | | |3 = Sample interrupt input once per 8 clocks
+ * | | |4 = Sample interrupt input once per 16 clocks
+ * | | |5 = Sample interrupt input once per 32 clocks
+ * | | |6 = Sample interrupt input once per 64 clocks
+ * | | |7 = Sample interrupt input once per 128 clocks
+ * | | |8 = Sample interrupt input once per 256 clocks
+ * | | |9 = Sample interrupt input once per 2*256 clocks
+ * | | |10 = Sample interrupt input once per 4*256clocks
+ * | | |11 = Sample interrupt input once per 8*256 clocks
+ * | | |12 = Sample interrupt input once per 16*256 clocks
+ * | | |13 = Sample interrupt input once per 32*256 clocks
+ * | | |14 = Sample interrupt input once per 64*256 clocks
+ * | | |15 = Sample interrupt input once per 128*256 clocks
+ * |[4] |DBCLKSRC |De-bounce counter clock source select
+ * | | |1 = De-bounce counter clock source is the internal 10KHz clock
+ * | | |0 = De-bounce counter clock source is the HCLK
+ * |[5] |ICLK_ON |Interrupt clock On mode
+ * | | |Set this bit "0" will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled
+ * | | |0 = disable the clock if the P0/1/2/3/4[n] interrupt is disabled
+ * | | |1 = interrupt generated circuit clock always enable
+ * | | |n=0~7
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __IO uint32_t DBNCECON;
+} GPIO_DBNCECON_T;
+
+
+/** @addtogroup GPIO_CONST GPIO Bit Field Definition
+ Constant Definitions for GPIO Controller
+ @{
+ */
+
+/* GPIO PMD Bit Field Definitions */
+#define GPIO_PMD_PMD7_Pos 14 /*!< GPIO PMD: PMD7 Position */
+#define GPIO_PMD_PMD7_Msk (0x3ul << GPIO_PMD_PMD7_Pos) /*!< GPIO PMD: PMD7 Mask */
+
+#define GPIO_PMD_PMD6_Pos 12 /*!< GPIO PMD: PMD6 Position */
+#define GPIO_PMD_PMD6_Msk (0x3ul << GPIO_PMD_PMD6_Pos) /*!< GPIO PMD: PMD6 Mask */
+
+#define GPIO_PMD_PMD5_Pos 10 /*!< GPIO PMD: PMD5 Position */
+#define GPIO_PMD_PMD5_Msk (0x3ul << GPIO_PMD_PMD5_Pos) /*!< GPIO PMD: PMD5 Mask */
+
+#define GPIO_PMD_PMD4_Pos 8 /*!< GPIO PMD: PMD4 Position */
+#define GPIO_PMD_PMD4_Msk (0x3ul << GPIO_PMD_PMD4_Pos) /*!< GPIO PMD: PMD4 Mask */
+
+#define GPIO_PMD_PMD3_Pos 6 /*!< GPIO PMD: PMD3 Position */
+#define GPIO_PMD_PMD3_Msk (0x3ul << GPIO_PMD_PMD3_Pos) /*!< GPIO PMD: PMD3 Mask */
+
+#define GPIO_PMD_PMD2_Pos 4 /*!< GPIO PMD: PMD2 Position */
+#define GPIO_PMD_PMD2_Msk (0x3ul << GPIO_PMD_PMD2_Pos) /*!< GPIO PMD: PMD2 Mask */
+
+#define GPIO_PMD_PMD1_Pos 2 /*!< GPIO PMD: PMD1 Position */
+#define GPIO_PMD_PMD1_Msk (0x3ul << GPIO_PMD_PMD1_Pos) /*!< GPIO PMD: PMD1 Mask */
+
+#define GPIO_PMD_PMD0_Pos 0 /*!< GPIO PMD: PMD0 Position */
+#define GPIO_PMD_PMD0_Msk (0x3ul << GPIO_PMD_PMD0_Pos) /*!< GPIO PMD: PMD0 Mask */
+
+/* GPIO OFFD Bit Field Definitions */
+#define GPIO_OFFD_OFFD_Pos 16 /*!< GPIO OFFD: OFFD Position */
+#define GPIO_OFFD_OFFD_Msk (0xFFul << GPIO_OFFD_OFFD_Pos) /*!< GPIO OFFD: OFFD Mask */
+
+/* GPIO DOUT Bit Field Definitions */
+#define GPIO_DOUT_DOUT_Pos 0 /*!< GPIO DOUT: DOUT Position */
+#define GPIO_DOUT_DOUT_Msk (0xFFul << GPIO_DOUT_DOUT_Pos) /*!< GPIO DOUT: DOUT Mask */
+
+/* GPIO DMASK Bit Field Definitions */
+#define GPIO_DMASK_DMASK_Pos 0 /*!< GPIO DMASK: DMASK Position */
+#define GPIO_DMASK_DMASK_Msk (0xFFul << GPIO_DMASK_DMASK_Pos) /*!< GPIO DMASK: DMASK Mask */
+
+/* GPIO PIN Bit Field Definitions */
+#define GPIO_PIN_PIN_Pos 0 /*!< GPIO PIN: PIN Position */
+#define GPIO_PIN_PIN_Msk (0xFFul << GPIO_PIN_PIN_Pos) /*!< GPIO PIN: PIN Mask */
+
+/* GPIO DBEN Bit Field Definitions */
+#define GPIO_DBEN_DBEN_Pos 0 /*!< GPIO DBEN: DBEN Position */
+#define GPIO_DBEN_DBEN_Msk (0xFFul << GPIO_DBEN_DBEN_Pos) /*!< GPIO DBEN: DBEN Mask */
+
+/* GPIO IMD Bit Field Definitions */
+#define GPIO_IMD_IMD_Pos 0 /*!< GPIO IMD: IMD Position */
+#define GPIO_IMD_IMD_Msk (0xFFul << GPIO_IMD_IMD_Pos) /*!< GPIO IMD: IMD Mask */
+
+/* GPIO IEN Bit Field Definitions */
+#define GPIO_IEN_IR_EN_Pos 16 /*!< GPIO IEN: IR_EN Position */
+#define GPIO_IEN_IR_EN_Msk (0xFFul << GPIO_IEN_IR_EN_Pos) /*!< GPIO IEN: IR_EN Mask */
+
+#define GPIO_IEN_IF_EN_Pos 0 /*!< GPIO IEN: IF_EN Position */
+#define GPIO_IEN_IF_EN_Msk (0xFFul << GPIO_IEN_IF_EN_Pos) /*!< GPIO IEN: IF_EN Mask */
+
+/* GPIO ISRC Bit Field Definitions */
+#define GPIO_ISRC_ISRC_Pos 0 /*!< GPIO ISRC: ISRC Position */
+#define GPIO_ISRC_ISRC_Msk (0xFFul << GPIO_ISRC_ISRC_Pos) /*!< GPIO ISRC: ISRC Mask */
+
+/* GPIO DBNCECON Bit Field Definitions */
+#define GPIO_DBNCECON_ICLK_ON_Pos 5 /*!< GPIO DBNCECON: ICLK_ON Position */
+#define GPIO_DBNCECON_ICLK_ON_Msk (1ul << GPIO_DBNCECON_ICLK_ON_Pos) /*!< GPIO DBNCECON: ICLK_ON Mask */
+
+#define GPIO_DBNCECON_DBCLKSRC_Pos 4 /*!< GPIO DBNCECON: DBCLKSRC Position */
+#define GPIO_DBNCECON_DBCLKSRC_Msk (1ul << GPIO_DBNCECON_DBCLKSRC_Pos) /*!< GPIO DBNCECON: DBCLKSRC Mask */
+
+#define GPIO_DBNCECON_DBCLKSEL_Pos 0 /*!< GPIO DBNCECON: DBCLKSEL Position */
+#define GPIO_DBNCECON_DBCLKSEL_Msk (0xFul << GPIO_DBNCECON_DBCLKSEL_Pos) /*!< GPIO DBNCECON: DBCLKSEL Mask */
+/**@}*/ /* GPIO_CONST */
+/**@}*/ /* GPIO */
+
+
+/*------------------------------ I2C Controller ------------------------------*/
+
+/** @addtogroup I2C I2C Controller(I2C)
+ Memory Mapped Structure for I2C Serial Interface Controller
+ @{
+ */
+typedef struct
+{
+ /**
+ * I2CON
+ * ===================================================================================================
+ * Offset: 0x00 I2C Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2] |AA |Assert Acknowledge control bit.
+ * | | |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during
+ * | | |the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from
+ * | | |master, 2.) The receiver devices are acknowledging the data sent by transmitter. When AA=0 prior to
+ * | | |address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge
+ * | | |clock pulse on the SCL line.
+ * |[3] |SI |I2C Interrupt Flag.
+ * | | |When a new SIO state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI
+ * | | |(I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one
+ * | | |to this bit.
+ * |[4] |STO |I2C STOP Flag.
+ * | | |In master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus
+ * | | |condition if a STOP condition is detected this flag will be cleared by hardware automatically.
+ * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. This means
+ * | | |it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
+ * |[5] |STA |I2C START Flag.
+ * | | |Setting STA to logic 1 to enter master mode, the I2C hardware sends a START or repeat START condition
+ * | | |to bus when the bus is free.
+ * |[6] |ENSI |I2C controller is enabled/disable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * | | |Set to enable I2C serial function block. When ENS=1 the I2C serial function enables. The multi-function
+ * | | |pin function of SDA and SCL must set to I2C function first.
+ * |[7] |EI |Enable interrupt.
+ * | | |1 = Enable I2C interrupt.
+ * | | |0 = Disable I2C interrupt.
+ */
+ __IO uint32_t I2CON;
+
+ /**
+ * I2CADDR0
+ * ===================================================================================================
+ * Offset: 0x04 I2C Slave Address Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = Disable General Call Function.
+ * | | |1 = Enable General Call Function.
+ * |[7:1] |I2CADDR |I2C Address Register
+ * | | |The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven
+ * | | |most significant bits must be loaded with the MCU's own address. The I2C hardware will react if
+ * | | |either of the address is matched.
+ */
+ __IO uint32_t I2CADDR0;
+
+ /**
+ * I2CDAT
+ * ===================================================================================================
+ * Offset: 0x08 I2C Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |I2CDAT |I2C Data Register
+ * | | |Bit[7:0] is located with the 8-bit transferred data of I2C serial port.
+ */
+ __IO uint32_t I2CDAT;
+
+ /**
+ * I2CSTATUS
+ * ===================================================================================================
+ * Offset: 0x0C I2C Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |I2CSTATUS |I2C Status Register
+ * | | |The status register of I2C:
+ * | | |The three least significant bits are always 0. The five most significant bits contain the status code.
+ * | | |There are 26 possible status codes. When I2STATUS contains F8H, no serial interrupt is
+ * | | |requested. All other I2STATUS values correspond to defined I2C states. When each of these
+ * | | |states is entered, a status interrupt is requested (SI = 1). A valid status code is present in
+ * | | |I2STATUS one machine cycle after SI is set by hardware and is still present one machine cycle
+ * | | |after SI has been reset by software. In addition, states 00H stands for a Bus Error. A Bus Error
+ * | | |occurs when a START or STOP condition is present at an illegal position in the formation frame.
+ * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an
+ * | | |acknowledge bit.
+ */
+ __I uint32_t I2CSTATUS;
+
+ /**
+ * I2CLK
+ * ===================================================================================================
+ * Offset: 0x10 I2C Clock Divided Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |I2CLK |I2C clock divided Register
+ * | | |The I2C clock rate bits: Data Baud Rate of I2C = PCLK /(4x(I2CLK+1)).
+ */
+ __IO uint32_t I2CLK;
+
+ /**
+ * I2CTOC
+ * ===================================================================================================
+ * Offset: 0x14 I2C Time-Out Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TIF |Time-Out flag.
+ * | | |1 = Time-Out falg is set by H/W. It can interrupt CPU.
+ * | | |0 = S/W can clear the flag.
+ * |[1] |DIV4 |Time-Out counter input clock is divider by 4
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * | | |When Enable, The time-Out period is prolong 4 times.
+ * |[2] |ENTI |Time-out counter is enabled/disable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * | | |When Enable, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will
+ * | | |reset counter and re-start up counting after SI is cleared.
+ */
+ __IO uint32_t I2CTOC;
+
+ /**
+ * I2CADDR1
+ * ===================================================================================================
+ * Offset: 0x18 I2C Slave Address Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = Disable General Call Function.
+ * | | |1 = Enable General Call Function.
+ * |[7:1] |I2CADDR |I2C Address Register
+ * | | |The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven
+ * | | |most significant bits must be loaded with the MCU's own address. The I2C hardware will react if
+ * | | |either of the address is matched.
+ */
+ __IO uint32_t I2CADDR1;
+
+ /**
+ * I2CADDR2
+ * ===================================================================================================
+ * Offset: 0x1C I2C Slave Address Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = Disable General Call Function.
+ * | | |1 = Enable General Call Function.
+ * |[7:1] |I2CADDR |I2C Address Register
+ * | | |The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven
+ * | | |most significant bits must be loaded with the MCU's own address. The I2C hardware will react if
+ * | | |either of the address is matched.
+ */
+ __IO uint32_t I2CADDR2;
+
+ /**
+ * I2CADDR3
+ * ===================================================================================================
+ * Offset: 0x20 I2C Slave Address Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = Disable General Call Function.
+ * | | |1 = Enable General Call Function.
+ * |[7:1] |I2CADDR |I2C Address Register
+ * | | |The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven
+ * | | |most significant bits must be loaded with the MCU's own address. The I2C hardware will react if
+ * | | |either of the address is matched.
+ */
+ __IO uint32_t I2CADDR3;
+
+ /**
+ * I2CADM0
+ * ===================================================================================================
+ * Offset: 0x24 I2C Slave Address Mask Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |I2ADMx |I2C Address Mask register
+ * | | |1 = Mask enable (the received corresponding address bit is don't care.)
+ * | | |0 = Mask disable (the received corresponding register bit should be exact the same as
+ * | | |address register.)
+ * | | |I2C bus controllers support multiple address recognition with four address mask register.
+ * | | |When the bit in the address mask register is set to one, it means the received
+ * | | |corresponding address bit is don't-care. If the bit is set to zero, that means the received
+ * | | |corresponding register bit should be exact the same as address register.
+ */
+ __IO uint32_t I2CADM0;
+
+ /**
+ * I2CADM1
+ * ===================================================================================================
+ * Offset: 0x28 I2C Slave Address Mask Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |I2ADMx |I2C Address Mask register
+ * | | |1 = Mask enable (the received corresponding address bit is don't care.)
+ * | | |0 = Mask disable (the received corresponding register bit should be exact the same as
+ * | | |address register.)
+ * | | |I2C bus controllers support multiple address recognition with four address mask register.
+ * | | |When the bit in the address mask register is set to one, it means the received
+ * | | |corresponding address bit is don't-care. If the bit is set to zero, that means the received
+ * | | |corresponding register bit should be exact the same as address register.
+ */
+ __IO uint32_t I2CADM1;
+
+ /**
+ * I2CADM2
+ * ===================================================================================================
+ * Offset: 0x2C I2C Slave Address Mask Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |I2ADMx |I2C Address Mask register
+ * | | |1 = Mask enable (the received corresponding address bit is don't care.)
+ * | | |0 = Mask disable (the received corresponding register bit should be exact the same as
+ * | | |address register.)
+ * | | |I2C bus controllers support multiple address recognition with four address mask register.
+ * | | |When the bit in the address mask register is set to one, it means the received
+ * | | |corresponding address bit is don't-care. If the bit is set to zero, that means the received
+ * | | |corresponding register bit should be exact the same as address register.
+ */
+ __IO uint32_t I2CADM2;
+
+ /**
+ * I2CADM3
+ * ===================================================================================================
+ * Offset: 0x30 I2C Slave Address Mask Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |I2ADMx |I2C Address Mask register
+ * | | |1 = Mask enable (the received corresponding address bit is don't care.)
+ * | | |0 = Mask disable (the received corresponding register bit should be exact the same as
+ * | | |address register.)
+ * | | |I2C bus controllers support multiple address recognition with four address mask register.
+ * | | |When the bit in the address mask register is set to one, it means the received
+ * | | |corresponding address bit is don't-care. If the bit is set to zero, that means the received
+ * | | |corresponding register bit should be exact the same as address register.
+ */
+ __IO uint32_t I2CADM3;
+
+ /**
+ * RESERVED0
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ uint32_t RESERVED0[2];
+
+ /**
+ * I2CWKUPCON
+ * ===================================================================================================
+ * Offset: 0x3C I2C Wake Up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __IO uint32_t I2CWKUPCON;
+
+ /**
+ * I2CWKUPSTS
+ * ===================================================================================================
+ * Offset: 0x40 I2C Wake Up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __IO uint32_t I2CWKUPSTS;
+
+} I2C_T;
+
+/** @addtogroup I2C_CONST I2C Bit Field Definition
+ Constant Definitions for I2C Controller
+ @{
+ */
+
+/* I2C I2CON Bit Field Definitions */
+#define I2C_I2CON_EI_Pos 7 /*!< I2C I2CON: EI Position */
+#define I2C_I2CON_EI_Msk (1ul << I2C_I2CON_EI_Pos) /*!< I2C I2CON: EI Mask */
+
+#define I2C_I2CON_ENS1_Pos 6 /*!< I2C I2CON: ENS1 Position */
+#define I2C_I2CON_ENS1_Msk (1ul << I2C_I2CON_ENS1_Pos) /*!< I2C I2CON: ENS1 Mask */
+
+#define I2C_I2CON_STA_Pos 5 /*!< I2C I2CON: STA Position */
+#define I2C_I2CON_STA_Msk (1ul << I2C_I2CON_STA_Pos) /*!< I2C I2CON: STA Mask */
+
+#define I2C_I2CON_STO_Pos 4 /*!< I2C I2CON: STO Position */
+#define I2C_I2CON_STO_Msk (1ul << I2C_I2CON_STO_Pos) /*!< I2C I2CON: STO Mask */
+
+#define I2C_I2CON_SI_Pos 3 /*!< I2C I2CON: SI Position */
+#define I2C_I2CON_SI_Msk (1ul << I2C_I2CON_SI_Pos) /*!< I2C I2CON: SI Mask */
+
+#define I2C_I2CON_AA_Pos 2 /*!< I2C I2CON: AA Position */
+#define I2C_I2CON_AA_Msk (1ul << I2C_I2CON_AA_Pos) /*!< I2C I2CON: AA Mask */
+
+/* I2C I2CADDR Bit Field Definitions */
+#define I2C_I2CADDR_I2CADDR_Pos 1 /*!< I2C I2CADDR: I2CADDR Position */
+#define I2C_I2CADDR_I2CADDR_Msk (0x7Ful << I2C_I2CADDR_I2CADDR_Pos) /*!< I2C I2CADDR: I2CADDR Mask */
+
+#define I2C_I2CADDR_GC_Pos 0 /*!< I2C I2CADDR: GC Position */
+#define I2C_I2CADDR_GC_Msk (1ul << I2C_I2CADDR_GC_Pos) /*!< I2C I2CADDR: GC Mask */
+
+/* I2C I2CDAT Bit Field Definitions */
+#define I2C_I2CDAT_I2CDAT_Pos 0 /*!< I2C I2CDAT: I2CDAT Position */
+#define I2C_I2CDAT_I2CDAT_Msk (0xFFul << I2C_I2CDAT_I2CDAT_Pos) /*!< I2C I2CDAT: I2CDAT Mask */
+
+/* I2C I2CSTATUS Bit Field Definitions */
+#define I2C_I2CSTATUS_I2CSTATUS_Pos 0 /*!< I2C I2CSTATUS: I2CSTATUS Position */
+#define I2C_I2CSTATUS_I2CSTATUS_Msk (0xFFul << I2C_I2CSTATUS_I2CSTATUS_Pos) /*!< I2C I2CSTATUS: I2CSTATUS Mask */
+
+/* I2C I2CLK Bit Field Definitions */
+#define I2C_I2CLK_I2CLK_Pos 0 /*!< I2C I2CLK: I2CLK Position */
+#define I2C_I2CLK_I2CLK_Msk (0xFFul << I2C_I2CLK_I2CLK_Pos) /*!< I2C I2CLK: I2CLK Mask */
+
+/* I2C I2CTOC Bit Field Definitions */
+#define I2C_I2CTOC_ENTI_Pos 2 /*!< I2C I2CTOC: ENTI Position */
+#define I2C_I2CTOC_ENTI_Msk (1ul << I2C_I2CTOC_ENTI_Pos) /*!< I2C I2CTOC: ENTI Mask */
+
+#define I2C_I2CTOC_DIV4_Pos 1 /*!< I2C I2CTOC: DIV4 Position */
+#define I2C_I2CTOC_DIV4_Msk (1ul << I2C_I2CTOC_DIV4_Pos) /*!< I2C I2CTOC: DIV4 Mask */
+
+#define I2C_I2CTOC_TIF_Pos 0 /*!< I2C I2CTOC: TIF Position */
+#define I2C_I2CTOC_TIF_Msk (1ul << I2C_I2CTOC_TIF_Pos) /*!< I2C I2CTOC: TIF Mask */
+
+/* I2C I2CADM Bit Field Definitions */
+#define I2C_I2CADM_I2CADM_Pos 1 /*!< I2C I2CADM: I2CADM Position */
+#define I2C_I2CADM_I2CADM_Msk (0x7Ful << I2C_I2CADM_I2CADM_Pos) /*!< I2C I2CADM: I2CADM Mask */
+
+/* I2C I2CWKUPCON Bit Field Definitions */
+#define I2C_I2CWKUPCON_WKUPEN_Pos 0 /*!< I2C I2CWKUPCON: WKUPEN Position */
+#define I2C_I2CWKUPCON_WKUPEN_Msk (1ul << I2C_I2CWKUPCON_WKUPEN_Pos) /*!< I2C I2CWKUPCON: WKUPEN Mask */
+
+/* I2C I2CWKUPSTS Bit Field Definitions */
+#define I2C_I2CWKUPSTS_WKUPIF_Pos 0 /*!< I2C I2CWKUPSTS: WKUPIF Position */
+#define I2C_I2CWKUPSTS_WKUPIF_Msk (1ul << I2C_I2CWKUPSTS_WKUPIF_Pos) /*!< I2C I2CWKUPSTS: WKUPIF Mask */
+
+/**@}*/ /* I2C_CONST */
+/**@}*/ /* I2C */
+
+
+
+/*----------------------------- PWM Controller -------------------------------*/
+
+/** @addtogroup PWM PWM Controller(PWM)
+ Memory Mapped Structure for PWM Generator and Capture Timer
+ @{
+ */
+typedef struct
+{
+ /**
+ * PPR
+ * ===================================================================================================
+ * Offset: 0x00 PWM Pre-Scale Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CP01 |Clock pre-scalar 0(PWM counter 0 & 1 for group A and PWM counter 4 & 5 for group B)
+ * | | |Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter
+ * | | |If CP01=0, then the pre-scalar 0 output clock will be stopped. So corresponding PWM
+ * | | |counter will be stopped also.
+ * |[15:8] |CP23 |Clock pre-scalar 2(PWM counter 2 & 3 for group A and PWM counter 6 & 7 for group B)
+ * | | |Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter
+ * | | |If CP23=0, then the pre-scalar 2 output clock will be stopped. So corresponding PWM
+ * | | |counter will be stopped also.
+ * |[23:16] |DZI01 |Dead zone interval register for pair of channel 0 and channel 1(PWM0 and PWM1 pair
+ * | | |for PWM group A, PWM4 and PWM5 pair for PWM group B)
+ * | | |These 8 bits determine dead zone length.
+ * | | |The unit time of dead zone length is received from corresponding CSR bits.
+ * |[31:24] |DZI23 |Dead zone interval register for pair of channel 2 and channel 3(PWM2 and PWM3 pair
+ * | | |for PWM group A, PWM6 and PWM7 pair for PWM group B)
+ * | | |These 8 bits determine dead zone length.
+ * | | |The unit time of dead zone length is received from corresponding CSR bits.
+ */
+ __IO uint32_t PPR;
+
+ /**
+ * CSR
+ * ===================================================================================================
+ * Offset: 0x04 PWM Clock Source Divider Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |CSR0 |Timer 0 Clock Source Selection(PWM timer 0 for group A and PWM timer 4 for group B)
+ * | | |Select clock input for timer.
+ * | | |(Table is the same as CSR3)
+ * |[6:4] |CSR1 |Timer 1 Clock Source Selection(PWM timer 1 for group A and PWM timer 5 for group B)
+ * | | |Select clock input for timer.
+ * | | |(Table is the same as CSR3)
+ * |[10:8] |CSR2 |Timer 2 Clock Source Selection(PWM timer 2 for group A and PWM timer 6 for group B)
+ * | | |Select clock input for timer.
+ * | | |(Table is the same as CSR3)
+ * |[14:12] |CSR3 |Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B)
+ * | | |Select clock input for timer.
+ * | | |CSRx[2:0] = Input clock divider
+ * | | |100 = 1
+ * | | |011 = 16
+ * | | |010 = 8
+ * | | |001 = 4
+ * | | |000 = 2
+ */
+ __IO uint32_t CSR;
+
+ /**
+ * PCR
+ * ===================================================================================================
+ * Offset: 0x08 PWM Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CH0EN |PWM-Timer 0 Enable/Disable Start Run (PWM timer 0 for group A and PWM timer 4 for
+ * | | |group B)
+ * | | |1 = Enable corresponding PWM-Timer Start Run
+ * | | |0 = Stop corresponding PWM-Timer Running
+ * |[2] |CH0INV |PWM-Timer 0 Output Inverter ON/OFF(PWM timer 0 for group A and PWM timer 4 for
+ * | | |group B)
+ * | | |1 = Inverter ON
+ * | | |0 = Inverter OFF
+ * |[3] |CH0MOD |PWM-Timer 0 Auto-reload/One-Shot Mode(PWM timer 0 for group A and PWM timer 4
+ * | | |for group B)
+ * | | |1 = Auto-reload Mode
+ * | | |0 = One-Shot Mode
+ * | | |Note: If there is a rising transition at this bit, it will cause CNR0 and CMR0 be clear.
+ * |[4] |DZEN01 |Dead-Zone 0 Generator Enable/Disable(PWM0 and PWM1 pair for PWM group A,
+ * | | |PWM4 and PWM5 pair for PWM group B)
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * | | |Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a
+ * | | |complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a
+ * | | |complementary pair for PWM group B.
+ * |[5] |DZEN23 |Dead-Zone 2 Generator Enable/Disable(PWM2 and PWM3 pair for PWM group A,
+ * | | |PWM6 and PWM7 pair for PWM group B)
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * | | |Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a
+ * | | |complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a
+ * | | |complementary pair for PWM group B.
+ * |[8] |CH1EN |PWM-Timer 1 Enable/Disable Start Run (PWM timer 1 for group A and PWM timer 5 for
+ * | | |group B)
+ * | | |1 = Enable corresponding PWM-Timer Start Run
+ * | | |0 = Stop corresponding PWM-Timer Running
+ * |[10] |CH1INV |PWM-Timer 1 Output Inverter ON/OFF(PWM timer 1 for group A and PWM timer 5 for
+ * | | |group B)
+ * | | |1 = Inverter ON
+ * | | |0 = Inverter OFF
+ * |[11] |CH1MOD |PWM-Timer 1 Auto-reload/One-Shot Mode(PWM timer 1 for group A and PWM timer 5
+ * | | |for group B)
+ * | | |1 = Auto-reload Mode
+ * | | |0 = One-Shot Mode
+ * | | |Note: If there is a rising transition at this bit, it will cause CNR1 and CMR1 be clear.
+ * |[16] |CH2EN |PWM-Timer 2 Enable/Disable Start Run (PWM timer 2 for group A and PWM timer 6 for
+ * | | |group B)
+ * | | |1 = Enable corresponding PWM-Timer Start Run
+ * | | |0 = Stop corresponding PWM-Timer Running
+ * |[18] |CH2INV |PWM-Timer 2 Output Inverter ON/OFF(PWM timer 2 for group A and PWM timer 6 for
+ * | | |group B)
+ * | | |1 = Inverter ON
+ * | | |0 = Inverter OFF
+ * |[19] |CH2MOD |PWM-Timer 2 Auto-reload/One-Shot Mode(PWM timer 2 for group A and PWM timer 6
+ * | | |for group B)
+ * | | |1 = Auto-reload Mode
+ * | | |0 = One-Shot Mode
+ * | | |Note: If there is a rising transition at this bit, it will cause CNR2 and CMR2 be clear.
+ * |[24] |CH3EN |PWM-Timer 3 Enable/Disable Start Run (PWM timer 3 for group A and PWM timer 7 for
+ * | | |group B)
+ * | | |1 = Enable corresponding PWM-Timer Start Run
+ * | | |0 = Stop corresponding PWM-Timer Running
+ * |[26] |CH3INV |PWM-Timer 3 Output Inverter ON/OFF(PWM timer 3 for group A and PWM timer 7 for
+ * | | |group B)
+ * | | |1 = Inverter ON
+ * | | |0 = Inverter OFF
+ * |[27] |CH3MOD |PWM-Timer 3 Auto-reload/One-Shot Mode(PWM timer 3 for group A and PWM timer 7
+ * | | |for group B)
+ * | | |1 = Auto-reload Mode
+ * | | |0 = One-Shot Mode
+ * | | |Note: If there is a rising transition at this bit, it will cause CNR3 and CMR3 be clear.
+ */
+ __IO uint32_t PCR;
+
+ /**
+ * CNR0
+ * ===================================================================================================
+ * Offset: 0x0C PWM Counter 0/Timer 0 Loaded Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CNR |PWM Counter/Timer Loaded Value
+ * | | |CNR determines the PWM period.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23,
+ * | | |45 or 67, depends on selected PWM channel.
+ * | | |Duty ratio = (CMR+1)/(CNR+1).
+ * | | |CMR >= CNR: PWM output is always high.
+ * | | |CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit.
+ * | | |CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit
+ * | | |(Unit = one PWM clock cycle)
+ * | | |Note: Any write to CNR will take effect in next PWM cycle.
+ */
+ __IO uint32_t CNR0;
+
+ /**
+ * CMR0
+ * ===================================================================================================
+ * Offset: 0x10 PWM Comparator 0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMR |PWM Comparator Register
+ * | | |CNR determines the PWM duty.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23,
+ * | | |45 or 67, depends on selected PWM channel.
+ * | | |Duty ratio = (CMR+1)/(CNR+1).
+ * | | |CMR >= CNR: PWM output is always high.
+ * | | |CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit.
+ * | | |CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit
+ * | | |(Unit = one PWM clock cycle)
+ * | | |Note: Any write to CNR will take effect in next PWM cycle.
+ */
+ __IO uint32_t CMR0;
+
+ /**
+ * PDR0
+ * ===================================================================================================
+ * Offset: 0x14 PWM Data 0 Register(current counter 0 value)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PDR |PWM Data Register
+ * | | |User can monitor PDR to know the current value in 16-bit down counter.
+ */
+ __I uint32_t PDR0;
+
+ /**
+ * CNR1
+ * ===================================================================================================
+ * Offset: 0x18 PWM Counter 1/Timer 1 Loaded Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CNR |PWM Counter/Timer Loaded Value
+ * | | |CNR determines the PWM period.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23,
+ * | | |45 or 67, depends on selected PWM channel.
+ * | | |Duty ratio = (CMR+1)/(CNR+1).
+ * | | |CMR >= CNR: PWM output is always high.
+ * | | |CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit.
+ * | | |CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit
+ * | | |(Unit = one PWM clock cycle)
+ * | | |Note: Any write to CNR will take effect in next PWM cycle.
+ */
+ __IO uint32_t CNR1;
+
+ /**
+ * CMR1
+ * ===================================================================================================
+ * Offset: 0x1C PWM Comparator 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMR |PWM Comparator Register
+ * | | |CNR determines the PWM duty.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23,
+ * | | |45 or 67, depends on selected PWM channel.
+ * | | |Duty ratio = (CMR+1)/(CNR+1).
+ * | | |CMR >= CNR: PWM output is always high.
+ * | | |CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit.
+ * | | |CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit
+ * | | |(Unit = one PWM clock cycle)
+ * | | |Note: Any write to CNR will take effect in next PWM cycle.
+ */
+ __IO uint32_t CMR1;
+
+ /**
+ * PDR1
+ * ===================================================================================================
+ * Offset: 0x20 PWM Data 1 Register(current counter 1 value)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PDR |PWM Data Register
+ * | | |User can monitor PDR to know the current value in 16-bit down counter.
+ */
+ __I uint32_t PDR1;
+
+ /**
+ * CNR2
+ * ===================================================================================================
+ * Offset: 0x24 PWM Counter 2/Timer 2 Loaded Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CNR |PWM Counter/Timer Loaded Value
+ * | | |CNR determines the PWM period.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23,
+ * | | |45 or 67, depends on selected PWM channel.
+ * | | |Duty ratio = (CMR+1)/(CNR+1).
+ * | | |CMR >= CNR: PWM output is always high.
+ * | | |CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit.
+ * | | |CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit
+ * | | |(Unit = one PWM clock cycle)
+ * | | |Note: Any write to CNR will take effect in next PWM cycle.
+ */
+ __IO uint32_t CNR2;
+
+ /**
+ * CMR2
+ * ===================================================================================================
+ * Offset: 0x28 PWM Comparator 2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMR |PWM Comparator Register
+ * | | |CNR determines the PWM duty.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23,
+ * | | |45 or 67, depends on selected PWM channel.
+ * | | |Duty ratio = (CMR+1)/(CNR+1).
+ * | | |CMR >= CNR: PWM output is always high.
+ * | | |CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit.
+ * | | |CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit
+ * | | |(Unit = one PWM clock cycle)
+ * | | |Note: Any write to CNR will take effect in next PWM cycle.
+ */
+ __IO uint32_t CMR2;
+
+ /**
+ * PDR2
+ * ===================================================================================================
+ * Offset: 0x2C PWM Data 2 Register(current counter 2 value)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PDR |PWM Data Register
+ * | | |User can monitor PDR to know the current value in 16-bit down counter.
+ */
+ __I uint32_t PDR2;
+
+ /**
+ * CNR3
+ * ===================================================================================================
+ * Offset: 0x30 PWM Counter 3/Timer 3 Loaded Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CNR |PWM Counter/Timer Loaded Value
+ * | | |CNR determines the PWM period.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23,
+ * | | |45 or 67, depends on selected PWM channel.
+ * | | |Duty ratio = (CMR+1)/(CNR+1).
+ * | | |CMR >= CNR: PWM output is always high.
+ * | | |CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit.
+ * | | |CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit
+ * | | |(Unit = one PWM clock cycle)
+ * | | |Note: Any write to CNR will take effect in next PWM cycle.
+ */
+ __IO uint32_t CNR3;
+
+ /**
+ * CMR3
+ * ===================================================================================================
+ * Offset: 0x34 PWM Comparator 3 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMR |PWM Comparator Register
+ * | | |CNR determines the PWM duty.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)/(clock divider)/(CNR+1); where xy, could be 01, 23,
+ * | | |45 or 67, depends on selected PWM channel.
+ * | | |Duty ratio = (CMR+1)/(CNR+1).
+ * | | |CMR >= CNR: PWM output is always high.
+ * | | |CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit.
+ * | | |CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit
+ * | | |(Unit = one PWM clock cycle)
+ * | | |Note: Any write to CNR will take effect in next PWM cycle.
+ */
+ __IO uint32_t CMR3;
+
+ /**
+ * PDR3
+ * ===================================================================================================
+ * Offset: 0x38 PWM Data 3 Register(current counter 3 value)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PDR |PWM Data Register
+ * | | |User can monitor PDR to know the current value in 16-bit down counter.
+ */
+ __I uint32_t PDR3;
+
+ /**
+ * RESERVE0
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE0;
+
+ /**
+ * PIER
+ * ===================================================================================================
+ * Offset: 0x40 PWM Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWMIE0 |PWM channel 0 Interrupt Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[1] |PWMIE1 |PWM channel 1 Interrupt Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[2] |PWMIE2 |PWM channel 2 Interrupt Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ * |[3] |PWMIE3 |PWM channel 3 Interrupt Enable
+ * | | |1 = Enable
+ * | | |0 = Disable
+ */
+ __IO uint32_t PIER;
+
+ /**
+ * PIIR
+ * ===================================================================================================
+ * Offset: 0x44 PWM Interrupt Indication Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWMIF0 |PWM channel 0 Interrupt Status
+ * | | |Flag is set by hardware when PWM0 down counter reaches zero, software can clear this
+ * | | |bit by writing a one to it.
+ * |[1] |PWMIF1 |PWM channel 1 Interrupt Status
+ * | | |Flag is set by hardware when PWM1 down counter reaches zero, software can clear this
+ * | | |bit by writing a one to it.
+ * |[2] |PWMIF2 |PWM channel 2 Interrupt Status
+ * | | |Flag is set by hardware when PWM2 down counter reaches zero, software can clear this
+ * | | |bit by writing a one to it.
+ * |[3] |PWMIF3 |PWM channel 3 Interrupt Status
+ * | | |Flag is set by hardware when PWM3 down counter reaches zero, software can clear this
+ * | | |bit by writing a one to it.
+ */
+ __IO uint32_t PIIR;
+
+ /**
+ * RESERVE1
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE1[2];
+
+ /**
+ * CCR0
+ * ===================================================================================================
+ * Offset: 0x50 Capture 0/1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INV0 |PWM Group Channel 0 Inverter ON/OFF
+ * | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
+ * | | |0 = Inverter OFF
+ * |[1] |CRL_IE0 |PWM Group Channel 0 Rising Latch Interrupt Enable ON/OFF
+ * | | |1 = Enable rising latch interrupt
+ * | | |0 = Disable rising latch interrupt
+ * | | |When Enable, if Capture detects PWM group channel 0 has rising transition, Capture
+ * | | |issues an Interrupt.
+ * |[2] |CFL_IE0 |PWM Group Channel 0 Falling Latch Interrupt Enable ON/OFF
+ * | | |1 = Enable falling latch interrupt
+ * | | |0 = Disable falling latch interrupt
+ * | | |When Enable, if Capture detects PWM group channel 0 has falling transition, Capture
+ * | | |issues an Interrupt.
+ * |[3] |CAPCH0EN |Capture Channel 0 transition Enable/Disable
+ * | | |1 = Enable capture function on PWM group channel 0.
+ * | | |0 = Disable capture function on PWM group channel 0
+ * | | |When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising
+ * | | |latch) and CFLR (Falling latch).
+ * | | |When Disable, Capture does not update CRLR and CFLR, and disable PWM group
+ * | | |channel 0 Interrupt.
+ * |[4] |CAPIF0 |Capture0 Interrupt Indication Flag
+ * | | |If PWM group channel 0 rising latch interrupt is enabled (CRL_IE0=1), a rising transition occurs
+ * | | |at PWM group channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause
+ * | | |CAPIF0 to be set high if PWM group channel 0 falling latch interrupt is enabled (CFL_IE0=1).
+ * | | |This flag is clear by software with a write 1 to itself.
+ * |[6] |CRLRI0 |CRLR0 Latched Indicator Bit
+ * | | |When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of
+ * | | |PWM down-counter and this bit is set by hardware.
+ * | | |Clear this bit by writing a one to it.
+ * |[7] |CFLRI0 |CFLR0 Latched Indicator Bit
+ * | | |When PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of
+ * | | |PWM down-counter and this bit is set by hardware.
+ * | | |Clear this bit by writing a one to it.
+ * |[16] |INV1 |PWM Group Channel 1 Inverter ON/OFF
+ * | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
+ * | | |0 = Inverter OFF
+ * |[17] |CRL_IE1 |PWM Group Channel 1 Rising Latch Interrupt Enable ON/OFF
+ * | | |1 = Enable rising latch interrupt
+ * | | |0 = Disable rising latch interrupt
+ * | | |When Enable, if Capture detects PWM group channel 1 has rising transition, Capture
+ * | | |issues an Interrupt.
+ * |[18] |CFL_IE1 |PWM Group Channel 1 Falling Latch Interrupt Enable ON/OFF
+ * | | |1 = Enable falling latch interrupt
+ * | | |0 = Disable falling latch interrupt
+ * | | |When Enable, if Capture detects PWM group channel 1 has falling transition, Capture
+ * | | |issues an Interrupt.
+ * |[19] |CAPCH1EN |Capture Channel 1 transition Enable/Disable
+ * | | |1 = Enable capture function on PWM group channel 1.
+ * | | |0 = Disable capture function on PWM group channel 1
+ * | | |When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising
+ * | | |latch) and CFLR (Falling latch).
+ * | | |When Disable, Capture does not update CRLR and CFLR, and disable PWM group
+ * | | |channel 1 Interrupt.
+ * |[20] |CAPIF1 |Capture1 Interrupt Indication Flag
+ * | | |If PWM group channel 1 rising latch interrupt is enabled (CRL_IE1=1), a rising transition occurs
+ * | | |at PWM group channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause
+ * | | |CAPIF1 to be set high if PWM group channel 1 falling latch interrupt is enabled (CFL_IE1=1).
+ * | | |This flag is clear by software with a write 1 to itself.
+ * |[22] |CRLRI1 |CRLR1 Latched Indicator Bit
+ * | | |When PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of
+ * | | |PWM down-counter and this bit is set by hardware.
+ * | | |Clear this bit by writing a one to it.
+ * |[23] |CFLRI1 |CFLR1 Latched Indicator Bit
+ * | | |When PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of
+ * | | |PWM down-counter and this bit is set by hardware.
+ * | | |Clear this bit by writing a one to it.
+ */
+ __IO uint32_t CCR0;
+
+ /**
+ * CCR2
+ * ===================================================================================================
+ * Offset: 0x54 Capture 2/3 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INV2 |PWM Group Channel 2 Inverter ON/OFF
+ * | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
+ * | | |0 = Inverter OFF
+ * |[1] |CRL_IE2 |PWM Group Channel 2 Rising Latch Interrupt Enable ON/OFF
+ * | | |1 = Enable rising latch interrupt
+ * | | |0 = Disable rising latch interrupt
+ * | | |When Enable, if Capture detects PWM group channel 2 has rising transition, Capture
+ * | | |issues an Interrupt.
+ * |[2] |CFL_IE2 |PWM Group Channel 2 Falling Latch Interrupt Enable ON/OFF
+ * | | |1 = Enable falling latch interrupt
+ * | | |0 = Disable falling latch interrupt
+ * | | |When Enable, if Capture detects PWM group channel 2 has falling transition, Capture
+ * | | |issues an Interrupt.
+ * |[3] |CAPCH2EN |Capture Channel 2 transition Enable/Disable
+ * | | |1 = Enable capture function on PWM group channel 2.
+ * | | |0 = Disable capture function on PWM group channel 2
+ * | | |When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising
+ * | | |latch) and CFLR (Falling latch).
+ * | | |When Disable, Capture does not update CRLR and CFLR, and disable PWM group
+ * | | |channel 2 Interrupt.
+ * |[4] |CAPIF2 |Capture2 Interrupt Indication Flag
+ * | | |If PWM group channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition occurs
+ * | | |at PWM group channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause
+ * | | |CAPIF2 to be set high if PWM group channel 2 falling latch interrupt is enabled (CFL_IE2=1).
+ * | | |This flag is clear by software with a write 1 to itself.
+ * |[6] |CRLRI2 |CRLR2 Latched Indicator Bit
+ * | | |When PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of
+ * | | |PWM down-counter and this bit is set by hardware.
+ * | | |Clear this bit by writing a one to it.
+ * |[7] |CFLRI2 |CFLR2 Latched Indicator Bit
+ * | | |When PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of
+ * | | |PWM down-counter and this bit is set by hardware.
+ * | | |Clear this bit by writing a one to it.
+ * |[16] |INV3 |PWM Group Channel 3 Inverter ON/OFF
+ * | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
+ * | | |0 = Inverter OFF
+ * |[17] |CRL_IE3 |PWM Group Channel 3 Rising Latch Interrupt Enable ON/OFF
+ * | | |1 = Enable rising latch interrupt
+ * | | |0 = Disable rising latch interrupt
+ * | | |When Enable, if Capture detects PWM group channel 3 has rising transition, Capture
+ * | | |issues an Interrupt.
+ * |[18] |CFL_IE3 |PWM Group Channel 3 Falling Latch Interrupt Enable ON/OFF
+ * | | |1 = Enable falling latch interrupt
+ * | | |0 = Disable falling latch interrupt
+ * | | |When Enable, if Capture detects PWM group channel 3 has falling transition, Capture
+ * | | |issues an Interrupt.
+ * |[19] |CAPCH3EN |Capture Channel 3 transition Enable/Disable
+ * | | |1 = Enable capture function on PWM group channel 3.
+ * | | |0 = Disable capture function on PWM group channel 3
+ * | | |When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising
+ * | | |latch) and CFLR (Falling latch).
+ * | | |When Disable, Capture does not update CRLR and CFLR, and disable PWM group
+ * | | |channel 3 Interrupt.
+ * |[20] |CAPIF3 |Capture3 Interrupt Indication Flag
+ * | | |If PWM group channel 3 rising latch interrupt is enabled (CRL_IE3=1), a rising transition occurs
+ * | | |at PWM group channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause
+ * | | |CAPIF3 to be set high if PWM group channel 3 falling latch interrupt is enabled (CFL_IE3=1).
+ * | | |This flag is clear by software with a write 1 to itself.
+ * |[22] |CRLRI3 |CRLR3 Latched Indicator Bit
+ * | | |When PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of
+ * | | |PWM down-counter and this bit is set by hardware.
+ * | | |Clear this bit by writing a one to it.
+ * |[23] |CFLRI3 |CFLR3 Latched Indicator Bit
+ * | | |When PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of
+ * | | |PWM down-counter and this bit is set by hardware.
+ * | | |Clear this bit by writing a one to it.
+ */
+ __IO uint32_t CCR2;
+
+ /**
+ * CRLR0
+ * ===================================================================================================
+ * Offset: 0x58 Capture 0 Rising Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRLR |Capture Rising Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
+ */
+ __IO uint32_t CRLR0;
+
+ /**
+ * CFLR0
+ * ===================================================================================================
+ * Offset: 0x5C Capture 0 Falling Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CFLR |Capture Falling Latch Register
+ * | | |Latch the PWM counter when Channel 01/2/3 has Falling transition.
+ */
+ __IO uint32_t CFLR0;
+
+ /**
+ * CRLR1
+ * ===================================================================================================
+ * Offset: 0x60 Capture 1 Rising Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRLR |Capture Rising Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
+ */
+ __IO uint32_t CRLR1;
+
+ /**
+ * CFLR1
+ * ===================================================================================================
+ * Offset: 0x64 Capture 1 Falling Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CFLR |Capture Falling Latch Register
+ * | | |Latch the PWM counter when Channel 01/2/3 has Falling transition.
+ */
+ __IO uint32_t CFLR1;
+
+ /**
+ * CRLR2
+ * ===================================================================================================
+ * Offset: 0x68 Capture 2 Rising Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRLR |Capture Rising Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
+ */
+ __IO uint32_t CRLR2;
+
+ /**
+ * CFLR2
+ * ===================================================================================================
+ * Offset: 0x6C Capture 2 Falling Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CFLR |Capture Falling Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
+ */
+ __IO uint32_t CFLR2;
+
+ /**
+ * CRLR3
+ * ===================================================================================================
+ * Offset: 0x70 Capture 3 Rising Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRLR |Capture Rising Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
+ */
+ __IO uint32_t CRLR3;
+
+ /**
+ * CFLR3
+ * ===================================================================================================
+ * Offset: 0x74 Capture 3 Falling Latch Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CFLR |Capture Falling Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
+ */
+ __IO uint32_t CFLR3;
+
+ /**
+ * CAPENR
+ * ===================================================================================================
+ * Offset: 0x78 Capture Input Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CAPENR |Capture Input Enable Register
+ * | | |There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or
+ * | | |OFF.
+ * | | |0 = OFF (PWMx multi-function pin input does not affect input capture function.)
+ * | | |1 = (PWMx multi-function pin input will affect its input capture function.)
+ * | | |CAPENR
+ * | | |Bit 3210 for PWM group A
+ * | | |Bit xxx1 -> Capture channel 0 is from P2 [0]
+ * | | |Bit xx1x -> Capture channel 1 is from P2 [1]
+ * | | |Bit x1xx -> Capture channel 2 is from P2 [2]
+ * | | |Bit 1xxx -> Capture channel 3 is from P2 [3]
+ * | | |Bit 3210 for PWM group B
+ * | | |Bit xxx1 -> Capture channel 0 is from P2 [4]
+ * | | |Bit xx1x -> Capture channel 1 is from P2 [5]
+ * | | |Bit x1xx -> Capture channel 2 is from P2 [6]
+ * | | |Bit 1xxx -> Capture channel 3 is from P2 [7]
+ */
+ __IO uint32_t CAPENR;
+
+ /**
+ * POE
+ * ===================================================================================================
+ * Offset: 0x7C PWM Output Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWM0 |PWM Channel 0 Output Enable Register
+ * | | |1 = Enable PWM channel 0 output to pin.
+ * | | |0 = Disable PWM channel 0 output to pin.
+ * | | |Note: The corresponding GPIO pin also must be switched to PWM function.
+ * |[1] |PWM1 |PWM Channel 1 Output Enable Register
+ * | | |1 = Enable PWM channel 1 output to pin.
+ * | | |0 = Disable PWM channel 1 output to pin.
+ * | | |Note: The corresponding GPIO pin also must be switched to PWM function.
+ * |[2] |PWM2 |PWM Channel 2 Output Enable Register
+ * | | |1 = Enable PWM channel 2 output to pin.
+ * | | |0 = Disable PWM channel 2 output to pin.
+ * | | |Note: The corresponding GPIO pin also must be switched to PWM function.
+ * |[3] |PWM3 |PWM Channel 3 Output Enable Register
+ * | | |1 = Enable PWM channel 3 output to pin.
+ * | | |0 = Disable PWM channel 3 output to pin.
+ * | | |Note: The corresponding GPIO pin also must be switched to PWM function.
+ */
+ __IO uint32_t POE;
+
+ /**
+ * TCON
+ * ===================================================================================================
+ * Offset: 0x80 PWM Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWM0PTEN |Channel 0 PWM Period Trigger ADC Enable Register
+ * | | |1 = Enable PWM channel 0 trigger ADC function
+ * | | |0 = Disable PWM channel 0 trigger ADC function
+ * | | |As PWM operating at edge-aligned mode, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.
+ * | | |As PWM operating at center-aligned mode, enable this bit can make PWM trigger ADC to start conversion
+ * | | |when PWM counter up count to (CNR+1) or down count to underflow based on INT01PTYPE setting.
+ * | | |1 = Enable PWM channel 0 output to pin.
+ * | | |0 = Disable PWM channel 0 output to pin.
+ * | | |Note: The corresponding GPIO pin also must be switched to PWM function.
+ * |[1] |PWM1PTEN |Channel 1 PWM Period Trigger ADC Enable Register
+ * | | |1 = Enable PWM channel 1 trigger ADC function
+ * | | |0 = Disable PWM channel 1 trigger ADC function
+ * | | |As PWM operating at edge-aligned mode, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.
+ * | | |As PWM operating at center-aligned mode, enable this bit can make PWM trigger ADC to start conversion
+ * | | |when PWM counter up count to (CNR+1) or down count to underflow based on INT01PTYPE setting.
+ * |[2] |PWM2PTEN |Channel 2 PWM Period Trigger ADC Enable Register
+ * | | |1 = Enable PWM channel 2 trigger ADC function
+ * | | |0 = Disable PWM channel 2 trigger ADC function
+ * | | |As PWM operating at edge-aligned mode, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.
+ * | | |As PWM operating at center-aligned mode, enable this bit can make PWM trigger ADC to start conversion
+ * | | |when PWM counter up count to (CNR+1) or down count to underflow based on INT23PTYPE setting.
+ * |[3] |PWM3PTEN |Channel 3 PWM Period Trigger ADC Enable Register
+ * | | |1 = Enable PWM channel 3 trigger ADC function
+ * | | |0 = Disable PWM channel 3 trigger ADC function
+ * | | |As PWM operating at edge-aligned mode, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.
+ * | | |As PWM operating at center-aligned mode, enable this bit can make PWM trigger ADC to start conversion
+ * | | |when PWM counter up count to (CNR+1) or down count to underflow based on INT23PTYPE setting.
+ * |[8] |PWM0DTEN |Channel 0 PWM Duty Trigger ADC Enable Register
+ * | | |1 = Enable PWM channel 0 trigger ADC function
+ * | | |0 = Disable PWM channel 0 trigger ADC function
+ * | | |As PWM operating at edge-aligned mode, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.
+ * | | |As PWM operating at center-aligned mode, enable this bit can make PWM trigger ADC to start conversion
+ * | | |when PWM counter up count or down count to match CMR based on INT01DTYPE setting.
+ * |[9] |PWM1DTEN |Channel 1 PWM Duty Trigger ADC Enable Register
+ * | | |1 = Enable PWM channel 1 trigger ADC function
+ * | | |0 = Disable PWM channel 1 trigger ADC function
+ * | | |As PWM operating at edge-aligned mode, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.
+ * | | |As PWM operating at center-aligned mode, enable this bit can make PWM trigger ADC to start conversion
+ * | | |when PWM counter up count or down count to match CMR based on INT01DTYPE setting.
+ * |[10] |PWM2DTEN |Channel 2 PWM Duty Trigger ADC Enable Register
+ * | | |1 = Enable PWM channel 2 trigger ADC function
+ * | | |0 = Disable PWM channel 2 trigger ADC function
+ * | | |As PWM operating at edge-aligned mode, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.
+ * | | |As PWM operating at center-aligned mode, enable this bit can make PWM trigger ADC to start conversion
+ * | | |when PWM counter up count or down count to match CMR based on INT23DTYPE setting.
+ * |[11] |PWM3DTEN |Channel 3 PWM Duty Trigger ADC Enable Register
+ * | | |1 = Enable PWM channel 3 trigger ADC function
+ * | | |0 = Disable PWM channel 3 trigger ADC function
+ * | | |As PWM operating at edge-aligned mode, enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.
+ * | | |As PWM operating at center-aligned mode, enable this bit can make PWM trigger ADC to start conversion
+ * | | |when PWM counter up count or down count to match CMR based on INT23DTYPE setting.
+ */
+ __IO uint32_t TCON;
+
+ /**
+ * TSTATUS
+ * ===================================================================================================
+ * Offset: 0x84 PWM Trigger Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWM0TF |PWM Channel 0 Trigger ADC Flag
+ * | | |This bit is set to 1 by hardware when PWM0 trigger ADC condition matched. As this bit is set to 1,
+ * | | |ADC will start conversion if ADC triggered source is selected by PWM.
+ * | | |Software can write 1 to clear this bit.
+ * |[1] |PWM1TF |PWM Channel 1 Trigger ADC Flag
+ * | | |This bit is set to 1 by hardware when PWM1 trigger ADC condition matched. As this bit is set to 1,
+ * | | |ADC will start conversion if ADC triggered source is selected by PWM.
+ * | | |Software can write 1 to clear this bit.
+ * |[2] |PWM2TF |PWM Channel 2 Trigger ADC Flag
+ * | | |This bit is set to 1 by hardware when PWM2 trigger ADC condition matched. As this bit is set to 1,
+ * | | |ADC will start conversion if ADC triggered source is selected by PWM.
+ * | | |Software can write 1 to clear this bit.
+ * |[3] |PWM3TF |PWM Channel 3 Trigger ADC Flag
+ * | | |This bit is set to 1 by hardware when PWM3 trigger ADC condition matched. As this bit is set to 1,
+ * | | |ADC will start conversion if ADC triggered source is selected by PWM.
+ * | | |Software can write 1 to clear this bit.
+ */
+ __IO uint32_t TSTATUS;
+
+ /**
+ * RESERVE2
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE2[4];
+
+ /**
+ * PSCR
+ * ===================================================================================================
+ * Offset: 0x98 PWM Synchronous Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8] |PSSEN1 |PWM1 Synchronous Start Enable
+ * | | |1 = PWM1 synchronous start enable.
+ * | | |0 = PWM1 synchronous start disable.
+ * | | |If this bit is set to 1, PWM-Timer1 will synchronous start with PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
+ * |[16] |PSSEN2 |PWM2 Synchronous Start Enable
+ * | | |1 = PWM2 synchronous start enable.
+ * | | |0 = PWM2 synchronous start disable.
+ * | | |If this bit is set to 1, PWM-Timer2 will synchronous start with PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
+ * |[24] |PSSEN3 |PWM3 Synchronous Start Enable
+ * | | |1 = PWM3 synchronous start enable.
+ * | | |0 = PWM3 synchronous start disable.
+ * | | |If this bit is set to 1, PWM-Timer3 will synchronous start with PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A.
+ */
+ __IO uint32_t PSCR;
+
+} PWM_T;
+
+/** @addtogroup PWM_CONST PWM Bit Field Definition
+ Constant Definitions for PWM Controller
+ @{
+ */
+
+/* PWM PPR Bit Field Definitions */
+#define PWM_PPR_DZI23_Pos 24 /*!< PWM PPR: DZI23 Position */
+#define PWM_PPR_DZI23_Msk (0xFFul << PWM_PPR_DZI23_Pos) /*!< PWM PPR: DZI23 Mask */
+
+#define PWM_PPR_DZI01_Pos 16 /*!< PWM PPR: DZI01 Position */
+#define PWM_PPR_DZI01_Msk (0xFFul << PWM_PPR_DZI01_Pos) /*!< PWM PPR: DZI01 Mask */
+
+#define PWM_PPR_CP23_Pos 8 /*!< PWM PPR: CP23 Position */
+#define PWM_PPR_CP23_Msk (0xFFul << PWM_PPR_CP23_Pos) /*!< PWM PPR: CP23 Mask */
+
+#define PWM_PPR_CP01_Pos 0 /*!< PWM PPR: CP01 Position */
+#define PWM_PPR_CP01_Msk (0xFFul << PWM_PPR_CP01_Pos) /*!< PWM PPR: CP01 Mask */
+
+/* PWM CSR Bit Field Definitions */
+#define PWM_CSR_CSR3_Pos 12 /*!< PWM CSR: CSR3 Position */
+#define PWM_CSR_CSR3_Msk (7ul << PWM_CSR_CSR3_Pos) /*!< PWM CSR: CSR3 Mask */
+
+#define PWM_CSR_CSR2_Pos 8 /*!< PWM CSR: CSR2 Position */
+#define PWM_CSR_CSR2_Msk (7ul << PWM_CSR_CSR2_Pos) /*!< PWM CSR: CSR2 Mask */
+
+#define PWM_CSR_CSR1_Pos 4 /*!< PWM CSR: CSR1 Position */
+#define PWM_CSR_CSR1_Msk (7ul << PWM_CSR_CSR1_Pos) /*!< PWM CSR: CSR1 Mask */
+
+#define PWM_CSR_CSR0_Pos 0 /*!< PWM CSR: CSR0 Position */
+#define PWM_CSR_CSR0_Msk (7ul << PWM_CSR_CSR0_Pos) /*!< PWM CSR: CSR0 Mask */
+
+/* PWM PCR Bit Field Definitions */
+#define PWM_PCR_PWM23TYPE_Pos 31 /*!< PWM PCR: PWM23TYPE Position */
+#define PWM_PCR_PWM23TYPE_Msk (1ul << PWM_PCR_PWM23TYPE_Pos) /*!< PWM PCR: PWM23TYPE Mask */
+
+#define PWM_PCR_PWM01TYPE_Pos 30 /*!< PWM PCR: PWM01TYPE Position */
+#define PWM_PCR_PWM01TYPE_Msk (1ul << PWM_PCR_PWM01TYPE_Pos) /*!< PWM PCR: PWM01TYPE Mask */
+
+#define PWM_PCR_CH3MOD_Pos 27 /*!< PWM PCR: CH3MOD Position */
+#define PWM_PCR_CH3MOD_Msk (1ul << PWM_PCR_CH3MOD_Pos) /*!< PWM PCR: CH3MOD Mask */
+
+#define PWM_PCR_CH3INV_Pos 26 /*!< PWM PCR: CH3INV Position */
+#define PWM_PCR_CH3INV_Msk (1ul << PWM_PCR_CH3INV_Pos) /*!< PWM PCR: CH3INV Mask */
+
+#define PWM_PCR_CH3PINV_Pos 25 /*!< PWM PCR: CH3PINV Position */
+#define PWM_PCR_CH3PINV_Msk (1ul << PWM_PCR_CH3PINV_Pos) /*!< PWM PCR: CH3PINV Mask */
+
+#define PWM_PCR_CH3EN_Pos 24 /*!< PWM PCR: CH3EN Position */
+#define PWM_PCR_CH3EN_Msk (1ul << PWM_PCR_CH3EN_Pos) /*!< PWM PCR: CH3EN Mask */
+
+#define PWM_PCR_CH2MOD_Pos 19 /*!< PWM PCR: CH2MOD Position */
+#define PWM_PCR_CH2MOD_Msk (1ul << PWM_PCR_CH2MOD_Pos) /*!< PWM PCR: CH2MOD Mask */
+
+#define PWM_PCR_CH2INV_Pos 18 /*!< PWM PCR: CH2INV Position */
+#define PWM_PCR_CH2INV_Msk (1ul << PWM_PCR_CH2INV_Pos) /*!< PWM PCR: CH2INV Mask */
+
+#define PWM_PCR_CH2PINV_Pos 17 /*!< PWM PCR: CH2PINV Position */
+#define PWM_PCR_CH2PINV_Msk (1ul << PWM_PCR_CH2PINV_Pos) /*!< PWM PCR: CH2PINV Mask */
+
+#define PWM_PCR_CH2EN_Pos 16 /*!< PWM PCR: CH2EN Position */
+#define PWM_PCR_CH2EN_Msk (1ul << PWM_PCR_CH2EN_Pos) /*!< PWM PCR: CH2EN Mask */
+
+#define PWM_PCR_CH1MOD_Pos 11 /*!< PWM PCR: CH1MOD Position */
+#define PWM_PCR_CH1MOD_Msk (1ul << PWM_PCR_CH1MOD_Pos) /*!< PWM PCR: CH1MOD Mask */
+
+#define PWM_PCR_CH1INV_Pos 10 /*!< PWM PCR: CH1INV Position */
+#define PWM_PCR_CH1INV_Msk (1ul << PWM_PCR_CH1INV_Pos) /*!< PWM PCR: CH1INV Mask */
+
+#define PWM_PCR_CH1PINV_Pos 9 /*!< PWM PCR: CH1PINV Position */
+#define PWM_PCR_CH1PINV_Msk (1ul << PWM_PCR_CH1PINV_Pos) /*!< PWM PCR: CH1PINV Mask */
+
+#define PWM_PCR_CH1EN_Pos 8 /*!< PWM PCR: CH1EN Position */
+#define PWM_PCR_CH1EN_Msk (1ul << PWM_PCR_CH1EN_Pos) /*!< PWM PCR: CH1EN Mask */
+
+#define PWM_PCR_DZEN23_Pos 5 /*!< PWM PCR: DZEN23 Position */
+#define PWM_PCR_DZEN23_Msk (1ul << PWM_PCR_DZEN23_Pos) /*!< PWM PCR: DZEN23 Mask */
+
+#define PWM_PCR_DZEN01_Pos 4 /*!< PWM PCR: DZEN01 Position */
+#define PWM_PCR_DZEN01_Msk (1ul << PWM_PCR_DZEN01_Pos) /*!< PWM PCR: DZEN01 Mask */
+
+#define PWM_PCR_CH0MOD_Pos 3 /*!< PWM PCR: CH0MOD Position */
+#define PWM_PCR_CH0MOD_Msk (1ul << PWM_PCR_CH0MOD_Pos) /*!< PWM PCR: CH0MOD Mask */
+
+#define PWM_PCR_CH0INV_Pos 2 /*!< PWM PCR: CH0INV Position */
+#define PWM_PCR_CH0INV_Msk (1ul << PWM_PCR_CH0INV_Pos) /*!< PWM PCR: CH0INV Mask */
+
+#define PWM_PCR_CH0PINV_Pos 1 /*!< PWM PCR: CH0PINV Position */
+#define PWM_PCR_CH0PINV_Msk (1ul << PWM_PCR_CH0PINV_Pos) /*!< PWM PCR: CH0PINV Mask */
+
+#define PWM_PCR_CH0EN_Pos 0 /*!< PWM PCR: CH0EN Position */
+#define PWM_PCR_CH0EN_Msk (1ul << PWM_PCR_CH0EN_Pos) /*!< PWM PCR: CH0EN Mask */
+
+/* PWM CNR Bit Field Definitions */
+#define PWM_CNR_CNR_Pos 0 /*!< PWM CNR: CNR Position */
+#define PWM_CNR_CNR_Msk (0xFFFFul << PWM_CNR_CNR_Pos) /*!< PWM CNR: CNR Mask */
+
+/* PWM CMR Bit Field Definitions */
+#define PWM_CMR_CMR_Pos 0 /*!< PWM CMR: CMR Position */
+#define PWM_CMR_CMR_Msk (0xFFFFul << PWM_CMR_CMR_Pos) /*!< PWM CMR: CMR Mask */
+
+/* PWM PDR Bit Field Definitions */
+#define PWM_PDR_PDR_Pos 0 /*!< PWM PDR: PDR Position */
+#define PWM_PDR_PDR_Msk (0xFFFFul << PWM_PDR_PDR_Pos) /*!< PWM PDR: PDR Mask */
+
+
+/* PWM PIER Bit Field Definitions */
+#define PWM_PIER_INT23DTYPE_Pos 25 /*!< PWM PIER: INT23DTYPE Position */
+#define PWM_PIER_INT23DTYPE_Msk (1ul << PWM_PIER_INT23DTYPE_Pos) /*!< PWM PIER: INT23DTYPE Mask */
+
+#define PWM_PIER_INT01DTYPE_Pos 24 /*!< PWM PIER: INT01DTYPE Position */
+#define PWM_PIER_INT01DTYPE_Msk (1ul << PWM_PIER_INT01DTYPE_Pos) /*!< PWM PIER: INT01DTYPE Mask */
+
+#define PWM_PIER_INT23TYPE_Pos 17 /*!< PWM PIER: INT23TYPE Position */
+#define PWM_PIER_INT23TYPE_Msk (1ul << PWM_PIER_INT23TYPE_Pos) /*!< PWM PIER: INT23TYPE Mask */
+
+#define PWM_PIER_INT01TYPE_Pos 16 /*!< PWM PIER: INT01TYPE Position */
+#define PWM_PIER_INT01TYPE_Msk (1ul << PWM_PIER_INT01TYPE_Pos) /*!< PWM PIER: INT01TYPE Mask */
+
+#define PWM_PIER_PWMDIE3_Pos 11 /*!< PWM PIER: PWMDIE3 Position */
+#define PWM_PIER_PWMDIE3_Msk (1ul << PWM_PIER_PWMDIE3_Pos) /*!< PWM PIER: PWMDIE3 Mask */
+
+#define PWM_PIER_PWMDIE2_Pos 10 /*!< PWM PIER: PWMDIE2 Position */
+#define PWM_PIER_PWMDIE2_Msk (1ul << PWM_PIER_PWMDIE2_Pos) /*!< PWM PIER: PWMDIE2 Mask */
+
+#define PWM_PIER_PWMDIE1_Pos 9 /*!< PWM PIER: PWMDIE1 Position */
+#define PWM_PIER_PWMDIE1_Msk (1ul << PWM_PIER_PWMDIE1_Pos) /*!< PWM PIER: PWMDIE1 Mask */
+
+#define PWM_PIER_PWMDIE0_Pos 8 /*!< PWM PIER: PWMDIE0 Position */
+#define PWM_PIER_PWMDIE0_Msk (1ul << PWM_PIER_PWMDIE0_Pos) /*!< PWM PIER: PWMDIE0 Mask */
+
+#define PWM_PIER_PWMIE3_Pos 3 /*!< PWM PIER: PWMIE3 Position */
+#define PWM_PIER_PWMIE3_Msk (1ul << PWM_PIER_PWMIE3_Pos) /*!< PWM PIER: PWMIE3 Mask */
+
+#define PWM_PIER_PWMIE2_Pos 2 /*!< PWM PIER: PWMIE2 Position */
+#define PWM_PIER_PWMIE2_Msk (1ul << PWM_PIER_PWMIE2_Pos) /*!< PWM PIER: PWMIE2 Mask */
+
+#define PWM_PIER_PWMIE1_Pos 1 /*!< PWM PIER: PWMIE1 Position */
+#define PWM_PIER_PWMIE1_Msk (1ul << PWM_PIER_PWMIE1_Pos) /*!< PWM PIER: PWMIE1 Mask */
+
+#define PWM_PIER_PWMIE0_Pos 0 /*!< PWM PIER: PWMIE0 Position */
+#define PWM_PIER_PWMIE0_Msk (1ul << PWM_PIER_PWMIE0_Pos) /*!< PWM PIER: PWMIE0 Mask */
+
+/* PWM PIIR Bit Field Definitions */
+#define PWM_PIIR_PWMDIF3_Pos 11 /*!< PWM PIIR: PWMDIF3 Position */
+#define PWM_PIIR_PWMDIF3_Msk (1ul << PWM_PIIR_PWMDIF3_Pos) /*!< PWM PIIR: PWMDIF3 Mask */
+
+#define PWM_PIIR_PWMDIF2_Pos 10 /*!< PWM PIIR: PWMDIF2 Position */
+#define PWM_PIIR_PWMDIF2_Msk (1ul << PWM_PIIR_PWMDIF2_Pos) /*!< PWM PIIR: PWMDIF2 Mask */
+
+#define PWM_PIIR_PWMDIF1_Pos 9 /*!< PWM PIIR: PWMDIF1 Position */
+#define PWM_PIIR_PWMDIF1_Msk (1ul << PWM_PIIR_PWMDIF1_Pos) /*!< PWM PIIR: PWMDIF1 Mask */
+
+#define PWM_PIIR_PWMDIF0_Pos 8 /*!< PWM PIIR: PWMDIF0 Position */
+#define PWM_PIIR_PWMDIF0_Msk (1ul << PWM_PIIR_PWMDIF0_Pos) /*!< PWM PIIR: PWMDIF0 Mask */
+
+#define PWM_PIIR_PWMIF3_Pos 3 /*!< PWM PIIR: PWMIF3 Position */
+#define PWM_PIIR_PWMIF3_Msk (1ul << PWM_PIIR_PWMIF3_Pos) /*!< PWM PIIR: PWMIF3 Mask */
+
+#define PWM_PIIR_PWMIF2_Pos 2 /*!< PWM PIIR: PWMIF2 Position */
+#define PWM_PIIR_PWMIF2_Msk (1ul << PWM_PIIR_PWMIF2_Pos) /*!< PWM PIIR: PWMIF2 Mask */
+
+#define PWM_PIIR_PWMIF1_Pos 1 /*!< PWM PIIR: PWMIF1 Position */
+#define PWM_PIIR_PWMIF1_Msk (1ul << PWM_PIIR_PWMIF1_Pos) /*!< PWM PIIR: PWMIF1 Mask */
+
+#define PWM_PIIR_PWMIF0_Pos 0 /*!< PWM PIIR: PWMIF0 Position */
+#define PWM_PIIR_PWMIF0_Msk (1ul << PWM_PIIR_PWMIF0_Pos) /*!< PWM PIIR: PWMIF0 Mask */
+
+/* PWM CCR0 Bit Field Definitions */
+#define PWM_CCR0_CFLRI1_Pos 23 /*!< PWM CCR0: CFLRI1 Position */
+#define PWM_CCR0_CFLRI1_Msk (1ul << PWM_CCR0_CFLRI1_Pos) /*!< PWM CCR0: CFLRI1 Mask */
+
+#define PWM_CCR0_CRLRI1_Pos 22 /*!< PWM CCR0: CRLRI1 Position */
+#define PWM_CCR0_CRLRI1_Msk (1ul << PWM_CCR0_CRLRI1_Pos) /*!< PWM CCR0: CRLRI1 Mask */
+
+#define PWM_CCR0_CAPIF1_Pos 20 /*!< PWM CCR0: CAPIF1 Position */
+#define PWM_CCR0_CAPIF1_Msk (1ul << PWM_CCR0_CAPIF1_Pos) /*!< PWM CCR0: CAPIF1 Mask */
+
+#define PWM_CCR0_CAPCH1EN_Pos 19 /*!< PWM CCR0: CAPCH1EN Position */
+#define PWM_CCR0_CAPCH1EN_Msk (1ul << PWM_CCR0_CAPCH1EN_Pos) /*!< PWM CCR0: CAPCH1EN Mask */
+
+#define PWM_CCR0_CFL_IE1_Pos 18 /*!< PWM CCR0: CFL_IE1 Position */
+#define PWM_CCR0_CFL_IE1_Msk (1ul << PWM_CCR0_CFL_IE1_Pos) /*!< PWM CCR0: CFL_IE1 Mask */
+
+#define PWM_CCR0_CRL_IE1_Pos 17 /*!< PWM CCR0: CRL_IE1 Position */
+#define PWM_CCR0_CRL_IE1_Msk (1ul << PWM_CCR0_CRL_IE1_Pos) /*!< PWM CCR0: CRL_IE1 Mask */
+
+#define PWM_CCR0_INV1_Pos 16 /*!< PWM CCR0: INV1 Position */
+#define PWM_CCR0_INV1_Msk (1ul << PWM_CCR0_INV1_Pos) /*!< PWM CCR0: INV1 Mask */
+
+#define PWM_CCR0_CFLRI0_Pos 7 /*!< PWM CCR0: CFLRI0 Position */
+#define PWM_CCR0_CFLRI0_Msk (1ul << PWM_CCR0_CFLRI0_Pos) /*!< PWM CCR0: CFLRI0 Mask */
+
+#define PWM_CCR0_CRLRI0_Pos 6 /*!< PWM CCR0: CRLRI0 Position */
+#define PWM_CCR0_CRLRI0_Msk (1ul << PWM_CCR0_CRLRI0_Pos) /*!< PWM CCR0: CRLRI0 Mask */
+
+#define PWM_CCR0_CAPIF0_Pos 4 /*!< PWM CCR0: CAPIF0 Position */
+#define PWM_CCR0_CAPIF0_Msk (1ul << PWM_CCR0_CAPIF0_Pos) /*!< PWM CCR0: CAPIF0 Mask */
+
+#define PWM_CCR0_CAPCH0EN_Pos 3 /*!< PWM CCR0: CAPCH0EN Position */
+#define PWM_CCR0_CAPCH0EN_Msk (1ul << PWM_CCR0_CAPCH0EN_Pos) /*!< PWM CCR0: CAPCH0EN Mask */
+
+#define PWM_CCR0_CFL_IE0_Pos 2 /*!< PWM CCR0: CFL_IE0 Position */
+#define PWM_CCR0_CFL_IE0_Msk (1ul << PWM_CCR0_CFL_IE0_Pos) /*!< PWM CCR0: CFL_IE0 Mask */
+
+#define PWM_CCR0_CRL_IE0_Pos 1 /*!< PWM CCR0: CRL_IE0 Position */
+#define PWM_CCR0_CRL_IE0_Msk (1ul << PWM_CCR0_CRL_IE0_Pos) /*!< PWM CCR0: CRL_IE0 Mask */
+
+#define PWM_CCR0_INV0_Pos 0 /*!< PWM CCR0: INV0 Position */
+#define PWM_CCR0_INV0_Msk (1ul << PWM_CCR0_INV0_Pos) /*!< PWM CCR0: INV0 Mask */
+
+/* PWM CCR2 Bit Field Definitions */
+#define PWM_CCR2_CFLRI3_Pos 23 /*!< PWM CCR2: CFLRI3 Position */
+#define PWM_CCR2_CFLRI3_Msk (1ul << PWM_CCR2_CFLRI3_Pos) /*!< PWM CCR2: CFLRI3 Mask */
+
+#define PWM_CCR2_CRLRI3_Pos 22 /*!< PWM CCR2: CRLRI3 Position */
+#define PWM_CCR2_CRLRI3_Msk (1ul << PWM_CCR2_CRLRI3_Pos) /*!< PWM CCR2: CRLRI3 Mask */
+
+#define PWM_CCR2_CAPIF3_Pos 20 /*!< PWM CCR2: CAPIF3 Position */
+#define PWM_CCR2_CAPIF3_Msk (1ul << PWM_CCR2_CAPIF3_Pos) /*!< PWM CCR2: CAPIF3 Mask */
+
+#define PWM_CCR2_CAPCH3EN_Pos 19 /*!< PWM CCR2: CAPCH3EN Position */
+#define PWM_CCR2_CAPCH3EN_Msk (1ul << PWM_CCR2_CAPCH3EN_Pos) /*!< PWM CCR2: CAPCH3EN Mask */
+
+#define PWM_CCR2_CFL_IE3_Pos 18 /*!< PWM CCR2: CFL_IE3 Position */
+#define PWM_CCR2_CFL_IE3_Msk (1ul << PWM_CCR2_CFL_IE3_Pos) /*!< PWM CCR2: CFL_IE3 Mask */
+
+#define PWM_CCR2_CRL_IE3_Pos 17 /*!< PWM CCR2: CRL_IE3 Position */
+#define PWM_CCR2_CRL_IE3_Msk (1ul << PWM_CCR2_CRL_IE3_Pos) /*!< PWM CCR2: CRL_IE3 Mask */
+
+#define PWM_CCR2_INV3_Pos 16 /*!< PWM CCR2: INV3 Position */
+#define PWM_CCR2_INV3_Msk (1ul << PWM_CCR2_INV3_Pos) /*!< PWM CCR2: INV3 Mask */
+
+#define PWM_CCR2_CFLRI2_Pos 7 /*!< PWM CCR2: CFLRI2 Position */
+#define PWM_CCR2_CFLRI2_Msk (1ul << PWM_CCR2_CFLRI2_Pos) /*!< PWM CCR2: CFLRI2 Mask */
+
+#define PWM_CCR2_CRLRI2_Pos 6 /*!< PWM CCR2: CRLRI2 Position */
+#define PWM_CCR2_CRLRI2_Msk (1ul << PWM_CCR2_CRLRI2_Pos) /*!< PWM CCR2: CRLRI2 Mask */
+
+#define PWM_CCR2_CAPIF2_Pos 4 /*!< PWM CCR2: CAPIF2 Position */
+#define PWM_CCR2_CAPIF2_Msk (1ul << PWM_CCR2_CAPIF2_Pos) /*!< PWM CCR2: CAPIF2 Mask */
+
+#define PWM_CCR2_CAPCH2EN_Pos 3 /*!< PWM CCR2: CAPCH2EN Position */
+#define PWM_CCR2_CAPCH2EN_Msk (1ul << PWM_CCR2_CAPCH2EN_Pos) /*!< PWM CCR2: CAPCH2EN Mask */
+
+#define PWM_CCR2_CFL_IE2_Pos 2 /*!< PWM CCR2: CFL_IE2 Position */
+#define PWM_CCR2_CFL_IE2_Msk (1ul << PWM_CCR2_CFL_IE2_Pos) /*!< PWM CCR2: CFL_IE2 Mask */
+
+#define PWM_CCR2_CRL_IE2_Pos 1 /*!< PWM CCR2: CRL_IE2 Position */
+#define PWM_CCR2_CRL_IE2_Msk (1ul << PWM_CCR2_CRL_IE2_Pos) /*!< PWM CCR2: CRL_IE2 Mask */
+
+#define PWM_CCR2_INV2_Pos 0 /*!< PWM CCR2: INV2 Position */
+#define PWM_CCR2_INV2_Msk (1ul << PWM_CCR2_INV2_Pos) /*!< PWM CCR2: INV2 Mask */
+
+/* PWM CRLR Bit Field Definitions */
+#define PWM_CRLR_CRLR_Pos 0 /*!< PWM CRLR: CRLR Position */
+#define PWM_CRLR_CRLR_Msk (0xFFFFul << PWM_CRLR_CRLR_Pos) /*!< PWM CRLR: CRLR Mask */
+
+/* PWM CFLR Bit Field Definitions */
+#define PWM_CFLR_CFLR_Pos 0 /*!< PWM CFLR: CFLR Position */
+#define PWM_CFLR_CFLR_Msk (0xFFFFul << PWM_CFLR_CFLR_Pos) /*!< PWM CFLR: CFLR Mask */
+
+/* PWM CAPENR Bit Field Definitions */
+#define PWM_CAPENR_CINEN3_Pos 3 /*!< PWM CAPENR: CINEN3 Position */
+#define PWM_CAPENR_CINEN3_Msk (1ul << PWM_CAPENR_CINEN3_Pos) /*!< PWM CAPENR: CINEN3 Mask */
+
+#define PWM_CAPENR_CINEN2_Pos 2 /*!< PWM CAPENR: CINEN2 Position */
+#define PWM_CAPENR_CINEN2_Msk (1ul << PWM_CAPENR_CINEN2_Pos) /*!< PWM CAPENR: CINEN2 Mask */
+
+#define PWM_CAPENR_CINEN1_Pos 1 /*!< PWM CAPENR: CINEN1 Position */
+#define PWM_CAPENR_CINEN1_Msk (1ul << PWM_CAPENR_CINEN1_Pos) /*!< PWM CAPENR: CINEN1 Mask */
+
+#define PWM_CAPENR_CINEN0_Pos 0 /*!< PWM CAPENR: CINEN0 Position */
+#define PWM_CAPENR_CINEN0_Msk (1ul << PWM_CAPENR_CINEN0_Pos) /*!< PWM CAPENR: CINEN0 Mask */
+
+/* PWM POE Bit Field Definitions */
+#define PWM_POE_PWM3_Pos 3 /*!< PWM POE: POE3 Position */
+#define PWM_POE_PWM3_Msk (1ul << PWM_POE_PWM3_Pos) /*!< PWM POE: POE3 Mask */
+
+#define PWM_POE_PWM2_Pos 2 /*!< PWM POE: POE2 Position */
+#define PWM_POE_PWM2_Msk (1ul << PWM_POE_PWM2_Pos) /*!< PWM POE: POE2 Mask */
+
+#define PWM_POE_PWM1_Pos 1 /*!< PWM POE: POE1 Position */
+#define PWM_POE_PWM1_Msk (1ul << PWM_POE_PWM1_Pos) /*!< PWM POE: POE1 Mask */
+
+#define PWM_POE_PWM0_Pos 0 /*!< PWM POE: POE0 Position */
+#define PWM_POE_PWM0_Msk (1ul << PWM_POE_PWM0_Pos) /*!< PWM POE: POE0 Mask */
+
+/* PWM TCON Bit Field Definitions */
+#define PWM_TCON_PWM3DTEN_Pos 11 /*!< PWM TCON: PWM3DTEN Position */
+#define PWM_TCON_PWM3DTEN_Msk (1ul << PWM_TCON_PWM3DTEN_Pos) /*!< PWM TCON: PWM3DTEN Mask */
+
+#define PWM_TCON_PWM2DTEN_Pos 10 /*!< PWM TCON: PWM2DTEN Position */
+#define PWM_TCON_PWM2DTEN_Msk (1ul << PWM_TCON_PWM2DTEN_Pos) /*!< PWM TCON: PWM2DTEN Mask */
+
+#define PWM_TCON_PWM1DTEN_Pos 9 /*!< PWM TCON: PWM1DTEN Position */
+#define PWM_TCON_PWM1DTEN_Msk (1ul << PWM_TCON_PWM1DTEN_Pos) /*!< PWM TCON: PWM1DTEN Mask */
+
+#define PWM_TCON_PWM0DTEN_Pos 8 /*!< PWM TCON: PWM0DTEN Position */
+#define PWM_TCON_PWM0DTEN_Msk (1ul << PWM_TCON_PWM0DTEN_Pos) /*!< PWM TCON: PWM0DTEN Mask */
+
+#define PWM_TCON_PWM3TEN_Pos 3 /*!< PWM TCON: PWM3TEN Position */
+#define PWM_TCON_PWM3TEN_Msk (1ul << PWM_TCON_PWM3TEN_Pos) /*!< PWM TCON: PWM3TEN Mask */
+
+#define PWM_TCON_PWM2TEN_Pos 2 /*!< PWM TCON: PWM2TEN Position */
+#define PWM_TCON_PWM2TEN_Msk (1ul << PWM_TCON_PWM2TEN_Pos) /*!< PWM TCON: PWM2TEN Mask */
+
+#define PWM_TCON_PWM1TEN_Pos 1 /*!< PWM TCON: PWM1TEN Position */
+#define PWM_TCON_PWM1TEN_Msk (1ul << PWM_TCON_PWM1TEN_Pos) /*!< PWM TCON: PWM1TEN Mask */
+
+#define PWM_TCON_PWM0TEN_Pos 0 /*!< PWM TCON: PWM0TEN Position */
+#define PWM_TCON_PWM0TEN_Msk (1ul << PWM_TCON_PWM0TEN_Pos) /*!< PWM TCON: PWM0TEN Mask */
+
+/* PWM TSTATUS Bit Field Definitions */
+#define PWM_TSTATUS_PWM3TF_Pos 3 /*!< PWM TSTATUS: PWM3TF Position */
+#define PWM_TSTATUS_PWM3TF_Msk (1ul << PWM_TSTATUS_PWM3TF_Pos) /*!< PWM TSTATUS: PWM3TF Mask */
+
+#define PWM_TSTATUS_PWM2TF_Pos 2 /*!< PWM TSTATUS: PWM2TF Position */
+#define PWM_TSTATUS_PWM2TF_Msk (1ul << PWM_TSTATUS_PWM2TF_Pos) /*!< PWM TSTATUS: PWM2TF Mask */
+
+#define PWM_TSTATUS_PWM1TF_Pos 1 /*!< PWM TSTATUS: PWM1TF Position */
+#define PWM_TSTATUS_PWM1TF_Msk (1ul << PWM_TSTATUS_PWM1TF_Pos) /*!< PWM TSTATUS: PWM1TF Mask */
+
+#define PWM_TSTATUS_PWM0TF_Pos 0 /*!< PWM TSTATUS: PWM0TF Position */
+#define PWM_TSTATUS_PWM0TF_Msk (1ul << PWM_TSTATUS_PWM0TF_Pos) /*!< PWM TSTATUS: PWM0TF Mask */
+
+/* PWM PSCR Bit Field Definitions */
+#define PWM_PSCR_PSSEN3_Pos 24 /*!< PWM PSCR: PSSEN3 Position */
+#define PWM_PSCR_PSSEN3_Msk (1ul << PWM_PSCR_PSSEN3_Pos) /*!< PWM PSCR: PSSEN3 Mask */
+
+#define PWM_PSCR_PSSEN2_Pos 16 /*!< PWM PSCR: PSSEN2 Position */
+#define PWM_PSCR_PSSEN2_Msk (1ul << PWM_PSCR_PSSEN2_Pos) /*!< PWM PSCR: PSSEN2 Mask */
+
+#define PWM_PSCR_PSSEN1_Pos 8 /*!< PWM PSCR: PSSEN1 Position */
+#define PWM_PSCR_PSSEN1_Msk (1ul << PWM_PSCR_PSSEN1_Pos) /*!< PWM PSCR: PSSEN1 Mask */
+
+#define PWM_PSCR_PSSEN0_Pos 0 /*!< PWM PSCR: PSSEN0 Position */
+#define PWM_PSCR_PSSEN0_Msk (1ul << PWM_PSCR_PSSEN0_Pos) /*!< PWM PSCR: PSSEN0 Mask */
+/**@}*/ /* PWM_CONST */
+/**@}*/ /* PWM */
+
+
+
+
+/*------------------------- SPI Interface Controller -------------------------*/
+/** @addtogroup SPI SPI Controller(SPI)
+ Memory Mapped Structure for SPI Controller
+ @{
+ */
+typedef struct
+{
+ /**
+ * CNTRL
+ * ===================================================================================================
+ * Offset: 0x00 SPI Control and Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GO_BUSY |Go and Busy Status
+ * | | |1 = In master mode, writing 1 to this bit to start the SPI data transfer; in slave
+ * | | |mode, writing 1 to this bit indicates that the slave is ready to communicate with a
+ * | | |master.
+ * | | |0 = Writing 0 to this bit to stop data transfer if SPI is transferring.
+ * | | |During the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will
+ * | | |be cleared automatically.
+ * | | |NOTE: All registers should be set before writing 1 to this GO_BUSY bit. The
+ * | | |transfer result will be unpredictable if software changes related settings when
+ * | | |GO_BUSY bit is 1.
+ * |[1] |RX_NEG |Receive At Negative Edge
+ * | | |1 = The received data input signal is latched at the falling edge of SPICLK.
+ * | | |0 = The received data input signal is latched at the rising edge of SPICLK.
+ * |[2] |TX_NEG |Transmit At Negative Edge
+ * | | |1 = The transmitted data output signal is changed at the falling edge of SPICLK.
+ * | | |0 = The transmitted data output signal is changed at the rising edge of SPICLK.
+ * |[7:3] |TX_BIT_LEN|Transmit Bit Length
+ * | | |This field specifies how many bits are transmitted in one transaction. Up to 32 bits
+ * | | |can be transmitted.
+ * | | |TX_BIT_LEN = 0x01 ... 1 bit
+ * | | |TX_BIT_LEN = 0x02 ... 2 bits
+ * | | |......
+ * | | |TX_BIT_LEN = 0x1f ... 31 bits
+ * | | |TX_BIT_LEN = 0x00 .. 32 bits
+ * |[10] |LSB |LSB First
+ * | | |1 = The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received
+ * | | |from the line will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1).
+ * | | |0 = The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1
+ * | | |register that is depends on the TX_BIT_LEN field).
+ * |[11] |CLKP |Clock Polarity
+ * | | |1 = SPICLK idle high.
+ * | | |0 = SPICLK idle low.
+ * |[15:12] |SP_CYCLE |Suspend Interval (master only)
+ * | | |These four bits provide configurable suspend interval between two successive
+ * | | |transmit/receive transactions in a transfer. The suspend interval is from the last
+ * | | |falling clock edge of the current transaction to the first rising clock edge of the
+ * | | |successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising clock
+ * | | |edge to the falling clock edge. The default value is 0x0. When TX_NUM = 00b,
+ * | | |setting this field has no effect on transfer. The desired suspend interval is obtained
+ * | | |according to the following equation:
+ * | | |(SP_CYCLE[3:0] + 2)*period of SPI clock
+ * | | |SP_CYCLE = 0x0 ... 2 SPICLK clock cycle
+ * | | |SP_CYCLE = 0x1 ... 3 SPICLK clock cycle
+ * | | |......
+ * | | |SP_CYCLE = 0xe ... 16 SPICLK clock cycle
+ * | | |SP_CYCLE = 0xf ... 17 SPICLK clock cycle
+ * |[16] |IF |Interrupt Flag
+ * | | |1 = It indicates that the transfer is done. The interrupt flag is set if it was enable.
+ * | | |0 = It indicates that the transfer does not finish yet.
+ * | | |NOTE: This bit can be cleared by writing 1 to itself.
+ * |[17] |IE |Interrupt Enable
+ * | | |1 = Enable MICROWIRE/SPI Interrupt.
+ * | | |0 = Disable MICROWIRE/SPI Interrupt.
+ * |[18] |SLAVE |SLAVE Mode Indication
+ * | | |1 = Slave mode.
+ * | | |0 = Master mode.
+ * |[19] |REORDER |Reorder Mode Select
+ * | | |0 = Disable byte reorder function.
+ * | | |1 = Enable byte reorder function.
+ * | | |Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24 and 32.
+ */
+ __IO uint32_t CNTRL;
+
+ /**
+ * DIVIDER
+ * ===================================================================================================
+ * Offset: 0x04 SPI Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DIVIDER |Clock Divider Register
+ */
+ __IO uint32_t DIVIDER;
+
+ /**
+ * SSR
+ * ===================================================================================================
+ * Offset: 0x08 SPI Slave Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SSR |Slave Select Register (master only)
+ * | | |If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to active state and
+ * | | |writing 0 sets the line back to inactive state.
+ * | | |If AUTOSS bit is set, writing 1 to this bit will select the SPISSx line to be automatically
+ * | | |driven to active state for the duration of the transmit/receive, and will be driven to
+ * | | |inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in
+ * | | |SS_LVL).
+ * |[2] |SS_LVL |Slave Select Active Level
+ * | | |It defines the active level of slave select signal (SPISSx).
+ * | | |1 = The slave select signal SPISSx is active at high-level/rising-edge.
+ * | | |0 = The slave select signal SPISSx is active at low-level/falling-edge.
+ * |[3] |AUTOSS |Automatic Slave Select (master only)
+ * | | |1 = If this bit is set, SPISSx signal is generated automatically. It means that slave
+ * | | |select signal will be asserted by the SPI controller when transmit/receive is started by
+ * | | |setting GO_BUSY, and is de-asserted after each transmit/receive is finished.
+ * | | |0 = If this bit is cleared, slave select signal will be asserted and de-asserted by setting
+ * | | |and clearing SSR[0].
+ * |[4] |SS_LTRIG |Slave Select Level Trigger (slave only)
+ * | | |1: The slave select signal will be level-trigger. It depends on SS_LVL to decide the
+ * | | |signal is active low or active high.
+ * | | |0: The input slave select signal is edge-trigger. This is default value.
+ * |[5] |LTRIG_FLAG|Level Trigger Flag
+ * | | |When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the
+ * | | |received bit number is met the requirement or not.
+ * | | |1 = The transaction number and the transferred bit length met the specified
+ * | | |requirements which defined in TX_NUM and TX_BIT_LEN.
+ * | | |0 = The transaction number or the transferred bit length of one transaction doesn't
+ * | | |meet the specified requirements.
+ * | | |Note: This bit is READ only
+ */
+ __IO uint32_t SSR;
+
+ /**
+ * RESERVE0
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE0;
+
+ /**
+ * SPI_RX0, SPI_RX1
+ * ===================================================================================================
+ * Offset: 0x10, 0x14 Data Receive Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RX |Data Receive Register
+ * | | |The Data Receive Registers hold the value of received data of the last executed transfer. The
+ * | | |number of valid bits depend on the transmit bit length field in the SPI_CNTRL register. For
+ * | | |example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the
+ * | | |received data.
+ * | | |NOTE: The Data Receive Registers are read only registers.
+ */
+ __I uint32_t RX0;
+
+ /**
+ * RESERVE1
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE1[2];
+
+ /**
+ * RESERVE2
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE2;
+
+ /**
+ * SPI_TX0, SPI_TX1
+ * ===================================================================================================
+ * Offset: 0x20, 0x24 Data Transmit Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TX |Data Transmit Register
+ * | | |The Data Transmit Registers hold the data to be transmitted in the next transfer. The number
+ * | | |of valid bits depend on the transmit bit length field in the CNTRL register.
+ * | | |For example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be
+ * | | |transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the core will
+ * | | |perform two successive 32-bit transmit/receive using the same setting (the order is TX0[31:0],
+ * | | |TX1[31:0]).
+ */
+ __O uint32_t TX0;
+
+ /**
+ * RESERVE3
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE3[2];
+
+ /**
+ * RESERVE4
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE4;
+
+ /**
+ * RESERVE5
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE5;
+
+ /**
+ * RESERVE6
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE6;
+
+ /**
+ * RESERVE7
+ * ===================================================================================================
+ *
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __I uint32_t RESERVE7;
+
+ /**
+ * CNTRL2
+ * ===================================================================================================
+ * Offset: 0x3C SPI Control and Status Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8] |NOSLVSEL |Slave 3-Wire Mode Enable Bit
+ * | | |This is used to ignore the slave select signal in slave mode.
+ * | | |The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.
+ * | | |0 = 4-wire bi-direction interface.
+ * | | |1 = 3-wire bi-direction interface.
+ * | | |Note: In 3-wire mode, the SS_LTRIG, SPI_SSR[4], shall be set as 1.
+ * |[9] |SLV_ABORT |Slave 3-Wire Mode Abort Control Bit
+ * | | |In normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.
+ * | | |If the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode,
+ * | | |the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event.
+ * | | |Note: It will be cleared to 0 automatically by hardware after the software sets this bit to 1.
+ * |[10] |SSTA_INTEN|Slave 3-Wire Mode Start Interrupt Enable
+ * | | |It is used to enable interrupt when the transfer has started in slave 3-wire mode.
+ * | | |If there is no transfer done interrupt over the time period which is defined by user after the transfer start,
+ * | | |the user can set the SLV_ABORT bit to force the transfer done.
+ * | | |1 = Enable the transaction start interrupt. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared.
+ * | | |0 = Disable the transfer start interrupt.
+ * |[11] |SLV_START_INTSTS|Slave 3-Wire Mode Start Interrupt Status
+ * | | |It is used to dedicate that the transfer has started in slave 3-wire mode.
+ * | | |1 = It indicates that the transfer has started in slave 3-wire mode. It will be cleared to 0 as transfer done or by writing one to this bit.
+ * | | |0 = It indicates that the SPI transfer is not active.
+ * |[16] |SS_INT_OPT|Slave Select Inactive Interrupt Option
+ * | | |This setting is only available if the SPI controller is configured as level trigger slave device.
+ * | | |1 = As the slave select signal goes to inactive level, the IF bit will be set to 1.
+ * | | |0 = As the slave select signal goes to inactive level, the IF bit will NOT be set to 1.
+ * |[31] |BCn |SPI Engine Clock Backward Compatible Option
+ * | | |1 = The clock configuration is not backward compatible.
+ * | | |0 = Backward compatible clock configuration.
+ */
+ __IO uint32_t CNTRL2;
+
+ /**
+ * FIFO_CTL
+ * ===================================================================================================
+ * Offset: 0x40 SPI FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RX_CLR |Clear Receive FIFO Buffer
+ * | | |0 = No effect.
+ * | | |1 = Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1.
+ * | | |This bit will be cleared to 0 by hardware after software sets it to 1.
+ * |[1] |TX_CLR |Clear Transmit FIFO Buffer
+ * | | |0 = No effect.
+ * | | |1 = Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1.
+ * | | |This bit will be cleared to 0 by hardware after software sets it to 1.
+ * |[2] |RX_INTEN |Receive Threshold Interrupt Enable
+ * | | |0 = Disable receive threshold interrupt
+ * | | |1 = Enable receive threshold interrupt
+ * |[3] |TX_INTEN |Transmit Threshold Interrupt Enable
+ * | | |0 = Disable transmit threshold interrupt
+ * | | |1 = Enable transmit threshold interrupt
+ * |[6] |RXOV_INTEN|Receive FIFO Overrun Interrupt Enable
+ * | | |1 = Enable Receive FIFO overrun interrupt.
+ * | | |0 = Disable Receive FIFO overrun interrupt
+ * |[21] |TIMEOUT_INTEN|Receive FIFO Time-out Interrupt Enable
+ * | | |1 = Enable time-out interrupt.
+ * | | |0 = Disable time-out interrupt.
+ * |[25:24] |RX_THRESHOLD |Received FIFO Threshold
+ * | | |If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting,
+ * | | |the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
+ * |[29:28] |RX_THRESHOLD |Transmit FIFO Threshold
+ * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting,
+ * | | |the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
+ */
+ __IO uint32_t FIFO_CTL;
+
+ /**
+ * STATUS
+ * ===================================================================================================
+ * Offset: 0x44 SPI Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RX_INTSTS |Receive FIFO Threshold Interrupt Status (read only)
+ * | | |1 = It indicates that the valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD.
+ * | | |0 = It indicates that the valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD.
+ * | | |Note: If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI interrupt request.
+ * |[2] |RX_OVERRUN|Receive FIFO Overrun Status
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+ * | | |Note: This bit will be cleared by writing 1 to itself.
+ * |[4] |TX_INTSTS |Transmit FIFO Threshold Interrupt Status (read only)
+ * | | |1 = It indicates that the valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD.
+ * | | |0 = It indicates that the valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD.
+ * | | |Note: If TX_INTEN = 1 and TX_INTSTS = 1, the SPI controller will generate a SPI interrupt request.
+ * |[11] |SLV_START_INTSTS|Slave Start Interrupt Status
+ * | | |It is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].
+ * | | |1 = It indicates that the transfer has started in slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit.
+ * | | |0 = It indicates that the transfer is not started.
+ * |[15:12] |RX_FIFO_COUNT |Receive FIFO Data Count (read only)
+ * | | |Indicates the valid data count of receive FIFO buffer.
+ * |[16] |IF |SPI Unit Transfer Interrupt Flag
+ * | | |It's a mutual mirror bit of SPI_CNTRL[16].
+ * | | |1 = It indicates that the SPI controller has finished one unit transfer.
+ * | | |0 = It indicates that the transfer does not finish yet.
+ * | | |Note: This bit will be cleared by writing 1 to itself.
+ * |[20] |TIMEOUT |Time-out Interrupt Flag
+ * | | |1 = It indicates that the receive FIFO buffer is not empty and there is not be read over 64 SPI clock period in master mode and over 576 SPI engine clock period in slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+ * | | |0 = No receive FIFO time-out event.
+ * | | |Note: This bit will be cleared by writing 1 to itself.
+ * |[24] |RX_EMPTY |Receive FIFO Buffer Empty Indicator (read only)
+ * | | |It's a mutual mirror bit of SPI_CNTRL[24].
+ * | | |1 = Indicates that the receive FIFO buffer is empty
+ * | | |0 = Indicates that the receive FIFO buffer is not empty
+ * |[25] |RX_FULL |Receive FIFO Buffer Full Indicator (read only)
+ * | | |It's a mutual mirror bit of SPI_CNTRL[25].
+ * | | |1 = Indicates that the receive FIFO buffer is full
+ * | | |0 = Indicates that the receive FIFO buffer is not full
+ * |[26] |TX_EMPTY |Transmit FIFO Buffer Empty Indicator (read only)
+ * | | |It's a mutual mirror bit of SPI_CNTRL[26].
+ * | | |1 = Indicates that the transmit FIFO buffer is empty
+ * | | |0 = Indicates that the transmit FIFO buffer is not empty
+ * |[27] |TX_FULL |Transmit FIFO Buffer Full Indicator (read only)
+ * | | |It's a mutual mirror bit of SPI_CNTRL[27].
+ * | | |1 = Indicates that the transmit FIFO buffer is full
+ * | | |0 = Indicates that the transmit FIFO buffer is not full
+ * |[31:28] |TX_FIFO_COUNT |Transmit FIFO Data Count (read only)
+ * | | |Indicates the valid data count of transmit FIFO buffer.
+ */
+ __IO uint32_t STATUS;
+
+} SPI_T;
+
+/** @addtogroup SPI_CONST SPI Bit Field Definition
+ Constant Definitions for SPI Controller
+ @{
+ */
+
+/* SPI_CNTRL Bit Field Definitions */
+#define SPI_CNTRL_TX_FULL_Pos 27 /*!< SPI CNTRL: TX_FULL Position */
+#define SPI_CNTRL_TX_FULL_Msk (1ul << SPI_CNTRL_TX_FULL_Pos) /*!< SPI CNTRL: TX_FULL Mask */
+
+#define SPI_CNTRL_TX_EMPTY_Pos 26 /*!< SPI CNTRL: TX_EMPTY Position */
+#define SPI_CNTRL_TX_EMPTY_Msk (1ul << SPI_CNTRL_TX_EMPTY_Pos) /*!< SPI CNTRL: TX_EMPTY Mask */
+
+#define SPI_CNTRL_RX_FULL_Pos 25 /*!< SPI CNTRL: RX_FULL Position */
+#define SPI_CNTRL_RX_FULL_Msk (1ul << SPI_CNTRL_RX_FULL_Pos) /*!< SPI CNTRL: RX_FULL Mask */
+
+#define SPI_CNTRL_RX_EMPTY_Pos 24 /*!< SPI CNTRL: RX_EMPTY Position */
+#define SPI_CNTRL_RX_EMPTY_Msk (1ul << SPI_CNTRL_RX_EMPTY_Pos) /*!< SPI CNTRL: RX_EMPTY Mask */
+
+#define SPI_CNTRL_FIFO_Pos 21 /*!< SPI CNTRL: FIFO Position */
+#define SPI_CNTRL_FIFO_Msk (1ul << SPI_CNTRL_FIFO_Pos) /*!< SPI CNTRL: FIFO Mask */
+
+#define SPI_CNTRL_REORDER_Pos 19 /*!< SPI CNTRL: REORDER Position */
+#define SPI_CNTRL_REORDER_Msk (3ul << SPI_CNTRL_REORDER_Pos) /*!< SPI CNTRL: REORDER Mask */
+
+#define SPI_CNTRL_SLAVE_Pos 18 /*!< SPI CNTRL: SLAVE Position */
+#define SPI_CNTRL_SLAVE_Msk (1ul << SPI_CNTRL_SLAVE_Pos) /*!< SPI CNTRL: SLAVE Mask */
+
+#define SPI_CNTRL_IE_Pos 17 /*!< SPI CNTRL: IE Position */
+#define SPI_CNTRL_IE_Msk (1ul << SPI_CNTRL_IE_Pos) /*!< SPI CNTRL: IE Mask */
+
+#define SPI_CNTRL_IF_Pos 16 /*!< SPI CNTRL: IF Position */
+#define SPI_CNTRL_IF_Msk (1ul << SPI_CNTRL_IF_Pos) /*!< SPI CNTRL: IF Mask */
+
+#define SPI_CNTRL_SP_CYCLE_Pos 12 /*!< SPI CNTRL: SP_CYCLE Position */
+#define SPI_CNTRL_SP_CYCLE_Msk (0xFul << SPI_CNTRL_SP_CYCLE_Pos) /*!< SPI CNTRL: SP_CYCLE Mask */
+
+#define SPI_CNTRL_CLKP_Pos 11 /*!< SPI CNTRL: CLKP Position */
+#define SPI_CNTRL_CLKP_Msk (1ul << SPI_CNTRL_CLKP_Pos) /*!< SPI CNTRL: CLKP Mask */
+
+#define SPI_CNTRL_LSB_Pos 10 /*!< SPI CNTRL: LSB Position */
+#define SPI_CNTRL_LSB_Msk (1ul << SPI_CNTRL_LSB_Pos) /*!< SPI CNTRL: LSB Mask */
+
+#define SPI_CNTRL_TX_BIT_LEN_Pos 3 /*!< SPI CNTRL: TX_BIT_LEN Position */
+#define SPI_CNTRL_TX_BIT_LEN_Msk (0x1Ful << SPI_CNTRL_TX_BIT_LEN_Pos) /*!< SPI CNTRL: TX_BIT_LEN Mask */
+
+#define SPI_CNTRL_TX_NEG_Pos 2 /*!< SPI CNTRL: TX_NEG Position */
+#define SPI_CNTRL_TX_NEG_Msk (1ul << SPI_CNTRL_TX_NEG_Pos) /*!< SPI CNTRL: TX_NEG Mask */
+
+#define SPI_CNTRL_RX_NEG_Pos 1 /*!< SPI CNTRL: RX_NEG Position */
+#define SPI_CNTRL_RX_NEG_Msk (1ul << SPI_CNTRL_RX_NEG_Pos) /*!< SPI CNTRL: RX_NEG Mask */
+
+#define SPI_CNTRL_GO_BUSY_Pos 0 /*!< SPI CNTRL: GO_BUSY Position */
+#define SPI_CNTRL_GO_BUSY_Msk (1ul << SPI_CNTRL_GO_BUSY_Pos) /*!< SPI CNTRL: GO_BUSY Mask */
+
+/* SPI_DIVIDER Bit Field Definitions */
+#define SPI_DIVIDER_DIVIDER2_Pos 16 /*!< SPI DIVIDER: DIVIDER2 Position */
+#define SPI_DIVIDER_DIVIDER2_Msk (0xFFFFul << SPI_DIVIDER_DIVIDER2_Pos) /*!< SPI DIVIDER: DIVIDER2 Mask */
+
+#define SPI_DIVIDER_DIVIDER_Pos 0 /*!< SPI DIVIDER: DIVIDER Position */
+#define SPI_DIVIDER_DIVIDER_Msk (0xFFFFul << SPI_DIVIDER_DIVIDER_Pos) /*!< SPI DIVIDER: DIVIDER Mask */
+
+/* SPI_SSR Bit Field Definitions */
+#define SPI_SSR_LTRIG_FLAG_Pos 5 /*!< SPI SSR: LTRIG_FLAG Position */
+#define SPI_SSR_LTRIG_FLAG_Msk (1ul << SPI_SSR_LTRIG_FLAG_Pos) /*!< SPI SSR: LTRIG_FLAG Mask */
+
+#define SPI_SSR_SS_LTRIG_Pos 4 /*!< SPI SSR: SS_LTRIG Position */
+#define SPI_SSR_SS_LTRIG_Msk (1ul << SPI_SSR_SS_LTRIG_Pos) /*!< SPI SSR: SS_LTRIG Mask */
+
+#define SPI_SSR_AUTOSS_Pos 3 /*!< SPI SSR: AUTOSS Position */
+#define SPI_SSR_AUTOSS_Msk (1ul << SPI_SSR_AUTOSS_Pos) /*!< SPI SSR: AUTOSS Mask */
+
+#define SPI_SSR_SS_LVL_Pos 2 /*!< SPI SSR: SS_LVL Position */
+#define SPI_SSR_SS_LVL_Msk (1ul << SPI_SSR_SS_LVL_Pos) /*!< SPI SSR: SS_LVL Mask */
+
+#define SPI_SSR_SSR_Pos 0 /*!< SPI SSR: SSR Position */
+#define SPI_SSR_SSR_Msk (1ul << SPI_SSR_SSR_Pos) /*!< SPI SSR: SSR Mask */
+
+/* SPI_CNTRL2 Bit Field Definitions */
+#define SPI_CNTRL2_BCn_Pos 31 /*!< SPI CNTRL2: BCn Position */
+#define SPI_CNTRL2_BCn_Msk (1ul << SPI_CNTRL2_BCn_Pos) /*!< SPI CNTRL2: BCn Mask */
+
+#define SPI_CNTRL2_SS_INT_OPT_Pos 16 /*!< SPI CNTRL2: SS_INT_OPT Position */
+#define SPI_CNTRL2_SS_INT_OPT_Msk (1ul << SPI_CNTRL2_SS_INT_OPT_Pos) /*!< SPI CNTRL2: SS_INT_OPT Mask */
+
+#define SPI_CNTRL2_SLV_START_INTSTS_Pos 11 /*!< SPI CNTRL2: SLV_START_INTSTS Position */
+#define SPI_CNTRL2_SLV_START_INTSTS_Msk (1ul << SPI_CNTRL2_SLV_START_INTSTS_Pos) /*!< SPI CNTRL2: SLV_START_INTSTS Mask */
+
+#define SPI_CNTRL2_SSTA_INTEN_Pos 10 /*!< SPI CNTRL2: SSTA_INTEN Position */
+#define SPI_CNTRL2_SSTA_INTEN_Msk (1ul << SPI_CNTRL2_SSTA_INTEN_Pos) /*!< SPI CNTRL2: SSTA_INTEN Mask */
+
+#define SPI_CNTRL2_SLV_ABORT_Pos 9 /*!< SPI CNTRL2: SLV_ABORT Position */
+#define SPI_CNTRL2_SLV_ABORT_Msk (1ul << SPI_CNTRL2_SLV_ABORT_Pos) /*!< SPI CNTRL2: SLV_ABORT Mask */
+
+#define SPI_CNTRL2_NOSLVSEL_Pos 8 /*!< SPI CNTRL2: NOSLVSEL Position */
+#define SPI_CNTRL2_NOSLVSEL_Msk (1ul << SPI_CNTRL2_NOSLVSEL_Pos) /*!< SPI CNTRL2: NOSLVSEL Mask */
+
+#define SPI_CNTRL2_DIV_ONE_Pos 0 /*!< SPI CNTRL2: DIV_ONE Position */
+#define SPI_CNTRL2_DIV_ONE_Msk (1ul << SPI_CNTRL2_DIV_ONE_Pos) /*!< SPI CNTRL2: DIV_ONE Mask */
+
+/* SPI_FIFO_CTL Bit Field Definitions */
+#define SPI_FIFO_CTL_TX_THRESHOLD_Pos 28 /*!< SPI FIFO_CTL: TX_THRESHOLD Position */
+#define SPI_FIFO_CTL_TX_THRESHOLD_Msk (3ul << SPI_FIFO_CTL_TX_THRESHOLD_Pos) /*!< SPI FIFO_CTL: TX_THRESHOLD Mask */
+
+#define SPI_FIFO_CTL_RX_THRESHOLD_Pos 24 /*!< SPI FIFO_CTL: RX_THRESHOLD Position */
+#define SPI_FIFO_CTL_RX_THRESHOLD_Msk (3ul << SPI_FIFO_CTL_RX_THRESHOLD_Pos) /*!< SPI FIFO_CTL: RX_THRESHOLD Mask */
+
+#define SPI_FIFO_CTL_TIMEOUT_INTEN_Pos 21 /*!< SPI FIFO_CTL: TIMEOUT_INTEN Position */
+#define SPI_FIFO_CTL_TIMEOUT_INTEN_Msk (1ul << SPI_FIFO_CTL_TIMEOUT_INTEN_Pos) /*!< SPI FIFO_CTL: TIMEOUT_INTEN Mask */
+
+#define SPI_FIFO_CTL_RXOV_INTEN_Pos 6 /*!< SPI FIFO_CTL: RXOV_INTEN Position */
+#define SPI_FIFO_CTL_RXOV_INTEN_Msk (1ul << SPI_FIFO_CTL_RXOV_INTEN_Pos) /*!< SPI FIFO_CTL: RXOV_INTEN Mask */
+
+#define SPI_FIFO_CTL_TX_INTEN_Pos 3 /*!< SPI FIFO_CTL: TX_INTEN Position */
+#define SPI_FIFO_CTL_TX_INTEN_Msk (1ul << SPI_FIFO_CTL_TX_INTEN_Pos) /*!< SPI FIFO_CTL: TX_INTEN Mask */
+
+#define SPI_FIFO_CTL_RX_INTEN_Pos 2 /*!< SPI FIFO_CTL: RX_INTEN Position */
+#define SPI_FIFO_CTL_RX_INTEN_Msk (1ul << SPI_FIFO_CTL_RX_INTEN_Pos) /*!< SPI FIFO_CTL: RX_INTEN Mask */
+
+#define SPI_FIFO_CTL_TX_CLR_Pos 1 /*!< SPI FIFO_CTL: TX_CLR Position */
+#define SPI_FIFO_CTL_TX_CLR_Msk (1ul << SPI_FIFO_CTL_TX_CLR_Pos) /*!< SPI FIFO_CTL: TX_CLR Mask */
+
+#define SPI_FIFO_CTL_RX_CLR_Pos 0 /*!< SPI FIFO_CTL: RX_CLR Position */
+#define SPI_FIFO_CTL_RX_CLR_Msk (1ul << SPI_FIFO_CTL_RX_CLR_Pos) /*!< SPI FIFO_CTL: RX_CLR Mask */
+
+/* SPI_STATUS Bit Field Definitions */
+#define SPI_STATUS_TX_FIFO_COUNT_Pos 28 /*!< SPI STATUS: TX_FIFO_COUNT Position */
+#define SPI_STATUS_TX_FIFO_COUNT_Msk (0xFul << SPI_STATUS_TX_FIFO_COUNT_Pos) /*!< SPI STATUS: TX_FIFO_COUNT Mask */
+
+#define SPI_STATUS_TX_FULL_Pos 27 /*!< SPI STATUS: TX_FULL Position */
+#define SPI_STATUS_TX_FULL_Msk (1ul << SPI_STATUS_TX_FULL_Pos) /*!< SPI STATUS: TX_FULL Mask */
+
+#define SPI_STATUS_TX_EMPTY_Pos 26 /*!< SPI STATUS: TX_EMPTY Position */
+#define SPI_STATUS_TX_EMPTY_Msk (1ul << SPI_STATUS_TX_EMPTY_Pos) /*!< SPI STATUS: TX_EMPTY Mask */
+
+#define SPI_STATUS_RX_FULL_Pos 25 /*!< SPI STATUS: RX_FULL Position */
+#define SPI_STATUS_RX_FULL_Msk (1ul << SPI_STATUS_RX_FULL_Pos) /*!< SPI STATUS: RX_FULL Mask */
+
+#define SPI_STATUS_RX_EMPTY_Pos 24 /*!< SPI STATUS: RX_EMPTY Position */
+#define SPI_STATUS_RX_EMPTY_Msk (1ul << SPI_STATUS_RX_EMPTY_Pos) /*!< SPI STATUS: RX_EMPTY Mask */
+
+#define SPI_STATUS_TIMEOUT_Pos 20 /*!< SPI STATUS: TIMEOUT Position */
+#define SPI_STATUS_TIMEOUT_Msk (1ul << SPI_STATUS_TIMEOUT_Pos) /*!< SPI STATUS: TIMEOUT Mask */
+
+#define SPI_STATUS_IF_Pos 16 /*!< SPI STATUS: IF Position */
+#define SPI_STATUS_IF_Msk (1ul << SPI_STATUS_IF_Pos) /*!< SPI STATUS: IF Mask */
+
+#define SPI_STATUS_RX_FIFO_COUNT_Pos 12 /*!< SPI STATUS: RX_FIFO_COUNT Position */
+#define SPI_STATUS_RX_FIFO_COUNT_Msk (0xFul << SPI_STATUS_RX_FIFO_COUNT_Pos) /*!< SPI STATUS: RX_FIFO_COUNT Mask */
+
+#define SPI_STATUS_SLV_START_INTSTS_Pos 11 /*!< SPI STATUS: SLV_START_INTSTS Position */
+#define SPI_STATUS_SLV_START_INTSTS_Msk (1ul << SPI_STATUS_SLV_START_INTSTS_Pos) /*!< SPI STATUS: SLV_START_INTSTS Mask */
+
+#define SPI_STATUS_TX_INTSTS_Pos 4 /*!< SPI STATUS: TX_INTSTS Position */
+#define SPI_STATUS_TX_INTSTS_Msk (1ul << SPI_STATUS_TX_INTSTS_Pos) /*!< SPI STATUS: TX_INTSTS Mask */
+
+#define SPI_STATUS_RX_OVERRUN_Pos 2 /*!< SPI STATUS: RX_OVERRUN Position */
+#define SPI_STATUS_RX_OVERRUN_Msk (1ul << SPI_STATUS_RX_OVERRUN_Pos) /*!< SPI STATUS: RX_OVERRUN Mask */
+
+#define SPI_STATUS_RX_INTSTS_Pos 0 /*!< SPI STATUS: RX_INTSTS Position */
+#define SPI_STATUS_RX_INTSTS_Msk (1ul << SPI_STATUS_RX_INTSTS_Pos) /*!< SPI STATUS: RX_INTSTS Mask */
+/**@}*/ /* SPI_CONST */
+/**@}*/ /* SPI */
+
+
+
+
+/*---------------------------- Clock Controller ------------------------------*/
+
+/** @addtogroup CLK System Clock Controller(CLK)
+ Memory Mapped Structure for System Clock Controller
+ @{
+ */
+
+typedef struct
+{
+ /**
+ * PWRCON
+ * ===================================================================================================
+ * Offset: 0x00 System Power Down Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |XTL12M_EN |External Crystal Oscillator Control
+ * | | |The bit default value is set by flash controller user configuration register config0 [26:24].
+ * | | |When the default clock source is from external crystal. The bit is auto set to "1"
+ * | | |1 = Crystal oscillation enable
+ * | | |0 = Crystal oscillation disable
+ * |[2] |OSC22M_EN |Internal 22.1184 MHz Oscillator Control
+ * | | |1 = 22.1184 MHz Oscillation enable
+ * | | |0 = 22.1184 MHz Oscillation disable
+ * |[3] |OSC10K_EN |Internal 10KHz Oscillator Control
+ * | | |1 = 10KHz Oscillation enable
+ * | | |0 = 10KHz Oscillation disable
+ * |[4] |PD_WU_DLY |Enable the wake up delay counter.
+ * | | |When the chip wakes up from power down mode, the clock control will delay certain clock
+ * | | |cycles to wait system clock stable.
+ * | | |The delayed clock cycle is 4096 clock cycles when chip work at external crystal (4 ~
+ * | | |24MHz), and 256 clock cycles when chip work at 22.1184 MHz oscillator.
+ * | | |1 = Enable the clock cycle delay
+ * | | |0 = Disable the clock cycle delay
+ * |[5] |PD_WU_INT_EN|Power down mode wake Up Interrupt Enable
+ * | | |0 = Disable
+ * | | |1 = Enable. The interrupt will occur when Power down mode (Deep Sleep Mode) wakeup.
+ * |[6] |PD_WU_STS |Chip power down wake up status flag
+ * | | |Set by "power down wake up", it indicates that resume from power down mode
+ * | | |The flag is set if the GPIO(P0~P4), UART wakeup
+ * | | |Write 1 to clear the bit
+ * | | |Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
+ * |[7] |PWR_DOWN_EN |System power down enable bit
+ * | | |When set this bit "1", the chip power down mode is enabled and the chip power down active
+ * | | |is depend on the PD_WAIT_CPU bit
+ * | | |(a) if the PD_WAIT_CPU is "0" then the chip power down after the PWR_DOWN_EN bit set.
+ * | | |(b) if the PD_WAIT_CPU is "1" then the chip keep active till the CPU sleep mode also active
+ * | | |and then the chip power down
+ * | | |When chip wake up from power down, this bit is auto cleared, user need to set this bit again
+ * | | |for next power down.
+ * | | |When in power down mode, external crystal (4~ 24MHz) and the 22.1184 MHz OSC will be
+ * | | |disabled in this mode, but the 10 kHz OSC is not controlled by power down mode.
+ * | | |When in power down mode, the PLL and system clock are disabled, and ignored the clock
+ * | | |source selection. The clocks of peripheral are not controlled by power down mode, if the
+ * | | |peripheral clock source is from 10 kHz oscillator.
+ * | | |1 = Chip enter the power down mode instant or wait CPU sleep command WFI
+ * | | |0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI
+ * | | |command
+ * |[8] |PD_WAIT_CPU |This bit control the power down entry condition
+ * | | |1 = Chip entry power down mode when the both PWR_DOWN and CPU run WFI instruction.
+ * | | |0 = Chip entry power down mode when the PWR_DOWN bit is set to 1
+ */
+ __IO uint32_t PWRCON;
+
+ /**
+ * AHBCLK
+ * ===================================================================================================
+ * Offset: 0x04 AHB Devices Clock Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2] |ISP_EN |Flash ISP Controller Clock Enable Control.
+ * | | |1 = To enable the Flash ISP controller clock.
+ * | | |0 = To disable the Flash ISP controller clock.
+ * |[3] |EBI_EN |EBI Controller Clock Enable Control.
+ * | | |1 = To enable the EBI Controller clock.
+ * | | |0 = To disable the EBI Controller clock.
+ * |[4] |HDIV_EN |Divider Controller Clock Enable Control.
+ * | | |1 = To enable the Divider Controller clock.
+ * | | |0 = To disable the Divider Controller clock.
+ */
+ __IO uint32_t AHBCLK;
+
+ /**
+ * APBCLK
+ * ===================================================================================================
+ * Offset: 0x08 APB Devices Clock Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WDT_EN |Watch Dog Timer Clock Enable.
+ * | | |This bit is the protected bit, program this need a open lock sequence, write "59h","16h","88h" to
+ * | | |address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address
+ * | | |GCR_BA + 0x100
+ * | | |0 = Disable Watchdog Timer Clock
+ * | | |1 = Enable Watchdog Timer Clock
+ * |[2] |TMR0_EN |Timer0 Clock Enable Control
+ * | | |0 = Disable Timer0 Clock
+ * | | |1 = Enable Timer0 Clock
+ * |[3] |TMR1_EN |Timer1 Clock Enable Control
+ * | | |0 = Disable Timer1 Clock
+ * | | |1 = Enable Timer1 Clock
+ * |[4] |TMR2_EN |Timer2 Clock Enable Control
+ * | | |0 = Disable Timer2 Clock
+ * | | |1 = Enable Timer2 Clock
+ * |[5] |TMR3_EN |Timer3 Clock Enable Control
+ * | | |0 = Disable Timer3 Clock
+ * | | |1 = Enable Timer3 Clock
+ * |[6] |FDIV_EN |Clock Divider Clock Enable Control
+ * | | |0 = Disable FDIV Clock
+ * | | |1 = Enable FDIV Clock
+ * |[8] |I2C_EN |I2C Clock Enable Control.
+ * | | |0 = Disable I2C Clock
+ * | | |1 = Enable I2C Clock
+ * |[12] |SPI0_EN |SPI0 Clock Enable Control.
+ * | | |0 = Disable SPI0 Clock
+ * | | |1 = Enable SPI0 Clock
+ * |[13] |SPI1_EN |SPI1 Clock Enable Control.
+ * | | |0 = Disable SPI1 Clock
+ * | | |1 = Enable SPI1 Clock
+ * |[16] |UART0_EN |UART0 Clock Enable Control.
+ * | | |1 = Enable UART0 clock
+ * | | |0 = Disable UART0 clock
+ * |[17] |UART1_EN |UART1 Clock Enable Control.
+ * | | |1 = Enable UART1 clock
+ * | | |0 = Disable UART1 clock
+ * |[20] |PWM01_EN |PWM_01 Clock Enable Control.
+ * | | |1 = Enable PWM01 clock
+ * | | |0 = Disable PWM01 clock
+ * |[21] |PWM23_EN |PWM_23 Clock Enable Control.
+ * | | |1 = Enable PWM23 clock
+ * | | |0 = Disable PWM23 clock
+ * |[22] |PWM45_EN |PWM_45 Clock Enable Control.
+ * | | |1 = Enable PWM45 clock
+ * | | |0 = Disable PWM45 clock
+ * |[23] |PWM67_EN |PWM_67 Clock Enable Control.
+ * | | |1 = Enable PWM67 clock
+ * | | |0 = Disable PWM67 clock
+ * |[28] |ADC_EN |Analog-Digital-Converter (ADC) Clock Enable Control.
+ * | | |1 = Enable ADC clock
+ * | | |0 = Disable ADC clock
+ */
+ __IO uint32_t APBCLK;
+
+ /**
+ * CLKSTATUS
+ * ===================================================================================================
+ * Offset: 0x0C Clock Status Monitor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |XTL12M_STB |XTL12M clock source stable flag
+ * | | |1 = External Crystal clock is stable
+ * | | |0 = External Crystal clock is not stable or not enable
+ * |[2] |PLL_STB |PLL clock source stable flag
+ * | | |1 = PLL clock is stable
+ * | | |0 = PLL clock is not stable or not enable
+ * |[3] |OSC10K_STB |OSC10K clock source stable flag
+ * | | |1 = OSC10K clock is stable
+ * | | |0 = OSC10K clock is not stable or not enable
+ * |[4] |OSC22M_STB |OSC22M clock source stable flag
+ * | | |1 = OSC22M clock is stable
+ * | | |0 = OSC22M clock is not stable or not enable
+ * |[7] |CLK_SW_FAIL|Clock switch fail flag
+ * | | |1 = Clock switch fail
+ * | | |0 = Clock switch success
+ * | | |This bit will be set when target switch clock source is not stable. Write 1 to clear this bit to zero.
+ */
+ __IO uint32_t CLKSTATUS;
+
+ /**
+ * CLKSEL0
+ * ===================================================================================================
+ * Offset: 0x10 Clock Source Select Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |HCLK_S |HCLK clock source select.
+ * | | |Note:
+ * | | |1. Before clock switch the related clock sources (pre-select and new-select) must be turn on
+ * | | |2. The 3-bit default value is reloaded with the value of Config0.CFOSC[26:24] in user
+ * | | |configuration register in Flash controller by any reset. Therefore the default value is either
+ * | | |000b or 111b.
+ * | | |3. These bits are protected bit, program this need an open lock sequence, write
+ * | | |"59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register
+ * | | |REGWRPROT at address GCR_BA + 0x100
+ * | | |000 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |010 = clock source from PLL clock
+ * | | |011 = clock source from internal 10KHz oscillator clock
+ * | | |111 = clock source from internal 22.1184 MHz oscillator clock
+ * | | |others = Reserved
+ * |[5:3] |STCLK_S |MCU Cortex_M0 SysTick clock source select.
+ * | | |These bits are protected bit, program this need an open lock sequence, write "59h","16h","88h" to
+ * | | |address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA
+ * | | |+ 0x100
+ * | | |000 = Clock source from external crystal clock (4 ~ 24MHz)
+ * | | |010 = Clock source from external crystal clock (4 ~ 24MHz)/2
+ * | | |011 = clock source from HCLK/2
+ * | | |1xx = clock source from internal 22.1184 MHz oscillator clock/2
+ */
+ __IO uint32_t CLKSEL0;
+
+ /**
+ * CLKSEL1
+ * ===================================================================================================
+ * Offset: 0x14 Clock Source Select Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |WDT_S |Watchdog Timer clock source select.
+ * | | |These bits are protected bit, program this need a open lock sequence, write "59h","16h","88h" to
+ * | | |address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address
+ * | | |GCR_BA + 0x100
+ * | | |00 = clock source from external crystal clock (4 ~ 24MHz).
+ * | | |10 = clock source from HCLK/2048 clock
+ * | | |11 = clock source from internal 10KHz oscillator clock
+ * |[3:2] |ADC_S |ADC clock source select.
+ * | | |00 = clock source from external crystal clock (4 ~ 24MHz).
+ * | | |01 = clock source from PLL clock
+ * | | |1x = clock source from internal 22.1184 MHz oscillator clock
+ * |[10:8] |TMR0_S |TIMER0 clock source select.
+ * | | |000 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |010 = clock source from HCLK
+ * | | |011 = clock source from external trigger
+ * | | |1xx = clock source from internal 22.1184 MHz oscillator clock
+ * |[14:12] |TMR1_S |TIMER1 clock source select.
+ * | | |000 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |010 = clock source from HCLK
+ * | | |011 = clock source from external trigger
+ * | | |1xx = clock source from internal 22.1184 MHz oscillator clock
+ * |[18:16] |TMR2_S |TIMER2 clock source select.
+ * | | |000 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |010 = clock source from HCLK
+ * | | |011 = clock source from external trigger
+ * | | |1xx = clock source from internal 22.1184 MHz oscillator clock
+ * |[22:20] |TMR3_S |TIMER3 clock source select.
+ * | | |000 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |010 = clock source from HCLK
+ * | | |011 = clock source from external trigger
+ * | | |1xx = clock source from internal 22.1184 MHz oscillator clock
+ * |[25:24] |UART_S |UART clock source select.
+ * | | |00 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |01 = clock source from PLL clock
+ * | | |1x = clock source from internal 22.1184 MHz oscillator clock
+ * |[29:28] |PWM01_S |PWM0 and PWM1 clock source select.
+ * | | |PWM0 and PWM1 uses the same Engine clock source, both of them with the same pre-scalar
+ * | | |00 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |10 = clock source from HCLK
+ * | | |11 = clock source from internal 22.1184 MHz oscillator clock
+ * |[31:30] |PWM23_S |PWM2 and PWM3 clock source select.
+ * | | |PWM2 and PWM3 uses the same Engine clock source, both of them with the same pre-scalar
+ * | | |00 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |10 = clock source from HCLK
+ * | | |11 = clock source from internal 22.1184 MHz oscillator clock
+ */
+ __IO uint32_t CLKSEL1;
+
+ /**
+ * CLKDIV
+ * ===================================================================================================
+ * Offset: 0x18 Clock Divider Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |HCLK_N |HCLK clock divide number from HCLK clock source
+ * | | |The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1)
+ * |[11:8] |UART_N |UART clock divide number from UART clock source
+ * | | |The UART clock frequency = (UART clock source frequency ) / (UART_N + 1)
+ * |[23:16] |ADC_N |ADC clock divide number from ADC clock source
+ * | | |The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1)
+ */
+ __IO uint32_t CLKDIV;
+
+ /**
+ * CLKSEL2
+ * ===================================================================================================
+ * Offset: 0x1C Clock Source Select Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:2] |FRQDIV_S |Clock Divider Clock Source Select
+ * | | |00 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |10 = clock source from HCLK
+ * | | |11 = clock source from internal 22.1184 MHz oscillator clock
+ * |[5:4] |PWM45_S |PWM4 and PWM5 clock source select. - PWM4 and PWM5 used the same Engine clock source,
+ * | | |both of them with the same pre-scalar
+ * | | |00 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |10 = clock source from HCLK
+ * | | |11 = clock source from internal 22.1184 MHz oscillator clock
+ * |[7:6] |PWM67_S |PWM6 and PWM7 clock source select. - PWM6 and PWM7 used the same Engine clock source,
+ * | | |both of them with the same pre-scalar
+ * | | |00 = clock source from external crystal clock (4 ~ 24MHz)
+ * | | |10 = clock source from HCLK
+ * | | |11 = clock source from internal 22.1184 MHz oscillator clock
+ */
+ __IO uint32_t CLKSEL2;
+
+ /**
+ * PLLCON
+ * ===================================================================================================
+ * Offset: 0x20 PLL Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |FB_DV |PLL Feedback Divider Control Pins (PLL_F[8:0])
+ * |[13:9] |IN_DV |PLL Input Divider Control Pins (PLL_R[4:0])
+ * |[15:14] |OUT_DV |PLL Output Divider Control Pins (PLL_OD[1:0])
+ * |[16] |PD |Power Down Mode.
+ * | | |If set the IDLE bit "1" in PWRCON register, the PLL will enter power down mode too
+ * | | |0 = PLL is in normal mode (default)
+ * | | |1 = PLL is in power-down mode
+ * |[17] |BP |PLL Bypass Control
+ * | | |0 = PLL is in normal mode (default)
+ * | | |1 = PLL clock output is same as clock input (XTALin)
+ * |[18] |OE |PLL OE (FOUT enable) pin Control
+ * | | |0 = PLL FOUT enable
+ * | | |1 = PLL FOUT is fixed low
+ * |[19] |PLL_SRC |PLL Source Clock Select
+ * | | |1 = PLL source clock from 22.1184 MHz oscillator
+ * | | |0 = PLL source clock from external crystal clock (4 ~ 24 MHz)
+ */
+ __IO uint32_t PLLCON;
+
+ /**
+ * FRQDIV
+ * ===================================================================================================
+ * Offset: 0x24 Frequency Divider Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |FSEL |Divider Output Frequency Selection Bits
+ * | | |The formula of output frequency is
+ * | | |Fout = Fin/2(N+1),
+ * | | |where Fin is the input clock frequency, Fout is the frequency of divider output clock, N is the 4-bit
+ * | | |value of FSEL[3:0].
+ * |[4] |DIVIDER_EN|Frequency Divider Enable Bit
+ * | | |0 = Disable Frequency Divider
+ * | | |1 = Enable Frequency Divider
+ */
+ __IO uint32_t FRQDIV;
+
+} CLK_T;
+
+/** @addtogroup CLK_CONST CLK Bit Field Definition
+ Constant Definitions for CLK Controller
+ @{
+ */
+
+/* CLK PWRCON Bit Field Definitions */
+#define CLK_PWRCON_PD_WAIT_CPU_Pos 8 /*!< CLK PWRCON: PD_WAIT_CPU Position */
+#define CLK_PWRCON_PD_WAIT_CPU_Msk (1ul << CLK_PWRCON_PD_WAIT_CPU_Pos) /*!< CLK PWRCON: PD_WAIT_CPU Mask */
+
+#define CLK_PWRCON_PWR_DOWN_EN_Pos 7 /*!< CLK PWRCON: PWR_DOWN_EN Position */
+#define CLK_PWRCON_PWR_DOWN_EN_Msk (1ul << CLK_PWRCON_PWR_DOWN_EN_Pos) /*!< CLK PWRCON: PWR_DOWN_EN Mask */
+
+#define CLK_PWRCON_PD_WU_STS_Pos 6 /*!< CLK PWRCON: PD_WU_STS Position */
+#define CLK_PWRCON_PD_WU_STS_Msk (1ul << CLK_PWRCON_PD_WU_STS_Pos) /*!< CLK PWRCON: PD_WU_STS Mask */
+
+#define CLK_PWRCON_PD_WU_INT_EN_Pos 5 /*!< CLK PWRCON: PD_WU_INT_EN Position */
+#define CLK_PWRCON_PD_WU_INT_EN_Msk (1ul << CLK_PWRCON_PD_WU_INT_EN_Pos) /*!< CLK PWRCON: PD_WU_INT_EN Mask */
+
+#define CLK_PWRCON_PD_WU_DLY_Pos 4 /*!< CLK PWRCON: PD_WU_DLY Position */
+#define CLK_PWRCON_PD_WU_DLY_Msk (1ul << CLK_PWRCON_PD_WU_DLY_Pos) /*!< CLK PWRCON: PD_WU_DLY Mask */
+
+#define CLK_PWRCON_OSC10K_EN_Pos 3 /*!< CLK PWRCON: OSC10K_EN Position */
+#define CLK_PWRCON_OSC10K_EN_Msk (1ul << CLK_PWRCON_OSC10K_EN_Pos) /*!< CLK PWRCON: OSC10K_EN Mask */
+#define CLK_PWRCON_IRC10K_EN_Pos 3 /*!< CLK PWRCON: OSC10K_EN Position */
+#define CLK_PWRCON_IRC10K_EN_Msk (1ul << CLK_PWRCON_OSC10K_EN_Pos) /*!< CLK PWRCON: OSC10K_EN Mask */
+
+#define CLK_PWRCON_OSC22M_EN_Pos 2 /*!< CLK PWRCON: OSC22M_EN Position */
+#define CLK_PWRCON_OSC22M_EN_Msk (1ul << CLK_PWRCON_OSC22M_EN_Pos) /*!< CLK PWRCON: OSC22M_EN Mask */
+#define CLK_PWRCON_IRC22M_EN_Pos 2 /*!< CLK PWRCON: OSC22M_EN Position */
+#define CLK_PWRCON_IRC22M_EN_Msk (1ul << CLK_PWRCON_OSC22M_EN_Pos) /*!< CLK PWRCON: OSC22M_EN Mask */
+
+#define CLK_PWRCON_XTL12M_EN_Pos 0 /*!< CLK PWRCON: XTL12M_EN Position */
+#define CLK_PWRCON_XTL12M_EN_Msk (1ul << CLK_PWRCON_XTL12M_EN_Pos) /*!< CLK PWRCON: XTL12M_EN Mask */
+
+/* CLK AHBCLK Bit Field Definitions */
+#define CLK_AHBCLK_HDIV_EN_Pos 4 /*!< CLK AHBCLK: HDIV_EN Position */
+#define CLK_AHBCLK_HDIV_EN_Msk (1ul << CLK_AHBCLK_HDIV_EN_Pos) /*!< CLK AHBCLK: HDIV_EN Mask */
+
+#define CLK_AHBCLK_EBI_EN_Pos 3 /*!< CLK AHBCLK: EBI_EN Position */
+#define CLK_AHBCLK_EBI_EN_Msk (1ul << CLK_AHBCLK_EBI_EN_Pos) /*!< CLK AHBCLK: EBI_EN Mask */
+
+#define CLK_AHBCLK_ISP_EN_Pos 2 /*!< CLK AHBCLK: ISP_EN Position */
+#define CLK_AHBCLK_ISP_EN_Msk (1ul << CLK_AHBCLK_ISP_EN_Pos) /*!< CLK AHBCLK: ISP_EN Mask */
+
+/* CLK APBCLK Bit Field Definitions */
+#define CLK_APBCLK_ACMP23_EN_Pos 31 /*!< CLK APBCLK: ACMP23_EN Position */
+#define CLK_APBCLK_ACMP23_EN_Msk (1ul << CLK_APBCLK_ACMP23_EN_Pos) /*!< CLK APBCLK: ACMP23_EN Mask */
+
+#define CLK_APBCLK_ACMP01_EN_Pos 30 /*!< CLK APBCLK: ACMP01_EN Position */
+#define CLK_APBCLK_ACMP01_EN_Msk (1ul << CLK_APBCLK_ACMP01_EN_Pos) /*!< CLK APBCLK: ACMP01_EN Mask */
+
+#define CLK_APBCLK_ADC_EN_Pos 28 /*!< CLK APBCLK: ADC_EN Position */
+#define CLK_APBCLK_ADC_EN_Msk (1ul << CLK_APBCLK_ADC_EN_Pos) /*!< CLK APBCLK: ADC_EN Mask */
+
+#define CLK_APBCLK_PWM67_EN_Pos 23 /*!< CLK APBCLK: PWM67_EN Position */
+#define CLK_APBCLK_PWM67_EN_Msk (1ul << CLK_APBCLK_PWM67_EN_Pos) /*!< CLK APBCLK: PWM67_EN Mask */
+
+#define CLK_APBCLK_PWM45_EN_Pos 22 /*!< CLK APBCLK: PWM45_EN Position */
+#define CLK_APBCLK_PWM45_EN_Msk (1ul << CLK_APBCLK_PWM45_EN_Pos) /*!< CLK APBCLK: PWM45_EN Mask */
+
+#define CLK_APBCLK_PWM23_EN_Pos 21 /*!< CLK APBCLK: PWM23_EN Position */
+#define CLK_APBCLK_PWM23_EN_Msk (1ul << CLK_APBCLK_PWM23_EN_Pos) /*!< CLK APBCLK: PWM23_EN Mask */
+
+#define CLK_APBCLK_PWM01_EN_Pos 20 /*!< CLK APBCLK: PWM01_EN Position */
+#define CLK_APBCLK_PWM01_EN_Msk (1ul << CLK_APBCLK_PWM01_EN_Pos) /*!< CLK APBCLK: PWM01_EN Mask */
+
+#define CLK_APBCLK_UART1_EN_Pos 17 /*!< CLK APBCLK: UART1_EN Position */
+#define CLK_APBCLK_UART1_EN_Msk (1ul << CLK_APBCLK_UART1_EN_Pos) /*!< CLK APBCLK: UART1_EN Mask */
+
+#define CLK_APBCLK_UART0_EN_Pos 16 /*!< CLK APBCLK: UART0_EN Position */
+#define CLK_APBCLK_UART0_EN_Msk (1ul << CLK_APBCLK_UART0_EN_Pos) /*!< CLK APBCLK: UART0_EN Mask */
+
+#define CLK_APBCLK_SPI1_EN_Pos 13 /*!< CLK APBCLK: SPI1_EN Position */
+#define CLK_APBCLK_SPI1_EN_Msk (1ul << CLK_APBCLK_SPI1_EN_Pos) /*!< CLK APBCLK: SPI1_EN Mask */
+
+#define CLK_APBCLK_SPI0_EN_Pos 12 /*!< CLK APBCLK: SPI0_EN Position */
+#define CLK_APBCLK_SPI0_EN_Msk (1ul << CLK_APBCLK_SPI0_EN_Pos) /*!< CLK APBCLK: SPI0_EN Mask */
+
+#define CLK_APBCLK_I2C1_EN_Pos 9 /*!< CLK APBCLK: I2C1_EN Position */
+#define CLK_APBCLK_I2C1_EN_Msk (1ul << CLK_APBCLK_I2C1_EN_Pos) /*!< CLK APBCLK: I2C1_EN Mask */
+
+#define CLK_APBCLK_I2C0_EN_Pos 8 /*!< CLK APBCLK: I2C0_EN Position */
+#define CLK_APBCLK_I2C0_EN_Msk (1ul << CLK_APBCLK_I2C0_EN_Pos) /*!< CLK APBCLK: I2C0_EN Mask */
+#define CLK_APBCLK_I2C_EN_Pos 8 /*!< CLK APBCLK: I2C_EN Position */
+#define CLK_APBCLK_I2C_EN_Msk (1ul << CLK_APBCLK_I2C_EN_Pos) /*!< CLK APBCLK: I2C_EN Mask */
+
+#define CLK_APBCLK_FDIV_EN_Pos 6 /*!< CLK APBCLK: FDIV_EN Position */
+#define CLK_APBCLK_FDIV_EN_Msk (1ul << CLK_APBCLK_FDIV_EN_Pos) /*!< CLK APBCLK: FDIV_EN Mask */
+
+#define CLK_APBCLK_TMR3_EN_Pos 5 /*!< CLK APBCLK: TMR3_EN Position */
+#define CLK_APBCLK_TMR3_EN_Msk (1ul << CLK_APBCLK_TMR3_EN_Pos) /*!< CLK APBCLK: TMR3_EN Mask */
+
+#define CLK_APBCLK_TMR2_EN_Pos 4 /*!< CLK APBCLK: TMR2_EN Position */
+#define CLK_APBCLK_TMR2_EN_Msk (1ul << CLK_APBCLK_TMR2_EN_Pos) /*!< CLK APBCLK: TMR2_EN Mask */
+
+#define CLK_APBCLK_TMR1_EN_Pos 3 /*!< CLK APBCLK: TMR1_EN Position */
+#define CLK_APBCLK_TMR1_EN_Msk (1ul << CLK_APBCLK_TMR1_EN_Pos) /*!< CLK APBCLK: TMR1_EN Mask */
+
+#define CLK_APBCLK_TMR0_EN_Pos 2 /*!< CLK APBCLK: TMR0_EN Position */
+#define CLK_APBCLK_TMR0_EN_Msk (1ul << CLK_APBCLK_TMR0_EN_Pos) /*!< CLK APBCLK: TMR0_EN Mask */
+
+#define CLK_APBCLK_WDT_EN_Pos 0 /*!< CLK APBCLK: WDT_EN Position */
+#define CLK_APBCLK_WDT_EN_Msk (1ul << CLK_APBCLK_WDT_EN_Pos) /*!< CLK APBCLK: WDT_EN Mask */
+
+/* CLK CLKSTATUS Bit Field Definitions */
+#define CLK_CLKSTATUS_CLK_SW_FAIL_Pos 7 /*!< CLK CLKSTATUS: CLK_SW_FAIL Position */
+#define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos)/*!< CLK CLKSTATUS: CLK_SW_FAIL Mask */
+
+#define CLK_CLKSTATUS_OSC22M_STB_Pos 4 /*!< CLK CLKSTATUS: OSC22M_STB Position */
+#define CLK_CLKSTATUS_OSC22M_STB_Msk (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos)/*!< CLK CLKSTATUS: OSC22M_STB Mask */
+#define CLK_CLKSTATUS_IRC22M_STB_Pos 4 /*!< CLK CLKSTATUS: IRC22M_STB Position */
+#define CLK_CLKSTATUS_IRC22M_STB_Msk (1ul << CLK_CLKSTATUS_IRC22M_STB_Pos)/*!< CLK CLKSTATUS: IRC22M_STB Mask */
+
+#define CLK_CLKSTATUS_OSC10K_STB_Pos 3 /*!< CLK CLKSTATUS: OSC10K_STB Position */
+#define CLK_CLKSTATUS_OSC10K_STB_Msk (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos)/*!< CLK CLKSTATUS: OSC10K_STB Mask */
+#define CLK_CLKSTATUS_IRC10K_STB_Pos 3 /*!< CLK CLKSTATUS: IRC10K_STB Position */
+#define CLK_CLKSTATUS_IRC10K_STB_Msk (1ul << CLK_CLKSTATUS_IRC10K_STB_Pos)/*!< CLK CLKSTATUS: IRC10K_STB Mask */
+
+#define CLK_CLKSTATUS_PLL_STB_Pos 2 /*!< CLK CLKSTATUS: PLL_STB Position */
+#define CLK_CLKSTATUS_PLL_STB_Msk (1ul << CLK_CLKSTATUS_PLL_STB_Pos) /*!< CLK CLKSTATUS: PLL_STB Mask */
+
+#define CLK_CLKSTATUS_XTL12M_STB_Pos 0 /*!< CLK CLKSTATUS: XTL12M_STB Position */
+#define CLK_CLKSTATUS_XTL12M_STB_Msk (1ul << CLK_CLKSTATUS_XTL12M_STB_Pos)/*!< CLK CLKSTATUS: XTL12M_STB Mask */
+
+/* CLK CLKSEL0 Bit Field Definitions */
+#define CLK_CLKSEL0_STCLK_S_Pos 3 /*!< CLK CLKSEL0: STCLK_S Position */
+#define CLK_CLKSEL0_STCLK_S_Msk (7ul << CLK_CLKSEL0_STCLK_S_Pos) /*!< CLK CLKSEL0: STCLK_S Mask */
+
+#define CLK_CLKSEL0_HCLK_S_Pos 0 /*!< CLK CLKSEL0: HCLK_S Position */
+#define CLK_CLKSEL0_HCLK_S_Msk (7ul << CLK_CLKSEL0_HCLK_S_Pos) /*!< CLK CLKSEL0: HCLK_S Mask */
+
+/* CLK CLKSEL1 Bit Field Definitions */
+#define CLK_CLKSEL1_PWM23_S_Pos 30 /*!< CLK CLKSEL1: PWM23_S Position */
+#define CLK_CLKSEL1_PWM23_S_Msk (3ul << CLK_CLKSEL1_PWM23_S_Pos) /*!< CLK CLKSEL1: PWM23_S Mask */
+
+#define CLK_CLKSEL1_PWM01_S_Pos 28 /*!< CLK CLKSEL1: PWM01_S Position */
+#define CLK_CLKSEL1_PWM01_S_Msk (3ul << CLK_CLKSEL1_PWM01_S_Pos) /*!< CLK CLKSEL1: PWM01_S Mask */
+
+#define CLK_CLKSEL1_UART_S_Pos 24 /*!< CLK CLKSEL1: UART_S Position */
+#define CLK_CLKSEL1_UART_S_Msk (3ul << CLK_CLKSEL1_UART_S_Pos) /*!< CLK CLKSEL1: UART_S Mask */
+
+#define CLK_CLKSEL1_TMR3_S_Pos 20 /*!< CLK CLKSEL1: TMR3_S Position */
+#define CLK_CLKSEL1_TMR3_S_Msk (7ul << CLK_CLKSEL1_TMR3_S_Pos) /*!< CLK CLKSEL1: TMR3_S Mask */
+
+#define CLK_CLKSEL1_TMR2_S_Pos 16 /*!< CLK CLKSEL1: TMR2_S Position */
+#define CLK_CLKSEL1_TMR2_S_Msk (7ul << CLK_CLKSEL1_TMR2_S_Pos) /*!< CLK CLKSEL1: TMR2_S Mask */
+
+#define CLK_CLKSEL1_TMR1_S_Pos 12 /*!< CLK CLKSEL1: TMR1_S Position */
+#define CLK_CLKSEL1_TMR1_S_Msk (7ul << CLK_CLKSEL1_TMR1_S_Pos) /*!< CLK CLKSEL1: TMR1_S Mask */
+
+#define CLK_CLKSEL1_TMR0_S_Pos 8 /*!< CLK CLKSEL1: TMR0_S Position */
+#define CLK_CLKSEL1_TMR0_S_Msk (7ul << CLK_CLKSEL1_TMR0_S_Pos) /*!< CLK CLKSEL1: TMR0_S Mask */
+
+#define CLK_CLKSEL1_SPI1_S_Pos 5 /*!< CLK CLKSEL1: SPI1_S Position */
+#define CLK_CLKSEL1_SPI1_S_Msk (1ul << CLK_CLKSEL1_SPI1_S_Pos) /*!< CLK CLKSEL1: SPI1_S Mask */
+
+#define CLK_CLKSEL1_SPI0_S_Pos 4 /*!< CLK CLKSEL1: SPI0_S Position */
+#define CLK_CLKSEL1_SPI0_S_Msk (1ul << CLK_CLKSEL1_SPI0_S_Pos) /*!< CLK CLKSEL1: SPI0_S Mask */
+
+#define CLK_CLKSEL1_ADC_S_Pos 2 /*!< CLK CLKSEL1: ADC_S Position */
+#define CLK_CLKSEL1_ADC_S_Msk (3ul << CLK_CLKSEL1_ADC_S_Pos) /*!< CLK CLKSEL1: ADC_S Mask */
+
+#define CLK_CLKSEL1_WDT_S_Pos 0 /*!< CLK CLKSEL1: WDT_S Position */
+#define CLK_CLKSEL1_WDT_S_Msk (3ul << CLK_CLKSEL1_WDT_S_Pos) /*!< CLK CLKSEL1: WDT_S Mask */
+
+/* CLK CLKSEL2 Bit Field Definitions */
+#define CLK_CLKSEL2_WWDT_S_Pos 16 /*!< CLK CLKSEL2: WWDT_S Position */
+#define CLK_CLKSEL2_WWDT_S_Msk (3ul << CLK_CLKSEL2_WWDT_S_Pos) /*!< CLK CLKSEL2: WWDT_S Mask */
+
+#define CLK_CLKSEL2_PWM67_S_Pos 6 /*!< CLK CLKSEL2: PWM67_S Position */
+#define CLK_CLKSEL2_PWM67_S_Msk (3ul << CLK_CLKSEL2_PWM67_S_Pos) /*!< CLK CLKSEL2: PWM67_S Mask */
+
+#define CLK_CLKSEL2_PWM45_S_Pos 4 /*!< CLK CLKSEL2: PWM45_S Position */
+#define CLK_CLKSEL2_PWM45_S_Msk (3ul << CLK_CLKSEL2_PWM45_S_Pos) /*!< CLK CLKSEL2: PWM45_S Mask */
+
+#define CLK_CLKSEL2_FRQDIV_S_Pos 2 /*!< CLK CLKSEL2: FRQDIV_S Position */
+#define CLK_CLKSEL2_FRQDIV_S_Msk (3ul << CLK_CLKSEL2_FRQDIV_S_Pos) /*!< CLK CLKSEL2: FRQDIV_S Mask */
+
+/* CLK CLKDIV Bit Field Definitions */
+#define CLK_CLKDIV_ADC_N_Pos 16 /*!< CLK CLKDIV: ADC_N Position */
+#define CLK_CLKDIV_ADC_N_Msk (0xFFul << CLK_CLKDIV_ADC_N_Pos) /*!< CLK CLKDIV: ADC_N Mask */
+
+#define CLK_CLKDIV_UART_N_Pos 8 /*!< CLK CLKDIV: UART_N Position */
+#define CLK_CLKDIV_UART_N_Msk (0xFul << CLK_CLKDIV_UART_N_Pos) /*!< CLK CLKDIV: UART_N Mask */
+
+#define CLK_CLKDIV_HCLK_N_Pos 0 /*!< CLK CLKDIV: HCLK_N Position */
+#define CLK_CLKDIV_HCLK_N_Msk (0xFul << CLK_CLKDIV_HCLK_N_Pos) /*!< CLK CLKDIV: HCLK_N Mask */
+
+/* CLK PLLCON Bit Field Definitions */
+#define CLK_PLLCON_PLL_SRC_Pos 19 /*!< CLK PLLCON: PLL_SRC Position */
+#define CLK_PLLCON_PLL_SRC_Msk (1ul << CLK_PLLCON_PLL_SRC_Pos) /*!< CLK PLLCON: PLL_SRC Mask */
+
+#define CLK_PLLCON_OE_Pos 18 /*!< CLK PLLCON: OE Position */
+#define CLK_PLLCON_OE_Msk (1ul << CLK_PLLCON_OE_Pos) /*!< CLK PLLCON: OE Mask */
+
+#define CLK_PLLCON_BP_Pos 17 /*!< CLK PLLCON: BP Position */
+#define CLK_PLLCON_BP_Msk (1ul << CLK_PLLCON_BP_Pos) /*!< CLK PLLCON: BP Mask */
+
+#define CLK_PLLCON_PD_Pos 16 /*!< CLK PLLCON: PD Position */
+#define CLK_PLLCON_PD_Msk (1ul << CLK_PLLCON_PD_Pos) /*!< CLK PLLCON: PD Mask */
+
+#define CLK_PLLCON_OUT_DV_Pos 14 /*!< CLK PLLCON: OUT_DV Position */
+#define CLK_PLLCON_OUT_DV_Msk (3ul << CLK_PLLCON_OUT_DV_Pos) /*!< CLK PLLCON: OUT_DV Mask */
+
+#define CLK_PLLCON_IN_DV_Pos 9 /*!< CLK PLLCON: IN_DV Position */
+#define CLK_PLLCON_IN_DV_Msk (0x1Ful << CLK_PLLCON_IN_DV_Pos) /*!< CLK PLLCON: IN_DV Mask */
+
+#define CLK_PLLCON_FB_DV_Pos 0 /*!< CLK PLLCON: FB_DV Position */
+#define CLK_PLLCON_FB_DV_Msk (0x1FFul << CLK_PLLCON_FB_DV_Pos) /*!< CLK PLLCON: FB_DV Mask */
+
+/* CLK FRQDIV Bit Field Definitions */
+#define CLK_FRQDIV_DIVIDER1_Pos 5 /*!< CLK FRQDIV: DIVIDER1 Position */
+#define CLK_FRQDIV_DIVIDER1_Msk (1ul << CLK_FRQDIV_DIVIDER1_Pos) /*!< CLK FRQDIV: DIVIDER1 Mask */
+
+#define CLK_FRQDIV_DIVIDER_EN_Pos 4 /*!< CLK FRQDIV: DIVIDER_EN Position */
+#define CLK_FRQDIV_DIVIDER_EN_Msk (1ul << CLK_FRQDIV_DIVIDER_EN_Pos) /*!< CLK FRQDIV: DIVIDER_EN Mask */
+
+#define CLK_FRQDIV_FSEL_Pos 0 /*!< CLK FRQDIV: FSEL Position */
+#define CLK_FRQDIV_FSEL_Msk (0xFul << CLK_FRQDIV_FSEL_Pos) /*!< CLK FRQDIV: FSEL Mask */
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* CLK */
+
+
+
+
+/*----------------------------- TIMER Controller -----------------------------*/
+/** @addtogroup TIMER TIMER Controller(TIMER)
+ Memory Mapped Structure for Timer Controller
+ @{
+ */
+typedef struct
+{
+ /**
+ * TCSR
+ * ===================================================================================================
+ * Offset: 0x00 Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |PRESCALE |Pre-scale Counter
+ * | | |Clock input is divided by PRESCALE+1 before it is fed to the counter. If
+ * | | |PRESCALE=0, then there is no scaling.
+ * |[16] |TDR_EN |Data Load Enable
+ * | | |When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with
+ * | | |the 24-bit up-timer value as the timer is counting.
+ * | | |1 = Timer Data Register update enable.
+ * | | |0 = Timer Data Register update disable.
+ * |[25] |CACT |Timer Active Status Bit (Read only)
+ * | | |This bit indicates the up-timer status.
+ * | | |0 = Timer is not active.
+ * | | |1 = Timer is active.
+ * |[26] |CRST |Timer Reset Bit
+ * | | |Set this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to
+ * | | |0.
+ * | | |0 = No effect.
+ * | | |1 = Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit.
+ * |[28:27] |MODE |Timer Operating Mode
+ * | | |00 =
+ * | | |The timer is operating in the one-shot mode. The associated
+ * | | |interrupt signal is generated once (if IE is enabled) and CEN is
+ * | | |automatically cleared by hardware.
+ * | | |01 =
+ * | | |The timer is operating in the periodic mode. The associated
+ * | | |interrupt signal is generated periodically (if IE is enabled).
+ * | | |10 =
+ * | | |The timer is operating in the toggle mode. The interrupt signal is
+ * | | |generated periodically (if IE is enabled). And the associated
+ * | | |signal (tout) is changing back and forth with 50% duty cycle.
+ * | | |11 =
+ * | | |Reserved
+ * |[29] |IE |Interrupt Enable Bit
+ * | | |1 = Enable timer Interrupt.
+ * | | |0 = Disable timer Interrupt.
+ * | | |If timer interrupt is enabled, the timer asserts its interrupt signal when the associated
+ * | | |up-timer value is equal to TCMPR.
+ * |[30] |CEN |Timer Enable Bit
+ * | | |1 = Starts counting
+ * | | |0 = Stops/Suspends counting
+ * | | |Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up
+ * | | |counting from the last stop counting value.
+ * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (MODE[28:27]=00)
+ * | | |when the associated timer interrupt is generated (IE[29]=1).
+ */
+ __IO uint32_t TCSR;
+
+ /**
+ * TCMPR
+ * ===================================================================================================
+ * Offset: 0x04 Timer Compare Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |TCMP |Timer Compared Value
+ * | | |TCMP is a 24-bit compared register. When the internal 24-bit up-timer counts and its value
+ * | | |is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with
+ * | | |TCSR.IE[29]=1. The TCMP value defines the timer counting cycle time.
+ * | | |Time out period = (Period of timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP)
+ * | | |NOTE1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.
+ * | | |NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register,
+ * | | |TIMER will restart counting using this new value and abort previous count.
+ */
+ __IO uint32_t TCMPR;
+
+ /**
+ * TISR
+ * ===================================================================================================
+ * Offset: 0x08 Timer Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TIF |Timer Interrupt Flag
+ * | | |This bit indicates the interrupt status of Timer.
+ * | | |TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer
+ * | | |compared value (TCMP). It is cleared by writing 1 to this bit.
+ */
+ __IO uint32_t TISR;
+
+ /**
+ * TDR
+ * ===================================================================================================
+ * Timer Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |TDR |Timer Data Register
+ * | | |When TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR.
+ * | | |User can read this register for the up-timer value.
+ */
+ __IO uint32_t TDR;
+
+ /**
+ * TCAP
+ * ===================================================================================================
+ * Timer Capture Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |TCAP |Timer Capture Data Register
+ * | | |When TEXEN (TEXCON[3]) is set, RSTCAPSEL (TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred,
+ * | | |the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value.
+ */
+ __IO uint32_t TCAP;
+
+ /**
+ * TEXCON
+ * ===================================================================================================
+ * Offset: 0x14 Timer External Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TX_PHASE |Timer External Count Phase
+ * | | |This bit indicates the external count pin phase.
+ * | | |1 = A rising edge of external count pin will be counted.
+ * | | |0 = A falling edge of external count pin will be counted.
+ * |[2:1] |TEX_EDGE |Timer External Pin Edge Detect
+ * | | |00 = a 1 to 0 transition on TEX will be detected.
+ * | | |01 = a 0 to 1 transition on TEX will be detected.
+ * | | |10 = either 1 to 0 or 0 to 1 transition on TEX will be detected.
+ * | | |11 = Reserved.
+ * |[3] |TEXEN |Timer External Pin Enable.
+ * | | |This bit enables the reset/capture function on the TEX pin.
+ * | | |1 = The transition detected on the TEX pin will result in capture or reset of timer counter.
+ * | | |0 = The TEX pin will be ignored.
+ * |[4] |RSTCAPSEL |Timer External Reset Counter / Capture mode select
+ * | | |1 = TEX transition is using as the timer counter reset function.
+ * | | |0 = TEX transition is using as the timer capture function.
+ * |[5] |TEXIEN |Timer External interrupt Enable Bit
+ * | | |1 = Enable timer External Interrupt
+ * | | |0 = Disable timer External Interrupt
+ * | | |If timer external interrupt is enabled, the timer asserts its external interrupt signal and sent to NVIC to inform CPU
+ * | | |when the transition on the TEX pins associated with TEX_EDGE(TEXCON[2:1]) setting is happened.
+ * | | |For example, while TEXIEN = 1, TEXEN = 1, and TEX_EDGE = 00,
+ * | | |a 1 to 0 transition on the TEX pin will cause the TEXIF(TEXISR[0]) interrupt flag to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
+ * |[6] |TEXDB |Timer External Capture pin De-bounce enable bit
+ * | | |1 = Enable De-bounce
+ * | | |0 = Disable De-bounce
+ * | | |If this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit.
+ * |[7] |TCDB |Timer Counter pin De-bounce enable bit
+ * | | |1 = Enable De-bounce
+ * | | |0 = Disable De-bounce
+ * | | |If this bit is enabled, the edge of T0~T3 pin is detected with de-bounce circuit.
+ */
+ __IO uint32_t TEXCON;
+
+ /**
+ * TEXISR
+ * ===================================================================================================
+ * Offset: 0x14 Timer External Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TEXIF |Timer External Interrupt Flag
+ * | | |This bit indicates the external interrupt status of Timer.
+ * | | |This bit is set by hardware when TEXEN (TEXCON[3]) is to 1,and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred.
+ * | | |It is cleared by writing 1 to this bit.
+ * | | |For example, while TEXEN = 1, and TEX_EDGE = 00, a 1 to 0 transition on the TEX pin will cause the TEXIF to be set.
+ */
+ __IO uint32_t TEXISR;
+} TIMER_T;
+
+/** @addtogroup TMR_CONST Timer Bit Field Definition
+ Constant Definitions for Timer Controller
+ @{
+ */
+
+/* TIMER TCSR Bit Field Definitions */
+#define TIMER_TCSR_DBGACK_TMR_Pos 31 /*!< TIMER TCSR: DBGACK_TMR Position */
+#define TIMER_TCSR_DBGACK_TMR_Msk (1ul << TIMER_TCSR_DBGACK_TMR_Pos) /*!< TIMER TCSR: DBGACK_TMR Mask */
+
+#define TIMER_TCSR_CEN_Pos 30 /*!< TIMER TCSR: CEN Position */
+#define TIMER_TCSR_CEN_Msk (1ul << TIMER_TCSR_CEN_Pos) /*!< TIMER TCSR: CEN Mask */
+
+#define TIMER_TCSR_IE_Pos 29 /*!< TIMER TCSR: IE Position */
+#define TIMER_TCSR_IE_Msk (1ul << TIMER_TCSR_IE_Pos) /*!< TIMER TCSR: IE Mask */
+
+#define TIMER_TCSR_MODE_Pos 27 /*!< TIMER TCSR: MODE Position */
+#define TIMER_TCSR_MODE_Msk (0x3ul << TIMER_TCSR_MODE_Pos) /*!< TIMER TCSR: MODE Mask */
+
+#define TIMER_TCSR_CRST_Pos 26 /*!< TIMER TCSR: CRST Position */
+#define TIMER_TCSR_CRST_Msk (1ul << TIMER_TCSR_CRST_Pos) /*!< TIMER TCSR: CRST Mask */
+
+#define TIMER_TCSR_CACT_Pos 25 /*!< TIMER TCSR: CACT Position */
+#define TIMER_TCSR_CACT_Msk (1ul << TIMER_TCSR_CACT_Pos) /*!< TIMER TCSR: CACT Mask */
+
+#define TIMER_TCSR_CTB_Pos 24 /*!< TIMER TCSR: CTB Position */
+#define TIMER_TCSR_CTB_Msk (1ul << TIMER_TCSR_CTB_Pos) /*!< TIMER TCSR: CTB Mask */
+
+#define TIMER_TCSR_WAKE_EN_Pos 23 /*!< TIMER TCSR: WAKE_EN Position */
+#define TIMER_TCSR_WAKE_EN_Msk (1ul << TIMER_TCSR_WAKE_EN_Pos) /*!< TIMER TCSR: WAKE_EN Mask */
+
+#define TIMER_TCSR_CAP_SRC_Pos 22 /*!< TIMER TCSR: CAP_SRC Position */
+#define TIMER_TCSR_CAP_SRC_Msk (1ul << TIMER_TCSR_CAP_SRC_Pos) /*!< TIMER TCSR: CAP_SRC Mask */
+
+#define TIMER_TCSR_TOUT_SEL_Pos 21 /*!< TIMER TCSR: TOUT_SEL Position */
+#define TIMER_TCSR_TOUT_SEL_Msk (1ul << TIMER_TCSR_TOUT_SEL_Pos) /*!< TIMER TCSR: TOUT_SEL Mask */
+
+#define TIMER_TCSR_ERIODIC_SEL_Pos 20 /*!< TIMER TCSR: PERIODIC_SEL Position */
+#define TIMER_TCSR_ERIODIC_SEL_Msk (1ul << TIMER_TCSR_ERIODIC_SEL_Pos) /*!< TIMER TCSR: PERIODIC_SEL Mask */
+
+#define TIMER_TCSR_INTR_TRG_EN_Pos 19 /*!< TIMER TCSR: INTR_TRG_EN Position */
+#define TIMER_TCSR_INTR_TRG_EN_Msk (1ul << TIMER_TCSR_INTR_TRG_EN_Pos) /*!< TIMER TCSR: INTR_TRG_EN Mask */
+
+#define TIMER_TCSR_TDR_EN_Pos 16 /*!< TIMER TCSR: TDR_EN Position */
+#define TIMER_TCSR_TDR_EN_Msk (1ul << TIMER_TCSR_TDR_EN_Pos) /*!< TIMER TCSR: TDR_EN Mask */
+
+#define TIMER_TCSR_PRESCALE_Pos 0 /*!< TIMER TCSR: PRESCALE Position */
+#define TIMER_TCSR_PRESCALE_Msk (0xFFul << TIMER_TCSR_PRESCALE_Pos) /*!< TIMER TCSR: PRESCALE Mask */
+
+/* TIMER TCMPR Bit Field Definitions */
+#define TIMER_TCMP_TCMP_Pos 0 /*!< TIMER TCMPR: TCMP Position */
+#define TIMER_TCMP_TCMP_Msk (0xFFFFFFul << TIMER_TCMP_TCMP_Pos) /*!< TIMER TCMPR: TCMP Mask */
+
+/* TIMER TISR Bit Field Definitions */
+#define TIMER_TISR_TWF_Pos 1 /*!< TIMER TISR: TWF Position */
+#define TIMER_TISR_TWF_Msk (1ul << TIMER_TISR_TWF_Pos) /*!< TIMER TISR: TWF Mask */
+
+#define TIMER_TISR_TIF_Pos 0 /*!< TIMER TISR: TIF Position */
+#define TIMER_TISR_TIF_Msk (1ul << TIMER_TISR_TIF_Pos) /*!< TIMER TISR: TIF Mask */
+
+/* TIMER TDR Bit Field Definitions */
+#define TIMER_TDR_TDR_Pos 0 /*!< TIMER TDR: TDR Position */
+#define TIMER_TDR_TDR_Msk (0xFFFFFFul << TIMER_TDR_TDR_Pos) /*!< TIMER TDR: TDR Mask */
+
+/* TIMER TCAP Bit Field Definitions */
+#define TIMER_TCAP_TCAP_Pos 0 /*!< TIMER TCAP: TCAP Position */
+#define TIMER_TCAP_TCAP_Msk (0xFFFFFFul << TIMER_TCAP_TCAP_Pos) /*!< TIMER TCAP: TCAP Mask */
+
+/* TIMER TEXCON Bit Field Definitions */
+#define TIMER_TEXCON_TCDB_Pos 7 /*!< TIMER TEXCON: TCDB Position */
+#define TIMER_TEXCON_TCDB_Msk (1ul << TIMER_TEXCON_TCDB_Pos) /*!< TIMER TEXCON: TCDB Mask */
+
+#define TIMER_TEXCON_TEXDB_Pos 6 /*!< TIMER TEXCON: TEXDB Position */
+#define TIMER_TEXCON_TEXDB_Msk (1ul << TIMER_TEXCON_TEXDB_Pos) /*!< TIMER TEXCON: TEXDB Mask */
+
+#define TIMER_TEXCON_TEXIEN_Pos 5 /*!< TIMER TEXCON: TEXIEN Position */
+#define TIMER_TEXCON_TEXIEN_Msk (1ul << TIMER_TEXCON_TEXIEN_Pos) /*!< TIMER TEXCON: TEXIEN Mask */
+
+#define TIMER_TEXCON_RSTCAPSEL_Pos 4 /*!< TIMER TEXCON: RSTCAPSEL Position */
+#define TIMER_TEXCON_RSTCAPSEL_Msk (1ul << TIMER_TEXCON_RSTCAPSEL_Pos) /*!< TIMER TEXCON: RSTCAPSEL Mask */
+
+#define TIMER_TEXCON_TEXEN_Pos 3 /*!< TIMER TEXCON: TEXEN Position */
+#define TIMER_TEXCON_TEXEN_Msk (1ul << TIMER_TEXCON_TEXEN_Pos) /*!< TIMER TEXCON: TEXEN Mask */
+
+#define TIMER_TEXCON_TEX_EDGE_Pos 1 /*!< TIMER TEXCON: TEX_EDGE Position */
+#define TIMER_TEXCON_TEX_EDGE_Msk (0x3ul << TIMER_TEXCON_TEX_EDGE_Pos) /*!< TIMER TEXCON: TEX_EDGE Mask */
+
+#define TIMER_TEXCON_TX_PHASE_Pos 0 /*!< TIMER TEXCON: TX_PHASE Position */
+#define TIMER_TEXCON_TX_PHASE_Msk (1ul << TIMER_TEXCON_TX_PHASE_Pos) /*!< TIMER TEXCON: TX_PHASE Mask */
+
+/* TIMER TEXISR Bit Field Definitions */
+#define TIMER_TEXISR_TEXIF_Pos 0 /*!< TIMER TEXISR: TEXIF Position */
+#define TIMER_TEXISR_TEXIF_Msk (1ul << TIMER_TEXISR_TEXIF_Pos) /*!< TIMER TEXISR: TEXIF Mask */
+/**@}*/ /* TMR_CONST */
+/**@}*/ /* TIMER */
+
+
+/*------------------------- UART Interface Controller ------------------------*/
+
+/** @addtogroup UART UART Controller(UART)
+ Memory Mapped Structure for UART Serial Interface Controller
+ @{
+ */
+typedef struct
+{
+
+ union
+ {
+ __IO uint32_t DATA;
+
+ /**
+ * THR
+ * ===================================================================================================
+ * Offset: 0x00 Transmit Holding DATA
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] | |bitTransmittedData
+ * | | |Transmit Holding Register
+ * | | |By writing to this register, the UART will send out an 8-bit data through the Tx pin (LSB
+ * | | |first).
+ */
+ __IO uint32_t THR;
+
+ /**
+ * RBR
+ * ===================================================================================================
+ * Offset: 0x00 Receive Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] | |Receive Buffer Register
+ * | | |By reading this register, the UART will return an 8-bit data received from Rx pin (LSB first).
+ */
+ __IO uint32_t RBR;
+ };
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x04 UART Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDA_IEN |Receive Data Available Interrupt Enable.
+ * | | |0 = Mask off INT_RDA
+ * | | |1 = Enable INT_RDA
+ * |[1] |THRE_IEN |Transmit Holding Register Empty Interrupt Enable
+ * | | |0 = Mask off INT_THRE
+ * | | |1 = Enable INT_THRE
+ * |[2] |RLS_IEN |Receive Line Status Interrupt Enable
+ * | | |0 = Mask off INT_RLS
+ * | | |1 = Enable INT_RLS
+ * |[3] |MODEM_IEN |Modem Status Interrupt Enable
+ * | | |0 = Mask off INT_MOS
+ * | | |1 = Enable INT_MOS
+ * |[4] |RTO_IEN |Rx Time out Interrupt Enable
+ * | | |0 = Mask off INT_tout
+ * | | |1 = Enable INT_tout
+ * |[5] |BUF_ERR_IEN|Buffer Error Interrupt Enable
+ * | | |0 = Mask off INT_Buf_err
+ * | | |1 = Enable INT_Buf_err
+ * |[6] |WAKE_EN |Wake up CPU function enable
+ * | | |0 = Disable UART wake up CPU function
+ * | | |1 = Enable wake up function, when the system is in deep sleep mode, an external /CTS
+ * | | |change will wake up CPU from deep sleep mode.
+ * |[11] |TIME_OUT_EN|Time-Out Counter Enable
+ * | | |1 = Enable Time-out counter.
+ * | | |0 = Disable Time-out counter.
+ * |[12] |AUTO_RTS_EN|RTS Auto Flow Control Enable
+ * | | |1 = Enable RTS auto flow control.
+ * | | |0 = Disable RTS auto flow control.
+ * | | |When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals the UA_FCR
+ * | | |[RTS_TRI_LEV], the UART will dessert RTS signal.|[13] |Auto_CTS_EN
+ * |[13] |AUTO_CTS_EN|CTS Auto Flow Control Enable
+ * | | |1 = Enable CTS auto flow control.
+ * | | |0 = Disable CTS auto flow control.
+ * | | |When CTS auto-flow is enabled, the UART will send data to external device when CTS input
+ * | | |assert (UART will not send data to device until CTS is asserted).
+ */
+ __IO uint32_t IER;
+
+ /**
+ * FCR
+ * ===================================================================================================
+ * Offset: 0x08 UART FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |RFR |Rx Software Reset
+ * | | |When Rx_RST is set, all the bytes in the transmit FIFO and Rx internal state machine are
+ * | | |cleared.
+ * | | |0 = Writing 0 to this bit has no effect.
+ * | | |1 = Writing 1 to this bit will reset the Rx internal state machine and pointers.
+ * | | |Note: This bit will auto clear and takes at least 3 UART engine clock cycles.
+ * |[2] |TFR |Tx Software Reset
+ * | | |When Tx_RST is set, all the bytes in the transmit FIFO and Tx internal state machine are
+ * | | |cleared.
+ * | | |0 = Writing 0 to this bit has no effect.
+ * | | |1 = Writing 1 to this bit will reset the Tx internal state machine and pointers.
+ * | | |Note: This bit will auto clear and takes at least 3 UART engine clock cycles.
+ * |[7:4] |RFITL |INT_RDA Tigger Level(Bytes)
+ * | | |0000 = 01 Bytes
+ * | | |0001 = 04 Bytes
+ * | | |0010 = 08 Bytes
+ * | | |0011 = 14 Bytes
+ * |[8] |RX_DIS |Receiver Disable register.
+ * | | |The receiver is disabled or not (set 1 is disable receiver)
+ * | | |1: Disable Receiver
+ * | | |0: Enable Receiver
+ * | | |Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before
+ * | | |RS-485 enable function in UA_FUN_SEL. FUN_SEL is programmed.
+ * |[19:16] |RTS_TRI_LEV|RTS Trigger Level Select
+ * | | |0000 = 01 Bytes
+ * | | |0001 = 04 Bytes
+ * | | |0010 = 08 Bytes
+ * | | |0011 = 14 Bytes
+ */
+ __IO uint32_t FCR;
+
+ /**
+ * LCR
+ * ===================================================================================================
+ * Offset: 0x0C UART Line Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |WLS |Word Length Select
+ * | | |00 = 5 bits
+ * | | |01 = 6 bits
+ * | | |10 = 7 bits
+ * | | |11 = 8 bits
+ * |[2] |NSB |Number of "STOP bit"
+ * | | |0= One "STOP bit" is generated in the transmitted data
+ * | | |1= One and a half "STOP bit" is generated in the transmitted data when 5-bit word length is selected;
+ * | | |Two "STOP bit" is generated when 6-, 7- and 8-bit word length is selected.
+ * |[3] |PBE |Parity Bit Enable
+ * | | |0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer.
+ * | | |1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
+ * |[4] |EPE |Even Parity Enable
+ * | | |0 = Odd number of logic 1's are transmitted or checked in the data word and parity bits.
+ * | | |1 = Even number of logic 1's are transmitted or checked in the data word and parity bits.
+ * | | |This bit has effect only when bit 3 (parity bit enable) is set.
+ * |[5] |SPE |Stick Parity Enable
+ * | | |0 = Disable stick parity
+ * | | |1 = When bits PBE , EPE and SPE are set, the parity bit is transmitted and checked as cleared. When
+ * | | |PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as set.
+ * |[6] |BCB |Break Control Bit
+ * | | |When this bit is set to logic 1, the serial data output (Tx) is forced to the Spacing State (logic 0). This bit
+ * | | |acts only on Tx and has no effect on the transmitter logic.
+ */
+ __IO uint32_t LCR;
+
+ /**
+ * MCR
+ * ===================================================================================================
+ * Offset: 0x10 UART Modem Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |RTS |RTS (Request-To-Send) Signal
+ * | | |0: Drive RTS pin to logic 1 (If the Lev_RTS set to low level triggered).
+ * | | |1: Drive RTS pin to logic 0 (If the Lev_RTS set to low level triggered).
+ * | | |0: Drive RTS pin to logic 0 (If the Lev_RTS set to high level triggered).
+ * | | |1: Drive RTS pin to logic 1 (If the Lev_RTS set to high level triggered).
+ * |[9] |LEV_RTS |RTS Trigger Level
+ * | | |This bit can change the RTS trigger level.
+ * | | |0= low level triggered
+ * | | |1= high level triggered
+ * |[13] |RTS_ST |RTS Pin State
+ * | | |This bit is the pin status of RTS.
+ */
+ __IO uint32_t MCR;
+
+ /**
+ * MSR
+ * ===================================================================================================
+ * Offset: 0x14 UART Modem Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DCTSF |Detect CTS State Change Flag
+ * | | |This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU
+ * | | |when IER [Modem_IEN].
+ * | | |NOTE: This bit is cleared by writing 1 to itself.
+ * |[4] |CTS_ST |CTS Pin Status
+ * | | |This bit is the pin status of CTS.
+ * |[8] |LEV_CTS |CTS Trigger Level
+ * | | |This bit can change the CTS trigger level.
+ * | | |0= low level triggered
+ * | | |1= high level triggered
+ */
+ __IO uint32_t MSR;
+
+ /**
+ * FSR
+ * ===================================================================================================
+ * Offset: 0x18 UART FIFO Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RX_OVER_IF|Rx overflow Error IF (Read Only)
+ * | | |This bit is set when Rx FIFO overflow.
+ * | | |If the number of bytes of received data is greater than Rx FIFO(UA_RBR) size, 16 bytes of
+ * | | |UART0/UART1, this bit will be set.
+ * | | |NOTE: This bit is cleared by writing 1 to itself.
+ * |[3] |RS485_ADD_DETF|RS-485 Address Byte Detection Flag
+ * | | |This bit is set to logic 1 and set UA_RS-485_CSR [RS485_ADD_EN] whenever in RS-485
+ * | | |mode the receiver detect any address byte received address byte character (bit9 = '1') bit",
+ * | | |and it is reset whenever the CPU writes 1 to this bit.
+ * | | |Note: This field is used for RS-485 mode.
+ * |[4] |PEF |Parity Error Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit",
+ * | | |and is reset whenever the CPU writes 1 to this bit.
+ * |[5] |FEF |Framing Error Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that
+ * | | |is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset
+ * | | |whenever the CPU writes 1 to this bit.
+ * |[6] |BIF |Break Interrupt Flag
+ * | | |This bit is set to a logic 1 whenever the received data input(Rx) is held in the "spacing state"
+ * | | |(logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data
+ * | | |bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
+ * |[13:8] |RX_POINTER|Rx FIFO pointer (Read Only)
+ * | | |This field indicates the Rx FIFO Buffer Pointer. When UART receives one byte from external
+ * | | |device, Rx_Pointer increases one. When one byte of Rx FIFO is read by CPU, Rx_Pointer
+ * | | |decreases one.
+ * |[14] |RX_EMPTY |Receiver FIFO Empty (Read Only)
+ * | | |This bit initiate Rx FIFO empty or not.
+ * | | |When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be
+ * | | |cleared when UART receives any new data.
+ * |[15] |RX_FULL |Receiver FIFO Full (Read Only)
+ * | | |This bit initiates Rx FIFO full or not.
+ * | | |This bit is set when Rx_Pointer is equal to 16(UART0/UART1), otherwise is cleared by
+ * | | |hardware.
+ * |[21:16] |TX_POINTER|TX FIFO Pointer (Read Only)
+ * | | |This field indicates the Tx FIFO Buffer Pointer. When CPU write one byte into UA_THR,
+ * | | |Tx_Pointer increases one. When one byte of Tx FIFO is transferred to Transmitter Shift
+ * | | |Register, Tx_Pointer decreases one.
+ * |[22] |TX_EMPTY |Transmitter FIFO Empty (Read Only)
+ * | | |This bit indicates Tx FIFO empty or not.
+ * | | |When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware
+ * | | |sets this bit high. It will be cleared when writing data into THR (Tx FIFO not empty).
+ * |[23] |TX_Full |Transmitter FIFO Full (Read Only)
+ * | | |This bit indicates Tx FIFO full or not.
+ * | | |This bit is set when Tx_Pointer is equal to 64/16(UART0/UART1), otherwise is cleared by
+ * | | |hardware.
+ * |[24] |TX_OVER_IF|Tx Overflow Error Interrupt Flag (Read Only)
+ * | | |If Tx FIFO(UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.
+ * | | |NOTE: This bit is cleared by writing 1 to itself.
+ * |[28] |TE_FLAG |Transmitter Empty Flag (Read Only)
+ * | | |Bit is set by hardware when Tx FIFO(UA_THR) is empty and the STOP bit of the last byte
+ * | | |has been transmitted.
+ * | | |Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not
+ * | | |completed.
+ * | | |NOTE: This bit is read only.
+ */
+ __IO uint32_t FSR;
+
+ /**
+ * ISR
+ * ===================================================================================================
+ * Offset: 0x1C UART Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDA_IF |Receive Data Available Interrupt Flag (Read Only).
+ * | | |When the number of bytes in the Rx FIFO equals the RFITL then the RDA_IF will be set. If
+ * | | |IER[RDA_IEN] is enabled, the RDA interrupt will be generated.
+ * | | |NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO
+ * | | |drops below the threshold level (RFITL).
+ * |[1] |THRE_IF |Transmit Holding Register Empty Interrupt Flag (Read Only).
+ * | | |This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If
+ * | | |IER[THRE_IEN] is enabled, the THRE interrupt will be generated.
+ * | | |NOTE: This bit is read only and it will be cleared when writing data into THR (Tx FIFO not empty).
+ * |[2] |RLS_IF |Receive Line Interrupt Flag (Read Only).
+ * | | |In UART mode this bit is set when the Rx receive data have parity error, framing error or break
+ * | | |error (at least one of 3 bits, BIF, FEF and PEF, is set). In RS-485 mode, the field includes RS-485
+ * | | |Address Byte Detection Flag. If IER[RLS_IEN] is enabled, the RLS interrupt will be generated.
+ * | | |NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS-485_Add_Det
+ * | | |are cleared.
+ * |[3] |MODEM_IF |MODEM Interrupt Flag (Read Only)
+ * | | |This bit is set when the CTS pin has state change (DCTSF=1). If IER[Modem_IEN] is enabled, the
+ * | | |Modem interrupt will be generated.
+ * | | |NOTE: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
+ * |[4] |TOUT_IF |Time Out Interrupt Flag (Read Only)
+ * | | |This bit is set when the Rx FIFO is not empty and no activities occur in the Rx FIFO and the time
+ * | | |out counter equal to TOIC. If IER [Tout_IEN] is enabled, the Tout interrupt will be generated.
+ * | | |NOTE: This bit is read only and user can read UA_RBR (Rx is in active) to clear it.
+ * |[5] |BUF_ERR_IF|Buffer Error Interrupt Flag (Read Only)
+ * | | |This bit is set when the Tx or Rx FIFO overflows (Tx_Over_IF or Rx_Over_IF is set). When
+ * | | |Buf_Err_IF is set, the transfer maybe not correct. If IER[Buf_Err_IEN] is enabled, the buffer error
+ * | | |interrupt will be generated.
+ * | | |NOTE: This bit is cleared when both Tx_Over_IF and Rx_Over_IF are cleared.
+ * |[8] |RDA_INT |Receive Data Available Interrupt Indicator to Interrupt Controller (INT_RDA).
+ * | | |An AND output with inputs of RDA_IEN and RDA_IF
+ * |[9] |THRE_INT |Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller (INT_THRE).
+ * | | |An AND output with inputs of THRE_IEN and THRE_IF
+ * |[10] |RLS_INT |Receive Line Status Interrupt Indicator to Interrupt Controller (INT_RLS).
+ * | | |An AND output with inputs of RLS_IEN and RLS_IF
+ * | | |Note: In RS-485 mode, the field includes RS-485 Address Byte Detection Flag.
+ * |[11] |MODEM_INT |MODEM Status Interrupt Indicator to Interrupt Controller (INT_MOS).
+ * | | |An AND output with inputs of Modem_IEN and Modem_IF
+ * |[12] |TOUT_INT |Time Out Interrupt Indicator to Interrupt Controller (INT_Tout)
+ * | | |An AND output with inputs of RTO_IEN and Tout_IF
+ * |[13] |BUF_ERR_INT|Buffer Error Interrupt Indicator to Interrupt Controller (INT_Buf_err)
+ * | | |An AND output with inputs of BUF_ERR_IEN and Buf_Err_IF
+ */
+ __IO uint32_t ISR;
+
+ /**
+ * TOR
+ * ===================================================================================================
+ * Offset: 0x20 UART Time Out Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |TOIC |Time Out Interrupt Comparator
+ * | | |The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO
+ * | | |receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out
+ * | | |interrupt comparator (TOIC), a receiver time out interrupt (INT_TOUT) is generated if UA_IER[RTO_IEN].
+ * | | |A new incoming data word or RX FIFO empty clears INT_TOUT.
+ * |[15:8] |DLY |TX Delay time value
+ * | | |This field is use to programming the transfer delay time between the last stop bit leaving the TX-FIFO
+ * | | |and the de-assertion of by setting UA_TOR. DLY register.
+ */
+ __IO uint32_t TOR;
+
+ /**
+ * BAUD
+ * ===================================================================================================
+ * Offset: 0x24 UART Baud Rate Divisor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |BRD_LowByte|Baud Rate Divider
+ * | | |The low byte of the baud rate divider
+ * |[15:8] |BRD_HighByte|Baud Rate Divider
+ * | | |The high byte of the baud rate divider
+ * |[27:24] |Divider_X |Divider X
+ * | | |The baud rate divider M = X+1.
+ * |[28] |DIV_X_ONE |Divider X equal 1
+ * | | |0 = Divider M = X (the equation of M = X+1, but Divider_X[27:24] must > 8)
+ * | | |1 = Divider M = 1 (the equation of M = 1, but BRD[15:0] must > 3).
+ * |[29] |DIV_X_EN |Divider X Enable
+ * | | |The BRD = Baud Rate Divider, and the baud rate equation is
+ * | | |Baud Rate = Clock / [ M * (BRD + 2) ] ; The default value of M is 16.
+ * | | |0 = Disable divider X (the equation of M = 16)
+ * | | |1 = Enable divider X (the equation of M = X+1, but Divider_X[27:24 must > 8).
+ * | | |NOTE: When in IrDA mode, this bit must disable.
+ */
+ __IO uint32_t BAUD;
+
+ /**
+ * IRCR
+ * ===================================================================================================
+ * Offset: 0x28 UART IrDA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |Tx_SELECT |Tx_SELECT
+ * | | |1: Enable IrDA transmitter
+ * | | |0: Enable IrDA receiver
+ * |[5] |INV_Tx |INV_Tx
+ * | | |1= Inverse Tx output signal
+ * | | |0= No inversion
+ * |[6] |INV_Rx |INV_Rx
+ * | | |1= Inverse Rx input signal
+ * | | |0= No inversion
+ */
+ __IO uint32_t IRCR;
+
+ /**
+ * ALT_CSR
+ * ===================================================================================================
+ * Offset: 0x2C UART Alternate Control/Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |LIN_BKFL |UART LIN Break Field Length
+ * | | |This field indicates a 4-bit LIN TX break field count.
+ * | | |Note: This break field length is UA_LIN_BKFL + 2.
+ * |[6] |LIN_RX_EN |LIN RX Enable
+ * | | |1 = Enable LIN RX mode
+ * | | |0 = Disable LIN RX mode
+ * |[7] |LIN_TX_EN |LIN TX Break Mode Enable
+ * | | |1 = Enable LIN TX Break Mode
+ * | | |0 = Disable LIN TX Break Mode
+ * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
+ * |[8] |RS485_NMM |RS-485 Normal Multi-drop Operation Mode (NMM)
+ * | | |1: Enable RS-485 Normal Multi-drop Operation Mode (NMM)
+ * | | |0: Disable RS-485 Normal Multi-drop Operation Mode (NMM)
+ * | | |Note: It can't be active with RS-485_AAD operation mode.
+ * |[9] |RS485_AAD |RS-485 Auto Address Detection Operation Mode (AAD)
+ * | | |1: Enable RS-485 Auto Address Detection Operation Mode (AAD)
+ * | | |0: Disable RS-485 Auto Address Detection Operation Mode (AAD)
+ * | | |Note: It can't be active with RS-485_NMM operation mode.
+ * |[10] |RS485_AUD |RS-485 Auto Direction Mode (AUD)
+ * | | |1: Enable RS-485 Auto Direction Mode (AUD)
+ * | | |0: Disable RS-485 Auto Direction Mode (AUD)
+ * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
+ * |[15] |RS485_ADD_EN|RS-485 Address Detection Enable
+ * | | |This bit is use to enable RS-485 address detection mode.
+ * | | |1: Enable address detection mode
+ * | | |0: Disable address detection mode
+ * | | |Note: This field is used for RS-485 any operation mode.
+ * |[31:24] |ADDR_MATCH|Address match value register
+ * | | |This field contains the RS-485 address match values.
+ * | | |Note: This field is used for RS-485 auto address detection mode.
+ */
+ __IO uint32_t ALT_CSR;
+
+ /**
+ * FUN_SEL
+ * ===================================================================================================
+ * Offset: 0x30 UART Function Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FUN_SEL |Function Select Enable
+ * | | |00 = UART Function.
+ * | | |01 = LIN Function.
+ * | | |10 = IrDA Function.
+ * | | |11 = RS-485 Function.
+ */
+ __IO uint32_t FUN_SEL;
+} UART_T;
+
+/** @addtogroup UART_CONST UART Bit Field Definition
+ Constant Definitions for UART Controller
+ @{
+ */
+
+/* UART THR Bit Field Definitions */
+#define UART_THR_THR_Pos 0 /*!< UART THR: THR Position */
+#define UART_THR_THR_Msk (0xFul << UART_THR_THR_Pos) /*!< UART THR: THR Mask */
+
+/* UART RBR Bit Field Definitions */
+#define UART_RBR_RBR_Pos 0 /*!< UART RBR: RBR Posistion */
+#define UART_RBR_RBR_Msk (0xFul << UART_RBR_RBR_Pos) /*!< UART RBR: RBR Mask */
+
+/* UART IER Bit Field Definitions */
+#define UART_IER_AUTO_CTS_EN_Pos 13 /*!< UART IER: AUTO_CTS_EN Posistion */
+#define UART_IER_AUTO_CTS_EN_Msk (1ul << UART_IER_AUTO_CTS_EN_Pos) /*!< UART IER: AUTO_CTS_EN Mask */
+
+#define UART_IER_AUTO_RTS_EN_Pos 12 /*!< UART IER: AUTO_RTS_EN Posistion */
+#define UART_IER_AUTO_RTS_EN_Msk (1ul << UART_IER_AUTO_RTS_EN_Pos) /*!< UART IER: AUTO_RTS_EN Mask */
+
+#define UART_IER_TIME_OUT_EN_Pos 11 /*!< UART IER: TIME_OUT_EN Posistion */
+#define UART_IER_TIME_OUT_EN_Msk (1ul << UART_IER_TIME_OUT_EN_Pos) /*!< UART IER: TIME_OUT_EN Mask */
+
+#define UART_IER_LIN_RX_BRK_IEN_Pos 8 /*!< UART IER: LIN_RX_BRK_IEN Posistion */
+#define UART_IER_LIN_RX_BRK_IEN_Msk (1ul << UART_IER_LIN_RX_BRK_IEN_Pos) /*!< UART IER: LIN_RX_BRK_IEN Mask */
+
+#define UART_IER_WAKE_EN_Pos 6 /*!< UART IER: WAKE_EN Posistion */
+#define UART_IER_WAKE_EN_Msk (1ul << UART_IER_WAKE_EN_Pos) /*!< UART IER: WAKE_EN Mask */
+
+#define UART_IER_BUF_ERR_IEN_Pos 5 /*!< UART IER: BUF_ERR_IEN Posistion */
+#define UART_IER_BUF_ERR_IEN_Msk (1ul << UART_IER_BUF_ERR_IEN_Pos) /*!< UART IER: BUF_ERR_IEN Mask */
+
+#define UART_IER_RTO_IEN_Pos 4 /*!< UART IER: RTO_IEN Posistion */
+#define UART_IER_RTO_IEN_Msk (1ul << UART_IER_RTO_IEN_Pos) /*!< UART IER: RTO_IEN Mask */
+
+#define UART_IER_MODEM_IEN_Pos 3 /*!< UART IER: MODEM_IEN Posistion */
+#define UART_IER_MODEM_IEN_Msk (1ul << UART_IER_MODEM_IEN_Pos) /*!< UART IER: MODEM_IEN Mask */
+
+#define UART_IER_RLS_IEN_Pos 2 /*!< UART IER: RLS_IEN Posistion */
+#define UART_IER_RLS_IEN_Msk (1ul << UART_IER_RLS_IEN_Pos) /*!< UART IER: RLS_IEN Mask */
+
+#define UART_IER_THRE_IEN_Pos 1 /*!< UART IER: THRE_IEN Posistion */
+#define UART_IER_THRE_IEN_Msk (1ul << UART_IER_THRE_IEN_Pos) /*!< UART IER: THRE_IEN Mask */
+
+#define UART_IER_RDA_IEN_Pos 0 /*!< UART IER: RDA_IEN Position */
+#define UART_IER_RDA_IEN_Msk (1ul << UART_IER_RDA_IEN_Pos) /*!< UART IER: RDA_IEN Mask */
+
+/* UART FCR Bit Field Definitions */
+#define UART_FCR_RTS_TRI_LEV_Pos 16 /*!< UART FCR: RTS_TRI_LEV Position */
+#define UART_FCR_RTS_TRI_LEV_Msk (0xFul << UART_FCR_RTS_TRI_LEV_Pos) /*!< UART FCR: RTS_TRI_LEV Mask */
+
+#define UART_FCR_RX_DIS_Pos 8 /*!< UART FCR: RX_DIS Position */
+#define UART_FCR_RX_DIS_Msk (1ul << UART_FCR_RX_DIS_Pos) /*!< UART FCR: RX_DIS Mask */
+
+#define UART_FCR_RFITL_Pos 4 /*!< UART FCR: RFITL Position */
+#define UART_FCR_RFITL_Msk (0xFul << UART_FCR_RFITL_Pos) /*!< UART FCR: RFITL Mask */
+
+#define UART_FCR_TFR_Pos 2 /*!< UART FCR: TFR Position */
+#define UART_FCR_TFR_Msk (1ul << UART_FCR_TFR_Pos) /*!< UART FCR: TFR Mask */
+
+#define UART_FCR_RFR_Pos 1 /*!< UART FCR: RFR Position */
+#define UART_FCR_RFR_Msk (1ul << UART_FCR_RFR_Pos) /*!< UART FCR: RFR Mask */
+
+/* UART LCR Bit Field Definitions */
+#define UART_LCR_BCB_Pos 6 /*!< UART LCR: BCB Position */
+#define UART_LCR_BCB_Msk (1ul << UART_LCR_BCB_Pos) /*!< UART LCR: BCB Mask */
+
+#define UART_LCR_SPE_Pos 5 /*!< UART LCR: SPE Position */
+#define UART_LCR_SPE_Msk (1ul << UART_LCR_SPE_Pos) /*!< UART LCR: SPE Mask */
+
+#define UART_LCR_EPE_Pos 4 /*!< UART LCR: EPE Position */
+#define UART_LCR_EPE_Msk (1ul << UART_LCR_EPE_Pos) /*!< UART LCR: EPE Mask */
+
+#define UART_LCR_PBE_Pos 3 /*!< UART LCR: PBE Position */
+#define UART_LCR_PBE_Msk (1ul << UART_LCR_PBE_Pos) /*!< UART LCR: PBE Mask */
+
+#define UART_LCR_NSB_Pos 2 /*!< UART LCR: NSB Position */
+#define UART_LCR_NSB_Msk (1ul << UART_LCR_NSB_Pos) /*!< UART LCR: NSB Mask */
+
+#define UART_LCR_WLS_Pos 0 /*!< UART LCR: WLS Position */
+#define UART_LCR_WLS_Msk (0x3ul << UART_LCR_WLS_Pos) /*!< UART LCR: WLS Mask */
+
+/* UART MCR Bit Field Definitions */
+#define UART_MCR_RTS_ST_Pos 13 /*!< UART MCR: RTS_ST Position */
+#define UART_MCR_RTS_ST_Msk (1ul << UART_MCR_RTS_ST_Pos) /*!< UART MCR: RTS_ST Mask */
+
+#define UART_MCR_LEV_RTS_Pos 9 /*!< UART MCR: LEV_RTS Position */
+#define UART_MCR_LEV_RTS_Msk (1ul << UART_MCR_LEV_RTS_Pos) /*!< UART MCR: LEV_RTS Mask */
+
+#define UART_MCR_RTS_Pos 1 /*!< UART MCR: RTS Position */
+#define UART_MCR_RTS_Msk (1ul << UART_MCR_RTS_Pos) /*!< UART MCR: RTS Mask */
+
+/* UART MSR Bit Field Definitions */
+#define UART_MSR_LEV_CTS_Pos 8 /*!< UART MSR: LEV_CTS Position */
+#define UART_MSR_LEV_CTS_Msk (1ul << UART_MSR_LEV_CTS_Pos) /*!< UART MSR: LEV_CTS Mask */
+
+#define UART_MSR_CTS_ST_Pos 4 /*!< UART MSR: CTS_ST Position */
+#define UART_MSR_CTS_ST_Msk (1ul << UART_MSR_CTS_ST_Pos) /*!< UART MSR: CTS_ST Mask */
+
+#define UART_MSR_DCTSF_Pos 0 /*!< UART MSR: DCTST Position */
+#define UART_MSR_DCTSF_Msk (1ul << UART_MSR_DCTSF_Pos) /*!< UART MSR: DCTST Mask */
+
+/* UART FSR Bit Field Definitions */
+#define UART_FSR_TE_FLAG_Pos 28 /*!< UART FSR: TE_FLAG Position */
+#define UART_FSR_TE_FLAG_Msk (1ul << UART_FSR_TE_FLAG_Pos) /*!< UART FSR: TE_FLAG Mask */
+
+#define UART_FSR_TX_OVER_IF_Pos 24 /*!< UART FSR: TX_OVER_IF Position */
+#define UART_FSR_TX_OVER_IF_Msk (1ul << UART_FSR_TX_OVER_IF_Pos) /*!< UART FSR: TX_OVER_IF Mask */
+
+#define UART_FSR_TX_FULL_Pos 23 /*!< UART FSR: TX_FULL Position */
+#define UART_FSR_TX_FULL_Msk (1ul << UART_FSR_TX_FULL_Pos) /*!< UART FSR: TX_FULL Mask */
+
+#define UART_FSR_TX_EMPTY_Pos 22 /*!< UART FSR: TX_EMPTY Position */
+#define UART_FSR_TX_EMPTY_Msk (1ul << UART_FSR_TX_EMPTY_Pos) /*!< UART FSR: TX_EMPTY Mask */
+
+#define UART_FSR_TX_POINTER_Pos 16 /*!< UART FSR: TX_POINTER Position */
+#define UART_FSR_TX_POINTER_Msk (0x3Ful << UART_FSR_TX_POINTER_Pos) /*!< UART FSR: TX_POINTER Mask */
+
+#define UART_FSR_RX_FULL_Pos 15 /*!< UART FSR: RX_FULL Position */
+#define UART_FSR_RX_FULL_Msk (1ul << UART_FSR_RX_FULL_Pos) /*!< UART FSR: RX_FULL Mask */
+
+#define UART_FSR_RX_EMPTY_Pos 14 /*!< UART FSR: RX_EMPTY Position */
+#define UART_FSR_RX_EMPTY_Msk (1ul << UART_FSR_RX_EMPTY_Pos) /*!< UART FSR: RX_EMPTY Mask */
+
+#define UART_FSR_RX_POINTER_Pos 8 /*!< UART FSR: RX_POINTERS Position */
+#define UART_FSR_RX_POINTER_Msk (0x3Ful << UART_FSR_RX_POINTER_Pos) /*!< UART FSR: RX_POINTER Mask */
+
+#define UART_FSR_BIF_Pos 6 /*!< UART FSR: BIF Position */
+#define UART_FSR_BIF_Msk (1ul << UART_FSR_BIF_Pos) /*!< UART FSR: BIF Mask */
+
+#define UART_FSR_FEF_Pos 5 /*!< UART FSR: FEF Position */
+#define UART_FSR_FEF_Msk (1ul << UART_FSR_FEF_Pos) /*!< UART FSR: FEF Mask */
+
+#define UART_FSR_PEF_Pos 4 /*!< UART FSR: PEF Position */
+#define UART_FSR_PEF_Msk (1ul << UART_FSR_PEF_Pos) /*!< UART FSR: PEF Mask */
+
+#define UART_FSR_RS485_ADD_DETF_Pos 3 /*!< UART FSR: RS485_ADD_DETF Position */
+#define UART_FSR_RS485_ADD_DETF_Msk (1ul << UART_FSR_RS485_ADD_DETF_Pos) /*!< UART FSR: RS485_ADD_DETF Mask */
+
+#define UART_FSR_RX_OVER_IF_Pos 0 /*!< UART FSR: RX_OVER_IF Position */
+#define UART_FSR_RX_OVER_IF_Msk (1ul << UART_FSR_RX_OVER_IF_Pos) /*!< UART FSR: RX_OVER_IF Mask */
+
+/* UART ISR Bit Field Definitions */
+#define UART_ISR_LIN_RX_BREAK_INT_Pos 15 /*!< UART ISR: LIN_RX_BREAK_INT Position */
+#define UART_ISR_LIN_RX_BREAK_INT_Msk (1ul << UART_ISR_LIN_RX_BREAK_INT_Pos) /*!< UART ISR: LIN_RX_BREAK_INT Mask */
+
+#define UART_ISR_BUF_ERR_INT_Pos 13 /*!< UART ISR: BUF_ERR_INT Position */
+#define UART_ISR_BUF_ERR_INT_Msk (1ul << UART_ISR_BUF_ERR_INT_Pos) /*!< UART ISR: BUF_ERR_INT Mask */
+
+#define UART_ISR_TOUT_INT_Pos 12 /*!< UART ISR: TOUT_INT Position */
+#define UART_ISR_TOUT_INT_Msk (1ul << UART_ISR_TOUT_INT_Pos) /*!< UART ISR: TOUT_INT Mask */
+
+#define UART_ISR_MODEM_INT_Pos 11 /*!< UART ISR: MODEM_INT Position */
+#define UART_ISR_MODEM_INT_Msk (1ul << UART_ISR_MODEM_INT_Pos) /*!< UART ISR: MODEM_INT Mask */
+
+#define UART_ISR_RLS_INT_Pos 10 /*!< UART ISR: RLS_INT Position */
+#define UART_ISR_RLS_INT_Msk (1ul << UART_ISR_RLS_INT_Pos) /*!< UART ISR: RLS_INT Mask */
+
+#define UART_ISR_THRE_INT_Pos 9 /*!< UART ISR: THRE_INT Position */
+#define UART_ISR_THRE_INT_Msk (1ul << UART_ISR_THRE_INT_Pos) /*!< UART ISR: THRE_INT Mask */
+
+#define UART_ISR_RDA_INT_Pos 8 /*!< UART ISR: RDA_INT Position */
+#define UART_ISR_RDA_INT_Msk (1ul << UART_ISR_RDA_INT_Pos) /*!< UART ISR: RDA_INT Mask */
+
+#define UART_ISR_LIN_RX_BREAK_IF_Pos 7 /*!< UART ISR: LIN RX BREAK IF Position */
+#define UART_ISR_LIN_RX_BREAK_IF_Msk (1ul << UART_ISR_LIN_RX_BREAK_IF_Pos) /*!< UART ISR: LIN RX BREAK IF Mask */
+
+#define UART_ISR_BUF_ERR_IF_Pos 5 /*!< UART ISR: BUF_ERR_IF Position */
+#define UART_ISR_BUF_ERR_IF_Msk (1ul << UART_ISR_BUF_ERR_IF_Pos) /*!< UART ISR: BUF_ERR_IF Mask */
+
+#define UART_ISR_TOUT_IF_Pos 4 /*!< UART ISR: TOUT_IF Position */
+#define UART_ISR_TOUT_IF_Msk (1ul << UART_ISR_TOUT_IF_Pos) /*!< UART ISR: TOUT_IF Mask */
+
+#define UART_ISR_MODEM_IF_Pos 3 /*!< UART ISR: MODEM_IF Position */
+#define UART_ISR_MODEM_IF_Msk (1ul << UART_ISR_MODEM_IF_Pos) /*!< UART ISR: MODEM_IF Mask */
+
+#define UART_ISR_RLS_IF_Pos 2 /*!< UART ISR: RLS_IF Position */
+#define UART_ISR_RLS_IF_Msk (1ul << UART_ISR_RLS_IF_Pos) /*!< UART ISR: RLS_IF Mask */
+
+#define UART_ISR_THRE_IF_Pos 1 /*!< UART ISR: THRE_IF Position */
+#define UART_ISR_THRE_IF_Msk (1ul << UART_ISR_THRE_IF_Pos) /*!< UART ISR: THRE_IF Mask */
+
+#define UART_ISR_RDA_IF_Pos 0 /*!< UART ISR: RDA_IF Position */
+#define UART_ISR_RDA_IF_Msk (1ul << UART_ISR_RDA_IF_Pos) /*!< UART ISR: RDA_IF Mask */
+
+/* UART TOR Bit Field Definitions */
+#define UART_TOR_DLY_Pos 8 /*!< UART TOR: DLY Position */
+#define UART_TOR_DLY_Msk (0xFFul << UART_TOR_DLY_Pos) /*!< UART TOR: DLY Mask */
+
+#define UART_TOR_TOIC_Pos 0 /*!< UART TOR: TOIC Position */
+#define UART_TOR_TOIC_Msk (0xFFul << UART_TOR_TOIC_Pos) /*!< UART TOR: TOIC Mask */
+
+/* UART BAUD Bit Field Definitions */
+#define UART_BAUD_DIV_X_EN_Pos 29 /*!< UART BARD: DIV_X_EN Position */
+#define UART_BAUD_DIV_X_EN_Msk (1ul << UART_BAUD_DIV_X_EN_Pos) /*!< UART BARD: DIV_X_EN Mask */
+
+#define UART_BAUD_DIV_X_ONE_Pos 28 /*!< UART BARD: DIV_X_ONE Position */
+#define UART_BAUD_DIV_X_ONE_Msk (1ul << UART_BAUD_DIV_X_ONE_Pos) /*!< UART BARD: DIV_X_ONE Mask */
+
+#define UART_BAUD_DIVIDER_X_Pos 24 /*!< UART BARD: DIVIDER_X Position */
+#define UART_BAUD_DIVIDER_X_Msk (0xFul << UART_BAUD_DIVIDER_X_Pos) /*!< UART BARD: DIVIDER_X Mask */
+
+#define UART_BAUD_BRD_Pos 0 /*!< UART BARD: BRD Position */
+#define UART_BAUD_BRD_Msk (0xFFFFul << UART_BAUD_BRD_Pos) /*!< UART BARD: BRD Mask */
+
+/* UART IRCR Bit Field Definitions */
+#define UART_IRCR_INV_RX_Pos 6 /*!< UART IRCR: INV_RX Position */
+#define UART_IRCR_INV_RX_Msk (1ul << UART_IRCR_INV_RX_Pos) /*!< UART IRCR: INV_RX Mask */
+
+#define UART_IRCR_INV_TX_Pos 5 /*!< UART IRCR: INV_TX Position */
+#define UART_IRCR_INV_TX_Msk (1ul << UART_IRCR_INV_TX_Pos) /*!< UART IRCR: INV_TX Mask */
+
+#define UART_IRCR_TX_SELECT_Pos 1 /*!< UART IRCR: TX_SELECT Position */
+#define UART_IRCR_TX_SELECT_Msk (1ul << UART_IRCR_TX_SELECT_Pos) /*!< UART IRCR: TX_SELECT Mask */
+
+/* UART ALT_CSR Bit Field Definitions */
+#define UART_ALT_CSR_ADDR_MATCH_Pos 24 /*!< UART ALT_CSR: ADDR_MATCH Position */
+#define UART_ALT_CSR_ADDR_MATCH_Msk (0xFFul << UART_ALT_CSR_ADDR_MATCH_Pos) /*!< UART ALT_CSR: ADDR_MATCH Mask */
+
+#define UART_ALT_CSR_RS485_ADD_EN_Pos 15 /*!< UART ALT_CSR: RS485_ADD_EN Position */
+#define UART_ALT_CSR_RS485_ADD_EN_Msk (1ul << UART_ALT_CSR_RS485_ADD_EN_Pos) /*!< UART ALT_CSR: RS485_ADD_EN Mask */
+
+#define UART_ALT_CSR_RS485_AUD_Pos 10 /*!< UART ALT_CSR: RS485_AUD Position */
+#define UART_ALT_CSR_RS485_AUD_Msk (1ul << UART_ALT_CSR_RS485_AUD_Pos) /*!< UART ALT_CSR: RS485_AUD Mask */
+
+#define UART_ALT_CSR_RS485_AAD_Pos 9 /*!< UART ALT_CSR: RS485_AAD Position */
+#define UART_ALT_CSR_RS485_AAD_Msk (1ul << UART_ALT_CSR_RS485_AAD_Pos) /*!< UART ALT_CSR: RS485_AAD Mask */
+
+#define UART_ALT_CSR_RS485_NMM_Pos 8 /*!< UART ALT_CSR: RS485_NMM Position */
+#define UART_ALT_CSR_RS485_NMM_Msk (1ul << UART_ALT_CSR_RS485_NMM_Pos) /*!< UART ALT_CSR: RS485_NMM Mask */
+
+#define UART_ALT_CSR_LIN_TX_EN_Pos 7 /*!< UART ALT_CSR: LIN TX Break Mode Enable Position */
+#define UART_ALT_CSR_LIN_TX_EN_Msk (1ul << UART_ALT_CSR_LIN_TX_EN_Pos) /*!< UART ALT_CSR: LIN TX Break Mode Enable Mask */
+
+#define UART_ALT_CSR_LIN_RX_EN_Pos 6 /*!< UART ALT_CSR: LIN RX Enable Position */
+#define UART_ALT_CSR_LIN_RX_EN_Msk (1ul << UART_ALT_CSR_LIN_RX_EN_Pos) /*!< UART ALT_CSR: LIN RX Enable Mask */
+
+#define UART_ALT_CSR_UA_LIN_BKFL_Pos 0 /*!< UART ALT_CSR: UART LIN Break Field Length Position */
+#define UART_ALT_CSR_UA_LIN_BKFL_Msk (0xFul << UART_ALT_CSR_UA_LIN_BKFL_Pos) /*!< UART ALT_CSR: UART LIN Break Field Length Mask */
+
+/* UART FUN_SEL Bit Field Definitions */
+#define UART_FUN_SEL_FUN_SEL_Pos 0 /*!< UART FUN_SEL: FUN_SEL Position */
+#define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART FUN_SEL: FUN_SEL Mask */
+/**@}*/ /* UART_CONST */
+/**@}*/ /* UART */
+
+
+
+/*----------------------------- WDT Controller -----------------------------*/
+/** @addtogroup WDT WDT Controller(WDT)
+ Memory Mapped Structure for Watchdog Timer
+ @{
+ */
+typedef struct
+{
+ /**
+ * WTCR
+ * ===================================================================================================
+ * Offset: 0x00 Watchdog Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WTR |Clear Watchdog Timer
+ * | | |Set this bit will clear the Watchdog timer.
+ * | | |0= Writing 0 to this bit has no effect
+ * | | |1= Reset the contents of the Watchdog timer
+ * | | |NOTE: This bit will auto clear after few clock cycle
+ * |[1] |WTRE |Watchdog Timer Reset Enable
+ * | | |Setting this bit will enable the Watchdog timer reset function.
+ * | | |0= Disable Watchdog timer reset function
+ * | | |1= Enable Watchdog timer reset function
+ * |[2] |WTRF |Watchdog Timer Reset Flag
+ * | | |When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by
+ * | | |software to determine the source of reset. Software is responsible to clear it manually by writing 1 to
+ * | | |it. If WTRE is disabled, then the Watchdog timer has no effect on this bit.
+ * | | |0= Watchdog timer reset does not occur
+ * | | |1= Watchdog timer reset occurs
+ * | | |NOTE: This bit is cleared by writing 1 to this bit.
+ * |[3] |WTIF |Watchdog Timer Interrupt Flag
+ * | | |If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the
+ * | | |Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit
+ * | | |indicates that a timeout period has elapsed.
+ * | | |0= Watchdog timer interrupt does not occur
+ * | | |1= Watchdog timer interrupt occurs
+ * | | |NOTE: Write 1 to clear this bit to zero.
+ * |[4] |WTWKE |Watchdog Timer Wakeup Function Enable bit
+ * | | |0 = Disable Watchdog timer Wakeup CPU function.
+ * | | |1 = Enable the Wakeup function that Watchdog timer timeout can wake up CPU from power-down
+ * | | |mode.
+ * |[5] |WTWKF |Watchdog Timer Wakeup Flag
+ * | | |If Watchdog timer causes CPU wakes up from power-down mode, this bit will be set to high. It must
+ * | | |be cleared by software with a write 1 to this bit.
+ * | | |1 = CPU wake up from sleep or power-down mode by Watchdog timeout.
+ * | | |0 = Watchdog timer does not cause CPU wakeup.
+ * | | |NOTE: Write 1 to clear this bit to zero.
+ * |[6] |WTIE |Watchdog Timer Interrupt Enable
+ * | | |0= Disable the Watchdog timer interrupt
+ * | | |1= Enable the Watchdog timer interrupt
+ * |[7] |WTE |Watchdog Timer Enable
+ * | | |0= Disable the Watchdog timer (This action will reset the internal counter)
+ * | | |1= Enable the Watchdog timer
+ * |[10:8] |WTIS |Watchdog Timer Interval Select (write protection bit)
+ * | | |These three bits select the timeout interval for the Watchdog timer.
+ */
+ __IO uint32_t WTCR;
+
+ /**
+ * WTCRALT
+ * ===================================================================================================
+ * Offset: 0x04 Watchdog Timer Alternative Control Register
+ * ---------------------------------------------------------------------------------------------------
+ */
+ __IO uint32_t WTCRALT;
+} WDT_T;
+
+/** @addtogroup WDT_CONST WDT Bit Field Definition
+ Constant Definitions for WDT Controller
+ @{
+ */
+
+/* WDT WTCR Bit Field Definitions */
+#define WDT_WTCR_DBGACK_WDT_Pos 31 /*!< WDT WTCR : DBGACK_WDT Position */
+#define WDT_WTCR_DBGACK_WDT_Msk (1ul << WDT_WTCR_DBGACK_WDT_Pos) /*!< WDT WTCR : DBGACK_WDT Mask */
+
+#define WDT_WTCR_WTIS_Pos 8 /*!< WDT WTCR : WTIS Position */
+#define WDT_WTCR_WTIS_Msk (0x7ul << WDT_WTCR_WTIS_Pos) /*!< WDT WTCR : WTIS Mask */
+
+#define WDT_WTCR_WTE_Pos 7 /*!< WDT WTCR : WTE Position */
+#define WDT_WTCR_WTE_Msk (1ul << WDT_WTCR_WTE_Pos) /*!< WDT WTCR : WTE Mask */
+
+#define WDT_WTCR_WTIE_Pos 6 /*!< WDT WTCR : WTIE Position */
+#define WDT_WTCR_WTIE_Msk (1ul << WDT_WTCR_WTIE_Pos) /*!< WDT WTCR : WTIE Mask */
+
+#define WDT_WTCR_WTWKF_Pos 5 /*!< WDT WTCR : WTWKF Position */
+#define WDT_WTCR_WTWKF_Msk (1ul << WDT_WTCR_WTWKF_Pos) /*!< WDT WTCR : WTWKF Mask */
+
+#define WDT_WTCR_WTWKE_Pos 4 /*!< WDT WTCR : WTWKE Position */
+#define WDT_WTCR_WTWKE_Msk (1ul << WDT_WTCR_WTWKE_Pos) /*!< WDT WTCR : WTWKE Mask */
+
+#define WDT_WTCR_WTIF_Pos 3 /*!< WDT WTCR : WTIF Position */
+#define WDT_WTCR_WTIF_Msk (1ul << WDT_WTCR_WTIF_Pos) /*!< WDT WTCR : WTIF Mask */
+
+#define WDT_WTCR_WTRF_Pos 2 /*!< WDT WTCR : WTRF Position */
+#define WDT_WTCR_WTRF_Msk (1ul << WDT_WTCR_WTRF_Pos) /*!< WDT WTCR : WTRF Mask */
+
+#define WDT_WTCR_WTRE_Pos 1 /*!< WDT WTCR : WTRE Position */
+#define WDT_WTCR_WTRE_Msk (1ul << WDT_WTCR_WTRE_Pos) /*!< WDT WTCR : WTRE Mask */
+
+#define WDT_WTCR_WTR_Pos 0 /*!< WDT WTCR : WTR Position */
+#define WDT_WTCR_WTR_Msk (1ul << WDT_WTCR_WTR_Pos) /*!< WDT WTCR : WTR Mask */
+
+/* WDT WTCRALT Bit Field Definitions */
+#define WDT_WTCRALT_WTRDSEL_Pos 0 /*!< WDT WTCRALT : WTRDSEL Position */
+#define WDT_WTCRALT_WTRDSEL_Msk (0x3ul << WDT_WTCRALT_WTRDSEL_Pos) /*!< WDT WTCRALT : WTRDSEL Mask */
+/**@}*/ /* WDT_CONST */
+/**@}*/ /* WDT */
+
+
+/*----------------------------- WWDT Controller -----------------------------*/
+/** @addtogroup WWDT Window Watchdog Timer (WWDT)
+ Register data structure of Window Watchdog Timer and relative constant definitions.
+ @{
+ */
+typedef struct
+{
+ /**
+ * WWDTRLD
+ * ===================================================================================================
+ * WWDT Reload Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |WWDTRLD |WWDT Reload Counter Register
+ * | | |Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.
+ * | | |Note: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP.
+ * | | |If software writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
+ */
+ __IO uint32_t WWDTRLD;
+
+ /**
+ * WWDTCR
+ * ===================================================================================================
+ * Offset: 0x04 Window Watchdog Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WWDTEN |WWDT Enable
+ * | | |Set this bit to enable Window Watchdog Timer counter counting.
+ * | | |0 = Window Watchdog Timer counter is stopped.
+ * | | |1 = Window Watchdog Timer counter is starting counting.
+ * |[1] |WWDTIE |WWDT Interrupt Enable
+ * | | |Setting this bit to enable the Window Watchdog Timer time-out interrupt function.
+ * | | |0 = WWDT time-out interrupt function Disabled if WWDTIF (WWDTSR[0] WWDT compare match interrupt flag) is 1.
+ * | | |1 = WWDT time-out interrupt function Enabled if WWDTIF (WWDTSR[0] WWDT compare match interrupt flag) is 1.
+ * |[11:8] |PERIODSEL |WWDT Pre-scale Period Select
+ * | | |These 4-bit select the pre-scale period for the WWDT counter period.
+ * | | |PERIODSEL Pre-scale Value Time out Period Max. Time out Interval (WWDT_CLK=10 kHz)
+ * | | |Timeout period = Pre-scale * 64 * WWDT_CLK.
+ * | | |PERIODSEL={0,1,2,3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}
+ * | | |Pre-scale={1,2,4,8,16,32,64,128,192,256,384,512,768,1024,1536,2048}
+ * |[21:16] |WINCMP |WWDT Window Compare Register
+ * | | |Set this register to adjust the valid reload window.
+ * | | |Note: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP.
+ * | | |If Software writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
+ * |[31] |DBGACK_WWDT|ICE debug mode acknowledge Disable
+ * | | |0 = WWDT counter stopped if system is in Debug mode.
+ * | | |1 = WWDT still counted even system is in Debug mode.
+ */
+ __IO uint32_t WWDTCR;
+
+ /**
+ * WWDTSR
+ * ===================================================================================================
+ * Offset: 0x08 Window Watchdog Timer Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
+ * | | |When current WWDT counter value matches to WWCMP, this bit is set to 1. This bit will be cleared by writing 1 to itself.
+ * |[1] |WWDTRF |WWDT Reset Flag
+ * | | |When WWDT counter counts down to 0 or writes WWDTRLD during current WWDT counter value larger than WINCMP,
+ * | | |chip will be reset and this bit is set to 1. This bit will be cleared to 0 by writing 1 to itself.
+ */
+ __IO uint32_t WWDTSR;
+
+ /**
+ * WWDTCVR
+ * ===================================================================================================
+ * Offset: 0x0C Watchdog Timer Alternative Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |WWDTCVAL |WWDT Counter Value
+ * | | |This register reflects the current WWDT counter value and this register is read only.
+ */
+ __IO uint32_t WWDTCVR;
+
+} WWDT_T;
+
+/** @addtogroup WWDT_CONST WWDT Bit Field Definition
+ Constant Definitions for WWDT Controller
+ @{
+ */
+
+/* WWDT WWDTRLD Bit Field Definitions */
+#define WWDT_WWDTRLD_WWDTRLD_Pos 0 /*!< WWDT WWDTRLD : WWDTRLD Position */
+#define WWDT_WWDTRLD_WWDTRLD_Msk (0xFFFFFFFFul << WWDT_WWDTRLD_WWDTRLD_Pos) /*!< WWDT WWDTRLD : WWDTRLD Mask */
+
+/* WWDT WWDTCR Bit Field Definitions */
+#define WWDT_WWDTCR_DBGACK_WWDT_Pos 31 /*!< WWDT WWDTCR : DBGACK_WWDT Position */
+#define WWDT_WWDTCR_DBGACK_WWDT_Msk (1ul << WWDT_WWDTCR_DBGACK_WWDT_Pos) /*!< WWDT WWDTCR : DBGACK_WWDT Mask */
+
+#define WWDT_WWDTCR_WINCMP_Pos 16 /*!< WWDT WWDTCR : WINCMP Position */
+#define WWDT_WWDTCR_WINCMP_Msk (0x3Ful << WWDT_WWDTCR_WINCMP_Pos) /*!< WWDT WWDTCR : WINCMP Mask */
+
+#define WWDT_WWDTCR_PERIODSEL_Pos 8 /*!< WWDT WWDTCR : PERIODSEL Position */
+#define WWDT_WWDTCR_PERIODSEL_Msk (0xFul << WWDT_WWDTCR_PERIODSEL_Pos) /*!< WWDT WWDTCR : PERIODSEL Mask */
+
+#define WWDT_WWDTCR_WWDTIE_Pos 1 /*!< WWDT WWDTCR : WWDTIE Position */
+#define WWDT_WWDTCR_WWDTIE_Msk (1ul << WWDT_WWDTCR_WWDTIE_Pos) /*!< WWDT WWDTCR : WWDTIE Mask */
+
+#define WWDT_WWDTCR_WWDTEN_Pos 0 /*!< WWDT WWDTCR : WWDTEN Position */
+#define WWDT_WWDTCR_WWDTEN_Msk (1ul << WWDT_WWDTCR_WWDTEN_Pos) /*!< WWDT WWDTCR : WWDTEN Mask */
+
+/* WWDT WWDTSR Bit Field Definitions */
+#define WWDT_WWDTSR_WWDTRF_Pos 1 /*!< WWDT WWDTSR : WWDTRF Position */
+#define WWDT_WWDTSR_WWDTRF_Msk (1ul << WWDT_WWDTSR_WWDTRF_Pos) /*!< WWDT WWDTSR : WWDTRF Mask */
+
+#define WWDT_WWDTSR_WWDTIF_Pos 0 /*!< WWDT WWDTSR : WWDTIF Position */
+#define WWDT_WWDTSR_WWDTIF_Msk (1ul << WWDT_WWDTSR_WWDTIF_Pos) /*!< WWDT WWDTSR : WWDTIF Mask */
+
+/* WWDT WWDTCVR Bit Field Definitions */
+#define WWDT_WWDTCVR_WWDTCVAL_Pos 0 /*!< WWDT WWDTCVR : WWDTRF Position */
+#define WWDT_WWDTCVR_WWDTCVAL_Msk (0x3Ful << WWDT_WWDTCVR_WWDTCVAL_Pos) /*!< WWDT WWDTCVR : WWDTRF Mask */
+/**@}*/ /* end of group WWDT_CONST */
+/**@}*/ /* end of group WWDT */
+/**@}*/ /* end of group REGISTER */
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base
+ Memory Mapped Structure for Series Peripheral
+ @{
+ */
+/* Peripheral and SRAM base address */
+#define FLASH_BASE (( uint32_t)0x00000000)
+#define SRAM_BASE (( uint32_t)0x20000000)
+#define AHB_BASE (( uint32_t)0x50000000)
+#define APB1_BASE (( uint32_t)0x40000000)
+#define APB2_BASE (( uint32_t)0x40100000)
+
+/* Peripheral memory map */
+#define GPIO_BASE (AHB_BASE + 0x4000) /*!< GPIO Base Address */
+#define P0_BASE (GPIO_BASE ) /*!< GPIO P0 Base Address */
+#define P1_BASE (GPIO_BASE + 0x0040) /*!< GPIO P1 Base Address */
+#define P2_BASE (GPIO_BASE + 0x0080) /*!< GPIO P2 Base Address */
+#define P3_BASE (GPIO_BASE + 0x00C0) /*!< GPIO P3 Base Address */
+#define P4_BASE (GPIO_BASE + 0x0100) /*!< GPIO P4 Base Address */
+#define GPIO_DBNCECON_BASE (GPIO_BASE + 0x0180) /*!< GPIO De-bounce Cycle Control Base Address */
+#define GPIO_PIN_DATA_BASE (GPIO_BASE + 0x0200) /*!< GPIO Pin Data Input/Output Control Base Address */
+
+#define UART0_BASE (APB1_BASE + 0x50000) /*!< UART0 Base Address */
+#define UART1_BASE (APB2_BASE + 0x50000) /*!< UART1 Base Address */
+
+#define TIMER0_BASE (APB1_BASE + 0x10000) /*!< Timer0 Base Address */
+#define TIMER1_BASE (APB1_BASE + 0x10020) /*!< Timer1 Base Address */
+#define TIMER2_BASE (APB2_BASE + 0x10000) /*!< Timer2 Base Address */
+#define TIMER3_BASE (APB2_BASE + 0x10020) /*!< Timer3 Base Address */
+
+#define WDT_BASE (APB1_BASE + 0x4000) /*!< Watch Dog Timer Base Address */
+
+#define WWDT_BASE (APB1_BASE + 0x4100) /*!< Window Watch Dog Timer Base Address */
+
+#define SPI0_BASE (APB1_BASE + 0x30000) /*!< SPI0 Base Address */
+#define SPI1_BASE (APB1_BASE + 0x34000) /*!< SPI1 Base Address */
+
+#define I2C0_BASE (APB1_BASE + 0x20000) /*!< I2C0 Base Address */
+#define I2C1_BASE (APB2_BASE + 0x20000) /*!< I2C1 Base Address */
+
+#define RTC_BASE (APB1_BASE + 0x08000) /*!< RTC Base Address */
+
+#define ADC_BASE (APB1_BASE + 0xE0000) /*!< ADC Base Address */
+
+#define ACMP01_BASE (APB1_BASE + 0xD0000) /*!< ACMP01 Base Address */
+#define ACMP23_BASE (APB2_BASE + 0xD0000) /*!< ACMP23 Base Address */
+
+#define CLK_BASE (AHB_BASE + 0x00200) /*!< System Clock Controller Base Address */
+
+#define GCR_BASE (AHB_BASE + 0x00000) /*!< System Global Controller Base Address */
+
+#define INT_BASE (AHB_BASE + 0x00300) /*!< Interrupt Source Controller Base Address */
+
+#define FMC_BASE (AHB_BASE + 0x0C000) /*!< Flash Memory Controller Base Address */
+
+#define PWMA_BASE (APB1_BASE + 0x40000) /*!< PWMA Base Address */
+#define PWMB_BASE (APB2_BASE + 0x40000) /*!< PWMB Base Address */
+
+#define EBI_BASE (AHB_BASE + 0x10000) /*!< EBI Base Address */
+
+#define HDIV_BASE (AHB_BASE + 0x14000) /*!< HDIV Base Address */
+
+/**@}*/ /* PERIPHERAL */
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+/** @addtogroup PMODULE Peripheral Pointer
+ The Declaration of Peripheral Pointer
+ @{
+ */
+#define P0 ((GPIO_T *) P0_BASE) /*!< GPIO PORT0 Configuration Struct */
+#define P1 ((GPIO_T *) P1_BASE) /*!< GPIO PORT1 Configuration Struct */
+#define P2 ((GPIO_T *) P2_BASE) /*!< GPIO PORT2 Configuration Struct */
+#define P3 ((GPIO_T *) P3_BASE) /*!< GPIO PORT3 Configuration Struct */
+#define P4 ((GPIO_T *) P4_BASE) /*!< GPIO PORT4 Configuration Struct */
+#define GPIO ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE) /*!< Interrupt De-bounce Cycle Control Configuration Struct */
+
+#define UART0 ((UART_T *) UART0_BASE) /*!< UART0 Configuration Struct */
+#define UART1 ((UART_T *) UART1_BASE) /*!< UART1 Configuration Struct */
+
+#define TIMER0 ((TIMER_T *) TIMER0_BASE) /*!< TIMER0 Configuration Struct */
+#define TIMER1 ((TIMER_T *) TIMER1_BASE) /*!< TIMER1 Configuration Struct */
+#define TIMER2 ((TIMER_T *) TIMER2_BASE) /*!< TIMER2 Configuration Struct */
+#define TIMER3 ((TIMER_T *) TIMER3_BASE) /*!< TIMER3 Configuration Struct */
+
+#define WDT ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Configuration Struct */
+
+#define WWDT ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Configuration Struct */
+
+#define SPI0 ((SPI_T *) SPI0_BASE) /*!< SPI0 Configuration Struct */
+#define SPI1 ((SPI_T *) SPI1_BASE) /*!< SPI1 Configuration Struct */
+
+#define I2C0 ((I2C_T *) I2C0_BASE) /*!< I2C0 Configuration Struct */
+#define I2C1 ((I2C_T *) I2C1_BASE) /*!< I2C1 Configuration Struct */
+
+#define ADC ((ADC_T *) ADC_BASE) /*!< ADC Configuration Struct */
+
+#define ACMP01 ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Configuration Struct */
+#define ACMP23 ((ACMP_T *) ACMP23_BASE) /*!< ACMP23 Configuration Struct */
+
+#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Configuration Struct */
+
+#define SYS ((GCR_T *) GCR_BASE) /*!< System Global Controller Configuration Struct */
+
+#define SYSINT ((GCR_INT_T *) INT_BASE) /*!< Interrupt Source Controller Configuration Struct */
+
+#define FMC ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */
+
+#define PWMA ((PWM_T *) PWMA_BASE) /*!< PWMA Configuration Struct */
+#define PWMB ((PWM_T *) PWMB_BASE) /*!< PWMB Configuration Struct */
+
+#define EBI ((EBI_T *) EBI_BASE) /*!< EBI Configuration Struct */
+
+#define HDIV ((HDIV_T *) HDIV_BASE) /*!< HDIV Configuration Struct */
+
+/**@}*/ /* end of group PMODULE */
+
+
+//=============================================================================
+typedef volatile unsigned char vu8;
+typedef volatile unsigned long vu32;
+typedef volatile unsigned short vu16;
+#define M8(adr) (*((vu8 *) (adr)))
+#define M16(adr) (*((vu16 *) (adr)))
+#define M32(adr) (*((vu32 *) (adr)))
+
+#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
+#define inpw(port) ((*((volatile unsigned int *)(port))))
+#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
+#define inpb(port) ((*((volatile unsigned char *)(port))))
+#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
+#define inps(port) ((*((volatile unsigned short *)(port))))
+
+#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
+#define inp32(port) ((*((volatile unsigned int *)(port))))
+#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
+#define inp8(port) ((*((volatile unsigned char *)(port))))
+#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
+#define inp16(port) ((*((volatile unsigned short *)(port))))
+
+
+#define E_SUCCESS 0
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define TRUE 1
+#define FALSE 0
+
+#define ENABLE 1
+#define DISABLE 0
+
+/* Bit Mask Definitions */
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk (0x000000FF)
+#define BYTE1_Msk (0x0000FF00)
+#define BYTE2_Msk (0x00FF0000)
+#define BYTE3_Msk (0xFF000000)
+
+#define _GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
+#define _GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
+#define _GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define _GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+
+/******************************************************************************/
+/* Peripheral header files */
+/******************************************************************************/
+#include "sys.h"
+#include "clk.h"
+#include "adc.h"
+#include "ebi.h"
+#include "fmc.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "pwm.h"
+#include "spi.h"
+#include "timer.h"
+#include "wdt.h"
+#include "wwdt.h"
+#include "uart.h"
+#include "hdiv.h"
+#include "acmp.h"
+#endif
+
+/* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. */
+
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/system_M051Series.h b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/system_M051Series.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac067b61cbaeb4a86043f9ba243dadddefc7a6f9
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/system_M051Series.h
@@ -0,0 +1,99 @@
+/**************************************************************************//**
+ * @file system_M051Series.h
+ * @version V3.00
+ * $Revision: 9 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 Series System Setting Header File
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __SYSTEM_M051Series_H__
+#define __SYSTEM_M051Series_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*---------------------------------------------------------------------------------------------------------*/
+#ifndef DEBUG_PORT
+# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
+#endif
+
+/**
+ *
+ * @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using
+ * default clock source (External crystal or internal 22.1184MHz IRC).
+ * Enable this option will casue system booting in 50MHz(By XTAL) or 50.1918MHz(By IRC22M) according to
+ * user configuration setting in CONFIG0
+ *
+ */
+//#define INIT_SYSCLK_AT_BOOTING
+
+/*----------------------------------------------------------------------------
+ Define SYSCLK
+ *----------------------------------------------------------------------------*/
+#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
+#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
+#define __HIRC (22118400UL) /*!< Internal 22M RC Oscillator Frequency */
+#define __HSI (50000000UL) /*!< PLL default output is 48MHz@12M X'tal */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
+extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
+
+#if USE_ASSERT
+/**
+ * @brief Assert Function
+ *
+ * @param[in] expr Expression to be evaluated
+ *
+ * @return None
+ *
+ * @details If the expression is false, an error message will be printed out
+ * from debug port (UART0 or UART1).
+ */
+#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
+
+void AssertError(uint8_t* file, uint32_t line);
+#else
+#define ASSERT_PARAM(expr)
+#endif
+
+#define assert_param(expr) ASSERT_PARAM(expr)
+
+
+/**
+ * @brief System Initializaiton
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details The necessary initializaiton of system.
+ */
+extern void SystemInit(void);
+
+
+/**
+ * @brief Update the Variable SystemCoreClock
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to update the variable SystemCoreClock
+ * and must be called whenever the core clock is changed.
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. */
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/ARM/startup_M051Series.s b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/ARM/startup_M051Series.s
new file mode 100644
index 0000000000000000000000000000000000000000..7cc01d3ec1c7b033e146bfffde323b1d558767e7
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/ARM/startup_M051Series.s
@@ -0,0 +1,237 @@
+;/**************************************************************************//**
+; * @file startup_M051Series.s
+; * @version V2.00
+; * $Revision: 9 $
+; * $Date: 14/01/10 9:11a $
+; * @brief M051 Series Startup Source File
+; *
+; * @note
+; * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
+; *
+; ******************************************************************************/
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; maximum of 32 External Interrupts are possible
+ DCD BOD_IRQHandler
+ DCD WDT_IRQHandler
+ DCD EINT0_IRQHandler
+ DCD EINT1_IRQHandler
+ DCD GPIOP0P1_IRQHandler
+ DCD GPIOP2P3P4_IRQHandler
+ DCD PWMA_IRQHandler
+ DCD PWMB_IRQHandler
+ DCD TMR0_IRQHandler
+ DCD TMR1_IRQHandler
+ DCD TMR2_IRQHandler
+ DCD TMR3_IRQHandler
+ DCD UART0_IRQHandler
+ DCD UART1_IRQHandler
+ DCD SPI0_IRQHandler
+ DCD SPI1_IRQHandler
+ DCD Default_Handler
+ DCD Default_Handler
+ DCD I2C0_IRQHandler
+ DCD I2C1_IRQHandler
+ DCD Default_Handler
+ DCD Default_Handler
+ DCD Default_Handler
+ DCD Default_Handler
+ DCD Default_Handler
+ DCD ACMP01_IRQHandler
+ DCD ACMP23_IRQHandler
+ DCD Default_Handler
+ DCD PWRWU_IRQHandler
+ DCD ADC_IRQHandler
+ DCD Default_Handler
+ DCD RTC_IRQHandler
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+ ENTRY
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =0x50000100
+ ; Unlock Register
+
+ LDR R1, =0x59
+ STR R1, [R0]
+ LDR R1, =0x16
+ STR R1, [R0]
+ LDR R1, =0x88
+ STR R1, [R0]
+
+ ; Init POR
+ LDR R2, =0x50000024
+ LDR R1, =0x00005AA5
+ STR R1, [R2]
+
+ ; Lock register
+ MOVS R1, #0
+ STR R1, [R0]
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT GPIOP0P1_IRQHandler [WEAK]
+ EXPORT GPIOP2P3P4_IRQHandler [WEAK]
+ EXPORT PWMA_IRQHandler [WEAK]
+ EXPORT PWMB_IRQHandler [WEAK]
+ EXPORT TMR0_IRQHandler [WEAK]
+ EXPORT TMR1_IRQHandler [WEAK]
+ EXPORT TMR2_IRQHandler [WEAK]
+ EXPORT TMR3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT ACMP01_IRQHandler [WEAK]
+ EXPORT ACMP23_IRQHandler [WEAK]
+ EXPORT PWRWU_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+
+BOD_IRQHandler
+WDT_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+GPIOP0P1_IRQHandler
+GPIOP2P3P4_IRQHandler
+PWMA_IRQHandler
+PWMB_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+ACMP01_IRQHandler
+ACMP23_IRQHandler
+PWRWU_IRQHandler
+ADC_IRQHandler
+RTC_IRQHandler
+ B .
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, = (Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/IAR/startup_M051Series.s b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/IAR/startup_M051Series.s
new file mode 100644
index 0000000000000000000000000000000000000000..41e87c88dc8aa658a1eb9cf525bd19262c71c2aa
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/IAR/startup_M051Series.s
@@ -0,0 +1,178 @@
+;/**************************************************************************//**
+; * @file startup_M051Series.s
+; * @version V2.00
+; * $Revision: 8 $
+; * $Date: 14/02/12 10:11a $
+; * @brief M051 Series Startup Source File for IAR Platform
+; *
+; * @note
+; * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
+; *
+; ******************************************************************************/
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment
+
+ SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment
+
+ EXTERN SystemInit
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD __iar_program_start
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD BOD_IRQHandler ; Brownout low voltage detected interrupt
+ DCD WDT_IRQHandler ; Watch Dog Timer interrupt
+ DCD EINT0_IRQHandler ; External signal interrupt from PB.14 pin
+ DCD EINT1_IRQHandler ; External signal interrupt from PB.15 pin
+ DCD GPIOP0P1_IRQHandler ; External signal interrupt from P0[15:0] / P1[13:0]
+ DCD GPIOP2P3P4_IRQHandler ; External interrupt from P2[15:0]/P3[15:0]/P4[15:0]
+ DCD PWMA_IRQHandler ; PWM0 or PWM2 interrupt
+ DCD PWMB_IRQHandler ; PWM1 or PWM3 interrupt
+ DCD TMR0_IRQHandler ; Timer 0 interrupt
+ DCD TMR1_IRQHandler ; Timer 1 interrupt
+ DCD TMR2_IRQHandler ; Timer 2 interrupt
+ DCD TMR3_IRQHandler ; Timer 3 interrupt
+ DCD UART0_IRQHandler ; UART0 interrupt
+ DCD UART1_IRQHandler ; UART1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD Default_Handler ; SPI2 interrupt
+ DCD Default_Handler ; SPI3 interrupt
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD Default_Handler ; Reserved
+ DCD Default_Handler ; Reserved
+ DCD Default_Handler ; Reserved
+ DCD Default_Handler ; Reserved
+ DCD Default_Handler ; Reserved
+ DCD ACMP01_IRQHandler ; ACMP0/1 interrupt
+ DCD ACMP23_IRQHandler ; ACMP2/3 interrupt
+ DCD Default_Handler ; Reserved
+ DCD PWRWU_IRQHandler ; Clock controller interrupt for chip wake up from power-
+ DCD ADC_IRQHandler ; ADC interrupt
+ DCD Default_Handler ; Reserved
+ DCD RTC_IRQHandler ; Real time clock interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2) ; 4 bytes alignment
+Reset_Handler
+ LDR R0, =0x50000100
+ ; Unlock Register
+ LDR R1, =0x59
+ STR R1, [R0]
+ LDR R1, =0x16
+ STR R1, [R0]
+ LDR R1, =0x88
+ STR R1, [R0]
+
+ ; Init POR
+ LDR R2, =0x50000024
+ LDR R1, =0x00005AA5
+ STR R1, [R2]
+
+ ; Disable NMI (Assign to reserved IRQ)
+ LDR R2, =0x50000380
+ LDR R1, =0x0000001F
+ STR R1, [R2]
+
+ ; Lock register
+ MOVS R1, #0
+ STR R1, [R0]
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK EINT0_IRQHandler
+ PUBWEAK EINT1_IRQHandler
+ PUBWEAK GPIOP0P1_IRQHandler
+ PUBWEAK GPIOP2P3P4_IRQHandler
+ PUBWEAK PWMA_IRQHandler
+ PUBWEAK PWMB_IRQHandler
+ PUBWEAK TMR0_IRQHandler
+ PUBWEAK TMR1_IRQHandler
+ PUBWEAK TMR2_IRQHandler
+ PUBWEAK TMR3_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK ACMP01_IRQHandler
+ PUBWEAK ACMP23_IRQHandler
+ PUBWEAK PWRWU_IRQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(2)
+HardFault_Handler
+NMI_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+BOD_IRQHandler
+WDT_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+GPIOP0P1_IRQHandler
+GPIOP2P3P4_IRQHandler
+PWMA_IRQHandler
+PWMB_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+ACMP01_IRQHandler
+ACMP23_IRQHandler
+PWRWU_IRQHandler
+ADC_IRQHandler
+RTC_IRQHandler
+Default_Handler
+ B Default_Handler
+
+
+ END
+
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/system_M051Series.c b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/system_M051Series.c
new file mode 100644
index 0000000000000000000000000000000000000000..e0fb66ce08338ffe9ba10c5542763efd8f11a1a2
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/system_M051Series.c
@@ -0,0 +1,148 @@
+/**************************************************************************//**
+ * @file system_M051Series.c
+ * @version V2.00
+ * $Revision: 13 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 Series System Setting Source File
+ *
+ * @note
+ * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#include
+#include
+#include "M051Series.h"
+
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
+uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
+uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
+const uint32_t gau32ClkSrcTbl[] = {__HXT, NULL, __HSI, __LIRC, NULL, NULL, NULL, __HIRC};
+
+
+/**
+ * @brief Update the Variable SystemCoreClock
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to update the variable SystemCoreClock
+ * and must be called whenever the core clock is changed.
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t u32Freq, u32ClkSrc;
+ uint32_t u32HclkDiv;
+
+ u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
+
+ /* Update PLL Clock */
+ PllClock = CLK_GetPLLClockFreq();
+
+ if(u32ClkSrc != CLK_CLKSEL0_HCLK_S_PLL)
+ {
+ /* Use the clock sources directly */
+ u32Freq = gau32ClkSrcTbl[u32ClkSrc];
+ }
+ else
+ {
+ /* Use PLL clock */
+ u32Freq = PllClock;
+ }
+
+ u32HclkDiv = (CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1;
+
+ /* Update System Core Clock */
+ SystemCoreClock = u32Freq / u32HclkDiv;
+
+ CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
+}
+
+
+/**
+ * @brief System Initialization
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details The necessary initialization of system. Global variables are forbidden here.
+ */
+void SystemInit(void)
+{
+#ifdef INIT_SYSCLK_AT_BOOTING
+ int32_t i32TimeoutCnt;
+ uint32_t u32HclkSelect;
+ int8_t i8IsPllEn;
+
+ PllClock = 0;
+ i8IsPllEn = 0;
+ u32HclkSelect = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
+ if(u32HclkSelect == CLK_CLKSEL0_HCLK_S_HXT)
+ {
+ /* Set to 50MHz system clock frequency when clock source is from external 12MHz */
+ CLK->PLLCON = CLK_PLLCON_50MHz_HXT;
+
+ /* Waiting for PLL ready */
+ i32TimeoutCnt = (__HXT / 1000); /* Timeout is about 1ms */
+ while((CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk) == 0)
+ {
+ if(i32TimeoutCnt-- <= 0)
+ break;
+ }
+
+ i8IsPllEn = 1;
+ }
+ else if(u32HclkSelect == CLK_CLKSEL0_HCLK_S_HIRC)
+ {
+ /* Set to 50.1918MHz system clock frequency when clock source is from internal 22.1184MHz RC clock */
+ CLK->PLLCON = CLK_PLLCON_50MHz_HIRC;
+
+ /* Waiting for PLL ready */
+ i32TimeoutCnt = (__HIRC / 1000); /* Timeout is about 1ms */
+ while((CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk) == 0)
+ {
+ if(i32TimeoutCnt-- <= 0)
+ break;
+ }
+
+ i8IsPllEn = 1;
+ }
+
+ if(i8IsPllEn)
+ {
+ /* Set PLL as HCLK clock source (HCLK_S is locked setting)*/
+ SYS_UnlockReg();
+ CLK->CLKSEL0 = CLK_CLKSEL0_HCLK_S_PLL;
+ SYS_LockReg();
+ }
+#endif
+}
+
+#if USE_ASSERT
+
+/**
+ * @brief Assert Error Message
+ *
+ * @param[in] file the source file name
+ * @param[in] line line number
+ *
+ * @return None
+ *
+ * @details The function prints the source file name and line number where
+ * the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
+ */
+void AssertError(uint8_t * file, uint32_t line)
+{
+
+ printf("[%s] line %d : wrong parameters.\r\n", file, line);
+
+ /* Infinite loop */
+ while(1) ;
+}
+#endif
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/README.txt b/bsp/nuvoton_m05x/Libraries/CMSIS/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9b92ccc75fddee97f9eec0a8b5c66ecaf2df8c84
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/README.txt
@@ -0,0 +1,37 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011-2012 ARM Limited. All rights reserved.
+*
+* Date: 07 March 2012
+* Revision: V3.01
+*
+* Project: Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title: Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation - Contains CMSIS documentation.
+
+DSP_Lib - MDK project files, Examples and source files etc.. to build the
+ CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib - CMSIS DSP Libraries.
+
+RTOS - CMSIS RTOS API template header file.
+
+SVD - CMSIS SVD Schema files and Conversion Utility.
diff --git a/bsp/nuvoton_m05x/Libraries/CMSIS/index.html b/bsp/nuvoton_m05x/Libraries/CMSIS/index.html
new file mode 100644
index 0000000000000000000000000000000000000000..c6da0802b47f310a1c6ae260189b80a126f0a3bb
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/CMSIS/index.html
@@ -0,0 +1,14 @@
+
+
+
+Redirect to the CMSIS main page after 0 seconds
+
+
+
+
+
+
+If the automatic redirection is failing, click open CMSIS Documentation.
+
+
+
diff --git a/bsp/nuvoton_m05x/Libraries/SConscript b/bsp/nuvoton_m05x/Libraries/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..af63c0d7101e57f1dcc8d122c52b9e85cf6053e7
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/SConscript
@@ -0,0 +1,31 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+CMSIS/Nuvoton/M051Series/Source/system_M051Series.c
+""")
+
+src += Glob('StdDriver/src/*.c')
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'iar':
+ src = src + ['CMSIS/Nuvoton/M051Series/Source/IAR/startup_M051Series.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src = src + ['CMSIS/Nuvoton/M051Series/Source/ARM/startup_M051Series.s']
+#elif rtconfig.CROSS_TOOL == 'gcc': // not support gcc
+# src = src + ['CMSIS/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s']
+
+path = [cwd + '/StdDriver/inc',
+ cwd + '/CMSIS/Nuvoton/M051Series/Include',
+ cwd + '/CMSIS/Include']
+
+#CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
+CPPDEFINES = ['']
+group = DefineGroup('M05X_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/acmp.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/acmp.h
new file mode 100644
index 0000000000000000000000000000000000000000..cb6ea5f303681867aceadb1d99692354069de07e
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/acmp.h
@@ -0,0 +1,167 @@
+/**************************************************************************//**
+ * @file acmp.h
+ * @version V3.00
+ * $Revision: 6 $
+ * $Date: 1/28/14 11:32a $
+ * @brief M051 series Analog Comparator(ACMP) driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __ACMP_H__
+#define __ACMP_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_ACMP_Driver ACMP Driver
+ @{
+*/
+
+/** @addtogroup M051_ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_CR constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_CR_OUTPUT_INV (1UL << ACMP_CR_ACMPOINV_Pos) /*!< ACMP_CR setting for ACMP output inverse function. */
+#define ACMP_CR_VNEG_BANDGAP (1UL << ACMP_CR_NEGSEL_Pos) /*!< ACMP_CR setting for selecting band-gap voltage as the source of ACMP V-. */
+#define ACMP_CR_VNEG_PIN (0UL << ACMP_CR_NEGSEL_Pos) /*!< ACMP_CR setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */
+#define ACMP_CR_HYSTERESIS_ENABLE (1UL << ACMP_CR_HYSEN_Pos) /*!< ACMP_CR setting for enabling the hysteresis function. */
+#define ACMP_CR_HYSTERESIS_DISABLE (0UL << ACMP_CR_HYSEN_Pos) /*!< ACMP_CR setting for disabling the hysteresis function. */
+#define ACMP_CR_INT_ENABLE (1UL << ACMP_CR_ACMPIE_Pos) /*!< ACMP_CR setting for enabling the interrupt function. */
+#define ACMP_CR_INT_DISABLE (0UL << ACMP_CR_ACMPIE_Pos) /*!< ACMP_CR setting for disabling the interrupt function. */
+#define ACMP_CR_ACMP_ENABLE (1UL << ACMP_CR_ACMPEN_Pos) /*!< ACMP_CR setting for enabling the ACMP analog circuit. */
+#define ACMP_CR_ACMP_DISABLE (0UL << ACMP_CR_ACMPEN_Pos) /*!< ACMP_CR setting for disabling the ACMP analog circuit. */
+
+/*@}*/ /* end of group M051_ACMP_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro is used to enable output inverse
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPOINV_Msk)
+
+/**
+ * @brief This macro is used to disable output inverse
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPOINV_Msk)
+
+/**
+ * @brief This macro is used to select ACMP negative input source
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Src is comparator0 negative input selection. Including :
+ * - \ref ACMP_CR_VNEG_PIN
+ * - \ref ACMP_CR_VNEG_BANDGAP
+ * @return None
+ */
+#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CR[(u32ChNum)%2] = ((acmp)->CR[(u32ChNum)%2] & ~ACMP_CR_NEGSEL_Msk) | (u32Src))
+
+/**
+ * @brief This macro is used to enable hysteresis function
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_HYSEN_Msk)
+
+/**
+ * @brief This macro is used to disable hysteresis function
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_HYSEN_Msk)
+
+/**
+ * @brief This macro is used to enable interrupt
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPIE_Msk)
+
+/**
+ * @brief This macro is used to disable interrupt
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPIE_Msk)
+
+
+/**
+ * @brief This macro is used to enable ACMP
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPEN_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPEN_Msk)
+
+/**
+ * @brief This macro is used to get ACMP output value
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return 1 or 0
+ */
+#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->SR & (ACMP_SR_ACMPO0_Msk<<((u32ChNum)%2)))?1:0)
+
+/**
+ * @brief This macro is used to get ACMP interrupt flag
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return ACMP interrupt occurred or not
+ */
+#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->SR & (ACMP_SR_ACMPF0_Msk<<((u32ChNum)%2)))?1:0)
+
+/**
+ * @brief This macro is used to clear ACMP interrupt flag
+ * @param[in] acmp The base address of ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ */
+#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->SR = (ACMP_SR_ACMPF0_Msk<<((u32ChNum)%2)))
+
+void ACMP_Open(ACMP_T *, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
+void ACMP_Close(ACMP_T *, uint32_t u32ChNum);
+
+/*@}*/ /* end of group M051_ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_ACMP_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__ACMP_H__
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/adc.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/adc.h
new file mode 100644
index 0000000000000000000000000000000000000000..a5479f66958c3fd7f59109e46ff1ee411b96ef0a
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/adc.h
@@ -0,0 +1,335 @@
+/**************************************************************************//**
+ * @file adc.h
+ * @version V3.0
+ * $Revision: 10 $
+ * $Date: 14/02/10 2:27p $
+ * @brief M051 series ADC driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ADC_H__
+#define __ADC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_ADC_Driver ADC Driver
+ @{
+*/
+
+/** @addtogroup M051_ADC_EXPORTED_CONSTANTS ADC Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADCR Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_ADCR_ADEN_CONVERTER_DISABLE (0UL<ADCHER = (ADC->ADCHER & ~ADC_ADCHER_PRESEL_Msk) | (u32Source))
+
+/**
+ * @brief Get conversion data of specified channel.
+ * @param[in] adc Base address of ADC module.
+ * @param[in] u32ChNum ADC Channel, valid value are from 0 to 7.
+ * @return Read RSLT bit field to get conversion data.
+ */
+#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((ADC->ADDR[(u32ChNum)] & ADC_ADDR_RSLT_Msk)>>ADC_ADDR_RSLT_Pos)
+
+/**
+ * @brief Return the user-specified interrupt flags.
+ * @param[in] adc Base address of ADC module.
+ * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
+ * Valid values are:
+ * - \ref ADC_ADF_INT :Convert complete interrupt flag.
+ * - \ref ADC_CMP0_INT :Comparator 0 interrupt flag.
+ * - \ref ADC_CMP1_INT :Comparator 1 interrupt flag.
+ * @return User specified interrupt flags.
+ */
+#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->ADSR & (u32Mask))
+
+/**
+ * @brief This macro clear the selected interrupt status bits.
+ * @param[in] adc Base address of ADC module.
+ * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
+ * Valid values are:
+ * - \ref ADC_ADF_INT :Convert complete interrupt flag
+ * - \ref ADC_CMP0_INT :Comparator 0 interrupt flag
+ * - \ref ADC_CMP1_INT :Comparator 1 interrupt flag
+ * @return None
+ */
+#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->ADSR = u32Mask)
+
+/**
+ * @brief Get the busy state of ADC.
+ * @param[in] adc Base address of ADC module.
+ * @return busy state of ADC.
+ * @retval 0 ADC is not busy.
+ * @retval 1 ADC is busy.
+ */
+#define ADC_IS_BUSY(adc) (ADC->ADSR & ADC_ADSR_BUSY_Msk ? 1 : 0)
+
+/**
+ * @brief Check if the ADC conversion data is over written or not.
+ * @param[in] adc Base address of ADC module.
+ * @param[in] u32ChNum ADC Channel, valid value are from 0 to 7.
+ * @return Over run state of ADC data.
+ * @retval 0 ADC data is not overrun.
+ * @retval 1 ADC data us overrun.
+ */
+#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->ADSR & (u32ChNum<ADSR & (0x1<<(ADC_ADSR_VALID_Pos+u32ChNum)) ? 1 : 0)
+
+/**
+ * @brief Power down ADC module.
+ * @param[in] adc Base address of ADC module.
+ * @return None
+ */
+#define ADC_POWER_DOWN(adc) (ADC->ADCR &= ~ADC_ADCR_ADEN_Msk)
+
+/**
+ * @brief Power on ADC module.
+ * @param[in] adc Base address of ADC module.
+ * @return None
+ */
+#define ADC_POWER_ON(adc) (ADC->ADCR |= ADC_ADCR_ADEN_Msk)
+
+/**
+ * @brief Configure the comparator 0 and enable it.
+ * @param[in] adc Base address of ADC module.
+ * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7.
+ * @param[in] u32Condition Specifies the compare condition. Valid values are:
+ * - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF.
+ * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
+ * Means ADC will assert comparator 0 flag if channel 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously.
+ * @note When DIFFEN bit is set to 1, ADC comparator compares CMPD with conversion result with unsigned
+ * format (M05xxBN only). u32Data should be filled in unsigned format (straight binary format).
+ */
+#define ADC_ENABLE_CMP0(adc, \
+ u32ChNum, \
+ u32Condition, \
+ u32Data, \
+ u32MatchCount) (ADC->ADCMPR[0] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
+ u32Condition | \
+ ((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
+ (((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
+ ADC_ADCMPR_CMPEN_Msk)
+
+/**
+ * @brief Disable comparator 0
+ * @param[in] adc Base address of ADC module
+ */
+#define ADC_DISABLE_CMP0(adc) (ADC->ADCMPR[0] = 0)
+
+/**
+ * @brief Configure the comparator 1 and enable it.
+ * @param[in] adc Base address of ADC module.
+ * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7.
+ * @param[in] u32Condition Specifies the compare condition. Valid values are:
+ * - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF.
+ * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
+ * Means ADC will assert comparator 1 flag if channel 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously.
+ */
+#define ADC_ENABLE_CMP1(adc, \
+ u32ChNum, \
+ u32Condition, \
+ u32Data, \
+ u32MatchCount) (ADC->ADCMPR[1] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
+ u32Condition | \
+ ((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
+ (((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
+ ADC_ADCMPR_CMPEN_Msk)
+
+/**
+ * @brief Disable comparator 1.
+ * @param[in] adc Base address of ADC module.
+ */
+#define ADC_DISABLE_CMP1(adc) (ADC->ADCMPR[1] = 0)
+
+/**
+ * @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
+ * @param[in] adc Base address of ADC module.
+ * @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 7 is channel 7.
+ * @return None
+ * @note M051 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
+ * with smallest number will be convert.
+ */
+#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32Mask))
+
+/**
+ * @brief Set the output format mode.
+ * @param[in] adc Base address of ADC module.
+ * @param[in] u32Format Decides the output format. Valid values are:
+ * - \ref ADC_ADCR_DMOF_UNSIGNED_OUTPUT :Select the straight binary format as the output format of the conversion result.
+ * - \ref ADC_ADCR_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
+ * @return None
+ * @note Burst mode and ADC compare function can not support 2's complement output format,
+ * this u32Format must be 0 (M05xxBN only).
+ */
+#define ADC_SET_DMOF(adc, u32Format) (ADC->ADCR = (ADC->ADCR & ~ADC_ADCR_DMOF_Msk) | (u32Format))
+
+/**
+ * @brief Start the A/D conversion.
+ * @param[in] adc Base address of ADC module.
+ * @return None
+ */
+#define ADC_START_CONV(adc) (ADC->ADCR |= ADC_ADCR_ADST_Msk)
+
+/**
+ * @brief Stop the A/D conversion.
+ * @param[in] adc Base address of ADC module.
+ * @return None
+ * @note When hardware clears the ADST bit, the ADST bit must be kept at 0 at least one ADC peripheral clock
+ * period before setting it to 1 again, otherwise the A/D converter may not work (M05xxBN only). If ADST
+ * bit is cleared to 0 when ADC is in converting, the BUSY bit will be cleared to 0 immediately, ADC will
+ * finish the current conversion and save the result to the ADDRx register of the enabled channel (M05xxBN only).
+ * But, ADC can not finish the current conversion and A/D converter enters idle state directly (M05xxDN only).
+ */
+#define ADC_STOP_CONV(adc) (ADC->ADCR &= ~ADC_ADCR_ADST_Msk)
+
+void ADC_Open(ADC_T *adc,
+ uint32_t u32InputMode,
+ uint32_t u32OpMode,
+ uint32_t u32ChMask);
+void ADC_Close(ADC_T *adc);
+void ADC_EnableHWTrigger(ADC_T *adc,
+ uint32_t u32Source,
+ uint32_t u32Param);
+void ADC_DisableHWTrigger(ADC_T *adc);
+void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
+void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
+
+
+
+/*@}*/ /* end of group M051_ADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_ADC_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__ADC_H__
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/clk.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..70334a32043951c3b4738270d9701919a85279ad
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/clk.h
@@ -0,0 +1,279 @@
+/**************************************************************************//**
+ * @file clk.h
+ * @version V3.0
+ * $Revision: 17 $
+ * $Date: 14/01/28 1:11p $
+ * @brief M051 Series Clock Control Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __CLK_H__
+#define __CLK_H__
+
+
+#include "M051Series.h"
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_CLK_Driver CLK Driver
+ @{
+*/
+
+/** @addtogroup M051_CLK_EXPORTED_FUNCTIONS CLK Exported Constants
+ @{
+*/
+
+#define FREQ_25MHZ 25000000
+#define FREQ_50MHZ 50000000
+#define FREQ_100MHZ 100000000
+#define FREQ_200MHZ 200000000
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PWRCON constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PWRCON_HXT_EN (0x01UL<>31) & 0x1) /*!< Calculate APBCLK offset on MODULE index */
+#define MODULE_CLKSEL(x) ((x >>29) & 0x3) /*!< Calculate CLKSEL offset on MODULE index */
+#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) /*!< Calculate CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index */
+#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
+#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
+/*-------------------------------------------------------------------------------------------------------------------------------------------------*/
+/* APBCLK(31)|CLKSEL(30:29)|CLKSEL_Msk(28:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0)*/
+/*-------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define WDT_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |( 0<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_WDT_EN_Pos ) /*!< WDT Module */
+#define TMR0_MODULE ((0x0<<31)|(0x1<<29) |(0x7<<25) |( 8<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_TMR0_EN_Pos) /*!< TMR0 Module */
+#define TMR1_MODULE ((0x0<<31)|(0x1<<29) |(0x7<<25) |(12<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_TMR1_EN_Pos) /*!< TMR1 Module */
+#define TMR2_MODULE ((0x0<<31)|(0x1<<29) |(0x7<<25) |(16<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_TMR0_EN_Pos) /*!< TMR2 Module */
+#define TMR3_MODULE ((0x0<<31)|(0x1<<29) |(0x7<<25) |(20<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_TMR1_EN_Pos) /*!< TMR3 Module */
+#define FDIV_MODULE ((0x0<<31)|(0x3<<29) |(0x3<<25) |( 2<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_FDIV_EN_Pos) /*!< FDIV Module */
+#define I2C0_MODULE ((0x0<<31) |(MODULE_NoMsk<<25) |(MODULE_NoMsk<<10) |CLK_APBCLK_I2C0_EN_Pos) /*!< I2C0 Module */
+#define I2C1_MODULE ((0x0<<31) |(MODULE_NoMsk<<25) |(MODULE_NoMsk<<10) |CLK_APBCLK_I2C1_EN_Pos) /*!< I2C1 Module */
+#define SPI0_MODULE ((0x0<<31)|(0x1<<29) |(0x1<<25) |( 4<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_SPI0_EN_Pos) /*!< SPI0 Module */
+#define SPI1_MODULE ((0x0<<31)|(0x1<<29) |(0x1<<25) |( 5<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_SPI1_EN_Pos) /*!< SPI1 Module */
+#define UART0_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |(24<<20) |(0x0<<18) |(0x0F<<10) |( 8<<5) |CLK_APBCLK_UART0_EN_Pos) /*!< UART0 Module */
+#define UART1_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |(24<<20) |(0x0<<18) |(0x0F<<10) |( 8<<5) |CLK_APBCLK_UART1_EN_Pos) /*!< UART1 Module */
+#define PWM01_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |(28<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_PWM01_EN_Pos) /*!< PWM01 Module */
+#define PWM23_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |(30<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_PWM23_EN_Pos) /*!< PWM23 Module */
+#define PWM45_MODULE ((0x0<<31)|(0x3<<29) |(0x3<<25) |( 4<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_PWM45_EN_Pos) /*!< PWM45 Module */
+#define PWM67_MODULE ((0x0<<31)|(0x3<<29) |(0x3<<25) |( 6<<20) |(MODULE_NoMsk<<10) |CLK_APBCLK_PWM67_EN_Pos) /*!< PWM67 Module */
+#define ADC_MODULE ((0x0<<31)|(0x1<<29) |(0x3<<25) |( 2<<20) |(0x0<<18) |(0xFF<<10) |(16<<5) |CLK_APBCLK_ADC_EN_Pos) /*!< ADC Module */
+#define ACMP01_MODULE ((0x0<<31) |(MODULE_NoMsk<<25) |(MODULE_NoMsk<<10) |CLK_APBCLK_ACMP01_EN_Pos) /*!< ACMP01 Module */
+#define ACMP23_MODULE ((0x0<<31) |(MODULE_NoMsk<<25) |(MODULE_NoMsk<<10) |CLK_APBCLK_ACMP23_EN_Pos) /*!< ACMP23 Module */
+#define WWDT_MODULE ((MODULE_NoMsk<<31)|(0x3<<29)|(0x3<<25) |(16<<20) |(MODULE_NoMsk<<10) |MODULE_NoMsk ) /*!< WWDT Module */
+
+
+/*@}*/ /* end of group M051_CLK_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief This function get PLL frequency. The frequency unit is Hz.
+ * @return PLL frequency
+ */
+static __INLINE uint32_t CLK_GetPLLClockFreq(void)
+{
+ uint32_t u32PllFreq = 0, u32PllReg;
+ uint32_t u32FIN, u32NF, u32NR, u32NO;
+ uint8_t au8NoTbl[4] = {1, 2, 2, 4};
+
+ u32PllReg = CLK->PLLCON;
+
+ if(u32PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk))
+ return 0; /* PLL is in power down mode or fix low */
+
+ if(u32PllReg & CLK_PLLCON_PLL_SRC_HIRC)
+ u32FIN = __HIRC; /* PLL source clock from HIRC */
+ else
+ u32FIN = __HXT; /* PLL source clock from HXT */
+
+ if(u32PllReg & CLK_PLLCON_BP_Msk)
+ return u32FIN; /* PLL is in bypass mode */
+
+ /* PLL is output enabled in normal work mode */
+ u32NO = au8NoTbl[((u32PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)];
+ u32NF = ((u32PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
+ u32NR = ((u32PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
+
+ /* u32FIN is shifted 2 bits to avoid overflow */
+ u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
+
+ return u32PllFreq;
+}
+
+/**
+ * @brief This function execute delay function.
+ * @param us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
+ * 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
+ * @return None
+ * @details Use the SysTick to generate the delay time and the UNIT is in us.
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.
+ */
+static __INLINE void CLK_SysTickDelay(uint32_t us)
+{
+ SysTick->LOAD = us * CyclesPerUs;
+ SysTick->VAL = (0x00);
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
+}
+
+
+void CLK_DisableCKO(void);
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
+void CLK_PowerDown(void);
+void CLK_Idle(void);
+uint32_t CLK_GetHXTFreq(void);
+uint32_t CLK_GetLXTFreq(void);
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetPCLKFreq(void);
+uint32_t CLK_GetCPUFreq(void);
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
+void CLK_EnableXtalRC(uint32_t u32ClkMask);
+void CLK_DisableXtalRC(uint32_t u32ClkMask);
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
+void CLK_DisablePLL(void);
+void CLK_WaitClockReady(uint32_t u32ClkMask);
+
+
+/*@}*/ /* end of group M051_CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_CLK_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+
+
+#endif //__CLK_H__
+
+
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/ebi.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/ebi.h
new file mode 100644
index 0000000000000000000000000000000000000000..6a1f36ee2636c40321a814915941bf38d516072f
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/ebi.h
@@ -0,0 +1,114 @@
+/**************************************************************************//**
+ * @file ebi.h
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series EBI driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EBI_H__
+#define __EBI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_EBI_Driver EBI Driver
+ @{
+*/
+
+/** @addtogroup M051_EBI_EXPORTED_CONSTANTS EBI Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* Miscellaneous Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BASE_ADDR 0x60000000UL /*!< EBI base address */
+#define EBI_MAX_SIZE 0x00020000UL /*!< Maximum EBI size */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI data bus width */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BUSWIDTH_8BIT 8 /*!< EBI bus width is 8-bit */
+#define EBI_BUSWIDTH_16BIT 16 /*!< EBI bus width is 16-bit */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI MCLK divider and Timing */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 */
+#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 */
+#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 */
+#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 */
+#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 */
+#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 */
+
+#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest */
+#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast */
+#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast */
+#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal */
+#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow */
+#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow */
+#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest */
+
+/*@}*/ /* end of group M051_EBI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+ @{
+*/
+
+/**
+ * @details This macro read 8-bit data from specify EBI address.
+ */
+#define EBI_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BASE_ADDR+u32Addr)))
+
+/**
+ * @details This macro write 8-bit data to specify EBI address.
+ */
+#define EBI_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BASE_ADDR+u32Addr)) = u32Data)
+
+/**
+ * @details This macro read 16-bit data from specify EBI address.
+ */
+#define EBI_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BASE_ADDR+u32Addr)))
+
+/**
+ * @details This macro write 16-bit data to specify EBI address.
+ */
+#define EBI_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BASE_ADDR+u32Addr)) = u32Data)
+
+/**
+ * @details This macro read 32-bit data from specify EBI address.
+ */
+#define EBI_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BASE_ADDR+u32Addr)))
+
+/**
+ * @details This macro write 32-bit data to specify EBI address.
+ */
+#define EBI_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BASE_ADDR+u32Addr)) = u32Data)Write 32-bit data to EBI bank 0
+
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+void EBI_Close(uint32_t u32Bank);
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
+
+/*@}*/ /* end of group M051_EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_EBI_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__EBI_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/fmc.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/fmc.h
new file mode 100644
index 0000000000000000000000000000000000000000..469d1b9a045e667c0bdadef97680138e4f2f1f40
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/fmc.h
@@ -0,0 +1,333 @@
+/**************************************************************************//**
+ * @file FMC.h
+ * @version V3.0
+ * $Revision: 13 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 Series Flash Memory Controller Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __FMC_H__
+#define __FMC_H__
+
+#include "M051Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_FMC_Driver FMC Driver
+ @{
+*/
+
+/** @addtogroup M051_FMC_EXPORTED_CONSTANTS FMC Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
+#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
+#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
+
+#define FMC_FLASH_PAGE_SIZE 0x200 /*!< Flash Page Size (512 Bytes) */
+#define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4 KBytes) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ISPCON constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCON_BS_LDROM 0x2 /*!< ISPCON setting to select to boot from LDROM */
+#define FMC_ISPCON_BS_APROM 0x0 /*!< ISPCON setting to select to boot from APROM */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ISPCMD constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */
+#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: Program Flash */
+#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
+#define FMC_ISPCMD_VECMAP 0x2e /*!< ISP Command: Set VECMAP */
+#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
+#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
+#define FMC_ISPCMD_READ_DID 0x0C /*!< ISP Command: Read Device ID */
+
+
+/*@}*/ /* end of group M051_FMC_EXPORTED_CONSTANTS */
+
+/** @addtogroup M051_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* FMC Macro Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ENABLE_ISP() (FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk) /*!< Enable ISP Function */
+#define FMC_DISABLE_ISP() (FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk) /*!< Disable ISP Function */
+#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk) /*!< Enable LDROM Update Function */
+#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk) /*!< Disable LDROM Update Function */
+#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk) /*!< Enable CONFIG Update Function */
+#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
+#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCON |= FMC_ISPCON_APUEN_Msk) /*!< Enable APROM Update Function */
+#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk) /*!< Disable APROM Update Function */
+#define FMC_GET_FAIL_FLAG() ((FMC->ISPCON & FMC_ISPCON_ISPFF_Msk) ? 1 : 0) /*!< Get ISP fail flag */
+#define FMC_SET_APROM_BOOT() (FMC->ISPCON &= ~FMC_ISPCON_BS_Msk) /*!< Select booting from APROM */
+#define FMC_SET_LDROM_BOOT() (FMC->ISPCON |= FMC_ISPCON_BS_Msk) /*!< Select booting from LDROM */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ * @brief Program 32-bit data into specified address of flash
+ *
+ * @param[in] u32addr Flash address include APROM, LDROM, Data Flash, and CONFIG
+ * @param[in] u32data 32-bit Data to program
+ *
+ * @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG.
+ * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
+ *
+ * @note
+ * Please make sure that Register Write-Protection Function has been disabled
+ * before using this function.
+ */
+static __INLINE void FMC_Write(uint32_t u32addr, uint32_t u32data)
+{
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM; /* Set ISP Command Code */
+ FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be word alignment. */
+ FMC->ISPDAT = u32data; /* Set Data to Program */
+ FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG); /* Waiting for ISP Done */
+}
+
+/**
+ * @brief Read 32-bit Data from specified address of flash
+ *
+ * @param[in] u32addr Flash address include APROM, LDROM, Data Flash, and CONFIG
+ *
+ * @return The data of specified address
+ *
+ * @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG.
+ *
+ * @note
+ * Please make sure that Register Write-Protection Function has been disabled
+ * before using this function.
+ */
+static __INLINE uint32_t FMC_Read(uint32_t u32addr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ; /* Set ISP Command Code */
+ FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be word alignment. */
+ FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG); /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief Flash page erase
+ *
+ * @param[in] u32addr Flash address including APROM, LDROM, Data Flash, and CONFIG
+ *
+ * @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG.
+ * The page size is 512 bytes.
+ *
+ * @retval 0: Success
+ * @retval -1: Erase failed
+ *
+ * @note
+ * Please make sure that Register Write-Protection Function has been disabled
+ * before using this function.
+ */
+static __INLINE int32_t FMC_Erase(uint32_t u32addr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; /* Set ISP Command Code */
+ FMC->ISPADR = u32addr; /* Set Target ROM Address. The address must be page alignment. */
+ FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG); /* Waiting for ISP Done */
+
+ /* Check ISPFF flag to know whether erase OK or fail. */
+ if(FMC->ISPCON & FMC_ISPCON_ISPFF_Msk)
+ {
+ FMC->ISPCON = FMC_ISPCON_ISPFF_Msk;
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * @brief Read Unique ID
+ *
+ * @param[in] u8index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
+ *
+ * @return The 32-bit unique ID data of specified UID index.
+ *
+ * @details To read out 96-bit Unique ID.
+ *
+ * @note
+ * Please make sure that Register Write-Protection Function has been disabled
+ * before using this function.
+ */
+static __INLINE uint32_t FMC_ReadUID(uint8_t u8index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
+ FMC->ISPADR = (u8index << 2); /* Set UID Address. It must be word alignment. */
+ FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG); /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief Read company ID
+ *
+ * @retval The company ID (32-bit)
+ *
+ * @details The company ID of Nuvoton is fixed to be 0xDA
+ */
+static __INLINE uint32_t FMC_ReadCID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
+ FMC->ISPADR = 0x0; /* Must keep 0x0 when read CID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ; /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief Read device ID
+ *
+ * @retval The device ID (32-bit)
+ *
+ */
+static __INLINE uint32_t FMC_ReadDID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
+ FMC->ISPADR = 0; /* Must keep 0x0 when read DID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+
+
+/**
+ * @brief Read product ID
+ *
+ * @retval The product ID (32-bit)
+ *
+ */
+static __INLINE uint32_t FMC_ReadPID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
+ FMC->ISPADR = 0x04; /* Must keep 0x4 when read PID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief To read UCID
+ *
+ * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
+ *
+ * @retval The UCID of specified index
+ *
+ */
+static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
+ FMC->ISPADR = (0x04 * u32Index) + 0x10; /* The UCID is at offset 0x10 with word alignment. */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+
+
+/**
+ * @brief Set vector mapping address
+ *
+ * @param[in] u32MapAddr The page address to remap to address 0x0. The address must be page alignment.
+ *
+ * @details To set VECMAP to remap specified page address to 0x0.
+ *
+ * @note
+ * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ *
+ */
+static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
+ FMC->ISPADR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
+ FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
+ __ISB(); /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG); /* Waiting for ISP Done */
+}
+
+
+/**
+ * @brief Get current vector mapping address.
+ *
+ * @return The current vector mapping address.
+ *
+ * @details To get VECMAP value which is the page address for remapping to 0x0.
+ *
+ * @note
+ * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ *
+ */
+static __INLINE uint32_t FMC_GetVECMAP(void)
+{
+ return (FMC->ISPSTA & FMC_ISPSTA_VECMAP_Msk);
+}
+
+extern void FMC_Open(void);
+extern void FMC_Close(void);
+extern void FMC_EnableAPUpdate(void);
+extern void FMC_DisableAPUpdate(void);
+extern void FMC_EnableConfigUpdate(void);
+extern void FMC_DisableConfigUpdate(void);
+extern void FMC_EnableLDUpdate(void);
+extern void FMC_DisableLDUpdate(void);
+extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
+extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
+extern void FMC_SetBootSource(int32_t i32BootSrc);
+extern int32_t FMC_GetBootSource(void);
+extern uint32_t FMC_ReadDataFlashBaseAddr(void);
+
+/*@}*/ /* end of group M051_FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_FMC_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/gpio.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..5ffd98ecc37b0ef1db994b79a69bba7c7273a032
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/gpio.h
@@ -0,0 +1,376 @@
+/**************************************************************************//**
+ * @file GPIO.h
+ * @version V2.1
+ * $Revision: 5 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 Series General Purpose I/O Driver Header File
+ *
+ * @note
+ * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup M051_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+ @{
+*/
+#define GPIO_PIN_MAX 8 /*!< Specify Maximum Pins of Each GPIO Port */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PMD Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_PMD_INPUT 0x0UL /*!< Input Mode */
+#define GPIO_PMD_OUTPUT 0x1UL /*!< Output Mode */
+#define GPIO_PMD_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
+#define GPIO_PMD_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Interrupt Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
+#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
+#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
+#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
+#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* IMD Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_IMD_EDGE 0UL /*!< IMD Setting for Edge Trigger Mode */
+#define GPIO_IMD_LEVEL 1UL /*!< IMD Setting for Edge Level Mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* DBNCECON Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_CLK_ON 0x00000020UL /*!< DBNCECON setting for all IO pins edge detection circuit is always active after reset */
+#define GPIO_INT_CLK_OFF 0x00000000UL /*!< DBNCECON setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
+
+#define GPIO_DBCLKSRC_LIRC 0x00000010UL /*!< DBNCECON setting for de-bounce counter clock source is the internal 10 kHz */
+#define GPIO_DBCLKSRC_HCLK 0x00000000UL /*!< DBNCECON setting for de-bounce counter clock source is the HCLK */
+
+#define GPIO_DBCLKSEL_1 0x00000000UL /*!< DBNCECON setting for sampling cycle = 1 clocks */
+#define GPIO_DBCLKSEL_2 0x00000001UL /*!< DBNCECON setting for sampling cycle = 2 clocks */
+#define GPIO_DBCLKSEL_4 0x00000002UL /*!< DBNCECON setting for sampling cycle = 4 clocks */
+#define GPIO_DBCLKSEL_8 0x00000003UL /*!< DBNCECON setting for sampling cycle = 8 clocks */
+#define GPIO_DBCLKSEL_16 0x00000004UL /*!< DBNCECON setting for sampling cycle = 16 clocks */
+#define GPIO_DBCLKSEL_32 0x00000005UL /*!< DBNCECON setting for sampling cycle = 32 clocks */
+#define GPIO_DBCLKSEL_64 0x00000006UL /*!< DBNCECON setting for sampling cycle = 64 clocks */
+#define GPIO_DBCLKSEL_128 0x00000007UL /*!< DBNCECON setting for sampling cycle = 128 clocks */
+#define GPIO_DBCLKSEL_256 0x00000008UL /*!< DBNCECON setting for sampling cycle = 256 clocks */
+#define GPIO_DBCLKSEL_512 0x00000009UL /*!< DBNCECON setting for sampling cycle = 512 clocks */
+#define GPIO_DBCLKSEL_1024 0x0000000AUL /*!< DBNCECON setting for sampling cycle = 1024 clocks */
+#define GPIO_DBCLKSEL_2048 0x0000000BUL /*!< DBNCECON setting for sampling cycle = 2048 clocks */
+#define GPIO_DBCLKSEL_4096 0x0000000CUL /*!< DBNCECON setting for sampling cycle = 4096 clocks */
+#define GPIO_DBCLKSEL_8192 0x0000000DUL /*!< DBNCECON setting for sampling cycle = 8192 clocks */
+#define GPIO_DBCLKSEL_16384 0x0000000EUL /*!< DBNCECON setting for sampling cycle = 16384 clocks */
+#define GPIO_DBCLKSEL_32768 0x0000000FUL /*!< DBNCECON setting for sampling cycle = 32768 clocks */
+
+/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
+ * Example 1:
+ *
+ * P00 = 1;
+ *
+ * It is used to set P0.0 to high;
+ *
+ * Example 2:
+ *
+ * if (P00)
+ * P00 = 0;
+ *
+ * If P0.0 pin status is high, then set P0.0 data output to low.
+ */
+#define GPIO_PIN_ADDR(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x20*(port))) + ((pin)<<2))))
+#define P00 GPIO_PIN_ADDR(0, 0) /*!< Specify P00 Pin Data Input/Output */
+#define P01 GPIO_PIN_ADDR(0, 1) /*!< Specify P01 Pin Data Input/Output */
+#define P02 GPIO_PIN_ADDR(0, 2) /*!< Specify P02 Pin Data Input/Output */
+#define P03 GPIO_PIN_ADDR(0, 3) /*!< Specify P03 Pin Data Input/Output */
+#define P04 GPIO_PIN_ADDR(0, 4) /*!< Specify P04 Pin Data Input/Output */
+#define P05 GPIO_PIN_ADDR(0, 5) /*!< Specify P05 Pin Data Input/Output */
+#define P06 GPIO_PIN_ADDR(0, 6) /*!< Specify P06 Pin Data Input/Output */
+#define P07 GPIO_PIN_ADDR(0, 7) /*!< Specify P07 Pin Data Input/Output */
+#define P10 GPIO_PIN_ADDR(1, 0) /*!< Specify P10 Pin Data Input/Output */
+#define P11 GPIO_PIN_ADDR(1, 1) /*!< Specify P11 Pin Data Input/Output */
+#define P12 GPIO_PIN_ADDR(1, 2) /*!< Specify P12 Pin Data Input/Output */
+#define P13 GPIO_PIN_ADDR(1, 3) /*!< Specify P13 Pin Data Input/Output */
+#define P14 GPIO_PIN_ADDR(1, 4) /*!< Specify P14 Pin Data Input/Output */
+#define P15 GPIO_PIN_ADDR(1, 5) /*!< Specify P15 Pin Data Input/Output */
+#define P16 GPIO_PIN_ADDR(1, 6) /*!< Specify P16 Pin Data Input/Output */
+#define P17 GPIO_PIN_ADDR(1, 7) /*!< Specify P17 Pin Data Input/Output */
+#define P20 GPIO_PIN_ADDR(2, 0) /*!< Specify P20 Pin Data Input/Output */
+#define P21 GPIO_PIN_ADDR(2, 1) /*!< Specify P21 Pin Data Input/Output */
+#define P22 GPIO_PIN_ADDR(2, 2) /*!< Specify P22 Pin Data Input/Output */
+#define P23 GPIO_PIN_ADDR(2, 3) /*!< Specify P23 Pin Data Input/Output */
+#define P24 GPIO_PIN_ADDR(2, 4) /*!< Specify P24 Pin Data Input/Output */
+#define P25 GPIO_PIN_ADDR(2, 5) /*!< Specify P25 Pin Data Input/Output */
+#define P26 GPIO_PIN_ADDR(2, 6) /*!< Specify P26 Pin Data Input/Output */
+#define P27 GPIO_PIN_ADDR(2, 7) /*!< Specify P27 Pin Data Input/Output */
+#define P30 GPIO_PIN_ADDR(3, 0) /*!< Specify P30 Pin Data Input/Output */
+#define P31 GPIO_PIN_ADDR(3, 1) /*!< Specify P31 Pin Data Input/Output */
+#define P32 GPIO_PIN_ADDR(3, 2) /*!< Specify P32 Pin Data Input/Output */
+#define P33 GPIO_PIN_ADDR(3, 3) /*!< Specify P33 Pin Data Input/Output */
+#define P34 GPIO_PIN_ADDR(3, 4) /*!< Specify P34 Pin Data Input/Output */
+#define P35 GPIO_PIN_ADDR(3, 5) /*!< Specify P35 Pin Data Input/Output */
+#define P36 GPIO_PIN_ADDR(3, 6) /*!< Specify P36 Pin Data Input/Output */
+#define P37 GPIO_PIN_ADDR(3, 7) /*!< Specify P37 Pin Data Input/Output */
+#define P40 GPIO_PIN_ADDR(4, 0) /*!< Specify P40 Pin Data Input/Output */
+#define P41 GPIO_PIN_ADDR(4, 1) /*!< Specify P41 Pin Data Input/Output */
+#define P42 GPIO_PIN_ADDR(4, 2) /*!< Specify P42 Pin Data Input/Output */
+#define P43 GPIO_PIN_ADDR(4, 3) /*!< Specify P43 Pin Data Input/Output */
+#define P44 GPIO_PIN_ADDR(4, 4) /*!< Specify P44 Pin Data Input/Output */
+#define P45 GPIO_PIN_ADDR(4, 5) /*!< Specify P45 Pin Data Input/Output */
+#define P46 GPIO_PIN_ADDR(4, 6) /*!< Specify P46 Pin Data Input/Output */
+#define P47 GPIO_PIN_ADDR(4, 7) /*!< Specify P47 Pin Data Input/Output */
+/*@}*/ /* end of group M051_GPIO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT7.
+ *
+ * @return None
+ *
+ * @details Clear the interrupt status of specified GPIO pin.
+ */
+#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->ISRC = u32PinMask)
+
+/**
+ * @brief Disable Pin De-bounce Function
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT7.
+ *
+ * @return None
+ *
+ * @details Disable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~u32PinMask)
+
+/**
+ * @brief Enable Pin De-bounce Function
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT7.
+ * @return None
+ *
+ * @details Enable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= u32PinMask)
+
+/**
+ * @brief Disable I/O Digital Input Path
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT7.
+ *
+ * @return None
+ *
+ * @details Disable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->OFFD |= u32PinMask)
+
+/**
+ * @brief Enable I/O Digital Input Path
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT7.
+ *
+ * @return None
+ *
+ * @details Enable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->OFFD &= ~u32PinMask)
+
+/**
+ * @brief Disable I/O DOUT mask
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT7.
+ *
+ * @return None
+ *
+ * @details Disable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DMASK |= u32PinMask)
+
+/**
+ * @brief Enable I/O DOUT mask
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT7.
+ *
+ * @return None
+ *
+ * @details Enable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DMASK &= ~u32PinMask)
+
+/**
+ * @brief Get GPIO Pin Interrupt Flag
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT7.
+ *
+ * @retval 0 No interrupt at specified GPIO pin
+ * @retval 1 The specified GPIO pin generate an interrupt
+ *
+ * @details Get the interrupt status of specified GPIO pin.
+ */
+#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->ISRC & u32PinMask)
+
+/**
+ * @brief Set De-bounce Sampling Cycle Time
+ *
+ * @param[in] clksrc The de-bounce counter clock source. It could be GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_LIRC.
+ * @param[in] clksel The de-bounce sampling cycle selection. It could be \n
+ * GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, GPIO_DBCLKSEL_8, \n
+ * GPIO_DBCLKSEL_16, GPIO_DBCLKSEL_32, GPIO_DBCLKSEL_64, GPIO_DBCLKSEL_128, \n
+ * GPIO_DBCLKSEL_256, GPIO_DBCLKSEL_512, GPIO_DBCLKSEL_1024, GPIO_DBCLKSEL_2048, \n
+ * GPIO_DBCLKSEL_4096, GPIO_DBCLKSEL_8192, GPIO_DBCLKSEL_16384, GPIO_DBCLKSEL_32768.
+ *
+ * @return None
+ *
+ * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
+ * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBNCECON_DBCLKSRC_IRC10K, GPIO_DBNCECON_DBCLKSEL_4). \n
+ * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
+ * Then the target de-bounce sampling cycle time is (2^4)*(1/(10*1000)) s = 16*0.0001 s = 1600 us,
+ * and system will sampling interrupt input once per 1600 us.
+ */
+#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBNCECON = (GPIO_DBNCECON_ICLK_ON_Msk | u32ClkSrc | u32ClkSel))
+
+/**
+ * @brief Get GPIO Port IN Data
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ *
+ * @retval The specified port data
+ *
+ * @details Get the PIN register of specified GPIO port.
+ */
+#define GPIO_GET_IN_DATA(port) ((port)->PIN)
+
+/**
+ * @brief Set GPIO Port OUT Data
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32Data GPIO port data.
+ *
+ * @retval None
+ *
+ * @details Set the Data into specified GPIO port.
+ */
+#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
+
+/**
+ * @brief Toggle Specified GPIO pin
+ *
+ * @param[in] u32Pin Pxy
+ *
+ * @retval None
+ *
+ * @details Toggle the specified GPIO pint.
+ */
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
+
+/**
+ * @brief Enable External GPIO Interrupt 0
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_EnableEINT0 GPIO_EnableInt
+
+
+/**
+ * @brief Disable External GPIO Interrupt 0
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_DisableEINT0 GPIO_DisableInt
+
+
+/**
+ * @brief Enable External GPIO Interrupt 1
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_EnableEINT1 GPIO_EnableInt
+
+
+/**
+ * @brief Disable External GPIO Interrupt 1
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_DisableEINT1 GPIO_DisableInt
+
+
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
+
+
+/*@}*/ /* end of group M051_GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_GPIO_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__GPIO_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/hdiv.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/hdiv.h
new file mode 100644
index 0000000000000000000000000000000000000000..2b8dc7c8b638ade1cbee871c0bfacde7def121c6
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/hdiv.h
@@ -0,0 +1,61 @@
+/**************************************************************************//**
+ * @file DIV.h
+ * @version V2.1
+ * $Revision: 4 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 Series DIV Driver Header File
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __DIVIDER_H__
+#define __DIVIDER_H__
+
+
+/**
+ * @brief Division function to calculate (x/y)
+ *
+ * @param[in] x the dividend of the division
+ * @param[in] y the divisor of the division
+ *
+ * @return The result of (x/y)
+ *
+ * @details This is a division function to calculate x/y
+ *
+ */
+static __INLINE int32_t HDIV_Div(int32_t x, int16_t y)
+{
+ uint32_t *p32;
+
+ p32 = (uint32_t *)HDIV_BASE;
+ *p32++ = x;
+ *p32++ = y;
+ return *p32;
+}
+
+
+/**
+ * @brief To calculate the remainder of x/y, i.e., the result of x mod y.
+ *
+ * @param[in] x the dividend of the division
+ * @param[in] y the divisor of the division
+ *
+ * @return The remainder of (x/y)
+ *
+ * @details This function is used to calculate the remainder of x/y.
+ */
+static __INLINE int16_t HDIV_Mod(int32_t x, int16_t y)
+{
+ uint32_t *p32;
+
+ p32 = (uint32_t *)HDIV_BASE;
+ *p32++ = x;
+ *p32++ = y;
+ return p32[1];
+}
+
+
+#endif
+
+
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/i2c.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/i2c.h
new file mode 100644
index 0000000000000000000000000000000000000000..ce72e5ac06b5e5f25d7250782493cfde7030f543
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/i2c.h
@@ -0,0 +1,187 @@
+/**************************************************************************//**
+ * @file I2C.h
+ * @version V3.0
+ * $Revision: 9 $
+ * $Date: 14/02/10 3:04p $
+ * @brief M051 Series I2C Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "M051Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_I2C_Driver I2C Driver
+ @{
+*/
+
+/** @addtogroup M051_I2C_EXPORTED_CONSTANTS I2C Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* I2CON constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_I2CON_STA_STO_SI 0x38UL /*!< I2CON setting for I2C control bits. It would set STA, STO and SI bits */
+#define I2C_I2CON_STA_STO_SI_AA 0x3CUL /*!< I2CON setting for I2C control bits. It would set STA, STO, SI and AA bits */
+#define I2C_I2CON_STA_SI 0x28UL /*!< I2CON setting for I2C control bits. It would set STA and SI bits */
+#define I2C_I2CON_STA_SI_AA 0x2CUL /*!< I2CON setting for I2C control bits. It would set STA, SI and AA bits */
+#define I2C_I2CON_STO_SI 0x18UL /*!< I2CON setting for I2C control bits. It would set STO and SI bits */
+#define I2C_I2CON_STO_SI_AA 0x1CUL /*!< I2CON setting for I2C control bits. It would set STO, SI and AA bits */
+#define I2C_I2CON_SI 0x08UL /*!< I2CON setting for I2C control bits. It would set SI bit */
+#define I2C_I2CON_SI_AA 0x0CUL /*!< I2CON setting for I2C control bits. It would set SI and AA bits */
+#define I2C_I2CON_STA 0x20UL /*!< I2CON setting for I2C control bits. It would set STA bit */
+#define I2C_I2CON_STO 0x10UL /*!< I2CON setting for I2C control bits. It would set STO bit */
+#define I2C_I2CON_AA 0x04UL /*!< I2CON setting for I2C control bits. It would set AA bit */
+
+/*@}*/ /* end of group M051_I2C_EXPORTED_CONSTANTS */
+
+/** @addtogroup M051_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+ @{
+*/
+/**
+ * @brief The macro is used to set I2C bus condition at One Time
+ *
+ * @param[in] i2c Specify I2C port
+ * @return None
+ *
+ * @details To control I2C bus conditions of START, STOP, SI, ACK.
+ */
+#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->I2CON = ((i2c)->I2CON & ~0x3c) | u8Ctrl)
+
+/**
+ * @brief The macro is used to set START condition of I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ * @return None
+ *
+ * @details To set the I2C bus START condition
+ */
+#define I2C_START(i2c) ((i2c)->I2CON = ((i2c)->I2CON & ~I2C_I2CON_SI_Msk) | I2C_I2CON_STA_Msk)
+
+/**
+ * @brief The macro is used to set STOP condition of I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ * @return None
+ *
+ * @details To set the I2C bus STOP condition
+ */
+#define I2C_STOP(i2c) ((i2c)->I2CON = ((i2c)->I2CON & ~I2C_I2CON_SI_Msk) | I2C_I2CON_STO_Msk)
+
+/**
+ * @brief The macro is used to wait I2C bus status get ready
+ *
+ * @param[in] i2c Specify I2C port
+ * @return None
+ *
+ * @details When a new status is presented of I2C bus, SI flag will be set.
+ */
+#define I2C_WAIT_READY(i2c) while(!((i2c)->I2CON & I2C_I2CON_SI_Msk))
+
+/**
+ * @brief The macro is used to Read I2C Bus Data Register
+ *
+ * @param[in] i2c Specify I2C port
+ * @return A byte of I2C data register
+ *
+ * @details I2C controller read data from bus and save it in I2CDAT
+ */
+#define I2C_GET_DATA(i2c) ((i2c)->I2CDAT)
+
+/**
+ * @brief The macro is used to write a Data to I2C Data Register
+ *
+ * @param[in] i2c Specify I2C port
+ * @return None
+ *
+ * @details I2C controller send a byte data to bus.
+ */
+#define I2C_SET_DATA(i2c, u8Data) ((i2c)->I2CDAT = u8Data)
+
+/**
+ * @brief The macro is used to get I2C Bus Status Code
+ *
+ * @param[in] i2c Specify I2C port
+ * @return I2C status code
+ *
+ * @details To get ths status code of I2C Bus.
+ */
+#define I2C_GET_STATUS(i2c) ((i2c)->I2CSTATUS)
+
+/**
+ * @brief The macro is used to get time-out flag
+ *
+ * @param[in] i2c Specify I2C port
+ * @return Time-out flag status
+ * @retval 0 Bus time-out is not happened
+ * @retval 1 Bus time-out is happened
+ *
+ * @details To get time-out flag of I2C bus
+ */
+#define I2C_GET_TIMEOUT_FLAG(i2c) ( (i2c->I2CTOC & I2C_I2CTOC_TIF_Msk) == I2C_I2CTOC_TIF_Msk ? 1:0 )
+
+/**
+ * @brief The macro is used to get wake-up flag
+ *
+ * @param[in] i2c Specify I2C port
+ * @return Wake-up flag status
+ * @retval 0 Chip is not woken-up from power-down mode
+ * @retval 1 Chip is woken-up from power-down mode
+ *
+ * @detail To get wake-up status of I2C bus
+ */
+#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->I2CWKUPSTS & I2C_I2CWKUPSTS_WKUPIF_Msk) == I2C_I2CWKUPSTS_WKUPIF_Msk ? 1:0 )
+
+/**
+ * @brief The macro is used to clear wake-up flag
+ *
+ * @param[in] i2c Specify I2C port
+ * @return None
+ *
+ * @detail To clear wake-up flag of I2C bus when wake-up flag is set.
+ */
+#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->I2CWKUPSTS |= I2C_I2CWKUPSTS_WKUPIF_Msk)
+
+void I2C_ClearTimeoutFlag(I2C_T *i2c);
+void I2C_Close(I2C_T *i2c);
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
+void I2C_DisableInt(I2C_T *i2c);
+void I2C_EnableInt(I2C_T *i2c);
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
+uint32_t I2C_GetIntFlag(I2C_T *i2c);
+uint32_t I2C_GetStatus(I2C_T *i2c);
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
+uint8_t I2C_GetData(I2C_T *i2c);
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
+uint32_t I2C_SetClockBusFreq(I2C_T *i2c, uint32_t u32BusClock);
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
+void I2C_DisableTimeout(I2C_T *i2c);
+void I2C_EnableWakeup(I2C_T *i2c);
+void I2C_DisableWakeup(I2C_T *i2c);
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
+
+/*@}*/ /* end of group M051_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_I2C_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+#endif //__I2C_H__
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/pwm.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/pwm.h
new file mode 100644
index 0000000000000000000000000000000000000000..61a7f07d5fc9105ef9d8402de7bf822e765d53b5
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/pwm.h
@@ -0,0 +1,275 @@
+/**************************************************************************//**
+ * @file pwm.h
+ * @version V1.00
+ * $Revision: 8 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series PWM driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_PWM_Driver PWM Driver
+ @{
+*/
+
+/** @addtogroup M051_PWM_EXPORTED_CONSTANTS PWM Exported Constants
+ @{
+*/
+#define PWM_CHANNEL_NUM (4) /*!< PWM channel number */
+#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 */
+#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 */
+#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 */
+#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 */
+#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 */
+#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type */
+#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type */
+#define PWM_DUTY_TRIGGER_ADC (PWM_TCON_PWM0DTEN_Msk) /*!< PWM trigger ADC while counter matches CMR in edge-aligned or center-aligned mode */
+#define PWM_PERIOD_TRIGGER_ADC (PWM_TCON_PWM0TEN_Msk) /*!< PWM trigger ADC while counter matches 0 in edge-aligned mode or matches (CNR+1) or zero in center-aligned mode */
+#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMR (0) /*!< PWM duty interrupt triggered if down count match CMR */
+#define PWM_DUTY_INT_UP_COUNT_MATCH_CMR (PWM_PIER_INT01DTYPE_Msk) /*!< PWM duty interrupt triggered if up down match CMR */
+#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt triggered if counter underflow */
+#define PWM_PERIOD_INT_MATCH_CNR (PWM_PIER_INT01TYPE_Msk) /*!< PWM period interrupt triggered if counter match CNR */
+#define PWM_CAPTURE_INT_RISING_LATCH (PWM_CCR0_CRL_IE0_Msk) /*!< PWM capture interrupt if channel has rising transition */
+#define PWM_CAPTURE_INT_FALLING_LATCH (PWM_CCR0_CFL_IE0_Msk) /*!< PWM capture interrupt if channel has falling transition */
+/*---------------------------------------------------------------------------------------------------------*/
+/* PWM Group channel number constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_CH0 0x0 /*!< PWM Group A/B channel 0 */
+#define PWM_CH1 0x1 /*!< PWM Group A/B channel 1 */
+#define PWM_CH2 0x2 /*!< PWM Group A/B channel 2 */
+#define PWM_CH3 0x3 /*!< PWM Group A/B channel 3 */
+#define PWM_CCR_MASK 0x000F000F /*!< PWM CCR0/CCR2 bit0~3 and bit16~19 mask */
+
+/*@}*/ /* end of group M051_PWM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enable timer synchronous mode of specified channel(s)
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable timer synchronous mode of specified channel(s)
+ */
+#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask) \
+ do{ \
+ int i;\
+ for(i = 0; i < 4; i++) { \
+ if((u32ChannelMask) & (1 << i)) \
+ (pwm)->PSCR |= (PWM_PSCR_PSSEN0_Msk << (i * 8)); \
+ } \
+ }while(0)
+
+/**
+ * @brief Disable timer synchronous mode of specified channel(s)
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to disable timer synchronous mode of specified channel(s)
+ */
+#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
+ do{ \
+ int i;\
+ for(i = 0; i < 4; i++) { \
+ if((u32ChannelMask) & (1 << i)) \
+ (pwm)->PSCR &= ~(PWM_PSCR_PSSEN0_Msk << (i * 8)); \
+ } \
+ }while(0)
+
+/**
+ * @brief Enable output inverter of specified channel(s)
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable capture input inverter for specified channel(s)
+ */
+#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) \
+ do{ \
+ int i;\
+ (pwm)->PCR &= ~(PWM_PCR_CH0INV_Msk|PWM_PCR_CH1INV_Msk|PWM_PCR_CH2INV_Msk|PWM_PCR_CH3INV_Msk);\
+ for(i = 0; i < 4; i++) { \
+ if((u32ChannelMask) & (1 << i)) \
+ (pwm)->PCR |= (PWM_PCR_CH0INV_Msk << (PWM_PCR_CH0INV_Pos * (i * 4))); \
+ } \
+ }while(0)
+
+/**
+ * @brief Get captured rising data of specified channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return uint32_t Return the timer counter, 0~0xFFFF
+ * @details This macro is used to get captured rising data for specified channel
+ */
+#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CRLR0)) + (u32ChannelNum) * 8))))
+
+/**
+ * @brief Get captured falling data of specified channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return uint32_t Return the timer counter, 0~0xFFFF
+ * @details This macro is used to get captured falling data for specified channel
+ */
+#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CFLR0)) + (u32ChannelNum) * 8))))
+
+/**
+ * @brief Set the prescaler of the selected channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
+ * @return None
+ * @details This macro is used to set timer pre-scale for specified channel
+ * @note - If u32Prescaler = 0, corresponding PWM-timer will be stopped
+ * - If u32Prescaler = x (x not equal to 0), it means Clock input is divided by (x + 1) before it is fed to the corresponding PWM counter.
+ */
+#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
+ ((pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_CP01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
+
+/**
+ * @brief Set the divider of the selected channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Divider Clock divider of specified channel. Valid values are
+ * - \ref PWM_CLK_DIV_1
+ * - \ref PWM_CLK_DIV_2
+ * - \ref PWM_CLK_DIV_4
+ * - \ref PWM_CLK_DIV_8
+ * - \ref PWM_CLK_DIV_16
+ * @return None
+ * @details This macro is used to set Timer clock source divider selection for specified channel
+ */
+#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
+ ((pwm)->CSR = ((pwm)->CSR & ~(PWM_CSR_CSR0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
+
+/**
+ * @brief Set the duty of the selected channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set PWM Comparator value for specified channel
+ * @note This new setting will take effect on next PWM period
+ */
+#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CMR0)) + (u32ChannelNum) * 12))) = u32CMR)
+
+/**
+ * @brief Set the period of the selected channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set timer loaded value(CNR) for specified channel.\n
+ * Loaded value determines the PWM period.
+ * @note This new setting will take effect on next PWM period
+ * @note PWM counter will stop if period length set to 0
+ */
+#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->CNR0)) + (u32ChannelNum) * 12))) = u32CNR)
+
+/**
+ * @brief Set the PWM aligned type
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32AlignedType PWM aligned type, valid values are:
+ * - \ref PWM_EDGE_ALIGNED
+ * - \ref PWM_CENTER_ALIGNED
+ * @return None
+ * @details This macro is used to set the PWM aligned type
+ */
+#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
+ do{ \
+ int i; \
+ for(i = 0; i < 4; i++) { \
+ if((u32ChannelMask) & (1 << i)) \
+ (pwm)->PCR = ((pwm)->PCR & ~(PWM_PCR_PWM01TYPE_Msk << (i >> 1))) | (u32AlignedType << (PWM_PCR_PWM01TYPE_Pos + (i >> 1))); \
+ } \
+ }while(0)
+
+
+uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32UnitTimeNsec,
+ uint32_t u32CaptureEdge);
+uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32Frequncy,
+ uint32_t u32DutyCycle);
+void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
+void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
+void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+
+
+
+/*@}*/ /* end of group M051_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_PWM_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PWM_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/spi.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/spi.h
new file mode 100644
index 0000000000000000000000000000000000000000..a943dab5fd11dfb196832fbed14af3721baefacd
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/spi.h
@@ -0,0 +1,267 @@
+/**************************************************************************//**
+ * @file spi.h
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series SPI driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_SPI_Driver SPI Driver
+ @{
+*/
+
+/** @addtogroup M051_SPI_EXPORTED_CONSTANTS SPI Exported Constants
+ @{
+*/
+
+#define SPI_MODE_0 (SPI_CNTRL_TX_NEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
+#define SPI_MODE_1 (SPI_CNTRL_RX_NEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
+#define SPI_MODE_2 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_RX_NEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
+#define SPI_MODE_3 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_TX_NEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
+
+#define SPI_SLAVE (SPI_CNTRL_SLAVE_Msk) /*!< Set as slave */
+#define SPI_MASTER (0x0) /*!< Set as master */
+
+#define SPI_SS (SPI_SSR_SSR_Msk) /*!< Set SS */
+#define SPI_SS_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS active high */
+#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
+
+#define SPI_UNIT_INT_MASK (0x01) /*!< Unit transfer interrupt mask */
+#define SPI_SSTA_INT_MASK (0x02) /*!< Slave 3-Wire mode start interrupt mask */
+#define SPI_FIFO_TX_INT_MASK (0x04) /*!< FIFO TX interrupt mask */
+#define SPI_FIFO_RX_INT_MASK (0x08) /*!< FIFO RX interrupt mask */
+#define SPI_FIFO_RXOV_INT_MASK (0x10) /*!< FIFO RX overrun interrupt mask */
+#define SPI_FIFO_TIMEOUT_INT_MASK (0x20) /*!< FIFO RX timeout interrupt mask */
+
+#define SPI_BUSY_MASK (0x01) /*!< Busy status mask */
+#define SPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
+#define SPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
+#define SPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
+#define SPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
+
+/*@}*/ /* end of group M051_SPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Abort the current transfer in slave 3-wire mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_ABORT_3WIRE_TRANSFER(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_SLV_ABORT_Msk)
+
+/**
+ * @brief Clear the slave 3-wire mode start interrupt flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_SLV_START_INTSTS_Msk)
+
+/**
+ * @brief Clear the unit transfer interrupt flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->CNTRL |= SPI_CNTRL_IF_Msk))
+
+/**
+ * @brief Disable slave 3-wire mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->CNTRL2 &= ~SPI_CNTRL2_NOSLVSEL_Msk)
+
+/**
+ * @brief Enable slave 3-wire mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->CNTRL2 |= SPI_CNTRL2_NOSLVSEL_Msk)
+
+/**
+ * @brief Get the count of available data in RX FIFO.
+ * @param[in] spi is the base address of SPI module.
+ * @return The count of available data in RX FIFO.
+ */
+#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RX_FIFO_COUNT_Msk) >> SPI_STATUS_RX_FIFO_COUNT_Pos)
+
+/**
+ * @brief Get the RX FIFO empty flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return RX FIFO empty flag
+ * @retval 0: RX FIFO is not empty
+ * @retval 1: RX FIFO is empty
+ */
+#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk)>>SPI_STATUS_RX_EMPTY_Pos)
+
+/**
+ * @brief Get the TX FIFO empty flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return Tx FIFO empty flag
+ * @retval 0: TX FIFO is not empty
+ * @retval 1: TX FIFO is empty
+ */
+#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk)>>SPI_STATUS_TX_EMPTY_Pos)
+
+/**
+ * @brief Get the TX FIFO full flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return TX FIFO full flag
+ * @retval 0: TX FIFO is not full
+ * @retval 1: TX FIFO is full
+ */
+#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TX_FULL_Msk)>>SPI_STATUS_TX_FULL_Pos)
+
+/**
+ * @brief Get the datum read from RX0 register.
+ * @param[in] spi is the base address of SPI module.
+ * @return Data in RX0 register
+ */
+#define SPI_READ_RX0(spi) ((spi)->RX0)
+
+/**
+ * @brief Get the datum read from RX1 register.
+ * @param[in] spi is the base address of SPI module.
+ * @return Data in RX1 register
+ */
+#define SPI_READ_RX1(spi) ((spi)->RX1)
+
+/**
+ * @brief Write datum to TX0 register.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
+ * @return None
+ */
+#define SPI_WRITE_TX0(spi, u32TxData) ((spi)->TX0 = (u32TxData))
+
+/**
+ * @brief Write datum to TX1 register.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
+ * @return None
+ */
+#define SPI_WRITE_TX1(spi, u32TxData) ((spi)->TX1 = (u32TxData))
+
+/**
+ * @brief Disable automatic slave select function and set SPI_SS pin to high state.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_SET_SS_HIGH(spi) ((spi)->SSR = ((spi)->SSR & (~SPI_SSR_AUTOSS_Msk)) | (SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk))
+
+/**
+ * @brief Disable automatic slave select function and set SPI_SS pin to low state.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_SET_SS_LOW(spi) ((spi)->SSR = ((spi)->SSR & (~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk))) | SPI_SSR_SSR_Msk)
+
+/**
+ * @brief Enable byte reorder function.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CNTRL = ((spi)->CNTRL & (~SPI_CNTRL_REORDER_Msk)) | (1<CNTRL &= ~SPI_CNTRL_REORDER_Msk)
+
+/**
+ * @brief Set the length of suspend interval.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32SuspCycle decides the length of suspend interval.
+ * @return None
+ */
+#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_SP_CYCLE_Msk) | ((u32SuspCycle) << SPI_CNTRL_SP_CYCLE_Pos))
+
+/**
+ * @brief Set the SPI transfer sequence with LSB first.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_SET_LSB_FIRST(spi) ((spi)->CNTRL |= SPI_CNTRL_LSB_Msk)
+
+/**
+ * @brief Set the SPI transfer sequence with MSB first.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_SET_MSB_FIRST(spi) ((spi)->CNTRL &= ~SPI_CNTRL_LSB_Msk)
+
+/**
+ * @brief Set the data width of a SPI transaction.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32Width is the bit width of transfer data.
+ * @return None
+ */
+#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_TX_BIT_LEN_Msk) | (((u32Width)&0x1F) << SPI_CNTRL_TX_BIT_LEN_Pos))
+
+/**
+ * @brief Get the SPI busy state.
+ * @param[in] spi is the base address of SPI module.
+ * @return SPI busy status
+ * @retval 0: SPI module is not busy
+ * @retval 1: SPI module is busy
+ */
+#define SPI_IS_BUSY(spi) ( ((spi)->CNTRL & SPI_CNTRL_GO_BUSY_Msk)>>SPI_CNTRL_GO_BUSY_Pos )
+
+/**
+ * @brief Set the GO_BUSY bit to trigger SPI transfer.
+ * @param[in] spi is the base address of SPI module.
+ * @return None
+ */
+#define SPI_TRIGGER(spi) ((spi)->CNTRL |= SPI_CNTRL_GO_BUSY_Msk)
+
+
+/* Function prototype declaration */
+uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void SPI_Close(SPI_T *spi);
+void SPI_ClearRxFIFO(SPI_T *spi);
+void SPI_ClearTxFIFO(SPI_T *spi);
+void SPI_DisableAutoSS(SPI_T *spi);
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
+void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+void SPI_DisableFIFO(SPI_T *spi);
+uint32_t SPI_GetBusClock(SPI_T *spi);
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
+
+/*@}*/ /* end of group M051_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_SPI_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SPI_H__
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/sys.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/sys.h
new file mode 100644
index 0000000000000000000000000000000000000000..2f07782baeb649951b713e97f14769c4a5ef2292
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/sys.h
@@ -0,0 +1,499 @@
+/**************************************************************************//**
+ * @file SYS.h
+ * @version V2.1
+ * $Revision: 10 $
+ * $Date: 14/02/05 1:17p $
+ * @brief M051 Series Global Control and Clock Control Driver Header File
+ *
+ * @note
+ * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __SYS_H__
+#define __SYS_H__
+
+
+#include "M051Series.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_SYS_Driver SYS Driver
+ @{
+*/
+
+/** @addtogroup M051_SYS_EXPORTED_CONSTANTS SYS Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Module Reset Control Resister constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CHIP_RST ((0x0<<24) | SYS_IPRSTC1_CPU_RST_Pos ) /*!< CPU reset is one of the SYS_ResetModule parameter */
+#define CPU_RST ((0x0<<24) | SYS_IPRSTC1_CHIP_RST_Pos ) /*!< CHIP reset is one of the SYS_ResetModule parameter */
+#define EBI_RST ((0x0<<24) | SYS_IPRSTC1_EBI_RST_Pos ) /*!< EBI reset is one of the SYS_ResetModule parameter */
+#define HDIV_RST ((0x0<<24) | SYS_IPRSTC1_HDIV_RST_Pos ) /*!< HDIV reset is one of the SYS_ResetModule parameter */
+#define GPIO_RST ((0x4<<24) | SYS_IPRSTC2_GPIO_RST_Pos ) /*!< GPIO reset is one of the SYS_ResetModule parameter */
+#define TMR0_RST ((0x4<<24) | SYS_IPRSTC2_TMR0_RST_Pos ) /*!< TMR0 reset is one of the SYS_ResetModule parameter */
+#define TMR1_RST ((0x4<<24) | SYS_IPRSTC2_TMR1_RST_Pos ) /*!< TMR1 reset is one of the SYS_ResetModule parameter */
+#define TMR2_RST ((0x4<<24) | SYS_IPRSTC2_TMR2_RST_Pos ) /*!< TMR2 reset is one of the SYS_ResetModule parameter */
+#define TMR3_RST ((0x4<<24) | SYS_IPRSTC2_TMR3_RST_Pos ) /*!< TMR3 reset is one of the SYS_ResetModule parameter */
+#define I2C0_RST ((0x4<<24) | SYS_IPRSTC2_I2C0_RST_Pos ) /*!< I2C0 reset is one of the SYS_ResetModule parameter */
+#define I2C1_RST ((0x4<<24) | SYS_IPRSTC2_I2C1_RST_Pos ) /*!< I2C1 reset is one of the SYS_ResetModule parameter */
+#define SPI0_RST ((0x4<<24) | SYS_IPRSTC2_SPI0_RST_Pos ) /*!< SPI0 reset is one of the SYS_ResetModule parameter */
+#define SPI1_RST ((0x4<<24) | SYS_IPRSTC2_SPI1_RST_Pos ) /*!< SPI1 reset is one of the SYS_ResetModule parameter */
+#define UART0_RST ((0x4<<24) | SYS_IPRSTC2_UART0_RST_Pos ) /*!< UART0 reset is one of the SYS_ResetModule parameter */
+#define UART1_RST ((0x4<<24) | SYS_IPRSTC2_UART1_RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */
+#define PWM03_RST ((0x4<<24) | SYS_IPRSTC2_PWM03_RST_Pos ) /*!< PWM03 reset is one of the SYS_ResetModule parameter */
+#define PWM47_RST ((0x4<<24) | SYS_IPRSTC2_PWM47_RST_Pos ) /*!< PWM47 reset is one of the SYS_ResetModule parameter */
+#define ACMP01_RST ((0x4<<24) | SYS_IPRSTC2_ACMP01_RST_Pos ) /*!< ACMP01 reset is one of the SYS_ResetModule parameter */
+#define ACMP23_RST ((0x4<<24) | SYS_IPRSTC2_ACMP23_RST_Pos ) /*!< ACMP23 reset is one of the SYS_ResetModule parameter */
+#define ADC_RST ((0x4<<24) | SYS_IPRSTC2_ADC_RST_Pos ) /*!< ADC reset is one of the SYS_ResetModule parameter */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Brown Out Detector Threshold Voltage Selection constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_BODCR_BOD_RST_EN (1UL<BODCR |= SYS_BODCR_BOD_INTF_Msk)
+
+/**
+ * @brief This macro set Brown-out detect to normal mode.
+ * @return None
+ */
+#define SYS_CLEAR_BOD_LPM() (SYS->BODCR &= ~SYS_BODCR_BOD_LPM_Msk)
+
+/**
+ * @brief This macro disable Brown-out detect function.
+ * @return None
+ */
+#define SYS_DISABLE_BOD() (SYS->BODCR &= ~SYS_BODCR_BOD_EN_Msk)
+
+/**
+ * @brief This macro enable Brown-out detect function.
+ * @return None
+ */
+#define SYS_ENABLE_BOD() (SYS->BODCR |= SYS_BODCR_BOD_EN_Msk)
+
+/**
+ * @brief This macro get Brown-out detect interrupt flag.
+ * @return 0: Brown-out detect interrupt flag is not set.
+ * 1: Brown-out detect interrupt flag is set.
+ */
+#define SYS_GET_BOD_INT_FLAG() ((SYS->BODCR & SYS_BODCR_BOD_INTF_Msk)>>SYS_BODCR_BOD_INTF_Pos)
+
+/**
+ * @brief This macro get Brown-out detector output status.
+ * @return 0: System voltage is higher than BOD_VL setting or BOD_EN is 0.
+ * 1: System voltage is lower than BOD_VL setting.
+ * @details If the BOD_EN is 0, this function always return 0.
+ */
+#define SYS_GET_BOD_OUTPUT() ((SYS->BODCR & SYS_BODCR_BOD_OUT_Msk)>>SYS_BODCR_BOD_OUT_Msk)
+
+/**
+ * @brief This macro enable Brown-out detect interrupt function.
+ * @return None
+ */
+#define SYS_DISABLE_BOD_RST() (SYS->BODCR &= ~SYS_BODCR_BOD_RSTEN_Msk)
+
+/**
+ * @brief This macro enable Brown-out detect reset function.
+ * @return None
+ */
+#define SYS_ENABLE_BOD_RST() (SYS->BODCR |= SYS_BODCR_BOD_RSTEN_Msk)
+
+/**
+ * @brief This macro set Brown-out detect to low power mode.
+ * @return None
+ */
+#define SYS_SET_BOD_LPM() (SYS->BODCR |= SYS_BODCR_BOD_LPM_Msk)
+
+/**
+ * @brief This macro set Brown-out detect voltage level.
+ * @param u32Level is Brown-out voltage level. Including :
+ * - \ref SYS_BODCR_BOD_VL_4_4V
+ * - \ref SYS_BODCR_BOD_VL_3_7V
+ * - \ref SYS_BODCR_BOD_VL_2_7V
+ * - \ref SYS_BODCR_BOD_VL_2_2V
+ * @return None
+ */
+#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_VL_Msk) | u32Level)
+
+/**
+ * @brief This macro get previous reset source is from Brown-out detect reset.
+ * @return 0: Previous reset source is not from Brown-out detect reset
+ * 1: Previous reset source is from Brown-out detect reset
+ */
+#define SYS_IS_BOD_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_BOD_Msk)
+
+/**
+ * @brief This macro get previous reset source is from Low-Voltage-Reset.
+ * @return 0: Previous reset source is not from CPU reset
+ * 1: Previous reset source is from CPU reset
+ */
+#define SYS_IS_CPU_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_CPU_Msk)
+
+/**
+ * @brief This macro get previous reset source is from Power-on Reset.
+ * @return 0: Previous reset source is not from Low-Voltage-Reset
+ * 1: Previous reset source is from Low-Voltage-Reset
+ */
+#define SYS_IS_POR_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_POR_Msk)
+
+/**
+ * @brief This macro get previous reset source is from reset pin reset.
+ * @return 0: Previous reset source is not from Power-on Reset
+ * 1: Previous reset source is from Power-on Reset
+ */
+#define SYS_IS_RSTPIN_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_RESET_Msk)
+
+/**
+ * @brief This macro get previous reset source is from system reset.
+ * @return 0: Previous reset source is not from reset pin reset
+ * 1: Previous reset source is from reset pin reset
+ */
+#define SYS_IS_SYSTEM_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_MCU_Msk)
+
+/**
+ * @brief This macro get previous reset source is from window watch dog reset.
+ * @return 0: Previous reset source is not from reset system reset
+ * 1: Previous reset source is from reset system reset
+ */
+#define SYS_IS_WDT_RST() (SYS->RSTSRC & SYS_RSTSRC_RSTS_WDT_Msk)
+
+/**
+ * @brief This macro disable Low-Voltage-Reset function.
+ * @return None
+ */
+#define SYS_DISABLE_LVR() (SYS->BODCR &= ~SYS_BODCR_LVR_EN_Msk)
+
+/**
+ * @brief This macro enable Low-Voltage-Reset function.
+ * @return None
+ */
+#define SYS_ENABLE_LVR() (SYS->BODCR |= SYS_BODCR_LVR_EN_Msk)
+
+/**
+ * @brief This macro disable Power-on Reset function.
+ * @return None
+ */
+#define SYS_DISABLE_POR() (SYS->PORCR = 0x5AA5)
+
+/**
+ * @brief This macro enable Power-on Reset function.
+ * @return None
+ */
+#define SYS_ENABLE_POR() (SYS->PORCR = 0)
+
+/**
+ * @brief This macro clear reset source flag.
+ * @param u32RstSrc is reset source.
+ * @return None
+ */
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RSTSRC | u32RstSrc )
+
+/**
+ * @brief This function enable register write-protection function
+ * @return None
+ * @details To lock the protected register to forbid write access
+ */
+static __INLINE void SYS_LockReg(void)
+{
+ SYS->REGWRPROT = 0;
+}
+
+/**
+ * @brief This function disable register write-protection function
+ * @return None
+ * @details To unlock the protected register to allow write access
+ */
+static __INLINE void SYS_UnlockReg(void)
+{
+ while(SYS->REGWRPROT != SYS_REGWRPROT_REGPROTDIS_Msk)
+ {
+ SYS->REGWRPROT = 0x59;
+ SYS->REGWRPROT = 0x16;
+ SYS->REGWRPROT = 0x88;
+ }
+}
+
+
+
+
+void SYS_ClearResetSrc(uint32_t u32Src);
+uint32_t SYS_GetBODStatus(void);
+uint32_t SYS_GetResetSrc(void);
+uint32_t SYS_IsRegLocked(void);
+uint32_t SYS_ReadPDID(void);
+void SYS_ResetChip(void);
+void SYS_ResetCPU(void);
+void SYS_ResetModule(uint32_t u32ModuleIndex);
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
+void SYS_DisableBOD(void);
+
+
+/*@}*/ /* end of group M051_SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_SYS_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SYS_H__
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/timer.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/timer.h
new file mode 100644
index 0000000000000000000000000000000000000000..d0d53d42f579c8028cad51f09e1a9635d54da5e4
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/timer.h
@@ -0,0 +1,312 @@
+/**************************************************************************//**
+ * @file timer.h
+ * @version V3.00
+ * $Revision: 6 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series Timer driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_TIMER_Driver TIMER Driver
+ @{
+*/
+
+/** @addtogroup M051_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
+ @{
+*/
+
+#define TIMER_ONESHOT_MODE (0UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in one-shot mode */
+#define TIMER_PERIODIC_MODE (1UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in periodic mode */
+#define TIMER_TOGGLE_MODE (2UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in toggle-output mode */
+#define TIMER_CONTINUOUS_MODE (3UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in continuous counting mode */
+#define TIMER_CONTINUOUS_MODE (3UL << TIMER_TCSR_MODE_Pos) /*!< Timer working in continuous counting mode */
+#define TIMER_CAPTURE_FROM_TXEX_PIN (0UL << TIMER_TCSR_CAP_SRC_Pos) /*!< Timer capture source is from TxEX pin */
+#define TIMER_CAPTURE_FROM_INTERNAL_ACMP (1UL << TIMER_TCSR_CAP_SRC_Pos) /*!< Timer capture source is from internal ACMP output signal */
+#define TIMER_TOUT_PIN_FROM_TX_PIN (0UL << TIMER_TCSR_TOUT_SEL_Pos) /*!< Timer toggle-output pin is from Tx pin */
+#define TIMER_TOUT_PIN_FROM_TXEX_PIN (1UL << TIMER_TCSR_TOUT_SEL_Pos) /*!< Timer toggle-output pin is from TxEX pin */
+#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_TEXCON_RSTCAPSEL_Pos) /*!< Timer capture event to get timer counter value */
+#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_TEXCON_RSTCAPSEL_Pos) /*!< Timer capture event to reset timer counter */
+#define TIMER_CAPTURE_FALLING_EDGE (0UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Falling edge trigger timer capture */
+#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Rising edge trigger timer capture */
+#define TIMER_CAPTURE_FALLING_AND_RISING_EDGE (2UL << TIMER_TEXCON_TEX_EDGE_Pos) /*!< Both falling and rising edge trigger timer capture */
+#define TIMER_COUNTER_FALLING_EDGE (0UL << TIMER_TEXCON_TX_PHASE_Pos) /*!< Counter increase on falling edge */
+#define TIMER_COUNTER_RISING_EDGE (1UL << TIMER_TEXCON_TX_PHASE_Pos) /*!< Counter increase on rising edge */
+
+/*@}*/ /* end of group M051_TIMER_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set Timer Compare Value
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set new Timer compared value.
+ */
+#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->TCMPR = (u32Value))
+
+/**
+ * @brief Set Timer Prescale Value
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set new Timer prescale value.
+ * @note Clock input is divided by (prescale + 1) before it is fed into timer.
+ */
+#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->TCSR = ((timer)->TCSR & ~TIMER_TCSR_PRESCALE_Msk) | (u32Value))
+
+/**
+ * @brief Check specify Timer Status
+ *
+ * @return Timer counter is activate or inactivate
+ * @retval 0 Timer 24-bit up counter is inactive
+ * @retval 1 Timer 24-bit up counter is active
+ *
+ * @details This macro is used to check if specify Timer is inactive or active.
+ */
+#define TIMER_IS_ACTIVE(timer) ((timer)->TCSR & TIMER_TCSR_CACT_Msk ? 1 : 0)
+
+/**
+ * @brief Select Toggle-output Pin
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32ToutSel Toggle-output pin selection, valid values are:
+ * - \ref TIMER_TOUT_PIN_FROM_TX_PIN
+ * - \ref TIMER_TOUT_PIN_FROM_TXEX_PIN
+ *
+ * @return None
+ *
+ * @details This macro is used to select Timer toggle-output pin.
+ */
+#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->TCSR = ((timer)->TCSR & ~TIMER_TCSR_TOUT_SEL_Msk) | (u32ToutSel))
+
+/**
+ * @details This function is used to start Timer counting.
+ */
+static __INLINE void TIMER_Start(TIMER_T *timer)
+{
+ timer->TCSR |= TIMER_TCSR_CEN_Msk;
+}
+
+/**
+ * @details This function is used to stop Timer counting.
+ */
+static __INLINE void TIMER_Stop(TIMER_T *timer)
+{
+ timer->TCSR &= ~TIMER_TCSR_CEN_Msk;
+}
+
+/**
+ * @details This function is used to enable the Timer wake-up function.
+ * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
+ */
+static __INLINE void TIMER_EnableWakeup(TIMER_T *timer)
+{
+ timer->TCSR |= TIMER_TCSR_WAKE_EN_Msk;
+}
+
+/**
+ * @details This function is used to disable the Timer wake-up function.
+ */
+static __INLINE void TIMER_DisableWakeup(TIMER_T *timer)
+{
+ timer->TCSR &= ~TIMER_TCSR_WAKE_EN_Msk;
+}
+
+/**
+ * @details This function is used to enable the capture pin detection de-bounce function.
+ */
+static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
+{
+ timer->TEXCON |= TIMER_TEXCON_TEXDB_Msk;
+}
+
+/**
+ * @details This function is used to disable the capture pin detection de-bounce function.
+ */
+static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
+{
+ timer->TEXCON &= ~TIMER_TEXCON_TEXDB_Msk;
+}
+
+/**
+ * @details This function is used to enable the counter pin detection de-bounce function.
+ */
+static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
+{
+ timer->TEXCON |= TIMER_TEXCON_TCDB_Msk;
+}
+
+/**
+ * @details This function is used to disable the counter pin detection de-bounce function.
+ */
+static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
+{
+ timer->TEXCON &= ~TIMER_TEXCON_TCDB_Msk;
+}
+
+/**
+ * @details This function is used to enable the Timer time-out interrupt function.
+ */
+static __INLINE void TIMER_EnableInt(TIMER_T *timer)
+{
+ timer->TCSR |= TIMER_TCSR_IE_Msk;
+}
+
+/**
+ * @details This function is used to disable the Timer time-out interrupt function.
+ */
+static __INLINE void TIMER_DisableInt(TIMER_T *timer)
+{
+ timer->TCSR &= ~TIMER_TCSR_IE_Msk;
+}
+
+/**
+ * @details This function is used to enable the Timer capture trigger interrupt function.
+ */
+static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
+{
+ timer->TEXCON |= TIMER_TEXCON_TEXIEN_Msk;
+}
+
+/**
+ * @details This function is used to disable the Timer capture trigger interrupt function.
+ */
+static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
+{
+ timer->TEXCON &= ~TIMER_TEXCON_TEXIEN_Msk;
+}
+
+/**
+ * @brief Get Timer Time-out Interrupt Flag
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Timer time-out interrupt occurred or not
+ * @retval 0 Timer time-out interrupt did not occur
+ * @retval 1 Timer time-out interrupt occurred
+ *
+ * @details This function indicates Timer time-out interrupt occurred or not.
+ */
+static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
+{
+ return (timer->TISR & TIMER_TISR_TIF_Msk ? 1 : 0);
+}
+
+/**
+ * @details This function clears Timer time-out interrupt flag.
+ */
+static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
+{
+ timer->TISR = TIMER_TISR_TIF_Msk;
+}
+
+/**
+ * @brief Get Timer Capture Interrupt Flag
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Timer capture interrupt occurred or not
+ * @retval 0 Timer capture interrupt did not occur
+ * @retval 1 Timer capture interrupt occurred
+ *
+ * @details This function indicates Timer capture interrupt occurred or not.
+ */
+static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
+{
+ return timer->TEXISR;
+}
+
+/**
+ * @details This function clears Timer capture interrupt flag.
+ */
+static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
+{
+ timer->TEXISR = TIMER_TEXISR_TEXIF_Msk;
+}
+
+/**
+ * @brief Get Timer Wakeup Flag
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Timer has waked up system or not
+ * @retval 0 Timer did not wake up system
+ * @retval 1 Timer Timer wake up system
+ *
+ * @details This function indicates Timer has waked up system or not.
+ */
+static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
+{
+ return (timer->TISR & TIMER_TISR_TWF_Msk ? 1 : 0);
+}
+
+/**
+ * @details This function clears the Timer wake-up system flag.
+ */
+static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
+{
+ timer->TISR = TIMER_TISR_TWF_Msk;
+}
+
+/**
+ * @details This function reports the current timer capture data value.
+ */
+static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
+{
+ return timer->TCAP;
+}
+
+/**
+ * @details This function reports the current timer counter value.
+ */
+static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
+{
+ return timer->TDR;
+}
+
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
+void TIMER_Close(TIMER_T *timer);
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
+void TIMER_DisableCapture(TIMER_T *timer);
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
+void TIMER_DisableEventCounter(TIMER_T *timer);
+uint32_t TIMER_GetModuleClock(TIMER_T *timer);
+
+/*@}*/ /* end of group M051_TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_TIMER_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__TIMER_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/uart.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/uart.h
new file mode 100644
index 0000000000000000000000000000000000000000..2b5433858c93152a19c55ed32e10df8cb5d21e9d
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/uart.h
@@ -0,0 +1,380 @@
+/**************************************************************************//**
+ * @file UART.h
+ * @version V1.00
+ * $Revision: 7 $
+ * $Date: 14/02/05 10:27a $
+ * @brief Mini51 series UART driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __UART_H__
+#define __UART_H__
+
+#include "M051Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_UART_Driver UART Driver
+ @{
+*/
+
+/** @addtogroup M051_UART_EXPORTED_CONSTANTS UART Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_FCR constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART_FCR_RFITL_1BYTE (0x0 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 1 bit */
+#define UART_FCR_RFITL_4BYTES (0x1 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 4 bits */
+#define UART_FCR_RFITL_8BYTES (0x2 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 8 bits */
+#define UART_FCR_RFITL_14BYTES (0x3 << UART_FCR_RFITL_Pos) /*!< UA_FCR setting to set RX FIFO Trigger Level to 14 bits */
+
+#define UART_FCR_RTS_TRI_LEV_1BYTE (0x0 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 1 bit */
+#define UART_FCR_RTS_TRI_LEV_4BYTES (0x1 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 4 bits */
+#define UART_FCR_RTS_TRI_LEV_8BYTES (0x2 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 8 bits */
+#define UART_FCR_RTS_TRI_LEV_14BYTES (0x3 << UART_FCR_RTS_TRI_LEV_Pos) /*!< UA_FCR setting to set RTS Trigger Level to 14 bits */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_LCR constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_WORD_LEN_5 (0) /*!< UA_LCR setting to set UART word length to 5 bits */
+#define UART_WORD_LEN_6 (1) /*!< UA_LCR setting to set UART word length to 6 bits */
+#define UART_WORD_LEN_7 (2) /*!< UA_LCR setting to set UART word length to 7 bits */
+#define UART_WORD_LEN_8 (3) /*!< UA_LCR setting to set UART word length to 8 bits */
+
+#define UART_PARITY_NONE (0x0 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as no parity */
+#define UART_PARITY_ODD (0x1 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as odd parity */
+#define UART_PARITY_EVEN (0x3 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to set UART as even parity */
+#define UART_PARITY_MARK (0x5 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to keep parity bit as '1' */
+#define UART_PARITY_SPACE (0x7 << UART_LCR_PBE_Pos) /*!< UA_LCR setting to keep parity bit as '0' */
+
+#define UART_STOP_BIT_1 (0x0 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for one stop bit */
+#define UART_STOP_BIT_1_5 (0x1 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for 1.5 stop bit when 5-bit word length */
+#define UART_STOP_BIT_2 (0x1 << UART_LCR_NSB_Pos) /*!< UA_LCR setting for two stop bit when 6, 7, 8-bit word length */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART RTS LEVEL TRIGGER constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x1 << UART_MCR_LEV_RTS_Pos) /*!< Set RTS is High Level Active */
+#define UART_RTS_IS_LOW_LEV_ACTIVE (0x0 << UART_MCR_LEV_RTS_Pos) /*!< Set RTS is Low Level Active */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_IRCR constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_IRCR_TX_SELECT (1) /*!< Set IrDA function Tx mode */
+#define UART_IRCR_RX_SELECT (0) /*!< Set IrDA function Rx mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_FUNC_SEL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_FUNC_SEL_UART (0x0 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set UART Function (Default) */
+#define UART_FUNC_SEL_LIN (0x1 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set LIN Function */
+#define UART_FUNC_SEL_IrDA (0x2 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set IrDA Function */
+#define UART_FUNC_SEL_RS485 (0x3 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UA_FUNC_SEL setting to set RS485 Function */
+
+
+/*@}*/ /* end of group M051_UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+
+/**
+ * @brief Calculate UART baudrate mode0 divider
+ *
+ * @param None
+ *
+ * @return UART baudrate mode0 register setting value
+ *
+ */
+#define UART_BAUD_MODE0 (0)
+
+/**
+ * @brief Calculate UART baudrate mode0 divider
+ *
+ * @param None
+ *
+ * @return UART baudrate mode2 register setting value
+ *
+ */
+#define UART_BAUD_MODE2 (UART_BAUD_DIV_X_EN_Msk | UART_BAUD_DIV_X_ONE_Msk)
+
+
+/**
+ * @brief Calculate UART baudrate mode0 divider
+ *
+ * @param u32SrcFreq UART clock frequency
+ * @param u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode0 divider
+ *
+ */
+#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
+
+/**
+ * @brief Calculate UART baudrate mode2 divider
+ *
+ * @param u32SrcFreq UART clock frequency
+ * @param u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode2 divider
+ */
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
+
+
+/**
+ * @brief Write Data to Tx data register
+ *
+ * @param uart The base address of UART module.
+ * @param u8Data Data byte to transmit
+ *
+ * @return None
+ */
+#define UART_WRITE(uart, u8Data) (uart->THR = (u8Data))
+
+/**
+ * @brief Read Rx data register
+ *
+ * @param uart The base address of UART module.
+ *
+ * @return The oldest data byte in RX FIFO
+ */
+#define UART_READ(uart) (uart->RBR)
+
+
+/**
+ * @brief Get Tx empty register value.
+ *
+ * @param uart The base address of UART module
+ *
+ * @return Tx empty register value.
+ */
+#define UART_GET_TX_EMPTY(uart) (uart->FSR & UART_FSR_TX_EMPTY_Msk)
+
+
+/**
+ * @brief Get Rx empty register value.
+ *
+ * @param uart The base address of UART module
+ *
+ * @return Rx empty register value.
+ */
+#define UART_GET_RX_EMPTY(uart) (uart->FSR & UART_FSR_RX_EMPTY_Msk)
+
+/**
+ * @brief Check specified uart port transmission is over.
+ *
+ * @param uart The base address of UART module
+ *
+ * @return TE_Flag.
+ */
+#define UART_IS_TX_EMPTY(uart) ((uart->FSR & UART_FSR_TE_FLAG_Msk) >> UART_FSR_TE_FLAG_Pos)
+
+
+/**
+ * @brief Wait specified uart port transmission is over
+ *
+ * @param uart The base address of UART module
+ *
+ * @return None
+ */
+#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FSR) & UART_FSR_TE_FLAG_Msk) >> UART_FSR_TE_FLAG_Pos))
+
+/**
+ * @brief Check RDA_IF is set or not
+ *
+ * @param uart The base address of UART module
+ *
+ * @return
+ * 0 : The number of bytes in the RX FIFO is less than the RFITL
+ * 1 : The number of bytes in the RX FIFO equals or larger than RFITL
+ */
+#define UART_IS_RX_READY(uart) ((uart->ISR & UART_ISR_RDA_IF_Msk)>>UART_ISR_RDA_IF_Pos)
+
+
+/**
+ * @brief Check TX FIFO is full or not
+ *
+ * @param uart The base address of UART module
+ *
+ * @return
+ * 1 = TX FIFO is full
+ * 0 = TX FIFO is not full
+ */
+#define UART_IS_TX_FULL(uart) ((uart->FSR & UART_FSR_TX_FULL_Msk)>>UART_FSR_TX_FULL_Pos)
+
+/**
+ * @brief Check RX FIFO is full or not
+ *
+ * @param uart The base address of UART module
+ *
+ * @return
+ * 1 = RX FIFO is full
+ * 0 = RX FIFO is not full
+ *
+ */
+#define UART_IS_RX_FULL(uart) ((uart->FSR & UART_FSR_RX_FULL_Msk)>>UART_FSR_RX_FULL_Pos)
+
+
+/**
+ * @brief Get Tx full register value
+ *
+ * @param uart The base address of UART module
+ *
+ * @return Tx full register value
+ */
+#define UART_GET_TX_FULL(uart) (uart->FSR & UART_FSR_TX_FULL_Msk)
+
+
+/**
+ * @brief Get Rx full register value
+ *
+ * @param uart The base address of UART module
+ *
+ * @return Rx full register value
+ */
+#define UART_GET_RX_FULL(uart) (uart->FSR & UART_FSR_RX_FULL_Msk)
+
+
+/**
+ * @brief Enable specified interrupt
+ *
+ * @param uart The base address of UART module
+ * @param u32eIntSel Interrupt type select
+ * - UART_IER_LIN_RX_BRK_IEN_Msk : Lin bus Rx break field interrupt
+ * - UART_IER_WAKE_EN_Msk : Wakeup interrupt
+ * - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt
+ * - UART_IER_RTO_IEN_Msk : Rx time-out interrupt
+ * - UART_IER_MODEM_IEN_Msk : Modem interrupt
+ * - UART_IER_RLS_IEN_Msk : Rx Line status interrupt
+ * - UART_IER_THRE_IEN_Msk : Tx empty interrupt
+ * - UART_IER_RDA_IEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ */
+#define UART_ENABLE_INT(uart, u32eIntSel) (uart->IER |= (u32eIntSel))
+
+
+/**
+ * @brief Disable specified interrupt
+ *
+ * @param uart The base address of UART module
+ * @param u32eIntSel Interrupt type select
+ * - UART_IER_LIN_RX_BRK_IEN_Msk : Lin bus Rx break field interrupt
+ * - UART_IER_WAKE_EN_Msk : Wakeup interrupt
+ * - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt
+ * - UART_IER_RTO_IEN_Msk : Rx time-out interrupt
+ * - UART_IER_MODEM_IEN_Msk : Modem interrupt
+ * - UART_IER_RLS_IEN_Msk : Rx Line status interrupt
+ * - UART_IER_THRE_IEN_Msk : Tx empty interrupt
+ * - UART_IER_RDA_IEN_Msk : Rx ready interrupt
+ * @return None
+ */
+#define UART_DISABLE_INT(uart, u32eIntSel) (uart->IER &= ~ (u32eIntSel))
+
+
+/**
+ * @brief Get specified interrupt flag/status
+ *
+ * @param uart The base address of UART module
+ * @param u32eIntTypeFlag Interrupt Type Flag,should be
+ * - UART_ISR_LIN_RX_BREAK_INT_Msk : Lin bus interrupt
+ * - UART_ISR_BUF_ERR_INT_Msk : Buffer Error interrupt
+ * - UART_ISR_TOUT_INT_Msk : Rx time-out interrupt
+ * - UART_ISR_MODEM_INT_Msk : Modem interrupt
+ * - UART_ISR_RLS_INT_Msk : Rx Line status interrupt
+ * - UART_ISR_THRE_INT_Msk : Tx empty interrupt
+ * - UART_ISR_RDA_INT_Msk : Rx ready interrupt
+ *
+ * @return
+ * 0 = The specified interrupt is not happened.
+ * 1 = The specified interrupt is happened.
+ */
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->ISR & (u32eIntTypeFlag))?1:0)
+
+
+/**
+ * @brief Set RTS pin is low
+ *
+ * @param uart The base address of UART module
+ * @return None
+ */
+__INLINE void UART_CLEAR_RTS(UART_T* uart)
+{
+ uart->MCR |= UART_MCR_LEV_RTS_Msk;
+ uart->MCR &= ~UART_MCR_RTS_Msk;
+}
+
+/**
+ * @brief Set RTS pin is high
+ *
+ * @param uart The base address of UART module
+ * @return None
+ */
+__INLINE void UART_SET_RTS(UART_T* uart)
+{
+ uart->MCR |= UART_MCR_LEV_RTS_Msk | UART_MCR_RTS_Msk;
+}
+
+
+/**
+ * @brief Clear RS-485 Address Byte Detection Flag
+ *
+ * @param uart The base address of UART module
+ * @return None
+ */
+#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FSR |= UART_FSR_RS485_ADD_DETF_Msk)
+
+
+/**
+ * @brief Get RS-485 Address Byte Detection Flag
+ *
+ * @param uart The base address of UART module
+ * @return RS-485 Address Byte Detection Flag
+ */
+#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->FSR & UART_FSR_RS485_ADD_DETF_Msk) >> UART_FSR_RS485_ADD_DETF_Pos)
+
+
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
+void UART_Close(UART_T* uart);
+void UART_DisableFlowCtrl(UART_T* uart);
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag);
+void UART_EnableFlowCtrl(UART_T* uart);
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag);
+void UART_Open(UART_T* uart, uint32_t u32baudrate);
+uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
+uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
+
+
+/*@}*/ /* end of group M051_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_UART_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__UART_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/wdt.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/wdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..e9fefde927194347eeb79da9893b247438837fa3
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/wdt.h
@@ -0,0 +1,173 @@
+/**************************************************************************//**
+ * @file wdt.h
+ * @version V3.00
+ * $Revision: 3 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series WDT driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WDT_H__
+#define __WDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_WDT_Driver WDT Driver
+ @{
+*/
+
+/** @addtogroup M051_WDT_EXPORTED_CONSTANTS WDT Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* WTCR Constants Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_TIMEOUT_2POW4 (0UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */
+#define WDT_TIMEOUT_2POW6 (1UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */
+#define WDT_TIMEOUT_2POW8 (2UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */
+#define WDT_TIMEOUT_2POW10 (3UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
+#define WDT_TIMEOUT_2POW12 (4UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
+#define WDT_TIMEOUT_2POW14 (5UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
+#define WDT_TIMEOUT_2POW16 (6UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
+#define WDT_TIMEOUT_2POW18 (7UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* WTCRALT Constants Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_DELAY_1026CLK (0UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
+#define WDT_RESET_DELAY_130CLK (1UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */
+#define WDT_RESET_DELAY_18CLK (2UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */
+#define WDT_RESET_DELAY_3CLK (3UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */
+
+/*@}*/ /* end of group M051_WDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+ @{
+*/
+
+/**
+ * @details This macro clear WDT time-out reset system flag.
+ */
+#define WDT_CLEAR_RESET_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk)) | WDT_WTCR_WTRF_Msk)
+
+/**
+ * @details This macro clear WDT time-out interrupt flag.
+ */
+#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTRF_Msk | WDT_WTCR_WTWKF_Msk)) | WDT_WTCR_WTIF_Msk)
+
+/**
+ * @details This macro clear WDT time-out wake-up system flag.
+ */
+#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTRF_Msk | WDT_WTCR_WTIF_Msk)) | WDT_WTCR_WTWKF_Msk)
+
+/**
+ * @brief Get WDT Time-out Reset Flag
+ *
+ * @return WDT reset system or not
+ * @retval 0 WDT did not cause system reset
+ * @retval 1 WDT caused system reset
+ *
+ * @details This macro indicate WDT time-out to reset system or not.
+ */
+#define WDT_GET_RESET_FLAG() (WDT->WTCR & WDT_WTCR_WTRF_Msk ? 1 : 0)
+
+/**
+ * @brief Get WDT Time-out Interrupt Flag
+ *
+ * @return WDT time-out interrupt occurred or not
+ * @retval 0 WDT time-out interrupt did not occur
+ * @retval 1 WDT time-out interrupt occurred
+ *
+ * @details This macro indicate WDT time-out interrupt occurred or not.
+ */
+#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->WTCR & WDT_WTCR_WTIF_Msk ? 1 : 0)
+
+/**
+ * @brief Get WDT Time-out Wake-up Flag
+ *
+ * @return WDT time-out waked system up or not
+ * @retval 0 WDT did not wake up system
+ * @retval 1 WDT waked up system
+ *
+ * @details This macro indicate WDT time-out waked system up or not
+ */
+#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->WTCR & WDT_WTCR_WTWKF_Msk ? 1 : 0)
+
+/**
+ * @details This macro is used to reset 18-bit WDT counter.
+ * @note If WDT is activated and enabled to reset system, software must reset WDT counter \n
+ * before WDT time-out plus reset delay reached. Or WDT generate a reset signal.
+ */
+#define WDT_RESET_COUNTER() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk | WDT_WTCR_WTRF_Msk)) | WDT_WTCR_WTR_Msk)
+
+/**
+ * @brief Stop WDT Counting
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function stops WDT counting and disable WDT module.
+ */
+static __INLINE void WDT_Close(void)
+{
+ WDT->WTCR = 0;
+ return;
+}
+
+/**
+ * @brief Enable WDT Time-out Interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function enable the WDT time-out interrupt.
+ */
+static __INLINE void WDT_EnableInt(void)
+{
+ WDT->WTCR |= WDT_WTCR_WTIE_Msk;
+ return;
+}
+
+/**
+ * @brief Disable WDT Time-out Interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function disables the WDT time-out interrupt.
+ */
+static __INLINE void WDT_DisableInt(void)
+{
+ // Do not touch write 1 clear bits
+ WDT->WTCR &= ~(WDT_WTCR_WTIE_Msk | WDT_WTCR_WTRF_Msk | WDT_WTCR_WTIF_Msk);
+ return;
+}
+
+void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
+
+/*@}*/ /* end of group M051_WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_WDT_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WDT_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/inc/wwdt.h b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/wwdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..e95ec6af904c11e6a779591117a2498918f25139
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/inc/wwdt.h
@@ -0,0 +1,118 @@
+/**************************************************************************//**
+ * @file wwdt.h
+ * @version V3.00
+ * $Revision: 6 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series WWDT driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WWDT_H__
+#define __WWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_WWDT_Driver WWDT Driver
+ @{
+*/
+
+/** @addtogroup M051_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* WWDTCR Constants Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_PRESCALER_1 (0 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_2 (1 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_4 (2 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_8 (3 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_16 (4 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_32 (5 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_64 (6 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_128 (7 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_192 (8 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_256 (9 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_384 (10 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_512 (11 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_768 (12 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_1024 (13 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_1536 (14 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_2048 (15 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */
+
+#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDTRLD register to reload WWDT counter */
+
+/*@}*/ /* end of group M051_WWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M051_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+ @{
+*/
+
+/**
+ * @details This macro clear WWDT counter time-out reset system flag.
+ */
+#define WWDT_CLEAR_RESET_FLAG() (WWDT->WWDTSR = WWDT_WWDTSR_WWDTRF_Msk)
+
+/**
+ * @details This macro clear WWDT counter compare match interrupt flag.
+ */
+#define WWDT_CLEAR_INT_FLAG() (WWDT->WWDTSR = WWDT_WWDTSR_WWDTIF_Msk)
+
+/**
+ * @brief Get WWDT Reset Flag
+ *
+ * @return WWDT counter time-out reset system or not
+ * @retval 0 WWDT did not cause system reset
+ * @retval 1 WWDT counter time-out caused system reset
+ *
+ * @details This macro is used to indicate WWDT counter time-out reset system flag.
+ */
+#define WWDT_GET_RESET_FLAG() ((((WWDT->WWDTSR) & WWDT_WWDTSR_WWDTRF_Msk) == WWDT_WWDTSR_WWDTRF_Msk)? 1:0)
+
+/**
+ * @brief Get WWDT Compared Match Interrupt Flag
+ *
+ * @return WWDT compare match interrupt occurred or not
+ * @retval 0 WWDT counter compare match interrupt did not occur
+ * @retval 1 WWDT counter compare match interrupt occurred
+ *
+ * @details This macro indicate WWDT counter compare match interrupt occurred or not.
+ */
+#define WWDT_GET_INT_FLAG() ((((WWDT->WWDTSR) & WWDT_WWDTSR_WWDTIF_Msk) == WWDT_WWDTSR_WWDTIF_Msk)? 1:0)
+
+/**
+ * @details This macro to reflects the current WWDT counter value.
+ */
+#define WWDT_GET_COUNTER() (WWDT->WWDTCVR)
+
+/**
+ * @details This macro is used to reload the WWDT counter value to 0x3F.
+ * @note After WWDT enabled, application must reload WWDT counter while current counter is less than compare value \n
+ * and larger than 0, otherwise WWDT will cause system reset immediately.
+ */
+#define WWDT_RELOAD_COUNTER() (WWDT->WWDTRLD = WWDT_RELOAD_WORD)
+
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
+
+/*@}*/ /* end of group M051_WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_WWDT_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WWDT_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/acmp.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/acmp.c
new file mode 100644
index 0000000000000000000000000000000000000000..67f119676467ce42dd171b18927f160da976d8b8
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/acmp.c
@@ -0,0 +1,78 @@
+/**************************************************************************//**
+ * @file acmp.c
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series Analog Comparator(ACMP) driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M051Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_ACMP_Driver ACMP Driver
+ @{
+*/
+
+
+/** @addtogroup M051_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Configure the specified ACMP module
+ *
+ * @param[in] Acmp The base address of ACMP module
+ * @param[in] u32ChNum comparator number.
+ * @param[in] u32NegSrc is comparator negative input selection. Including:
+ * - \ref ACMP_CR_VNEG_PIN
+ * - \ref ACMP_CR_VNEG_BANDGAP
+ *
+ * @param[in] u32HysteresisEn is the hysteresis function option. Including:
+ * - \ref ACMP_CR_HYSTERESIS_ENABLE
+ * - \ref ACMP_CR_HYSTERESIS_DISABLE
+ * @return None
+ */
+void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
+{
+ Acmp->CR[u32ChNum % 2] = (Acmp->CR[u32ChNum % 2] & (~(ACMP_CR_NEGSEL_Msk | ACMP_CR_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CR_ACMPEN_Msk);
+}
+
+/**
+ * @brief This function close comparator
+ *
+ * @param[in] Acmp The base address of ACMP module
+ * @param[in] u32ChNum comparator number.
+ *
+ * @return None
+ */
+void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum)
+{
+ Acmp->CR[u32ChNum % 2] &= (~ACMP_CR_ACMPEN_Msk);
+}
+
+
+
+/*@}*/ /* end of group M051_ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_ACMP_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/adc.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/adc.c
new file mode 100644
index 0000000000000000000000000000000000000000..54deef4ce07aa40a8bf56a452c1d10470f3bfe50
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/adc.c
@@ -0,0 +1,170 @@
+/**************************************************************************//**
+ * @file adc.c
+ * @version V3.00
+ * $Revision: 5 $
+ * $Date: 14/02/10 2:47p $
+ * @brief M051 series ADC driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_ADC_Driver ADC Driver
+ @{
+*/
+
+/** @addtogroup M051_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This API configures ADC module to be ready for convert the input from selected channel
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32InputMode Decides the ADC analog input mode. Valid values are:
+ * - \ref ADC_ADCR_DIFFEN_SINGLE_END :Single end input mode
+ * - \ref ADC_ADCR_DIFFEN_DIFFERENTIAL :Differential input type
+ * @param[in] u32OpMode Decides the ADC operation mode. Valid values are:
+ * - \ref ADC_ADCR_ADMD_SINGLE :Single mode.
+ * - \ref ADC_ADCR_ADMD_BURST :Burst mode.
+ * - \ref ADC_ADCR_ADMD_SINGLE_CYCLE :Single cycle scan mode.
+ * - \ref ADC_ADCR_ADMD_CONTINUOUS :Continuous scan mode.
+ * @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 7 is channel 7.
+ * @return None
+ * @note M051 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
+ * with smallest number will be convert.
+ * @note This API does not turn on ADC power nor does trigger ADC conversion
+ */
+void ADC_Open(ADC_T *adc,
+ uint32_t u32InputMode,
+ uint32_t u32OpMode,
+ uint32_t u32ChMask)
+{
+
+ ADC->ADCR = (ADC->ADCR & (~(ADC_ADCR_DIFFEN_Msk | ADC_ADCR_ADMD_Msk))) | \
+ u32InputMode | \
+ u32OpMode;
+
+ ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32ChMask);
+
+ return;
+}
+
+/**
+ * @brief Disable ADC module
+ * @param[in] adc Base address of ADC module
+ * @return None
+ */
+void ADC_Close(ADC_T *adc)
+{
+ SYS->IPRSTC2 |= SYS_IPRSTC2_ADC_RST_Msk;
+ SYS->IPRSTC2 &= ~SYS_IPRSTC2_ADC_RST_Msk;
+ return;
+
+}
+
+/**
+ * @brief Configure the hardware trigger condition and enable hardware trigger
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Source Decides the hardware trigger source. Valid values are:
+ * - \ref ADC_ADCR_TRGS_STADC :A/D conversion is started by external STADC pin.
+ * - \ref ADC_ADCR_TRGS_PWM :A/D conversion is started by PWM.
+ * @param[in] u32Param While ADC trigger by PWM, this parameter is used to set the delay between PWM
+ * trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay
+ * time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter
+ * is used to set trigger condition. Valid values are:
+ * - \ref ADC_ADCR_TRGCOND_LOW_LEVEL :STADC Low level active
+ * - \ref ADC_ADCR_TRGCOND_HIGH_LEVEL :STADC High level active
+ * - \ref ADC_ADCR_TRGCOND_FALLING_EDGE :STADC Falling edge active
+ * - \ref ADC_ADCR_TRGCOND_RISING_EDGE :STADC Rising edge active
+ * @return None
+ * @note ADC hardware trigger source does not support PWM trigger (M05xxBN only).
+ */
+void ADC_EnableHWTrigger(ADC_T *adc,
+ uint32_t u32Source,
+ uint32_t u32Param)
+{
+ ADC->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk);
+ if(u32Source == ADC_ADCR_TRGS_STADC)
+ {
+ ADC->ADCR |= u32Source | u32Param | ADC_ADCR_TRGEN_Msk;
+ }
+ else
+ {
+ ADC->ADTDCR = (ADC->ADTDCR & ~ADC_ADTDCR_PTDT_Msk) | u32Param;
+ ADC->ADCR |= u32Source | ADC_ADCR_TRGEN_Msk;
+ }
+ return;
+}
+
+/**
+ * @brief Disable hardware trigger ADC function.
+ * @param[in] adc Base address of ADC module
+ * @return None
+ */
+void ADC_DisableHWTrigger(ADC_T *adc)
+{
+ ADC->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk);
+ return;
+}
+
+/**
+ * @brief Enable the interrupt(s) selected by u32Mask parameter.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
+ * corresponds to a interrupt status. This parameter decides which
+ * interrupts will be enabled.
+ * - \ref ADC_ADF_INT :ADC convert complete interrupt
+ * - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
+ * - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
+ * @return None
+ */
+void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
+{
+ if(u32Mask & ADC_ADF_INT)
+ ADC->ADCR |= ADC_ADCR_ADIE_Msk;
+ if(u32Mask & ADC_CMP0_INT)
+ ADC->ADCMPR[0] |= ADC_ADCMPR_CMPIE_Msk;
+ if(u32Mask & ADC_CMP1_INT)
+ ADC->ADCMPR[1] |= ADC_ADCMPR_CMPIE_Msk;
+
+ return;
+}
+
+/**
+ * @brief Disable the interrupt(s) selected by u32Mask parameter.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
+ * corresponds to a interrupt status. This parameter decides which
+ * interrupts will be disabled.
+ * - \ref ADC_ADF_INT :ADC convert complete interrupt
+ * - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
+ * - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
+ * @return None
+ */
+void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
+{
+ if(u32Mask & ADC_ADF_INT)
+ ADC->ADCR &= ~ADC_ADCR_ADIE_Msk;
+ if(u32Mask & ADC_CMP0_INT)
+ ADC->ADCMPR[0] &= ~ADC_ADCMPR_CMPIE_Msk;
+ if(u32Mask & ADC_CMP1_INT)
+ ADC->ADCMPR[1] &= ~ADC_ADCMPR_CMPIE_Msk;
+
+ return;
+}
+
+
+
+/*@}*/ /* end of group M051_ADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_ADC_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/clk.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/clk.c
new file mode 100644
index 0000000000000000000000000000000000000000..5a395aac4920640c4fa64b18948c55b88126d4d1
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/clk.c
@@ -0,0 +1,470 @@
+/**************************************************************************//**
+ * @file clk.c
+ * @version V3.00
+ * $Revision: 15 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series CLK driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "M051Series.h"
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_CLK_Driver CLK Driver
+ @{
+*/
+
+
+/** @addtogroup M051_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function disable frequency output function.
+ * @return None
+ */
+void CLK_DisableCKO(void)
+{
+ /* Disable CKO clock source */
+ CLK_DisableModuleClock(FDIV_MODULE);
+}
+
+/**
+ * @brief This function enable frequency divider module clock,
+ * enable frequency divider clock function and configure frequency divider.
+ * @param u32ClkSrc is frequency divider function clock source. Including :
+ * - \ref CLK_CLKSEL2_FRQDIV_S_HXT
+ * - \ref CLK_CLKSEL2_FRQDIV_S_LIRC
+ * - \ref CLK_CLKSEL2_FRQDIV_S_HCLK
+ * - \ref CLK_CLKSEL2_FRQDIV_S_HIRC
+ * @param u32ClkDiv is divider output frequency selection.
+ * @param u32ClkDivBy1En is frequency divided by one enable.
+ * @return None
+ *
+ * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
+ * The formula is:
+ * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
+ * This function is just used to set CKO clock.
+ * User must enable I/O for CKO clock output pin by themselves.
+ */
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
+{
+ /* CKO = clock source / 2^(u32ClkDiv + 1) */
+ CLK->FRQDIV = CLK_FRQDIV_DIVIDER_EN_Msk | u32ClkDiv | u32ClkDivBy1En << CLK_FRQDIV_DIVIDER1_Pos;
+
+ /* Enable CKO clock source */
+ CLK_EnableModuleClock(FDIV_MODULE);
+
+ /* Select CKO clock source */
+ CLK_SetModuleClock(FDIV_MODULE, u32ClkSrc, 0);
+}
+
+/**
+ * @brief This function let system enter to Power-down mode.
+ * @return None
+ */
+void CLK_PowerDown(void)
+{
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ CLK->PWRCON |= (CLK_PWRCON_PWR_DOWN_EN_Msk | CLK_PWRCON_PD_WAIT_CPU_Msk);
+ __WFI();
+}
+
+/**
+ * @brief This function let system enter to Idle mode.
+ * @return None
+ */
+void CLK_Idle(void)
+{
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ CLK->PWRCON &= ~CLK_PWRCON_PWR_DOWN_EN_Msk;
+ __WFI();
+}
+
+/**
+ * @brief This function get external high frequency crystal frequency. The frequency unit is Hz.
+ * @return External high frequency crystal frequency
+ */
+uint32_t CLK_GetHXTFreq(void)
+{
+ if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)
+ return __HXT;
+ else
+ return 0;
+}
+
+
+/**
+ * @brief This function get HCLK frequency. The frequency unit is Hz.
+ * @return HCLK frequency
+ */
+uint32_t CLK_GetHCLKFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief This function get CPU frequency. The frequency unit is Hz.
+ * @return CPU frequency
+ */
+uint32_t CLK_GetCPUFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz
+ * @param u32Hclk is HCLK frequency
+ * @return HCLK frequency
+ */
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
+{
+ if(u32Hclk > FREQ_50MHZ)
+ u32Hclk = FREQ_50MHZ;
+ else if(u32Hclk < FREQ_25MHZ)
+ u32Hclk = FREQ_25MHZ;
+
+ if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)
+ u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk);
+ else
+ u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, u32Hclk);
+
+ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));
+
+ return u32Hclk;
+}
+
+/**
+ * @brief This function set HCLK clock source and HCLK clock divider
+ * @param u32ClkSrc is HCLK clock source. Including :
+ * - \ref CLK_CLKSEL0_HCLK_S_HXT
+ * - \ref CLK_CLKSEL0_HCLK_S_PLL
+ * - \ref CLK_CLKSEL0_HCLK_S_LIRC
+ * - \ref CLK_CLKSEL0_HCLK_S_HIRC
+ * @param u32ClkDiv is HCLK clock divider. Including :
+ * - \ref CLK_CLKDIV_HCLK(x)
+ * @return None
+ */
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_S_Msk) | u32ClkSrc;
+ CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_HCLK_N_Msk) | u32ClkDiv;
+ SystemCoreClockUpdate();
+}
+
+/**
+ * @brief This function set selected module clock source and module clock divider
+ * @param u32ModuleIdx is module index.
+ * @param u32ClkSrc is module clock source.
+ * @param u32ClkDiv is module clock divider.
+ * @return None
+ * @details Valid parameter combinations listed in following table:
+ *
+ * |Module index |Clock source |Divider |
+ * | :---------------- | :----------------------------------- | :--------------------- |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDT_S_HCLK_DIV2048 | x |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDT_S_LIRC | x |
+ * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HXT |\ref CLK_CLKDIV_ADC(x) |
+ * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_PLL |\ref CLK_CLKDIV_ADC(x) |
+ * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HCLK |\ref CLK_CLKDIV_ADC(x) |
+ * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HIRC |\ref CLK_CLKDIV_ADC(x) |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0_S_HCLK | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0_S_PLL | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1_S_HCLK | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1_S_PLL | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HCLK | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_T0 | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_LIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_HXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_HCLK | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_T1 | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_LIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR0_S_HIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HCLK | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_T2 | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_LIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2_S_HIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HCLK | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_T3 | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_LIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3_S_HIRC | x |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_CLKDIV_UART(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_CLKDIV_UART(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_CLKDIV_UART(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_CLKDIV_UART(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_CLKDIV_UART(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_CLKDIV_UART(x) |
+ * |\ref PWM01_MODULE |\ref CLK_CLKSEL1_PWM01_S_HXT | x |
+ * |\ref PWM01_MODULE |\ref CLK_CLKSEL1_PWM01_S_LIRC | x |
+ * |\ref PWM01_MODULE |\ref CLK_CLKSEL1_PWM01_S_HCLK | x |
+ * |\ref PWM01_MODULE |\ref CLK_CLKSEL1_PWM01_S_HIRC | x |
+ * |\ref PWM23_MODULE |\ref CLK_CLKSEL1_PWM23_S_HXT | x |
+ * |\ref PWM23_MODULE |\ref CLK_CLKSEL1_PWM23_S_LIRC | x |
+ * |\ref PWM23_MODULE |\ref CLK_CLKSEL1_PWM23_S_HCLK | x |
+ * |\ref PWM23_MODULE |\ref CLK_CLKSEL1_PWM23_S_HIRC | x |
+ * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HXT | x |
+ * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_LIRC | x |
+ * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HCLK | x |
+ * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HIRC | x
+ * |\ref PWM45_MODULE |\ref CLK_CLKSEL2_PWM45_S_HXT | x |
+ * |\ref PWM45_MODULE |\ref CLK_CLKSEL2_PWM45_S_LIRC | x |
+ * |\ref PWM45_MODULE |\ref CLK_CLKSEL2_PWM45_S_HCLK | x |
+ * |\ref PWM45_MODULE |\ref CLK_CLKSEL2_PWM45_S_HIRC | x |
+ * |\ref PWM67_MODULE |\ref CLK_CLKSEL2_PWM67_S_HXT | x |
+ * |\ref PWM67_MODULE |\ref CLK_CLKSEL2_PWM67_S_LIRC | x |
+ * |\ref PWM67_MODULE |\ref CLK_CLKSEL2_PWM67_S_HCLK | x |
+ * |\ref PWM67_MODULE |\ref CLK_CLKSEL2_PWM67_S_HIRC | x |
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDT_S_HCLK_DIV2048 | x |
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDT_S_LIRC | x |
+ */
+
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32tmp = 0, u32sel = 0, u32div = 0;
+
+ if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
+ {
+ u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4);
+ u32tmp = *(volatile uint32_t *)(u32sel);
+ u32tmp = u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)) | u32ClkSrc;
+ *(volatile uint32_t *)(u32sel) = u32tmp;
+ }
+
+ if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
+ {
+ u32div = (uint32_t)&CLK->CLKDIV + ((MODULE_CLKDIV(u32ModuleIdx)) * 4);
+ u32tmp = *(volatile uint32_t *)(u32div);
+ u32tmp = (u32tmp & ~MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)) | u32ClkDiv;
+ *(volatile uint32_t *)(u32div) = u32tmp;
+ }
+}
+
+/**
+ * @brief This function set systick clock source
+ * @param u32ClkSrc is module clock source. Including
+ * - \ref CLK_CLKSEL0_STCLK_S_HXT
+ * - \ref CLK_CLKSEL0_STCLK_S_HXT_DIV2
+ * - \ref CLK_CLKSEL0_STCLK_S_HCLK_DIV2
+ * - \ref CLK_CLKSEL0_STCLK_S_HIRC_DIV2
+ * @return None
+ */
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
+{
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLK_S_Msk) | u32ClkSrc;
+}
+
+/**
+ * @brief This function enable clock source
+ * @param u32ClkMask is clock source mask. Including :
+ * - \ref CLK_PWRCON_XTL12M_EN_Msk
+ * - \ref CLK_PWRCON_OSC22M_EN_Msk
+ * - \ref CLK_PWRCON_OSC10K_EN_Msk
+ * @return None
+ */
+void CLK_EnableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCON |= u32ClkMask;
+}
+
+/**
+ * @brief This function disable clock source
+ * @param u32ClkMask is clock source mask. Including :
+ * - \ref CLK_PWRCON_XTL12M_EN_Msk
+ * - \ref CLK_PWRCON_OSC22M_EN_Msk
+ * - \ref CLK_PWRCON_OSC10K_EN_Msk
+ * @return None
+ */
+void CLK_DisableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCON &= ~u32ClkMask;
+}
+
+/**
+ * @brief This function enable module clock
+ * @param u32ModuleIdx is module index. Including :
+ * - \ref WDT_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref FDIV_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref PWM01_MODULE
+ * - \ref PWM23_MODULE
+ * - \ref PWM45_MODULE
+ * - \ref PWM67_MODULE
+ * - \ref ADC_MODULE
+ * - \ref ACMP01_MODULE
+ * - \ref ACMP23_MODULE
+ * @return None
+ */
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
+{
+ *(volatile uint32_t *)((uint32_t)&CLK->APBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx);
+}
+
+/**
+ * @brief This function disable module clock
+ * @param u32ModuleIdx is module index
+ * - \ref WDT_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref FDIV_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref PWM01_MODULE
+ * - \ref PWM23_MODULE
+ * - \ref PWM45_MODULE
+ * - \ref PWM67_MODULE
+ * - \ref ADC_MODULE
+ * - \ref ACMP01_MODULE
+ * - \ref ACMP23_MODULE
+ * @return None
+ */
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
+{
+ *(volatile uint32_t *)((uint32_t)&CLK->APBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx));
+}
+
+
+/**
+ * @brief This function set PLL frequency
+ * @param u32PllClkSrc is PLL clock source. Including :
+ * - \ref CLK_PLLCON_PLL_SRC_HXT
+ * - \ref CLK_PLLCON_PLL_SRC_HIRC
+ * @param u32PllFreq is PLL frequency
+ * @return PLL frequency
+ */
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
+{
+ uint32_t u32PllSrcClk, u32PLLReg, u32NR, u32NF, u32NO;
+
+ if(u32PllClkSrc == CLK_PLLCON_PLL_SRC_HXT)
+ {
+ /* PLL source clock from HXT */
+ CLK->PLLCON &= ~CLK_PLLCON_PLL_SRC_Msk;
+ u32PllSrcClk = __HXT;
+ }
+ else
+ {
+ /* PLL source clock from HIRC */
+ CLK->PLLCON |= CLK_PLLCON_PLL_SRC_Msk;
+ u32PllSrcClk = __HIRC;
+ }
+
+ if((u32PllFreq <= FREQ_200MHZ) && (u32PllFreq > FREQ_100MHZ))
+ {
+ u32NO = 0;
+ }
+ else if((u32PllFreq <= FREQ_100MHZ) && (u32PllFreq > FREQ_50MHZ))
+ {
+ u32NO = 1;
+ u32PllFreq = u32PllFreq << 1;
+ }
+ else if((u32PllFreq <= FREQ_50MHZ) && (u32PllFreq >= FREQ_25MHZ))
+ {
+ u32NO = 3;
+ u32PllFreq = u32PllFreq << 2;
+ }
+ else
+ {
+ if(u32PllClkSrc == CLK_PLLCON_PLL_SRC_HXT)
+ CLK->PLLCON = 0xC22E;
+ else
+ CLK->PLLCON = 0xD66F;
+
+ CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
+ return CLK_GetPLLClockFreq();
+ }
+
+ u32NF = u32PllFreq / 1000000;
+ u32NR = u32PllSrcClk / 1000000;
+
+ while(1)
+ {
+ if((u32NR & 0x01) || (u32NF & 0x01) || (u32NR == 2) || (u32NF == 2))
+ {
+ break;
+ }
+ else
+ {
+ u32NR >>= 1;
+ u32NF >>= 1;
+ }
+ }
+
+ u32PLLReg = (u32NO << 14) | ((u32NR - 2) << 9) | (u32NF - 2);
+
+ CLK->PLLCON = (CLK->PLLCON & ~(CLK_PLLCON_FB_DV_Msk | CLK_PLLCON_IN_DV_Msk | CLK_PLLCON_OUT_DV_Msk)) | u32PLLReg;
+
+ CLK->PLLCON &= ~(CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk);
+
+ CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
+
+ return ((u32PllSrcClk * u32NF) / (u32NR * (u32NO + 1)));
+}
+
+/**
+ * @brief This function disable PLL
+ * @param None
+ * @return None
+ */
+void CLK_DisablePLL(void)
+{
+ CLK->PLLCON |= CLK_PLLCON_PD_Msk;
+}
+
+
+/**
+ * @brief This function check selected clock source status
+ * @param u32ClkMask is selected clock source. Including :
+ * - \ref CLK_CLKSTATUS_OSC22M_STB_Msk
+ * - \ref CLK_CLKSTATUS_OSC10K_STB_Msk
+ * - \ref CLK_CLKSTATUS_XTL12M_STB_Msk
+ * - \ref CLK_CLKSTATUS_PLL_STB_Msk
+ *
+ * @return None
+ */
+void CLK_WaitClockReady(uint32_t u32ClkMask)
+{
+ int32_t i32TimeOutCnt;
+
+ i32TimeOutCnt = __HSI / 200; /* About 5ms */
+
+ while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask)
+ {
+ if(i32TimeOutCnt-- <= 0)
+ break;
+ }
+}
+
+
+/*@}*/ /* end of group M051_CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_CLK_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/ebi.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/ebi.c
new file mode 100644
index 0000000000000000000000000000000000000000..4d16d0005c762f2a054fe985f0d4c212b71b364e
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/ebi.c
@@ -0,0 +1,156 @@
+/**************************************************************************//**
+ * @file ebi.c
+ * @version V3.00
+ * $Revision: 3 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series EBI driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_EBI_Driver EBI Driver
+ @{
+*/
+
+
+/** @addtogroup M051_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize EBI function
+ *
+ * @param[in] u32Bank Bank number for EBI. This parameter is current not used.
+ * @param[in] u32DataWidth Data bus width. Valid values are:
+ * - \ref EBI_BUSWIDTH_8BIT
+ * - \ref EBI_BUSWIDTH_16BIT
+ * @param[in] u32TimingClass Default timing configuration. Valid values are:
+ * - \ref EBI_TIMING_FASTEST
+ * - \ref EBI_TIMING_VERYFAST
+ * - \ref EBI_TIMING_FAST
+ * - \ref EBI_TIMING_NORMAL
+ * - \ref EBI_TIMING_SLOW
+ * - \ref EBI_TIMING_VERYSLOW
+ * - \ref EBI_TIMING_SLOWEST
+ * @param[in] u32BusMode Enable EBI separate mode. This parameter is current not used.
+ * @param[in] u32CSActiveLevel CS is active High/Low. This parameter is current not used.
+ *
+ * @return none
+ *
+ * @details This function make EBI module be ready for read and write operation.
+ * @note Only u32DataWidth and u32TimingClass is valid in M051 series.
+ */
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+ if(u32DataWidth == EBI_BUSWIDTH_8BIT)
+ EBI->EBICON &= ~EBI_EBICON_ExtBW16_Msk;
+ else
+ EBI->EBICON |= EBI_EBICON_ExtBW16_Msk;
+
+ switch(u32TimingClass)
+ {
+ case EBI_TIMING_FASTEST:
+ EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
+ (EBI_MCLKDIV_1 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk;
+ EBI->EXTIME = 0x0;
+ break;
+
+ case EBI_TIMING_VERYFAST:
+ EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
+ (EBI_MCLKDIV_1 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
+ (0x3 << EBI_EBICON_ExttALE_Pos) ;
+ EBI->EXTIME = 0x03003318;
+ break;
+
+ case EBI_TIMING_FAST:
+ EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk;
+ EBI->EXTIME = 0x0;
+ break;
+
+ case EBI_TIMING_NORMAL:
+ EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
+ (0x3 << EBI_EBICON_ExttALE_Pos) ;
+ EBI->EXTIME = 0x03003318;
+ break;
+
+ case EBI_TIMING_SLOW:
+ EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
+ (0x7 << EBI_EBICON_ExttALE_Pos) ;
+ EBI->EXTIME = 0x07007738;
+ break;
+
+ case EBI_TIMING_VERYSLOW:
+ EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
+ (EBI_MCLKDIV_4 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
+ (0x7 << EBI_EBICON_ExttALE_Pos) ;
+ EBI->EXTIME = 0x07007738;
+ break;
+
+ case EBI_TIMING_SLOWEST:
+ EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
+ (EBI_MCLKDIV_8 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
+ (0x7 << EBI_EBICON_ExttALE_Pos) ;
+ EBI->EXTIME = 0x07007738;
+ break;
+
+ default:
+ EBI->EBICON &= ~EBI_EBICON_ExtEN_Msk;
+ break;
+ }
+}
+
+/**
+ * @brief Disable EBI function
+ *
+ * @param[in] u32Bank Bank number for EBI. This parameter is current not used.
+ *
+ * @return none
+ *
+ * @details This function close EBI module.
+ */
+void EBI_Close(uint32_t u32Bank)
+{
+ EBI->EBICON &= ~EBI_EBICON_ExtEN_Msk;
+}
+
+/**
+ * @brief Set EBI bus timings
+ *
+ * @param[in] u32Bank Bank number for EBI. This parameter is current not used.
+ *
+ * @param[in] u32TimingConfig Configure EBI timing settings, ExttACC, ExttAHD, ExtIW2X and ExtIR2R.
+ * @param[in] u32MclkDiv Divider for MCLK. Valid values are:
+ * - \ref EBI_MCLKDIV_1
+ * - \ref EBI_MCLKDIV_2
+ * - \ref EBI_MCLKDIV_4
+ * - \ref EBI_MCLKDIV_8
+ * - \ref EBI_MCLKDIV_16
+ * - \ref EBI_MCLKDIV_32
+ *
+ * @return none
+ *
+ * @details This function make EBI module be ready for read and write operation.
+ */
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
+{
+ EBI->EBICON = (EBI->EBICON & ~EBI_EBICON_MCLKDIV_Msk) | (u32MclkDiv << EBI_EBICON_MCLKDIV_Pos);
+ EBI->EXTIME = u32TimingConfig;
+}
+
+/*@}*/ /* end of group M051_EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_EBI_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/fmc.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/fmc.c
new file mode 100644
index 0000000000000000000000000000000000000000..56a5367fef5660885cc199ba271827846c2289a9
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/fmc.c
@@ -0,0 +1,227 @@
+/**************************************************************************//**
+ * @file fmc.c
+ * @version V3.00
+ * $Revision: 11 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series FMC driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+//* Includes ------------------------------------------------------------------*/
+#include
+#include "M051Series.h"
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_FMC_Driver FMC Driver
+ @{
+*/
+
+
+/** @addtogroup M051_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Set boot source from LDROM or APROM after next software reset.
+ *
+ * @param i32BootSrc[in]
+ * 1: Boot from LDROM
+ * 0: Boot from APROM
+ *
+ * @details This function is used to switch APROM boot or LDROM boot. User need to call
+ * FMC_SetBootSource to select boot source first, then use CPU reset or
+ * System Reset Request to reset system.
+ *
+ */
+void FMC_SetBootSource(int32_t i32BootSrc)
+{
+ if(i32BootSrc)
+ FMC->ISPCON |= FMC_ISPCON_BS_Msk; /* Boot from LDROM */
+ else
+ FMC->ISPCON &= ~FMC_ISPCON_BS_Msk;/* Boot from APROM */
+}
+
+
+/**
+ * @brief Disable ISP Functions
+ */
+void FMC_Close(void)
+{
+ FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk;
+}
+
+
+/**
+ * @brief Disable APROM update function
+ *
+ * @details Disable APROM update function will forbid APROM programming when boot form APROM.
+ * APROM update is default to be disable.
+ *
+ */
+void FMC_DisableAPUpdate(void)
+{
+ FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk;
+}
+
+
+/**
+ * @brief Disable User Configuration update function
+ *
+ * @details Disable User Configuration update function will forbid User Configuration programming.
+ * User Configuration update is default to be disable.
+ */
+void FMC_DisableConfigUpdate(void)
+{
+ FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk;
+}
+
+
+/**
+ * @brief Disable LDROM update function
+ *
+ * @details Disable LDROM update function will forbid LDROM programming.
+ * LDROM update is default to be disable.
+ */
+void FMC_DisableLDUpdate(void)
+{
+ FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk;
+}
+
+
+/**
+ * @brief Enable APROM update function
+ *
+ * @details Enable APROM to be able to program when boot from APROM.
+ *
+ */
+void FMC_EnableAPUpdate(void)
+{
+ FMC->ISPCON |= FMC_ISPCON_APUEN_Msk;
+}
+
+
+/**
+ * @brief Enable User Configuration update function
+ *
+ * @details Enable User Configuration to be able to program.
+ *
+ */
+void FMC_EnableConfigUpdate(void)
+{
+ FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk;
+}
+
+
+/**
+ * @brief Enable LDROM update function
+ *
+ * @details Enable LDROM to be able to program.
+ *
+ */
+void FMC_EnableLDUpdate(void)
+{
+ FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk;
+}
+
+
+/**
+ * @brief Get the current boot source
+ *
+ * @retval 0: This chip is currently booting from APROM
+ * @retval 1: This chip is currently booting from LDROM
+ *
+ * @note This function only show the boot source.
+ * User need to read ISPSTA register to know if IAP mode supported or not in relative boot.
+ */
+int32_t FMC_GetBootSource(void)
+{
+ if(FMC->ISPCON & FMC_ISPCON_BS_Msk)
+ return 1;
+ else
+ return 0;
+}
+
+
+/**
+ * @brief Enable FMC ISP function
+ *
+ * @details ISPEN bit of ISPCON must be set before we can use ISP commands.
+ *
+ */
+void FMC_Open(void)
+{
+ FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk;
+}
+
+/**
+ * @brief Get the base address of Data Flash if enabled.
+ * @retval The base address of Data Flash
+ */
+uint32_t FMC_ReadDataFlashBaseAddr(void)
+{
+ return FMC->DFBADR;
+}
+
+
+/**
+ * @brief Read the User Configuration words.
+ * @param[out] u32Config The word buffer to store the User Configuration data.
+ * @param[in] u32Count The word count to be read.
+ * @retval 0: Success
+ * @retval -1: Failed
+ */
+int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
+{
+ int32_t i;
+
+ for(i = 0; i < u32Count; i++)
+ u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4);
+
+ return 0;
+}
+
+
+/**
+ * @brief Write User Configuration
+ *
+ * @param u32Config: The word buffer to store the User Configuration data.
+ * @param u32Count: The word count to program to User Configuration.
+ *
+ * @retval 0: Success
+ * @retval -1: Failed
+ *
+ * @details User must enable User Configuration update before writing it.
+ * User must erase User Configuration before writing it.
+ * User Configuration is also be page erase. User needs to backup necessary data
+ * before erase User Configuration.
+ */
+int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
+{
+ int32_t i;
+
+ for(i = 0; i < u32Count; i++)
+ {
+ FMC_Write(FMC_CONFIG_BASE + i * 4, u32Config[i]);
+ if(FMC_Read(FMC_CONFIG_BASE + i * 4) != u32Config[i])
+ return -1;
+ }
+
+ return 0;
+}
+
+
+/*@}*/ /* end of group M051_FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_FMC_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
+
+
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/gpio.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/gpio.c
new file mode 100644
index 0000000000000000000000000000000000000000..1ef9c03b5cc7299d5a65e1c5317a51792f078c83
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/gpio.c
@@ -0,0 +1,92 @@
+/**************************************************************************//**
+ * @file gpio.c
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series GPIO driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup M051_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set GPIO operation mode
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. It could be BIT0 ~ BIT7.
+ * @param[in] u32Mode Operation mode. GPIO_PMD_INPUT, GPIO_PMD_OUTPUT, GPIO_PMD_OPEN_DRAIN, GPIO_PMD_QUASI
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for(i = 0; i < GPIO_PIN_MAX; i++)
+ {
+ if(u32PinMask & (1 << i))
+ {
+ port->PMD = (port->PMD & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+/**
+ * @brief Enable GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+ port->IMD |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+ port->IEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief Disable GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
+{
+ port->IMD &= ~(1UL << u32Pin);
+ port->IEN &= ~((0x00010001UL) << u32Pin);
+}
+
+
+/*@}*/ /* end of group M051_GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_GPIO_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/i2c.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..7408ff1a22abfeda729a158068fb8ea637088e6e
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/i2c.c
@@ -0,0 +1,380 @@
+/**************************************************************************//**
+ * @file i2c.c
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series I2C driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "M051Series.h"
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_I2C_Driver I2C Driver
+ @{
+*/
+
+
+/** @addtogroup M051_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enable specify I2C controller and set divider
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32BusClock The target I2C bus clock in Hz
+ *
+ * @return Actual I2C bus clock frequency
+ *
+ * @details The function enable the specify I2C controller and set proper clock divider
+ * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.
+ * I2C bus clock = PCLK / (4*(divider+1).
+ *
+ */
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
+{
+ uint32_t u32Div;
+
+ u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
+ i2c->I2CLK = u32Div;
+
+ /* Enable I2C */
+ i2c->I2CON |= I2C_I2CON_ENS1_Msk;
+
+ return (SystemCoreClock / ((u32Div + 1) << 2));
+}
+
+/**
+ * @brief Disable specify I2C controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Reset I2C controller and disable specify I2C port.
+ *
+ */
+
+void I2C_Close(I2C_T *i2c)
+{
+ /* Reset I2C controller */
+ SYS->IPRSTC2 |= SYS_IPRSTC2_I2C_RST_Msk;
+ SYS->IPRSTC2 &= ~SYS_IPRSTC2_I2C_RST_Msk;
+
+ /* Disable I2C */
+ i2c->I2CON &= ~I2C_I2CON_ENS1_Msk;
+}
+
+/**
+ * @brief Clear time-out flag
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The function is used for clear I2C bus time-out flag.
+ *
+ */
+void I2C_ClearTimeoutFlag(I2C_T *i2c)
+{
+ i2c->I2CTOC |= I2C_I2CTOC_TIF_Msk;
+}
+
+/**
+ * @brief Set control bit of I2C controller
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8Start Set I2C START condition
+ * @param[in] u8Stop Set I2C STOP condition
+ * @param[in] u8Si Clear SI flag
+ * @param[in] u8Ack Set I2C ACK bit
+ *
+ * @return None
+ *
+ * @details The function set I2C control bit of I2C bus protocol.
+ *
+ */
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
+{
+ uint32_t u32Reg = 0;
+
+ if(u8Start)
+ u32Reg |= I2C_I2CON_STA;
+ if(u8Stop)
+ u32Reg |= I2C_I2CON_STO;
+ if(u8Si)
+ u32Reg |= I2C_I2CON_SI;
+ if(u8Ack)
+ u32Reg |= I2C_I2CON_AA;
+
+ i2c->I2CON = (i2c->I2CON & ~0x3C) | u32Reg;
+}
+
+/**
+ * @brief Disable Interrupt of I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The function is used for disable I2C interrupt
+ *
+ */
+void I2C_DisableInt(I2C_T *i2c)
+{
+ i2c->I2CON &= ~I2C_I2CON_EI_Msk;
+}
+
+/**
+ * @brief Enable Interrupt of I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The function is used for enable I2C interrupt
+ *
+ */
+void I2C_EnableInt(I2C_T *i2c)
+{
+ i2c->I2CON |= I2C_I2CON_EI_Msk;
+}
+
+/**
+ * @brief Get I2C Bus Clock
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return The actual I2C Bus clock in Hz
+ *
+ * @details To get the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
+{
+ uint32_t u32Divider = i2c->I2CLK;
+
+ return (SystemCoreClock / ((u32Divider + 1) << 2));
+}
+
+/**
+ * @brief Set I2C Bus Clock
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32BusClock The target I2C Bus Clock in Hz
+ *
+ * @return The actual I2C Bus clock in Hz
+ *
+ * @details To set the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
+{
+ uint32_t u32Div;
+
+ u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
+ i2c->I2CLK = u32Div;
+
+ return (SystemCoreClock / ((u32Div + 1) << 2));
+}
+
+/**
+ * @brief Get Interrupt Flag
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C interrupt flag status
+ *
+ * @details To get I2C Bus interrupt flag.
+ */
+uint32_t I2C_GetIntFlag(I2C_T *i2c)
+{
+ return ((i2c->I2CON & I2C_I2CON_SI_Msk) == I2C_I2CON_SI_Msk ? 1 : 0);
+}
+
+/**
+ * @brief Get I2C bus Status code
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C status code
+ *
+ * @details To get I2C bus status code.
+ */
+uint32_t I2C_GetStatus(I2C_T *i2c)
+{
+ return (i2c->I2CSTATUS);
+}
+
+/**
+ * @brief Read a Byte from I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C Data
+ *
+ * @details To read a bytes data from specify I2C port.
+ */
+uint8_t I2C_GetData(I2C_T *i2c)
+{
+ return (i2c->I2CDAT);
+}
+
+/**
+ * @brief Send a byte to I2C bus
+ *
+ * @param[in] i2c I2C port
+ * @param[in] u8Data The data to send to I2C bus
+ *
+ * @return None
+ *
+ * @details This function is used to write a byte to specified I2C port
+ */
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
+{
+ i2c->I2CDAT = u8Data;
+}
+
+/**
+ * @brief Set 7-bit Slave Address and GC Mode
+ *
+ * @param[in] i2c I2C port
+ * @param[in] u8SlaveNo Set the number of I2C address register (0~3)
+ * @param[in] u8SlaveAddr 7-bit slave address
+ * @param[in] u8GCMode Enable GC mode
+ *
+ * @return None
+ *
+ * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)
+ * and enable GC mode.
+ *
+ */
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
+{
+ switch(u8SlaveNo)
+ {
+ case 1:
+ i2c->I2CADDR1 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ case 2:
+ i2c->I2CADDR2 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ case 3:
+ i2c->I2CADDR3 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ case 0:
+ default:
+ i2c->I2CADDR0 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ }
+}
+
+/**
+ * @brief Configure the mask bits of 7-bit Slave Address
+ *
+ * @param[in] i2c I2C port
+ * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3)
+ * @param[in] u8SlaveAddrMask A byte for slave address mask
+ *
+ * @return None
+ *
+ * @details This function is used to set 7-bit slave addresses.
+ *
+ */
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
+{
+ switch(u8SlaveNo)
+ {
+ case 1:
+ i2c->I2CADM1 = u8SlaveAddrMask << 1;
+ break;
+ case 2:
+ i2c->I2CADM2 = u8SlaveAddrMask << 1;
+ break;
+ case 3:
+ i2c->I2CADM3 = u8SlaveAddrMask << 1;
+ break;
+ case 0:
+ default:
+ i2c->I2CADM0 = u8SlaveAddrMask << 1;
+ break;
+ }
+}
+
+/**
+ * @brief Enable Time-out Function and support long time-out
+ *
+ * @param[in] i2c I2C port
+ * @param[in] u8LongTimeout Configure DIV4 to enable long time-out
+ *
+ * @return None
+ *
+ * @details This function enable time-out function and configure DIV4 to support long
+ * time-out.
+ *
+ */
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
+{
+ if(u8LongTimeout)
+ i2c->I2CTOC |= I2C_I2CTOC_DIV4_Msk;
+ else
+ i2c->I2CTOC &= ~I2C_I2CTOC_DIV4_Msk;
+
+ i2c->I2CTOC |= I2C_I2CTOC_ENTI_Msk;
+}
+
+/**
+ * @brief Disable Time-out Function
+ *
+ * @param[in] i2c I2C port
+ *
+ * @return None
+ *
+ * @details This function disable time-out function.
+ *
+ */
+void I2C_DisableTimeout(I2C_T *i2c)
+{
+ i2c->I2CTOC &= ~I2C_I2CTOC_ENTI_Msk;
+}
+
+/**
+ * @brief Enable I2C Wake-up Function
+ *
+ * @param[in] i2c I2C port
+ *
+ * @return None
+ *
+ * @details The function is used to enable wake-up function of I2C controller
+ *
+ */
+void I2C_EnableWakeup(I2C_T *i2c)
+{
+ i2c->I2CWKUPCON |= I2C_I2CWKUPCON_WKUPEN_Msk;
+}
+
+/**
+ * @brief Disable I2C Wake-up Function
+ *
+ * @param[in] i2c I2C port
+ *
+ * @return None
+ *
+ * @details The function is used to disable wake-up function of I2C controller
+ *
+ */
+void I2C_DisableWakeup(I2C_T *i2c)
+{
+ i2c->I2CWKUPCON &= ~I2C_I2CWKUPCON_WKUPEN_Msk;
+}
+
+/*@}*/ /* end of group M051_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_I2C_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/pwm.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/pwm.c
new file mode 100644
index 0000000000000000000000000000000000000000..d551add8cce281878bd91a2700fe700a49a5e2fc
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/pwm.c
@@ -0,0 +1,648 @@
+/**************************************************************************//**
+ * @file pwm.c
+ * @version V3.00
+ * $Revision: 14 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series PWM driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_PWM_Driver PWM Driver
+ @{
+*/
+
+
+/** @addtogroup M051_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief Config PWM capture and get the nearest unit time.
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to config PWM capture and get the nearest unit time.
+ */
+uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32UnitTimeNsec,
+ uint32_t u32CaptureEdge)
+{
+ uint32_t u32Src;
+ uint32_t u32PWMClockSrc;
+ uint32_t u32PWMClkTbl[4] = {__HXT, __LIRC, 0, __HIRC};
+ uint32_t u32NearestUnitTimeNsec;
+ uint8_t u8Divider = 1;
+ /* this table is mapping divider value to register configuration */
+ uint32_t u32PWMDividerToRegTbl[17] = {NULL, 4, 0, NULL, 1, NULL, NULL, NULL, 2, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 3};
+ uint16_t u16Prescale = 2;
+ uint16_t u16CNR = 0xFFFF;
+
+ if(pwm == PWMA)
+ u32Src = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM01_S_Msk << (u32ChannelNum >> 1))) >> (CLK_CLKSEL1_PWM01_S_Pos << (u32ChannelNum >> 1));
+ else /*pwm == PWMB*/
+ u32Src = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM45_S_Msk << (u32ChannelNum >> 1))) >> (CLK_CLKSEL2_PWM45_S_Pos << (u32ChannelNum >> 1));
+
+ if(u32Src == 2)
+ {
+ SystemCoreClockUpdate();
+ u32PWMClockSrc = SystemCoreClock;
+ }
+ else
+ {
+ u32PWMClockSrc = u32PWMClkTbl[u32Src];
+ }
+
+ u32PWMClockSrc /= 1000;
+ for(; u16Prescale <= 0x100; u16Prescale++)
+ {
+ u32NearestUnitTimeNsec = (1000000 * u16Prescale * u8Divider) / u32PWMClockSrc;
+ if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
+ {
+ if((u16Prescale == 0x100) && (u8Divider == 16)) //limit to the maximum unit time(nano second)
+ break;
+ if(u16Prescale == 0x100)
+ {
+ u16Prescale = 2;
+ u8Divider <<= 1; // clk divider could only be 1, 2, 4, 8, 16
+ continue;
+ }
+ if(!((1000000 * ((u16Prescale * u8Divider) + 1)) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))
+ break;
+ continue;
+ }
+ break;
+ }
+
+ // Store return value here 'cos we're gonna change u8Divider & u16Prescale & u16CNR to the real value to fill into register
+ u16Prescale -= 1;
+
+ // convert to real register value
+ u8Divider = u32PWMDividerToRegTbl[u8Divider];
+
+ // every two channels share a prescaler
+ (pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u16Prescale << ((u32ChannelNum >> 1) * 8));
+ (pwm)->CSR = ((pwm)->CSR & ~(PWM_CSR_CSR0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
+ // set PWM to edge aligned type
+ (pwm)->PCR &= ~(PWM_PCR_PWM01TYPE_Msk << (u32ChannelNum >> 1));
+ (pwm)->PCR |= PWM_PCR_CH0MOD_Msk << (8 * u32ChannelNum);
+ *((__IO uint32_t *)((((uint32_t) & ((pwm)->CNR0)) + (u32ChannelNum) * 12))) = u16CNR;
+
+ return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
+ * existing frequency of other channel.
+ */
+uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32Frequency,
+ uint32_t u32DutyCycle)
+{
+ uint32_t u32Src;
+ uint32_t u32PWMClockSrc;
+ uint32_t u32PWMClkTbl[4] = {__HXT, __LIRC, 0, __HIRC};
+ uint32_t i;
+ uint8_t u8Divider = 1, u8Prescale = 0xFF;
+ /* this table is mapping divider value to register configuration */
+ uint32_t u32PWMDividerToRegTbl[17] = {NULL, 4, 0, NULL, 1, NULL, NULL, NULL, 2, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 3};
+ uint16_t u16CNR = 0xFFFF;
+
+ if(pwm == PWMA)
+ u32Src = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM01_S_Msk << (u32ChannelNum >> 1))) >> (CLK_CLKSEL1_PWM01_S_Pos << (u32ChannelNum >> 1));
+ else /*pwm == PWMB*/
+ u32Src = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM45_S_Msk << (u32ChannelNum >> 1))) >> (CLK_CLKSEL2_PWM45_S_Pos << (u32ChannelNum >> 1));
+
+ if(u32Src == 2)
+ {
+ SystemCoreClockUpdate();
+ u32PWMClockSrc = SystemCoreClock;
+ }
+ else
+ {
+ u32PWMClockSrc = u32PWMClkTbl[u32Src];
+ }
+
+ for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 8, 16
+ {
+ i = (u32PWMClockSrc / u32Frequency) / u8Divider;
+ // If target value is larger than CNR * prescale, need to use a larger divider
+ if(i > (0x10000 * 0x100))
+ continue;
+
+ // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
+ u8Prescale = (i + 0xFFFF) / 0x10000;
+
+ // u8Prescale must at least be 2, otherwise the output stop
+ if(u8Prescale < 3)
+ u8Prescale = 2;
+
+ i /= u8Prescale;
+
+ if(i <= 0x10000)
+ {
+ if(i == 1)
+ u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
+ else
+ u16CNR = i;
+ break;
+ }
+ }
+ // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
+ i = u32PWMClockSrc / (u8Prescale * u8Divider * u16CNR);
+
+ u8Prescale -= 1;
+ u16CNR -= 1;
+ // convert to real register value
+ u8Divider = u32PWMDividerToRegTbl[u8Divider];
+
+ // every two channels share a prescaler
+ (pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
+ (pwm)->CSR = ((pwm)->CSR & ~(PWM_CSR_CSR0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
+ // set PWM to edge aligned type
+ (pwm)->PCR &= ~(PWM_PCR_PWM01TYPE_Msk << (u32ChannelNum >> 1));
+ (pwm)->PCR |= PWM_PCR_CH0MOD_Msk << (8 * u32ChannelNum);
+ *((__IO uint32_t *)((((uint32_t) & ((pwm)->CMR0)) + u32ChannelNum * 12))) = u32DutyCycle * (u16CNR + 1) / 100 - 1;
+ *((__IO uint32_t *)((((uint32_t) & ((pwm)->CNR0)) + (u32ChannelNum) * 12))) = u16CNR;
+
+ return(i);
+}
+
+
+/**
+ * @brief Start PWM module
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to start PWM module
+ */
+void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t u32Mask = 0, i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ u32Mask |= (PWM_PCR_CH0EN_Msk << (i * 8));
+ }
+ }
+
+ (pwm)->PCR |= u32Mask;
+}
+
+/**
+ * @brief Stop PWM module
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop PWM module
+ */
+void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ *((__IO uint32_t *)((((uint32_t) & ((pwm)->CNR0)) + i * 12))) = 0;
+ }
+ }
+}
+
+/**
+ * @brief Stop PWM generation immediately by clear channel enable bit
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop PWM generation immediately by clear channel enable bit
+ */
+void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t u32Mask = 0, i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ u32Mask |= (PWM_PCR_CH0EN_Msk << (i * 8));
+ }
+ }
+
+ (pwm)->PCR &= ~u32Mask;
+}
+
+/**
+ * @brief Enable selected channel to trigger ADC
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
+ * - \ref PWM_DUTY_TRIGGER_ADC
+ * - \ref PWM_PERIOD_TRIGGER_ADC
+ * @return None
+ * @details This function is used to enable selected channel to trigger ADC
+ */
+void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (pwm)->TCON = ((pwm)->TCON & ~((PWM_DUTY_TRIGGER_ADC |
+ PWM_PERIOD_TRIGGER_ADC) << u32ChannelNum)) | (u32Condition << u32ChannelNum);
+}
+
+/**
+ * @brief Disable selected channel to trigger ADC
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to disable selected channel to trigger ADC
+ */
+void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->TCON = ((pwm)->TCON & ~((PWM_DUTY_TRIGGER_ADC | PWM_PERIOD_TRIGGER_ADC) << u32ChannelNum));
+}
+
+/**
+ * @brief Clear selected channel trigger ADC flag
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger ADC flag
+ */
+void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (pwm)->TSTATUS = (PWM_TSTATUS_PWM0TF_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger ADC flag
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @retval 0 The specified channel trigger ADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger ADC to start of conversion flag is set
+ * @details This function is used to get PWM trigger ADC to start of conversion flag for specified channel
+ */
+uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((pwm)->TSTATUS & (PWM_TSTATUS_PWM0TF_Msk << (u32ChannelNum))) ? 1 : 0);
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s)
+ */
+void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ if(i < 2)
+ {
+ (pwm)->CCR0 |= PWM_CCR0_CAPCH0EN_Msk << (i * 16);
+ }
+ else
+ {
+ (pwm)->CCR2 |= PWM_CCR2_CAPCH2EN_Msk << ((i - 2) * 16);
+ }
+ }
+ }
+ (pwm)->CAPENR |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s)
+ */
+void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ if(i < 2)
+ {
+ (pwm)->CCR0 &= ~(PWM_CCR0_CAPCH0EN_Msk << (i * 16));
+ }
+ else
+ {
+ (pwm)->CCR2 &= ~(PWM_CCR2_CAPCH2EN_Msk << ((i - 2) * 16));
+ }
+ }
+ }
+ (pwm)->CAPENR &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PWM output generation of selected channel(s)
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enables PWM output generation of selected channel(s)
+ */
+void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ (pwm)->POE |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables PWM output generation of selected channel(s)
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disables PWM output generation of selected channel(s)
+ */
+void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ (pwm)->POE &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable Dead zone of selected channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no
+ * dead zone.
+ * @return None
+ * @details This function is used to enable Dead zone of selected channel
+ */
+void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
+{
+ // every two channels shares the same setting
+ u32ChannelNum >>= 1;
+ // set duration
+ (pwm)->PPR = ((pwm)->PPR & ~(PWM_PPR_DZI01_Msk << (8 * u32ChannelNum))) | (u32Duration << (PWM_PPR_DZI01_Pos + 8 * u32ChannelNum));
+ // enable dead zone
+ (pwm)->PCR |= (PWM_PCR_DZEN01_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable Dead zone of selected channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to disable Dead zone of selected channel
+ */
+void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ // every two channels shares the same setting
+ u32ChannelNum >>= 1;
+ // enable dead zone
+ (pwm)->PCR &= ~(PWM_PCR_DZEN01_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref PWM_CAPTURE_INT_RISING_LATCH
+ * - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ if(u32ChannelNum < 2)
+ (pwm)->CCR0 |= u32Edge << (u32ChannelNum * 16);
+ else
+ (pwm)->CCR2 |= u32Edge << ((u32ChannelNum - 2) * 16);
+
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref PWM_CAPTURE_INT_RISING_LATCH
+ * - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ if(u32ChannelNum < 2)
+ (pwm)->CCR0 &= u32Edge << ~(u32ChannelNum * 16);
+ else
+ (pwm)->CCR2 &= u32Edge << ~((u32ChannelNum - 2) * 16);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref PWM_CAPTURE_INT_RISING_LATCH
+ * - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ //clear capture interrupt flag, and clear CRLR or CFLR latched indicator
+ if(u32ChannelNum < 2)
+ (pwm)->CCR0 = ((pwm)->CCR0 & PWM_CCR_MASK) | (PWM_CCR0_CAPIF0_Msk << (u32ChannelNum * 16)) | (u32Edge << (u32ChannelNum * 16 + 5));
+ else
+ (pwm)->CCR2 = ((pwm)->CCR2 & PWM_CCR_MASK) | (PWM_CCR2_CAPIF2_Msk << ((u32ChannelNum - 2) * 16)) | (u32Edge << ((u32ChannelNum - 2) * 16 + 5));
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ if(u32ChannelNum < 2)
+ {
+ return (((pwm)->CCR0 & ((PWM_CCR0_CRLRI0_Msk | PWM_CCR0_CFLRI0_Msk) << (u32ChannelNum * 16))) >> (PWM_CCR0_CRLRI0_Pos + u32ChannelNum * 16));
+ }
+ else
+ {
+ return (((pwm)->CCR2 & ((PWM_CCR2_CRLRI2_Msk | PWM_CCR2_CFLRI2_Msk) << ((u32ChannelNum - 2) * 16))) >> (PWM_CCR2_CRLRI2_Pos + (u32ChannelNum - 2) * 16));
+ }
+
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ * - \ref PWM_DUTY_INT_DOWN_COUNT_MATCH_CMR
+ * - \ref PWM_DUTY_INT_UP_COUNT_MATCH_CMR
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ * Every two channels, (0 & 1), (2 & 3), shares the duty interrupt type setting.
+ */
+void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+ (pwm)->PIER = ((pwm)->PIER & ~(PWM_PIER_INT01DTYPE_Msk << (u32ChannelNum >> 1))) | \
+ (PWM_PIER_PWMDIE0_Msk << u32ChannelNum) | (u32IntDutyType << (u32ChannelNum >> 1));
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * - PWMA : PWM Group A
+ * - PWMB : PWM Group B
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel
+ */
+void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->PIER &= ~(PWM_PIER_PWMDIE0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel
+ */
+void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->PIIR = PWM_PIIR_PWMDIF0_Msk << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel
+ */
+uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((pwm)->PIIR & (PWM_PIIR_PWMDIF0_Msk << u32ChannelNum)) ? 1 : 0);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @param[in] u32IntPeriodType Period interrupt type, could be either
+ * - \ref PWM_PERIOD_INT_UNDERFLOW
+ * - \ref PWM_PERIOD_INT_MATCH_CNR
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ * Every two channels, (0 & 1), (2 & 3), shares the period interrupt type setting.
+ */
+void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
+{
+ (pwm)->PIER = ((pwm)->PIER & ~(PWM_PIER_INT01TYPE_Msk << (u32ChannelNum >> 1))) | \
+ (PWM_PIER_PWMIE0_Msk << u32ChannelNum) | (u32IntPeriodType << (u32ChannelNum >> 1));
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ */
+void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->PIER &= ~(PWM_PIER_PWMIE0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel
+ */
+void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->PIIR = (PWM_PIIR_PWMIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~3
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel
+ */
+uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((pwm)->PIIR & (PWM_PIIR_PWMIF0_Msk << (u32ChannelNum))) ? 1 : 0);
+}
+
+
+
+/*@}*/ /* end of group M051_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_PWM_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/retarget.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/retarget.c
new file mode 100644
index 0000000000000000000000000000000000000000..e487900e8cd15ee4d4b00f23898993c0c67c9ebd
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/retarget.c
@@ -0,0 +1,434 @@
+/**************************************************************************//**
+ * @file retarget.c
+ * @version V3.00
+ * $Revision: 10 $
+ * $Date: 14/01/27 11:41a $
+ * @brief M051 Series Debug Port and Semihost Setting Source File
+ *
+ * @note
+ * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+
+
+#include
+#include "M051Series.h"
+
+#if defined ( __CC_ARM )
+#if (__ARMCC_VERSION < 400000)
+#else
+/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
+#pragma import _printf_widthprec
+#endif
+#endif
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global variables */
+/*---------------------------------------------------------------------------------------------------------*/
+#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
+struct __FILE
+{
+ int handle; /* Add whatever you need here */
+};
+#endif
+FILE __stdout;
+FILE __stdin;
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Routine to write a char */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#if defined(DEBUG_ENABLE_SEMIHOST)
+/* The static buffer is used to speed up the semihost */
+static char g_buf[16];
+static char g_buf_len = 0;
+
+# if defined(__ICCARM__)
+
+
+/**
+ * @brief This HardFault handler is implemented to support semihost
+ *
+ * @param None
+ *
+ * @returns None
+ *
+ * @details This function is implement to support semihost message print.
+ *
+ */
+int32_t HardFault_Handler(void)
+{
+ asm("MOV R0, lr \n"
+ "LSLS R0, #29 \n" //; Check bit 2
+ "BMI SP_is_PSP \n" //; previous stack is PSP
+ "MRS R0, MSP \n" //; previous stack is MSP, read MSP
+ "B SP_Read_Ready \n"
+ "SP_is_PSP: \n"
+ "MRS R0, PSP \n" //; Read PSP
+ "SP_Read_Ready: \n"
+ "LDR R1, [R0, #24] \n" //; Get previous PC
+ "LDRH R3, [R1] \n" //; Get instruction
+ "LDR R2, [pc, #8] \n" //; The specific BKPT instruction
+ "CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT
+ "BNE HardFault_Handler_Ret\n" //; Not BKPT
+ "ADDS R1, #4 \n" //; Skip BKPT and next line
+ "STR R1, [R0, #24] \n" //; Save previous PC
+ "BX lr \n" //; Return
+ "DCD 0xBEAB \n" //; BKPT instruction code
+ "HardFault_Handler_Ret:\n"
+ );
+
+ /* TODO: Implement your own hard fault handler here. */
+ while(1);
+}
+
+/**
+ *
+ * @brief The function to process semihosted command
+ * @param[in] n32In_R0 : semihost register 0
+ * @param[in] n32In_R1 : semihost register 1
+ * @param[out] pn32Out_R0: semihost register 0
+ * @retval 0: No ICE debug
+ * @retval 1: ICE debug
+ *
+ */
+int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
+{
+ asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault
+ "B SH_ICE \n"
+ "SH_HardFault: \n" //; Captured by HardFault
+ "MOVS R0, #0 \n" //; Set return value to 0
+ "BX lr \n" //; Return
+ "SH_ICE: \n" //; Captured by ICE
+ "CMP R2, #0 \n"
+ "BEQ SH_End \n"
+ "STR R0, [R2]\n" //; Save the return value to *pn32Out_R0
+ "SH_End: \n");
+
+ return 1; //; Return 1 when it is trap by ICE
+
+}
+
+
+# else
+
+/**
+ * @brief This HardFault handler is implemented to support semihost
+ *
+ * @param None
+ *
+ * @returns None
+ *
+ * @details This function is implement to support semihost message print.
+ *
+ */
+__asm int32_t HardFault_Handler(void)
+{
+
+ MOV R0, LR
+ LSLS R0, #29 //; Check bit 2
+ BMI SP_is_PSP //; previous stack is PSP
+ MRS R0, MSP //; previous stack is MSP, read MSP
+ B SP_Read_Ready
+SP_is_PSP
+ MRS R0, PSP //; Read PSP
+
+SP_Read_Ready
+ LDR R1, [R0, #24] //; Get previous PC
+ LDRH R3, [R1] //; Get instruction
+ LDR R2, = 0xBEAB //; The specific BKPT instruction
+ CMP R3, R2 //; Test if the instruction at previous PC is BKPT
+ BNE HardFault_Handler_Ret //; Not BKPT
+
+ ADDS R1, #4 //; Skip BKPT and next line
+ STR R1, [R0, #24] //; Save previous PC
+
+ BX LR //; Return
+HardFault_Handler_Ret
+
+ /* TODO: Implement your own hard fault handler here. */
+ B .
+
+ ALIGN
+}
+
+/**
+ *
+ * @brief The function to process semihosted command
+ * @param[in] n32In_R0 : semihost register 0
+ * @param[in] n32In_R1 : semihost register 1
+ * @param[out] pn32Out_R0: semihost register 0
+ * @retval 0: No ICE debug
+ * @retval 1: ICE debug
+ *
+ */
+__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
+{
+ BKPT 0xAB //; Wait ICE or HardFault
+ //; ICE will step over BKPT directly
+ //; HardFault will step BKPT and the next line
+ B SH_ICE
+
+SH_HardFault //; Captured by HardFault
+ MOVS R0, #0 //; Set return value to 0
+ BX lr //; Return
+
+SH_ICE //; Captured by ICE
+ //; Save return value
+ CMP R2, #0
+ BEQ SH_End
+ STR R0, [R2] //; Save the return value to *pn32Out_R0
+
+SH_End
+ MOVS R0, #1 //; Set return value to 1
+ BX lr //; Return
+}
+#endif
+#endif
+
+
+/**
+ * @brief Routine to send a char
+ *
+ * @param None
+ *
+ * @returns Send value from UART debug port
+ *
+ * @details Send a target char to UART debug port .
+ */
+
+void SendChar_ToUART(int ch)
+{
+
+ while(DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk);
+ DEBUG_PORT->DATA = ch;
+ if(ch == '\n')
+ {
+ while(DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk);
+ DEBUG_PORT->DATA = '\r';
+ }
+}
+
+/**
+ * @brief Routine to send a char
+ *
+ * @param None
+ *
+ * @returns Send value from UART debug port or semihost
+ *
+ * @details Send a target char to UART debug port or semihost.
+ */
+void SendChar(int ch)
+{
+#if defined(DEBUG_ENABLE_SEMIHOST)
+ g_buf[g_buf_len++] = ch;
+ g_buf[g_buf_len] = '\0';
+ if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
+ {
+ /* Send the char */
+ if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
+ {
+ g_buf_len = 0;
+ return;
+ }
+ else
+ {
+ int i;
+
+ for(i = 0; i < g_buf_len; i++)
+ SendChar_ToUART(g_buf[i]);
+ g_buf_len = 0;
+ }
+ }
+#else
+ SendChar_ToUART(ch);
+#endif
+}
+
+/**
+ * @brief Routine to get a char
+ *
+ * @param None
+ *
+ * @returns Get value from UART debug port or semihost
+ *
+ * @details Wait UART debug port or semihost to input a char.
+ */
+char GetChar(void)
+{
+#ifdef DEBUG_ENABLE_SEMIHOST
+# if defined (__CC_ARM)
+ int nRet;
+ while(SH_DoCommand(0x101, 0, &nRet) != 0)
+ {
+ if(nRet != 0)
+ {
+ SH_DoCommand(0x07, 0, &nRet);
+ return (char)nRet;
+ }
+ }
+# else
+ int nRet;
+ while(SH_DoCommand(0x7, 0, &nRet) != 0)
+ {
+ if(nRet != 0)
+ return (char)nRet;
+ }
+# endif
+ return (0);
+#else
+
+ while(1)
+ {
+ if((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_Msk) == 0)
+ {
+ return (DEBUG_PORT->DATA);
+ }
+ }
+
+#endif
+}
+
+/**
+ * @brief Check any char input from UART
+ *
+ * @param None
+ *
+ * @retval 1: No any char input
+ * @retval 0: Have some char input
+ *
+ * @details Check UART RSR RX EMPTY or not to determine if any char input from UART
+ */
+
+int kbhit(void)
+{
+ return !((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_Msk) == 0);
+}
+/**
+ * @brief Check if debug message finished
+ *
+ * @param None
+ *
+ * @retval 1: Message is finished
+ * @retval 0: Message is transmitting.
+ *
+ * @details Check if message finished (FIFO empty of debug port)
+ */
+
+int IsDebugFifoEmpty(void)
+{
+ return ((DEBUG_PORT->FSR & UART_FSR_TE_FLAG_Msk) != 0);
+}
+
+/**
+ * @brief C library retargetting
+ *
+ * @param None
+ *
+ * @returns None
+ *
+ * @details Check if message finished (FIFO empty of debug port)
+ */
+
+void _ttywrch(int ch)
+{
+ SendChar(ch);
+ return;
+}
+
+
+/**
+ * @brief Write character to stream
+ *
+ * @param[in] ch Character to be written. The character is passed as its int promotion.
+ * @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.
+ *
+ * @returns If there are no errors, the same character that has been written is returned.
+ * If an error occurs, EOF is returned and the error indicator is set (see ferror).
+ *
+ * @details Writes a character to the stream and advances the position indicator.\n
+ * The character is written at the current position of the stream as indicated \n
+ * by the internal position indicator, which is then advanced one character.
+ *
+ * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.
+ *
+ *
+ */
+
+int fputc(int ch, FILE *stream)
+{
+ SendChar(ch);
+ return ch;
+}
+
+
+/**
+ * @brief Get character from UART debug port or semihosting input
+ *
+ * @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.
+ *
+ * @returns The character read from UART debug port or semihosting
+ *
+ * @details For get message from debug port or semihosting.
+ *
+ */
+
+int fgetc(FILE *stream)
+{
+ return (GetChar());
+}
+
+/**
+ * @brief Check error indicator
+ *
+ * @param[in] stream Pointer to a FILE object that identifies the stream.
+ *
+ * @returns If the error indicator associated with the stream was set, the function returns a nonzero value.
+ * Otherwise, it returns a zero value.
+ *
+ * @details Checks if the error indicator associated with stream is set, returning a value different
+ * from zero if it is. This indicator is generally set by a previous operation on the stream that failed.
+ *
+ * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.
+ *
+ */
+
+int ferror(FILE *stream)
+{
+ return EOF;
+}
+
+#ifdef DEBUG_ENABLE_SEMIHOST
+# ifdef __ICCARM__
+void __exit(int return_code)
+{
+
+ /* Check if link with ICE */
+ if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
+ {
+ /* Make sure all message is print out */
+ while(IsDebugFifoEmpty() == 0);
+ }
+label:
+ goto label; /* endless loop */
+}
+# else
+void _sys_exit(int return_code)
+{
+
+ /* Check if link with ICE */
+ if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
+ {
+ /* Make sure all message is print out */
+ while(IsDebugFifoEmpty() == 0);
+ }
+label:
+ goto label; /* endless loop */
+}
+# endif
+#endif
+
+
+
+
+
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/spi.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/spi.c
new file mode 100644
index 0000000000000000000000000000000000000000..7c5e057060ddc60e4a689dbc2d7778aa3be9f484
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/spi.c
@@ -0,0 +1,661 @@
+/**************************************************************************//**
+ * @file spi.c
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 2/07/14 6:59p $
+ * @brief M051 series SPI driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_SPI_Driver SPI Driver
+ @{
+*/
+
+
+/** @addtogroup M051_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make SPI module be ready to transfer.
+ * By default, the SPI transfer sequence is MSB first and
+ * the automatic slave select function is disabled. In
+ * Slave mode, the u32BusClock must be NULL and the SPI clock
+ * divider setting will be 0.
+ * @param spi is the base address of SPI module.
+ * @param u32MasterSlave decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
+ * @param u32SPIMode decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_03)
+ * @param u32DataWidth decides the data width of a SPI transaction.
+ * @param u32BusClock is the expected frequency of SPI bus clock in Hz.
+ * @return Actual frequency of SPI peripheral clock.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note In slave mode, the SPI peripheral clock rate will be set to equal to system clock rate.
+ * @note On M05xxBN, if u32BusClock is equal to system clock rate, DIV_ONE will be set to 1.
+ * So that byte reorder function, byte suspend function and variable clock function must be disabled.
+ * @note On M05xxBN, if u32BusClock is larger than system clock rate, the SPI peripheral clock rate will be set to a half of system clock rate.
+ * @note On M05xxDN and M05xxDE, if u32BusClock is larger than system clock rate, the SPI peripheral clock rate will be set to equal to system clock rate.
+ */
+uint32_t SPI_Open(SPI_T *spi,
+ uint32_t u32MasterSlave,
+ uint32_t u32SPIMode,
+ uint32_t u32DataWidth,
+ uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc = 0, u32Div;
+
+ if(u32DataWidth == 32)
+ u32DataWidth = 0;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ spi->CNTRL = u32MasterSlave | (u32DataWidth << SPI_CNTRL_TX_BIT_LEN_Pos) | (u32SPIMode);
+
+ if(((SYS->PDID & 0xF0000000) == 0) || ((SYS->PDID & 0xF0000000) == 0x10000000)) /* For M05xxAN and M05xxBN, the SPI peripheral clock source is PCLK. */
+ {
+ /* Get the system clock rate */
+ u32ClkSrc = CLK_GetHCLKFreq();
+
+ if(u32MasterSlave == SPI_MASTER)
+ {
+ /* Default setting: slave select signal is active low; disable automatic slave select function. */
+ spi->SSR = SPI_SS_ACTIVE_LOW;
+
+ if((u32BusClock == u32ClkSrc) && ((SYS->PDID & 0xF0000000) == 0x10000000)) /* M05xxBN support DIV_ONE feature */
+ {
+ /* Enable DIV_ONE feature */
+ /* Note: When DIV_ONE feature is enabled, byte reorder function, byte suspend function and variable clock function must be disabled. */
+ spi->CNTRL2 |= SPI_CNTRL2_DIV_ONE_Msk;
+ /* Return master peripheral clock rate */
+ return u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ spi->DIVIDER &= (~SPI_DIVIDER_DIVIDER_Msk);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / 2);
+ }
+ else if(u32BusClock == 0)
+ {
+ /* Set DIVIDER to the maximum value 0xFFFF */
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (0xFFFF << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / ((0xFFFF + 1) * 2));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10) / (u32BusClock * 2) + 5) / 10) - 1; /* Round to the nearest integer */
+ if(u32Div > 0xFFFF)
+ u32Div = 0xFFFF;
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / ((u32Div + 1) * 2));
+ }
+ }
+ else /* For slave mode, SPI peripheral clock rate is equal to system clock rate. */
+ {
+ /* Default setting: slave select signal is low level active. */
+ spi->SSR = SPI_SSR_SS_LTRIG_Msk;
+ /* Return slave peripheral clock rate */
+ return u32ClkSrc;
+ }
+ }
+ else /* M05xxDN or M05xxDE */
+ {
+ /* Set BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ spi->CNTRL2 |= SPI_CNTRL2_BCn_Msk;
+
+ if(u32MasterSlave == SPI_MASTER)
+ {
+ /* Default setting: slave select signal is active low; disable automatic slave select function. */
+ spi->SSR = SPI_SS_ACTIVE_LOW;
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ }
+
+ if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ spi->DIVIDER = 0;
+ /* Return master peripheral clock rate */
+ return u32ClkSrc;
+ }
+ else if(u32BusClock == 0)
+ {
+ /* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
+ spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk);
+ /* Set DIVIDER to the maximum value 0xFF */
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (0xFF << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / ((0xFF + 1) * 2));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
+ if(u32Div > 0xFF)
+ {
+ /* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
+ spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk);
+ u32Div = (((u32ClkSrc * 10) / (u32BusClock * 2) + 5) / 10) - 1; /* Round to the nearest integer */
+ if(u32Div > 0xFF)
+ u32Div = 0xFF;
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / ((u32Div + 1) * 2));
+ }
+ else
+ {
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / (u32Div + 1));
+ }
+ }
+
+ }
+ else /* For slave mode, force the SPI peripheral clock rate to system clock rate. */
+ {
+ /* Default setting: slave select signal is low level active. */
+ spi->SSR = SPI_SSR_SS_LTRIG_Msk;
+
+ /* Select HCLK as the clock source of SPI */
+ if(spi == SPI0)
+ CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI0_S_Msk)) | CLK_CLKSEL1_SPI0_S_HCLK;
+ else
+ CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI1_S_Msk)) | CLK_CLKSEL1_SPI1_S_HCLK;
+
+
+ /* Set DIVIDER = 0 */
+ spi->DIVIDER = 0;
+ /* Return slave peripheral clock rate */
+ return u32ClkSrc;
+ }
+ }
+
+}
+
+/**
+ * @brief Reset SPI module and disable SPI peripheral clock.
+ * @param spi is the base address of SPI module.
+ * @return None
+ */
+void SPI_Close(SPI_T *spi)
+{
+ if(spi == SPI0)
+ {
+ /* Reset SPI */
+ SYS->IPRSTC2 |= SYS_IPRSTC2_SPI0_RST_Msk;
+ SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI0_RST_Msk;
+
+ /* Disable SPI clock */
+ CLK->APBCLK &= ~CLK_APBCLK_SPI0_EN_Msk;
+ }
+ else
+ {
+ /* Reset SPI */
+ SYS->IPRSTC2 |= SYS_IPRSTC2_SPI1_RST_Msk;
+ SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI1_RST_Msk;
+
+ /* Disable SPI clock */
+ CLK->APBCLK &= ~CLK_APBCLK_SPI1_EN_Msk;
+ }
+}
+
+/**
+ * @brief Clear RX FIFO buffer.
+ * @param spi is the base address of SPI module.
+ * @return None
+ */
+void SPI_ClearRxFIFO(SPI_T *spi)
+{
+ spi->FIFO_CTL |= SPI_FIFO_CTL_RX_CLR_Msk;
+}
+
+/**
+ * @brief Clear TX FIFO buffer.
+ * @param spi is the base address of SPI module.
+ * @return None
+ */
+void SPI_ClearTxFIFO(SPI_T *spi)
+{
+ spi->FIFO_CTL |= SPI_FIFO_CTL_TX_CLR_Msk;
+}
+
+/**
+ * @brief Disable the automatic slave select function and set slave select signal to inactive state.
+ * @param spi is the base address of SPI module.
+ * @return None
+ */
+void SPI_DisableAutoSS(SPI_T *spi)
+{
+ spi->SSR &= ~(SPI_SSR_AUTOSS_Msk | SPI_SSR_SSR_Msk);
+}
+
+/**
+ * @brief Enable the automatic slave select function. Only available in Master mode.
+ * @param spi is the base address of SPI module.
+ * @param u32SSPinMask specifies slave select pins. (SPI_SS)
+ * @param u32ActiveLevel specifies the active level of slave select signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)
+ * @return None
+ */
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+ spi->SSR = (spi->SSR & (~(SPI_SSR_AUTOSS_Msk | SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSR_AUTOSS_Msk);
+}
+
+/**
+ * @brief Set the SPI bus clock. Only available in Master mode.
+ * @param spi is the base address of SPI module.
+ * @param u32BusClock is the expected frequency of SPI bus clock in Hz.
+ * @return Actual frequency of SPI peripheral clock.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note On M05xxBN, if u32BusClock is equal to system clock rate, DIV_ONE will be set to 1.
+ * So that byte reorder function, byte suspend function and variable clock function must be disabled.
+ * @note On M05xxBN, if u32BusClock is larger than system clock rate, the SPI peripheral clock rate will be set to a half of system clock rate.
+ * @note On M05xxDN and M05xxDE, if u32BusClock is larger than system clock rate, the SPI peripheral clock rate will be set to equal to system clock rate.
+ */
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc;
+ uint32_t u32Div;
+
+ if(((SYS->PDID & 0xF0000000) == 0) || ((SYS->PDID & 0xF0000000) == 0x10000000)) /* For M05xxAN and M05xxBN, the SPI peripheral clock source is PCLK. */
+ {
+ /* Get the system clock rate */
+ u32ClkSrc = CLK_GetHCLKFreq();
+
+ if((u32BusClock == u32ClkSrc) && ((SYS->PDID & 0xF0000000) == 0x10000000)) /* M05xxBN support DIV_ONE feature */
+ {
+ /* Enable DIV_ONE feature */
+ /* Note: When DIV_ONE feature is enabled, byte reorder function, byte suspend function and variable clock function must be disabled. */
+ spi->CNTRL2 |= SPI_CNTRL2_DIV_ONE_Msk;
+ /* Return master peripheral clock rate */
+ return u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ spi->DIVIDER &= (~SPI_DIVIDER_DIVIDER_Msk);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / 2);
+ }
+ else if(u32BusClock == 0)
+ {
+ /* Set DIVIDER to the maximum value 0xFFFF */
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (0xFFFF << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / ((0xFFFF + 1) * 2));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10) / (u32BusClock * 2) + 5) / 10) - 1; /* Round to the nearest integer */
+ if(u32Div > 0xFFFF)
+ u32Div = 0xFFFF;
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / ((u32Div + 1) * 2));
+ }
+ }
+ else /* M05xxDN or M05xxDE */
+ {
+ /* Set BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ spi->CNTRL2 |= SPI_CNTRL2_BCn_Msk;
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ }
+
+ if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ spi->DIVIDER = 0;
+ /* Return master peripheral clock rate */
+ return u32ClkSrc;
+ }
+ else if(u32BusClock == 0)
+ {
+ /* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
+ spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk);
+ /* Set DIVIDER to the maximum value 0xFF */
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (0xFF << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / ((0xFF + 1) * 2));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
+ if(u32Div > 0xFF)
+ {
+ /* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
+ spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk);
+ u32Div = (((u32ClkSrc * 10) / (u32BusClock * 2) + 5) / 10) - 1; /* Round to the nearest integer */
+ if(u32Div > 0xFF)
+ u32Div = 0xFF;
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / ((u32Div + 1) * 2));
+ }
+ else
+ {
+ spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / (u32Div + 1));
+ }
+ }
+ }
+}
+
+/**
+ * @brief Enable FIFO mode with user-specified TX FIFO threshold and RX FIFO threshold configurations.
+ * @param spi is the base address of SPI module.
+ * @param u32TxThreshold decides the TX FIFO threshold.
+ * @param u32RxThreshold decides the RX FIFO threshold.
+ * @return None
+ */
+void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ spi->FIFO_CTL = (spi->FIFO_CTL & ~(SPI_FIFO_CTL_TX_THRESHOLD_Msk | SPI_FIFO_CTL_RX_THRESHOLD_Msk) |
+ (u32TxThreshold << SPI_FIFO_CTL_TX_THRESHOLD_Pos) |
+ (u32RxThreshold << SPI_FIFO_CTL_RX_THRESHOLD_Pos));
+
+ spi->CNTRL |= SPI_CNTRL_FIFO_Msk;
+}
+
+/**
+ * @brief Disable FIFO mode.
+ * @param spi is the base address of SPI module.
+ * @return None
+ */
+void SPI_DisableFIFO(SPI_T *spi)
+{
+ spi->CNTRL &= ~SPI_CNTRL_FIFO_Msk;
+}
+
+/**
+ * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
+ * @param spi is the base address of SPI module.
+ * @return Actual SPI bus clock frequency.
+ */
+uint32_t SPI_GetBusClock(SPI_T *spi)
+{
+ uint32_t u32Div;
+ uint32_t u32ClkSrc;
+
+ if(((SYS->PDID & 0xF0000000) == 0) || ((SYS->PDID & 0xF0000000) == 0x10000000)) /* For M05xxAN and M05xxBN, the SPI peripheral clock source is PCLK. */
+ {
+ /* Get the system clock rate */
+ u32ClkSrc = CLK_GetHCLKFreq();
+
+ if(((SYS->PDID & 0xF0000000) == 0x10000000) && (spi->CNTRL2 & SPI_CNTRL2_DIV_ONE_Msk))
+ {
+ /* SPI bus clock rate is equal to system clock rate */
+ return u32ClkSrc;
+ }
+
+ /* Get DIVIDER setting */
+ u32Div = (spi->DIVIDER & SPI_DIVIDER_DIVIDER_Msk) >> SPI_DIVIDER_DIVIDER_Pos;
+ /* Return SPI bus clock rate */
+ return (u32ClkSrc / ((u32Div + 1) * 2));
+ }
+ else /* M05xxDN or M05xxDE */
+ {
+ /* Get DIVIDER setting */
+ u32Div = (spi->DIVIDER & SPI_DIVIDER_DIVIDER_Msk) >> SPI_DIVIDER_DIVIDER_Pos;
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ }
+
+ if(spi->CNTRL2 & SPI_CNTRL2_BCn_Msk) /* BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ {
+ /* Return SPI bus clock rate */
+ return (u32ClkSrc / (u32Div + 1));
+ }
+ else /* BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
+ {
+ /* Return SPI bus clock rate */
+ return (u32ClkSrc / ((u32Div + 1) * 2));
+ }
+ }
+}
+
+/**
+ * @brief Enable SPI related interrupts specified by u32Mask parameter.
+ * @param spi is the base address of SPI module.
+ * @param u32Mask is the combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be enabled.
+ * (SPI_UNIT_INT_MASK, SPI_SSTA_INT_MASK, SPI_FIFO_TX_INT_MASK,
+ * SPI_FIFO_RX_INT_MASK, SPI_FIFO_RXOV_INT_MASK, SPI_FIFO_TIMEOUT_INT_MASK)
+ * @return None
+ */
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
+{
+ /* Enable unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+ spi->CNTRL |= SPI_CNTRL_IE_Msk;
+
+ /* Enable slave 3-wire mode start interrupt flag */
+ if((u32Mask & SPI_SSTA_INT_MASK) == SPI_SSTA_INT_MASK)
+ spi->CNTRL2 |= SPI_CNTRL2_SSTA_INTEN_Msk;
+
+ if(((SYS->PDID & 0xF0000000) == 0) || ((SYS->PDID & 0xF0000000) == 0x10000000)) /* M05xxAN or M05xxBN */
+ return; /* M05xxAN and M05xxBN does not support the following functions */
+
+ /* Enable TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TX_INT_MASK) == SPI_FIFO_TX_INT_MASK)
+ spi->FIFO_CTL |= SPI_FIFO_CTL_TX_INTEN_Msk;
+
+ /* Enable RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RX_INT_MASK) == SPI_FIFO_RX_INT_MASK)
+ spi->FIFO_CTL |= SPI_FIFO_CTL_RX_INTEN_Msk;
+
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+ spi->FIFO_CTL |= SPI_FIFO_CTL_RXOV_INTEN_Msk;
+
+ /* Enable RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_TIMEOUT_INT_MASK) == SPI_FIFO_TIMEOUT_INT_MASK)
+ spi->FIFO_CTL |= SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;
+}
+
+/**
+ * @brief Disable SPI related interrupts specified by u32Mask parameter.
+ * @param spi is the base address of SPI module.
+ * @param u32Mask is the combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be disabled.
+ * (SPI_UNIT_INT_MASK, SPI_SSTA_INT_MASK, SPI_FIFO_TX_INT_MASK,
+ * SPI_FIFO_RX_INT_MASK, SPI_FIFO_RXOV_INT_MASK, SPI_FIFO_TIMEOUT_INT_MASK)
+ * @return None
+ */
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
+{
+ /* Disable unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+ spi->CNTRL &= ~SPI_CNTRL_IE_Msk;
+
+ /* Disable slave 3-wire mode start interrupt flag */
+ if((u32Mask & SPI_SSTA_INT_MASK) == SPI_SSTA_INT_MASK)
+ spi->CNTRL2 &= ~SPI_CNTRL2_SSTA_INTEN_Msk;
+
+ if(((SYS->PDID & 0xF0000000) == 0) || ((SYS->PDID & 0xF0000000) == 0x10000000)) /* M05xxAN or M05xxBN */
+ return; /* M05xxAN and M05xxBN does not support the following functions */
+
+ /* Disable TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TX_INT_MASK) == SPI_FIFO_TX_INT_MASK)
+ spi->FIFO_CTL &= ~SPI_FIFO_CTL_TX_INTEN_Msk;
+
+ /* Disable RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RX_INT_MASK) == SPI_FIFO_RX_INT_MASK)
+ spi->FIFO_CTL &= ~SPI_FIFO_CTL_RX_INTEN_Msk;
+
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+ spi->FIFO_CTL &= ~SPI_FIFO_CTL_RXOV_INTEN_Msk;
+
+ /* Disable RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_TIMEOUT_INT_MASK) == SPI_FIFO_TIMEOUT_INT_MASK)
+ spi->FIFO_CTL &= ~SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;
+}
+
+/**
+ * @brief Get SPI related interrupt flags specified by u32Mask parameter.
+ * @param spi is the base address of SPI module.
+ * @param u32Mask is the combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be read.
+ * (SPI_UNIT_INT_MASK, SPI_SSTA_INT_MASK, SPI_FIFO_TX_INT_MASK,
+ * SPI_FIFO_RX_INT_MASK, SPI_FIFO_RXOV_INT_MASK, SPI_FIFO_TIMEOUT_INT_MASK)
+ * @return Interrupt flags of selected sources.
+ */
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+ uint32_t u32IntFlag = 0;
+
+ /* Check unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) && (spi->CNTRL & SPI_CNTRL_IF_Msk))
+ u32IntFlag |= SPI_UNIT_INT_MASK;
+
+ /* Check slave 3-wire mode start interrupt flag */
+ if((u32Mask & SPI_SSTA_INT_MASK) && (spi->CNTRL2 & SPI_CNTRL2_SLV_START_INTSTS_Msk))
+ u32IntFlag |= SPI_SSTA_INT_MASK;
+
+ if(((SYS->PDID & 0xF0000000) == 0) || ((SYS->PDID & 0xF0000000) == 0x10000000)) /* M05xxAN or M05xxBN */
+ return u32IntFlag; /* M05xxAN and M05xxBN does not support the following functions */
+
+ /* Check TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TX_INT_MASK) && (spi->STATUS & SPI_STATUS_TX_INTSTS_Msk))
+ u32IntFlag |= SPI_FIFO_TX_INT_MASK;
+
+ /* Check RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RX_INT_MASK) && (spi->STATUS & SPI_STATUS_RX_INTSTS_Msk))
+ u32IntFlag |= SPI_FIFO_RX_INT_MASK;
+
+ /* Check RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (spi->STATUS & SPI_STATUS_RX_OVERRUN_Msk))
+ u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
+
+ /* Check RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_TIMEOUT_INT_MASK) && (spi->STATUS & SPI_STATUS_TIMEOUT_Msk))
+ u32IntFlag |= SPI_FIFO_TIMEOUT_INT_MASK;
+
+ return u32IntFlag;
+}
+
+/**
+ * @brief Clear SPI related interrupt flags specified by u32Mask parameter.
+ * @param spi is the base address of SPI module.
+ * @param u32Mask is the combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared.
+ * (SPI_UNIT_INT_MASK, SPI_SSTA_INT_MASK,
+ * SPI_FIFO_RXOV_INT_MASK, SPI_FIFO_TIMEOUT_INT_MASK)
+ * @return None
+ */
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+ if(u32Mask & SPI_UNIT_INT_MASK)
+ spi->CNTRL |= SPI_CNTRL_IF_Msk; /* Clear unit transfer interrupt flag */
+
+ if(u32Mask & SPI_SSTA_INT_MASK)
+ spi->CNTRL2 |= SPI_CNTRL2_SLV_START_INTSTS_Msk; /* Clear slave 3-wire mode start interrupt flag */
+
+ if(((SYS->PDID & 0xF0000000) == 0) || ((SYS->PDID & 0xF0000000) == 0x10000000)) /* M05xxAN or M05xxBN */
+ return; /* M05xxAN and M05xxBN does not support the following functions */
+
+ if(u32Mask & SPI_FIFO_RXOV_INT_MASK)
+ spi->STATUS = SPI_STATUS_RX_OVERRUN_Msk; /* Clear RX overrun interrupt flag */
+
+ if(u32Mask & SPI_FIFO_TIMEOUT_INT_MASK)
+ spi->STATUS = SPI_STATUS_TIMEOUT_Msk; /* Clear RX time-out interrupt flag */
+}
+
+/**
+ * @brief Get SPI related status specified by u32Mask parameter.
+ * @param spi is the base address of SPI module.
+ * @param u32Mask is the combination of all related sources.
+ * Each bit corresponds to a source.
+ * This parameter decides which flags will be read.
+ * (SPI_BUSY_MASK, SPI_RX_EMPTY_MASK, SPI_RX_FULL_MASK,
+ * SPI_TX_EMPTY_MASK, SPI_TX_FULL_MASK)
+ * @return Flags of selected sources.
+ */
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
+{
+ uint32_t u32Flag = 0;
+
+ /* Check busy status */
+ if((u32Mask & SPI_BUSY_MASK) && (spi->CNTRL & SPI_CNTRL_GO_BUSY_Msk))
+ u32Flag |= SPI_BUSY_MASK;
+
+ if(((SYS->PDID & 0xF0000000) == 0) || ((SYS->PDID & 0xF0000000) == 0x10000000)) /* M05xxAN or M05xxBN */
+ return u32Flag; /* M05xxAN and M05xxBN does not support the following functions */
+
+ /* Check RX empty flag */
+ if((u32Mask & SPI_RX_EMPTY_MASK) && (spi->CNTRL & SPI_CNTRL_RX_EMPTY_Msk))
+ u32Flag |= SPI_RX_EMPTY_MASK;
+
+ /* Check RX full flag */
+ if((u32Mask & SPI_RX_FULL_MASK) && (spi->CNTRL & SPI_CNTRL_RX_FULL_Msk))
+ u32Flag |= SPI_RX_FULL_MASK;
+
+ /* Check TX empty flag */
+ if((u32Mask & SPI_TX_EMPTY_MASK) && (spi->CNTRL & SPI_CNTRL_TX_EMPTY_Msk))
+ u32Flag |= SPI_TX_EMPTY_MASK;
+
+ /* Check TX full flag */
+ if((u32Mask & SPI_TX_FULL_MASK) && (spi->CNTRL & SPI_CNTRL_TX_FULL_Msk))
+ u32Flag |= SPI_TX_FULL_MASK;
+
+ return u32Flag;
+}
+
+/*@}*/ /* end of group M051_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_SPI_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/sys.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/sys.c
new file mode 100644
index 0000000000000000000000000000000000000000..780d92ce4ec550076061a6acc809728c07d71363
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/sys.c
@@ -0,0 +1,161 @@
+/**************************************************************************//**
+ * @file sys.c
+ * @version V3.00
+ * $Revision: 6 $
+ * $Date: 14/01/28 6:58p $
+ * @brief M051 series SYS driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_SYS_Driver SYS Driver
+ @{
+*/
+
+
+/** @addtogroup M051_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function clear the selected system reset source
+ * @param u32Src is system reset source
+ * @return None
+ */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+ SYS->RSTSRC |= u32Src;
+}
+
+/**
+ * @brief This function get Brown-out detector output status
+ * @return 0: System voltage is higher than BOD_VL setting or BOD_EN is 0.
+ * 1: System voltage is lower than BOD_VL setting.
+ * Note : If the BOD_EN is 0, this function always return 0.
+ */
+uint32_t SYS_GetBODStatus(void)
+{
+ return (SYS->BODCR & SYS_BODCR_BOD_OUT_Msk) ? 1 : 0;
+}
+
+/**
+ * @brief This function get the system reset source register value
+ * @return Reset source
+ */
+uint32_t SYS_GetResetSrc(void)
+{
+ return (SYS->RSTSRC);
+}
+
+/**
+ * @brief This function check register write-protection bit setting
+ * @return 0: Write-protection function is disabled.
+ * 1: Write-protection function is enabled.
+ */
+uint32_t SYS_IsRegLocked(void)
+{
+ return !(SYS->REGWRPROT & SYS_REGWRPROT_REGPROTDIS_Msk);
+}
+
+/**
+ * @brief This function get product ID.
+ * @return Product ID
+ */
+uint32_t SYS_ReadPDID(void)
+{
+ return SYS->PDID;
+}
+
+/**
+ * @brief This function reset chip.
+ * @return None
+ */
+void SYS_ResetChip(void)
+{
+ SYS->IPRSTC1 |= SYS_IPRSTC1_CHIP_RST_Msk;
+}
+
+/**
+ * @brief This function reset CPU.
+ * @return None
+ */
+void SYS_ResetCPU(void)
+{
+ SYS->IPRSTC1 |= SYS_IPRSTC1_CPU_RST_Msk;
+}
+
+/**
+ * @brief This function reset selected modules.
+ * @param u32ModuleIndex is module index. Including :
+ * - \ref CHIP_RST
+ * - \ref CPU_RST
+ * - \ref EBI_RST
+ * - \ref HDIV_RST
+ * - \ref GPIO_RST
+ * - \ref TMR0_RST
+ * - \ref TMR1_RST
+ * - \ref TMR2_RST
+ * - \ref TMR3_RST
+ * - \ref I2C0_RST
+ * - \ref I2C1_RST
+ * - \ref SPI0_RST
+ * - \ref SPI1_RST
+ * - \ref UART0_RST
+ * - \ref UART1_RST
+ * - \ref PWM03_RST
+ * - \ref PWM47_RST
+ * - \ref ACMP01_RST
+ * - \ref ACMP23_RST
+ * - \ref ADC_RST
+ * @return None
+ */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+ *(volatile uint32_t *)(&(SYS->IPRSTC1) + (u32ModuleIndex >> 24)) |= 1 << (u32ModuleIndex & 0x00ffffff);
+ *(volatile uint32_t *)(&(SYS->IPRSTC1) + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff));
+}
+
+/**
+ * @brief This function configure BOD function.
+ * Configure BOD reset or interrupt mode and set Brown-out voltage level.
+ * Enable Brown-out function
+ * @param i32Mode is reset or interrupt mode. Including :
+ * - \ref SYS_BODCR_BOD_RST_EN
+ * - \ref SYS_BODCR_BOD_INTERRUPT_EN
+ * @param u32BODLevel is Brown-out voltage level. Including :
+ * - \ref SYS_BODCR_BOD_VL_4_4V
+ * - \ref SYS_BODCR_BOD_VL_3_7V
+ * - \ref SYS_BODCR_BOD_VL_2_7V
+ * - \ref SYS_BODCR_BOD_VL_2_2V
+ * @return None
+ */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+ SYS->BODCR |= SYS_BODCR_BOD_EN_Msk;
+ SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_RSTEN_Msk) | i32Mode;
+ SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_VL_Msk) | u32BODLevel;
+}
+
+/**
+ * @brief This function disable BOD function.
+ * @return None
+ */
+void SYS_DisableBOD(void)
+{
+ SYS->BODCR &= ~SYS_BODCR_BOD_EN_Msk;
+}
+
+
+
+/*@}*/ /* end of group M051_SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_SYS_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/timer.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/timer.c
new file mode 100644
index 0000000000000000000000000000000000000000..352b736bf5b0cc638b18d4c2aa537b0bc2df67b1
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/timer.c
@@ -0,0 +1,292 @@
+/**************************************************************************//**
+ * @file timer.c
+ * @version V3.00
+ * $Revision: 6 $
+ * $Date: 14/01/28 4:19p $
+ * @brief M051 series Timer driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_TIMER_Driver TIMER Driver
+ @{
+*/
+
+/** @addtogroup M051_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+ @{
+*/
+
+/**
+ * @brief Open Timer in specified mode and frequency
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Mode Operation mode. Possible options are
+ * - \ref TIMER_ONESHOT_MODE
+ * - \ref TIMER_PERIODIC_MODE
+ * - \ref TIMER_TOGGLE_MODE
+ * - \ref TIMER_CONTINUOUS_MODE
+ * @param[in] u32Freq Target working frequency
+ *
+ * @return Real Timer working frequency
+ *
+ * @details This API is used to configure timer to operate in specified mode and frequency.
+ * If timer cannot work in target frequency, a closest frequency will be chose and returned.
+ * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
+ * \ref TIMER_Start macro or program registers directly.
+ */
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
+{
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);
+ uint32_t u32Cmpr = 0, u32Prescale = 0;
+
+ // Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0.
+ if(u32Freq > (u32Clk / 2))
+ {
+ u32Cmpr = 2;
+ }
+ else
+ {
+ if(u32Clk >= 0x4000000)
+ {
+ u32Prescale = 7; // real prescaler value is 8
+ u32Clk >>= 3;
+ }
+ else if(u32Clk >= 0x2000000)
+ {
+ u32Prescale = 3; // real prescaler value is 4
+ u32Clk >>= 2;
+ }
+ else if(u32Clk >= 0x1000000)
+ {
+ u32Prescale = 1; // real prescaler value is 2
+ u32Clk >>= 1;
+ }
+
+ u32Cmpr = u32Clk / u32Freq;
+ }
+
+ timer->TCSR = u32Mode | u32Prescale;
+ timer->TCMPR = u32Cmpr;
+
+ return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
+}
+
+/**
+ * @brief Stop Timer Counting
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API stops Timer counting and disable the Timer interrupt function.
+ */
+void TIMER_Close(TIMER_T *timer)
+{
+ timer->TCSR = 0;
+ timer->TEXCON = 0;
+}
+
+/**
+ * @brief Open Timer in specified mode and frequency
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
+ *
+ * @return None
+ *
+ * @details This API is used to create a delay loop for u32usec micro seconds.
+ * @note This API overwrites the register setting of the timer used to count the delay time.
+ * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
+ */
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
+{
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);
+ uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk;
+ uint32_t u32Cmpr, u32NsecPerTick;
+
+ // Clear current timer configuration/
+ timer->TCSR = 0;
+ timer->TEXCON = 0;
+
+ if (u32Clk <= 1000000) // min delay is 1000 us if timer clock source is <= 1 MHz
+ {
+ if (u32Usec < 1000)
+ u32Usec = 1000;
+ if (u32Usec > 1000000)
+ u32Usec = 1000000;
+ }
+ else
+ {
+ if (u32Usec < 100)
+ u32Usec = 100;
+ if (u32Usec > 1000000)
+ u32Usec = 1000000;
+ }
+
+ if (u32Clk <= 1000000)
+ {
+ u32Prescale = 0;
+ u32NsecPerTick = 1000000000 / u32Clk;
+ u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
+ }
+ else
+ {
+ if (u32Clk > 64000000)
+ {
+ u32Prescale = 7; // real prescaler value is 8
+ u32Clk >>= 3;
+ }
+ else if (u32Clk > 32000000)
+ {
+ u32Prescale = 3; // real prescaler value is 4
+ u32Clk >>= 2;
+ }
+ else if (u32Clk > 16000000)
+ {
+ u32Prescale = 1; // real prescaler value is 2
+ u32Clk >>= 1;
+ }
+
+ if (u32Usec < 250)
+ {
+ u32Cmpr = (u32Usec * u32Clk) / 1000000;
+ }
+ else
+ {
+ u32NsecPerTick = 1000000000 / u32Clk;
+ u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
+ }
+ }
+
+ timer->TCMPR = u32Cmpr;
+ timer->TCSR = TIMER_TCSR_CEN_Msk | (u32Prescale - 1); // one shot mode
+
+ // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
+ // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
+ for(; delay > 0; delay--)
+ {
+ __NOP();
+ }
+
+ while(timer->TCSR & TIMER_TCSR_CACT_Msk);
+}
+
+/**
+ * @brief Enable Timer Capture Function
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32CapMode Timer capture mode. Could be
+ * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
+ * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
+ * @param[in] u32Edge Timer capture edge. Possible values are
+ * - \ref TIMER_CAPTURE_FALLING_EDGE
+ * - \ref TIMER_CAPTURE_RISING_EDGE
+ * - \ref TIMER_CAPTURE_FALLING_AND_RISING_EDGE
+ *
+ * @return None
+ *
+ * @details This API is used to enable timer capture function with specified mode and capture edge.
+ * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
+ */
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
+{
+
+ timer->TEXCON = (timer->TEXCON & ~(TIMER_TEXCON_RSTCAPSEL_Msk |
+ TIMER_TEXCON_TEX_EDGE_Msk)) |
+ u32CapMode | u32Edge | TIMER_TEXCON_TEXEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Capture Function
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API is used to disable the Timer capture function.
+ */
+void TIMER_DisableCapture(TIMER_T *timer)
+{
+ timer->TEXCON &= ~TIMER_TEXCON_TEXEN_Msk;
+}
+
+/**
+ * @brief Enable Timer Counter Function
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Edge Detection edge of counter pin. Could be ether
+ * - \ref TIMER_COUNTER_FALLING_EDGE, or
+ * - \ref TIMER_COUNTER_RISING_EDGE
+ *
+ * @return None
+ *
+ * @details This function is used to enable the Timer counter function with specify detection edge.
+ * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
+ * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
+ */
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
+{
+ timer->TEXCON = (timer->TEXCON & ~TIMER_TEXCON_TX_PHASE_Msk) | u32Edge;
+ timer->TCSR |= TIMER_TCSR_CTB_Msk;
+}
+
+/**
+ * @brief Disable Timer Counter Function
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API is used to disable the Timer event counter function.
+ */
+void TIMER_DisableEventCounter(TIMER_T *timer)
+{
+ timer->TCSR &= ~TIMER_TCSR_CTB_Msk;
+}
+
+/**
+ * @brief Get Timer Clock Frequency
+ *
+ * @param[in] timer The base address of Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Timer clock frequency
+ *
+ * @details This API is used to get the clock frequency of Timer.
+ * @note This API cannot return correct clock rate if timer source is external clock input.
+ */
+uint32_t TIMER_GetModuleClock(TIMER_T *timer)
+{
+ uint32_t u32Src;
+ const uint32_t au32Clk[] = {__HXT, 0, 0, 0, 0, __LIRC, 0, __HIRC};
+
+ if(timer == TIMER0)
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0_S_Msk) >> CLK_CLKSEL1_TMR0_S_Pos;
+ else if(timer == TIMER1)
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1_S_Msk) >> CLK_CLKSEL1_TMR1_S_Pos;
+ else if(timer == TIMER2)
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2_S_Msk) >> CLK_CLKSEL1_TMR2_S_Pos;
+ else // Timer 3
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3_S_Msk) >> CLK_CLKSEL1_TMR3_S_Pos;
+
+ if(u32Src == 2)
+ {
+ return(SystemCoreClock);
+ }
+
+ return(au32Clk[u32Src]);
+}
+
+/*@}*/ /* end of group M051_TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_TIMER_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/uart.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/uart.c
new file mode 100644
index 0000000000000000000000000000000000000000..53525eaf43d79ac0cb0785eb332ffa23ee7b95d1
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/uart.c
@@ -0,0 +1,459 @@
+/**************************************************************************//**
+ * @file uart.c
+ * @version V3.00
+ * $Revision: 27 $
+ * $Date: 14/01/29 11:05a $
+ * @brief M051 series UART driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include "M051Series.h"
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_UART_Driver UART Driver
+ @{
+*/
+
+
+/** @addtogroup M051_UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+
+/**
+ * @brief The function is used to clear UART specified interrupt flag.
+ *
+ * @param uart The base address of UART module.
+ * @param u32InterruptFlag The specified interrupt of UART module.
+ * - UART_ISR_LIN_RX_BREAK_INT_Msk : LIN bus interrupt
+ * - UART_ISR_BUF_ERR_INT_Msk : Buffer Error interrupt
+ * - UART_ISR_MODEM_INT_Msk : Modem interrupt
+ * - UART_ISR_RLS_INT_Msk : Rx Line status interrupt
+ *
+ * @return None
+ */
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
+{
+
+ if(u32InterruptFlag & UART_ISR_RLS_INT_Msk) /* clear Receive Line Status Interrupt */
+ {
+ uart->FSR |= UART_FSR_BIF_Msk | UART_FSR_FEF_Msk | UART_FSR_FEF_Msk;
+ uart->FSR |= UART_FSR_RS485_ADD_DETF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_ISR_MODEM_INT_Msk) /* clear Modem Interrupt */
+ uart->MSR |= UART_MSR_DCTSF_Msk;
+
+ if(u32InterruptFlag & UART_ISR_BUF_ERR_INT_Msk) /* clear Buffer Error Interrupt */
+ {
+ uart->FSR |= UART_FSR_RX_OVER_IF_Msk | UART_FSR_TX_OVER_IF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_ISR_LIN_RX_BREAK_INT_Msk) /* clear LIN break Interrupt */
+ uart->ISR |= UART_ISR_LIN_RX_BREAK_IF_Msk;
+
+}
+
+
+/**
+ * @brief The function is used to disable UART.
+ *
+ * @param uart The base address of UART module.
+ *
+ * @return None
+ */
+void UART_Close(UART_T* uart)
+{
+ uart->IER = 0;
+}
+
+
+/**
+ * @brief The function is used to disable UART auto flow control.
+ *
+ * @param uart The base address of UART module.
+ *
+ * @return None
+ */
+void UART_DisableFlowCtrl(UART_T* uart)
+{
+ uart->IER &= ~(UART_IER_AUTO_RTS_EN_Msk | UART_IER_AUTO_CTS_EN_Msk);
+}
+
+
+/**
+ * @brief The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ *
+ * @param uart The base address of UART module.
+ * @param u32InterruptFlag The specified interrupt of UART module.
+ * - UART_IER_LIN_RX_BRK_IEN_Msk : LIN bus interrupt
+ * - UART_IER_WAKE_EN_Msk : Wakeup interrupt
+ * - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt
+ * - UART_IER_RTO_IEN_Msk : Rx time-out interrupt
+ * - UART_IER_MODEM_IEN_Msk : Modem interrupt
+ * - UART_IER_RLS_IEN_Msk : Rx Line status interrupt
+ * - UART_IER_THRE_IEN_Msk : Tx empty interrupt
+ * - UART_IER_RDA_IEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ */
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag)
+{
+ /* Disable UART specified interrupt */
+ UART_DISABLE_INT(uart, u32InterruptFlag);
+
+ /* Disable NVIC UART IRQ */
+ if(uart == UART0)
+ NVIC_DisableIRQ(UART0_IRQn);
+ else
+ NVIC_DisableIRQ(UART1_IRQn);
+}
+
+
+/**
+ * @brief The function is used to Enable UART auto flow control.
+ *
+ * @param uart The base address of UART module.
+ *
+ * @return None
+ */
+void UART_EnableFlowCtrl(UART_T* uart)
+{
+ /* Set RTS pin output is low level active */
+ uart->MCR |= UART_MCR_LEV_RTS_Msk;
+
+ /* Set CTS pin input is low level active */
+ uart->MSR |= UART_MSR_LEV_CTS_Msk;
+
+ /* Set RTS and CTS auto flow control enable */
+ uart->IER |= UART_IER_AUTO_RTS_EN_Msk | UART_IER_AUTO_CTS_EN_Msk;
+}
+
+
+/**
+ * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ *
+ * @param uart The base address of UART module.
+ * @param u32InterruptFlag The specified interrupt of UART module:
+ * - UART_IER_LIN_RX_BRK_IEN_Msk : LIN bus interrupt * - UART_IER_WAKE_EN_Msk : Wakeup interrupt
+ * - UART_IER_WAKE_EN_Msk : Wakeup interrupt
+ * - UART_IER_BUF_ERR_IEN_Msk : Buffer Error interrupt
+ * - UART_IER_RTO_IEN_Msk : Rx time-out interrupt
+ * - UART_IER_MODEM_IEN_Msk : Modem interrupt
+ * - UART_IER_RLS_IEN_Msk : Rx Line status interrupt
+ * - UART_IER_THRE_IEN_Msk : Tx empty interrupt
+ * - UART_IER_RDA_IEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ */
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag)
+{
+
+ /* Enable UART specified interrupt */
+ UART_ENABLE_INT(uart, u32InterruptFlag);
+
+ /* Enable NVIC UART IRQ */
+ if(uart == UART0)
+ NVIC_EnableIRQ(UART0_IRQn);
+ else
+ NVIC_EnableIRQ(UART1_IRQn);
+
+}
+
+
+/**
+ * @brief This function use to enable UART function and set baud-rate.
+ *
+ * @param uart The base address of UART module.
+ * @param u32baudrate The baudrate of UART module.
+ *
+ * @return None
+ */
+void UART_Open(UART_T* uart, uint32_t u32baudrate)
+{
+ uint8_t u8UartClkSrcSel;
+ uint32_t u32ClkTbl[4] = {__HXT, 0, 0, __HIRC};
+ uint32_t u32Baud_Div = 0;
+
+ /* Get UART clock source selection */
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos;
+
+ /* Select UART function */
+ uart->FUN_SEL = UART_FUNC_SEL_UART;
+
+ /* Set UART line configuration */
+ uart->LCR = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
+
+ /* Set UART Rx and RTS trigger level */
+ uart->FCR &= ~(UART_FCR_RFITL_Msk | UART_FCR_RTS_TRI_LEV_Msk);
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u8UartClkSrcSel == 1)
+ u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+ /* Set UART baud rate */
+ if(u32baudrate != 0)
+ {
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32ClkTbl[u8UartClkSrcSel], u32baudrate);
+
+ if(u32Baud_Div > 0xFFFF)
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32ClkTbl[u8UartClkSrcSel], u32baudrate));
+ else
+ uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+}
+
+
+/**
+ * @brief The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ *
+ * @param uart The base address of UART module.
+ * @param pu8RxBuf The buffer to receive the data of receive FIFO.
+ * @param u32ReadBytes The the read bytes number of data.
+ *
+ * @return u32Count: Receive byte count
+ *
+ */
+uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
+{
+ uint32_t u32Count, u32delayno;
+
+ for(u32Count = 0; u32Count < u32ReadBytes; u32Count++)
+ {
+ u32delayno = 0;
+
+ while(uart->FSR & UART_FSR_RX_EMPTY_Msk) /* Check RX empty => failed */
+ {
+ u32delayno++;
+ if(u32delayno >= 0x40000000)
+ return FALSE;
+ }
+ pu8RxBuf[u32Count] = uart->RBR; /* Get Data from UART RX */
+ }
+
+ return u32Count;
+
+}
+
+
+/**
+ * @brief This function use to config UART line setting.
+ *
+ * @param uart The base address of UART module.
+ * @param u32baudrate The register value of baudrate of UART module.
+ * If u32baudrate = 0, UART baudrate will not change.
+ * @param u32data_width The data length of UART module.
+ * - UART_WORD_LEN_5
+ * - UART_WORD_LEN_6
+ * - UART_WORD_LEN_7
+ * - UART_WORD_LEN_8
+ * @param u32parity The parity setting (none/odd/even/mark/space) of UART module.
+ * - UART_PARITY_NONE
+ * - UART_PARITY_ODD
+ * - UART_PARITY_EVEN
+ * - UART_PARITY_MARK
+ * - UART_PARITY_SPACE
+ * @param u32stop_bits The stop bit length (1/1.5/2 bit) of UART module.
+ * - UART_STOP_BIT_1
+ * - UART_STOP_BIT_1_1.5
+ * - UART_STOP_BIT_2
+ *
+ * @return None
+ */
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
+{
+ uint8_t u8UartClkSrcSel;
+ uint32_t u32ClkTbl[4] = {__HXT, 0, 0, __HIRC};
+ uint32_t u32Baud_Div = 0;
+
+ /* Get UART clock source selection */
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos;
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u8UartClkSrcSel == 1)
+ u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+ /* Set UART baud rate */
+ if(u32baudrate != 0)
+ {
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32ClkTbl[u8UartClkSrcSel], u32baudrate);
+
+ if(u32Baud_Div > 0xFFFF)
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32ClkTbl[u8UartClkSrcSel], u32baudrate));
+ else
+ uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+
+ /* Set UART line configuration */
+ uart->LCR = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ * @brief This function use to set Rx timeout count.
+ *
+ * @param uart The base address of UART module.
+ * @param u32TOC Rx timeout counter.
+ *
+ * @return None
+ */
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
+{
+ /* Set time-out interrupt comparator */
+ uart->TOR = (uart->TOR & ~UART_TOR_TOIC_Msk) | (u32TOC);
+
+ /* Set time-out counter enable */
+ uart->IER |= UART_IER_TIME_OUT_EN_Msk;
+}
+
+
+/**
+ * @brief The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ *
+ * @param uart The base address of UART module.
+ * @param u32Buadrate The baudrate of UART module.
+ * @param u32Direction The direction(transmit:1/receive:0) of UART module in IrDA mode.
+ *
+ * @return None
+ */
+/**
+ * @brief The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ *
+ * @param uart The base address of UART module.
+ * @param u32Buadrate The baudrate of UART module.
+ * @param u32Direction The direction(transmit:1/receive:0) of UART module in IrDA mode:
+ * - UART_IRCR_TX_SELECT
+ * - UART_IRCR_RX_SELECT
+ *
+ * @return None
+ */
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+ uint8_t u8UartClkSrcSel;
+ uint32_t u32ClkTbl[4] = {__HXT, 0, 0, __HIRC};
+ uint32_t u32Baud_Div;
+
+ /* Select IrDA function mode */
+ uart->FUN_SEL = UART_FUNC_SEL_IrDA;
+
+ /* Get UART clock source selection */
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos;
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u8UartClkSrcSel == 1)
+ u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+ /* Set UART IrDA baud rate in mode 0 */
+ if(u32Buadrate != 0)
+ {
+ u32Baud_Div = UART_BAUD_MODE0_DIVIDER(u32ClkTbl[u8UartClkSrcSel], u32Buadrate);
+
+ if(u32Baud_Div < 0xFFFF)
+ uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
+ }
+
+ /* Configure IrDA relative settings */
+ if(u32Direction == UART_IRCR_TX_SELECT)
+ {
+ uart->IRCR &= ~UART_IRCR_INV_TX_Msk; //Tx signal is not inversed
+ uart->IRCR |= UART_IRCR_TX_SELECT_Msk;
+ }
+ else
+ {
+ uart->IRCR |= UART_IRCR_INV_RX_Msk; //Rx signal is inversed
+ uart->IRCR &= ~UART_IRCR_TX_SELECT_Msk;
+ }
+}
+
+
+/**
+ * @brief The function is used to set RS485 relative setting.
+ *
+ * @param uart The base address of UART module.
+ * @param u32Mode The operation mode(NMM/AUD/AAD).
+ * - UART_ALT_CSR_RS485_NMM_Msk
+ * - UART_ALT_CSR_RS485_AUD_Msk
+ * - UART_ALT_CSR_RS485_AAD_Msk
+ * @param u32Addr The RS485 address.
+ *
+ * @return None
+ */
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+ /* Select UART RS485 function mode */
+ uart->FUN_SEL = UART_FUNC_SEL_RS485;
+
+ /* Set RS585 configuration */
+ uart->ALT_CSR &= ~(UART_ALT_CSR_RS485_NMM_Msk | UART_ALT_CSR_RS485_AUD_Msk | UART_ALT_CSR_RS485_AAD_Msk | UART_ALT_CSR_ADDR_MATCH_Msk);
+ uart->ALT_CSR |= (u32Mode | (u32Addr << UART_ALT_CSR_ADDR_MATCH_Pos));
+}
+
+
+/**
+ * @brief The function is used to set LIN relative setting.
+ *
+ * @param uart The base address of UART module.
+ * @param u32Mode The LIN direction :
+ * - UART_ALT_CSR_LIN_TX_EN_Msk
+ * - UART_ALT_CSR_LIN_RX_EN_Msk
+ * - (UART_ALT_CSR_LIN_TX_EN_Msk|UART_ALT_CSR_LIN_RX_EN_Msk)
+ * @param u32BreakLength The breakfield length is u32BreakLength+2.
+ *
+ * @return None
+ */
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+ /* Select LIN function mode */
+ uart->FUN_SEL = UART_FUNC_SEL_LIN;
+
+ /* Select LIN function setting : Tx enable, Rx enable and break field length */
+ uart->ALT_CSR &= ~(UART_ALT_CSR_LIN_TX_EN_Msk | UART_ALT_CSR_LIN_TX_EN_Msk | UART_ALT_CSR_UA_LIN_BKFL_Msk);
+ uart->ALT_CSR |= (u32Mode | (u32BreakLength << UART_ALT_CSR_UA_LIN_BKFL_Pos));
+}
+
+
+/**
+ * @brief The function is to write data into TX buffer to transmit data by UART.
+ *
+ * @param uart The base address of UART module.
+ * @param pu8TxBuf The buffer to send the data to UART transmission FIFO.
+ * @param u32WriteBytes The byte number of data.
+ *
+ * @return u32Count: transfer byte count
+ */
+uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
+{
+ uint32_t u32Count, u32delayno;
+
+ for(u32Count = 0; u32Count != u32WriteBytes; u32Count++)
+ {
+ u32delayno = 0;
+ while((uart->FSR & UART_FSR_TE_FLAG_Msk) == 0) /* Wait Tx empty and Time-out manner */
+ {
+ u32delayno++;
+ if(u32delayno >= 0x40000000)
+ return FALSE;
+ }
+ uart->THR = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
+ }
+
+ return u32Count;
+
+}
+
+
+/*@}*/ /* end of group M051_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_UART_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2012 Nuvoton Technology Corp. ***/
+
+
+
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/wdt.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/wdt.c
new file mode 100644
index 0000000000000000000000000000000000000000..ea000be90b521d790506b1692f958d3b7b1aca11
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/wdt.c
@@ -0,0 +1,69 @@
+/**************************************************************************//**
+ * @file wdt.c
+ * @version V3.00
+ * $Revision: 2 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series WDT driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_WDT_Driver WDT Driver
+ @{
+*/
+
+/** @addtogroup M051_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize WDT counter and start counting
+ *
+ * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
+ * - \ref WDT_TIMEOUT_2POW4
+ * - \ref WDT_TIMEOUT_2POW6
+ * - \ref WDT_TIMEOUT_2POW8
+ * - \ref WDT_TIMEOUT_2POW10
+ * - \ref WDT_TIMEOUT_2POW12
+ * - \ref WDT_TIMEOUT_2POW14
+ * - \ref WDT_TIMEOUT_2POW16
+ * - \ref WDT_TIMEOUT_2POW18
+ * @param[in] u32ResetDelay Configure reset delay period while WDT time-out happened. Valid values are:
+ * - \ref WDT_RESET_DELAY_1026CLK
+ * - \ref WDT_RESET_DELAY_130CLK
+ * - \ref WDT_RESET_DELAY_18CLK
+ * - \ref WDT_RESET_DELAY_3
+ * @param[in] u32EnableReset Enable WDT rest system function. Valid values are TRUE and FALSE.
+ * @param[in] u32EnableWakeup Enable WDT wake-up system function. Valid values are TRUE and FALSE.
+ *
+ * @return None
+ *
+ * @details This function make WDT module start counting with different time-out interval and reset delay period.
+ */
+void WDT_Open(uint32_t u32TimeoutInterval,
+ uint32_t u32ResetDelay,
+ uint32_t u32EnableReset,
+ uint32_t u32EnableWakeup)
+{
+ WDT->WTCRALT = u32ResetDelay;
+
+ WDT->WTCR = u32TimeoutInterval | WDT_WTCR_WTE_Msk |
+ (u32EnableReset << WDT_WTCR_WTRE_Pos) |
+ (u32EnableWakeup << WDT_WTCR_WTWKE_Pos);
+ return;
+}
+
+/*@}*/ /* end of group M051_WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_WDT_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/Libraries/StdDriver/src/wwdt.c b/bsp/nuvoton_m05x/Libraries/StdDriver/src/wwdt.c
new file mode 100644
index 0000000000000000000000000000000000000000..0e194f70b8a1d283744c76c17409595b8488511f
--- /dev/null
+++ b/bsp/nuvoton_m05x/Libraries/StdDriver/src/wwdt.c
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+ * @file wwdt.c
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 14/01/28 10:49a $
+ * @brief M051 series WWDT driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M051Series.h"
+
+
+/** @addtogroup M051_Device_Driver M051 Device Driver
+ @{
+*/
+
+/** @addtogroup M051_WWDT_Driver WWDT Driver
+ @{
+*/
+
+/** @addtogroup M051_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Open WWDT function to start counting
+ *
+ * @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are:
+ * - \ref WWDT_PRESCALER_1
+ * - \ref WWDT_PRESCALER_2
+ * - \ref WWDT_PRESCALER_4
+ * - \ref WWDT_PRESCALER_8
+ * - \ref WWDT_PRESCALER_16
+ * - \ref WWDT_PRESCALER_32
+ * - \ref WWDT_PRESCALER_64
+ * - \ref WWDT_PRESCALER_128
+ * - \ref WWDT_PRESCALER_192
+ * - \ref WWDT_PRESCALER_256
+ * - \ref WWDT_PRESCALER_384
+ * - \ref WWDT_PRESCALER_512
+ * - \ref WWDT_PRESCALER_768
+ * - \ref WWDT_PRESCALER_1024
+ * - \ref WWDT_PRESCALER_1536
+ * - \ref WWDT_PRESCALER_2048
+ * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F.
+ * @param[in] u32EnableInt Enable WWDT interrupt function. Valid values are TRUE and FALSE.
+ *
+ * @return None
+ *
+ * @details This function make WWDT module start counting with different counter period and compared window value.
+ * @note Application can call this function only once after boot up.
+ */
+void WWDT_Open(uint32_t u32PreScale,
+ uint32_t u32CmpValue,
+ uint32_t u32EnableInt)
+{
+ WWDT->WWDTCR = u32PreScale |
+ (u32CmpValue << WWDT_WWDTCR_WINCMP_Pos) |
+ ((u32EnableInt == TRUE) ? WWDT_WWDTCR_WWDTIE_Msk : 0) |
+ WWDT_WWDTCR_WWDTEN_Msk;
+ return;
+}
+
+/*@}*/ /* end of group M051_WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M051_WWDT_Driver */
+
+/*@}*/ /* end of group M051_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m05x/SConscript b/bsp/nuvoton_m05x/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..fe0ae941ae9a759ae478de901caec1c961e56af8
--- /dev/null
+++ b/bsp/nuvoton_m05x/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nuvoton_m05x/SConstruct b/bsp/nuvoton_m05x/SConstruct
new file mode 100644
index 0000000000000000000000000000000000000000..7fad129d8eb214a805687643ca359c43ada56610
--- /dev/null
+++ b/bsp/nuvoton_m05x/SConstruct
@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-nuvotan_m05x.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/nuvoton_m05x/applications/SConscript b/bsp/nuvoton_m05x/applications/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..01eb940dfb35f92c503a78b0b49a4354590f9f3a
--- /dev/null
+++ b/bsp/nuvoton_m05x/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuvoton_m05x/applications/application.c b/bsp/nuvoton_m05x/applications/application.c
new file mode 100644
index 0000000000000000000000000000000000000000..bf48aeb4a3d12ecd18d4c64b680d78f103732135
--- /dev/null
+++ b/bsp/nuvoton_m05x/applications/application.c
@@ -0,0 +1,84 @@
+/*
+ * File : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-11-23 Bright first implementation
+ */
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+#include
+
+#include
+#include
+#ifdef RT_USING_COMPONENTS_INIT
+#include
+#endif /* RT_USING_COMPONENTS_INIT */
+
+#include "led.h"
+
+/* led thread entry */
+static void led_thread_entry(void* parameter)
+{
+ while(1)
+ {
+ rt_hw_led_on();
+ rt_thread_delay(RT_TICK_PER_SECOND);
+ rt_hw_led_off();
+ rt_thread_delay(RT_TICK_PER_SECOND);
+ }
+}
+
+static void rt_init_thread_entry(void* parameter)
+{
+ rt_thread_t led_thread;
+
+/* Initialization RT-Thread Components */
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_init();
+#endif
+
+/* Set finsh device */
+#ifdef RT_USING_FINSH
+ finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_FINSH */
+
+ /* Create led thread */
+ led_thread = rt_thread_create("led",
+ led_thread_entry, RT_NULL,
+ 256, 20, 20);
+ if(led_thread != RT_NULL)
+ rt_thread_startup(led_thread);
+}
+
+int rt_application_init()
+{
+ rt_thread_t init_thread;
+
+#if (RT_THREAD_PRIORITY_MAX == 32)
+ init_thread = rt_thread_create("init",
+ rt_init_thread_entry, RT_NULL,
+ 512, 8, 20);
+#else
+ init_thread = rt_thread_create("init",
+ rt_init_thread_entry, RT_NULL,
+ 512, 80, 20);
+#endif
+ if(init_thread != RT_NULL)
+ rt_thread_startup(init_thread);
+
+ return 0;
+}
+
+
+/*@}*/
diff --git a/bsp/nuvoton_m05x/applications/startup.c b/bsp/nuvoton_m05x/applications/startup.c
new file mode 100644
index 0000000000000000000000000000000000000000..f35e595c9c113b51f4981d0b33d50e7cfaaa100e
--- /dev/null
+++ b/bsp/nuvoton_m05x/applications/startup.c
@@ -0,0 +1,115 @@
+/*
+ * File : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-11-23 Bright first implementation
+ */
+
+#include
+#include
+
+#include "board.h"
+
+/**
+ * @addtogroup NUVOTON_M05X
+ */
+
+/*@{*/
+
+extern int rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define M05X_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define M05X_SRAM_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define M05X_SRAM_BEGIN (&__bss_end)
+#endif
+
+/*******************************************************************************
+* Function Name : assert_failed
+* Description : Reports the name of the source file and the source line number
+* where the assert error has occurred.
+* Input : - file: pointer to the source file name
+* - line: assert error line source number
+* Output : None
+* Return : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+ rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+ rt_kprintf(" file %s\r\n", file);
+ rt_kprintf(" line %d\r\n", line);
+
+ while (1) ;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+ /* init board */
+ rt_hw_board_init();
+
+ /* show version */
+ rt_show_version();
+
+ /* init tick */
+ rt_system_tick_init();
+
+ /* init kernel object */
+ rt_system_object_init();
+
+ /* init timer system */
+ rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+ rt_system_heap_init((void*)M05X_SRAM_BEGIN, (void*)M05X_SRAM_END);
+#endif
+
+ /* init scheduler system */
+ rt_system_scheduler_init();
+
+ /* init application */
+ rt_application_init();
+
+ /* init timer thread */
+ rt_system_timer_thread_init();
+
+ /* init idle thread */
+ rt_thread_idle_init();
+
+ /* start scheduler */
+ rt_system_scheduler_start();
+
+ /* never reach here */
+ return ;
+}
+
+int main(void)
+{
+ /* disable interrupt first */
+ rt_hw_interrupt_disable();
+
+ /* startup RT-Thread RTOS */
+ rtthread_startup();
+
+ return 0;
+}
+
+/*@}*/
diff --git a/bsp/nuvoton_m05x/drivers/SConscript b/bsp/nuvoton_m05x/drivers/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..5bbef48785846a30d44415d5e06808a4f2620933
--- /dev/null
+++ b/bsp/nuvoton_m05x/drivers/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'drivers')
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuvoton_m05x/drivers/board.c b/bsp/nuvoton_m05x/drivers/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..8c9bd8ea76073584e6f622c53ff6f1863c714dab
--- /dev/null
+++ b/bsp/nuvoton_m05x/drivers/board.c
@@ -0,0 +1,92 @@
+/*
+ * File : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-11-23 Bright first implementation
+ */
+
+#include
+#include
+
+#include "board.h"
+
+/* RT_USING_COMPONENTS_INIT */
+#ifdef RT_USING_COMPONENTS_INIT
+#include
+#endif
+/**
+ * @addtogroup NUVOTON_M05X
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name : NVIC_Configuration
+* Description : Configures Vector Table base location.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+// NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+/**
+* @brief Inserts a delay time.
+* @param nCount: specifies the delay time length.
+* @retval None
+*/
+static void Delay(__IO uint32_t nCount)
+{
+ /* Decrement nCount value */
+ while (nCount != 0)
+ {
+ nCount--;
+ }
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+/**
+ * This function will initial Nuvoton board.
+ */
+void rt_hw_board_init()
+{
+ /* NVIC Configuration */
+ NVIC_Configuration();
+
+ /* Configure the SysTick */
+ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+ /* Initial usart deriver, and set console device */
+#ifdef RT_USING_CONSOLE
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+ /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+}
+
+/*@}*/
diff --git a/bsp/nuvoton_m05x/drivers/board.h b/bsp/nuvoton_m05x/drivers/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..e2f4ed673f720290dbf7c73833c34ed3534b2f1a
--- /dev/null
+++ b/bsp/nuvoton_m05x/drivers/board.h
@@ -0,0 +1,33 @@
+/*
+ * File : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-11-23 Bright add board.h to this bsp
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "M051Series.h"
+
+/* board configuration */
+// Internal SRAM memory size[Kbytes]
+// Default: 64
+#define M05X_SRAM_SIZE 4
+#define M05X_SRAM_END (0x20000000 + M05X_SRAM_SIZE * 1024)
+
+void rt_hw_board_init(void);
+
+//#define PRINT_RCC_FREQ_INFO
+
+#endif
+
+// <<< Use Configuration Wizard in Context Menu >>>
diff --git a/bsp/nuvoton_m05x/drivers/led.c b/bsp/nuvoton_m05x/drivers/led.c
new file mode 100644
index 0000000000000000000000000000000000000000..6f2c9d05b13124077f1234e075e5a68922a53115
--- /dev/null
+++ b/bsp/nuvoton_m05x/drivers/led.c
@@ -0,0 +1,47 @@
+/*
+ * File : led.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-11-23 Bright first implementation
+ */
+
+#include "led.h"
+/* RT_USING_COMPONENTS_INIT */
+#ifdef RT_USING_COMPONENTS_INIT
+#include
+#endif
+
+/*
+ LED: P3.6
+*/
+#define LED_PORT P3
+#define LED_DATA(dat) (P36 = dat)
+#define LED_BIT BIT6
+
+/* Initial led gpio pin */
+int rt_hw_led_init(void)
+{
+ /* Configure the GPIO_LED pin */
+ GPIO_SetMode(LED_PORT, LED_BIT, GPIO_PMD_OUTPUT);
+ return 0;
+}
+
+void rt_hw_led_on(void)
+{
+ LED_DATA(0);
+}
+
+void rt_hw_led_off(void)
+{
+ LED_DATA(1);
+}
+
+/* Initial components for device */
+INIT_DEVICE_EXPORT(rt_hw_led_init);
diff --git a/bsp/nuvoton_m05x/drivers/led.h b/bsp/nuvoton_m05x/drivers/led.h
new file mode 100644
index 0000000000000000000000000000000000000000..e6e8858bdc356d4664e1493011e2d75ee31acd21
--- /dev/null
+++ b/bsp/nuvoton_m05x/drivers/led.h
@@ -0,0 +1,25 @@
+/*
+ * File : led.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-11-23 Bright first implementation
+ */
+
+#ifndef __LED_H__
+#define __LED_H__
+
+#include
+#include
+#include "M051Series.h"
+
+void rt_hw_led_on(void);
+void rt_hw_led_off(void);
+
+#endif
diff --git a/bsp/nuvoton_m05x/nuvoton_m05x.ld b/bsp/nuvoton_m05x/nuvoton_m05x.ld
new file mode 100644
index 0000000000000000000000000000000000000000..6070bf4af62cf3bd89ed581949dc4afc16aad8ef
--- /dev/null
+++ b/bsp/nuvoton_m05x/nuvoton_m05x.ld
@@ -0,0 +1,141 @@
+/*
+ * linker script for STM32F0x with GNU ld
+ * bernard.xiong 2009-10-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ CODE (rx) : ORIGIN = 0x08000000, LENGTH = 64k /* 64KB flash */
+ DATA (rw) : ORIGIN = 0x20000000, LENGTH = 8k /* 8K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x100;
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ _etext = .;
+ } > CODE = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > CODE
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >DATA
+
+ .stack :
+ {
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >DATA
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > DATA
+ __bss_end = .;
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/nuvoton_m05x/nuvoton_m05x.sct b/bsp/nuvoton_m05x/nuvoton_m05x.sct
new file mode 100644
index 0000000000000000000000000000000000000000..5fef1e63af82d6d753897717f60ac49719d7f693
--- /dev/null
+++ b/bsp/nuvoton_m05x/nuvoton_m05x.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00010000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00010000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00001000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/nuvoton_m05x/project.uvprojx b/bsp/nuvoton_m05x/project.uvprojx
new file mode 100644
index 0000000000000000000000000000000000000000..67cde697ec229f78e82168de5cec2a3b2961927f
--- /dev/null
+++ b/bsp/nuvoton_m05x/project.uvprojx
@@ -0,0 +1,670 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+
+ (Generic) M051 Series
+ Nuvoton
+ CLOCK(50000000) CPUTYPE("Cortex-M0")
+
+ "Startup\Nuvoton\M051Series\startup_M051Series.s" ("Nuvoton M05X Startup Code")
+
+ 0
+
+
+
+
+
+
+
+
+
+
+ SFD\Nuvoton\M05x_v1.SFR
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\obj\
+ rt-thread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\lst\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ fromelf --bin ".\obj\@L.axf" --output ".\obj\@L.bin"
+ fromelf --text -c ".\obj\@L.axf" --output ".\obj\@L.txt"
+ 0
+ 0
+
+ 1
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DARMCM1.DLL
+
+ SARMCM3.DLL
+
+ TARMCM1.DLL
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
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+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 1
+
+ 0
+ 15
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Bin\Nu_Link.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4107
+
+ 0
+ Bin\Nu_Link.dll
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M0"
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 5
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x1000
+
+
+ 1
+ 0x0
+ 0x10000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x10000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x2000000
+ 0x1000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 0
+ 0
+
+
+ INIT_SYSCLK_AT_BOOTING
+
+ .;..\..\components\drivers\include;..\..\components\init;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;Libraries\CMSIS\Include;Libraries\CMSIS\Nuvoton\M051Series\Include;Libraries\StdDriver\inc;applications;drivers
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+ .\nuvoton_m05x.sct
+
+
+ --keep __rt_init*
+
+
+
+
+
+
+
+ Applications
+
+
+ application.c
+ 1
+ applications\application.c
+
+
+ startup.c
+ 1
+ applications\startup.c
+
+
+
+
+ Drivers
+
+
+ board.c
+ 1
+ drivers\board.c
+
+
+ led.c
+ 1
+ drivers\led.c
+
+
+
+
+ M05X_StdPeriph
+
+
+ system_M051Series.c
+ 1
+ Libraries\CMSIS\Nuvoton\M051Series\Source\system_M051Series.c
+
+
+ acmp.c
+ 1
+ Libraries\StdDriver\src\acmp.c
+
+
+ adc.c
+ 1
+ Libraries\StdDriver\src\adc.c
+
+
+ clk.c
+ 1
+ Libraries\StdDriver\src\clk.c
+
+
+ ebi.c
+ 1
+ Libraries\StdDriver\src\ebi.c
+
+
+ fmc.c
+ 1
+ Libraries\StdDriver\src\fmc.c
+
+
+ gpio.c
+ 1
+ Libraries\StdDriver\src\gpio.c
+
+
+ i2c.c
+ 1
+ Libraries\StdDriver\src\i2c.c
+
+
+ pwm.c
+ 1
+ Libraries\StdDriver\src\pwm.c
+
+
+ retarget.c
+ 1
+ Libraries\StdDriver\src\retarget.c
+
+
+ spi.c
+ 1
+ Libraries\StdDriver\src\spi.c
+
+
+ sys.c
+ 1
+ Libraries\StdDriver\src\sys.c
+
+
+ timer.c
+ 1
+ Libraries\StdDriver\src\timer.c
+
+
+ uart.c
+ 1
+ Libraries\StdDriver\src\uart.c
+
+
+ wdt.c
+ 1
+ Libraries\StdDriver\src\wdt.c
+
+
+ wwdt.c
+ 1
+ Libraries\StdDriver\src\wwdt.c
+
+
+ startup_M051Series.s
+ 2
+ Libraries\CMSIS\Nuvoton\M051Series\Source\ARM\startup_M051Series.s
+
+
+
+
+ Kernel
+
+
+ clock.c
+ 1
+ ..\..\src\clock.c
+
+
+ device.c
+ 1
+ ..\..\src\device.c
+
+
+ idle.c
+ 1
+ ..\..\src\idle.c
+
+
+ ipc.c
+ 1
+ ..\..\src\ipc.c
+
+
+ irq.c
+ 1
+ ..\..\src\irq.c
+
+
+ kservice.c
+ 1
+ ..\..\src\kservice.c
+
+
+ mem.c
+ 1
+ ..\..\src\mem.c
+
+
+ object.c
+ 1
+ ..\..\src\object.c
+
+
+ scheduler.c
+ 1
+ ..\..\src\scheduler.c
+
+
+ thread.c
+ 1
+ ..\..\src\thread.c
+
+
+ src_timer.c
+ 1
+ ..\..\src\timer.c
+
+
+
+
+ CORTEX-M0
+
+
+ cpuport.c
+ 1
+ ..\..\libcpu\arm\cortex-m0\cpuport.c
+
+
+ context_rvds.S
+ 2
+ ..\..\libcpu\arm\cortex-m0\context_rvds.S
+
+
+ backtrace.c
+ 1
+ ..\..\libcpu\arm\common\backtrace.c
+
+
+ div0.c
+ 1
+ ..\..\libcpu\arm\common\div0.c
+
+
+ showmem.c
+ 1
+ ..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ DeviceDrivers
+
+
+ serial.c
+ 1
+ ..\..\components\drivers\serial\serial.c
+
+
+ completion.c
+ 1
+ ..\..\components\drivers\src\completion.c
+
+
+ dataqueue.c
+ 1
+ ..\..\components\drivers\src\dataqueue.c
+
+
+ pipe.c
+ 1
+ ..\..\components\drivers\src\pipe.c
+
+
+ portal.c
+ 1
+ ..\..\components\drivers\src\portal.c
+
+
+ ringbuffer.c
+ 1
+ ..\..\components\drivers\src\ringbuffer.c
+
+
+ workqueue.c
+ 1
+ ..\..\components\drivers\src\workqueue.c
+
+
+
+
+ Components
+
+
+ components.c
+ 1
+ ..\..\components\init\components.c
+
+
+
+
+
+
+
+
diff --git a/bsp/nuvoton_m05x/readme.txt b/bsp/nuvoton_m05x/readme.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e592a1f4cc641036cb4140545bc83d495bec44b2
--- /dev/null
+++ b/bsp/nuvoton_m05x/readme.txt
@@ -0,0 +1,3 @@
+board info:
+Nu-Tiny-SDK
+http://www.nuvoton.com
diff --git a/bsp/nuvoton_m05x/rtconfig.h b/bsp/nuvoton_m05x/rtconfig.h
new file mode 100644
index 0000000000000000000000000000000000000000..a8d3a488113291ad3435e1bf21b1abfdecbeea51
--- /dev/null
+++ b/bsp/nuvoton_m05x/rtconfig.h
@@ -0,0 +1,112 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX 32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND 100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+//#define RT_DEBUG
+//#define RT_DEBUG_INIT 1
+//#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+/* #define RT_USING_HOOK */
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_TIMER_TICK_PER_SECOND 10
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+/* #define RT_USING_MUTEX */
+
+/* Using Event */
+/* #define RT_USING_EVENT */
+
+/* Using MailBox */
+/* #define RT_USING_MAILBOX */
+
+/* Using Message Queue */
+/* #define RT_USING_MESSAGEQUEUE */
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+/* #define RT_USING_MEMPOOL */
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+#define RT_USING_TINY_SIZE
+
+//
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+//
+#define RT_USING_DEVICE_IPC
+//
+#define RT_USING_SERIAL
+
+/* SECTION: Console options */
+//#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+//
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+
+
+
+/* SECTION: finsh, a C-Express shell */
+//#define RT_USING_FINSH
+/* configure finsh parameters */
+#define FINSH_THREAD_PRIORITY 25
+#define FINSH_THREAD_STACK_SIZE 1024
+#define FINSH_HISTORY_LINES 1
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: libc management */
+//#define RT_USING_LIBC
+
+/* SECTION: device filesystem */
+/* #define RT_USING_DFS */
+//#define RT_USING_DFS_ELMFAT
+#define RT_DFS_ELM_WORD_ACCESS
+/* Reentrancy (thread safe) of the FatFs module. */
+#define RT_DFS_ELM_REENTRANT
+/* Number of volumes (logical drives) to be used. */
+#define RT_DFS_ELM_DRIVES 2
+/* #define RT_DFS_ELM_USE_LFN 1 */
+#define RT_DFS_ELM_MAX_LFN 255
+/* Maximum sector size to be handled. */
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+
+#define RT_USING_DFS_ROMFS
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX 2
+/* the max number of opened files */
+#define DFS_FD_MAX 4
+
+#endif
diff --git a/bsp/nuvoton_m05x/rtconfig.py b/bsp/nuvoton_m05x/rtconfig.py
new file mode 100644
index 0000000000000000000000000000000000000000..7ebee5ade069e1cd3a06aca6fe534efbc07ba8b8
--- /dev/null
+++ b/bsp/nuvoton_m05x/rtconfig.py
@@ -0,0 +1,126 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'iar': # not support gcc
+ PLATFORM = 'iar'
+ EXEC_PATH = 'C:/IAR'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = 'C:/Keil'
+elif CROSS_TOOL == 'gcc':
+ print '================ERROR============================'
+ print 'Not support gcc yet!'
+ print '================================================='
+ exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+STM32_TYPE = 'STM32F0XX'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'axf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-nuvoton_m05x.map,-cref,-u,Reset_Handler -T nuvoton_m05x.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread-nuvoton_m05x.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --device DARMSTM'
+ CFLAGS = DEVICE + ' --apcs=interwork'
+ AFLAGS = DEVICE
+ LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-nuvoton_m05x.map --scatter nuvoton_m05x.sct'
+
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ EXEC_PATH += '/ARM/ARMCC/bin'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread-nuvoton_m05x.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --debug'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M0'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=None'
+ CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' -Ol'
+ CFLAGS += ' --use_c++_inline'
+
+ AFLAGS = ''
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M0'
+ AFLAGS += ' --fpu None'
+
+ LFLAGS = ' --config stm32f0xx_flash.icf'
+ LFLAGS += ' --redirect _Printf=_PrintfTiny'
+ LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+ LFLAGS += ' --entry __iar_program_start'
+
+ EXEC_PATH = IAR_PATH + '/arm/bin/'
+ POST_ACTION = ''
diff --git a/bsp/nuvoton_m05x/template.uvprojx b/bsp/nuvoton_m05x/template.uvprojx
new file mode 100644
index 0000000000000000000000000000000000000000..cdd969a1e9da712a85daac059d5b807e46f2a428
--- /dev/null
+++ b/bsp/nuvoton_m05x/template.uvprojx
@@ -0,0 +1,408 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+
+ (Generic) M051 Series
+ Nuvoton
+ IRAM(0x20000000-0x20000FFF) IROM(0-0xFFFF) CLOCK(50000000) CPUTYPE("Cortex-M0")
+
+ "Startup\Nuvoton\M051Series\startup_M051Series.s" ("Nuvoton M05X Startup Code")
+
+ 0
+
+
+
+
+
+
+
+
+
+
+ SFD\Nuvoton\M051AN_v1.SFR
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\
+ rt-thread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ fromelf --bin ".\obj\@L.axf" --output ".\obj\@L.bin"
+ fromelf --text -c ".\obj\@L.axf" --output ".\obj\@L.txt"
+ 0
+ 0
+
+ 1
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DARMCM1.DLL
+
+ SARMCM3.DLL
+
+ TARMCM1.DLL
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
+ 0
+ 1
+
+ 0
+ 15
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Bin\Nu_Link.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4107
+
+ 0
+ Bin\Nu_Link.dll
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
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+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ "Cortex-M0"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 8
+ 1
+ 0
+ 0
+ 3
+ 3
+ 0
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+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
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+
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+ 0x0
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+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x1000
+
+
+ 1
+ 0x0
+ 0x10000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x10000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x2000000
+ 0x1000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
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+
+ 1
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+
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+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+ .\nuvoton_m05x.sct
+
+
+ --map --first='startup_M051Series.o(RESET)' --datacompressor=off --info=inline --entry Reset_Handler
+
+
+
+
+
+
+
+
+