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未验证 提交 817afd27 编写于 作者: B Bernard Xiong 提交者： GitHub
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Merge pull request #4431 from mysterywolf/stm32 

[stm32][driver] auto formatted
上级 38835721 fc04d828
隐藏空白更改
内联 并排
Showing with 461 addition and 461 deletion
bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -27,7 +27,7 @@ extern "C" {
#define UART1_RX_DMA_INSTANCE DMA1_Channel3
#define UART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
#define SPI1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
......
bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -27,7 +27,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -59,7 +59,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -49,7 +49,7 @@ extern "C" {
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -29,7 +29,7 @@ extern "C" {
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
......@@ -45,7 +45,7 @@ extern "C" {
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
}
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
......@@ -61,7 +61,7 @@ extern "C" {
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
}
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
......
bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -27,7 +27,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -59,7 +59,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......@@ -91,7 +91,7 @@ extern "C" {
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -134,7 +134,7 @@ extern "C" {
#endif
/* DMA2 stream3 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
......
bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -27,7 +27,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -61,7 +61,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......@@ -95,7 +95,7 @@ extern "C" {
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -8,7 +8,7 @@
* 2018-10-30 SummerGift first version
* 2019-01-03 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
......@@ -27,7 +27,7 @@ extern "C" {
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
......@@ -74,7 +74,7 @@ extern "C" {
}
#endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
......@@ -109,7 +109,7 @@ extern "C" {
}
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
......@@ -179,7 +179,7 @@ extern "C" {
}
#endif /* UART5_DMA_RX_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
......@@ -214,7 +214,7 @@ extern "C" {
}
#endif /* UART6_DMA_RX_CONFIG */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-22 zylx first version
* 2018-12-22 zylx first version
*/
#ifndef __QSPI_CONFIG_H__
......
bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -27,7 +27,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -61,7 +61,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......@@ -95,7 +95,7 @@ extern "C" {
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
......@@ -129,7 +129,7 @@ extern "C" {
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
......@@ -163,7 +163,7 @@ extern "C" {
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -8,7 +8,7 @@
* 2018-10-30 SummerGift first version
* 2019-01-03 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
......@@ -27,7 +27,7 @@ extern "C" {
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
......@@ -74,7 +74,7 @@ extern "C" {
}
#endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
......@@ -109,7 +109,7 @@ extern "C" {
}
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
......@@ -179,7 +179,7 @@ extern "C" {
}
#endif /* UART5_DMA_RX_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
......@@ -214,7 +214,7 @@ extern "C" {
}
#endif /* UART6_DMA_RX_CONFIG */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
......@@ -249,7 +249,7 @@ extern "C" {
}
#endif /* UART7_DMA_RX_CONFIG */
#endif /* BSP_UART7_RX_USING_DMA */
#if defined(BSP_UART7_TX_USING_DMA)
#ifndef UART7_DMA_TX_CONFIG
#define UART7_DMA_TX_CONFIG \
......@@ -284,7 +284,7 @@ extern "C" {
}
#endif /* UART8_DMA_RX_CONFIG */
#endif /* BSP_UART8_RX_USING_DMA */
#if defined(BSP_UART8_TX_USING_DMA)
#ifndef UART8_DMA_TX_CONFIG
#define UART8_DMA_TX_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-22 zylx first version
* 2018-12-22 zylx first version
*/
#ifndef __QSPI_CONFIG_H__
......
bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -26,7 +26,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -60,7 +60,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......@@ -94,7 +94,7 @@ extern "C" {
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
......@@ -128,7 +128,7 @@ extern "C" {
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
......@@ -162,7 +162,7 @@ extern "C" {
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -8,7 +8,7 @@
* 2018-10-30 SummerGift first version
* 2019-01-05 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
......@@ -19,7 +19,7 @@ extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
......
bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -27,7 +27,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -61,7 +61,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-22 zylx first version
* 2018-12-22 zylx first version
*/
#ifndef __QSPI_CONFIG_H__
......
bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -27,7 +27,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -61,7 +61,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......@@ -95,7 +95,7 @@ extern "C" {
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
......@@ -129,7 +129,7 @@ extern "C" {
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
......@@ -163,7 +163,7 @@ extern "C" {
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -9,7 +9,7 @@
* 2019-01-03 zylx modify dma support
* 2019-10-03 xuzhuoyi modify for STM32G4
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
......@@ -50,7 +50,7 @@ extern "C" {
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
......@@ -97,7 +97,7 @@ extern "C" {
}
#endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
......@@ -132,7 +132,7 @@ extern "C" {
}
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
......@@ -202,7 +202,7 @@ extern "C" {
}
#endif /* UART5_DMA_RX_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/h7/dac_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-22 zylx first version
* 2018-12-22 zylx first version
*/
#ifndef __QSPI_CONFIG_H__
......
bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -26,7 +26,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -60,7 +60,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......@@ -94,7 +94,7 @@ extern "C" {
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
......@@ -128,7 +128,7 @@ extern "C" {
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
......@@ -162,7 +162,7 @@ extern "C" {
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -9,7 +9,7 @@
* 2019-01-05 zylx modify dma support
* 2020-05-02 whj4674672 support stm32h7 uart dma
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
......@@ -20,7 +20,7 @@ extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
......@@ -75,7 +75,7 @@ extern "C" {
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -49,7 +49,7 @@ extern "C" {
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/l1/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -29,7 +29,7 @@ extern "C" {
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
......@@ -45,7 +45,7 @@ extern "C" {
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
}
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
......@@ -61,7 +61,7 @@ extern "C" {
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
}
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
......
bsp/stm32/libraries/HAL_Drivers/config/l1/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l1/pulse_encoder_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l1/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l1/sdio_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l1/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -27,7 +27,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -59,7 +59,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......@@ -91,7 +91,7 @@ extern "C" {
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/l1/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l1/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l1/usbd_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-22 zylx first version
* 2018-12-22 zylx first version
*/
#ifndef __QSPI_CONFIG_H__
......@@ -28,7 +28,7 @@ extern "C" {
}
#endif /* QSPI_BUS_CONFIG */
#endif /* BSP_USING_QSPI */
#ifdef BSP_QSPI_USING_DMA
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -60,7 +60,7 @@ extern "C" {
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_RX_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_DMA_TX_CONFIG
......@@ -146,6 +146,6 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif
#endif
bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/mp1/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/mp1/dac_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -47,7 +47,7 @@ extern "C" {
#define SPI5_RX_DMA_CHANNEL DMA_REQUEST_SPI5_RX
#define SPI5_RX_DMA_IRQ DMA2_Stream0_IRQn
#endif
/* DMA2 stream1 */
#if defined(BSP_UART3_TX_USING_DMA) && !defined(BSP_UART3_TX_USING_INSTANCE)
#define UART3_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
......@@ -78,7 +78,7 @@ extern "C" {
#define UART4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
#define UART4_RX_DMA_INSTANCE DMA2_Stream3
#define UART4_RX_DMA_CHANNEL DMA_REQUEST_UART4_RX
#define UART4_RX_DMA_IRQ DMA2_Stream3_IRQn
#define UART4_RX_DMA_IRQ DMA2_Stream3_IRQn
#endif
/* DMA2 stream4 */
......@@ -87,7 +87,7 @@ extern "C" {
#define UART4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
#define UART4_TX_DMA_INSTANCE DMA2_Stream4
#define UART4_TX_DMA_CHANNEL DMA_REQUEST_UART4_TX
#define UART4_TX_DMA_IRQ DMA2_Stream4_IRQn
#define UART4_TX_DMA_IRQ DMA2_Stream4_IRQn
#endif
/* DMA2 stream5 */
......@@ -105,7 +105,7 @@ extern "C" {
#define CRYP2_IN_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
#define CRYP2_IN_DMA_INSTANCE DMA2_Stream6
#define CRYP2_IN_DMA_CHANNEL DMA_REQUEST_CRYP2_IN
#define CRYP2_IN_DMA_IRQ DMA2_Stream6_IRQn
#define CRYP2_IN_DMA_IRQ DMA2_Stream6_IRQn
#endif
/* DMA2 stream7 */
......@@ -114,9 +114,9 @@ extern "C" {
#define HASH2_IN_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
#define HASH2_IN_DMA_INSTANCE DMA2_Stream7
#define HASH2_IN_DMA_CHANNEL DMA_REQUEST_HASH2_IN
#define HASH2_IN_DMA_IRQ DMA2_Stream7_IRQn
#define HASH2_IN_DMA_IRQ DMA2_Stream7_IRQn
#endif
#ifdef __cplusplus
}
#endif
......
bsp/stm32/libraries/HAL_Drivers/config/mp1/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-22 zylx first version
* 2018-12-22 zylx first version
*/
#ifndef __QSPI_CONFIG_H__
......
bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -26,7 +26,7 @@ extern "C" {
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
......@@ -60,7 +60,7 @@ extern "C" {
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
......@@ -94,7 +94,7 @@ extern "C" {
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
......@@ -128,7 +128,7 @@ extern "C" {
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
......@@ -162,7 +162,7 @@ extern "C" {
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/mp1/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/mp1/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -8,7 +8,7 @@
* 2018-10-30 SummerGift first version
* 2019-01-03 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
......@@ -27,7 +27,7 @@ extern "C" {
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
......@@ -74,7 +74,7 @@ extern "C" {
}
#endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
......@@ -109,7 +109,7 @@ extern "C" {
}
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
......@@ -179,7 +179,7 @@ extern "C" {
}
#endif /* UART5_DMA_RX_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
......@@ -214,7 +214,7 @@ extern "C" {
}
#endif /* UART6_DMA_RX_CONFIG */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/wb/adc_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
......
bsp/stm32/libraries/HAL_Drivers/config/wb/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
......
bsp/stm32/libraries/HAL_Drivers/config/wb/pwm_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
......
bsp/stm32/libraries/HAL_Drivers/config/wb/qspi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
......@@ -28,7 +28,7 @@ extern "C" {
}
#endif /* QSPI_BUS_CONFIG */
#endif /* BSP_USING_QSPI */
#ifdef BSP_QSPI_USING_DMA
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/wb/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
......
bsp/stm32/libraries/HAL_Drivers/config/wb/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
......
bsp/stm32/libraries/HAL_Drivers/config/wb/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
......@@ -60,7 +60,7 @@ extern "C" {
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_RX_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_DMA_TX_CONFIG
......@@ -146,6 +146,6 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif
#endif
bsp/stm32/libraries/HAL_Drivers/config/wb/usbd_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
#ifndef __USBD_CONFIG_H__
......
bsp/stm32/libraries/HAL_Drivers/config/wl/dma_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/wl/spi_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/config/wl/tim_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -33,8 +33,8 @@ extern "C" {
.minfreq = 2000, \
.maxcnt = 0xFFFF, \
.cntmode = HWTIMER_CNTMODE_UP, \
}
#endif
}
#endif
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_TIM2
......@@ -47,7 +47,7 @@ extern "C" {
}
#endif /* TIM2_CONFIG */
#endif /* BSP_USING_TIM2 */
#ifdef BSP_USING_TIM15
#ifndef TIM15_CONFIG
#define TIM15_CONFIG \
......
bsp/stm32/libraries/HAL_Drivers/config/wl/uart_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -50,7 +50,7 @@ extern "C" {
#endif /* UART1_DMA_TX_CONFIG */
#endif /* BSP_UART1_TX_USING_DMA */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
......@@ -72,8 +72,8 @@ extern "C" {
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_RX_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
......@@ -120,9 +120,9 @@ extern "C" {
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif
#endif
bsp/stm32/libraries/HAL_Drivers/drv_adc.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -192,13 +192,13 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
#endif
return -RT_ERROR;
}
#if defined(SOC_SERIES_STM32MP1) || defined (SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
ADC_ChanConf.Rank = ADC_REGULAR_RANK_1;
#else
ADC_ChanConf.Rank = 1;
#endif
#if defined(SOC_SERIES_STM32F0)
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
#elif defined(SOC_SERIES_STM32F1)
......@@ -224,7 +224,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE; /* ADC channel affected to offset number */
ADC_ChanConf.Offset = 0;
ADC_ChanConf.Offset = 0;
ADC_ChanConf.SingleDiff = ADC_SINGLE_ENDED; /* ADC channel differential mode */
#endif
HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
......
bsp/stm32/libraries/HAL_Drivers/drv_can.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -305,8 +305,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
{
drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr;
drv_can->FilterConfig.FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) |
drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) |
(filter_cfg->items[i].rtr << 1)) & 0xFFFF;
drv_can->FilterConfig.FilterMaskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
drv_can->FilterConfig.FilterMaskIdLow = filter_cfg->items[i].mask & 0xFFFF;
......
bsp/stm32/libraries/HAL_Drivers/drv_can.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_common.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_common.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_config.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -8,7 +8,7 @@
* 2018-10-30 SummerGift first version
* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
*/
#ifndef __DRV_CONFIG_H__
#define __DRV_CONFIG_H__
......@@ -43,7 +43,7 @@ extern "C" {
#include "f2/adc_config.h"
#include "f2/tim_config.h"
#include "f2/sdio_config.h"
#include "f2/pwm_config.h"
#include "f2/pwm_config.h"
#elif defined(SOC_SERIES_STM32F4)
#include "f4/dma_config.h"
#include "f4/uart_config.h"
......@@ -114,9 +114,9 @@ extern "C" {
#include "mp1/qspi_config.h"
#include "mp1/spi_config.h"
#include "mp1/adc_config.h"
#include "mp1/dac_config.h"
#include "mp1/dac_config.h"
#include "mp1/tim_config.h"
#include "mp1/pwm_config.h"
#include "mp1/pwm_config.h"
#elif defined(SOC_SERIES_STM32WL)
#include "wl/dma_config.h"
#include "wl/uart_config.h"
......@@ -126,7 +126,7 @@ extern "C" {
#include "wb/adc_config.h"
#include "wb/dma_config.h"
#include "wb/pwm_config.h"
#include "wb/qspi_config.h"
#include "wb/qspi_config.h"
#include "wb/spi_config.h"
#include "wb/tim_config.h"
#include "wb/uart_config.h"
......
bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
浏览文件 @ 817afd27
......@@ -19,7 +19,7 @@
#include "drv_crypto.h"
#include "board.h"
#include "drv_config.h"
struct stm32_hwcrypto_device
{
struct rt_hwcrypto_device dev;
......@@ -148,7 +148,7 @@ static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx)
{
return gen_random ;
}
return 0;
}
......@@ -164,8 +164,8 @@ static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt
rt_uint32_t tickstart = 0;
rt_uint32_t result = RT_EOK;
struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
#if defined(SOC_SERIES_STM32MP1)
HASH_HandleTypeDef *HW_TypeDef = (HASH_HandleTypeDef *)(ctx->parent.contex);
/* Start HASH computation using DMA transfer */
......@@ -191,7 +191,7 @@ static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt
{
goto _exit;
}
/* Wait for DMA transfer to complete */
/* Wait for DMA transfer to complete */
tickstart = rt_tick_get();
while (HAL_HASH_GetState(HW_TypeDef) == HAL_HASH_STATE_BUSY)
{
......@@ -201,11 +201,11 @@ static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt
goto _exit;
}
}
#endif
_exit:
rt_mutex_release(&stm32_hw_dev->mutex);
return result;
}
......@@ -243,12 +243,12 @@ static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size
{
goto _exit;
}
#endif
#endif
_exit:
rt_mutex_release(&stm32_hw_dev->mutex);
return result;
return result;
}
static const struct hwcrypto_hash_ops hash_ops =
......@@ -259,7 +259,7 @@ static const struct hwcrypto_hash_ops hash_ops =
#endif /* BSP_USING_HASH */
#if defined(BSP_USING_CRYP)
#if defined(BSP_USING_CRYP)
static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
struct hwcrypto_symmetric_info *info)
{
......@@ -268,10 +268,10 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
#if defined(SOC_SERIES_STM32MP1)
CRYP_HandleTypeDef *HW_TypeDef = (CRYP_HandleTypeDef *)(ctx->parent.contex);
switch (ctx->parent.type)
{
case HWCRYPTO_TYPE_AES_ECB:
......@@ -287,25 +287,25 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
break;
case HWCRYPTO_TYPE_DES_ECB:
HW_TypeDef->Init.Algorithm = CRYP_DES_ECB;
HW_TypeDef->Init.Algorithm = CRYP_DES_ECB;
break;
case HWCRYPTO_TYPE_DES_CBC:
HW_TypeDef->Init.Algorithm = CRYP_DES_CBC;
HW_TypeDef->Init.Algorithm = CRYP_DES_CBC;
break;
default :
rt_kprintf("not support cryp type: %x", ctx->parent.type);
break;
break;
}
HAL_CRYP_DeInit(HW_TypeDef);
HW_TypeDef->Init.DataType = CRYP_DATATYPE_8B;
HW_TypeDef->Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_BYTE;
HW_TypeDef->Init.KeySize = CRYP_KEYSIZE_128B;
HW_TypeDef->Init.pKey = (uint32_t*)ctx->key;
result = HAL_CRYP_Init(HW_TypeDef);
if (result != HAL_OK)
{
......@@ -314,11 +314,11 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
}
if (info->mode == HWCRYPTO_MODE_ENCRYPT)
{
result = HAL_CRYP_Encrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out);
result = HAL_CRYP_Encrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out);
}
else if (info->mode == HWCRYPTO_MODE_DECRYPT)
{
result = HAL_CRYP_Decrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out);
result = HAL_CRYP_Decrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out);
}
else
{
......@@ -326,7 +326,7 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
result = RT_ERROR;
goto _exit;
}
if (result != HAL_OK)
{
goto _exit;
......@@ -334,28 +334,28 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
tickstart = rt_tick_get();
while (HAL_CRYP_GetState(HW_TypeDef) != HAL_CRYP_STATE_READY)
{
{
if (rt_tick_get() - tickstart > 0xFFFF)
{
result = RT_ETIMEOUT;
goto _exit;
}
}
#endif
if (result != HAL_OK)
{
goto _exit;
}
_exit:
rt_mutex_release(&stm32_hw_dev->mutex);
return result;
return result;
}
static const struct hwcrypto_symmetric_ops cryp_ops =
static const struct hwcrypto_symmetric_ops cryp_ops =
{
.crypt = _cryp_crypt
};
......@@ -364,7 +364,7 @@ static const struct hwcrypto_symmetric_ops cryp_ops =
static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
{
rt_err_t res = RT_EOK;
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_RNG)
......@@ -417,11 +417,11 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
#endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */
ctx->contex = hcrc;
((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
break;
}
#endif /* BSP_USING_CRC */
#if defined(BSP_USING_HASH)
case HWCRYPTO_TYPE_MD5:
case HWCRYPTO_TYPE_SHA1:
......@@ -437,18 +437,18 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
/* enable dma for hash */
__HAL_RCC_DMA2_CLK_ENABLE();
HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
hash->Init.DataType = HASH_DATATYPE_8B;
if (HAL_HASH_Init(hash) != HAL_OK)
{
res = -RT_ERROR;
}
}
#endif
ctx->contex = hash;
((struct hwcrypto_hash *)ctx)->ops = &hash_ops;
break;
break;
}
#endif /* BSP_USING_HASH */
......@@ -480,14 +480,14 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
{
res = -RT_ERROR;
}
#endif
#endif
ctx->contex = cryp;
((struct hwcrypto_symmetric *)ctx)->ops = &cryp_ops;
break;
break;
}
#endif /* BSP_USING_CRYP */
default:
res = -RT_ERROR;
break;
......@@ -506,11 +506,11 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
__HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);
__HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);
HAL_CRC_DeInit((CRC_HandleTypeDef *)(ctx->contex));
break;
#endif /* BSP_USING_CRC */
#if defined(BSP_USING_HASH)
case HWCRYPTO_TYPE_MD5:
case HWCRYPTO_TYPE_SHA1:
......@@ -529,7 +529,7 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
HAL_CRYP_DeInit((CRYP_HandleTypeDef *)(ctx->contex));
break;
#endif /* BSP_USING_CRYP */
default:
break;
}
......@@ -548,7 +548,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
if (des->contex && src->contex)
{
rt_memcpy(des->contex, src->contex, sizeof(RNG_HandleTypeDef));
}
}
break;
#endif /* BSP_USING_RNG */
......@@ -560,7 +560,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
}
break;
#endif /* BSP_USING_CRC */
#if defined(BSP_USING_HASH)
case HWCRYPTO_TYPE_MD5:
case HWCRYPTO_TYPE_SHA1:
......@@ -568,7 +568,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
if (des->contex && src->contex)
{
rt_memcpy(des->contex, src->contex, sizeof(HASH_HandleTypeDef));
}
}
break;
#endif /* BSP_USING_HASH */
......@@ -577,14 +577,14 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
case HWCRYPTO_TYPE_DES:
case HWCRYPTO_TYPE_3DES:
case HWCRYPTO_TYPE_RC4:
case HWCRYPTO_TYPE_GCM:
case HWCRYPTO_TYPE_GCM:
if (des->contex && src->contex)
{
rt_memcpy(des->contex, src->contex, sizeof(CRYP_HandleTypeDef));
}
}
break;
#endif /* BSP_USING_CRYP */
default:
res = -RT_ERROR;
break;
......@@ -606,7 +606,7 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
__HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);
break;
#endif /* BSP_USING_CRC */
#if defined(BSP_USING_HASH)
case HWCRYPTO_TYPE_MD5:
case HWCRYPTO_TYPE_SHA1:
......@@ -614,16 +614,16 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
__HAL_HASH_RESET_HANDLE_STATE((HASH_HandleTypeDef *)(ctx->contex));
break;
#endif /* BSP_USING_HASH*/
#if defined(BSP_USING_CRYP)
case HWCRYPTO_TYPE_AES:
case HWCRYPTO_TYPE_DES:
case HWCRYPTO_TYPE_3DES:
case HWCRYPTO_TYPE_RC4:
case HWCRYPTO_TYPE_GCM:
case HWCRYPTO_TYPE_GCM:
break;
#endif /* BSP_USING_CRYP */
default:
break;
}
......@@ -636,9 +636,9 @@ void HASH2_DMA_IN_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&hdma_hash_in);
/* leave interrupt */
rt_interrupt_leave();
}
......@@ -646,14 +646,14 @@ void HASH2_DMA_IN_IRQHandler(void)
#if defined(CRYP2_IN_DMA_INSTANCE)
void CRYP2_DMA_IN_IRQHandler(void)
{
{
extern DMA_HandleTypeDef hdma_cryp_in;
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&hdma_cryp_in);
/* leave interrupt */
rt_interrupt_leave();
}
......@@ -663,12 +663,12 @@ void CRYP2_DMA_IN_IRQHandler(void)
void CRYP2_DMA_OUT_IRQHandler(void)
{
extern DMA_HandleTypeDef hdma_cryp_out;
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&hdma_cryp_out);
/* leave interrupt */
rt_interrupt_leave();
}
......@@ -690,7 +690,7 @@ int stm32_hw_crypto_device_init(void)
_crypto_dev.dev.ops = &_ops;
#if defined(BSP_USING_UDID)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
cpuid[0] = HAL_GetUIDw0();
cpuid[1] = HAL_GetUIDw1();
#elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
......
bsp/stm32/libraries/HAL_Drivers/drv_dac.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -11,7 +11,7 @@
#include <board.h>
#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
#include "drv_config.h"
//#define DRV_DEBUG
......@@ -23,7 +23,7 @@ static DAC_HandleTypeDef dac_config[] =
#ifdef BSP_USING_DAC1
DAC1_CONFIG,
#endif
#ifdef BSP_USING_DAC2
DAC2_CONFIG,
#endif
......@@ -72,12 +72,12 @@ static rt_err_t stm32_dac_enabled(struct rt_dac_device *device, rt_uint32_t chan
}
else
{
LOG_E("dac channel must be 1 or 2.");
LOG_E("dac channel must be 1 or 2.");
return -RT_ERROR;
}
HAL_DAC_Start(stm32_dac_handler, dac_channel);
#endif
return RT_EOK;
}
......@@ -87,7 +87,7 @@ static rt_err_t stm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t cha
DAC_HandleTypeDef *stm32_dac_handler;
RT_ASSERT(device != RT_NULL);
stm32_dac_handler = device->parent.user_data;
#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
if ((channel <= 2) && (channel > 0))
{
......@@ -96,28 +96,28 @@ static rt_err_t stm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t cha
}
else
{
LOG_E("dac channel must be 1 or 2.");
LOG_E("dac channel must be 1 or 2.");
return -RT_ERROR;
}
HAL_DAC_Stop(stm32_dac_handler, dac_channel);
#endif
return RT_EOK;
}
static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
uint32_t dac_channel;
DAC_ChannelConfTypeDef DAC_ChanConf;
DAC_ChannelConfTypeDef DAC_ChanConf;
DAC_HandleTypeDef *stm32_dac_handler;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
stm32_dac_handler = device->parent.user_data;
rt_memset(&DAC_ChanConf, 0, sizeof(DAC_ChanConf));
#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
if ((channel <= 2) && (channel > 0))
{
......@@ -126,15 +126,15 @@ static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t ch
}
else
{
LOG_E("dac channel must be 1 or 2.");
LOG_E("dac channel must be 1 or 2.");
return -RT_ERROR;
}
#endif
#endif
#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
DAC_ChanConf.DAC_Trigger = DAC_TRIGGER_NONE;
DAC_ChanConf.DAC_Trigger = DAC_TRIGGER_NONE;
DAC_ChanConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
#endif
#endif
/* config dac out channel*/
if (HAL_DAC_ConfigChannel(stm32_dac_handler, &DAC_ChanConf, dac_channel) != HAL_OK)
{
......@@ -153,7 +153,7 @@ static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t ch
LOG_D("Start dac Error!\n");
return -RT_ERROR;
}
return RT_EOK;
}
......
bsp/stm32/libraries/HAL_Drivers/drv_dma.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -20,10 +20,10 @@ extern "C" {
#endif
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */
......
bsp/stm32/libraries/HAL_Drivers/drv_eth.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_eth.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -155,7 +155,7 @@ int stm32_flash_erase_bank(uint32_t bank, rt_uint32_t addr, size_t size)
EraseInitStruct.PageAddress = GetPage(addr);
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
EraseInitStruct.Banks = bank;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
{
result = -RT_ERROR;
......@@ -186,8 +186,8 @@ __exit:
*/
int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
#if defined(FLASH_BANK2_END)
rt_err_t result = RT_EOK;
#if defined(FLASH_BANK2_END)
rt_err_t result = RT_EOK;
rt_uint32_t addr_bank1 = 0;
rt_uint32_t size_bank1 = 0;
rt_uint32_t addr_bank2 = 0;
......@@ -203,7 +203,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
size_bank1 = 0;
addr_bank2 = addr;
size_bank2 = size;
size_bank2 = size;
}
else
{
......@@ -222,7 +222,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
goto __exit;
}
}
if(size_bank2)
{
LOG_D("bank2: addr (0x%p), size %d", (void *)addr_bank2, size_bank2);
......@@ -233,12 +233,12 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
}
}
__exit:
__exit:
if(result != RT_EOK)
{
return result;
}
return size_bank1 + size_bank2;
#else
return stm32_flash_erase_bank(FLASH_BANK_1, addr, size);
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -43,7 +43,7 @@
static rt_uint32_t GetSector(rt_uint32_t Address)
{
uint32_t sector = 0;
#if defined (FLASH_OPTCR_nDBANK)
FLASH_OBProgramInitTypeDef OBInit;
uint32_t nbank = 0;
......@@ -53,7 +53,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
nbank = ((OBInit.USERConfig & 0x20000000U) >> 29);
//1:single bank mode
if (1 == nbank)
{
{
if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
{
sector = FLASH_SECTOR_0;
......@@ -98,7 +98,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
{
sector = FLASH_SECTOR_10;
}
else
else
{
sector = FLASH_SECTOR_11;
}
......@@ -153,7 +153,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
{
sector = FLASH_SECTOR_10;
}
else
else
{
sector = FLASH_SECTOR_11;
}
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -60,7 +60,7 @@ static void GetSector(rt_uint32_t Address,uint32_t* bank,uint32_t* sector)
nbank = ((OBInit.USERConfig & 0x20000000U) >> 29);
/* 1:single bank mode */
if (1 == nbank)
{
{
if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
{
sector = FLASH_SECTOR_0;
......@@ -105,7 +105,7 @@ static void GetSector(rt_uint32_t Address,uint32_t* bank,uint32_t* sector)
{
sector = FLASH_SECTOR_10;
}
else
else
{
sector = FLASH_SECTOR_11;
}
......@@ -115,7 +115,7 @@ static void GetSector(rt_uint32_t Address,uint32_t* bank,uint32_t* sector)
LOG_E("rtthread doesn't support duel bank mode yet!");
RT_ASSERT(0);
}
#else /* no dual bank ability */
#else /* no dual bank ability */
*sector = (Address&0xffffff)/FLASH_SIZE_GRANULARITY_128K;
if(*sector>7)
{
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_wb.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2020-10-14 Dozingfiretruck first version
*/
......@@ -183,7 +183,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
/* Fill EraseInit structure*/
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
EraseInitStruct.Page = GetPage(addr);
EraseInitStruct.Page = GetPage(addr);
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
......
bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_gpio.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -7,7 +7,7 @@
* Date Author Notes
* 2018-11-06 balanceTWK first version
* 2020-06-16 thread-liu add stm32mp1
* 2020-09-01 thread-liu add GPIOZ
* 2020-09-01 thread-liu add GPIOZ
* 2020-09-18 geniusgogo optimization design pin-index algorithm
*/
......
bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -175,10 +175,10 @@ static void pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_dou
}
if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
{
*pclk2_doubler = 2;
*pclk2_doubler = 2;
}
#else
if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
{
*pclk1_doubler = 2;
}
......@@ -288,7 +288,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_
{
tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
}
/* start timer */
if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
{
......@@ -344,7 +344,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
#elif defined(SOC_SERIES_STM32WB)
if (tim->Instance == TIM16 || tim->Instance == TIM17)
#elif defined(SOC_SERIES_STM32MP1)
if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
if (0)
#endif
......@@ -458,7 +458,7 @@ void TIM8_UP_TIM13_IRQHandler(void)
#ifdef BSP_USING_TIM14
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
void TIM8_TRG_COM_TIM14_IRQHandler(void)
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
void TIM14_IRQHandler(void)
#endif
{
......@@ -480,9 +480,9 @@ void TIM1_BRK_TIM15_IRQHandler(void)
}
#endif
#ifdef BSP_USING_TIM16
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
void TIM1_UP_TIM16_IRQHandler(void)
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
void TIM16_IRQHandler(void)
#endif
{
......@@ -494,9 +494,9 @@ void TIM1_BRK_TIM15_IRQHandler(void)
}
#endif
#ifdef BSP_USING_TIM17
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
void TIM1_TRG_COM_TIM17_IRQHandler(void)
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
void TIM17_IRQHandler(void)
#endif
{
......
bsp/stm32/libraries/HAL_Drivers/drv_lcd.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -258,7 +258,7 @@ void turn_on_lcd_backlight(void)
#else
void turn_on_lcd_backlight(void)
{
}
#endif
......
bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -7,7 +7,7 @@
* Date Author Notes
* 2019-05-23 WillianChan first version
*/
#include <board.h>
#ifdef BSP_USING_LCD_MIPI
......@@ -23,7 +23,7 @@ struct stm32_lcd
struct rt_device parent;
struct rt_device_graphic_info info;
};
static struct stm32_lcd lcd;
static struct stm32_lcd lcd;
extern void stm32_mipi_lcd_init(void);
extern void stm32_mipi_lcd_config(rt_uint32_t pixel_format);
......@@ -32,14 +32,14 @@ extern void stm32_mipi_display_off(void);
rt_err_t ltdc_init(void)
{
uint32_t lcd_clock = 27429;
uint32_t lcd_clock = 27429;
uint32_t lanebyte_clock = 62500;
uint32_t HSA = LCD_HSYNC, HFP = LCD_HFP, HBP = LCD_HBP, HACT = LCD_WIDTH;
uint32_t VSA = LCD_VSYNC, VFP = LCD_VFP, VBP = LCD_VBP, VACT = LCD_HEIGHT;
stm32_mipi_lcd_init();
__HAL_RCC_LTDC_CLK_ENABLE();
__HAL_RCC_LTDC_FORCE_RESET();
__HAL_RCC_LTDC_RELEASE_RESET();
......@@ -47,92 +47,92 @@ rt_err_t ltdc_init(void)
__HAL_RCC_DSI_CLK_ENABLE();
__HAL_RCC_DSI_FORCE_RESET();
__HAL_RCC_DSI_RELEASE_RESET();
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
PeriphClkInitStruct.PLLSAI.PLLSAIR = 7;
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
HAL_NVIC_SetPriority(LTDC_IRQn, 3, 0);
HAL_NVIC_SetPriority(DSI_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(LTDC_IRQn);
HAL_NVIC_EnableIRQ(DSI_IRQn);
DSI_PLLInitTypeDef dsi_pll;
hdsi.Instance = DSI;
hdsi.Instance = DSI;
hdsi.Init.NumberOfLanes = DSI_TWO_DATA_LANES;
hdsi.Init.TXEscapeCkdiv = lanebyte_clock / 15620;
dsi_pll.PLLNDIV = 125;
dsi_pll.PLLIDF = DSI_PLL_IN_DIV2;
dsi_pll.PLLODF = DSI_PLL_OUT_DIV1;
dsi_pll.PLLODF = DSI_PLL_OUT_DIV1;
HAL_DSI_DeInit(&hdsi);
HAL_DSI_Init(&hdsi, &dsi_pll);
HAL_DSI_Init(&hdsi, &dsi_pll);
hdsi_video.VirtualChannelID = 0;
hdsi_video.ColorCoding = DSI_RGB888;
hdsi_video.VSPolarity = DSI_VSYNC_ACTIVE_HIGH;
hdsi_video.HSPolarity = DSI_HSYNC_ACTIVE_HIGH;
hdsi_video.DEPolarity = DSI_DATA_ENABLE_ACTIVE_HIGH;
hdsi_video.Mode = DSI_VID_MODE_BURST;
hdsi_video.Mode = DSI_VID_MODE_BURST;
hdsi_video.NullPacketSize = 0xFFF;
hdsi_video.NumberOfChunks = 0;
hdsi_video.PacketSize = HACT;
hdsi_video.PacketSize = HACT;
hdsi_video.HorizontalSyncActive = (HSA * lanebyte_clock) / lcd_clock;
hdsi_video.HorizontalBackPorch = (HBP * lanebyte_clock) / lcd_clock;
hdsi_video.HorizontalLine = ((HACT + HSA + HBP + HFP) * lanebyte_clock) / lcd_clock;
hdsi_video.HorizontalLine = ((HACT + HSA + HBP + HFP) * lanebyte_clock) / lcd_clock;
hdsi_video.VerticalSyncActive = VSA;
hdsi_video.VerticalBackPorch = VBP;
hdsi_video.VerticalFrontPorch = VFP;
hdsi_video.VerticalActive = VACT;
hdsi_video.LPCommandEnable = DSI_LP_COMMAND_ENABLE;
hdsi_video.VerticalActive = VACT;
hdsi_video.LPCommandEnable = DSI_LP_COMMAND_ENABLE;
hdsi_video.LPLargestPacketSize = 16;
hdsi_video.LPVACTLargestPacketSize = 0;
hdsi_video.LPHorizontalFrontPorchEnable = DSI_LP_HFP_ENABLE;
hdsi_video.LPHorizontalBackPorchEnable = DSI_LP_HBP_ENABLE;
hdsi_video.LPVerticalActiveEnable = DSI_LP_VACT_ENABLE;
hdsi_video.LPVerticalFrontPorchEnable = DSI_LP_VFP_ENABLE;
hdsi_video.LPVerticalBackPorchEnable = DSI_LP_VBP_ENABLE;
hdsi_video.LPVerticalSyncActiveEnable = DSI_LP_VSYNC_ENABLE;
HAL_DSI_ConfigVideoMode(&hdsi, &hdsi_video);
hdsi_video.LPHorizontalFrontPorchEnable = DSI_LP_HFP_ENABLE;
hdsi_video.LPHorizontalBackPorchEnable = DSI_LP_HBP_ENABLE;
hdsi_video.LPVerticalActiveEnable = DSI_LP_VACT_ENABLE;
hdsi_video.LPVerticalFrontPorchEnable = DSI_LP_VFP_ENABLE;
hdsi_video.LPVerticalBackPorchEnable = DSI_LP_VBP_ENABLE;
hdsi_video.LPVerticalSyncActiveEnable = DSI_LP_VSYNC_ENABLE;
HAL_DSI_ConfigVideoMode(&hdsi, &hdsi_video);
DSI_PHY_TimerTypeDef dsi_phy;
dsi_phy.ClockLaneHS2LPTime = 35;
dsi_phy.ClockLaneLP2HSTime = 35;
dsi_phy.DataLaneHS2LPTime = 35;
dsi_phy.DataLaneLP2HSTime = 35;
dsi_phy.DataLaneMaxReadTime = 0;
dsi_phy.StopWaitTime = 10;
HAL_DSI_ConfigPhyTimer(&hdsi, &dsi_phy);
HAL_DSI_ConfigPhyTimer(&hdsi, &dsi_phy);
hltdc.Instance = LTDC;
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
hltdc.Init.HorizontalSync = (HSA - 1);
hltdc.Init.AccumulatedHBP = (HSA + HBP - 1);
hltdc.Init.AccumulatedActiveW = (LCD_WIDTH + HSA + HBP - 1);
hltdc.Init.TotalWidth = (LCD_WIDTH + HSA + HBP + HFP - 1);
hltdc.LayerCfg->ImageWidth = LCD_WIDTH;
hltdc.LayerCfg->ImageHeight = LCD_HEIGHT;
hltdc.LayerCfg->ImageHeight = LCD_HEIGHT;
hltdc.Init.Backcolor.Blue = 0x00;
hltdc.Init.Backcolor.Green = 0x00;
hltdc.Init.Backcolor.Red = 0x00;
HAL_LTDCEx_StructInitFromVideoConfig(&hltdc, &(hdsi_video));
HAL_LTDCEx_StructInitFromVideoConfig(&hltdc, &(hdsi_video));
HAL_LTDC_Init(&(hltdc));
HAL_DSI_Start(&(hdsi));
HAL_DSI_Start(&(hdsi));
stm32_mipi_lcd_config(RTGRAPHIC_PIXEL_FORMAT_ARGB888);
return RT_EOK;
return RT_EOK;
}
void ltdc_layer_init(uint16_t index, uint32_t framebuffer)
......@@ -140,7 +140,7 @@ void ltdc_layer_init(uint16_t index, uint32_t framebuffer)
LTDC_LayerCfgTypeDef layer_cfg;
layer_cfg.WindowX0 = 0;
layer_cfg.WindowX1 = LCD_WIDTH;
layer_cfg.WindowX1 = LCD_WIDTH;
layer_cfg.WindowY0 = 0;
layer_cfg.WindowY1 = LCD_HEIGHT;
layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
......@@ -161,7 +161,7 @@ void ltdc_layer_init(uint16_t index, uint32_t framebuffer)
void LTDC_IRQHandler(void)
{
rt_interrupt_enter();
HAL_LTDC_IRQHandler(&hltdc);
HAL_LTDC_IRQHandler(&hltdc);
rt_interrupt_leave();
}
......@@ -171,11 +171,11 @@ static rt_err_t stm32_lcd_init(rt_device_t device)
lcd.info.height = LCD_HEIGHT;
lcd.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888;
lcd.info.bits_per_pixel = 32;
lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32);
lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32);
memset(lcd.info.framebuffer, 0, LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8));
ltdc_init();
ltdc_layer_init(0, (uint32_t)lcd.info.framebuffer);
ltdc_layer_init(0, (uint32_t)lcd.info.framebuffer);
return RT_EOK;
}
......@@ -186,12 +186,12 @@ static rt_err_t stm32_lcd_control(rt_device_t device, int cmd, void *args)
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
stm32_mipi_display_on();
case RTGRAPHIC_CTRL_POWERON:
stm32_mipi_display_on();
break;
case RTGRAPHIC_CTRL_POWEROFF:
stm32_mipi_display_off();
case RTGRAPHIC_CTRL_POWEROFF:
stm32_mipi_display_off();
break;
case RTGRAPHIC_CTRL_GET_INFO:
......@@ -210,9 +210,9 @@ static rt_err_t stm32_lcd_control(rt_device_t device, int cmd, void *args)
int rt_hw_lcd_init(void)
{
rt_err_t ret;
rt_memset(&lcd, 0x00, sizeof(lcd));
rt_err_t ret;
rt_memset(&lcd, 0x00, sizeof(lcd));
lcd.parent.type = RT_Device_Class_Graphic;
lcd.parent.init = stm32_lcd_init;
......
bsp/stm32/libraries/HAL_Drivers/drv_log.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_lptim.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_lptim.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_pm.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -285,9 +285,9 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
rt_uint32_t pclk1_doubler, pclk2_doubler;
/* Converts the channel number to the channel number of Hal library */
rt_uint32_t channel = 0x04 * (configuration->channel - 1);
pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)
......
bsp/stm32/libraries/HAL_Drivers/drv_qspi.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -108,7 +108,7 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
{
__HAL_RCC_DMA2_CLK_ENABLE();
}
HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG;
qspi_bus->hdma_quadspi = hdma_quadspi_config;
......
bsp/stm32/libraries/HAL_Drivers/drv_qspi.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -7,7 +7,7 @@
* Date Author Notes
* 2018-11-27 zylx first version
*/
#ifndef __DRV_QSPI_H__
#define __DRV_QSPI_H__
......
bsp/stm32/libraries/HAL_Drivers/drv_rtc.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_sdio.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_sdio.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_sdram.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -207,10 +207,10 @@ int rt_hw_i2c_init(void)
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
RT_ASSERT(result == RT_EOK);
stm32_i2c_bus_unlock(&soft_i2c_config[i]);
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].sda);
}
......
bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -37,7 +37,7 @@ struct stm32_i2c
.bus_name = "i2c1", \
}
#endif
#ifdef BSP_USING_I2C2
#define I2C2_BUS_CONFIG \
{ \
......@@ -46,7 +46,7 @@ struct stm32_i2c
.bus_name = "i2c2", \
}
#endif
#ifdef BSP_USING_I2C3
#define I2C3_BUS_CONFIG \
{ \
......@@ -55,7 +55,7 @@ struct stm32_i2c
.bus_name = "i2c3", \
}
#endif
#ifdef BSP_USING_I2C4
#define I2C4_BUS_CONFIG \
{ \
......
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -317,7 +317,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
already_send_length = message->length - send_length - message_length;
send_buf = (rt_uint8_t *)message->send_buf + already_send_length;
recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
/* start once data exchange in DMA mode */
if (message->send_buf && message->recv_buf)
{
......@@ -447,8 +447,8 @@ static int rt_hw_spi_bus_init(void)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
#elif defined(SOC_SERIES_STM32MP1)
__HAL_RCC_DMAMUX_CLK_ENABLE();
#elif defined(SOC_SERIES_STM32MP1)
__HAL_RCC_DMAMUX_CLK_ENABLE();
SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc);
#endif
......@@ -490,7 +490,7 @@ static int rt_hw_spi_bus_init(void)
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
#elif defined(SOC_SERIES_STM32MP1)
__HAL_RCC_DMAMUX_CLK_ENABLE();
__HAL_RCC_DMAMUX_CLK_ENABLE();
SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc);
tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc);
#endif
......@@ -900,23 +900,23 @@ static void stm32_get_dma_info(void)
}
#if defined(SOC_SERIES_STM32F0)
void SPI1_DMA_RX_TX_IRQHandler(void)
void SPI1_DMA_RX_TX_IRQHandler(void)
{
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
SPI1_DMA_TX_IRQHandler();
#endif
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
SPI1_DMA_RX_IRQHandler();
#endif
}
void SPI2_DMA_RX_TX_IRQHandler(void)
void SPI2_DMA_RX_TX_IRQHandler(void)
{
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
SPI2_DMA_TX_IRQHandler();
#endif
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
SPI2_DMA_RX_IRQHandler();
#endif
......
bsp/stm32/libraries/HAL_Drivers/drv_spi.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -62,7 +62,7 @@ struct stm32_spi
DMA_HandleTypeDef handle_rx;
DMA_HandleTypeDef handle_tx;
} dma;
rt_uint8_t spi_dma_flag;
struct rt_spi_bus spi_bus;
};
......
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -9,7 +9,7 @@
* 2020-03-16 SummerGift add device close feature
* 2020-03-20 SummerGift fix bug caused by ORE
* 2020-05-02 whj4674672 support stm32h7 uart dma
* 2020-09-09 forest-rain support stm32wl uart
* 2020-09-09 forest-rain support stm32wl uart
* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
*/
......@@ -216,7 +216,7 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
HAL_NVIC_EnableIRQ(uart->config->irq_type);
/* enable interrupt */
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
......@@ -874,7 +874,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|| defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32MP1)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
......@@ -883,7 +883,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
/* enable DMAMUX clock for L4+ and G4 */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
__HAL_RCC_DMAMUX1_CLK_ENABLE();
#elif defined(SOC_SERIES_STM32MP1)
__HAL_RCC_DMAMUX_CLK_ENABLE();
#endif
......@@ -1032,7 +1032,7 @@ static void _dma_tx_complete(struct rt_serial_device *serial)
/**
* @brief HAL_UART_TxCpltCallback
* @param huart: UART handle
* @note This callback can be called by two functions, first in UART_EndTransmit_IT when
* @note This callback can be called by two functions, first in UART_EndTransmit_IT when
* UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
* @retval None
*/
......
bsp/stm32/libraries/HAL_Drivers/drv_usart.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_usbd.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_usbh.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_usbh.h
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
浏览文件 @ 817afd27
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
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