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体验新版 GitCode,发现更多精彩内容 >>
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7515fb9d
编写于
12月 11, 2017
作者:
B
Bernard Xiong
浏览文件
操作
浏览文件
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差异文件
[lwIP] merge net/Kconfig
上级
b6fef984
2e0c91a9
变更
11
隐藏空白更改
内联
并排
Showing
11 changed file
with
26 addition
and
1009 deletion
+26
-1009
bsp/imxrt1052-evk/imxrt1052_sdram.icf
bsp/imxrt1052-evk/imxrt1052_sdram.icf
+0
-103
bsp/imxrt1052-evk/imxrt1052_sdram.sct
bsp/imxrt1052-evk/imxrt1052_sdram.sct
+0
-99
bsp/imxrt1052-evk/rtconfig.py
bsp/imxrt1052-evk/rtconfig.py
+2
-2
bsp/imxrt1052-evk/sdram_init.jlinkscript
bsp/imxrt1052-evk/sdram_init.jlinkscript
+0
-311
bsp/imxrt1052-evk/sdram_mpu_init.ini
bsp/imxrt1052-evk/sdram_mpu_init.ini
+0
-236
bsp/imxrt1052-evk/sdram_mpu_init.mac
bsp/imxrt1052-evk/sdram_mpu_init.mac
+0
-249
components/drivers/spi/SConscript
components/drivers/spi/SConscript
+7
-1
components/drivers/spi/spi_flash_sfud.c
components/drivers/spi/spi_flash_sfud.c
+3
-8
components/net/Kconfig
components/net/Kconfig
+4
-0
components/net/lwip-1.4.1/src/lwipopts.h
components/net/lwip-1.4.1/src/lwipopts.h
+5
-0
components/net/lwip-2.0.2/src/lwipopts.h
components/net/lwip-2.0.2/src/lwipopts.h
+5
-0
未找到文件。
bsp/imxrt1052-evk/imxrt1052_sdram.icf
已删除
100644 → 0
浏览文件 @
b6fef984
/*
** ###################################################################
** Processor: MIMXRT1052DVL6A
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: i.MX 6RT for ROM
** Version: rev. 0.1, 2017-01-10
** Build: b170608
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_base_addr = 0x00000000;
define symbol m_interrupts_start = 0x00000000 + m_base_addr;
define symbol m_interrupts_end = 0x000003FF + m_base_addr;
define symbol m_text_start = 0x00000400 + m_base_addr;
define symbol m_text_end = 0x0007FFFF + m_base_addr;
define symbol m_data_start = 0x80000000;
define symbol m_data_end = 0x81DFFFFF;
define symbol m_ncache_start = 0x81E00000;
define symbol m_ncache_end = 0x81FFFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* };
define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly, block RTT_INIT_FUNC };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };
place in NCACHE_region { block NCACHE_VAR };
bsp/imxrt1052-evk/imxrt1052_sdram.sct
已删除
100644 → 0
浏览文件 @
b6fef984
#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVL5A
** MIMXRT1052DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_start_address 0x00000000
#define m_interrupts_start (0x00000000 + m_start_address)
#define m_interrupts_size 0x00000400
#define m_text_start (m_interrupts_start + m_interrupts_size)
#define m_text_size 0x0001FC00
#define m_data_start 0x80000000
#define m_data_size 0x01E00000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_text_start m_text_size { ; load region size_region
ER_m_text m_text_start m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
}
LR_m_interrupts m_interrupts_start m_interrupts_size {
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
}
bsp/imxrt1052-evk/rtconfig.py
浏览文件 @
7515fb9d
...
...
@@ -77,7 +77,7 @@ elif PLATFORM == 'armcc':
DEVICE
=
' --cpu Cortex-M7.fp.sp'
CFLAGS
=
DEVICE
+
' --apcs=interwork'
AFLAGS
=
DEVICE
LFLAGS
=
DEVICE
+
' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt.map --scatter
imxrt1052_sdram.sct
'
LFLAGS
=
DEVICE
+
' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt.map --scatter
./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf
'
CFLAGS
+=
' --c99 --diag_suppress=66,1296,186'
CFLAGS
+=
' -I'
+
EXEC_PATH
+
'/ARM/RV31/INC'
...
...
@@ -128,7 +128,7 @@ elif PLATFORM == 'iar':
AFLAGS
+=
' --cpu Cortex-M7'
AFLAGS
+=
' --fpu None'
LFLAGS
=
' --config
imxrt1052_sdram
.icf'
LFLAGS
=
' --config
./Libraries/iar/MIMXRT1052xxxxx_flexspi_nor
.icf'
LFLAGS
+=
' --redirect _Printf=_PrintfTiny'
LFLAGS
+=
' --redirect _Scanf=_ScanfSmall'
LFLAGS
+=
' --entry __iar_program_start'
...
...
bsp/imxrt1052-evk/sdram_init.jlinkscript
已删除
100644 → 0
浏览文件 @
b6fef984
/*********************************************************************
* SEGGER MICROCONTROLLER GmbH & Co. K.G. *
* Solutions for real time microcontroller applications *
**********************************************************************
* *
* (c) 2011-2015 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
**********************************************************************
----------------------------------------------------------------------
Purpose :
---------------------------END-OF-HEADER------------------------------
*/
void Clock_Init() {
// Enable all clocks
MEM_WriteU32(0x400FC068,0xffffffff);
MEM_WriteU32(0x400FC06C,0xffffffff);
MEM_WriteU32(0x400FC070,0xffffffff);
MEM_WriteU32(0x400FC074,0xffffffff);
MEM_WriteU32(0x400FC078,0xffffffff);
MEM_WriteU32(0x400FC07C,0xffffffff);
MEM_WriteU32(0x400FC080,0xffffffff);
MEM_WriteU32(0x400D8030,0x00002001);
MEM_WriteU32(0x400D8100,0x00100000);
MEM_WriteU32(0x400FC014,0x00050D40);
Report("Clock Init Done");
}
void SDRAM_WaitIpCmdDone(void)
{
unsigned int reg;
do
{
reg = MEM_ReadU32(0x402F003C);
}while((reg & 0x3) == 0);
}
void SDRAM_Init() {
// Config IOMUX for SDRAM
MEM_WriteU32(0x401F8014,0x00000000);
MEM_WriteU32(0x401F8018,0x00000000);
MEM_WriteU32(0x401F801C,0x00000000);
MEM_WriteU32(0x401F8020,0x00000000);
MEM_WriteU32(0x401F8024,0x00000000);
MEM_WriteU32(0x401F8028,0x00000000);
MEM_WriteU32(0x401F802C,0x00000000);
MEM_WriteU32(0x401F8030,0x00000000);
MEM_WriteU32(0x401F8034,0x00000000);
MEM_WriteU32(0x401F8038,0x00000000);
MEM_WriteU32(0x401F803C,0x00000000);
MEM_WriteU32(0x401F8040,0x00000000);
MEM_WriteU32(0x401F8044,0x00000000);
MEM_WriteU32(0x401F8048,0x00000000);
MEM_WriteU32(0x401F804C,0x00000000);
MEM_WriteU32(0x401F8050,0x00000000);
MEM_WriteU32(0x401F8054,0x00000000);
MEM_WriteU32(0x401F8058,0x00000000);
MEM_WriteU32(0x401F805C,0x00000000);
MEM_WriteU32(0x401F8060,0x00000000);
MEM_WriteU32(0x401F8064,0x00000000);
MEM_WriteU32(0x401F8068,0x00000000);
MEM_WriteU32(0x401F806C,0x00000000);
MEM_WriteU32(0x401F8070,0x00000000);
MEM_WriteU32(0x401F8074,0x00000000);
MEM_WriteU32(0x401F8078,0x00000000);
MEM_WriteU32(0x401F807C,0x00000000);
MEM_WriteU32(0x401F8080,0x00000000);
MEM_WriteU32(0x401F8084,0x00000000);
MEM_WriteU32(0x401F8088,0x00000000);
MEM_WriteU32(0x401F808C,0x00000000);
MEM_WriteU32(0x401F8090,0x00000000);
MEM_WriteU32(0x401F8094,0x00000000);
MEM_WriteU32(0x401F8098,0x00000000);
MEM_WriteU32(0x401F809C,0x00000000);
MEM_WriteU32(0x401F80A0,0x00000000);
MEM_WriteU32(0x401F80A4,0x00000000);
MEM_WriteU32(0x401F80A8,0x00000000);
MEM_WriteU32(0x401F80AC,0x00000000);
MEM_WriteU32(0x401F80B0,0x00000000);
MEM_WriteU32(0x401F80B4,0x00000000);
MEM_WriteU32(0x401F80B8,0x00000000);
// PAD ctrl
MEM_WriteU32(0x401F8204,0x000000F1);
MEM_WriteU32(0x401F8208,0x000000F1);
MEM_WriteU32(0x401F820C,0x000000F1);
MEM_WriteU32(0x401F8210,0x000000F1);
MEM_WriteU32(0x401F8214,0x000000F1);
MEM_WriteU32(0x401F8218,0x000000F1);
MEM_WriteU32(0x401F821C,0x000000F1);
MEM_WriteU32(0x401F8220,0x000000F1);
MEM_WriteU32(0x401F8224,0x000000F1);
MEM_WriteU32(0x401F8228,0x000000F1);
MEM_WriteU32(0x401F822C,0x000000F1);
MEM_WriteU32(0x401F8230,0x000000F1);
MEM_WriteU32(0x401F8234,0x000000F1);
MEM_WriteU32(0x401F8238,0x000000F1);
MEM_WriteU32(0x401F823C,0x000000F1);
MEM_WriteU32(0x401F8240,0x000000F1);
MEM_WriteU32(0x401F8244,0x000000F1);
MEM_WriteU32(0x401F8248,0x000000F1);
MEM_WriteU32(0x401F824C,0x000000F1);
MEM_WriteU32(0x401F8250,0x000000F1);
MEM_WriteU32(0x401F8254,0x000000F1);
MEM_WriteU32(0x401F8258,0x000000F1);
MEM_WriteU32(0x401F825C,0x000000F1);
MEM_WriteU32(0x401F8260,0x000000F1);
MEM_WriteU32(0x401F8264,0x000000F1);
MEM_WriteU32(0x401F8268,0x000000F1);
MEM_WriteU32(0x401F826C,0x000000F1);
MEM_WriteU32(0x401F8270,0x000000F1);
MEM_WriteU32(0x401F8274,0x000000F1);
MEM_WriteU32(0x401F8278,0x000000F1);
MEM_WriteU32(0x401F827C,0x000000F1);
MEM_WriteU32(0x401F8280,0x000000F1);
MEM_WriteU32(0x401F8284,0x000000F1);
MEM_WriteU32(0x401F8288,0x000000F1);
MEM_WriteU32(0x401F828C,0x000000F1);
MEM_WriteU32(0x401F8290,0x000000F1);
MEM_WriteU32(0x401F8294,0x000000F1);
MEM_WriteU32(0x401F8298,0x000000F1);
MEM_WriteU32(0x401F829C,0x000000F1);
MEM_WriteU32(0x401F82A0,0x000000F1);
MEM_WriteU32(0x401F82A4,0x000000F1);
MEM_WriteU32(0x401F82A8,0x000000F1);
// Config SEMC
MEM_WriteU32(0x402F0000,0x1000E000);
MEM_WriteU32(0x402F0008,0x00030524);
MEM_WriteU32(0x402F000C,0x06030524);
MEM_WriteU32(0x402F0010,0x8000001B);
MEM_WriteU32(0x402F0014,0x90000021);
MEM_WriteU32(0x402F0004,0x00000008);
MEM_WriteU32(0x402F0040,0x00000B27);
MEM_WriteU32(0x402F0044,0x00100100);
MEM_WriteU32(0x402F0048,0x00020201);
MEM_WriteU32(0x402F004C,0x08193D0E);
MEM_WriteU32(0x402F0080,0x00000021);
MEM_WriteU32(0x402F0084,0x00888888);
MEM_WriteU32(0x402F0094,0x00000002);
MEM_WriteU32(0x402F0098,0x00000000);
MEM_WriteU32(0x402F0090,0x80000000);
MEM_WriteU32(0x402F009C,0xA55A000F);
SDRAM_WaitIpCmdDone();
MEM_WriteU32(0x402F0090,0x80000000);
MEM_WriteU32(0x402F009C,0xA55A000C);
SDRAM_WaitIpCmdDone();
MEM_WriteU32(0x402F0090,0x80000000);
MEM_WriteU32(0x402F009C,0xA55A000C);
SDRAM_WaitIpCmdDone();
MEM_WriteU32(0x402F00A0,0x00000022);
MEM_WriteU32(0x402F0090,0x80000000);
MEM_WriteU32(0x402F009C,0xA55A000A);
SDRAM_WaitIpCmdDone();
Report("SDRAM Init Done");
}
/* MPU configuration */
void MPU_Init()
{
unsigned int rbar0;
unsigned int rbar1;
unsigned int rbar2;
unsigned int rbar3;
unsigned int rbar4;
unsigned int rbar5;
unsigned int rbar6;
unsigned int rasr0;
unsigned int rasr1;
unsigned int rasr2;
unsigned int rasr3;
unsigned int rasr4;
unsigned int rasr5;
unsigned int rasr6;
unsigned int ctrl;
rbar0 = ((0xC0000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (0 << 0));
rbar1 = ((0x80000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (1 << 0));
rbar2 = ((0x60000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (2 << 0));
rbar3 = ((0x10000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (3 << 0));
rbar4 = ((0x08000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (4 << 0));
rbar5 = ((0x80000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (5 << 0));
rbar6 = ((0x81E00000 & ((0x7FFFFFF << 5))) | (1 << 4) | (6 << 0));
rasr0 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (28 << 1) | (1 << 0);
rasr1 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (29 << 1) | (1 << 0);
rasr2 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (28 << 1) | (1 << 0);
rasr3 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (27 << 1) | (1 << 0);
rasr4 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (26 << 1) | (1 << 0);
rasr5 = (0x3 << 24) | (3 << 16) | (0xC0 << 8) | (25 << 1) | (1 << 0);
rasr6 = (0x3 << 24) | (1 << 19) | (0xC0 << 8) | (20 << 1) | (1 << 0);
ctrl = (0x1 << 0) | (1 << 2);
/* MPU_CTRL. */
MEM_WriteU32(0xE000ED94, 0x0);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar6);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr6);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar5);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr5);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar4);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr4);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar3);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr3);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar2);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr2);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar1);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr1);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar0);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr0);
/* MPU_CTRL. */
MEM_WriteU32(0xE000ED94, ctrl);
}
void flexram_init(void)
{
Report("flexram init\n");
MEM_WriteU32(0x400AC040, 0x80000000); //IOMUXC_GPR_GPR16
//MEM_WriteU32(0x400AC044, 0xFFFFAA55); //IOMUXC_GPR_GPR17: 256K ITCM, 128K DTCM, 128K OCRAM
MEM_WriteU32(0x400AC044, 0xFFFFFFFF); //IOMUXC_GPR_GPR17: 512K ITCM
MEM_WriteU32(0x400AC038, 0x00890000); //IOMUXC_GPR_GPR14
MEM_WriteU32(0x400AC040, 0x80000007); //IOMUXC_GPR_GPR16
}
/* ConfigTarget */
void ConfigTargetSettings(void)
{
Report("Config JTAG Speed to 4000kHz");
JTAG_Speed = 4000;
}
/* SetupTarget */
void SetupTarget(void) {
Report("Enabling i.MXRT SDRAM");
Clock_Init();
flexram_init();
SDRAM_Init();
MPU_Init();
}
/* ResetTarget */
void ResetTarget(void) {
unsigned int v;
unsigned int Tmp;
//
// J-Link DLL expects CPU to be reset and halted when leaving this function
//
Report("J-Link script: ResetTarget()");
//issue a software reset
//Tmp = MEM_ReadU32(0xE000ED0C);
//Tmp = (Tmp&0x0000ffff)|0x05fa0000|(1<<2);
//MEM_WriteU32(0xE000ED0C,Tmp);
//SYS_Sleep(10);
// Read IDCODE
v=JLINK_CORESIGHT_ReadDP(0);
Report1("DP0: ", v);
// Power up Debugger
JLINK_CORESIGHT_WriteDP(1, 0x50000000);
v=JLINK_CORESIGHT_ReadDP(1);
Report1("DP1: ", v);
JLINK_CORESIGHT_WriteAP(0, 0x23000042);
v=JLINK_CORESIGHT_ReadAP(0);
Report1("AHB-AP0: ", v);
JLINK_CORESIGHT_WriteAP(1, 0xE000EDF0);
v=JLINK_CORESIGHT_ReadAP(1);
Report1("AHB-AP1: ", v);
v=JLINK_CORESIGHT_ReadAP(3);
Report1("AHB-AP3: ", v);
JLINK_CORESIGHT_WriteAP(3, 0xa05f0003);
v=JLINK_CORESIGHT_ReadAP(3);
Report1("AHB-AP3: ", v);
Clock_Init();
SDRAM_Init();
MPU_Init();
}
bsp/imxrt1052-evk/sdram_mpu_init.ini
已删除
100644 → 0
浏览文件 @
b6fef984
FUNC
void
SDRAM_WaitIpCmdDone(void)
{
unsigned
long
reg
;
do
{
reg
=
_RDWORD(0x402F003C);
}while((reg
&
0x3)
==
0)
;
}
FUNC
void
_clock_init(void)
{
//
Enable
all
clocks
_WDWORD(0x400FC068,
0xffffffff)
;
_WDWORD(0x400FC06C,
0xffffffff)
;
_WDWORD(0x400FC070,
0xffffffff)
;
_WDWORD(0x400FC074,
0xffffffff)
;
_WDWORD(0x400FC078,
0xffffffff)
;
_WDWORD(0x400FC07C,
0xffffffff)
;
_WDWORD(0x400FC080,
0xffffffff)
;
_WDWORD(0x400D8030,
0x00002001)
;
_WDWORD(0x400D8100,
0x00100000)
;
_WDWORD(0x400FC014,
0x00050D40)
;
}
FUNC
void
_sdr_Init(void)
{
//
Config
IOMUX
_WDWORD(0x401F8014,
0x00000000)
;
_WDWORD(0x401F8018,
0x00000000)
;
_WDWORD(0x401F801C,
0x00000000)
;
_WDWORD(0x401F8020,
0x00000000)
;
_WDWORD(0x401F8024,
0x00000000)
;
_WDWORD(0x401F8028,
0x00000000)
;
_WDWORD(0x401F802C,
0x00000000)
;
_WDWORD(0x401F8030,
0x00000000)
;
_WDWORD(0x401F8034,
0x00000000)
;
_WDWORD(0x401F8038,
0x00000000)
;
_WDWORD(0x401F803C,
0x00000000)
;
_WDWORD(0x401F8040,
0x00000000)
;
_WDWORD(0x401F8044,
0x00000000)
;
_WDWORD(0x401F8048,
0x00000000)
;
_WDWORD(0x401F804C,
0x00000000)
;
_WDWORD(0x401F8050,
0x00000000)
;
_WDWORD(0x401F8054,
0x00000000)
;
_WDWORD(0x401F8058,
0x00000000)
;
_WDWORD(0x401F805C,
0x00000000)
;
_WDWORD(0x401F8060,
0x00000000)
;
_WDWORD(0x401F8064,
0x00000000)
;
_WDWORD(0x401F8068,
0x00000000)
;
_WDWORD(0x401F806C,
0x00000000)
;
_WDWORD(0x401F8070,
0x00000000)
;
_WDWORD(0x401F8074,
0x00000000)
;
_WDWORD(0x401F8078,
0x00000000)
;
_WDWORD(0x401F807C,
0x00000000)
;
_WDWORD(0x401F8080,
0x00000000)
;
_WDWORD(0x401F8084,
0x00000000)
;
_WDWORD(0x401F8088,
0x00000000)
;
_WDWORD(0x401F808C,
0x00000000)
;
_WDWORD(0x401F8090,
0x00000000)
;
_WDWORD(0x401F8094,
0x00000000)
;
_WDWORD(0x401F8098,
0x00000000)
;
_WDWORD(0x401F809C,
0x00000000)
;
_WDWORD(0x401F80A0,
0x00000000)
;
_WDWORD(0x401F80A4,
0x00000000)
;
_WDWORD(0x401F80A8,
0x00000000)
;
_WDWORD(0x401F80AC,
0x00000000)
;
_WDWORD(0x401F80B0,
0x00000000)
;
_WDWORD(0x401F80B4,
0x00000000)
;
_WDWORD(0x401F80B8,
0x00000000)
;
//
PAD
ctrl
_WDWORD(0x401F8204,
0x000000F1)
;
_WDWORD(0x401F8208,
0x000000F1)
;
_WDWORD(0x401F820C,
0x000000F1)
;
_WDWORD(0x401F8210,
0x000000F1)
;
_WDWORD(0x401F8214,
0x000000F1)
;
_WDWORD(0x401F8218,
0x000000F1)
;
_WDWORD(0x401F821C,
0x000000F1)
;
_WDWORD(0x401F8220,
0x000000F1)
;
_WDWORD(0x401F8224,
0x000000F1)
;
_WDWORD(0x401F8228,
0x000000F1)
;
_WDWORD(0x401F822C,
0x000000F1)
;
_WDWORD(0x401F8230,
0x000000F1)
;
_WDWORD(0x401F8234,
0x000000F1)
;
_WDWORD(0x401F8238,
0x000000F1)
;
_WDWORD(0x401F823C,
0x000000F1)
;
_WDWORD(0x401F8240,
0x000000F1)
;
_WDWORD(0x401F8244,
0x000000F1)
;
_WDWORD(0x401F8248,
0x000000F1)
;
_WDWORD(0x401F824C,
0x000000F1)
;
_WDWORD(0x401F8250,
0x000000F1)
;
_WDWORD(0x401F8254,
0x000000F1)
;
_WDWORD(0x401F8258,
0x000000F1)
;
_WDWORD(0x401F825C,
0x000000F1)
;
_WDWORD(0x401F8260,
0x000000F1)
;
_WDWORD(0x401F8264,
0x000000F1)
;
_WDWORD(0x401F8268,
0x000000F1)
;
_WDWORD(0x401F826C,
0x000000F1)
;
_WDWORD(0x401F8270,
0x000000F1)
;
_WDWORD(0x401F8274,
0x000000F1)
;
_WDWORD(0x401F8278,
0x000000F1)
;
_WDWORD(0x401F827C,
0x000000F1)
;
_WDWORD(0x401F8280,
0x000000F1)
;
_WDWORD(0x401F8284,
0x000000F1)
;
_WDWORD(0x401F8288,
0x000000F1)
;
_WDWORD(0x401F828C,
0x000000F1)
;
_WDWORD(0x401F8290,
0x000000F1)
;
_WDWORD(0x401F8294,
0x000000F1)
;
_WDWORD(0x401F8298,
0x000000F1)
;
_WDWORD(0x401F829C,
0x000000F1)
;
_WDWORD(0x401F82A0,
0x000000F1)
;
_WDWORD(0x401F82A4,
0x000000F1)
;
_WDWORD(0x401F82A8,
0x000000F1)
;
_WDWORD(0x402F0000,
0x1000E000)
;
_WDWORD(0x402F0008,
0x00030524)
;
_WDWORD(0x402F000C,
0x06030524)
;
_WDWORD(0x402F0010,
0x8000001B)
;
_WDWORD(0x402F0014,
0x90000021)
;
_WDWORD(0x402F0004,
0x00000008)
;
_WDWORD(0x402F0040,
0x00000B27)
;
_WDWORD(0x402F0044,
0x00100100)
;
_WDWORD(0x402F0048,
0x00020201)
;
_WDWORD(0x402F004C,
0x08193D0E)
;
_WDWORD(0x402F0080,
0x00000021)
;
_WDWORD(0x402F0084,
0x00888888)
;
_WDWORD(0x402F0094,
0x00000002)
;
_WDWORD(0x402F0098,
0x00000000)
;
_WDWORD(0x402F0090,
0x80000000)
;
_WDWORD(0x402F009C,
0xA55A000F)
;
SDRAM_WaitIpCmdDone()
;
_WDWORD(0x402F0090,
0x80000000)
;
_WDWORD(0x402F009C,
0xA55A000C)
;
SDRAM_WaitIpCmdDone()
;
_WDWORD(0x402F0090,
0x80000000)
;
_WDWORD(0x402F009C,
0xA55A000C)
;
SDRAM_WaitIpCmdDone()
;
_WDWORD(0x402F00A0,
0x00000022)
;
_WDWORD(0x402F0090,
0x80000000)
;
_WDWORD(0x402F009C,
0xA55A000A)
;
SDRAM_WaitIpCmdDone()
;
}
FUNC
void
_mpu_Init()
{
unsigned
long
rbar0,
rbar1,
rbar2,
rbar3,
rbar4,
rbar5,
rbar6
;
unsigned
long
rasr0,
rasr1,
rasr2,
rasr3,
rasr4,
rasr5,
rasr6
;
unsigned
long
ctrl
;
rbar0
=
((0xC0000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (0U << 0U));
rbar1
=
((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (1U << 0U));
rbar2
=
((0x60000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (2U << 0U));
rbar3
=
((0x10000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (3U << 0U));
rbar4
=
((0x08000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (4U << 0U));
rbar5
=
((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (5U << 0U));
rbar6
=
((0x81E00000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (6U << 0U));
rasr0
=
(0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U);
rasr1
=
(0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (29U << 1U) | (1U << 0U);
rasr2
=
(0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U);
rasr3
=
(0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (27U << 1U) | (1U << 0U);
rasr4
=
(0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (26U << 1U) | (1U << 0U);
rasr5
=
(0x3U << 24U) | (3UL << 16U) | (0xC0U << 8U) | (25U << 1U) | (1U << 0U);
rasr6
=
(0x3U << 24U) | (1UL << 19U) | (0xC0U << 8U) | (20U << 1U) | (1U << 0U);
/*
Enable
Privileged
default
memory
map
and
the
MPU.
*/
ctrl
=
(0x1U << 0) | (1U << 2U);
/*
MPU_CTRL.
*/
_WDWORD(0xE000ED94,
0x0)
;
/*
MPU_RBAR.
*/
_WDWORD(0xE000ED9C,
rbar6)
;
/*
MPU_RASR.
*/
_WDWORD(0xE000EDA0,
rasr6)
;
/*
MPU_RBAR.
*/
_WDWORD(0xE000ED9C,
rbar5)
;
/*
MPU_RASR.
*/
_WDWORD(0xE000EDA0,
rasr5)
;
_WDWORD(0xE000ED9C,
rbar4)
;
/*
MPU_RASR.
*/
_WDWORD(0xE000EDA0,
rasr4)
;
_WDWORD(0xE000ED9C,
rbar3)
;
/*
MPU_RASR.
*/
_WDWORD(0xE000EDA0,
rasr3)
;
/*
MPU_RBAR.
*/
_WDWORD(0xE000ED9C,
rbar2)
;
/*
MPU_RASR.
*/
_WDWORD(0xE000EDA0,
rasr2)
;
_WDWORD(0xE000ED9C,
rbar1)
;
/*
MPU_RASR.
*/
_WDWORD(0xE000EDA0,
rasr1)
;
_WDWORD(0xE000ED9C,
rbar0)
;
/*
MPU_RASR.
*/
_WDWORD(0xE000EDA0,
rasr0)
;
/*
MPU_CTRL.
*/
_WDWORD(0xE000ED94,
ctrl)
;
}
FUNC
void
_flexram_init(void)
{
_WDWORD(0x400AC040,
0x80000000)
; //IOMUXC_GPR_GPR16
//_WDWORD(0x400AC044,
0xFFFFAA55)
; //IOMUXC_GPR_GPR17
_WDWORD(0x400AC044,
0xFFFFFFFF)
; //IOMUXC_GPR_GPR17
_WDWORD(0x400AC038,
0x00890000)
; //IOMUXC_GPR_GPR14
_WDWORD(0x400AC040,
0x80000007)
; //IOMUXC_GPR_GPR16
}
FUNC
void
Setup
(void)
{
_clock_init()
;
//_flexram_init()
;
_sdr_Init()
;
_mpu_Init()
;
SP
=
_RDWORD(0x00000000); // Setup Stack Pointer
PC
=
_RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08,
0x00000000)
; // Setup Vector Table Offset Register
}
FUNC
void
OnResetExec
(void)
{
//
executes
upon
software
RESET
Setup()
; // Setup for Running
}
LOAD
%L
INCREMENTAL
//
Download
Setup()
; // Setup for Running
//
g,
main
bsp/imxrt1052-evk/sdram_mpu_init.mac
已删除
100644 → 0
浏览文件 @
b6fef984
/*****************************************************************************/
SDRAM_WaitIpCmdDone()
{
__var reg;
do
{
reg = __readMemory32(0x402F003C, "Memory");
}while((reg & 0x3) == 0);
}
_clock_init()
{
// Enable all clocks
__writeMemory32(0xffffffff, 0x400FC068, "Memory");
__writeMemory32(0xffffffff, 0x400FC06C, "Memory");
__writeMemory32(0xffffffff, 0x400FC070, "Memory");
__writeMemory32(0xffffffff, 0x400FC074, "Memory");
__writeMemory32(0xffffffff, 0x400FC078, "Memory");
__writeMemory32(0xffffffff, 0x400FC07C, "Memory");
__writeMemory32(0xffffffff, 0x400FC080, "Memory");
__writeMemory32(0x00002001, 0x400D8030, "Memory");
__writeMemory32(0x00100000, 0x400D8100, "Memory");
__writeMemory32(0x00050D40, 0x400FC014, "Memory");
}
_sdr_Init()
{
// Config IOMUX
__writeMemory32(0x00000000, 0x401F8014, "Memory");
__writeMemory32(0x00000000, 0x401F8018, "Memory");
__writeMemory32(0x00000000, 0x401F801C, "Memory");
__writeMemory32(0x00000000, 0x401F8020, "Memory");
__writeMemory32(0x00000000, 0x401F8024, "Memory");
__writeMemory32(0x00000000, 0x401F8028, "Memory");
__writeMemory32(0x00000000, 0x401F802C, "Memory");
__writeMemory32(0x00000000, 0x401F8030, "Memory");
__writeMemory32(0x00000000, 0x401F8034, "Memory");
__writeMemory32(0x00000000, 0x401F8038, "Memory");
__writeMemory32(0x00000000, 0x401F803C, "Memory");
__writeMemory32(0x00000000, 0x401F8040, "Memory");
__writeMemory32(0x00000000, 0x401F8044, "Memory");
__writeMemory32(0x00000000, 0x401F8048, "Memory");
__writeMemory32(0x00000000, 0x401F804C, "Memory");
__writeMemory32(0x00000000, 0x401F8050, "Memory");
__writeMemory32(0x00000000, 0x401F8054, "Memory");
__writeMemory32(0x00000000, 0x401F8058, "Memory");
__writeMemory32(0x00000000, 0x401F805C, "Memory");
__writeMemory32(0x00000000, 0x401F8060, "Memory");
__writeMemory32(0x00000000, 0x401F8064, "Memory");
__writeMemory32(0x00000000, 0x401F8068, "Memory");
__writeMemory32(0x00000000, 0x401F806C, "Memory");
__writeMemory32(0x00000000, 0x401F8070, "Memory");
__writeMemory32(0x00000000, 0x401F8074, "Memory");
__writeMemory32(0x00000000, 0x401F8078, "Memory");
__writeMemory32(0x00000000, 0x401F807C, "Memory");
__writeMemory32(0x00000000, 0x401F8080, "Memory");
__writeMemory32(0x00000000, 0x401F8084, "Memory");
__writeMemory32(0x00000000, 0x401F8088, "Memory");
__writeMemory32(0x00000000, 0x401F808C, "Memory");
__writeMemory32(0x00000000, 0x401F8090, "Memory");
__writeMemory32(0x00000000, 0x401F8094, "Memory");
__writeMemory32(0x00000000, 0x401F8098, "Memory");
__writeMemory32(0x00000000, 0x401F809C, "Memory");
__writeMemory32(0x00000000, 0x401F80A0, "Memory");
__writeMemory32(0x00000000, 0x401F80A4, "Memory");
__writeMemory32(0x00000000, 0x401F80A8, "Memory");
__writeMemory32(0x00000000, 0x401F80AC, "Memory");
__writeMemory32(0x00000000, 0x401F80B0, "Memory");
__writeMemory32(0x00000000, 0x401F80B4, "Memory");
__writeMemory32(0x00000000, 0x401F80B8, "Memory");
// PAD ctrl
__writeMemory32(0x000000F1, 0x401F8204, "Memory");
__writeMemory32(0x000000F1, 0x401F8208, "Memory");
__writeMemory32(0x000000F1, 0x401F820C, "Memory");
__writeMemory32(0x000000F1, 0x401F8210, "Memory");
__writeMemory32(0x000000F1, 0x401F8214, "Memory");
__writeMemory32(0x000000F1, 0x401F8218, "Memory");
__writeMemory32(0x000000F1, 0x401F821C, "Memory");
__writeMemory32(0x000000F1, 0x401F8220, "Memory");
__writeMemory32(0x000000F1, 0x401F8224, "Memory");
__writeMemory32(0x000000F1, 0x401F8228, "Memory");
__writeMemory32(0x000000F1, 0x401F822C, "Memory");
__writeMemory32(0x000000F1, 0x401F8230, "Memory");
__writeMemory32(0x000000F1, 0x401F8234, "Memory");
__writeMemory32(0x000000F1, 0x401F8238, "Memory");
__writeMemory32(0x000000F1, 0x401F823C, "Memory");
__writeMemory32(0x000000F1, 0x401F8240, "Memory");
__writeMemory32(0x000000F1, 0x401F8244, "Memory");
__writeMemory32(0x000000F1, 0x401F8248, "Memory");
__writeMemory32(0x000000F1, 0x401F824C, "Memory");
__writeMemory32(0x000000F1, 0x401F8250, "Memory");
__writeMemory32(0x000000F1, 0x401F8254, "Memory");
__writeMemory32(0x000000F1, 0x401F8258, "Memory");
__writeMemory32(0x000000F1, 0x401F825C, "Memory");
__writeMemory32(0x000000F1, 0x401F8260, "Memory");
__writeMemory32(0x000000F1, 0x401F8264, "Memory");
__writeMemory32(0x000000F1, 0x401F8268, "Memory");
__writeMemory32(0x000000F1, 0x401F826C, "Memory");
__writeMemory32(0x000000F1, 0x401F8270, "Memory");
__writeMemory32(0x000000F1, 0x401F8274, "Memory");
__writeMemory32(0x000000F1, 0x401F8278, "Memory");
__writeMemory32(0x000000F1, 0x401F827C, "Memory");
__writeMemory32(0x000000F1, 0x401F8280, "Memory");
__writeMemory32(0x000000F1, 0x401F8284, "Memory");
__writeMemory32(0x000000F1, 0x401F8288, "Memory");
__writeMemory32(0x000000F1, 0x401F828C, "Memory");
__writeMemory32(0x000000F1, 0x401F8290, "Memory");
__writeMemory32(0x000000F1, 0x401F8294, "Memory");
__writeMemory32(0x000000F1, 0x401F8298, "Memory");
__writeMemory32(0x000000F1, 0x401F829C, "Memory");
__writeMemory32(0x000000F1, 0x401F82A0, "Memory");
__writeMemory32(0x000000F1, 0x401F82A4, "Memory");
__writeMemory32(0x000000F1, 0x401F82A8, "Memory");
__writeMemory32(0x1000E000, 0x402F0000, "Memory");
__writeMemory32(0x00030524, 0x402F0008, "Memory");
__writeMemory32(0x06030524, 0x402F000C, "Memory");
__writeMemory32(0x8000001B, 0x402F0010, "Memory");
__writeMemory32(0x90000021, 0x402F0014, "Memory");
__writeMemory32(0x00000008, 0x402F0004, "Memory");
__writeMemory32(0x00000B27, 0x402F0040, "Memory");
__writeMemory32(0x00100100, 0x402F0044, "Memory");
__writeMemory32(0x00020201, 0x402F0048, "Memory");
__writeMemory32(0x08193D0E, 0x402F004C, "Memory");
__writeMemory32(0x00000021, 0x402F0080, "Memory");
__writeMemory32(0x00888888, 0x402F0084, "Memory");
__writeMemory32(0x00000002, 0x402F0094, "Memory");
__writeMemory32(0x00000000, 0x402F0098, "Memory");
__writeMemory32(0x80000000, 0x402F0090, "Memory");
__writeMemory32(0xA55A000F, 0x402F009C, "Memory");
SDRAM_WaitIpCmdDone();
__writeMemory32(0x80000000, 0x402F0090, "Memory");
__writeMemory32(0xA55A000C, 0x402F009C, "Memory");
SDRAM_WaitIpCmdDone();
__writeMemory32(0x80000000, 0x402F0090, "Memory");
__writeMemory32(0xA55A000C, 0x402F009C, "Memory");
SDRAM_WaitIpCmdDone();
__writeMemory32(0x00000022, 0x402F00A0, "Memory");
__writeMemory32(0x80000000, 0x402F0090, "Memory");
__writeMemory32(0xA55A000A, 0x402F009C, "Memory");
SDRAM_WaitIpCmdDone();
__message "SDRAM init done\n";
}
_mpu_Init()
{
__var rbar0, rbar1, rbar2, rbar3, rbar4, rbar5, rbar6;
rbar0 = ((0xC0000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (0U << 0U));
rbar1 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (1U << 0U));
rbar2 = ((0x60000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (2U << 0U));
rbar3 = ((0x10000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (3U << 0U));
rbar4 = ((0x08000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (4U << 0U));
rbar5 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (5U << 0U));
rbar6 = ((0x81E00000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (6U << 0U));
__var rasr0, rasr1, rasr2, rasr3, rasr4, rasr5, rasr6;
rasr0 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U);
rasr1 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (29U << 1U) | (1U << 0U);
rasr2 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U);
rasr3 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (27U << 1U) | (1U << 0U);
rasr4 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (26U << 1U) | (1U << 0U);
rasr5 = (0x3U << 24U) | (3UL << 16U) | (0xC0U << 8U) | (25U << 1U) | (1U << 0U);
rasr6 = (0x3U << 24U) | (1UL << 19U) | (0xC0U << 8U) | (20U << 1U) | (1U << 0U);
/* Enable Privileged default memory map and the MPU. */
__var ctrl;
ctrl = (0x1U << 0) | (1U << 2U);
/* MPU_CTRL. */
__writeMemory32(0x0, 0xE000ED94, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar6, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr6, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar5, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr5, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar4, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr4, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar3, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr3, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar2, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr2, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar1, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr1, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar0, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr0, 0xE000EDA0, "Memory");
/* MPU_CTRL. */
__writeMemory32(ctrl, 0xE000ED94, "Memory");
}
_flexram_init()
{
__message "flexram init\n";
__writeMemory32(0x80000000, 0x400AC040, "Memory"); //IOMUXC_GPR_GPR16
//__writeMemory32(0xFFFFAA55, 0x400AC044, "Memory"); //IOMUXC_GPR_GPR17
__writeMemory32(0xFFFFFFFF, 0x400AC044, "Memory"); //IOMUXC_GPR_GPR17
__writeMemory32(0x00890000, 0x400AC038, "Memory"); //IOMUXC_GPR_GPR14
__writeMemory32(0x80000007, 0x400AC040, "Memory"); //IOMUXC_GPR_GPR16
}
execUserPreload()
{
__message "execUserPreload() start.\n";
_clock_init();
_flexram_init();
_sdr_Init();
_mpu_Init();
__message "execUserPreload() done.\n";
}
execUserReset()
{
__message "execUserReset() start.\n";
_clock_init();
_flexram_init();
_sdr_Init();
_mpu_Init();
__message "execUserReset() done.\n";
}
components/drivers/spi/SConscript
浏览文件 @
7515fb9d
from
building
import
*
import
rtconfig
cwd
=
GetCurrentDir
()
src
=
[
'spi_core.c'
,
'spi_dev.c'
]
CPPPATH
=
[
cwd
,
cwd
+
'/../include'
]
LOCAL_CCFLAGS
=
''
src_device
=
[]
...
...
@@ -32,9 +34,13 @@ if GetDepend('RT_USING_SFUD'):
CPPPATH
+=
[
cwd
+
'/sfud/inc'
]
if
GetDepend
(
'RT_SFUD_USING_SFDP'
):
src_device
+=
[
'sfud/src/sfud_sfdp.c'
]
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
LOCAL_CCFLAGS
+=
' -std=c99'
elif
rtconfig
.
CROSS_TOOL
==
'keil'
:
LOCAL_CCFLAGS
+=
' --c99'
src
+=
src_device
group
=
DefineGroup
(
'DeviceDrivers'
,
src
,
depend
=
[
'RT_USING_SPI'
],
CPPPATH
=
CPPPATH
)
group
=
DefineGroup
(
'DeviceDrivers'
,
src
,
depend
=
[
'RT_USING_SPI'
],
CPPPATH
=
CPPPATH
,
LOCAL_CCFLAGS
=
LOCAL_CCFLAGS
)
Return
(
'group'
)
components/drivers/spi/spi_flash_sfud.c
浏览文件 @
7515fb9d
...
...
@@ -165,11 +165,6 @@ static void spi_unlock(const sfud_spi *spi) {
rt_mutex_release
(
&
(
rtt_dev
->
lock
));
}
static
void
retry_delay_ms
(
void
)
{
/* millisecond delay */
rt_tick_from_millisecond
(
1
);
}
static
void
retry_delay_100us
(
void
)
{
/* 100 microsecond delay */
rt_thread_delay
((
RT_TICK_PER_SECOND
*
1
+
9999
)
/
10000
);
...
...
@@ -242,6 +237,9 @@ rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const
rt_spi_flash_device_t
rtt_dev
=
RT_NULL
;
sfud_flash
*
sfud_dev
=
RT_NULL
;
char
*
spi_flash_dev_name_bak
=
RT_NULL
,
*
spi_dev_name_bak
=
RT_NULL
;
/* using default flash SPI configuration for initialize SPI Flash
* @note you also can change the SPI to other configuration after initialized finish */
struct
rt_spi_configuration
cfg
=
RT_SFUD_DEFAULT_SPI_CFG
;
extern
sfud_err
sfud_device_init
(
sfud_flash
*
flash
);
RT_ASSERT
(
spi_flash_dev_name
);
...
...
@@ -269,9 +267,6 @@ rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const
goto
error
;
}
sfud_dev
->
spi
.
name
=
spi_dev_name_bak
;
/* using default flash SPI configuration for initialize SPI Flash
* @note you also can change the SPI to other configuration after initialized finish */
struct
rt_spi_configuration
cfg
=
RT_SFUD_DEFAULT_SPI_CFG
;
rt_spi_configure
(
rtt_dev
->
rt_spi_device
,
&
cfg
);
/* initialize lock */
rt_mutex_init
(
&
(
rtt_dev
->
lock
),
spi_flash_dev_name
,
RT_IPC_FLAG_FIFO
);
...
...
components/net/Kconfig
浏览文件 @
7515fb9d
...
...
@@ -97,6 +97,10 @@ config RT_USING_LWIP
default n
endif
config RT_MEMP_NUM_NETCONN
int "the number of struct netconns"
default 8
config RT_LWIP_PBUF_NUM
int "the number of PBUF"
default 16
...
...
components/net/lwip-1.4.1/src/lwipopts.h
浏览文件 @
7515fb9d
...
...
@@ -93,6 +93,11 @@
should be set high. */
#define MEMP_NUM_PBUF 16
/* the number of struct netconns */
#ifdef RT_MEMP_NUM_NETCONN
#define MEMP_NUM_NETCONN RT_MEMP_NUM_NETCONN
#endif
/* the number of UDP protocol control blocks. One per active RAW "connection". */
#ifdef RT_LWIP_RAW_PCB_NUM
#define MEMP_NUM_RAW_PCB RT_LWIP_RAW_PCB_NUM
...
...
components/net/lwip-2.0.2/src/lwipopts.h
浏览文件 @
7515fb9d
...
...
@@ -105,6 +105,11 @@
should be set high. */
#define MEMP_NUM_PBUF 32 //16
/* the number of struct netconns */
#ifdef RT_MEMP_NUM_NETCONN
#define MEMP_NUM_NETCONN RT_MEMP_NUM_NETCONN
#endif
/* the number of UDP protocol control blocks. One per active RAW "connection". */
#ifdef RT_LWIP_RAW_PCB_NUM
#define MEMP_NUM_RAW_PCB RT_LWIP_RAW_PCB_NUM
...
...
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