From 24d29d829760f1432a68c9e06aaa7c47ff652d1f Mon Sep 17 00:00:00 2001 From: Weilin Wang Date: Tue, 3 Aug 2021 11:26:46 +0800 Subject: [PATCH] fix net driver --- bsp/raspberry-pi/raspi4-32/.config | 151 ++++++---- bsp/raspberry-pi/raspi4-32/Kconfig | 1 + bsp/raspberry-pi/raspi4-32/driver/drv_eth.c | 291 ++++++++++---------- bsp/raspberry-pi/raspi4-32/link.lds | 2 +- bsp/raspberry-pi/raspi4-32/rtconfig.h | 29 +- bsp/raspberry-pi/raspi4-32/rtconfig.py | 2 +- 6 files changed, 259 insertions(+), 217 deletions(-) diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config index 813f9417f1..40f89fce1a 100644 --- a/bsp/raspberry-pi/raspi4-32/.config +++ b/bsp/raspberry-pi/raspi4-32/.config @@ -23,6 +23,12 @@ CONFIG_IDLE_THREAD_STACK_SIZE=2048 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -67,8 +73,10 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 # CONFIG_RT_USING_CPU_FFS is not set +CONFIG_RT_USING_GIC_V2=y CONFIG_ARCH_ARMV8=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -125,6 +133,11 @@ CONFIG_RT_DFS_ELM_WORD_ACCESS=y # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set CONFIG_RT_DFS_ELM_USE_LFN_3=y CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 CONFIG_RT_DFS_ELM_MAX_LFN=255 CONFIG_RT_DFS_ELM_DRIVES=2 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 @@ -133,8 +146,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set # CONFIG_RT_USING_DFS_NFS is not set # @@ -146,6 +157,8 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=512 # CONFIG_RT_USING_CAN is not set @@ -181,6 +194,7 @@ CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set CONFIG_RT_USING_TOUCH=y +# CONFIG_RT_TOUCH_PIN_IRQ is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set @@ -203,6 +217,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Network @@ -212,6 +227,7 @@ CONFIG_RT_USING_POSIX=y # Socket abstraction layer # CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y # # protocol stack implement @@ -238,6 +254,7 @@ CONFIG_NETDEV_IPV6=0 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP203 is not set # CONFIG_RT_USING_LWIP212 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set CONFIG_RT_LWIP_MEM_ALIGNMENT=4 @@ -252,8 +269,8 @@ CONFIG_IP_SOF_BROADCAST_RECV=1 # # Static IPv4 Address # -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_IPADDR="192.168.111.172" +CONFIG_RT_LWIP_GWADDR="192.168.111.1" CONFIG_RT_LWIP_MSKADDR="255.255.255.0" CONFIG_RT_LWIP_UDP=y CONFIG_RT_LWIP_TCP=y @@ -307,6 +324,12 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set # # RT-Thread online packages @@ -375,8 +398,6 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -390,6 +411,13 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set # # security packages @@ -415,6 +443,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set # CONFIG_PKG_USING_HELIX is not set # CONFIG_PKG_USING_AZUREGUIX is not set # CONFIG_PKG_USING_TOUCHGFX2RTT is not set @@ -429,6 +458,8 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set @@ -441,6 +472,20 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_URLENCODE is not set # CONFIG_PKG_USING_UMCN is not set # CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set # # system packages @@ -448,7 +493,6 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set # CONFIG_PKG_USING_FLASHDB is not set @@ -458,6 +502,9 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set @@ -478,6 +525,15 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set # # peripheral libraries and drivers @@ -486,6 +542,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -534,6 +591,29 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_DM9051 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages @@ -543,6 +623,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -564,64 +645,24 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # -# games: games run on RT-Thread console +# entertainment: terminal games and other interesting software packages # # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set # CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set # CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_MDNS is not set -# CONFIG_PKG_USING_UPNP is not set -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_VIRTUAL_DEVICE is not set -# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set CONFIG_BCM2711_SOC=y # CONFIG_BSP_SUPPORT_FPU is not set diff --git a/bsp/raspberry-pi/raspi4-32/Kconfig b/bsp/raspberry-pi/raspi4-32/Kconfig index 1e49c47680..79712f4f17 100644 --- a/bsp/raspberry-pi/raspi4-32/Kconfig +++ b/bsp/raspberry-pi/raspi4-32/Kconfig @@ -23,6 +23,7 @@ config BCM2711_SOC select ARCH_ARMV8 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_GIC_V2 default y source "driver/Kconfig" diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c index 163f58c150..a11707f7a2 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c @@ -19,6 +19,7 @@ #include "raspi4.h" #include "drv_eth.h" + #define DBG_LEVEL DBG_LOG #include #define LOG_TAG "drv.eth" @@ -26,12 +27,14 @@ static int link_speed = 0; static int link_flag = 0; -#define RECV_CACHE_BUF (2048) -#define SEND_CACHE_BUF (2048) -#define DMA_DISC_ADDR_SIZE (2 * 1024 *1024) +#define RECV_CACHE_BUF (1024) +#define SEND_CACHE_BUF (1024) +#define SEND_DATA_NO_CACHE (0x08200000) +#define RECV_DATA_NO_CACHE (0x08400000) +#define DMA_DISC_ADDR_SIZE (4 * 1024 *1024) -#define RX_DESC_BASE (mac_reg_base_addr + GENET_RX_OFF) -#define TX_DESC_BASE (mac_reg_base_addr + GENET_TX_OFF) +#define RX_DESC_BASE (MAC_REG + GENET_RX_OFF) +#define TX_DESC_BASE (MAC_REG + GENET_TX_OFF) #define MAX_ADDR_LEN (6) @@ -45,11 +48,11 @@ static rt_thread_t link_thread_tid = RT_NULL; #define LINK_THREAD_PRIORITY (20) #define LINK_THREAD_TIMESLICE (10) - static rt_uint32_t tx_index = 0; static rt_uint32_t rx_index = 0; static rt_uint32_t index_flag = 0; +static rt_uint32_t send_cache_pbuf[RECV_CACHE_BUF]; struct rt_eth_dev { @@ -60,12 +63,11 @@ struct rt_eth_dev int state; int index; struct rt_timer link_timer; + struct rt_timer rx_poll_timer; void *priv; }; static struct rt_eth_dev eth_dev; - -static struct rt_semaphore send_finsh_sem_lock; - +static struct rt_semaphore sem_lock; static struct rt_semaphore link_ack; static inline rt_uint32_t read32(void *addr) @@ -78,18 +80,12 @@ static inline void write32(void *addr, rt_uint32_t value) (*((volatile unsigned int*)(addr))) = value; } - - - static void eth_rx_irq(int irq, void *param) { rt_uint32_t val = 0; - - val = read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT); - val &= ~read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT_MASK); - - write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR, val); - + val = read32(MAC_REG + GENET_INTRL2_CPU_STAT); + val &= ~read32(MAC_REG + GENET_INTRL2_CPU_STAT_MASK); + write32(MAC_REG + GENET_INTRL2_CPU_CLEAR, val); if (val & GENET_IRQ_RXDMA_DONE) { eth_device_ready(ð_dev.parent); @@ -97,7 +93,7 @@ static void eth_rx_irq(int irq, void *param) if (val & GENET_IRQ_TXDMA_DONE) { - rt_sem_release(&send_finsh_sem_lock); + rt_sem_release(&sem_lock); } } @@ -109,11 +105,10 @@ static int bcmgenet_interface_set(void) { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_RXID: - write32(mac_reg_base_addr + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY); + write32(MAC_REG + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY); break; - default: - rt_kprintf("unknown phy mode: %d\n", mac_reg_base_addr); + rt_kprintf("unknown phy mode: %d\n", MAC_REG); return -1; } return 0; @@ -122,48 +117,44 @@ static int bcmgenet_interface_set(void) static void bcmgenet_umac_reset(void) { rt_uint32_t reg; - reg = read32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL); + reg = read32(MAC_REG + SYS_RBUF_FLUSH_CTRL); reg |= BIT(1); - write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); + write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg); reg &= ~BIT(1); - write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); + write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg); DELAY_MICROS(10); - - write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), 0); + write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), 0); DELAY_MICROS(10); - - write32(mac_reg_base_addr + UMAC_CMD, 0); - write32(mac_reg_base_addr + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); + write32(MAC_REG + UMAC_CMD, 0); + write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); DELAY_MICROS(2); - - write32(mac_reg_base_addr + UMAC_CMD, 0); + write32(MAC_REG + UMAC_CMD, 0); /* clear tx/rx counter */ - write32(mac_reg_base_addr + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT); - write32(mac_reg_base_addr + UMAC_MIB_CTRL, 0); - write32(mac_reg_base_addr + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE); - + write32(MAC_REG + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT); + write32(MAC_REG + UMAC_MIB_CTRL, 0); + write32(MAC_REG + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE); /* init rx registers, enable ip header optimization */ - reg = read32(mac_reg_base_addr + RBUF_CTRL); + reg = read32(MAC_REG + RBUF_CTRL); reg |= RBUF_ALIGN_2B; - write32(mac_reg_base_addr + RBUF_CTRL, reg); - write32(mac_reg_base_addr + RBUF_TBUF_SIZE_CTRL, 1); + write32(MAC_REG + RBUF_CTRL, reg); + write32(MAC_REG + RBUF_TBUF_SIZE_CTRL, 1); } static void bcmgenet_disable_dma(void) { rt_uint32_t tdma_reg = 0, rdma_reg = 0; - tdma_reg = read32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL); + tdma_reg = read32(MAC_REG + TDMA_REG_BASE + DMA_CTRL); tdma_reg &= ~(1UL << DMA_EN); - write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, tdma_reg); - rdma_reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL); + write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, tdma_reg); + rdma_reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL); rdma_reg &= ~(1UL << DMA_EN); - write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, rdma_reg); - write32(mac_reg_base_addr + UMAC_TX_FLUSH, 1); + write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, rdma_reg); + write32(MAC_REG + UMAC_TX_FLUSH, 1); DELAY_MICROS(100); - write32(mac_reg_base_addr + UMAC_TX_FLUSH, 0); + write32(MAC_REG + UMAC_TX_FLUSH, 0); } static void bcmgenet_enable_dma(void) @@ -172,10 +163,10 @@ static void bcmgenet_enable_dma(void) rt_uint32_t dma_ctrl = 0; dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; - write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, dma_ctrl); + write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, dma_ctrl); - reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL); - write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg); + reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL); + write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg); } static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value) @@ -183,16 +174,16 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va int count = 10000; rt_uint32_t val; val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value); - write32(mac_reg_base_addr + MDIO_CMD, val); + write32(MAC_REG + MDIO_CMD, val); - rt_uint32_t reg_val = read32(mac_reg_base_addr + MDIO_CMD); + rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD); reg_val = reg_val | MDIO_START_BUSY; - write32(mac_reg_base_addr + MDIO_CMD, reg_val); + write32(MAC_REG + MDIO_CMD, reg_val); - while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count)) DELAY_MICROS(1); - reg_val = read32(mac_reg_base_addr + MDIO_CMD); + reg_val = read32(MAC_REG + MDIO_CMD); return reg_val & 0xffff; } @@ -204,31 +195,32 @@ static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg) rt_uint32_t reg_val = 0; val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); - write32(mac_reg_base_addr + MDIO_CMD, val); + write32(MAC_REG + MDIO_CMD, val); - reg_val = read32(mac_reg_base_addr + MDIO_CMD); + reg_val = read32(MAC_REG + MDIO_CMD); reg_val = reg_val | MDIO_START_BUSY; - write32(mac_reg_base_addr + MDIO_CMD, reg_val); + write32(MAC_REG + MDIO_CMD, reg_val); - while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count)) DELAY_MICROS(1); - reg_val = read32(mac_reg_base_addr + MDIO_CMD); + reg_val = read32(MAC_REG + MDIO_CMD); return reg_val & 0xffff; } static int bcmgenet_gmac_write_hwaddr(void) { + //{0xdc,0xa6,0x32,0x28,0x22,0x50}; rt_uint8_t addr[6]; rt_uint32_t reg; bcm271x_mbox_hardware_get_mac_address(&addr[0]); reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; - write32(mac_reg_base_addr + UMAC_MAC0, reg); + write32(MAC_REG + UMAC_MAC0, reg); reg = addr[4] << 8 | addr[5]; - write32(mac_reg_base_addr + UMAC_MAC1, reg); + write32(MAC_REG + UMAC_MAC1, reg); return 0; } @@ -254,8 +246,10 @@ static void bcmgenet_mdio_init(void) rt_uint32_t ret = 0; /*get ethernet uid*/ ret = get_ethernet_uid(); - if (ret == 0) return; - + if (ret == 0) + { + return; + } /* reset phy */ bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET); /* read control reg */ @@ -282,34 +276,34 @@ static void bcmgenet_mdio_init(void) static void rx_ring_init(void) { - write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); - write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); - write32(mac_reg_base_addr + RDMA_READ_PTR, 0x0); - write32(mac_reg_base_addr + RDMA_WRITE_PTR, 0x0); - write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); - - write32(mac_reg_base_addr + RDMA_PROD_INDEX, 0x0); - write32(mac_reg_base_addr + RDMA_CONS_INDEX, 0x0); - write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); - write32(mac_reg_base_addr + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); - write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); + write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(MAC_REG + RDMA_READ_PTR, 0x0); + write32(MAC_REG + RDMA_WRITE_PTR, 0x0); + write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); + + write32(MAC_REG + RDMA_PROD_INDEX, 0x0); + write32(MAC_REG + RDMA_CONS_INDEX, 0x0); + write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); + write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); } static void tx_ring_init(void) { - write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); - write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); - write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); - write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); - write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); - write32(mac_reg_base_addr + TDMA_WRITE_PTR, 0x0); - write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1); - write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0x0); - write32(mac_reg_base_addr + TDMA_CONS_INDEX, 0x0); - write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1); - write32(mac_reg_base_addr + TDMA_FLOW_PERIOD, 0x0); - write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); - write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); + write32(MAC_REG + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(MAC_REG + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(MAC_REG + TDMA_READ_PTR, 0x0); + write32(MAC_REG + TDMA_READ_PTR, 0x0); + write32(MAC_REG + TDMA_READ_PTR, 0x0); + write32(MAC_REG + TDMA_WRITE_PTR, 0x0); + write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1); + write32(MAC_REG + TDMA_PROD_INDEX, 0x0); + write32(MAC_REG + TDMA_CONS_INDEX, 0x0); + write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1); + write32(MAC_REG + TDMA_FLOW_PERIOD, 0x0); + write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); } static void rx_descs_init(void) @@ -348,14 +342,14 @@ static int bcmgenet_adjust_link(void) return -1; } - rt_uint32_t reg1 = read32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL); + rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL); //reg1 &= ~(1UL << OOB_DISABLE); //rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE); reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); - write32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL, reg1); + write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1); DELAY_MICROS(1000); - write32(mac_reg_base_addr + UMAC_CMD, speed << CMD_SPEED_SHIFT); + write32(MAC_REG + UMAC_CMD, speed << CMD_SPEED_SHIFT); return 0; } @@ -393,28 +387,28 @@ static int bcmgenet_gmac_eth_start(void) } /* wait tx index clear */ - while ((read32(mac_reg_base_addr + TDMA_CONS_INDEX) != 0) && (--count)) + while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count)) DELAY_MICROS(1); - tx_index = read32(mac_reg_base_addr + TDMA_CONS_INDEX); - write32(mac_reg_base_addr + TDMA_PROD_INDEX, tx_index); + tx_index = read32(MAC_REG + TDMA_CONS_INDEX); + write32(MAC_REG + TDMA_PROD_INDEX, tx_index); - index_flag = read32(mac_reg_base_addr + RDMA_PROD_INDEX); + index_flag = read32(MAC_REG + RDMA_PROD_INDEX); rx_index = index_flag % RX_DESCS; - write32(mac_reg_base_addr + RDMA_CONS_INDEX, index_flag); - write32(mac_reg_base_addr + RDMA_PROD_INDEX, index_flag); + write32(MAC_REG + RDMA_CONS_INDEX, index_flag); + write32(MAC_REG + RDMA_PROD_INDEX, index_flag); /* Enable Rx/Tx */ rt_uint32_t rx_tx_en; - rx_tx_en = read32(mac_reg_base_addr + UMAC_CMD); - rx_tx_en |= (CMD_TX_EN | CMD_RX_EN); + rx_tx_en = read32(MAC_REG + UMAC_CMD); - write32(mac_reg_base_addr + UMAC_CMD, rx_tx_en); + rx_tx_en |= (CMD_TX_EN | CMD_RX_EN); - // eanble IRQ for TxDMA done and RxDMA done - write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE); + write32(MAC_REG + UMAC_CMD, rx_tx_en); + //IRQ + write32(MAC_REG + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE); return 0; } @@ -424,16 +418,17 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) { void* desc_base; rt_uint32_t length = 0, addr = 0; - rt_uint32_t prod_index = read32(mac_reg_base_addr + RDMA_PROD_INDEX); - if(prod_index == index_flag) //no buff + rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX); + if(prod_index == index_flag) { cur_recv_cnt = index_flag; index_flag = 0x7fffffff; + /* no buff */ return 0; } else { - if(prev_recv_cnt == (prod_index & 0xffff)) //no new buff + if(prev_recv_cnt == prod_index & 0xffff) { return 0; } @@ -446,11 +441,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) * This would actually not be needed if we don't program * RBUF_ALIGN_2B */ - - //Convert to memory address - addr = addr + eth_recv_no_cache - RECV_DATA_NO_CACHE; - rt_hw_cpu_dcache_invalidate(addr,length); - + rt_hw_cpu_dcache_invalidate(addr,length); *packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET); rx_index = rx_index + 1; @@ -458,8 +449,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) { rx_index = 0; } - - write32(mac_reg_base_addr + RDMA_CONS_INDEX, cur_recv_cnt); + write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt); cur_recv_cnt = cur_recv_cnt + 1; @@ -469,43 +459,45 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) } prev_recv_cnt = cur_recv_cnt; - return length - RX_BUF_OFFSET; + return length; } } - -static int bcmgenet_gmac_eth_send(rt_uint32_t packet, int length,struct pbuf *p) +static int bcmgenet_gmac_eth_send(void *packet, int length) { - rt_ubase_t level; void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); - pbuf_copy_partial(p, (void*)(packet + tx_index * SEND_CACHE_BUF), p->tot_len, 0); rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT; - len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; - len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; - rt_hw_cpu_dcache_clean((void*)(packet + tx_index * SEND_CACHE_BUF),length); - rt_uint32_t prod_index; + rt_uint32_t prod_index, cons; + rt_uint32_t tries = 100; - prod_index = read32(mac_reg_base_addr + TDMA_PROD_INDEX); + prod_index = read32(MAC_REG + TDMA_PROD_INDEX); - write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE + tx_index * SEND_CACHE_BUF); + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; + + rt_hw_cpu_dcache_clean((void*)packet, length); + write32((desc_base + DMA_DESC_ADDRESS_LO), packet); write32((desc_base + DMA_DESC_ADDRESS_HI), 0); write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat); - tx_index ++; - if(tx_index >= TX_DESCS) - { - tx_index = 0; - } + tx_index = tx_index + 1; prod_index = prod_index + 1; - if (prod_index > 0xffff) + if (prod_index == 0xe000) { + write32(MAC_REG + TDMA_PROD_INDEX, 0); prod_index = 0; } + if (tx_index >= TX_DESCS) + { + tx_index = 0; + } + /* Start Transmisson */ - write32(mac_reg_base_addr + TDMA_PROD_INDEX, prod_index); + write32(MAC_REG + TDMA_PROD_INDEX, prod_index); + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); return 0; } @@ -514,10 +506,8 @@ static void link_task_entry(void *param) struct eth_device *eth_device = (struct eth_device *)param; RT_ASSERT(eth_device != RT_NULL); struct rt_eth_dev *dev = ð_dev; - //start mdio bcmgenet_mdio_init(); - //start timer link rt_timer_init(&dev->link_timer, "link_timer", link_irq, @@ -532,7 +522,7 @@ static void link_task_entry(void *param) rt_timer_stop(&dev->link_timer); //set mac - // bcmgenet_gmac_write_hwaddr(); + bcmgenet_gmac_write_hwaddr(); bcmgenet_gmac_write_hwaddr(); //check link speed @@ -552,13 +542,9 @@ static void link_task_entry(void *param) rt_kprintf("Support link mode Speed 10M\n"); } - - //Convert to memory address bcmgenet_gmac_eth_start(); - rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq"); rt_hw_interrupt_umask(ETH_IRQ); - link_flag = 1; } @@ -569,7 +555,7 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device) /* Read GENET HW version */ rt_uint8_t major = 0; - hw_reg = read32(mac_reg_base_addr + SYS_REV_CTRL); + hw_reg = read32(MAC_REG + SYS_REV_CTRL); major = (hw_reg >> 24) & 0x0f; if (major != 6) { @@ -589,12 +575,12 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device) } /* rbuf clear */ - write32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL, 0); + write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0); /* disable MAC while updating its registers */ - write32(mac_reg_base_addr + UMAC_CMD, 0); + write32(MAC_REG + UMAC_CMD, 0); /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ - write32(mac_reg_base_addr + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); + write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device, LINK_THREAD_STACK_SIZE, @@ -623,28 +609,32 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args) rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) { + rt_uint32_t sendbuf = (rt_uint32_t)SEND_DATA_NO_CACHE + (rt_uint32_t)(tx_index * SEND_CACHE_BUF); + /* lock eth device */ if (link_flag == 1) { - bcmgenet_gmac_eth_send((rt_uint32_t)eth_send_no_cache, p->tot_len,p); - rt_sem_take(&send_finsh_sem_lock,RT_WAITING_FOREVER); + pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0); + rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len); + bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len); } - return RT_EOK; } struct pbuf *rt_eth_rx(rt_device_t device) { int recv_len = 0; - rt_uint8_t* addr_point = RT_NULL; + rt_uint8_t *addr_point = RT_NULL; struct pbuf *pbuf = RT_NULL; if (link_flag == 1) { - recv_len = bcmgenet_gmac_eth_recv(&addr_point); + recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point); if (recv_len > 0) { pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); - if(pbuf) - rt_memcpy(pbuf->payload, addr_point, recv_len); + if(pbuf) + { + rt_memcpy(pbuf->payload, addr_point, recv_len); + } } } return pbuf; @@ -653,14 +643,15 @@ struct pbuf *rt_eth_rx(rt_device_t device) int rt_hw_eth_init(void) { rt_uint8_t mac_addr[6]; - rt_sem_init(&send_finsh_sem_lock,"send_finsh_sem_lock",TX_DESCS,RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_send_lock", TX_DESCS, RT_IPC_FLAG_FIFO); rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO); + memset(ð_dev, 0, sizeof(eth_dev)); - memset((void *)eth_send_no_cache, 0, DMA_DISC_ADDR_SIZE); - memset((void *)eth_recv_no_cache, 0, DMA_DISC_ADDR_SIZE); + memset((void *)SEND_DATA_NO_CACHE, 0, DMA_DISC_ADDR_SIZE); + memset((void *)RECV_DATA_NO_CACHE, 0, DMA_DISC_ADDR_SIZE); bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]); - eth_dev.iobase = mac_reg_base_addr; + eth_dev.iobase = MAC_REG; eth_dev.name = "e0"; eth_dev.dev_addr[0] = mac_addr[0]; eth_dev.dev_addr[1] = mac_addr[1]; diff --git a/bsp/raspberry-pi/raspi4-32/link.lds b/bsp/raspberry-pi/raspi4-32/link.lds index df4ecb5ad3..6ab3707d08 100644 --- a/bsp/raspberry-pi/raspi4-32/link.lds +++ b/bsp/raspberry-pi/raspi4-32/link.lds @@ -11,7 +11,7 @@ SECTIONS { - . = 0x8000; + . = 0x200000; . = ALIGN(4096); .text : { diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h index c31d300cb2..0ceac4cfd7 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h @@ -19,6 +19,9 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 2048 + +/* kservice optimization */ + #define RT_DEBUG /* Inter-Thread communication */ @@ -41,7 +44,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40003 +#define RT_VER_NUM 0x40004 +#define RT_USING_GIC_V2 #define ARCH_ARMV8 /* RT-Thread Components */ @@ -84,6 +88,8 @@ #define RT_DFS_ELM_WORD_ACCESS #define RT_DFS_ELM_USE_LFN_3 #define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 #define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 @@ -98,6 +104,7 @@ #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 512 #define RT_USING_I2C @@ -120,12 +127,14 @@ #define RT_USING_LIBC #define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 /* Network */ /* Socket abstraction layer */ #define RT_USING_SAL +#define SAL_INTERNET_CHECK /* protocol stack implement */ @@ -156,8 +165,8 @@ /* Static IPv4 Address */ -#define RT_LWIP_IPADDR "192.168.1.30" -#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_IPADDR "192.168.111.172" +#define RT_LWIP_GWADDR "192.168.111.1" #define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP @@ -195,6 +204,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -232,19 +244,16 @@ /* peripheral libraries and drivers */ -/* miscellaneous packages */ - - -/* samples: kernel and components samples */ +/* AI packages */ -/* games: games run on RT-Thread console */ +/* miscellaneous packages */ -/* Privated Packages of RealThread */ +/* samples: kernel and components samples */ -/* Network Utilities */ +/* entertainment: terminal games and other interesting software packages */ #define BCM2711_SOC diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.py b/bsp/raspberry-pi/raspi4-32/rtconfig.py index 681ec91b9e..49fa603b1e 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.py +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.py @@ -37,7 +37,7 @@ if PLATFORM == 'gcc': DEVICE = ' -march=armv8-a -mtune=cortex-a72' CFLAGS = DEVICE + ' -Wall' - AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' CPATH = '' LPATH = '' -- GitLab