From f1fd03c3fc91d787643fd7e3bc6d14b2a3a99993 Mon Sep 17 00:00:00 2001 From: Ouxiaolong <1576690133@qq.com> Date: Sat, 4 Sep 2021 09:48:56 +0800 Subject: [PATCH] add gd32407v-start --- bsp/gd32/gd32407v-start/README.md | 2 +- bsp/gd32/gd32407v-start/board/Kconfig | 2 +- bsp/gd32/gd32407v-start/board/SConscript | 2 - bsp/gd32/gd32407v-start/project.uvoptx | 262 +++++---------------- bsp/gd32/gd32407v-start/project.uvprojx | 139 ++++------- bsp/gd32/libraries/HAL_Drivers/Kconfig | 36 --- bsp/gd32/libraries/HAL_Drivers/drv_gpio.c | 46 ++-- bsp/gd32/libraries/HAL_Drivers/drv_usart.c | 24 +- 8 files changed, 145 insertions(+), 368 deletions(-) diff --git a/bsp/gd32/gd32407v-start/README.md b/bsp/gd32/gd32407v-start/README.md index a95a715158..31a3403810 100644 --- a/bsp/gd32/gd32407v-start/README.md +++ b/bsp/gd32/gd32407v-start/README.md @@ -39,7 +39,7 @@ GD32407V-STARTL是-兆易创新推出的一款GD32F4XX系列的评估板，最 ### 快速上手 -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 +本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 #### 硬件连接 diff --git a/bsp/gd32/gd32407v-start/board/Kconfig b/bsp/gd32/gd32407v-start/board/Kconfig index 4bf9b828c3..190489eaa9 100644 --- a/bsp/gd32/gd32407v-start/board/Kconfig +++ b/bsp/gd32/gd32407v-start/board/Kconfig @@ -2,7 +2,7 @@ menu "Hardware Drivers Config" config SOC_GD32407V bool - select SOC_SERIES_GD32F4 + select SOC_SERIES_GD32F4 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/gd32/gd32407v-start/board/SConscript b/bsp/gd32/gd32407v-start/board/SConscript index fa88754d91..0e2bf06321 100644 --- a/bsp/gd32/gd32407v-start/board/SConscript +++ b/bsp/gd32/gd32407v-start/board/SConscript @@ -19,8 +19,6 @@ if rtconfig.CROSS_TOOL == 'gcc': src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S'] elif rtconfig.CROSS_TOOL == 'keil': src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s'] -elif rtconfig.CROSS_TOOL == 'iar': - src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s'] CPPDEFINES = ['GD3232F407xx'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) diff --git a/bsp/gd32/gd32407v-start/project.uvoptx b/bsp/gd32/gd32407v-start/project.uvoptx index 88b9d8ef78..b6bd27ba2c 100644 --- a/bsp/gd32/gd32407v-start/project.uvoptx +++ b/bsp/gd32/gd32407v-start/project.uvoptx @@ -224,8 +224,8 @@ 0 0 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c + ..\..\..\libcpu\arm\common\div0.c + div0.c 0 0 @@ -236,8 +236,8 @@ 0 0 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c 0 0 @@ -304,8 +304,8 @@ 0 0 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c + ..\..\..\components\drivers\src\completion.c + completion.c 0 0 @@ -316,8 +316,8 @@ 0 0 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c + ..\..\..\components\drivers\src\workqueue.c + workqueue.c 0 0 @@ -328,8 +328,8 @@ 0 0 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c 0 0 @@ -352,8 +352,8 @@ 0 0 0 - ..\..\..\components\drivers\src\completion.c - completion.c + ..\..\..\components\drivers\src\pipe.c + pipe.c 0 0 @@ -364,8 +364,8 @@ 0 0 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c 0 0 @@ -376,8 +376,8 @@ 0 0 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c 0 0 @@ -385,7 +385,7 @@ Drivers - 1 + 0 0 0 0 @@ -440,7 +440,7 @@ - finsh + Finsh 0 0 0 @@ -452,8 +452,8 @@ 0 0 0 - ..\..\..\components\finsh\finsh_node.c - finsh_node.c + ..\..\..\components\finsh\shell.c + shell.c 0 0 @@ -464,143 +464,11 @@ 0 0 0 - ..\..\..\components\finsh\finsh_parser.c - finsh_parser.c - 0 - 0 - - - 5 - 22 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 5 - 23 - 1 - 0 - 0 - 0 ..\..\..\components\finsh\msh.c msh.c 0 0 - - 5 - 24 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\finsh_vm.c - finsh_vm.c - 0 - 0 - - - 5 - 25 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\shell.c - shell.c - 0 - 0 - - - 5 - 26 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\finsh_var.c - finsh_var.c - 0 - 0 - - - 5 - 27 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\finsh_compiler.c - finsh_compiler.c - 0 - 0 - - - 5 - 28 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\finsh_heap.c - finsh_heap.c - 0 - 0 - - - 5 - 29 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\finsh_ops.c - finsh_ops.c - 0 - 0 - - - 5 - 30 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\finsh_error.c - finsh_error.c - 0 - 0 - - - 5 - 31 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\finsh_token.c - finsh_token.c - 0 - 0 - - - 5 - 32 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\finsh_init.c - finsh_init.c - 0 - 0 - @@ -611,115 +479,115 @@ 0 6 - 33 + 22 1 0 0 0 - ..\..\..\src\thread.c - thread.c + ..\..\..\src\object.c + object.c 0 0 6 - 34 + 23 1 0 0 0 - ..\..\..\src\timer.c - timer.c + ..\..\..\src\irq.c + irq.c 0 0 6 - 35 + 24 1 0 0 0 - ..\..\..\src\clock.c - clock.c + ..\..\..\src\mempool.c + mempool.c 0 0 6 - 36 + 25 1 0 0 0 - ..\..\..\src\components.c - components.c + ..\..\..\src\timer.c + timer.c 0 0 6 - 37 + 26 1 0 0 0 - ..\..\..\src\device.c - device.c + ..\..\..\src\components.c + components.c 0 0 6 - 38 + 27 1 0 0 0 - ..\..\..\src\scheduler.c - scheduler.c + ..\..\..\src\kservice.c + kservice.c 0 0 6 - 39 + 28 1 0 0 0 - ..\..\..\src\mem.c - mem.c + ..\..\..\src\idle.c + idle.c 0 0 6 - 40 + 29 1 0 0 0 - ..\..\..\src\mempool.c - mempool.c + ..\..\..\src\mem.c + mem.c 0 0 6 - 41 + 30 1 0 0 0 - ..\..\..\src\idle.c - idle.c + ..\..\..\src\device.c + device.c 0 0 6 - 42 + 31 1 0 0 @@ -731,37 +599,37 @@ 6 - 43 + 32 1 0 0 0 - ..\..\..\src\kservice.c - kservice.c + ..\..\..\src\thread.c + thread.c 0 0 6 - 44 + 33 1 0 0 0 - ..\..\..\src\irq.c - irq.c + ..\..\..\src\clock.c + clock.c 0 0 6 - 45 + 34 1 0 0 0 - ..\..\..\src\object.c - object.c + ..\..\..\src\scheduler.c + scheduler.c 0 0 @@ -775,7 +643,7 @@ 0 7 - 46 + 35 1 0 0 @@ -795,7 +663,7 @@ 0 8 - 47 + 36 1 0 0 @@ -807,7 +675,7 @@ 8 - 48 + 37 1 0 0 @@ -819,7 +687,7 @@ 8 - 49 + 38 1 0 0 @@ -831,7 +699,7 @@ 8 - 50 + 39 1 0 0 @@ -843,7 +711,7 @@ 8 - 51 + 40 1 0 0 @@ -855,7 +723,7 @@ 8 - 52 + 41 1 0 0 @@ -867,7 +735,7 @@ 8 - 53 + 42 1 0 0 diff --git a/bsp/gd32/gd32407v-start/project.uvprojx b/bsp/gd32/gd32407v-start/project.uvprojx index 64c3b12177..bc6d9b4142 100644 --- a/bsp/gd32/gd32407v-start/project.uvprojx +++ b/bsp/gd32/gd32407v-start/project.uvprojx @@ -399,14 +399,14 @@ ..\..\..\libcpu\arm\common\showmem.c - backtrace.c + div0.c 1 - ..\..\..\libcpu\arm\common\backtrace.c + ..\..\..\libcpu\arm\common\div0.c - div0.c + backtrace.c 1 - ..\..\..\libcpu\arm\common\div0.c + ..\..\..\libcpu\arm\common\backtrace.c cpuport.c @@ -434,19 +434,19 @@ ..\..\..\components\drivers\serial\serial.c - ringblk_buf.c + completion.c 1 - ..\..\..\components\drivers\src\ringblk_buf.c + ..\..\..\components\drivers\src\completion.c - pipe.c + workqueue.c 1 - ..\..\..\components\drivers\src\pipe.c + ..\..\..\components\drivers\src\workqueue.c - waitqueue.c + dataqueue.c 1 - ..\..\..\components\drivers\src\waitqueue.c + ..\..\..\components\drivers\src\dataqueue.c ringbuffer.c @@ -454,19 +454,19 @@ ..\..\..\components\drivers\src\ringbuffer.c - completion.c + pipe.c 1 - ..\..\..\components\drivers\src\completion.c + ..\..\..\components\drivers\src\pipe.c - workqueue.c + waitqueue.c 1 - ..\..\..\components\drivers\src\workqueue.c + ..\..\..\components\drivers\src\waitqueue.c - dataqueue.c + ringblk_buf.c 1 - ..\..\..\components\drivers\src\dataqueue.c + ..\..\..\components\drivers\src\ringblk_buf.c @@ -496,72 +496,17 @@ - finsh + Finsh - - finsh_node.c - 1 - ..\..\..\components\finsh\finsh_node.c - - - finsh_parser.c - 1 - ..\..\..\components\finsh\finsh_parser.c - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - finsh_vm.c - 1 - ..\..\..\components\finsh\finsh_vm.c - shell.c 1 ..\..\..\components\finsh\shell.c - finsh_var.c - 1 - ..\..\..\components\finsh\finsh_var.c - - - finsh_compiler.c - 1 - ..\..\..\components\finsh\finsh_compiler.c - - - finsh_heap.c - 1 - ..\..\..\components\finsh\finsh_heap.c - - - finsh_ops.c - 1 - ..\..\..\components\finsh\finsh_ops.c - - - finsh_error.c - 1 - ..\..\..\components\finsh\finsh_error.c - - - finsh_token.c - 1 - ..\..\..\components\finsh\finsh_token.c - - - finsh_init.c + msh.c 1 - ..\..\..\components\finsh\finsh_init.c + ..\..\..\components\finsh\msh.c @@ -569,19 +514,24 @@ Kernel - thread.c + object.c 1 - ..\..\..\src\thread.c + ..\..\..\src\object.c - timer.c + irq.c 1 - ..\..\..\src\timer.c + ..\..\..\src\irq.c - clock.c + mempool.c 1 - ..\..\..\src\clock.c + ..\..\..\src\mempool.c + + + timer.c + 1 + ..\..\..\src\timer.c components.c @@ -589,14 +539,14 @@ ..\..\..\src\components.c - device.c + kservice.c 1 - ..\..\..\src\device.c + ..\..\..\src\kservice.c - scheduler.c + idle.c 1 - ..\..\..\src\scheduler.c + ..\..\..\src\idle.c mem.c @@ -604,14 +554,9 @@ ..\..\..\src\mem.c - mempool.c - 1 - ..\..\..\src\mempool.c - - - idle.c + device.c 1 - ..\..\..\src\idle.c + ..\..\..\src\device.c ipc.c @@ -619,19 +564,19 @@ ..\..\..\src\ipc.c - kservice.c + thread.c 1 - ..\..\..\src\kservice.c + ..\..\..\src\thread.c - irq.c + clock.c 1 - ..\..\..\src\irq.c + ..\..\..\src\clock.c - object.c + scheduler.c 1 - ..\..\..\src\object.c + ..\..\..\src\scheduler.c diff --git a/bsp/gd32/libraries/HAL_Drivers/Kconfig b/bsp/gd32/libraries/HAL_Drivers/Kconfig index 41cf5cf08b..93e9ecd88f 100644 --- a/bsp/gd32/libraries/HAL_Drivers/Kconfig +++ b/bsp/gd32/libraries/HAL_Drivers/Kconfig @@ -24,39 +24,3 @@ if BSP_USING_USBD # "ULPI: UTMI+ Low Pin Interface" endif -config BSP_USING_CRC - bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)" - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_CRC - # "Crypto device frame dose not support above 8-bits granularity" - # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4" - depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1) - default n - -config BSP_USING_RNG - bool "Enable RNG (Random Number Generator)" - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_RNG - depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \ - SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1) - default n - -config BSP_USING_HASH - bool "Enable HASH (Hash House Harriers)" - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_HASH - depends on (SOC_SERIES_STM32MP1) - default n - -config BSP_USING_CRYP - bool "Enable CRYP (Encrypt And Decrypt Data)" - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_CRYP - depends on (SOC_SERIES_STM32MP1) - default n - -config BSP_USING_UDID - bool "Enable UDID (Unique Device Identifier)" - select RT_USING_HWCRYPTO - default n - diff --git a/bsp/gd32/libraries/HAL_Drivers/drv_gpio.c b/bsp/gd32/libraries/HAL_Drivers/drv_gpio.c index 1fc7339643..3ff4282c82 100644 --- a/bsp/gd32/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/gd32/libraries/HAL_Drivers/drv_gpio.c @@ -156,7 +156,7 @@ const struct pin_index *get_pin(rt_uint8_t pin) return index; }; -void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { const struct pin_index *index = RT_NULL; rt_uint32_t pin_mode = 0, pin_pupd = 0, pin_odpp = 0; @@ -211,7 +211,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) } } -void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { const struct pin_index *index = RT_NULL; @@ -224,7 +224,7 @@ void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); } -int gd32_pin_read(rt_device_t dev, rt_base_t pin) +static int _pin_read(rt_device_t dev, rt_base_t pin) { int value = PIN_LOW; const struct pin_index *index = RT_NULL; @@ -262,7 +262,7 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) return &pin_irq_map[map_index]; }; -rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, +static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) { const struct pin_index *index = RT_NULL; @@ -272,13 +272,13 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return -RT_EINVAL; } hdr_index = bit2bitno(index->pin); if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) { - return RT_EINVAL; + return -RT_EINVAL; } level = rt_hw_interrupt_disable(); @@ -293,7 +293,7 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, if (pin_irq_hdr_tab[hdr_index].pin != -1) { rt_hw_interrupt_enable(level); - return RT_EFULL; + return -RT_EFULL; } pin_irq_hdr_tab[hdr_index].pin = pin; pin_irq_hdr_tab[hdr_index].hdr = hdr; @@ -304,7 +304,7 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, return RT_EOK; } -rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin) { const struct pin_index *index = RT_NULL; rt_base_t level; @@ -313,13 +313,13 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return -RT_EINVAL; } hdr_index = bit2bitno(index->pin); if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) { - return RT_EINVAL; + return -RT_EINVAL; } level = rt_hw_interrupt_disable(); @@ -337,7 +337,7 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) return RT_EOK; } -rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) { const struct pin_index *index; const struct pin_irq_map *irqmap; @@ -348,7 +348,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return -RT_EINVAL; } if (enabled == PIN_IRQ_ENABLE) @@ -356,14 +356,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ hdr_index = bit2bitno(index->pin); if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) { - return RT_EINVAL; + return -RT_EINVAL; } level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[hdr_index].pin == -1) { rt_hw_interrupt_enable(level); - return RT_EINVAL; + return -RT_EINVAL; } irqmap = &pin_irq_map[hdr_index]; @@ -381,7 +381,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ break; default: rt_hw_interrupt_enable(level); - return RT_EINVAL; + return -RT_EINVAL; } rcu_periph_clock_enable(RCU_SYSCFG); @@ -403,13 +403,13 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ irqmap = get_pin_irq_map(index->pin); if (irqmap == RT_NULL) { - return RT_EINVAL; + return -RT_EINVAL; } nvic_irq_disable(irqmap->irqno); } else { - return RT_EINVAL; + return -RT_EINVAL; } return RT_EOK; @@ -417,12 +417,12 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ const static struct rt_pin_ops gd32_pin_ops = { - gd32_pin_mode, - gd32_pin_write, - gd32_pin_read, - gd32_pin_attach_irq, - gd32_pin_detach_irq, - gd32_pin_irq_enable, + _pin_mode, + _pin_write, + _pin_read, + _pin_attach_irq, + _pin_detach_irq, + _pin_irq_enable, RT_NULL, }; diff --git a/bsp/gd32/libraries/HAL_Drivers/drv_usart.c b/bsp/gd32/libraries/HAL_Drivers/drv_usart.c index 283eb47de3..54a36d6f73 100644 --- a/bsp/gd32/libraries/HAL_Drivers/drv_usart.c +++ b/bsp/gd32/libraries/HAL_Drivers/drv_usart.c @@ -304,7 +304,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart) NVIC_EnableIRQ(uart->irqn); } -static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct gd32_uart *uart; @@ -358,7 +358,7 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co return RT_EOK; } -static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg) +static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) { struct gd32_uart *uart; @@ -385,7 +385,7 @@ static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg return RT_EOK; } -static int gd32_putc(struct rt_serial_device *serial, char ch) +static int _uart_putc(struct rt_serial_device *serial, char ch) { struct gd32_uart *uart; @@ -395,10 +395,10 @@ static int gd32_putc(struct rt_serial_device *serial, char ch) usart_data_transmit(uart->uart_periph, ch); while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - return 1; + return RT_EOK; } -static int gd32_getc(struct rt_serial_device *serial) +static int _uart_getc(struct rt_serial_device *serial) { int ch; struct gd32_uart *uart; @@ -435,10 +435,10 @@ static void uart_isr(struct rt_serial_device *serial) static const struct rt_uart_ops gd32_uart_ops = { - gd32_configure, - gd32_control, - gd32_putc, - gd32_getc, + _uart_configure, + _uart_control, + _uart_putc, + _uart_getc, }; int gd32_hw_usart_init(void) @@ -446,6 +446,7 @@ int gd32_hw_usart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; int i; + int result; for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { @@ -453,13 +454,14 @@ int gd32_hw_usart_init(void) uarts[i].serial->config = config; /* register UART1 device */ - rt_hw_serial_register(uarts[i].serial, + result = rt_hw_serial_register(uarts[i].serial, uarts[i].device_name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, (void *)&uarts[i]); + RT_ASSERT(result == RT_EOK); } - return 0; + return result; } INIT_BOARD_EXPORT(gd32_hw_usart_init); #endif -- GitLab