diff --git a/libcpu/arm/lm3s/context_gcc.S b/libcpu/arm/lm3s/context_gcc.S
index 04d45c132756be9d703aecb076e2dff244d84601..e4a0a3e68cf36866e5ed6e6875fbeb54c55cf6e0 100644
--- a/libcpu/arm/lm3s/context_gcc.S
+++ b/libcpu/arm/lm3s/context_gcc.S
@@ -146,7 +146,9 @@ rt_hw_context_switch_to:
 	/* set the PendSV exception priority */
 	LDR		r0, =NVIC_SYSPRI2
 	LDR		r1, =NVIC_PENDSV_PRI
-	STR		r1, [r0]
+	LDR.W   R2, [r0,#0x00]          ; read
+	ORR     r1,r1,r2                ; modify
+    STR     r1, [r0]                ; write-bak
 
 	LDR		r0, =NVIC_INT_CTRL      /* trigger the PendSV exception (causes context switch) */
 	LDR		r1, =NVIC_PENDSVSET
diff --git a/libcpu/arm/lm3s/context_rvds.S b/libcpu/arm/lm3s/context_rvds.S
index 5eab028ee4b8c199edcb4cc22fd86e839fa7b246..6432965f575e764c9cd42e8c07755f6db17380a9 100644
--- a/libcpu/arm/lm3s/context_rvds.S
+++ b/libcpu/arm/lm3s/context_rvds.S
@@ -155,7 +155,9 @@ rt_hw_context_switch_to    PROC
 	; trigger the PendSV exception (causes context switch)
 	LDR		r0, =NVIC_INT_CTRL
 	LDR		r1, =NVIC_PENDSVSET
-	STR		r1, [r0]
+	LDR.W   R2, [r0,#0x00]          ; read
+	ORR     r1,r1,r2                ; modify
+    STR     r1, [r0]                ; write-bak
 
 	; enable interrupts at processor level
 	CPSIE		I
diff --git a/libcpu/arm/lpc17xx/context_iar.S b/libcpu/arm/lpc17xx/context_iar.S
index 70ab59d362881a8c32e7b4bb78a4231097602696..3c8f2d35999467ad5436eca1cab6bb8e30f227a1 100644
--- a/libcpu/arm/lpc17xx/context_iar.S
+++ b/libcpu/arm/lpc17xx/context_iar.S
@@ -148,7 +148,9 @@ rt_hw_context_switch_to:
 	; set the PendSV exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
-    STR     r1, [r0]
+	LDR.W   R2, [r0,#0x00]          ; read
+	ORR     r1,r1,r2                ; modify
+    STR     r1, [r0]                ; write-bak
 
 	; trigger the PendSV exception (causes context switch)
     LDR     r0, =NVIC_INT_CTRL
diff --git a/libcpu/arm/lpc17xx/context_rvds.S b/libcpu/arm/lpc17xx/context_rvds.S
index 0ffeb59c7e5704f0c043e5b57eafd4cb8bdc7ff7..b59c5da3da7f03225f351276b69f91609e9fb86c 100644
--- a/libcpu/arm/lpc17xx/context_rvds.S
+++ b/libcpu/arm/lpc17xx/context_rvds.S
@@ -150,7 +150,9 @@ rt_hw_context_switch_to    PROC
 	; set the PendSV exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
-    STR     r1, [r0]
+	LDR.W   R2, [r0,#0x00]          ; read
+	ORR     r1,r1,r2                ; modify
+    STR     r1, [r0]                ; write-bak
 
 	; trigger the PendSV exception (causes context switch)
     LDR     r0, =NVIC_INT_CTRL
diff --git a/libcpu/arm/s3c24x0/start_rvds.S b/libcpu/arm/s3c24x0/start_rvds.S
index fe194148e9424208e80e13326b5a8821ea0611bc..5ca6f94022b58f406b2ee36fda701cd23ecbe961 100644
--- a/libcpu/arm/s3c24x0/start_rvds.S
+++ b/libcpu/arm/s3c24x0/start_rvds.S
@@ -498,7 +498,7 @@ GPDAT_OFS       EQU     0x04            ; Data Register Offset
 GPUP_OFS        EQU     0x08            ; Pull-up Disable Register Offset
 
 ;// <e> I/O Setup
-GP_SETUP        EQU     0
+GP_SETUP        EQU     1
 
 ;//   <e> Port A Settings
 ;//     <h> Port A Control Register (GPACON)
@@ -710,9 +710,9 @@ GPEUP_Val       EQU     0x00000000
 ;//       <o2.0>      GPF0  Pull-up Disable
 ;//     </h>
 ;//   </e>
-GPF_SETUP       EQU     0
-GPFCON_Val      EQU     0x00000000
-GPFUP_Val       EQU     0x00000000
+GPF_SETUP       EQU     1
+GPFCON_Val      EQU     0x000000AA
+GPFUP_Val       EQU     0x0000000F
 
 ;//   <e> Port G Settings
 ;//     <h> Port G Control Register (GPGCON)
@@ -866,10 +866,34 @@ FIQ_Addr        DCD     FIQ_Handler
 Undef_Handler   B       Undef_Handler
 SWI_Handler     B       SWI_Handler
 PAbt_Handler    B       PAbt_Handler
-DAbt_Handler    B       DAbt_Handler
+;DAbt_Handler    B       DAbt_Handler
 FIQ_Handler     B       FIQ_Handler
 
-
+;*
+;*************************************************************************
+;*
+;* Interrupt handling
+;*
+;*************************************************************************
+;*
+; DAbt Handler
+DAbt_Handler
+               IMPORT rt_hw_trap_dabt
+
+                	sub 	sp, sp, #72
+	                stmia 	sp, {r0 - r12}   		;/* Calling r0-r12					*/
+                    add		r8, sp, #60
+	                stmdb   r8, {sp, lr}            ;/* Calling SP, LR					*/
+	                str		lr, [r8, #0]            ;/* Save calling PC					*/
+	                mrs		r6, spsr
+	                str		r6, [r8, #4]            ;/* Save CPSR						*/
+	                str		r0, [r8, #8]            ;/* Save OLD_R0						*/
+	                mov		r0, sp
+
+	                bl 		rt_hw_trap_dabt
+
+
+;##########################################
 ; Reset Handler
 
                 EXPORT  Reset_Handler