From 153b03f310b6dfd2faa9765d4b4007a6f651e193 Mon Sep 17 00:00:00 2001 From: supperthomas <78900636@qq.com> Date: Thu, 11 Feb 2021 16:18:33 +0800 Subject: [PATCH] [bsp/max32660] add the keil project --- bsp/maxim/MAX32660_EVSYS/.config | 47 +- bsp/maxim/MAX32660_EVSYS/SConstruct | 4 +- .../MAX32660_EVSYS/applications/application.c | 4 +- bsp/maxim/MAX32660_EVSYS/board/Kconfig | 31 +- bsp/maxim/MAX32660_EVSYS/board/SConscript | 29 +- bsp/maxim/MAX32660_EVSYS/board/app_config.h | 4 - bsp/maxim/MAX32660_EVSYS/board/board.c | 3 +- bsp/maxim/MAX32660_EVSYS/board/fal_cfg.h | 82 - .../board/linker_scripts/link.lds | 104 +- bsp/maxim/MAX32660_EVSYS/project.uvoptx | 601 +- bsp/maxim/MAX32660_EVSYS/project.uvprojx | 213 +- bsp/maxim/MAX32660_EVSYS/rtconfig.h | 58 +- bsp/maxim/MAX32660_EVSYS/rtconfig.py | 72 +- bsp/maxim/MAX32660_EVSYS/template.uvoptx | 2 +- bsp/maxim/MAX32660_EVSYS/template.uvprojx | 12 +- bsp/maxim/libraries/HAL_Drivers/SConscript | 34 + .../HAL_Drivers}/drv_uart.c | 9 +- .../HAL_Drivers}/drv_usart.h | 0 .../CMSIS/Core/Include}/RTE_Components.h | 2 +- .../CMSIS/Core/Include/cachel1_armv7.h | 411 + .../CMSIS/Core/Include}/cmsis_armcc.h | 0 .../CMSIS/Core/Include}/cmsis_armclang.h | 0 .../CMSIS/Core/Include}/cmsis_armclang_ltm.h | 0 .../CMSIS/Core/Include}/cmsis_compiler.h | 0 .../CMSIS/Core/Include/cmsis_gcc.h | 2177 ++++ .../CMSIS/Core/Include/cmsis_iccarm.h | 968 ++ .../CMSIS/Core/Include}/cmsis_version.h | 0 .../CMSIS/Core/Include/core_armv81mml.h | 4191 ++++++ .../CMSIS/Core/Include/core_armv8mbl.h | 2222 ++++ .../CMSIS/Core/Include/core_armv8mml.h | 3196 +++++ .../CMSIS/Core/Include}/core_cm4.h | 0 .../CMSIS/Core/Include/core_sc000.h | 1030 ++ .../CMSIS/Core/Include/core_sc300.h | 1917 +++ .../CMSIS/Core/Include}/mpu_armv7.h | 0 .../CMSIS/Core/Include/mpu_armv8.h | 352 + .../CMSIS/Core/Include/pmu_armv8.h | 337 + .../CMSIS/Core/Include/tz_context.h | 70 + .../Device/Maxim/MAX32660/Include/bbfc_regs.h | 127 + .../Maxim/MAX32660/Include/bbsir_regs.h | 111 + .../Device/Maxim/MAX32660/Include/dma_regs.h | 470 + .../Device/Maxim/MAX32660/Include/flc_regs.h | 264 + .../Device/Maxim/MAX32660/Include/gcr_regs.h | 769 ++ .../Device/Maxim/MAX32660/Include/gpio_regs.h | 663 + .../Device/Maxim/MAX32660/Include/i2c_regs.h | 843 ++ .../Device/Maxim/MAX32660/Include/icc_regs.h | 167 + .../Device/Maxim/MAX32660/Include}/max32660.h | 0 .../Maxim/MAX32660/Include/max32660.svd | 10650 ++++++++++++++++ .../Maxim/MAX32660/Include/mxc_device.h} | 51 +- .../Maxim/MAX32660/Include/pwrseq_regs.h | 273 + .../Device/Maxim/MAX32660/Include/rtc_regs.h | 297 + .../Device/Maxim/MAX32660/Include/sir_regs.h | 255 + .../Device/Maxim/MAX32660/Include/smon_regs.h | 628 + .../Maxim/MAX32660/Include/spi17y_regs.h | 664 + .../Maxim/MAX32660/Include/spimss_regs.h | 496 + .../Maxim/MAX32660/Include}/system_max32660.h | 0 .../Device/Maxim/MAX32660/Include/tmr_regs.h | 233 + .../Device/Maxim/MAX32660/Include/uart_regs.h | 450 + .../Device/Maxim/MAX32660/Include/wdt_regs.h | 236 + .../MAX32660/Source/ARM}/startup_max32660.s | 0 .../Device/Maxim/MAX32660/Source/GCC/gcc.mk | 391 + .../Maxim/MAX32660/Source/GCC/max32660.ld | 131 + .../Maxim/MAX32660/Source/GCC/max32660.mk} | 68 +- .../MAX32660/Source/GCC/max32660_emulator.ld | 131 + .../Source/GCC/max32660_emulator_ram.ld | 132 + .../Maxim/MAX32660/Source/GCC/max32660_ram.ld | 132 + .../Maxim/MAX32660/Source/GCC/max32660_sbl.ld | 271 + .../MAX32660/Source/GCC/startup_max32660.S | 314 + .../Device/Maxim/MAX32660/Source/IAR/cmain.s | 79 + .../MAX32660/Source/IAR/low_level_init.c | 50 + .../MAX32660/Source/IAR/startup_max32660.s | 480 + .../CMSIS/Device/Maxim/MAX32660/Source/heap.c | 77 + .../Maxim/MAX32660/Source}/system_max32660.c | 0 .../libraries/MAX32660PeriphDriver/SConscript | 50 + 73 files changed, 37384 insertions(+), 751 deletions(-) delete mode 100644 bsp/maxim/MAX32660_EVSYS/board/app_config.h delete mode 100644 bsp/maxim/MAX32660_EVSYS/board/fal_cfg.h create mode 100644 bsp/maxim/libraries/HAL_Drivers/SConscript rename bsp/maxim/{MAX32660_EVSYS/applications => libraries/HAL_Drivers}/drv_uart.c (98%) rename bsp/maxim/{MAX32660_EVSYS/applications => libraries/HAL_Drivers}/drv_usart.h (100%) rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Core/Include}/RTE_Components.h (85%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cachel1_armv7.h rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Core/Include}/cmsis_armcc.h (100%) rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Core/Include}/cmsis_armclang.h (100%) rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Core/Include}/cmsis_armclang_ltm.h (100%) rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Core/Include}/cmsis_compiler.h (100%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_gcc.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_iccarm.h rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Core/Include}/cmsis_version.h (100%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv81mml.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv8mbl.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv8mml.h rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Core/Include}/core_cm4.h (100%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_sc000.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_sc300.h rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Core/Include}/mpu_armv7.h (100%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/mpu_armv8.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/pmu_armv8.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/tz_context.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbfc_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbsir_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include}/max32660.h (100%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.svd rename bsp/maxim/libraries/{CMSIS/mxc_config.h => MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/mxc_device.h} (69%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/smon_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spi17y_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include}/system_max32660.h (100%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM}/startup_max32660.s (100%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/gcc.mk create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.ld rename bsp/maxim/libraries/MAX32660PeriphDriver/{periphdriver.mk => CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.mk} (59%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator.ld create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator_ram.ld create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_ram.ld create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_sbl.ld create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/cmain.s create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/low_level_init.c create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/startup_max32660.s create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/heap.c rename bsp/maxim/libraries/{CMSIS => MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source}/system_max32660.c (100%) create mode 100644 bsp/maxim/libraries/MAX32660PeriphDriver/SConscript diff --git a/bsp/maxim/MAX32660_EVSYS/.config b/bsp/maxim/MAX32660_EVSYS/.config index ab3a8da17a..76a58dd3d9 100644 --- a/bsp/maxim/MAX32660_EVSYS/.config +++ b/bsp/maxim/MAX32660_EVSYS/.config @@ -64,7 +64,9 @@ CONFIG_RT_USING_HEAP=y CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set -# CONFIG_RT_USING_CONSOLE is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x40003 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -72,8 +74,10 @@ CONFIG_RT_VER_NUM=0x40003 # # RT-Thread Components # -# CONFIG_RT_USING_COMPONENTS_INIT is not set -# CONFIG_RT_USING_USER_MAIN is not set +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -83,7 +87,21 @@ CONFIG_RT_VER_NUM=0x40003 # # Command shell # -# CONFIG_RT_USING_FINSH is not set +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system @@ -97,14 +115,14 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PIN is not set # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set @@ -132,9 +150,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set +# CONFIG_RT_LIBC_USING_TIME is not set # # Network @@ -362,11 +380,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LITTLED is not set # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set -CONFIG_PKG_USING_NRFX=y -CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx" -CONFIG_PKG_USING_NRFX_V210=y -# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set -CONFIG_PKG_NRFX_VER="v2.1.0" +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set @@ -458,10 +472,15 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # # Hardware Drivers Config # +CONFIG_SOC_MAX32660=y CONFIG_SOC_MAXIM=y # # On-chip Peripheral Drivers # -CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_GPIO is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART0 is not set +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set diff --git a/bsp/maxim/MAX32660_EVSYS/SConstruct b/bsp/maxim/MAX32660_EVSYS/SConstruct index b0bdaf958d..8923a6dc8b 100644 --- a/bsp/maxim/MAX32660_EVSYS/SConstruct +++ b/bsp/maxim/MAX32660_EVSYS/SConstruct @@ -48,10 +48,10 @@ print(SDK_LIB) objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # include drivers -#objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) # include cmsis -#objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript'))) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'MAX32660PeriphDriver', 'SConscript'))) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/maxim/MAX32660_EVSYS/applications/application.c b/bsp/maxim/MAX32660_EVSYS/applications/application.c index 91f9ccf91e..2ae592d99b 100644 --- a/bsp/maxim/MAX32660_EVSYS/applications/application.c +++ b/bsp/maxim/MAX32660_EVSYS/applications/application.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-04-29 supperthomas first version + * 2021-02-11 supperthomas first version * */ @@ -29,4 +29,4 @@ int main(void) GPIO_OutToggle(&led_pin[0]); } return RT_EOK; -} \ No newline at end of file +} diff --git a/bsp/maxim/MAX32660_EVSYS/board/Kconfig b/bsp/maxim/MAX32660_EVSYS/board/Kconfig index 26d0dd025d..924b74f04c 100644 --- a/bsp/maxim/MAX32660_EVSYS/board/Kconfig +++ b/bsp/maxim/MAX32660_EVSYS/board/Kconfig @@ -5,7 +5,10 @@ config SOC_MAX32660 config SOC_MAX32660 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN - + select BSP_USING_UART + select BSP_USING_UART1 + default y + config SOC_MAXIM bool config SOC_MAXIM @@ -16,11 +19,35 @@ menu "On-chip Peripheral Drivers" bool "Enable GPIO" select RT_USING_PIN default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + endif config BSP_USING_ON_CHIP_FLASH select PKG_USING_FAL bool "Enable on-chip FLASH" default n - + endmenu diff --git a/bsp/maxim/MAX32660_EVSYS/board/SConscript b/bsp/maxim/MAX32660_EVSYS/board/SConscript index 27bcddd310..f2844f9ef6 100644 --- a/bsp/maxim/MAX32660_EVSYS/board/SConscript +++ b/bsp/maxim/MAX32660_EVSYS/board/SConscript @@ -1,11 +1,28 @@ -Import('RTT_ROOT') -Import('rtconfig') +import os +import rtconfig from building import * +Import('SDK_LIB') + cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] -define = ['USE_APP_CONFIG'] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define) +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s'] + + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + Return('group') diff --git a/bsp/maxim/MAX32660_EVSYS/board/app_config.h b/bsp/maxim/MAX32660_EVSYS/board/app_config.h deleted file mode 100644 index 7909dd55b4..0000000000 --- a/bsp/maxim/MAX32660_EVSYS/board/app_config.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef APP_CONFIG_H -#define APP_CONFIG_H - -#endif //APP_CONFIG_H diff --git a/bsp/maxim/MAX32660_EVSYS/board/board.c b/bsp/maxim/MAX32660_EVSYS/board/board.c index d89d2fd166..fc9ff80ad2 100644 --- a/bsp/maxim/MAX32660_EVSYS/board/board.c +++ b/bsp/maxim/MAX32660_EVSYS/board/board.c @@ -5,9 +5,10 @@ * * Change Logs: * Date Author Notes - * 2020-04-29 supperthomas first version + * 2021-02-11 supperthomas first version * */ + #include #include #include diff --git a/bsp/maxim/MAX32660_EVSYS/board/fal_cfg.h b/bsp/maxim/MAX32660_EVSYS/board/fal_cfg.h deleted file mode 100644 index 42611e0c13..0000000000 --- a/bsp/maxim/MAX32660_EVSYS/board/fal_cfg.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-05-05 supperthomas this is sample you can change by yourself - * - */ - -#ifndef _FAL_CFG_H_ -#define _FAL_CFG_H_ - -#include -#include - -#if (defined(BSP_USING_QSPI_FLASH)&&defined(BSP_USING_ON_CHIP_FLASH)) - -#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip" -#define NOR_FLASH_DEV_NAME "norflash0" - -extern const struct fal_flash_dev mcu_onchip_flash; -extern struct fal_flash_dev nor_flash0; - -/* flash device table */ -#define FAL_FLASH_DEV_TABLE \ - { \ - &mcu_onchip_flash, \ - &nor_flash0, \ - } -/* ====================== Partition Configuration ========================== */ -#ifdef FAL_PART_HAS_TABLE_CFG -/* partition table */ -#define FAL_PART_TABLE \ - { \ - {FAL_PART_MAGIC_WORD, "bl", ON_CHIP_FLASH_DEV_NAME, 0, 64*1024, 0}, \ - {FAL_PART_MAGIC_WORD, "app_flash", ON_CHIP_FLASH_DEV_NAME, 64*1024, 960*1024, 0}, \ - {FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME, 0, 1024*1024, 0}, \ - {FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \ - } -#endif /* FAL_PART_HAS_TABLE_CFG */ - -#elif defined(BSP_USING_QSPI_FLASH) - -#define NOR_FLASH_DEV_NAME "norflash0" -extern struct fal_flash_dev nor_flash0; - -/* flash device table */ -#define FAL_FLASH_DEV_TABLE \ - { \ - &nor_flash0, \ - } -/* ====================== Partition Configuration ========================== */ -#ifdef FAL_PART_HAS_TABLE_CFG -/* partition table */ -#define FAL_PART_TABLE \ - { \ - {FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME, 0, 1024*1024, 0}, \ - {FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \ - } -#endif -#elif defined(BSP_USING_ON_CHIP_FLASH) -extern const struct fal_flash_dev mcu_onchip_flash; -#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip" -/* flash device table */ -#define FAL_FLASH_DEV_TABLE \ - { \ - &mcu_onchip_flash, \ - } -/* ====================== Partition Configuration ========================== */ -#ifdef FAL_PART_HAS_TABLE_CFG -/* partition table */ -#define FAL_PART_TABLE \ - { \ - {FAL_PART_MAGIC_WORD, "bl", ON_CHIP_FLASH_DEV_NAME, 0, 64*1024, 0}, \ - {FAL_PART_MAGIC_WORD, "app_flash", ON_CHIP_FLASH_DEV_NAME, 64*1024, 960*1024, 0}, \ - } -#endif -#endif - -#endif /* _FAL_CFG_H_ */ diff --git a/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds b/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds index 9a9609eed7..8931956648 100644 --- a/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds +++ b/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds @@ -1,16 +1,102 @@ /* Linker script to configure memory regions. */ -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 - CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x10000 +MEMORY { + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + + +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") } -INCLUDE "packages/nrfx-v2.1.0/mdk/nrf_common.ld" diff --git a/bsp/maxim/MAX32660_EVSYS/project.uvoptx b/bsp/maxim/MAX32660_EVSYS/project.uvoptx index 678baff318..4d389bdf18 100644 --- a/bsp/maxim/MAX32660_EVSYS/project.uvoptx +++ b/bsp/maxim/MAX32660_EVSYS/project.uvoptx @@ -26,7 +26,7 @@ 0x4 ARM-ADS - 12000000 + 96000000 1 1 @@ -117,26 +117,6 @@ BIN\CMSIS_AGDI.dll - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - - 0 CMSIS_AGDI @@ -148,144 +128,19 @@ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MAX32660 -FL040000 -FS00 -FP0($$Device:MAX32660$Flash\MAX32660.FLM) - - - 0 - 0 - 221 - 1 -
7494
- 0 - 0 - 0 - 0 - 0 - 1 - .\applications\drv_uart.c - - \\rtthread\applications/drv_uart.c\221 - - - 1 - 0 - 108 - 1 -
7106
- 0 - 0 - 0 - 0 - 0 - 1 - .\applications\drv_uart.c - - \\rtthread\applications/drv_uart.c\108 - - - 2 - 0 - 91 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\applications\drv_uart.c - - - - - 3 - 0 - 92 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\applications\drv_uart.c - - - - - 4 - 0 - 206 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\applications\drv_uart.c - - - - - 5 - 0 - 209 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\applications\drv_uart.c - - - - - 6 - 0 - 220 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\applications\drv_uart.c - - - - - - - 0 - 1 - oflag - - - 1 - 1 - flag - - + 0 0 0 - 1 + 0 0 0 0 0 - 1 + 0 0 0 0 @@ -316,12 +171,6 @@ - - - System Viewer\UART1 - 35905 - - 1 1 @@ -350,213 +199,233 @@ 0 0 + + + + CPU + 1 + 0 + 0 + 0 - 1 + 2 2 1 0 0 0 - ..\libraries\CMSIS\system_max32660.c - system_max32660.c + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c 0 0 - 1 + 2 3 - 2 + 1 0 0 0 - ..\libraries\CMSIS\startup_max32660.s - startup_max32660.s + ..\..\..\libcpu\arm\common\div0.c + div0.c 0 0 - 1 + 2 4 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c - mxc_sys.c + ..\..\..\libcpu\arm\common\showmem.c + showmem.c 0 0 - 1 + 2 5 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c - mxc_assert.c + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c 0 0 - 1 + 2 6 - 1 + 2 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c - mxc_delay.c + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S 0 0 + + + + DeviceDrivers + 1 + 0 + 0 + 0 - 1 + 3 7 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\mxc_lock.c - mxc_lock.c + ..\..\..\components\drivers\serial\serial.c + serial.c 0 0 - 1 + 3 8 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\mxc_pins.c - mxc_pins.c + ..\..\..\components\drivers\src\completion.c + completion.c 0 0 - 1 + 3 9 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\nvic_table.c - nvic_table.c + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c 0 0 - 1 + 3 10 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\flc.c - flc.c + ..\..\..\components\drivers\src\pipe.c + pipe.c 0 0 - 1 + 3 11 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\icc.c - icc.c + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c 0 0 - 1 + 3 12 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\lp.c - lp.c + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c 0 0 - 1 + 3 13 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\gpio.c - gpio.c + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c 0 0 - 1 + 3 14 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\rtc.c - rtc.c + ..\..\..\components\drivers\src\workqueue.c + workqueue.c 0 0 + + + + Drivers + 1 + 0 + 0 + 0 - 1 + 4 15 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\tmr.c - tmr.c + board\board.c + board.c 0 0 - 1 + 4 16 - 1 + 2 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\tmr_utils.c - tmr_utils.c + ..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\ARM\startup_max32660.s + startup_max32660.s 0 0 - 1 + 4 17 1 0 0 0 - ..\libraries\MAX32660PeriphDriver\Source\uart.c - uart.c - 0 - 0 - - - 1 - 18 - 1 - 0 - 0 - 0 - .\applications\drv_uart.c + ..\libraries\HAL_Drivers\drv_uart.c drv_uart.c 0 0 + + + + finsh + 0 + 0 + 0 + 0 - 1 - 19 + 5 + 18 1 0 0 @@ -567,8 +436,8 @@ 0 - 1 - 20 + 5 + 19 1 0 0 @@ -579,8 +448,8 @@ 0 - 1 - 21 + 5 + 20 1 0 0 @@ -593,424 +462,340 @@ - CPU - 1 + Kernel + 0 0 0 0 - 2 + 6 + 21 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 22 1 0 0 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c + ..\..\..\src\components.c + components.c 0 0 - 2 + 6 23 1 0 0 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c + ..\..\..\src\device.c + device.c 0 0 - 2 + 6 24 1 0 0 0 - ..\..\..\libcpu\arm\common\showmem.c - showmem.c + ..\..\..\src\idle.c + idle.c 0 0 - 2 + 6 25 1 0 0 0 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c - cpuport.c + ..\..\..\src\ipc.c + ipc.c 0 0 - 2 + 6 26 - 2 + 1 0 0 0 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - context_rvds.S + ..\..\..\src\irq.c + irq.c 0 0 - - - - DeviceDrivers - 1 - 0 - 0 - 0 - 3 + 6 27 1 0 0 0 - ..\..\..\components\drivers\misc\pin.c - pin.c + ..\..\..\src\kservice.c + kservice.c 0 0 - 3 + 6 28 1 0 0 0 - ..\..\..\components\drivers\serial\serial.c - serial.c + ..\..\..\src\mem.c + mem.c 0 0 - 3 + 6 29 1 0 0 0 - ..\..\..\components\drivers\src\completion.c - completion.c + ..\..\..\src\mempool.c + mempool.c 0 0 - 3 + 6 30 1 0 0 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c + ..\..\..\src\object.c + object.c 0 0 - 3 + 6 31 1 0 0 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c + ..\..\..\src\scheduler.c + scheduler.c 0 0 - 3 + 6 32 1 0 0 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c + ..\..\..\src\thread.c + thread.c 0 0 - 3 + 6 33 1 0 0 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c + ..\..\..\src\timer.c + timer.c 0 0 + + + + Libraries + 1 + 0 + 0 + 0 - 3 + 7 34 1 0 0 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c + ..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\system_max32660.c + system_max32660.c 0 0 - 3 + 7 35 1 0 0 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c + ..\libraries\MAX32660PeriphDriver\Source\gpio.c + gpio.c 0 0 - - - - Drivers - 1 - 0 - 0 - 0 - 4 + 7 36 1 0 0 0 - board\board.c - board.c + ..\libraries\MAX32660PeriphDriver\Source\lp.c + lp.c 0 0 - - - - Kernel - 1 - 0 - 0 - 0 - 5 + 7 37 1 0 0 0 - ..\..\..\src\clock.c - clock.c + ..\libraries\MAX32660PeriphDriver\Source\tmr.c + tmr.c 0 0 - 5 + 7 38 1 0 0 0 - ..\..\..\src\components.c - components.c + ..\libraries\MAX32660PeriphDriver\Source\tmr_utils.c + tmr_utils.c 0 0 - 5 + 7 39 1 0 0 0 - ..\..\..\src\device.c - device.c + ..\libraries\MAX32660PeriphDriver\Source\rtc.c + rtc.c 0 0 - 5 + 7 40 1 0 0 0 - ..\..\..\src\idle.c - idle.c + ..\libraries\MAX32660PeriphDriver\Source\icc.c + icc.c 0 0 - 5 + 7 41 1 0 0 0 - ..\..\..\src\ipc.c - ipc.c + ..\libraries\MAX32660PeriphDriver\Source\mxc_lock.c + mxc_lock.c 0 0 - 5 + 7 42 1 0 0 0 - ..\..\..\src\irq.c - irq.c + ..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c + mxc_assert.c 0 0 - 5 + 7 43 1 0 0 0 - ..\..\..\src\kservice.c - kservice.c + ..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c + mxc_delay.c 0 0 - 5 + 7 44 1 0 0 0 - ..\..\..\src\mem.c - mem.c + ..\libraries\MAX32660PeriphDriver\Source\mxc_pins.c + mxc_pins.c 0 0 - 5 + 7 45 1 0 0 0 - ..\..\..\src\mempool.c - mempool.c + ..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c + mxc_sys.c 0 0 - 5 + 7 46 1 0 0 0 - ..\..\..\src\object.c - object.c + ..\libraries\MAX32660PeriphDriver\Source\nvic_table.c + nvic_table.c 0 0 - 5 + 7 47 1 0 0 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 5 - 48 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 5 - 49 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - 0 - 0 - - - - - libc - 1 - 0 - 0 - 0 - - 6 - 50 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\libc.c - libc.c - 0 - 0 - - - 6 - 51 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\mem_std.c - mem_std.c - 0 - 0 - - - 6 - 52 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\stubs.c - stubs.c - 0 - 0 - - - 6 - 53 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\common\time.c - time.c + ..\libraries\MAX32660PeriphDriver\Source\uart.c + uart.c 0 0 diff --git a/bsp/maxim/MAX32660_EVSYS/project.uvprojx b/bsp/maxim/MAX32660_EVSYS/project.uvprojx index f80037e4de..43a7564716 100644 --- a/bsp/maxim/MAX32660_EVSYS/project.uvprojx +++ b/bsp/maxim/MAX32660_EVSYS/project.uvprojx @@ -335,10 +335,10 @@ 0 0 - --reduce_paths - USE_APP_CONFIG, RT_USING_ARM_LIBC, __RTTHREAD__ + + __RTTHREAD__ - applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\CMSIS;..\libraries\MAX32660PeriphDriver\Include;..\..\..\components\finsh + applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\HAL_Drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\MAX32660PeriphDriverCMSIS\Device\Maxim\MAX32660\Include;..\libraries\MAX32660PeriphDriver\CMSIS\Core\Include;..\libraries\MAX32660PeriphDriver\Include @@ -353,14 +353,14 @@ 0 0 - --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74 + - 1 + 0 0 0 0 @@ -387,106 +387,6 @@ 1 applications\application.c - - system_max32660.c - 1 - ..\libraries\CMSIS\system_max32660.c - - - startup_max32660.s - 2 - ..\libraries\CMSIS\startup_max32660.s - - - mxc_sys.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c - - - mxc_assert.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c - - - mxc_delay.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c - - - mxc_lock.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\mxc_lock.c - - - mxc_pins.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\mxc_pins.c - - - nvic_table.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\nvic_table.c - - - flc.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\flc.c - - - icc.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\icc.c - - - lp.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\lp.c - - - gpio.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\gpio.c - - - rtc.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\rtc.c - - - tmr.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\tmr.c - - - tmr_utils.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\tmr_utils.c - - - uart.c - 1 - ..\libraries\MAX32660PeriphDriver\Source\uart.c - - - drv_uart.c - 1 - .\applications\drv_uart.c - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - @@ -522,11 +422,6 @@ DeviceDrivers - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - serial.c 1 @@ -577,6 +472,36 @@ 1 board\board.c + + startup_max32660.s + 2 + ..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\ARM\startup_max32660.s + + + drv_uart.c + 1 + ..\libraries\HAL_Drivers\drv_uart.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + @@ -650,27 +575,77 @@ - libc + Libraries - libc.c + system_max32660.c 1 - ..\..\..\components\libc\compilers\armlibc\libc.c + ..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\system_max32660.c - mem_std.c + gpio.c 1 - ..\..\..\components\libc\compilers\armlibc\mem_std.c + ..\libraries\MAX32660PeriphDriver\Source\gpio.c - stubs.c + lp.c 1 - ..\..\..\components\libc\compilers\armlibc\stubs.c + ..\libraries\MAX32660PeriphDriver\Source\lp.c - time.c + tmr.c 1 - ..\..\..\components\libc\compilers\common\time.c + ..\libraries\MAX32660PeriphDriver\Source\tmr.c + + + tmr_utils.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\tmr_utils.c + + + rtc.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\rtc.c + + + icc.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\icc.c + + + mxc_lock.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\mxc_lock.c + + + mxc_assert.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c + + + mxc_delay.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c + + + mxc_pins.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\mxc_pins.c + + + mxc_sys.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c + + + nvic_table.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\nvic_table.c + + + uart.c + 1 + ..\libraries\MAX32660PeriphDriver\Source\uart.c diff --git a/bsp/maxim/MAX32660_EVSYS/rtconfig.h b/bsp/maxim/MAX32660_EVSYS/rtconfig.h index 5fdbc1bc19..bd1b90652d 100644 --- a/bsp/maxim/MAX32660_EVSYS/rtconfig.h +++ b/bsp/maxim/MAX32660_EVSYS/rtconfig.h @@ -1,32 +1,6 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -#define RT_USING_USER_MAIN -#define RT_TICK_PER_SECOND 1000 -#define BSP_USING_UART1 -#define BSP_USING_UART0 -#define RT_USING_COMPONENTS_INIT - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 256 -#define RT_CONSOLE_DEVICE_NAME "uart1" - -#define RT_USING_FINSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY -#define FINSH_ARG_MAX 10 - - /* Automatically generated file; DO NOT EDIT. */ /* RT-Thread Configuration */ @@ -36,8 +10,7 @@ #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 - - +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK @@ -65,16 +38,36 @@ /* Kernel Device Object */ #define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40003 /* RT-Thread Components */ +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ /* Command shell */ +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -84,15 +77,14 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN /* Using USB */ /* POSIX layer and C standard library */ -#define RT_USING_LIBC /* Network */ @@ -150,8 +142,6 @@ /* peripheral libraries and drivers */ -#define PKG_USING_NRFX -#define PKG_USING_NRFX_V210 /* miscellaneous packages */ @@ -164,10 +154,12 @@ /* Hardware Drivers Config */ +#define SOC_MAX32660 #define SOC_MAXIM /* On-chip Peripheral Drivers */ -#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 #endif diff --git a/bsp/maxim/MAX32660_EVSYS/rtconfig.py b/bsp/maxim/MAX32660_EVSYS/rtconfig.py index 219d20d303..79deb508fd 100644 --- a/bsp/maxim/MAX32660_EVSYS/rtconfig.py +++ b/bsp/maxim/MAX32660_EVSYS/rtconfig.py @@ -3,7 +3,7 @@ import os # toolchains options ARCH='arm' CPU='cortex-m4' -CROSS_TOOL='keil' +CROSS_TOOL='gcc' if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') @@ -13,7 +13,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = 'D:/SourceryGCC/bin' + EXEC_PATH = r'C:\Users\XXYYZZ' elif CROSS_TOOL == 'keil': PLATFORM = 'armcc' EXEC_PATH = 'C:/Keil_v5' @@ -53,6 +53,8 @@ if PLATFORM == 'gcc': AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' @@ -64,16 +66,15 @@ elif PLATFORM == 'armcc': LINK = 'armlink' TARGET_EXT = 'axf' - DEVICE = ' --device DARMSTM' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"' - - CFLAGS += ' --c99' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + DEVICE = ' --cpu Cortex-M4.fp' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict --scatter "board\linker_scripts\link.sct"' - EXEC_PATH += '/arm/bin40/' + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' if BUILD == 'debug': CFLAGS += ' -g -O0' @@ -82,3 +83,52 @@ elif PLATFORM == 'armcc': CFLAGS += ' -O2' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/maxim/MAX32660_EVSYS/template.uvoptx b/bsp/maxim/MAX32660_EVSYS/template.uvoptx index 399d9edb19..e3e7bb8d2a 100644 --- a/bsp/maxim/MAX32660_EVSYS/template.uvoptx +++ b/bsp/maxim/MAX32660_EVSYS/template.uvoptx @@ -26,7 +26,7 @@ 0x4 ARM-ADS - 12000000 + 96000000 1 1 diff --git a/bsp/maxim/MAX32660_EVSYS/template.uvprojx b/bsp/maxim/MAX32660_EVSYS/template.uvprojx index 3d756e9b55..1ea2e5a7ba 100644 --- a/bsp/maxim/MAX32660_EVSYS/template.uvprojx +++ b/bsp/maxim/MAX32660_EVSYS/template.uvprojx @@ -10,7 +10,7 @@ rtthread 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC 0 @@ -188,7 +188,7 @@ 0 0 8 - 0 + 1 0 0 0 @@ -335,7 +335,7 @@ 0 0 - --reduce_paths + @@ -353,14 +353,14 @@ 0 0 - --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74 + - 1 + 0 0 0 0 @@ -369,7 +369,7 @@ 0x00000000 0x20000000 - + .\board\linker_scripts\link.sct diff --git a/bsp/maxim/libraries/HAL_Drivers/SConscript b/bsp/maxim/libraries/HAL_Drivers/SConscript new file mode 100644 index 0000000000..f6262f54da --- /dev/null +++ b/bsp/maxim/libraries/HAL_Drivers/SConscript @@ -0,0 +1,34 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_uart.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + src += ['drv_soft_i2c.c'] + + +if GetDepend(['BSP_USING_WDT']): + src += ['drv_wdt.c'] + +path = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/maxim/MAX32660_EVSYS/applications/drv_uart.c b/bsp/maxim/libraries/HAL_Drivers/drv_uart.c similarity index 98% rename from bsp/maxim/MAX32660_EVSYS/applications/drv_uart.c rename to bsp/maxim/libraries/HAL_Drivers/drv_uart.c index 66c23423d5..382806cc45 100644 --- a/bsp/maxim/MAX32660_EVSYS/applications/drv_uart.c +++ b/bsp/maxim/libraries/HAL_Drivers/drv_uart.c @@ -1,16 +1,19 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2021-02-08 Supperthomas first version + * 2021-02-11 supperthomas first version + * */ + #include "board.h" #include "uart.h" #include "rtdevice.h" +#ifdef RT_USING_SERIAL #define UART0_CONFIG \ { \ @@ -44,7 +47,7 @@ struct mcu_uart }; -#ifdef RT_USING_SERIAL + //#define DRV_DEBUG //#define LOG_TAG "drv.usart" diff --git a/bsp/maxim/MAX32660_EVSYS/applications/drv_usart.h b/bsp/maxim/libraries/HAL_Drivers/drv_usart.h similarity index 100% rename from bsp/maxim/MAX32660_EVSYS/applications/drv_usart.h rename to bsp/maxim/libraries/HAL_Drivers/drv_usart.h diff --git a/bsp/maxim/libraries/CMSIS/RTE_Components.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/RTE_Components.h similarity index 85% rename from bsp/maxim/libraries/CMSIS/RTE_Components.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/RTE_Components.h index a9774a9ad9..f79990c51e 100644 --- a/bsp/maxim/libraries/CMSIS/RTE_Components.h +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/RTE_Components.h @@ -19,6 +19,6 @@ #define BOARD EvKit_V1 /* Target Board */ #define RTE_USING_FINSH #define TARGET 32660 /* Target Device Part Number */ - #define TARGET_REV 0x4131 /* Target Device Revision Number */ +#define TARGET_REV 0x4131 /* Target Device Revision Number */ #endif /* RTE_COMPONENTS_H */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cachel1_armv7.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 0000000000..d2c3e2291f --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/maxim/libraries/CMSIS/cmsis_armcc.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_armcc.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/cmsis_armcc.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_armcc.h diff --git a/bsp/maxim/libraries/CMSIS/cmsis_armclang.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_armclang.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/cmsis_armclang.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_armclang.h diff --git a/bsp/maxim/libraries/CMSIS/cmsis_armclang_ltm.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_armclang_ltm.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/cmsis_armclang_ltm.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_armclang_ltm.h diff --git a/bsp/maxim/libraries/CMSIS/cmsis_compiler.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_compiler.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/cmsis_compiler.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_compiler.h diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_gcc.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000000..a2778f58e8 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..7eeffca5c7 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,968 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/maxim/libraries/CMSIS/cmsis_version.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_version.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/cmsis_version.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cmsis_version.h diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv81mml.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000000..1ad19e215a --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4191 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.3.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv8mbl.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000000..932d3d188b --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv8mml.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000000..71f000bcad --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3196 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/maxim/libraries/CMSIS/core_cm4.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_cm4.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/core_cm4.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_cm4.h diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_sc000.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000000..dbc755fff3 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_sc300.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000000..e8914ba601 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/maxim/libraries/CMSIS/mpu_armv7.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/mpu_armv7.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/mpu_armv7.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/mpu_armv7.h diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/mpu_armv8.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000000..ef44ad01df --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.2 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/pmu_armv8.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 0000000000..dbd39d20c7 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.0 + * @date 24. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/tz_context.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbfc_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbfc_regs.h new file mode 100644 index 0000000000..3b0a1d1314 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbfc_regs.h @@ -0,0 +1,127 @@ +/** + * @file bbfc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _BBFC_REGS_H_ +#define _BBFC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup bbfc + * @defgroup bbfc_registers BBFC_Registers + * @brief Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module. + * @details Battery-Backed Function Control. + */ + +/** + * @ingroup bbfc_registers + * Structure type to access the BBFC Registers. + */ +typedef struct { + __IO uint32_t bbfcr0; /**< \b 0x00: BBFC BBFCR0 Register */ +} mxc_bbfc_regs_t; + +/* Register offsets for module BBFC */ +/** + * @ingroup bbfc_registers + * @defgroup BBFC_Register_Offsets Register Offsets + * @brief BBFC Peripheral Register Offsets from the BBFC Base Peripheral Address. + * @{ + */ + #define MXC_R_BBFC_BBFCR0 ((uint32_t)0x00000000UL) /**< Offset from BBFC Base Address: 0x0000 */ +/**@} end of group bbfc_registers */ + +/** + * @ingroup bbfc_registers + * @defgroup BBFC_BBFCR0 BBFC_BBFCR0 + * @brief Function Control Register 0. + * @{ + */ + #define MXC_F_BBFC_BBFCR0_CKPDRV_POS 0 /**< BBFCR0_CKPDRV Position */ + #define MXC_F_BBFC_BBFCR0_CKPDRV ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKPDRV_POS)) /**< BBFCR0_CKPDRV Mask */ + + #define MXC_F_BBFC_BBFCR0_CKNPDRV_POS 4 /**< BBFCR0_CKNPDRV Position */ + #define MXC_F_BBFC_BBFCR0_CKNPDRV ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKNPDRV_POS)) /**< BBFCR0_CKNPDRV Mask */ + + #define MXC_F_BBFC_BBFCR0_RDSDLLEN_POS 8 /**< BBFCR0_RDSDLLEN Position */ + #define MXC_F_BBFC_BBFCR0_RDSDLLEN ((uint32_t)(0x1UL << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS)) /**< BBFCR0_RDSDLLEN Mask */ + #define MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS ((uint32_t)0x0UL) /**< BBFCR0_RDSDLLEN_DIS Value */ + #define MXC_S_BBFC_BBFCR0_RDSDLLEN_DIS (MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_DIS Setting */ + #define MXC_V_BBFC_BBFCR0_RDSDLLEN_EN ((uint32_t)0x1UL) /**< BBFCR0_RDSDLLEN_EN Value */ + #define MXC_S_BBFC_BBFCR0_RDSDLLEN_EN (MXC_V_BBFC_BBFCR0_RDSDLLEN_EN << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_EN Setting */ + +/**@} end of group BBFC_BBFCR0_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BBFC_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbsir_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbsir_regs.h new file mode 100644 index 0000000000..cac7b0a2e9 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbsir_regs.h @@ -0,0 +1,111 @@ +/** + * @file bbsir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _BBSIR_REGS_H_ +#define _BBSIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup bbsir + * @defgroup bbsir_registers BBSIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module. + * @details Battery-Backed Registers. + */ + +/** + * @ingroup bbsir_registers + * Structure type to access the BBSIR Registers. + */ +typedef struct { + __IO uint32_t rsv0; /**< \b 0x00: BBSIR RSV0 Register */ + __R uint32_t rsv_0x4; + __I uint32_t bb_sir2; /**< \b 0x08: BBSIR BB_SIR2 Register */ + __I uint32_t bb_sir3; /**< \b 0x0C: BBSIR BB_SIR3 Register */ +} mxc_bbsir_regs_t; + +/* Register offsets for module BBSIR */ +/** + * @ingroup bbsir_registers + * @defgroup BBSIR_Register_Offsets Register Offsets + * @brief BBSIR Peripheral Register Offsets from the BBSIR Base Peripheral Address. + * @{ + */ + #define MXC_R_BBSIR_RSV0 ((uint32_t)0x00000000UL) /**< Offset from BBSIR Base Address: 0x0000 */ + #define MXC_R_BBSIR_BB_SIR2 ((uint32_t)0x00000008UL) /**< Offset from BBSIR Base Address: 0x0008 */ + #define MXC_R_BBSIR_BB_SIR3 ((uint32_t)0x0000000CUL) /**< Offset from BBSIR Base Address: 0x000C */ +/**@} end of group bbsir_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BBSIR_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h new file mode 100644 index 0000000000..e60da8e143 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h @@ -0,0 +1,470 @@ +/** + * @file dma_regs.h + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _DMA_REGS_H_ +#define _DMA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup dma + * @defgroup dma_registers DMA_Registers + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @details DMA Controller Fully programmable, chaining capable DMA channels. + */ + +/** + * @ingroup dma_registers + * Structure type to access the DMA Registers. + */ +typedef struct { + __IO uint32_t cfg; /**< \b 0x100: DMA CFG Register */ + __IO uint32_t st; /**< \b 0x104: DMA ST Register */ + __IO uint32_t src; /**< \b 0x108: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x10C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x110: DMA CNT Register */ + __IO uint32_t src_rld; /**< \b 0x114: DMA SRC_RLD Register */ + __IO uint32_t dst_rld; /**< \b 0x118: DMA DST_RLD Register */ + __IO uint32_t cnt_rld; /**< \b 0x11C: DMA CNT_RLD Register */ +} mxc_dma_ch_regs_t; + +typedef struct { + __IO uint32_t cn; /**< \b 0x000: DMA CN Register */ + __I uint32_t intr; /**< \b 0x004: DMA INTR Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ +} mxc_dma_regs_t; + +/* Register offsets for module DMA */ +/** + * @ingroup dma_registers + * @defgroup DMA_Register_Offsets Register Offsets + * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. + * @{ + */ + #define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ + #define MXC_R_DMA_ST ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: 0x0104 */ + #define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: 0x0108 */ + #define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: 0x010C */ + #define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: 0x0110 */ + #define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: 0x0114 */ + #define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: 0x0118 */ + #define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: 0x011C */ + #define MXC_R_DMA_CN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ + #define MXC_R_DMA_INTR ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ + #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ +/**@} end of group dma_registers */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CN DMA_CN + * @brief DMA Control Register. + * @{ + */ + #define MXC_F_DMA_CN_CH0_IEN_POS 0 /**< CN_CH0_IEN Position */ + #define MXC_F_DMA_CN_CH0_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) /**< CN_CH0_IEN Mask */ + #define MXC_V_DMA_CN_CH0_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH0_IEN_DIS Value */ + #define MXC_S_DMA_CN_CH0_IEN_DIS (MXC_V_DMA_CN_CH0_IEN_DIS << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_DIS Setting */ + #define MXC_V_DMA_CN_CH0_IEN_EN ((uint32_t)0x1UL) /**< CN_CH0_IEN_EN Value */ + #define MXC_S_DMA_CN_CH0_IEN_EN (MXC_V_DMA_CN_CH0_IEN_EN << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_EN Setting */ + + #define MXC_F_DMA_CN_CH1_IEN_POS 1 /**< CN_CH1_IEN Position */ + #define MXC_F_DMA_CN_CH1_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) /**< CN_CH1_IEN Mask */ + + #define MXC_F_DMA_CN_CH2_IEN_POS 2 /**< CN_CH2_IEN Position */ + #define MXC_F_DMA_CN_CH2_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) /**< CN_CH2_IEN Mask */ + + #define MXC_F_DMA_CN_CH3_IEN_POS 3 /**< CN_CH3_IEN Position */ + #define MXC_F_DMA_CN_CH3_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) /**< CN_CH3_IEN Mask */ + +/**@} end of group DMA_CN_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INTR DMA_INTR + * @brief DMA Interrupt Register. + * @{ + */ + #define MXC_F_DMA_INTR_CH0_IPEND_POS 0 /**< INTR_CH0_IPEND Position */ + #define MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) /**< INTR_CH0_IPEND Mask */ + #define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH0_IPEND_INACTIVE Value */ + #define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_INACTIVE Setting */ + #define MXC_V_DMA_INTR_CH0_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH0_IPEND_PENDING Value */ + #define MXC_S_DMA_INTR_CH0_IPEND_PENDING (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_PENDING Setting */ + + #define MXC_F_DMA_INTR_CH1_IPEND_POS 1 /**< INTR_CH1_IPEND Position */ + #define MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) /**< INTR_CH1_IPEND Mask */ + + #define MXC_F_DMA_INTR_CH2_IPEND_POS 2 /**< INTR_CH2_IPEND Position */ + #define MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) /**< INTR_CH2_IPEND Mask */ + + #define MXC_F_DMA_INTR_CH3_IPEND_POS 3 /**< INTR_CH3_IPEND Position */ + #define MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) /**< INTR_CH3_IPEND Mask */ + +/**@} end of group DMA_INTR_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CFG DMA_CFG + * @brief DMA Channel Configuration Register. + * @{ + */ + #define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */ + #define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */ + #define MXC_V_DMA_CFG_CHEN_DIS ((uint32_t)0x0UL) /**< CFG_CHEN_DIS Value */ + #define MXC_S_DMA_CFG_CHEN_DIS (MXC_V_DMA_CFG_CHEN_DIS << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_DIS Setting */ + #define MXC_V_DMA_CFG_CHEN_EN ((uint32_t)0x1UL) /**< CFG_CHEN_EN Value */ + #define MXC_S_DMA_CFG_CHEN_EN (MXC_V_DMA_CFG_CHEN_EN << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_EN Setting */ + + #define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */ + #define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */ + #define MXC_V_DMA_CFG_RLDEN_DIS ((uint32_t)0x0UL) /**< CFG_RLDEN_DIS Value */ + #define MXC_S_DMA_CFG_RLDEN_DIS (MXC_V_DMA_CFG_RLDEN_DIS << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_DIS Setting */ + #define MXC_V_DMA_CFG_RLDEN_EN ((uint32_t)0x1UL) /**< CFG_RLDEN_EN Value */ + #define MXC_S_DMA_CFG_RLDEN_EN (MXC_V_DMA_CFG_RLDEN_EN << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_EN Setting */ + + #define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */ + #define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */ + #define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */ + #define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */ + #define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */ + #define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */ + #define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */ + #define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */ + #define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */ + #define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */ + + #define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */ + #define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */ + #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */ + #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */ + + #define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */ + #define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */ + #define MXC_V_DMA_CFG_REQWAIT_DIS ((uint32_t)0x0UL) /**< CFG_REQWAIT_DIS Value */ + #define MXC_S_DMA_CFG_REQWAIT_DIS (MXC_V_DMA_CFG_REQWAIT_DIS << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_DIS Setting */ + #define MXC_V_DMA_CFG_REQWAIT_EN ((uint32_t)0x1UL) /**< CFG_REQWAIT_EN Value */ + #define MXC_S_DMA_CFG_REQWAIT_EN (MXC_V_DMA_CFG_REQWAIT_EN << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_EN Setting */ + + #define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */ + #define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */ + #define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */ + + #define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */ + #define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */ + #define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */ + #define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */ + + #define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */ + #define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */ + #define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */ + #define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */ + #define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */ + #define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */ + #define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */ + #define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */ + + #define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */ + #define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */ + #define MXC_V_DMA_CFG_SRCINC_DIS ((uint32_t)0x0UL) /**< CFG_SRCINC_DIS Value */ + #define MXC_S_DMA_CFG_SRCINC_DIS (MXC_V_DMA_CFG_SRCINC_DIS << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_DIS Setting */ + #define MXC_V_DMA_CFG_SRCINC_EN ((uint32_t)0x1UL) /**< CFG_SRCINC_EN Value */ + #define MXC_S_DMA_CFG_SRCINC_EN (MXC_V_DMA_CFG_SRCINC_EN << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_EN Setting */ + + #define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */ + #define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */ + #define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */ + #define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */ + #define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */ + #define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */ + #define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */ + #define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */ + + #define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */ + #define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */ + #define MXC_V_DMA_CFG_DSTINC_DIS ((uint32_t)0x0UL) /**< CFG_DSTINC_DIS Value */ + #define MXC_S_DMA_CFG_DSTINC_DIS (MXC_V_DMA_CFG_DSTINC_DIS << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_DIS Setting */ + #define MXC_V_DMA_CFG_DSTINC_EN ((uint32_t)0x1UL) /**< CFG_DSTINC_EN Value */ + #define MXC_S_DMA_CFG_DSTINC_EN (MXC_V_DMA_CFG_DSTINC_EN << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_EN Setting */ + + #define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */ + #define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */ + + #define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */ + #define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */ + #define MXC_V_DMA_CFG_CHDIEN_DIS ((uint32_t)0x0UL) /**< CFG_CHDIEN_DIS Value */ + #define MXC_S_DMA_CFG_CHDIEN_DIS (MXC_V_DMA_CFG_CHDIEN_DIS << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_DIS Setting */ + #define MXC_V_DMA_CFG_CHDIEN_EN ((uint32_t)0x1UL) /**< CFG_CHDIEN_EN Value */ + #define MXC_S_DMA_CFG_CHDIEN_EN (MXC_V_DMA_CFG_CHDIEN_EN << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_EN Setting */ + + #define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */ + #define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */ + #define MXC_V_DMA_CFG_CTZIEN_DIS ((uint32_t)0x0UL) /**< CFG_CTZIEN_DIS Value */ + #define MXC_S_DMA_CFG_CTZIEN_DIS (MXC_V_DMA_CFG_CTZIEN_DIS << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_DIS Setting */ + #define MXC_V_DMA_CFG_CTZIEN_EN ((uint32_t)0x1UL) /**< CFG_CTZIEN_EN Value */ + #define MXC_S_DMA_CFG_CTZIEN_EN (MXC_V_DMA_CFG_CTZIEN_EN << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_EN Setting */ + +/**@} end of group DMA_CFG_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_ST DMA_ST + * @brief DMA Channel Status Register. + * @{ + */ + #define MXC_F_DMA_ST_CH_ST_POS 0 /**< ST_CH_ST Position */ + #define MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS)) /**< ST_CH_ST Mask */ + #define MXC_V_DMA_ST_CH_ST_DIS ((uint32_t)0x0UL) /**< ST_CH_ST_DIS Value */ + #define MXC_S_DMA_ST_CH_ST_DIS (MXC_V_DMA_ST_CH_ST_DIS << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_DIS Setting */ + #define MXC_V_DMA_ST_CH_ST_EN ((uint32_t)0x1UL) /**< ST_CH_ST_EN Value */ + #define MXC_S_DMA_ST_CH_ST_EN (MXC_V_DMA_ST_CH_ST_EN << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_EN Setting */ + + #define MXC_F_DMA_ST_IPEND_POS 1 /**< ST_IPEND Position */ + #define MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS)) /**< ST_IPEND Mask */ + #define MXC_V_DMA_ST_IPEND_INACTIVE ((uint32_t)0x0UL) /**< ST_IPEND_INACTIVE Value */ + #define MXC_S_DMA_ST_IPEND_INACTIVE (MXC_V_DMA_ST_IPEND_INACTIVE << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_INACTIVE Setting */ + #define MXC_V_DMA_ST_IPEND_PENDING ((uint32_t)0x1UL) /**< ST_IPEND_PENDING Value */ + #define MXC_S_DMA_ST_IPEND_PENDING (MXC_V_DMA_ST_IPEND_PENDING << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_PENDING Setting */ + + #define MXC_F_DMA_ST_CTZ_ST_POS 2 /**< ST_CTZ_ST Position */ + #define MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS)) /**< ST_CTZ_ST Mask */ + #define MXC_V_DMA_ST_CTZ_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_CTZ_ST_NOEVENT Value */ + #define MXC_S_DMA_ST_CTZ_ST_NOEVENT (MXC_V_DMA_ST_CTZ_ST_NOEVENT << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_NOEVENT Setting */ + #define MXC_V_DMA_ST_CTZ_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_CTZ_ST_OCCURRED Value */ + #define MXC_S_DMA_ST_CTZ_ST_OCCURRED (MXC_V_DMA_ST_CTZ_ST_OCCURRED << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_OCCURRED Setting */ + #define MXC_V_DMA_ST_CTZ_ST_CLEAR ((uint32_t)0x1UL) /**< ST_CTZ_ST_CLEAR Value */ + #define MXC_S_DMA_ST_CTZ_ST_CLEAR (MXC_V_DMA_ST_CTZ_ST_CLEAR << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_CLEAR Setting */ + + #define MXC_F_DMA_ST_RLD_ST_POS 3 /**< ST_RLD_ST Position */ + #define MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS)) /**< ST_RLD_ST Mask */ + #define MXC_V_DMA_ST_RLD_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_RLD_ST_NOEVENT Value */ + #define MXC_S_DMA_ST_RLD_ST_NOEVENT (MXC_V_DMA_ST_RLD_ST_NOEVENT << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_NOEVENT Setting */ + #define MXC_V_DMA_ST_RLD_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_RLD_ST_OCCURRED Value */ + #define MXC_S_DMA_ST_RLD_ST_OCCURRED (MXC_V_DMA_ST_RLD_ST_OCCURRED << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_OCCURRED Setting */ + #define MXC_V_DMA_ST_RLD_ST_CLEAR ((uint32_t)0x1UL) /**< ST_RLD_ST_CLEAR Value */ + #define MXC_S_DMA_ST_RLD_ST_CLEAR (MXC_V_DMA_ST_RLD_ST_CLEAR << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_CLEAR Setting */ + + #define MXC_F_DMA_ST_BUS_ERR_POS 4 /**< ST_BUS_ERR Position */ + #define MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS)) /**< ST_BUS_ERR Mask */ + #define MXC_V_DMA_ST_BUS_ERR_NOEVENT ((uint32_t)0x0UL) /**< ST_BUS_ERR_NOEVENT Value */ + #define MXC_S_DMA_ST_BUS_ERR_NOEVENT (MXC_V_DMA_ST_BUS_ERR_NOEVENT << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_NOEVENT Setting */ + #define MXC_V_DMA_ST_BUS_ERR_OCCURRED ((uint32_t)0x1UL) /**< ST_BUS_ERR_OCCURRED Value */ + #define MXC_S_DMA_ST_BUS_ERR_OCCURRED (MXC_V_DMA_ST_BUS_ERR_OCCURRED << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_OCCURRED Setting */ + #define MXC_V_DMA_ST_BUS_ERR_CLEAR ((uint32_t)0x1UL) /**< ST_BUS_ERR_CLEAR Value */ + #define MXC_S_DMA_ST_BUS_ERR_CLEAR (MXC_V_DMA_ST_BUS_ERR_CLEAR << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_CLEAR Setting */ + + #define MXC_F_DMA_ST_TO_ST_POS 6 /**< ST_TO_ST Position */ + #define MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS)) /**< ST_TO_ST Mask */ + #define MXC_V_DMA_ST_TO_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_TO_ST_NOEVENT Value */ + #define MXC_S_DMA_ST_TO_ST_NOEVENT (MXC_V_DMA_ST_TO_ST_NOEVENT << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_NOEVENT Setting */ + #define MXC_V_DMA_ST_TO_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_TO_ST_OCCURRED Value */ + #define MXC_S_DMA_ST_TO_ST_OCCURRED (MXC_V_DMA_ST_TO_ST_OCCURRED << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_OCCURRED Setting */ + #define MXC_V_DMA_ST_TO_ST_CLEAR ((uint32_t)0x1UL) /**< ST_TO_ST_CLEAR Value */ + #define MXC_S_DMA_ST_TO_ST_CLEAR (MXC_V_DMA_ST_TO_ST_CLEAR << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_CLEAR Setting */ + +/**@} end of group DMA_ST_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC DMA_SRC + * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or + * 4, depending on the data width of each AHB cycle. For peripheral transfers, some + * or all of the actual address bits are fixed. If SRCINC=0, this register remains + * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the + * register is reloaded with the contents of DMA_SRC_RLD. + * @{ + */ + #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ + #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ + +/**@} end of group DMA_SRC_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST DMA_DST + * @brief Destination Device Address. For peripheral transfers, some or all of the actual + * address bits are fixed. If DSTINC=1, this register is incremented on every AHB + * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the + * data width of each AHB cycle. In the case where a count-to-zero condition occurs + * while RLDEN=1, the register is reloaded with DMA_DST_RLD. + * @{ + */ + #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ + #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ + +/**@} end of group DMA_DST_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT DMA_CNT + * @brief DMA Counter. The user loads this register with the number of bytes to transfer. + * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will + * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter + * reaches 0, a count-to-zero condition is triggered. + * @{ + */ + #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ + #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ + +/**@} end of group DMA_CNT_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC_RLD DMA_SRC_RLD + * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC + * upon a count-to-zero condition. + * @{ + */ + #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */ + #define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */ + +/**@} end of group DMA_SRC_RLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST_RLD DMA_DST_RLD + * @brief Destination Address Reload Value. The value of this register is loaded into + * DMA0_DST upon a count-to-zero condition. + * @{ + */ + #define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */ + #define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */ + +/**@} end of group DMA_DST_RLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT_RLD DMA_CNT_RLD + * @brief DMA Channel Count Reload Register. + * @{ + */ + #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */ + #define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */ + + #define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */ + #define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */ + #define MXC_V_DMA_CNT_RLD_RLDEN_DIS ((uint32_t)0x0UL) /**< CNT_RLD_RLDEN_DIS Value */ + #define MXC_S_DMA_CNT_RLD_RLDEN_DIS (MXC_V_DMA_CNT_RLD_RLDEN_DIS << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_DIS Setting */ + #define MXC_V_DMA_CNT_RLD_RLDEN_EN ((uint32_t)0x1UL) /**< CNT_RLD_RLDEN_EN Value */ + #define MXC_S_DMA_CNT_RLD_RLDEN_EN (MXC_V_DMA_CNT_RLD_RLDEN_EN << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_EN Setting */ + +/**@} end of group DMA_CNT_RLD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _DMA_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h new file mode 100644 index 0000000000..c0c9864d23 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h @@ -0,0 +1,264 @@ +/** + * @file flc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _FLC_REGS_H_ +#define _FLC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup flc + * @defgroup flc_registers FLC_Registers + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @details Flash Memory Control. + */ + +/** + * @ingroup flc_registers + * Structure type to access the FLC Registers. + */ +typedef struct { + __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ + __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ + __IO uint32_t cn; /**< \b 0x08: FLC CN Register */ + __R uint32_t rsv_0xc_0x23[6]; + __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ + __R uint32_t rsv_0x28_0x2f[2]; + __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ + __O uint32_t acntl; /**< \b 0x40: FLC ACNTL Register */ +} mxc_flc_regs_t; + +/* Register offsets for module FLC */ +/** + * @ingroup flc_registers + * @defgroup FLC_Register_Offsets Register Offsets + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @{ + */ + #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ + #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ + #define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ + #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ + #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ + #define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ +/**@} end of group flc_registers */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ADDR FLC_ADDR + * @brief Flash Write Address. + * @{ + */ + #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ + #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group FLC_ADDR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CLKDIV FLC_CLKDIV + * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 + * MHz clock for Flash controller. + * @{ + */ + #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ + #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group FLC_CLKDIV_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CN FLC_CN + * @brief Flash Control Register. + * @{ + */ + #define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */ + #define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */ + #define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value */ + #define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */ + #define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */ + #define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */ + + #define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */ + #define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */ + + #define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */ + #define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */ + + #define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */ + #define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */ + #define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */ + #define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */ + #define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value */ + #define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */ + + #define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */ + #define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */ + #define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */ + #define MXC_S_FLC_CN_ERASE_CODE_NOP (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */ + #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */ + #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */ + #define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */ + #define MXC_S_FLC_CN_ERASE_CODE_ERASEALL (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */ + + #define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */ + #define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */ + #define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */ + #define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */ + #define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */ + #define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */ + + #define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */ + #define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */ + #define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */ + #define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */ + #define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */ + #define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting */ + + #define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */ + #define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */ + #define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */ + #define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */ + #define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value */ + #define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */ + + #define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */ + #define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */ + #define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */ + #define MXC_S_FLC_CN_UNLOCK_UNLOCKED (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */ + #define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */ + #define MXC_S_FLC_CN_UNLOCK_LOCKED (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */ + +/**@} end of group FLC_CN_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_INTR FLC_INTR + * @brief Flash Interrupt Register. + * @{ + */ + #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ + #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ + #define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */ + #define MXC_S_FLC_INTR_DONE_INACTIVE (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */ + #define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */ + #define MXC_S_FLC_INTR_DONE_PENDING (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */ + + #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ + #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ + #define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */ + #define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */ + #define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */ + #define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */ + + #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ + #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ + #define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */ + #define MXC_S_FLC_INTR_DONEIE_DISABLE (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */ + #define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */ + #define MXC_S_FLC_INTR_DONEIE_ENABLE (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */ + + #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ + #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ + +/**@} end of group FLC_INTR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_DATA FLC_DATA + * @brief Flash Write Data. + * @{ + */ + #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ + #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group FLC_DATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ACNTL FLC_ACNTL + * @brief Access Control Register. Writing the ACNTL register with the following values in + * the order shown, allows read and write access to the system and user Information + * block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = + * 0x9608b2c1. When unlocked, a write of any word will disable access to system and + * user information block. Readback of this register is always zero. + * @{ + */ + #define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */ + #define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */ + +/**@} end of group FLC_ACNTL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FLC_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h new file mode 100644 index 0000000000..1506311e1e --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h @@ -0,0 +1,769 @@ +/** + * @file gcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _GCR_REGS_H_ +#define _GCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gcr + * @defgroup gcr_registers GCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @details Global Control Registers. + */ + +/** + * @ingroup gcr_registers + * Structure type to access the GCR Registers. + */ +typedef struct { + __IO uint32_t scon; /**< \b 0x00: GCR SCON Register */ + __IO uint32_t rstr0; /**< \b 0x04: GCR RSTR0 Register */ + __IO uint32_t clkcn; /**< \b 0x08: GCR CLKCN Register */ + __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ + __R uint32_t rsv_0x10_0x17[2]; + __IO uint32_t pckdiv; /**< \b 0x18: GCR PCKDIV Register */ + __R uint32_t rsv_0x1c_0x23[2]; + __IO uint32_t perckcn0; /**< \b 0x24: GCR PERCKCN0 Register */ + __IO uint32_t memckcn; /**< \b 0x28: GCR MEMCKCN Register */ + __IO uint32_t memzcn; /**< \b 0x2C: GCR MEMZCN Register */ + __R uint32_t rsv_0x30; + __IO uint32_t scck; /**< \b 0x34: GCR SCCK Register */ + __IO uint32_t mpri0; /**< \b 0x38: GCR MPRI0 Register */ + __IO uint32_t mpri1; /**< \b 0x3C: GCR MPRI1 Register */ + __IO uint32_t sysst; /**< \b 0x40: GCR SYSST Register */ + __IO uint32_t rstr1; /**< \b 0x44: GCR RSTR1 Register */ + __IO uint32_t perckcn1; /**< \b 0x48: GCR PERCKCN1 Register */ + __IO uint32_t evten; /**< \b 0x4C: GCR EVTEN Register */ + __I uint32_t revision; /**< \b 0x50: GCR REVISION Register */ + __IO uint32_t syssie; /**< \b 0x54: GCR SYSSIE Register */ +} mxc_gcr_regs_t; + +/* Register offsets for module GCR */ +/** + * @ingroup gcr_registers + * @defgroup GCR_Register_Offsets Register Offsets + * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. + * @{ + */ + #define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ + #define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ + #define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ + #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ + #define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: 0x0018 */ + #define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ + #define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ + #define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ + #define MXC_R_GCR_SCCK ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: 0x0034 */ + #define MXC_R_GCR_MPRI0 ((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: 0x0038 */ + #define MXC_R_GCR_MPRI1 ((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: 0x003C */ + #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ + #define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ + #define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ + #define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ + #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ + #define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ +/**@} end of group gcr_registers */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SCON GCR_SCON + * @brief System Control. + * @{ + */ + #define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */ + #define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */ + #define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */ + #define MXC_S_GCR_SCON_SBUSARB_FIX (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */ + #define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */ + #define MXC_S_GCR_SCON_SBUSARB_ROUND (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */ + + #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */ + #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */ + #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */ + #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */ + #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */ + #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */ + + #define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */ + #define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */ + #define MXC_V_GCR_SCON_FPU_DIS_ENABLE ((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */ + #define MXC_S_GCR_SCON_FPU_DIS_ENABLE (MXC_V_GCR_SCON_FPU_DIS_ENABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */ + #define MXC_V_GCR_SCON_FPU_DIS_DISABLE ((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */ + #define MXC_S_GCR_SCON_FPU_DIS_DISABLE (MXC_V_GCR_SCON_FPU_DIS_DISABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */ + + #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */ + #define MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */ + #define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */ + #define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */ + #define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */ + #define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */ + + #define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */ + #define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */ + #define MXC_V_GCR_SCON_SWD_DIS_ENABLE ((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */ + #define MXC_S_GCR_SCON_SWD_DIS_ENABLE (MXC_V_GCR_SCON_SWD_DIS_ENABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */ + #define MXC_V_GCR_SCON_SWD_DIS_DISABLE ((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */ + #define MXC_S_GCR_SCON_SWD_DIS_DISABLE (MXC_V_GCR_SCON_SWD_DIS_DISABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */ + +/**@} end of group GCR_SCON_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RSTR0 GCR_RSTR0 + * @brief Reset. + * @{ + */ + #define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */ + #define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */ + #define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */ + #define MXC_S_GCR_RSTR0_DMA_RFU (MXC_V_GCR_RSTR0_DMA_RFU << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */ + #define MXC_V_GCR_RSTR0_DMA_RESET ((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */ + #define MXC_S_GCR_RSTR0_DMA_RESET (MXC_V_GCR_RSTR0_DMA_RESET << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */ + #define MXC_V_GCR_RSTR0_DMA_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_DMA_RESET_DONE (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_DMA_BUSY ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value */ + #define MXC_S_GCR_RSTR0_DMA_BUSY (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */ + #define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */ + #define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */ + #define MXC_S_GCR_RSTR0_WDT_RFU (MXC_V_GCR_RSTR0_WDT_RFU << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */ + #define MXC_V_GCR_RSTR0_WDT_RESET ((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */ + #define MXC_S_GCR_RSTR0_WDT_RESET (MXC_V_GCR_RSTR0_WDT_RESET << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */ + #define MXC_V_GCR_RSTR0_WDT_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_WDT_RESET_DONE (MXC_V_GCR_RSTR0_WDT_RESET_DONE << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_WDT_BUSY ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value */ + #define MXC_S_GCR_RSTR0_WDT_BUSY (MXC_V_GCR_RSTR0_WDT_BUSY << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */ + #define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */ + #define MXC_V_GCR_RSTR0_GPIO0_RFU ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */ + #define MXC_S_GCR_RSTR0_GPIO0_RFU (MXC_V_GCR_RSTR0_GPIO0_RFU << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */ + #define MXC_V_GCR_RSTR0_GPIO0_RESET ((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */ + #define MXC_S_GCR_RSTR0_GPIO0_RESET (MXC_V_GCR_RSTR0_GPIO0_RESET << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */ + #define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_GPIO0_BUSY ((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */ + #define MXC_S_GCR_RSTR0_GPIO0_BUSY (MXC_V_GCR_RSTR0_GPIO0_BUSY << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */ + #define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */ + #define MXC_V_GCR_RSTR0_TIMER0_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */ + #define MXC_S_GCR_RSTR0_TIMER0_RFU (MXC_V_GCR_RSTR0_TIMER0_RFU << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */ + #define MXC_V_GCR_RSTR0_TIMER0_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */ + #define MXC_S_GCR_RSTR0_TIMER0_RESET (MXC_V_GCR_RSTR0_TIMER0_RESET << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */ + #define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE (MXC_V_GCR_RSTR0_TIMER0_RESET_DONE << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_TIMER0_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */ + #define MXC_S_GCR_RSTR0_TIMER0_BUSY (MXC_V_GCR_RSTR0_TIMER0_BUSY << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */ + #define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */ + #define MXC_V_GCR_RSTR0_TIMER1_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */ + #define MXC_S_GCR_RSTR0_TIMER1_RFU (MXC_V_GCR_RSTR0_TIMER1_RFU << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */ + #define MXC_V_GCR_RSTR0_TIMER1_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */ + #define MXC_S_GCR_RSTR0_TIMER1_RESET (MXC_V_GCR_RSTR0_TIMER1_RESET << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */ + #define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE (MXC_V_GCR_RSTR0_TIMER1_RESET_DONE << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_TIMER1_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */ + #define MXC_S_GCR_RSTR0_TIMER1_BUSY (MXC_V_GCR_RSTR0_TIMER1_BUSY << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */ + #define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */ + #define MXC_V_GCR_RSTR0_TIMER2_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */ + #define MXC_S_GCR_RSTR0_TIMER2_RFU (MXC_V_GCR_RSTR0_TIMER2_RFU << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */ + #define MXC_V_GCR_RSTR0_TIMER2_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */ + #define MXC_S_GCR_RSTR0_TIMER2_RESET (MXC_V_GCR_RSTR0_TIMER2_RESET << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */ + #define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE (MXC_V_GCR_RSTR0_TIMER2_RESET_DONE << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_TIMER2_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */ + #define MXC_S_GCR_RSTR0_TIMER2_BUSY (MXC_V_GCR_RSTR0_TIMER2_BUSY << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */ + #define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */ + #define MXC_V_GCR_RSTR0_UART0_RFU ((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */ + #define MXC_S_GCR_RSTR0_UART0_RFU (MXC_V_GCR_RSTR0_UART0_RFU << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */ + #define MXC_V_GCR_RSTR0_UART0_RESET ((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */ + #define MXC_S_GCR_RSTR0_UART0_RESET (MXC_V_GCR_RSTR0_UART0_RESET << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */ + #define MXC_V_GCR_RSTR0_UART0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_UART0_RESET_DONE (MXC_V_GCR_RSTR0_UART0_RESET_DONE << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_UART0_BUSY ((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */ + #define MXC_S_GCR_RSTR0_UART0_BUSY (MXC_V_GCR_RSTR0_UART0_BUSY << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */ + #define MXC_F_GCR_RSTR0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */ + #define MXC_V_GCR_RSTR0_UART1_RFU ((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */ + #define MXC_S_GCR_RSTR0_UART1_RFU (MXC_V_GCR_RSTR0_UART1_RFU << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */ + #define MXC_V_GCR_RSTR0_UART1_RESET ((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */ + #define MXC_S_GCR_RSTR0_UART1_RESET (MXC_V_GCR_RSTR0_UART1_RESET << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */ + #define MXC_V_GCR_RSTR0_UART1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_UART1_RESET_DONE (MXC_V_GCR_RSTR0_UART1_RESET_DONE << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_UART1_BUSY ((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */ + #define MXC_S_GCR_RSTR0_UART1_BUSY (MXC_V_GCR_RSTR0_UART1_BUSY << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */ + #define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */ + #define MXC_V_GCR_RSTR0_SPI0_RFU ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value */ + #define MXC_S_GCR_RSTR0_SPI0_RFU (MXC_V_GCR_RSTR0_SPI0_RFU << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */ + #define MXC_V_GCR_RSTR0_SPI0_RESET ((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */ + #define MXC_S_GCR_RSTR0_SPI0_RESET (MXC_V_GCR_RSTR0_SPI0_RESET << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */ + #define MXC_V_GCR_RSTR0_SPI0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_SPI0_RESET_DONE (MXC_V_GCR_RSTR0_SPI0_RESET_DONE << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_SPI0_BUSY ((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */ + #define MXC_S_GCR_RSTR0_SPI0_BUSY (MXC_V_GCR_RSTR0_SPI0_BUSY << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */ + #define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */ + #define MXC_V_GCR_RSTR0_SPI1_RFU ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value */ + #define MXC_S_GCR_RSTR0_SPI1_RFU (MXC_V_GCR_RSTR0_SPI1_RFU << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */ + #define MXC_V_GCR_RSTR0_SPI1_RESET ((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */ + #define MXC_S_GCR_RSTR0_SPI1_RESET (MXC_V_GCR_RSTR0_SPI1_RESET << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */ + #define MXC_V_GCR_RSTR0_SPI1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_SPI1_RESET_DONE (MXC_V_GCR_RSTR0_SPI1_RESET_DONE << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_SPI1_BUSY ((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */ + #define MXC_S_GCR_RSTR0_SPI1_BUSY (MXC_V_GCR_RSTR0_SPI1_BUSY << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */ + #define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */ + #define MXC_V_GCR_RSTR0_I2C0_RFU ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value */ + #define MXC_S_GCR_RSTR0_I2C0_RFU (MXC_V_GCR_RSTR0_I2C0_RFU << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */ + #define MXC_V_GCR_RSTR0_I2C0_RESET ((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */ + #define MXC_S_GCR_RSTR0_I2C0_RESET (MXC_V_GCR_RSTR0_I2C0_RESET << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */ + #define MXC_V_GCR_RSTR0_I2C0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_I2C0_RESET_DONE (MXC_V_GCR_RSTR0_I2C0_RESET_DONE << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_I2C0_BUSY ((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */ + #define MXC_S_GCR_RSTR0_I2C0_BUSY (MXC_V_GCR_RSTR0_I2C0_BUSY << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */ + #define MXC_F_GCR_RSTR0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */ + #define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */ + #define MXC_S_GCR_RSTR0_RTC_RFU (MXC_V_GCR_RSTR0_RTC_RFU << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */ + #define MXC_V_GCR_RSTR0_RTC_RESET ((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */ + #define MXC_S_GCR_RSTR0_RTC_RESET (MXC_V_GCR_RSTR0_RTC_RESET << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */ + #define MXC_V_GCR_RSTR0_RTC_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_RTC_RESET_DONE (MXC_V_GCR_RSTR0_RTC_RESET_DONE << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_RTC_BUSY ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value */ + #define MXC_S_GCR_RSTR0_RTC_BUSY (MXC_V_GCR_RSTR0_RTC_BUSY << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */ + #define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */ + #define MXC_V_GCR_RSTR0_SRST_RFU ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value */ + #define MXC_S_GCR_RSTR0_SRST_RFU (MXC_V_GCR_RSTR0_SRST_RFU << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */ + #define MXC_V_GCR_RSTR0_SRST_RESET ((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */ + #define MXC_S_GCR_RSTR0_SRST_RESET (MXC_V_GCR_RSTR0_SRST_RESET << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */ + #define MXC_V_GCR_RSTR0_SRST_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_SRST_RESET_DONE (MXC_V_GCR_RSTR0_SRST_RESET_DONE << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_SRST_BUSY ((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */ + #define MXC_S_GCR_RSTR0_SRST_BUSY (MXC_V_GCR_RSTR0_SRST_BUSY << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */ + #define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */ + #define MXC_V_GCR_RSTR0_PRST_RFU ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value */ + #define MXC_S_GCR_RSTR0_PRST_RFU (MXC_V_GCR_RSTR0_PRST_RFU << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */ + #define MXC_V_GCR_RSTR0_PRST_RESET ((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */ + #define MXC_S_GCR_RSTR0_PRST_RESET (MXC_V_GCR_RSTR0_PRST_RESET << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */ + #define MXC_V_GCR_RSTR0_PRST_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_PRST_RESET_DONE (MXC_V_GCR_RSTR0_PRST_RESET_DONE << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_PRST_BUSY ((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */ + #define MXC_S_GCR_RSTR0_PRST_BUSY (MXC_V_GCR_RSTR0_PRST_BUSY << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */ + #define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */ + #define MXC_V_GCR_RSTR0_SYSTEM_RFU ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */ + #define MXC_S_GCR_RSTR0_SYSTEM_RFU (MXC_V_GCR_RSTR0_SYSTEM_RFU << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */ + #define MXC_V_GCR_RSTR0_SYSTEM_RESET ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */ + #define MXC_S_GCR_RSTR0_SYSTEM_RESET (MXC_V_GCR_RSTR0_SYSTEM_RESET << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */ + #define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE (MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_SYSTEM_BUSY ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */ + #define MXC_S_GCR_RSTR0_SYSTEM_BUSY (MXC_V_GCR_RSTR0_SYSTEM_BUSY << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */ + +/**@} end of group GCR_RSTR0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_CLKCN GCR_CLKCN + * @brief Clock Control. + * @{ + */ + #define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */ + #define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */ + #define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV128 (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */ + + #define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */ + #define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */ + #define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */ + #define MXC_S_GCR_CLKCN_CLKSEL_HIRC (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */ + #define MXC_V_GCR_CLKCN_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */ + #define MXC_S_GCR_CLKCN_CLKSEL_NANORING (MXC_V_GCR_CLKCN_CLKSEL_NANORING << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */ + #define MXC_V_GCR_CLKCN_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */ + #define MXC_S_GCR_CLKCN_CLKSEL_HFXIN (MXC_V_GCR_CLKCN_CLKSEL_HFXIN << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */ + + #define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */ + #define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */ + #define MXC_V_GCR_CLKCN_CKRDY_BUSY ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */ + #define MXC_S_GCR_CLKCN_CKRDY_BUSY (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */ + #define MXC_V_GCR_CLKCN_CKRDY_READY ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */ + #define MXC_S_GCR_CLKCN_CKRDY_READY (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */ + + #define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */ + #define MXC_F_GCR_CLKCN_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */ + #define MXC_V_GCR_CLKCN_X32K_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */ + #define MXC_S_GCR_CLKCN_X32K_EN_DIS (MXC_V_GCR_CLKCN_X32K_EN_DIS << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */ + #define MXC_V_GCR_CLKCN_X32K_EN_EN ((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */ + #define MXC_S_GCR_CLKCN_X32K_EN_EN (MXC_V_GCR_CLKCN_X32K_EN_EN << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */ + + #define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */ + #define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */ + #define MXC_V_GCR_CLKCN_HIRC_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */ + #define MXC_S_GCR_CLKCN_HIRC_EN_DIS (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */ + #define MXC_V_GCR_CLKCN_HIRC_EN_EN ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */ + #define MXC_S_GCR_CLKCN_HIRC_EN_EN (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */ + + #define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */ + #define MXC_F_GCR_CLKCN_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */ + #define MXC_V_GCR_CLKCN_X32K_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */ + #define MXC_S_GCR_CLKCN_X32K_RDY_NOT (MXC_V_GCR_CLKCN_X32K_RDY_NOT << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */ + #define MXC_V_GCR_CLKCN_X32K_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */ + #define MXC_S_GCR_CLKCN_X32K_RDY_READY (MXC_V_GCR_CLKCN_X32K_RDY_READY << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */ + + #define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */ + #define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */ + #define MXC_V_GCR_CLKCN_HIRC_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */ + #define MXC_S_GCR_CLKCN_HIRC_RDY_NOT (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */ + #define MXC_V_GCR_CLKCN_HIRC_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */ + #define MXC_S_GCR_CLKCN_HIRC_RDY_READY (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */ + + #define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */ + #define MXC_F_GCR_CLKCN_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */ + #define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */ + #define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT (MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting */ + #define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */ + #define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY (MXC_V_GCR_CLKCN_LIRC8K_RDY_READY << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY Setting */ + +/**@} end of group GCR_CLKCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PM GCR_PM + * @brief Power Management. + * @{ + */ + #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ + #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ + #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ + #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ + #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ + #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ + #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ + #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ + + #define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */ + #define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */ + #define MXC_V_GCR_PM_GPIOWKEN_DIS ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */ + #define MXC_S_GCR_PM_GPIOWKEN_DIS (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */ + #define MXC_V_GCR_PM_GPIOWKEN_EN ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value */ + #define MXC_S_GCR_PM_GPIOWKEN_EN (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */ + + #define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */ + #define MXC_F_GCR_PM_RTCWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask */ + #define MXC_V_GCR_PM_RTCWKEN_DIS ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value */ + #define MXC_S_GCR_PM_RTCWKEN_DIS (MXC_V_GCR_PM_RTCWKEN_DIS << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_DIS Setting */ + #define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */ + #define MXC_S_GCR_PM_RTCWKEN_EN (MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */ + + #define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */ + #define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */ + #define MXC_V_GCR_PM_HIRCPD_ACTIVE ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */ + #define MXC_S_GCR_PM_HIRCPD_ACTIVE (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */ + #define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */ + #define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */ + +/**@} end of group GCR_PM_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCKDIV GCR_PCKDIV + * @brief Peripheral Clock Divider. + * @{ + */ + #define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */ + #define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */ + #define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */ + #define MXC_S_GCR_PCKDIV_AONCD_DIV_4 (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */ + #define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */ + #define MXC_S_GCR_PCKDIV_AONCD_DIV_8 (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */ + #define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */ + #define MXC_S_GCR_PCKDIV_AONCD_DIV_16 (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */ + #define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */ + #define MXC_S_GCR_PCKDIV_AONCD_DIV_32 (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */ + +/**@} end of group GCR_PCKDIV_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PERCKCN0 GCR_PERCKCN0 + * @brief Peripheral Clock Disable. + * @{ + */ + #define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */ + #define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */ + #define MXC_V_GCR_PERCKCN0_GPIO0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_GPIO0D_EN (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_GPIO0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_GPIO0D_DIS (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */ + #define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */ + #define MXC_V_GCR_PERCKCN0_DMAD_EN ((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */ + #define MXC_S_GCR_PERCKCN0_DMAD_EN (MXC_V_GCR_PERCKCN0_DMAD_EN << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */ + #define MXC_V_GCR_PERCKCN0_DMAD_DIS ((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */ + #define MXC_S_GCR_PERCKCN0_DMAD_DIS (MXC_V_GCR_PERCKCN0_DMAD_DIS << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */ + #define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */ + #define MXC_V_GCR_PERCKCN0_SPI0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_SPI0D_EN (MXC_V_GCR_PERCKCN0_SPI0D_EN << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_SPI0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_SPI0D_DIS (MXC_V_GCR_PERCKCN0_SPI0D_DIS << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */ + #define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */ + #define MXC_V_GCR_PERCKCN0_SPI1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */ + #define MXC_S_GCR_PERCKCN0_SPI1D_EN (MXC_V_GCR_PERCKCN0_SPI1D_EN << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_SPI1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_SPI1D_DIS (MXC_V_GCR_PERCKCN0_SPI1D_DIS << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */ + #define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */ + #define MXC_V_GCR_PERCKCN0_UART0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_UART0D_EN (MXC_V_GCR_PERCKCN0_UART0D_EN << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_UART0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_UART0D_DIS (MXC_V_GCR_PERCKCN0_UART0D_DIS << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */ + #define MXC_F_GCR_PERCKCN0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D Mask */ + #define MXC_V_GCR_PERCKCN0_UART1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */ + #define MXC_S_GCR_PERCKCN0_UART1D_EN (MXC_V_GCR_PERCKCN0_UART1D_EN << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_UART1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_UART1D_DIS (MXC_V_GCR_PERCKCN0_UART1D_DIS << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */ + #define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */ + #define MXC_V_GCR_PERCKCN0_I2C0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_I2C0D_EN (MXC_V_GCR_PERCKCN0_I2C0D_EN << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_I2C0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_I2C0D_DIS (MXC_V_GCR_PERCKCN0_I2C0D_DIS << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */ + #define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */ + #define MXC_V_GCR_PERCKCN0_T0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_T0D_EN (MXC_V_GCR_PERCKCN0_T0D_EN << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_T0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_T0D_DIS (MXC_V_GCR_PERCKCN0_T0D_DIS << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */ + #define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */ + #define MXC_V_GCR_PERCKCN0_T1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */ + #define MXC_S_GCR_PERCKCN0_T1D_EN (MXC_V_GCR_PERCKCN0_T1D_EN << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_T1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_T1D_DIS (MXC_V_GCR_PERCKCN0_T1D_DIS << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */ + #define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */ + #define MXC_V_GCR_PERCKCN0_T2D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */ + #define MXC_S_GCR_PERCKCN0_T2D_EN (MXC_V_GCR_PERCKCN0_T2D_EN << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_T2D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_T2D_DIS (MXC_V_GCR_PERCKCN0_T2D_DIS << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */ + #define MXC_F_GCR_PERCKCN0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */ + #define MXC_V_GCR_PERCKCN0_I2C1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */ + #define MXC_S_GCR_PERCKCN0_I2C1D_EN (MXC_V_GCR_PERCKCN0_I2C1D_EN << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_I2C1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_I2C1D_DIS (MXC_V_GCR_PERCKCN0_I2C1D_DIS << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */ + +/**@} end of group GCR_PERCKCN0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMCKCN GCR_MEMCKCN + * @brief Memory Clock Control Register. + * @{ + */ + #define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */ + #define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */ + + #define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */ + #define MXC_F_GCR_MEMCKCN_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS Mask */ + #define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */ + + #define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */ + #define MXC_F_GCR_MEMCKCN_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */ + #define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Setting */ + + #define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */ + #define MXC_F_GCR_MEMCKCN_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */ + #define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Setting */ + + #define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */ + #define MXC_F_GCR_MEMCKCN_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */ + #define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Setting */ + + #define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */ + #define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */ + #define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE (MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Setting */ + +/**@} end of group GCR_MEMCKCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMZCN GCR_MEMZCN + * @brief Memory Zeroize Control. + * @{ + */ + #define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */ + #define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */ + #define MXC_V_GCR_MEMZCN_SRAM0Z_NOP ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */ + #define MXC_S_GCR_MEMZCN_SRAM0Z_NOP (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */ + #define MXC_V_GCR_MEMZCN_SRAM0Z_START ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */ + #define MXC_S_GCR_MEMZCN_SRAM0Z_START (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */ + + #define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */ + #define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */ + #define MXC_V_GCR_MEMZCN_ICACHEZ_NOP ((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */ + #define MXC_S_GCR_MEMZCN_ICACHEZ_NOP (MXC_V_GCR_MEMZCN_ICACHEZ_NOP << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */ + #define MXC_V_GCR_MEMZCN_ICACHEZ_START ((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */ + #define MXC_S_GCR_MEMZCN_ICACHEZ_START (MXC_V_GCR_MEMZCN_ICACHEZ_START << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */ + +/**@} end of group GCR_MEMZCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSST GCR_SYSST + * @brief System Status Register. + * @{ + */ + #define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */ + #define MXC_F_GCR_SYSST_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */ + #define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */ + #define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */ + #define MXC_V_GCR_SYSST_ICECLOCK_LOCKED ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */ + #define MXC_S_GCR_SYSST_ICECLOCK_LOCKED (MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */ + + #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ + #define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */ + #define MXC_V_GCR_SYSST_CODEINTERR_NORM ((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */ + #define MXC_S_GCR_SYSST_CODEINTERR_NORM (MXC_V_GCR_SYSST_CODEINTERR_NORM << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting */ + #define MXC_V_GCR_SYSST_CODEINTERR_CODE ((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */ + #define MXC_S_GCR_SYSST_CODEINTERR_CODE (MXC_V_GCR_SYSST_CODEINTERR_CODE << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_CODE Setting */ + + #define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ + #define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ + #define MXC_V_GCR_SYSST_SCMEMF_NORM ((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */ + #define MXC_S_GCR_SYSST_SCMEMF_NORM (MXC_V_GCR_SYSST_SCMEMF_NORM << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */ + #define MXC_V_GCR_SYSST_SCMEMF_MEMORY ((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */ + #define MXC_S_GCR_SYSST_SCMEMF_MEMORY (MXC_V_GCR_SYSST_SCMEMF_MEMORY << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */ + +/**@} end of group GCR_SYSST_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RSTR1 GCR_RSTR1 + * @brief Reset 1. + * @{ + */ + #define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */ + #define MXC_F_GCR_RSTR1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask */ + #define MXC_V_GCR_RSTR1_I2C1_RFU ((uint32_t)0x0UL) /**< RSTR1_I2C1_RFU Value */ + #define MXC_S_GCR_RSTR1_I2C1_RFU (MXC_V_GCR_RSTR1_I2C1_RFU << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RFU Setting */ + #define MXC_V_GCR_RSTR1_I2C1_RESET ((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */ + #define MXC_S_GCR_RSTR1_I2C1_RESET (MXC_V_GCR_RSTR1_I2C1_RESET << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */ + #define MXC_V_GCR_RSTR1_I2C1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */ + #define MXC_S_GCR_RSTR1_I2C1_RESET_DONE (MXC_V_GCR_RSTR1_I2C1_RESET_DONE << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR1_I2C1_BUSY ((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */ + #define MXC_S_GCR_RSTR1_I2C1_BUSY (MXC_V_GCR_RSTR1_I2C1_BUSY << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */ + +/**@} end of group GCR_RSTR1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PERCKCN1 GCR_PERCKCN1 + * @brief Peripheral Clock Disable. + * @{ + */ + #define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */ + #define MXC_F_GCR_PERCKCN1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */ + #define MXC_V_GCR_PERCKCN1_FLCD_EN ((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */ + #define MXC_S_GCR_PERCKCN1_FLCD_EN (MXC_V_GCR_PERCKCN1_FLCD_EN << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */ + #define MXC_V_GCR_PERCKCN1_FLCD_DIS ((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */ + #define MXC_S_GCR_PERCKCN1_FLCD_DIS (MXC_V_GCR_PERCKCN1_FLCD_DIS << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */ + + #define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */ + #define MXC_F_GCR_PERCKCN1_ICACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */ + #define MXC_V_GCR_PERCKCN1_ICACHED_EN ((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */ + #define MXC_S_GCR_PERCKCN1_ICACHED_EN (MXC_V_GCR_PERCKCN1_ICACHED_EN << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting */ + #define MXC_V_GCR_PERCKCN1_ICACHED_DIS ((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */ + #define MXC_S_GCR_PERCKCN1_ICACHED_DIS (MXC_V_GCR_PERCKCN1_ICACHED_DIS << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting */ + +/**@} end of group GCR_PERCKCN1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_EVTEN GCR_EVTEN + * @brief Event Enable Register. + * @{ + */ + #define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */ + #define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */ + + #define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */ + #define MXC_F_GCR_EVTEN_RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */ + +/**@} end of group GCR_EVTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_REVISION GCR_REVISION + * @brief Revision Register. + * @{ + */ + #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ + #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ + +/**@} end of group GCR_REVISION_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSSIE GCR_SYSSIE + * @brief System Status Interrupt Enable Register. + * @{ + */ + #define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */ + #define MXC_F_GCR_SYSSIE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */ + #define MXC_V_GCR_SYSSIE_ICEULIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */ + #define MXC_S_GCR_SYSSIE_ICEULIE_DIS (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */ + #define MXC_V_GCR_SYSSIE_ICEULIE_EN ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */ + #define MXC_S_GCR_SYSSIE_ICEULIE_EN (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */ + + #define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */ + #define MXC_F_GCR_SYSSIE_CIEIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */ + #define MXC_V_GCR_SYSSIE_CIEIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */ + #define MXC_S_GCR_SYSSIE_CIEIE_DIS (MXC_V_GCR_SYSSIE_CIEIE_DIS << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */ + #define MXC_V_GCR_SYSSIE_CIEIE_EN ((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */ + #define MXC_S_GCR_SYSSIE_CIEIE_EN (MXC_V_GCR_SYSSIE_CIEIE_EN << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */ + + #define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */ + #define MXC_F_GCR_SYSSIE_SCMFIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */ + #define MXC_V_GCR_SYSSIE_SCMFIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */ + #define MXC_S_GCR_SYSSIE_SCMFIE_DIS (MXC_V_GCR_SYSSIE_SCMFIE_DIS << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */ + #define MXC_V_GCR_SYSSIE_SCMFIE_EN ((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */ + #define MXC_S_GCR_SYSSIE_SCMFIE_EN (MXC_V_GCR_SYSSIE_SCMFIE_EN << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */ + +/**@} end of group GCR_SYSSIE_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GCR_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h new file mode 100644 index 0000000000..d25878b428 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h @@ -0,0 +1,663 @@ +/** + * @file gpio_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _GPIO_REGS_H_ +#define _GPIO_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gpio + * @defgroup gpio_registers GPIO_Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @details Individual I/O for each GPIO + */ + +/** + * @ingroup gpio_registers + * Structure type to access the GPIO Registers. + */ +typedef struct { + __IO uint32_t en; /**< \b 0x00: GPIO EN Register */ + __IO uint32_t en_set; /**< \b 0x04: GPIO EN_SET Register */ + __IO uint32_t en_clr; /**< \b 0x08: GPIO EN_CLR Register */ + __IO uint32_t out_en; /**< \b 0x0C: GPIO OUT_EN Register */ + __IO uint32_t out_en_set; /**< \b 0x10: GPIO OUT_EN_SET Register */ + __IO uint32_t out_en_clr; /**< \b 0x14: GPIO OUT_EN_CLR Register */ + __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ + __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ + __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ + __I uint32_t in; /**< \b 0x24: GPIO IN Register */ + __IO uint32_t int_mod; /**< \b 0x28: GPIO INT_MOD Register */ + __IO uint32_t int_pol; /**< \b 0x2C: GPIO INT_POL Register */ + __R uint32_t rsv_0x30; + __IO uint32_t int_en; /**< \b 0x34: GPIO INT_EN Register */ + __IO uint32_t int_en_set; /**< \b 0x38: GPIO INT_EN_SET Register */ + __IO uint32_t int_en_clr; /**< \b 0x3C: GPIO INT_EN_CLR Register */ + __I uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ + __R uint32_t rsv_0x44; + __IO uint32_t int_clr; /**< \b 0x48: GPIO INT_CLR Register */ + __IO uint32_t wake_en; /**< \b 0x4C: GPIO WAKE_EN Register */ + __IO uint32_t wake_en_set; /**< \b 0x50: GPIO WAKE_EN_SET Register */ + __IO uint32_t wake_en_clr; /**< \b 0x54: GPIO WAKE_EN_CLR Register */ + __R uint32_t rsv_0x58; + __IO uint32_t int_dual_edge; /**< \b 0x5C: GPIO INT_DUAL_EDGE Register */ + __IO uint32_t pad_cfg1; /**< \b 0x60: GPIO PAD_CFG1 Register */ + __IO uint32_t pad_cfg2; /**< \b 0x64: GPIO PAD_CFG2 Register */ + __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ + __R uint32_t rsv_0x80_0xa7[10]; + __IO uint32_t is; /**< \b 0xA8: GPIO IS Register */ + __IO uint32_t sr; /**< \b 0xAC: GPIO SR Register */ + __IO uint32_t ds; /**< \b 0xB0: GPIO DS Register */ + __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ + __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ + __R uint32_t rsv_0xbc; + __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ +} mxc_gpio_regs_t; + +/* Register offsets for module GPIO */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_Register_Offsets Register Offsets + * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ + #define MXC_R_GPIO_EN ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ + #define MXC_R_GPIO_EN_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ + #define MXC_R_GPIO_EN_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ + #define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ + #define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ + #define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ + #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ + #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ + #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ + #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ + #define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ + #define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ + #define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ + #define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ + #define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ + #define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ + #define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ + #define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ + #define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ + #define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ + #define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ + #define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ + #define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ + #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ + #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ + #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ + #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ + #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ + #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ + #define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ + #define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ + #define MXC_R_GPIO_DS ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ + #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ + #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ + #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ +/**@} end of group gpio_registers */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN GPIO_EN + * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one + * GPIO pin on the associated port. + * @{ + */ + #define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */ + #define MXC_F_GPIO_EN_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */ + #define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */ + #define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */ + #define MXC_V_GPIO_EN_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */ + #define MXC_S_GPIO_EN_GPIO_EN_GPIO (MXC_V_GPIO_EN_GPIO_EN_GPIO << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */ + +/**@} end of group GPIO_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN_SET GPIO_EN_SET + * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this + * register sets the bits in the same positions in GPIO_EN to 1, without affecting + * other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */ + #define MXC_F_GPIO_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */ + +/**@} end of group GPIO_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN_CLR GPIO_EN_CLR + * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN to 0, without + * affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */ + #define MXC_F_GPIO_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */ + +/**@} end of group GPIO_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN GPIO_OUT_EN + * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one + * GPIO pin in the associated port. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ + #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ + #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ + #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ + #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ + #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ + +/**@} end of group GPIO_OUT_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET + * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits + * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, + * without affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ + #define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ + +/**@} end of group GPIO_OUT_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR + * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more + * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, + * without affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ + #define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ + +/**@} end of group GPIO_OUT_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT GPIO_OUT + * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the + * associated port. This register can be written either directly, or by using the + * GPIO_OUT_SET and GPIO_OUT_CLR registers. + * @{ + */ + #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ + #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ + #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ + #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ + #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ + #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ + +/**@} end of group GPIO_OUT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_SET GPIO_OUT_SET + * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits + * in the same positions in GPIO_OUT to 1, without affecting other bits in that + * register. + * @{ + */ + #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ + #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ + #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ + #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ + #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ + #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ + +/**@} end of group GPIO_OUT_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR + * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_OUT to 0, without affecting other bits in + * that register. + * @{ + */ + #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ + #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ + +/**@} end of group GPIO_OUT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN GPIO_IN + * @brief GPIO Input Register. Read-only register to read from the logic states of the + * GPIO pins on this port. + * @{ + */ + #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ + #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ + +/**@} end of group GPIO_IN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_MOD GPIO_INT_MOD + * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt + * mode setting for the associated GPIO pin on this port. + * @{ + */ + #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */ + #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */ + #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ + #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */ + #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ + #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */ + +/**@} end of group GPIO_INT_MOD_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_POL GPIO_INT_POL + * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the + * interrupt polarity setting for one GPIO pin in the associated port. + * @{ + */ + #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ + #define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ + #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ + #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ + #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ + #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ + +/**@} end of group GPIO_INT_POL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN GPIO_INT_EN + * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO + * interrupt enable for the associated pin on the GPIO port. + * @{ + */ + #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ + #define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ + #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ + #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ + #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ + #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ + +/**@} end of group GPIO_INT_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET + * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets + * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits + * in that register. + * @{ + */ + #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ + #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ + #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ + #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ + #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ + #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ + +/**@} end of group GPIO_INT_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR + * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting + * other bits in that register. + * @{ + */ + #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ + #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ + #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ + #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ + #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ + #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ + +/**@} end of group GPIO_INT_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_STAT GPIO_INT_STAT + * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending + * interrupt status for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ + #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ + #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ + #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ + #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ + #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ + +/**@} end of group GPIO_INT_STAT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_CLR GPIO_INT_CLR + * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits + * in that register. + * @{ + */ + #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ + #define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ + +/**@} end of group GPIO_INT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN GPIO_WAKE_EN + * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup + * enable for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ + #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ + #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ + #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ + #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ + #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ + +/**@} end of group GPIO_WAKE_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET + * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the + * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in + * that register. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ + #define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */ + +/**@} end of group GPIO_WAKE_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR + * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears + * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ + #define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */ + +/**@} end of group GPIO_WAKE_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE + * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual + * edge mode for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ + #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ + #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ + #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ + #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ + #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ + +/**@} end of group GPIO_INT_DUAL_EDGE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1 + * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ + #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */ + +/**@} end of group GPIO_PAD_CFG1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2 + * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ + #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */ + +/**@} end of group GPIO_PAD_CFG2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1 GPIO_EN1 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ + #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ + #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ + #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ + #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ + #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ + +/**@} end of group GPIO_EN1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_SET GPIO_EN1_SET + * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ + #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ + +/**@} end of group GPIO_EN1_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR + * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ + #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ + +/**@} end of group GPIO_EN1_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2 GPIO_EN2 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ + #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ + #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ + #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ + #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ + #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ + +/**@} end of group GPIO_EN2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_SET GPIO_EN2_SET + * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ + #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ + +/**@} end of group GPIO_EN2_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR + * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN2 to 0, without + * affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ + #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ + +/**@} end of group GPIO_EN2_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS GPIO_DS + * @brief GPIO Drive Strength Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ + #define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */ + #define MXC_F_GPIO_DS_DS ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */ + #define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */ + #define MXC_S_GPIO_DS_DS_LD (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */ + #define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */ + #define MXC_S_GPIO_DS_DS_HD (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */ + +/**@} end of group GPIO_DS_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS1 GPIO_DS1 + * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ + #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ + #define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ + +/**@} end of group GPIO_DS1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PS GPIO_PS + * @brief GPIO Pull Select Mode. + * @{ + */ + #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ + #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ + +/**@} end of group GPIO_PS_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_VSSEL GPIO_VSSEL + * @brief GPIO Voltage Select. + * @{ + */ + #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ + #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ + +/**@} end of group GPIO_VSSEL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h new file mode 100644 index 0000000000..409a3b4e0c --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h @@ -0,0 +1,843 @@ +/** + * @file i2c_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _I2C_REGS_H_ +#define _I2C_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i2c + * @defgroup i2c_registers I2C_Registers + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + * @details Inter-Integrated Circuit. + */ + +/** + * @ingroup i2c_registers + * Structure type to access the I2C Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: I2C CTRL Register */ + __IO uint32_t status; /**< \b 0x04: I2C STATUS Register */ + __IO uint32_t int_fl0; /**< \b 0x08: I2C INT_FL0 Register */ + __IO uint32_t int_en0; /**< \b 0x0C: I2C INT_EN0 Register */ + __IO uint32_t int_fl1; /**< \b 0x10: I2C INT_FL1 Register */ + __IO uint32_t int_en1; /**< \b 0x14: I2C INT_EN1 Register */ + __IO uint32_t fifo_len; /**< \b 0x18: I2C FIFO_LEN Register */ + __IO uint32_t rx_ctrl0; /**< \b 0x1C: I2C RX_CTRL0 Register */ + __IO uint32_t rx_ctrl1; /**< \b 0x20: I2C RX_CTRL1 Register */ + __IO uint32_t tx_ctrl0; /**< \b 0x24: I2C TX_CTRL0 Register */ + __IO uint32_t tx_ctrl1; /**< \b 0x28: I2C TX_CTRL1 Register */ + __IO uint32_t fifo; /**< \b 0x2C: I2C FIFO Register */ + __IO uint32_t master_ctrl; /**< \b 0x30: I2C MASTER_CTRL Register */ + __IO uint32_t clk_lo; /**< \b 0x34: I2C CLK_LO Register */ + __IO uint32_t clk_hi; /**< \b 0x38: I2C CLK_HI Register */ + __IO uint32_t hs_clk; /**< \b 0x3C: I2C HS_CLK Register */ + __IO uint32_t timeout; /**< \b 0x40: I2C TIMEOUT Register */ + __IO uint32_t slave_addr; /**< \b 0x44: I2C SLAVE_ADDR Register */ + __IO uint32_t dma; /**< \b 0x48: I2C DMA Register */ +} mxc_i2c_regs_t; + +/* Register offsets for module I2C */ +/** + * @ingroup i2c_registers + * @defgroup I2C_Register_Offsets Register Offsets + * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. + * @{ + */ + #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ + #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ + #define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ + #define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ + #define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ + #define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ + #define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ + #define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ + #define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ + #define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ + #define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ + #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ + #define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ + #define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ + #define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ + #define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ + #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ + #define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: 0x0044 */ + #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +/**@} end of group i2c_registers */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CTRL I2C_CTRL + * @brief Control Register0. + * @{ + */ + #define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */ + #define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */ + #define MXC_V_I2C_CTRL_I2C_EN_DIS ((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */ + #define MXC_S_I2C_CTRL_I2C_EN_DIS (MXC_V_I2C_CTRL_I2C_EN_DIS << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */ + #define MXC_V_I2C_CTRL_I2C_EN_EN ((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value */ + #define MXC_S_I2C_CTRL_I2C_EN_EN (MXC_V_I2C_CTRL_I2C_EN_EN << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */ + + #define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */ + #define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */ + #define MXC_V_I2C_CTRL_MST_SLAVE_MODE ((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */ + #define MXC_S_I2C_CTRL_MST_SLAVE_MODE (MXC_V_I2C_CTRL_MST_SLAVE_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */ + #define MXC_V_I2C_CTRL_MST_MASTER_MODE ((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */ + #define MXC_S_I2C_CTRL_MST_MASTER_MODE (MXC_V_I2C_CTRL_MST_MASTER_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */ + + #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */ + #define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR Mask */ + #define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS ((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */ + #define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS (MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS Setting */ + #define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN ((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */ + #define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN (MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN Setting */ + + #define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */ + #define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */ + #define MXC_V_I2C_CTRL_RX_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */ + #define MXC_S_I2C_CTRL_RX_MODE_DIS (MXC_V_I2C_CTRL_RX_MODE_DIS << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */ + #define MXC_V_I2C_CTRL_RX_MODE_EN ((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */ + #define MXC_S_I2C_CTRL_RX_MODE_EN (MXC_V_I2C_CTRL_RX_MODE_EN << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */ + + #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */ + #define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK Mask */ + #define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK ((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */ + #define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK (MXC_V_I2C_CTRL_RX_MODE_ACK_ACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting */ + #define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK ((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */ + #define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK (MXC_V_I2C_CTRL_RX_MODE_ACK_NACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting */ + + #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ + #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ + #define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW ((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */ + #define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW (MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Setting */ + #define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL ((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */ + #define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL (MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting */ + + #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ + #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ + #define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW ((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */ + #define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW (MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Setting */ + #define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA ((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */ + #define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA (MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting */ + + #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ + #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ + + #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ + #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ + + #define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */ + #define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */ + #define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE ((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */ + #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Setting */ + #define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE ((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */ + #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Setting */ + + #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ + #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ + #define MXC_V_I2C_CTRL_READ_WRITE ((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */ + #define MXC_S_I2C_CTRL_READ_WRITE (MXC_V_I2C_CTRL_READ_WRITE << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */ + #define MXC_V_I2C_CTRL_READ_READ ((uint32_t)0x1UL) /**< CTRL_READ_READ Value */ + #define MXC_S_I2C_CTRL_READ_READ (MXC_V_I2C_CTRL_READ_READ << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */ + + #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS 12 /**< CTRL_SCL_CLK_STRECH_DIS Position */ + #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**< CTRL_SCL_CLK_STRECH_DIS Mask */ + #define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN ((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */ + #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_EN Setting */ + #define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS ((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */ + #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Setting */ + + #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */ + #define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE Mask */ + #define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */ + #define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS (MXC_V_I2C_CTRL_SCL_PP_MODE_DIS << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting */ + #define MXC_V_I2C_CTRL_SCL_PP_MODE_EN ((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */ + #define MXC_S_I2C_CTRL_SCL_PP_MODE_EN (MXC_V_I2C_CTRL_SCL_PP_MODE_EN << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting */ + + #define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */ + #define MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */ + #define MXC_V_I2C_CTRL_HS_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */ + #define MXC_S_I2C_CTRL_HS_MODE_DIS (MXC_V_I2C_CTRL_HS_MODE_DIS << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */ + #define MXC_V_I2C_CTRL_HS_MODE_EN ((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */ + #define MXC_S_I2C_CTRL_HS_MODE_EN (MXC_V_I2C_CTRL_HS_MODE_EN << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */ + +/**@} end of group I2C_CTRL_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_STATUS I2C_STATUS + * @brief Status Register. + * @{ + */ + #define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */ + #define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask */ + #define MXC_V_I2C_STATUS_BUS_IDLE ((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */ + #define MXC_S_I2C_STATUS_BUS_IDLE (MXC_V_I2C_STATUS_BUS_IDLE << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */ + #define MXC_V_I2C_STATUS_BUS_BUSY ((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */ + #define MXC_S_I2C_STATUS_BUS_BUSY (MXC_V_I2C_STATUS_BUS_BUSY << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */ + + #define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */ + #define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ + #define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */ + #define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY Setting */ + #define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */ + #define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting */ + + #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ + #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + #define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL ((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */ + #define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL (MXC_V_I2C_STATUS_RX_FULL_NOT_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting */ + #define MXC_V_I2C_STATUS_RX_FULL_FULL ((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */ + #define MXC_S_I2C_STATUS_RX_FULL_FULL (MXC_V_I2C_STATUS_RX_FULL_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */ + + #define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */ + #define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ + #define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */ + #define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY Setting */ + #define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */ + #define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting */ + + #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ + #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + #define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */ + #define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY (MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY Setting */ + #define MXC_V_I2C_STATUS_TX_FULL_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */ + #define MXC_S_I2C_STATUS_TX_FULL_EMPTY (MXC_V_I2C_STATUS_TX_FULL_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */ + + #define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */ + #define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */ + #define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Value */ + #define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Setting */ + #define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Value */ + #define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Setting */ + + #define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */ + #define MXC_F_I2C_STATUS_STATUS ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ + #define MXC_V_I2C_STATUS_STATUS_IDLE ((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */ + #define MXC_S_I2C_STATUS_STATUS_IDLE (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */ + #define MXC_V_I2C_STATUS_STATUS_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_MTX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_SRX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_TX ((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */ + #define MXC_S_I2C_STATUS_STATUS_TX (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */ + #define MXC_V_I2C_STATUS_STATUS_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_RX_ACK (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_RX ((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */ + #define MXC_S_I2C_STATUS_STATUS_RX (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */ + #define MXC_V_I2C_STATUS_STATUS_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_TX_ACK (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_NACK ((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */ + #define MXC_S_I2C_STATUS_STATUS_NACK (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_BY_ST ((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */ + #define MXC_S_I2C_STATUS_STATUS_BY_ST (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */ + +/**@} end of group I2C_STATUS_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INT_FL0 I2C_INT_FL0 + * @brief Interrupt Status Register. + * @{ + */ + #define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */ + #define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */ + #define MXC_V_I2C_INT_FL0_DONE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_DONE_INACTIVE (MXC_V_I2C_INT_FL0_DONE_INACTIVE << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_DONE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */ + #define MXC_S_I2C_INT_FL0_DONE_PENDING (MXC_V_I2C_INT_FL0_DONE_PENDING << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */ + #define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE Mask */ + #define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE (MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_RX_MODE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */ + #define MXC_S_I2C_INT_FL0_RX_MODE_PENDING (MXC_V_I2C_INT_FL0_RX_MODE_PENDING << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 /**< INT_FL0_GEN_CALL_ADDR Position */ + #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< INT_FL0_GEN_CALL_ADDR Mask */ + #define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING ((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */ + #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */ + #define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH Mask */ + #define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */ + #define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING (MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */ + #define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH Mask */ + #define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */ + #define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING (MXC_V_I2C_INT_FL0_RX_THRESH_PENDING << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */ + #define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH Mask */ + #define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */ + #define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING (MXC_V_I2C_INT_FL0_TX_THRESH_PENDING << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */ + #define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */ + #define MXC_V_I2C_INT_FL0_STOP_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_STOP_INACTIVE (MXC_V_I2C_INT_FL0_STOP_INACTIVE << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_STOP_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */ + #define MXC_S_I2C_INT_FL0_STOP_PENDING (MXC_V_I2C_INT_FL0_STOP_PENDING << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */ + #define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK Mask */ + #define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */ + #define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING (MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */ + #define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */ + #define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE (MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_ARB_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_ARB_ER_PENDING (MXC_V_I2C_INT_FL0_ARB_ER_PENDING << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */ + #define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */ + #define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE (MXC_V_I2C_INT_FL0_TO_ER_INACTIVE << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_TO_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_TO_ER_PENDING (MXC_V_I2C_INT_FL0_TO_ER_PENDING << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 /**< INT_FL0_ADDR_NACK_ER Position */ + #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< INT_FL0_ADDR_NACK_ER Mask */ + #define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */ + #define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER Mask */ + #define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE (MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_DATA_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_DATA_ER_PENDING (MXC_V_I2C_INT_FL0_DATA_ER_PENDING << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 /**< INT_FL0_DO_NOT_RESP_ER Position */ + #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< INT_FL0_DO_NOT_RESP_ER Mask */ + #define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */ + #define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER Mask */ + #define MXC_V_I2C_INT_FL0_START_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_START_ER_INACTIVE (MXC_V_I2C_INT_FL0_START_ER_INACTIVE << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_START_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_START_ER_PENDING (MXC_V_I2C_INT_FL0_START_ER_PENDING << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */ + #define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER Mask */ + #define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE (MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_STOP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_STOP_ER_PENDING (MXC_V_I2C_INT_FL0_STOP_ER_PENDING << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 /**< INT_FL0_TX_LOCK_OUT Position */ + #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */ + +/**@} end of group I2C_INT_FL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INT_EN0 I2C_INT_EN0 + * @brief Interrupt Enable Register. + * @{ + */ + #define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */ + #define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */ + #define MXC_V_I2C_INT_EN0_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */ + #define MXC_S_I2C_INT_EN0_DONE_DIS (MXC_V_I2C_INT_EN0_DONE_DIS << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */ + #define MXC_V_I2C_INT_EN0_DONE_EN ((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */ + #define MXC_S_I2C_INT_EN0_DONE_EN (MXC_V_I2C_INT_EN0_DONE_EN << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */ + + #define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */ + #define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE Mask */ + #define MXC_V_I2C_INT_EN0_RX_MODE_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */ + #define MXC_S_I2C_INT_EN0_RX_MODE_DIS (MXC_V_I2C_INT_EN0_RX_MODE_DIS << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */ + #define MXC_V_I2C_INT_EN0_RX_MODE_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */ + #define MXC_S_I2C_INT_EN0_RX_MODE_EN (MXC_V_I2C_INT_EN0_RX_MODE_EN << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */ + + #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS 2 /**< INT_EN0_GEN_CTRL_ADDR Position */ + #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**< INT_EN0_GEN_CTRL_ADDR Mask */ + #define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS ((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */ + #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_DIS Setting */ + #define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN ((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */ + #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN Setting */ + + #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */ + #define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH Mask */ + #define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */ + #define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS (MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS Setting */ + #define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */ + #define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN (MXC_V_I2C_INT_EN0_ADDR_MATCH_EN << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN Setting */ + + #define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */ + #define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH Mask */ + #define MXC_V_I2C_INT_EN0_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */ + #define MXC_S_I2C_INT_EN0_RX_THRESH_DIS (MXC_V_I2C_INT_EN0_RX_THRESH_DIS << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS Setting */ + #define MXC_V_I2C_INT_EN0_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */ + #define MXC_S_I2C_INT_EN0_RX_THRESH_EN (MXC_V_I2C_INT_EN0_RX_THRESH_EN << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting */ + + #define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */ + #define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH Mask */ + #define MXC_V_I2C_INT_EN0_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */ + #define MXC_S_I2C_INT_EN0_TX_THRESH_DIS (MXC_V_I2C_INT_EN0_TX_THRESH_DIS << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS Setting */ + #define MXC_V_I2C_INT_EN0_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */ + #define MXC_S_I2C_INT_EN0_TX_THRESH_EN (MXC_V_I2C_INT_EN0_TX_THRESH_EN << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting */ + + #define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */ + #define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */ + #define MXC_V_I2C_INT_EN0_STOP_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */ + #define MXC_S_I2C_INT_EN0_STOP_DIS (MXC_V_I2C_INT_EN0_STOP_DIS << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */ + #define MXC_V_I2C_INT_EN0_STOP_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */ + #define MXC_S_I2C_INT_EN0_STOP_EN (MXC_V_I2C_INT_EN0_STOP_EN << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */ + + #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */ + #define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK Mask */ + #define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */ + #define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS (MXC_V_I2C_INT_EN0_ADDR_ACK_DIS << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting */ + #define MXC_V_I2C_INT_EN0_ADDR_ACK_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */ + #define MXC_S_I2C_INT_EN0_ADDR_ACK_EN (MXC_V_I2C_INT_EN0_ADDR_ACK_EN << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting */ + + #define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */ + #define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */ + #define MXC_V_I2C_INT_EN0_ARB_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_ARB_ER_DIS (MXC_V_I2C_INT_EN0_ARB_ER_DIS << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_ARB_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_ARB_ER_EN (MXC_V_I2C_INT_EN0_ARB_ER_EN << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */ + #define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */ + #define MXC_V_I2C_INT_EN0_TO_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_TO_ER_DIS (MXC_V_I2C_INT_EN0_TO_ER_DIS << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_TO_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_TO_ER_EN (MXC_V_I2C_INT_EN0_TO_ER_EN << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */ + #define MXC_F_I2C_INT_EN0_ADDR_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER Mask */ + #define MXC_V_I2C_INT_EN0_ADDR_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_ADDR_ER_DIS (MXC_V_I2C_INT_EN0_ADDR_ER_DIS << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_ADDR_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_ADDR_ER_EN (MXC_V_I2C_INT_EN0_ADDR_ER_EN << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */ + #define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER Mask */ + #define MXC_V_I2C_INT_EN0_DATA_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_DATA_ER_DIS (MXC_V_I2C_INT_EN0_DATA_ER_DIS << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_DATA_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_DATA_ER_EN (MXC_V_I2C_INT_EN0_DATA_ER_EN << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 /**< INT_EN0_DO_NOT_RESP_ER Position */ + #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< INT_EN0_DO_NOT_RESP_ER Mask */ + #define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */ + #define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER Mask */ + #define MXC_V_I2C_INT_EN0_START_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_START_ER_DIS (MXC_V_I2C_INT_EN0_START_ER_DIS << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_START_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_START_ER_EN (MXC_V_I2C_INT_EN0_START_ER_EN << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */ + #define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER Mask */ + #define MXC_V_I2C_INT_EN0_STOP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_STOP_ER_DIS (MXC_V_I2C_INT_EN0_STOP_ER_DIS << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_STOP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_STOP_ER_EN (MXC_V_I2C_INT_EN0_STOP_ER_EN << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 /**< INT_EN0_TX_LOCK_OUT Position */ + #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */ + #define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */ + #define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS Setting */ + #define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */ + #define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN Setting */ + +/**@} end of group I2C_INT_EN0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INT_FL1 I2C_INT_FL1 + * @brief Interrupt Status Register 1. + * @{ + */ + #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 /**< INT_FL1_RX_OVERFLOW Position */ + #define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< INT_FL1_RX_OVERFLOW Mask */ + #define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */ + #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */ + #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING (MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_PENDING Setting */ + + #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 /**< INT_FL1_TX_UNDERFLOW Position */ + #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */ + #define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */ + #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */ + #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_PENDING Setting */ + +/**@} end of group I2C_INT_FL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INT_EN1 I2C_INT_EN1 + * @brief Interrupt Staus Register 1. + * @{ + */ + #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 /**< INT_EN1_RX_OVERFLOW Position */ + #define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< INT_EN1_RX_OVERFLOW Mask */ + #define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */ + #define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS (MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS Setting */ + #define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */ + #define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN (MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN Setting */ + + #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 /**< INT_EN1_TX_UNDERFLOW Position */ + #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */ + #define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */ + #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS Setting */ + #define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */ + #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN Setting */ + +/**@} end of group I2C_INT_EN1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFO_LEN I2C_FIFO_LEN + * @brief FIFO Configuration Register. + * @{ + */ + #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */ + #define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN Mask */ + + #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */ + #define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN Mask */ + +/**@} end of group I2C_FIFO_LEN_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0 + * @brief Receive Control Register 0. + * @{ + */ + #define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */ + #define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */ + #define MXC_V_I2C_RX_CTRL0_DNR_RESPOND ((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */ + #define MXC_S_I2C_RX_CTRL0_DNR_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */ + #define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY ((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */ + #define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY (MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Setting */ + + #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */ + #define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH Mask */ + #define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */ + #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED (MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Setting */ + #define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */ + #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH (MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH Setting */ + + #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */ + #define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH Mask */ + +/**@} end of group I2C_RX_CTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1 + * @brief Receive Control Register 1. + * @{ + */ + #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */ + #define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT Mask */ + + #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */ + #define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO Mask */ + +/**@} end of group I2C_RX_CTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0 + * @brief Transmit Control Register 0. + * @{ + */ + #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 /**< TX_CTRL0_TX_PRELOAD Position */ + #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< TX_CTRL0_TX_PRELOAD Mask */ + + #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 /**< TX_CTRL0_TX_READY_MODE Position */ + #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */ + #define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN ((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */ + #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_EN Setting */ + #define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS ((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */ + #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_DIS Setting */ + + #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */ + #define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */ + #define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */ + #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED (MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Setting */ + #define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */ + #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH (MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH Setting */ + + #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */ + #define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH Mask */ + +/**@} end of group I2C_TX_CTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1 + * @brief Transmit Control Register 1. + * @{ + */ + #define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */ + #define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY Mask */ + + #define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */ + #define MXC_F_I2C_TX_CTRL1_TX_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST Mask */ + #define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW ((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */ + #define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW (MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Setting */ + #define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION ((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */ + #define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION (MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Setting */ + + #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */ + #define MXC_F_I2C_TX_CTRL1_TX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO Mask */ + +/**@} end of group I2C_TX_CTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFO I2C_FIFO + * @brief Data Register. + * @{ + */ + #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ + #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +/**@} end of group I2C_FIFO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_MASTER_CTRL I2C_MASTER_CTRL + * @brief Master Control Register. + * @{ + */ + #define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */ + #define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START Mask */ + + #define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 /**< MASTER_CTRL_RESTART Position */ + #define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< MASTER_CTRL_RESTART Mask */ + + #define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */ + #define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP Mask */ + + #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 /**< MASTER_CTRL_SL_EX_ADDR Position */ + #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< MASTER_CTRL_SL_EX_ADDR Mask */ + #define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */ + #define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Setting */ + #define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */ + #define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Setting */ + + #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS 8 /**< MASTER_CTRL_MASTER_CODE Position */ + #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**< MASTER_CTRL_MASTER_CODE Mask */ + + #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 /**< MASTER_CTRL_SCL_SPEED_UP Position */ + #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**< MASTER_CTRL_SCL_SPEED_UP Mask */ + #define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN ((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */ + #define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_EN Setting */ + #define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS ((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */ + #define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Setting */ + +/**@} end of group I2C_MASTER_CTRL_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLK_LO I2C_CLK_LO + * @brief Clock Low Register. + * @{ + */ + #define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */ + #define MXC_F_I2C_CLK_LO_CLK_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */ + +/**@} end of group I2C_CLK_LO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLK_HI I2C_CLK_HI + * @brief Clock high Register. + * @{ + */ + #define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */ + #define MXC_F_I2C_CLK_HI_CKH ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */ + +/**@} end of group I2C_CLK_HI_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_HS_CLK I2C_HS_CLK + * @brief HS-Mode Clock Control Register + * @{ + */ + #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */ + #define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */ + + #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */ + #define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */ + +/**@} end of group I2C_HS_CLK_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TIMEOUT I2C_TIMEOUT + * @brief Timeout Register + * @{ + */ + #define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ + #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ + +/**@} end of group I2C_TIMEOUT_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_SLAVE_ADDR I2C_SLAVE_ADDR + * @brief Slave Address Register. + * @{ + */ + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */ + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */ + + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */ + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_DIS Mask */ + + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */ + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_IDX Mask */ + + #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 /**< SLAVE_ADDR_EX_ADDR Position */ + #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */ + #define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */ + #define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */ + #define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */ + #define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */ + +/**@} end of group I2C_SLAVE_ADDR_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_DMA I2C_DMA + * @brief DMA Register. + * @{ + */ + #define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ + #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ + #define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */ + #define MXC_S_I2C_DMA_TX_EN_DIS (MXC_V_I2C_DMA_TX_EN_DIS << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */ + #define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */ + #define MXC_S_I2C_DMA_TX_EN_EN (MXC_V_I2C_DMA_TX_EN_EN << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */ + + #define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ + #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ + #define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */ + #define MXC_S_I2C_DMA_RX_EN_DIS (MXC_V_I2C_DMA_RX_EN_DIS << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */ + #define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */ + #define MXC_S_I2C_DMA_RX_EN_EN (MXC_V_I2C_DMA_RX_EN_EN << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */ + +/**@} end of group I2C_DMA_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _I2C_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h new file mode 100644 index 0000000000..abfb9d1b86 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h @@ -0,0 +1,167 @@ +/** + * @file icc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _ICC_REGS_H_ +#define _ICC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup icc + * @defgroup icc_registers ICC_Registers + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @details Instruction Cache Controller Registers + */ + +/** + * @ingroup icc_registers + * Structure type to access the ICC Registers. + */ +typedef struct { + __I uint32_t cache_id; /**< \b 0x0000: ICC CACHE_ID Register */ + __I uint32_t memcfg; /**< \b 0x0004: ICC MEMCFG Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO uint32_t cache_ctrl; /**< \b 0x0100: ICC CACHE_CTRL Register */ + __R uint32_t rsv_0x104_0x6ff[383]; + __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ +} mxc_icc_regs_t; + +/* Register offsets for module ICC */ +/** + * @ingroup icc_registers + * @defgroup ICC_Register_Offsets Register Offsets + * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. + * @{ + */ + #define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ + #define MXC_R_ICC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ + #define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ + #define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ +/**@} end of group icc_registers */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CACHE_ID ICC_CACHE_ID + * @brief Cache ID Register. + * @{ + */ + #define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ + #define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ + + #define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ + #define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ + + #define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ + #define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ + +/**@} end of group ICC_CACHE_ID_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_MEMCFG ICC_MEMCFG + * @brief Memory Configuration Register. + * @{ + */ + #define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */ + #define MXC_F_ICC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */ + + #define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */ + #define MXC_F_ICC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */ + +/**@} end of group ICC_MEMCFG_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CACHE_CTRL ICC_CACHE_CTRL + * @brief Cache Control and Status Register. + * @{ + */ + #define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */ + #define MXC_F_ICC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */ + #define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */ + #define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS Setting */ + #define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */ + #define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN Setting */ + + #define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */ + #define MXC_F_ICC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */ + #define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */ + #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Setting */ + #define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */ + #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_READY Setting */ + +/**@} end of group ICC_CACHE_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ICC_REGS_H_ */ diff --git a/bsp/maxim/libraries/CMSIS/max32660.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/max32660.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.h diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.svd b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.svd new file mode 100644 index 0000000000..564a9c89ca --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.svd @@ -0,0 +1,10650 @@ + + + Maxim Integrated + Maxim + max32660 + ARMCM4 + 1.0 + MAX32660 32-bit ARM Cortex-M4 microcontroller with 96KB of system RAM and 256KB of flash memory. + + CM4 + r2p1 + little + true + true + 3 + false + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BBFC + Battery-Backed Function Control. + 0x40005800 + + 0x00 + 0x400 + registers + + + + BBFCR0 + Function Control Register 0. + 0x00 + read-write + + + CKPDRV + Hyperbus CK Pad Driver Control. + 0 + 4 + + + CKNPDRV + Hyperbus CKN Pad Driver Control. + 4 + 4 + + + RDSDLLEN + Hyperbus RDS DLL Power Up Control. + 8 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + + + + + + BBSIR + Battery-Backed Registers. + 0x40005400 + + 0x00 + 0x400 + registers + + + + rsv0 + RFU + 0x00 + + + BB_SIR2 + System Init. Configuration Register 2. + 0x08 + read-only + + + BB_SIR3 + System Init. Configuration Register 3. + 0x0C + read-only + + + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0 + 28 + + + DMA1 + 29 + + + DMA2 + 30 + + + DMA3 + 31 + + + DMA4 + 68 + + + DMA5 + 69 + + + DMA6 + 70 + + + DMA7 + 71 + + + DMA8 + 72 + + + DMA9 + 73 + + + DMA10 + 74 + + + DMA11 + 75 + + + DMA12 + 76 + + + DMA13 + 77 + + + DMA14 + 78 + + + DMA15 + 79 + + + + CN + DMA Control Register. + 0x000 + + + CH0_IEN + Channel 0 Interrupt Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1_IEN + Channel 1 Interrupt Enable. + 1 + 1 + + + CH2_IEN + Channel 2 Interrupt Enable. + 2 + 1 + + + CH3_IEN + Channel 3 Interrupt Enable. + 3 + 1 + + + + + INTR + DMA Interrupt Register. + 0x004 + read-only + + + CH0_IPEND + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. + 0 + 1 + + ch_ipend_enum + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CH1_IPEND + 1 + 1 + + + CH2_IPEND + 2 + 1 + + + CH3_IPEND + 3 + 1 + + + + + 4 + 4 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CFG + DMA Channel Configuration Register. + 0x100 + + + CHEN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQSEL + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPI0RX + SPI0 RX + 0x01 + + + SPI1RX + SPI1 RX + 0x02 + + + UART0RX + UART0 RX + 0x04 + + + UART1RX + UART1 RX + 0x05 + + + I2C0RX + I2C0 RX + 0x07 + + + I2C1RX + I2C1 RX + 0x08 + + + SPI0TX + SPI0 TX + 0x21 + + + SPI1TX + SPI1 TX + 0x22 + + + UART0TX + UART0 TX + 0x24 + + + UART1TX + UART1 TX + 0x25 + + + I2C0TX + I2C0 TX + 0x27 + + + I2C1TX + I2C1 TX + 0x28 + + + + + REQWAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOSEL + Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + PSSEL + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BRST + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + CHDIEN + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZIEN + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + ST + DMA Channel Status Register. + 0x104 + + + CH_ST + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_ST + Count-to-Zero (CTZ) Status + 2 + 1 + oneToClear + + ctz_st_enum_rd + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + ctz_st_enum_wr + write + + Clear + Clears the interrupt flag + 1 + + + + + RLD_ST + Reload Status. + 3 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + TO_ST + Time-Out Status. + 6 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x108 + + + ADDR + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x10C + + + ADDR + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x110 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRC_RLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x114 + + + SRC_RLD + Source Address Reload Value. + 0 + 31 + + + + + DST_RLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x118 + + + DST_RLD + Destination Address Reload Value. + 0 + 31 + + + + + CNT_RLD + DMA Channel Count Reload Register. + 0x11C + + + CNT_RLD + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + RLDEN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x1000 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CN + Flash Control Register. + 0x08 + + + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + WDTH + Data Width. This bits selects write data width. + 4 + 1 + + + size128 + 128-bit. + 0 + + + size32 + 32-bit. + 1 + + + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + LVE + Low Voltage Read Enable + 25 + 1 + read-only + + lve_read + read + + dis + Disabled + 0 + + + en + Enabled + 1 + + + + + BRST + Burst Mode Enable. + 27 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked + 2 + + + locked + Flash Locked + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending + 0 + + + pending + An interrupt is pending + 1 + + + + + AF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONEIE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + AFIE + 9 + 1 + + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACNTL + Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACNTL + Access control. + 0 + 32 + + + + + + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + + + SCON + System Control. + 0x00 + 0xFFFFFFFE + + + SBUSARB + System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. + 1 + 2 + + + fix + Fixed Burst abritration. + 0 + + + round + Round-robin scheme. + 1 + + + + + FLASH_PAGE_FLIP + Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + 4 + 1 + + + normal + Physical layout matches logical layout. + 0 + + + swapped + Bottom half mapped to logical top half and vice versa. + 1 + + + + + FPU_DIS + Floating Point Unit Disable + 5 + 1 + + + enable + enable Floating point unit + 0 + + + disable + disable floating point unit + 1 + + + + + CCACHE_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + SWD_DIS + Serial Wire Debug Disable + 14 + 1 + + + enable + Enable JTAG SWD + 0 + + + disable + Disable JTAG SWD + 1 + + + + + + + RSTR0 + Reset. + 0x04 + + + DMA + DMA Reset. + 0 + 1 + + dma_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + dma_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + WDT + Watchdog Timer Reset. + 1 + 1 + + wdt_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + wdt_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + gpio0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + gpio0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 + 1 + + timer0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 + 1 + + timer1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 + 1 + + timer2_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer2_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 + 1 + + uart0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + uart0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + uart1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + uart1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + 13 + 1 + + spi0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + spi0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 + 1 + + spi1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + xpi1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + I2C0 + I2C0 Reset. + 16 + 1 + + i2c0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + i2c0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + RTC + Real Time Clock Reset. + 17 + 1 + + rtc_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + rtc_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SRST + Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer. + 29 + 1 + + srst_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + srst_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + PRST + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + prst_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + prst_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SYSTEM + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + system_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + system_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + + + CLKCN + Clock Control. + 0x08 + 0x00000008 + + + PSC + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + CLKSEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + HIRC + The internal 96 MHz oscillator is used for the system clock. + 0 + + + nanoRing + The nano-ring output is used for the system clock. + 3 + + + hfxIn + HFXIN is used for the system clock. + 6 + + + + + CKRDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + X32K_EN + 32kHz Crystal Oscillator Enable. + 17 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + HIRC_EN + 60MHz High Frequency Internal Reference Clock Enable. + 18 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + X32K_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + read-only + + + not + Not Ready + 0 + + + Ready + X32K Ready + 1 + + + + + HIRC_RDY + 60MHz HIRC Ready. + 26 + 1 + + + not + Not Ready + 0 + + + ready + HIRC Ready + 1 + + + + + LIRC8K_RDY + 8kHz Low Frequency Reference Clock Ready. + 29 + 1 + + + not + Not Ready + 0 + + + ready + Clock Ready + 1 + + + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 3 + + + active + Active Mode. + 0 + + + shutdown + Shutdown Mode. + 3 + + + backup + Backup Mode. + 4 + + + + + GPIOWKEN + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + dis + Wake Up Disable. + 0 + + + en + Wake Up Enable. + 1 + + + + + RTCWKEN + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + dis + Wake Up Disable. + 0 + + + en + Wake Up Enable. + 1 + + + + + HIRCPD + HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode. + 15 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + + + PCKDIV + Peripheral Clock Divider. + 0x18 + 0x00000001 + + + AONCD + Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider. + 0 + 2 + + + div_4 + PCLK divide by 4. + 0 + + + div_8 + PCLK divide by 8. + 1 + + + div_16 + PCLK divide by 16. + 2 + + + div_32 + PCLK divide by 32. + 3 + + + + + + + PERCKCN0 + Peripheral Clock Disable. + 0x24 + + + GPIO0D + GPIO0 Disable. + 0 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + DMAD + DMA Disable. + 5 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + SPI0D + SPI 0 Disable. + 6 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + SPI1D + SPI 1 Disable. + 7 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + UART0D + UART 0 Disable. + 9 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + UART1D + UART 1 Disable. + 10 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + I2C0D + I2C 0 Disable. + 13 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + T0D + Timer 0 Disable. + 15 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + T1D + Timer 1 Disable. + 16 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + T2D + Timer 2 Disable. + 17 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + I2C1D + I2C 1 Disable. + 28 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + + + MEMCKCN + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + SYSRAM0LS + System RAM 0 Light Sleep Mode. + 8 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + SYSRAM1LS + System RAM 1 Light Sleep Mode. + 9 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + SYSRAM2LS + System RAM 2 Light Sleep Mode. + 10 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + SYSRAM3LS + System RAM 3 Light Sleep Mode. + 11 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + ICACHELS + ICache RAM Light Sleep Mode. + 12 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + + + MEMZCN + Memory Zeroize Control. + 0x2C + + + SRAM0Z + System RAM Block 0. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ICACHEZ + Instruction Cache. + 1 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + + + SCCK + Smart Card Clock Control. + 0x34 + 0x00001414 + + + MPRI0 + Master Priority Control Register 0. + 0x38 + 0x00001414 + + + MPRI1 + Mater Priority Control Register 1. + 0x3C + 0x00001414 + + + SYSST + System Status Register. + 0x40 + + + ICECLOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + CODEINTERR + Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. + 1 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + SCMEMF + System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. + 5 + 1 + + + norm + Normal Operating Condition. + 0 + + + memory + Memory Fault. + 1 + + + + + + + RSTR1 + Reset 1. + 0x44 + + + I2C1 + I2C1 Reset. + 0 + 1 + + reset_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + reset_read + read + + reset_done + Reset complete. + 0 + + + busy + Reset in progress. + 1 + + + + + + + PERCKCN1 + Peripheral Clock Disable. + 0x48 + + + FLCD + Secure Flash Controller Disable. + 3 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + ICACHED + ICache Clock Disable. + 11 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + + + EVTEN + Event Enable Register. + 0x4C + + + DMAEVENT + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + RXEVENT + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSSIE + System Status Interrupt Enable Register. + 0x54 + + + ICEULIE + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + CIEIE + Code Integrity Error Interrupt Enable. + 1 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + SCMFIE + System Cache Memory Fault Interrupt Enable. + 5 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + GPIO_EN + Mask of all of the pins on the port. + 0 + 32 + + + alternate + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT_EN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + GPIO_OUT_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUT_EN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT_EN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + GPIO_OUT + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + GPIO_OUT_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + GPIO_OUT_CLR + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + GPIO_IN + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_MOD + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + GPIO_INT_MOD + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INT_POL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + GPIO_INT_POL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + INT_EN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + GPIO_INT_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INT_EN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + GPIO_INT_EN_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INT_EN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + GPIO_INT_EN_CLR + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INT_STAT + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + GPIO_INT_STAT + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INT_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + GPIO_WAKE_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WAKE_EN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_DUAL_EDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + GPIO_INT_DUAL_EDGE + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PAD_CFG1 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + + + GPIO_PAD_CFG1 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + PAD_CFG2 + GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + + + GPIO_PAD_CFG2 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + GPIO_EN1 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + GPIO_EN2 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + IS + Input Hysteresis Enable Register + 0xA8 + + + SR + Slew Rate Select Register. + 0xAC + + + DS + GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + DS + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + PS + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + + + CTRL + Control Register0. + 0x00 + + + I2C_EN + I2C Enable. + [0:0] + read-write + + + dis + Disable I2C. + 0 + + + en + enable I2C. + 1 + + + + + MST + Master Mode Enable. + [1:1] + read-write + + + slave_mode + Slave Mode. + 0 + + + master_mode + Master Mode. + 1 + + + + + GEN_CALL_ADDR + General Call Address Enable. + [2:2] + read-write + + + dis + Ignore Gneral Call Address. + 0 + + + en + Acknowledge general call address. + 1 + + + + + RX_MODE + Interactive Receive Mode. + [3:3] + read-write + + + dis + Disable Interactive Receive Mode. + 0 + + + en + Enable Interactive Receive Mode. + 1 + + + + + RX_MODE_ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. + [4:4] + read-write + + + ack + return ACK (pulling SDA LOW). + 0 + + + nack + return NACK (leaving SDA HIGH). + 1 + + + + + SCL_OUT + SCL Output. This bits control SCL output when SWOE =1. + [6:6] + read-write + + + drive_scl_low + Drive SCL low. + 0 + + + release_scl + Release SCL. + 1 + + + + + SDA_OUT + SDA Output. This bits control SDA output when SWOE = 1. + [7:7] + read-write + + + drive_sda_low + Drive SDA low. + 0 + + + release_sda + Release SDA. + 1 + + + + + SCL + SCL status. This bit reflects the logic gate of SCL signal. + [8:8] + read-only + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + SW_OUT_EN + Software Output Enable. + [10:10] + read-write + + + outputs_disable + I2C Outputs SCLO and SDAO disabled. + 0 + + + outputs_enable + I2C Outputs SCLO and SDAO enabled. + 1 + + + + + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only + + + write + Write. + 0 + + + read + Read. + 1 + + + + + SCL_CLK_STRECH_DIS + This bit will disable slave clock stretching when set. + [12:12] + read-write + + + en + Slave clock stretching enabled. + 0 + + + dis + Slave clock stretching disabled. + 1 + + + + + SCL_PP_MODE + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write + + + dis + Standard open-drain operation: drive low for 0, Hi-Z for 1 + 0 + + + en + Non-standard push-pull operation: drive low for 0, drive high for 1 + 1 + + + + + HS_MODE + Hs-mode Enable. + 15 + 1 + + + dis + Hs-mode disabled. + 0 + + + en + Hs-mode enabled. + 1 + + + + + + + STATUS + Status Register. + 0x04 + + + BUS + Bus Status. + [0:0] + read-only + + + idle + I2C Bus Idle. + 0 + + + busy + I2C Bus Busy. + 1 + + + + + RX_EMPTY + RX empty. + [1:1] + read-only + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + RX_FULL + RX Full. + [2:2] + read-only + + + not_full + Not Full. + 0 + + + full + Full. + 1 + + + + + TX_EMPTY + TX Empty. + [3:3] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + TX_FULL + TX Full. + [4:4] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + CLK_MODE + Clock Mode. + [5:5] + read-only + + + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. + 0 + + + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. + 1 + + + + + STATUS + Controller Status. + [11:8] + + + idle + Controller Idle. + 0 + + + mtx_addr + master Transmit address. + 1 + + + mrx_addr_ack + Master Receive address ACK. + 2 + + + mtx_ex_addr + Master Transmit extended address. + 3 + + + mrx_ex_addr + Master Receive extended address ACK. + 4 + + + srx_addr + Slave Receive address. + 5 + + + stx_addr_ack + Slave Transmit address ACK. + 6 + + + srx_ex_addr + Slave Receive extended address. + 7 + + + stx_ex_addr_ack + Slave Transmit extended address ACK. + 8 + + + tx + Transmit data (master or slave). + 9 + + + rx_ack + Receive data ACK (master or slave). + 10 + + + rx + Receive data (master or slave). + 11 + + + tx_ack + Transmit data ACK (master or slave). + 12 + + + nack + NACK stage (master or slave). + 13 + + + by_st + Bystander state (ongoing transaction but not participant- another master addressing another slave). + 15 + + + + + + + INT_FL0 + Interrupt Status Register. + 0x08 + + + DONE + Transfer Done Interrupt. + [0:0] + + INT_FL0_Done + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_MODE + Interactive Receive Interrupt. + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + GEN_CALL_ADDR + Slave General Call Address Match Interrupt. + [2:2] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_MATCH + Slave Address Match Interrupt. + [3:3] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_THRESH + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + [4:4] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. + 1 + + + + + TX_THRESH + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. + [5:5] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + STOP + STOP Interrupt. + [6:6] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + ADDR_ACK + Address Acknowledge Interrupt. + [7:7] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ARB_ER + Arbritation error Interrupt. + [8:8] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TO_ER + timeout Error Interrupt. + [9:9] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_NACK_ER + Address NACK Error Interrupt. + [10:10] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DATA_ER + Data NACK Error Interrupt. + [11:11] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DO_NOT_RESP_ER + Do Not Respond Error Interrupt. + [12:12] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START_ER + Start Error Interrupt. + [13:13] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + STOP_ER + Stop Error Interrupt. + [14:14] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_LOCK_OUT + Transmit Lock Out Interrupt. + [15:15] + + + + + INT_EN0 + Interrupt Enable Register. + 0x0C + read-write + + + DONE + Transfer Done Interrupt Enable. + [0:0] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when DONE = 1. + 1 + + + + + RX_MODE + Description not available. + [1:1] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when RX_MODE = 1. + 1 + + + + + GEN_CTRL_ADDR + Slave mode general call address match received input enable. + [2:2] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when GEN_CTRL_ADDR = 1. + 1 + + + + + ADDR_MATCH + Slave mode incoming address match interrupt. + [3:3] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when ADDR_MATCH = 1. + 1 + + + + + RX_THRESH + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_THRESH + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP + Stop Interrupt Enable + [6:6] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when STOP = 1. + 1 + + + + + ADDR_ACK + Received Address ACK from Slave Interrupt. + [7:7] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ARB_ER + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TO_ER + Timeout Error Interrupt Enable. + [9:9] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ADDR_ER + Master Mode Address NACK Received Interrupt. + [10:10] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DATA_ER + Master Mode Data NACK Received Interrupt. + [11:11] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DO_NOT_RESP_ER + Slave Mode Do Not Respond Interrupt. + [12:12] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + START_ER + Out of Sequence START condition detected interrupt. + [13:13] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP_ER + Out of Sequence STOP condition detected interrupt. + [14:14] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_LOCK_OUT + TX FIFO Locked Out Interrupt. + [15:15] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when TXLOIE = 1. + 1 + + + + + + + INT_FL1 + Interrupt Status Register 1. + 0x10 + + + RX_OVERFLOW + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_UNDERFLOW + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + + + INT_EN1 + Interrupt Staus Register 1. + 0x14 + read-write + + + RX_OVERFLOW + Receiver Overflow Interrupt Enable. + [0:0] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + TX_UNDERFLOW + Transmit Underflow Interrupt Enable. + [1:1] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + + + FIFO_LEN + FIFO Configuration Register. + 0x18 + + + RX_LEN + Receive FIFO Length. + [7:0] + read-only + + + TX_LEN + Transmit FIFO Length. + [15:8] + read-only + + + + + RX_CTRL0 + Receive Control Register 0. + 0x1C + + + DNR + Do Not Respond. + [0:0] + + + respond + Always respond to address match. + 0 + + + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. + 1 + + + + + RX_FLUSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush RX_FIFO. + 1 + + + + + RX_THRESH + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] + + + + + RX_CTRL1 + Receive Control Register 1. + 0x20 + + + RX_CNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] + + + RX_FIFO + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only + + + + + TX_CTRL0 + Transmit Control Register 0. + 0x24 + + + TX_PRELOAD + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] + + + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + + en + HW control of I2CTXRDY enabled. + 0 + + + dis + HW control of I2CTXRDY disabled. + 1 + + + + + TX_FLUSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush TX_FIFO. + 1 + + + + + TX_THRESH + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + + TX_CTRL1 + Transmit Control Register 1. + 0x28 + + + TX_READY + Transmit FIFO Preload Ready. + [0:0] + + + TX_LAST + Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware). + [1:1] + + + hold_scl_low + Hold SCL low on TX_FIFO empty. + 0 + + + end_transaction + End transaction on TX_FIFO empty. + 1 + + + + + TX_FIFO + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + + FIFO + Data Register. + 0x2C + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + + MASTER_CTRL + Master Control Register. + 0x30 + + + START + Setting this bit to 1 will start a master transfer. + [0:0] + + + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] + + + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] + + + SL_EX_ADDR + Slave Extend Address Select. + [7:7] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + MASTER_CODE + Master Code. These bits set the Master Code used in Hs-mode operation. + [10:8] + + + SCL_SPEED_UP + Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves. + [11:11] + + + en + Master monitors SCL state. + 0 + + + dis + SCL state monitoring disabled. + 1 + + + + + + + CLK_LO + Clock Low Register. + 0x34 + + + CLK_LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + + CLK_HI + Clock high Register. + 0x38 + + + CKH + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + + HS_CLK + HS-Mode Clock Control Register + 0x3C + + + HS_CLK_LO + Slave Address. + [7:0] + + + HS_CLK_HI + Slave Address. + [15:8] + + + + + TIMEOUT + Timeout Register + 0x40 + + + TO + Timeout + [15:0] + + + + + SLAVE_ADDR + Slave Address Register. + 0x44 + + + SLAVE_ADDR + Slave Address. + [9:0] + + + SLAVE_ADDR_DIS + Slave Address DIS. + [10:10] + + + SLAVE_ADDR_IDX + Slave Address Index. + [14:11] + + + EX_ADDR + Extended Address Select. + [15:15] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + DMA + DMA Register. + 0x48 + + + TX_EN + TX channel enable. + [0:0] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RX_EN + RX channel enable. + [1:1] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + I2C1 + Inter-Integrated Circuit. 1 + 0x4001E000 + + I2C1 + I2C1 IRQ + 36 + + + + + ICC0 + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x1000 + registers + + + + CACHE_ID + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + CCHID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + MEMCFG + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCHSZ + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEMSZ + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CACHE_CTRL + Cache Control and Status Register. + 0x0100 + + + CACHE_EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + CACHE_RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + + + + + + ICC1 + Instruction Cache Controller Registers 1 + 0x4002F000 + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40006800 + + 0x00 + 0x800 + registers + + + + LP_CTRL + Low Power Control Register. + 0x00 + + + RAMRET_SEL0 + System RAM 0 Data retention in BACKUP mode. + 0 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL1 + System RAM 1 Data retention in BACKUP mode. + 1 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL2 + System RAM 2 Data retention in BACKUP mode. + 2 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL3 + System RAM 3 Data retention in BACKUP mode. + 3 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + OVR + Operating Voltage Range + 4 + 2 + + + 0_9V + 0.9V 24MHz + 0 + + + 1_0V + 1.0V 48MHz + 1 + + + 1_1V + 1.1V 96MHz + 2 + + + + + VCORE_DET_BYPASS + Bypass V CORE External Supply Detection + 6 + 1 + + + enabled + enable + 0 + + + Disable + disable + 1 + + + + + RETREG_EN + Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. + 8 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + FAST_WK_EN + Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. + 10 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + BG_OFF + Band Gap Disable for DEEPSLEEP and BACKUP Mode + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode(default). + 1 + + + + + VCORE_POR_DIS + V CORE POR Disable for DEEPSLEEP and BACKUP Mode + 12 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + LDO_DIS + LDO Disable + 16 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VCORE_SVM_DIS + V CORE Supply Voltage Monitor Disable + 20 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIO_POR_DIS + VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. + 25 + 1 + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + + + LP_WAKEFL + Low Power Mode Wakeup Flags for GPIO0 + 0x04 + + + WAKEST + Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. + 0 + 14 + + + + + LPWK_EN + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + WAKEEN + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 14 + + + + + LPMEMSD + Low Power Memory Shutdown Control. + 0x40 + + + SRAM0_OFF + System RAM block 0 Shut Down. + 0 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM1_OFF + System RAM block 1 Shut Down. + 1 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM2_OFF + System RAM block 2 Shut Down. + 2 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM3_OFF + System RAM block 3 Shut Down. + 3 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + + + + + + RTC + Real Time Clock and Alarm. + 0x40006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + RTSS + RTC Sub-second Counter. + 0 + 8 + + + + + RAS + Time-of-day Alarm. + 0x08 + 0x00000000 + + + RAS + Time-of-day Alarm. + 0 + 20 + + + + + RSSA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + RSSA + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + RTCE + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ADE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ASE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDYE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ALDF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + ALSF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + SQE + Square Wave Output Enable. + 8 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + FT + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + clkDiv8 + RTC Input Clock / 8. + 3 + + + + + X32KMD + 32KHz Oscillator Mode. + 11 + 2 + + + noiseImmuneMode + Always operate in Noise Immune Mode. Oscillator warm-up required. + 0 + + + quietMode + Always operate in Quiet Mode. No oscillator warm-up required. + 1 + + + quietInStopWithWarmup + Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit. + 2 + + + quietInStopNoWarmup + Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit. + 3 + + + + + WE + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VBATTMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FLITER_EN + RTC Oscillator Filter Enable + 0 + 1 + + + IBIAS_SEL + RTC Oscillator 4X Bias Current Select + 1 + 1 + + + 2X + Selects 2X bias current for RTC oscillator + 0 + + + 4X + Selects 4X bias current for RTC oscillator + 1 + + + + + HYST_EN + RTC Oscillator Hysteresis Buffer Enable + 2 + 1 + + + IBIAS_EN + RTC Oscillator Bias Current Enable + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + OUT32K + RTC 32kHz Square Wave Output + 5 + 1 + + + + + + + + SIR + System Initialization Registers. + 0x40000400 + read-only + + 0x00 + 0x400 + registers + + + + SISTAT + System Initialization Status Register. + 0x00 + read-only + + + MAGIC + Magic Word Validation. This bit is set by the system initialization block following power-up. + 0 + 1 + read-only + + read + + magicNotSet + Magic word was not set (OTP has not been initialized properly). + 0 + + + magicSet + Magic word was set (OTP contains valid settings). + 1 + + + + + CRCERR + CRC Error Status. This bit is set by the system initialization block following power-up. + 1 + 1 + read-only + + read + + noError + No CRC errors occurred during the read of the OTP memory block. + 0 + + + error + A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + 1 + + + + + + + ERRADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x04 + read-only + + + ERRADDR + 0 + 32 + + + + + FSTAT + funcstat register. + 0x100 + read-only + + + FPU + FPU Function. + 0 + 1 + + + no + 0 + + + yes + 1 + + + + + USB + USB Device. + 1 + 1 + + + no + 0 + + + yes + 1 + + + + + ADC + 10-bit Sigma Delta ADC. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + XIP + XiP function. + 3 + 1 + + + no + 0 + + + yes + 1 + + + + + PBM + PBM function. + 4 + 1 + + + no + 0 + + + yes + 1 + + + + + HBC + HBC function. + 5 + 1 + + + no + 0 + + + yes + 1 + + + + + SDHC + SDHC function. + 6 + 1 + + + no + 0 + + + yes + 1 + + + + + SMPHR + SMPHR function. + 7 + 1 + + + no + 0 + + + yes + 1 + + + + + SCACHE + System Cache function. + 8 + 1 + + + no + 0 + + + yes + 1 + + + + + + + SFSTAT + secfuncstat register. + 0x104 + read-only + + + TRNG + TRNG function. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + AES + AES function. + 3 + 1 + + + no + 0 + + + yes + 1 + + + + + SHA + SHA function. + 4 + 1 + + + no + 0 + + + yes + 1 + + + + + MAA + MAA function. + 5 + 1 + + + no + 0 + + + yes + 1 + + + + + + + + + + SMON + The Security Monitor block used to monitor system threat conditions. + 0x40004000 + + 0x00 + 0x1000 + registers + + + + EXTSCN + External Sensor Control Register. + 0x00 + 0x3800FFC0 + + + EXTS_EN0 + External Sensor Enable for input/output pair 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN1 + External Sensor Enable for input/output pair 1. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN2 + External Sensor Enable for input/output pair 2. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN3 + External Sensor Enable for input/output pair 3. + 3 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN4 + External Sensor Enable for input/output pair 4. + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN5 + External Sensor Enable for input/output pair 5. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTCNT + External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered. + 16 + 5 + + + EXTFRQ + External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair. + 21 + 3 + + + freq2000Hz + Div 4 (2000Hz). + 0 + + + freq1000Hz + Div 8 (1000Hz). + 1 + + + freq500Hz + Div 16 (500Hz). + 2 + + + freq250Hz + Div 32 (250Hz). + 3 + + + freq125Hz + Div 64 (125Hz). + 4 + + + freq63Hz + Div 128 (63Hz). + 5 + + + freq31Hz + Div 256 (31Hz). + 6 + + + RFU + Reserved. Do not use. + 7 + + + + + DIVCLK + Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor. + 24 + 3 + + + div1 + Divide by 1 (8000 Hz). + 0 + + + div2 + Divide by 2 (4000 Hz). + 1 + + + div4 + Divide by 4 (2000 Hz). + 2 + + + div8 + Divide by 8 (1000 Hz). + 3 + + + div16 + Divide by 16 (500 Hz). + 4 + + + div32 + Divide by 32 (250 Hz). + 5 + + + div64 + Divide by 64 (125 Hz). + 6 + + + + + BUSY + Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain. + 30 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Update in Progress. + 1 + + + + + LOCK + Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. + 31 + 1 + + + unlocked + Unlocked. + 0 + + + locked + Locked. + 1 + + + + + + + INTSCN + Internal Sensor Control Register. + 0x04 + 0x7F00FFF7 + + + SHIELD_EN + Die Shield Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TEMP_EN + Temperature Sensor Enable. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VBAT_EN + Battery Monitor Enable. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + LOTEMP_SEL + Low Temperature Detection Select. + 16 + 1 + + + neg50C + -50 degrees C. + 0 + + + neg30C + -30 degrees C. + 1 + + + + + VCORELOEN + VCORE Undervoltage Detect Enable. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VCOREHIEN + VCORE Overvoltage Detect Enable. + 19 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VDDLOEN + VDD Undervoltage Detect Enable. + 20 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VDDHIEN + VDD Overvoltage Detect Enable. + 21 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VGLEN + Voltage Glitch Detection Enable. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + LOCK + Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. + 31 + 1 + + + unlocked + Unlocked. + 0 + + + locked + Locked. + 1 + + + + + + + SECALM + Security Alarm Register. + 0x08 + 0x00000000 + 0x00000000 + + + DRS + Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + KEYWIPE + Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped. + 1 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SHIELDF + Die Shield Flag. + 2 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + LOTEMP + Low Temperature Detect. + 3 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + HITEMP + High Temperature Detect. + 4 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATLO + Battery Undervoltage Detect. + 5 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATHI + Battery Overvoltage Detect. + 6 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTF + External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. + 7 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VDDLO + VDD Undervoltage Detect Flag. + 8 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VCORELO + VCORE Undervoltage Detect Flag. + 9 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VCOREHI + VCORE Overvoltage Detect Flag. + 10 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VDDHI + VDD Overvoltage Flag. + 11 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VGL + Voltage Glitch Detection Flag. + 12 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT0 + External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 16 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT1 + External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 17 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT2 + External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 18 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT3 + External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 19 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT4 + External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 20 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT5 + External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 21 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN0 + External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 24 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN1 + External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 25 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN2 + External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 26 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN3 + External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 27 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN4 + External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 28 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN5 + External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 29 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + SECDIAG + Security Diagnostic Register. + 0x0C + read-only + 0x00000001 + 0xFFC0FE02 + + + BORF + Battery-On-Reset Flag. This bit is set once the back up battery is conneted. + 0 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + SHIELDF + Die Shield Flag. + 2 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + LOTEMP + Low Temperature Detect. + 3 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + HITEMP + High Temperature Detect. + 4 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATLO + Battery Undervoltage Detect. + 5 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATHI + Battery Overvoltage Detect. + 6 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + DYNF + Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. + 7 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + AESKT + AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR. + 8 + 1 + + + incomplete + Key has not been transferred. + 0 + + + complete + Key has been transferred. + 1 + + + + + EXTSTAT0 + External Sensor 0 Detect. + 16 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT1 + External Sensor 1 Detect. + 17 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT2 + External Sensor 2 Detect. + 18 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT3 + External Sensor 3 Detect. + 19 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT4 + External Sensor 4 Detect. + 20 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT5 + External Sensor 5 Detect. + 21 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + DLRTC + DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred. + 0x10 + read-only + 0x00000000 + + + DLRTC + DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured. + 0 + 32 + + + + + SECST + Security Monitor Status Register. + 0x34 + read-only + + + EXTSRS + External Sensor Control Register Status. + 0 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + INTSRS + Internal Sensor Control Register Status. + 1 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + SECALRS + Security Alarm Register Status. + 2 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + + + + + + SPI17Y + SPI peripheral. + 0x40046000 + + 0x00 + 0x1000 + registers + + + SPI0 + 16 + + + + DATA32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + DATA16[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 16 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + DATA8[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 8 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + MASTER + Master Mode Enable. + 1 + 1 + + + dis + SPI is Slave mode. + 0 + + + en + SPI is Master mode. + 1 + + + + + SS_IO + Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + 4 + 1 + + + output + Slave select 0 is output. + 0 + + + input + Slave Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + 1 + + + + + SS_CTRL + Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Slave Select at the end of a transaction. + 0 + + + ASSERT + SPI leaves Slave Select asserted at the end of a transaction. + 1 + + + + + SS + Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + 16 + 4 + + + SS0 + SS0 is selected. + 0x1 + + + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + SS3 + SS3 is selected. + 0x8 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CPHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CPOL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + SCLK_INV + Reserved - Must Always Be Cleared to 0. + 4 + 1 + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 0 + 16 bits per character. + 0 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + SS_POL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 8 + + + SS0_high + SS0 active high. + 0x1 + + + SS1_high + SS1 active high. + 0x2 + + + SS2_high + SS2 active high. + 0x4 + + + SS3_high + SS3 active high. + 0x8 + + + + + SRPOL + Slave Ready Polarity, each Slave Ready can have unique polarity. + 24 + 8 + + + SR0_high + SR0 active high. + 0x1 + + + SR1_high + SR1 active high. + 0x2 + + + SR2_high + SR2 active high. + 0x4 + + + SR3_high + SR3 active high. + 0x8 + + + SR4_high + SR4 active high. + 0x10 + + + SR5_high + SR5 active high. + 0x20 + + + SR6_high + SR6 active high. + 0x40 + + + SR7_high + SR7 active high. + 0x80 + + + + + + + SS_TIME + Register for controlling SPI peripheral/Slave Select Timing. + 0x10 + read-write + + + PRE + Slave Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + + + + POST + Slave Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + + + + INACT + Slave Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLK_CFG + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + SCALE + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_FIFO_LEVEL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FIFO_CLEAR + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + . + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_FIFO_CNT + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_DMA_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_FIFO_LEVEL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FIFO_CLEAR + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_FIFO_CNT + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_DMA_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INT_FL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THRESH + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THRESH + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSA + Slave Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSD + Slave Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Master Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Slave Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + M_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OVR + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UND + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OVR + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UND + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INT_EN + Register for enabling interrupts. + 0x24 + read-write + + + TX_THRESH + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EMPTY + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THRESH + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSA + Slave Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSD + Slave Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Master Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Slave Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + M_DONE + Master Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OVR + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UND + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OVR + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UND + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WAKE_FL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THRESH + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THRESH + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WAKE_EN + Register for wake up enable. + 0x2C + read-write + + + TX_THRESH + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THRESH + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STAT + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + + SPIMSS + Serial Peripheral Interface. + SPIMSS0_ + 0x40018000 + + 0x00 + 0x1000 + registers + + + + DATA16 + SPI 16-bit Data Access + 0x00 + 16 + read-write + + + DATA + SPI data. + 0 + 16 + + + + + 2 + 1 + DATA8[%s] + SPI Data 8-bit access + DATA16 + 0x00 + 8 + read-write + + + DATA + SPI data. + 0 + 8 + + + + + CTRL + SPI Control Register. + 0x04 + + + SPIEN + SPI Enable. + 0 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + MMEN + SPI Master Mode Enable. + 1 + 1 + + slv_mst_enum + + slave + 0 + + + master + 1 + + + + + WOR + Wired OR (open drain) Enable. + 2 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + CLKPOL + Clock Polarity. + 3 + 1 + + spi_pol_enum + + idleLo + SCLK idles Low (0) after character transmission/reception. + 0 + + + idleHi + SCLK idles High (1) after character transmission/reception. + 1 + + + + + PHASE + Phase Select. + 4 + 1 + + spi_phase_enum + + activeEdge + Transmit on active edge of SCLK. + 0 + + + inactiveEdge + Transmit on inactive edge of SCLK. + 1 + + + + + BIRQ + Baud Rate Generator Timer Interrupt Request. + 5 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + STR + Start SPI Interrupt. + 6 + 1 + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + IRQE + Interrupt Request Enable. + 7 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + + + STATUS + SPI Status Register. + 0x08 + 0x00000001 + + + SLAS + Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning. + 0 + 1 + read-only + + sel_enum + + selected + 0 + + + notSelected + 1 + + + + + TXST + Transmit Status. + 1 + 1 + read-only + + busy_enum + + idle + 0 + + + busy + 1 + + + + + TUND + Transmit Underrun. + 2 + 1 + oneToClear + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + ROVR + Receive Overrun. + 3 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + ABT + Slave Mode Transaction Abort. + 4 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + COL + Collision. + 5 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + TOVR + Transmit Overrun. + 6 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + IRQ + SPI Interrupt Request. + 7 + 1 + oneToClear + + flag_enum + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + + + MOD + SPI Mode Register. + 0x0C + + + SSV + Slave Select Value. + 0 + 1 + + lo_hi_enum + + lo + The SSEL pin will be driven low. + 0 + + + hi + The SSEL pin will be driven high. + 1 + + + + + SSIO + Slave Select I/O. + 1 + 1 + + input_output_enum + + input + 0 + + + output + 1 + + + + + NUMBITS + 2 + 4 + + spi_bits_enum + + bits16 + 0 + + + bits1 + 1 + + + bits2 + 2 + + + bits3 + 3 + + + bits4 + 4 + + + bits5 + 5 + + + bits6 + 6 + + + bits7 + 7 + + + bits8 + 8 + + + bits9 + 9 + + + bits10 + 10 + + + bits11 + 11 + + + bits12 + 12 + + + bits13 + 13 + + + bits14 + 14 + + + bits15 + 15 + + + + + TX_LJ + Transmit Left Justify. + 7 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + SSL1 + Slave Select 1. If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit. + 8 + 1 + + hi_lo_enum + + hi + High. + 0 + + + lo + Low. + 1 + + + + + SSL2 + Slave Select 2. If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit. + 9 + 1 + + hi_lo_enum + + hi + High. + 0 + + + lo + Low. + 1 + + + + + SSL3 + Slave Select 3. If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit. + 10 + 1 + + hi_lo_enum + + hi + High. + 0 + + + lo + Low. + 1 + + + + + + + BRG + Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4). + 0x14 + 0x0000FFFF + + + BRG + Baud Rate Reload Value. + 0 + 16 + + + + + DMA + SPI DMA Register. + 0x18 + 0x00070007 + + + TX_FIFO_LEVEL + Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs. + 0 + 3 + + fifo_level_enum + + entry1 + 0 + + + entries2 + 1 + + + entries3 + 2 + + + entries4 + 3 + + + entries5 + 4 + + + entries6 + 5 + + + entries7 + 6 + + + entries8 + 7 + + + + + TX_FIFO_CLEAR + Transmit FIFO Clear. + 4 + 1 + write-only + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + TX_FIFO_CNT + Transmit FIFO Count. + 8 + 4 + read-only + + + TX_DMA_EN + Transmit DMA Enable. + 15 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + RX_FIFO_LEVEL + Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request. + 16 + 3 + + fifo_level_enum + + entry1 + 0 + + + entries2 + 1 + + + entries3 + 2 + + + entries4 + 3 + + + entries5 + 4 + + + entries6 + 5 + + + entries7 + 6 + + + entries8 + 7 + + + + + RX_FIFO_CLEAR + Receive FIFO Clear. + 20 + 1 + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + RX_FIFO_CNT + Receive FIFO Count. + 24 + 4 + read-only + + + RX_DMA_EN + Receive DMA Enable. + 31 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + + + I2S_CTRL + I2S Control Register. + 0x1C + + + I2S_EN + I2S Mode Enable. + 0 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + I2S_MUTE + I2S Mute transmit. + 1 + 1 + + + normal + Normal Transmit. + 0 + + + replaced + Transmit data is replaced with 0. + 1 + + + + + I2S_PAUSE + I2S Pause transmit/receive. + 2 + 1 + + + normal + Normal Transmit. + 0 + + + halt + Halt transmit and receive FIFO and DMA access, transmit 0's. + 1 + + + + + I2S_MONO + I2S Monophonic Audio Mode. + 3 + 1 + + + stereophonic + Stereophonic audio. + 0 + + + monophonic + Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored. + 1 + + + + + I2S_LJ + I2S Left Justify. + 4 + 1 + + + normal + Normal I2S audio protocol. + 0 + + + replaced + Audio data is synchronized with SSEL. + 1 + + + + + + + + + + TMR0 + 32-bit reloadable timer that can be used for timing and event counting. + Timers + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR0 + TMR0 IRQ + 5 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + PWM + PWM. This register stores the value that is compared to the current timer count. + 0x08 + + + INTR + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + IRQ_CLR + Clear Interrupt. + 0 + 1 + + + + + CN + Timer Control Register. + 0x10 + + + TMODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + pwm + PWM Mode. + 3 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + PRES + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + TPOL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + TEN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRES3 + MSB of prescaler value. + 8 + 1 + + + PWMSYNC + Timer PWM Synchronization Mode Enable. + 9 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLHPOL + Timer PWM output 0A polarity bit. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLLPOL + Timer PWM output 0A' polarity bit. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PWMCKBD + Timer PWM output 0A Mode Disable. + 12 + 1 + + + dis + Disable. + 1 + + + en + Enable. + 0 + + + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + NOLLCMP + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + NOLHCMP + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + + + + TMR1 + 32-bit reloadable timer that can be used for timing and event counting. 1 + 0x40011000 + + TMR1 + TMR1 IRQ + 6 + + + + + TMR2 + 32-bit reloadable timer that can be used for timing and event counting. 2 + 0x40012000 + + TMR2 + TMR2 IRQ + 7 + + + + + UART0 + UART + 0x40042000 + + 0 + 0x1000 + registers + + + UART0 + UART0 IRQ + 14 + + + + CTRL + Control Register. + 0x00 + 32 + + + ENABLE + UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled. + 0 + 1 + + + dis + UART disabled. FIFOs are flushed. Clock is gated off for power savings. + 0 + + + en + UART enabled. + 1 + + + + + PARITY_EN + Enable/disable Parity bit (9th character). + 1 + 1 + + + dis + No Parity + 0 + + + en + Parity enabled as 9th bit + 1 + + + + + PARITY + When PARITY_EN=1, selects odd, even, Mark or Space parity. + Mark parity = always 1; Space parity = always 0. + 2 + 2 + + + Even + Even parity selected. + 0 + + + ODD + Odd parity selected. + 1 + + + MARK + Mark parity selected. + 2 + + + SPACE + Space parity selected. + 3 + + + + + PARMD + Selects parity based on 1s or 0s count (when PARITY_EN=1). + 4 + 1 + + + 1 + Parity calculation is based on number of 1s in frame. + 0 + + + 0 + Parity calculation is based on number of 0s in frame. + 1 + + + + + TX_FLUSH + Flushes the TX FIFO buffer. + 5 + 1 + + + RX_FLUSH + Flushes the RX FIFO buffer. + 6 + 1 + + + BITACC + If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation. + 7 + 1 + + + FRAME + Frame accuracy. + 0 + + + BIT + Bit accuracy. + 1 + + + + + CHAR_SIZE + Selects UART character size. + 8 + 2 + + + 5 + 5 bits. + 0 + + + 6 + 6 bits. + 1 + + + 7 + 7 bits. + 2 + + + 8 + 8 bits. + 3 + + + + + STOPBITS + Selects the number of stop bits that will be generated. + 10 + 1 + + + 1 + 1 stop bit. + 0 + + + 1_5 + 1.5 stop bits. + 1 + + + + + FLOW_CTRL + Enables/disables hardware flow control. + 11 + 1 + + + en + HW Flow Control with RTS/CTS enabled + 1 + + + dis + HW Flow Control disabled + 0 + + + + + FLOW_POL + RTS/CTS polarity. + 12 + 1 + + + 0 + RTS/CTS asserted is logic 0. + 0 + + + 1 + RTS/CTS asserted is logic 1. + 1 + + + + + NULL_MODEM + NULL Modem Support (RTS/CTS and TXD/RXD swap). + 13 + 1 + + + DIS + Direct convention. + 0 + + + EN + Null Modem Mode. + 1 + + + + + BREAK + Break control bit. It causes a break condition to be transmitted to receiving UART. + 14 + 1 + + + DIS + Break characters are not generated. + 0 + + + EN + Break characters are sent(all the bits are at '0' including start/parity/stop). + 1 + + + + + CLKSEL + Baud Rate Clock Source Select. Selects the baud rate clock. + 15 + 1 + + + SYSTEM + System clock. + 0 + + + ALTERNATE + Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. + 1 + + + + + RX_TO + RX Time Out. RX time out interrupt will occur after RXTO Uart + characters if RX-FIFO is not empty and RX FIFO has not been read. + 16 + 8 + + + + + THRESH_CTRL + Threshold Control register. + 0x04 + 32 + + + RX_FIFO_THRESH + RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. + 0 + 6 + + + TX_FIFO_THRESH + TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. + 8 + 6 + + + RTS_FIFO_THRESH + RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. + 16 + 6 + + + + + STATUS + Status Register. + 0x08 + 32 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status. + 0 + 1 + read-only + + + RX_BUSY + Read-only flag indicating the UARTreceiver status. + 1 + 1 + read-only + + + PARITY + 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. + 2 + 1 + read-only + + + BREAK + Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). + 3 + 1 + read-only + + + RX_EMPTY + Read-only flag indicating the RX FIFO state. + 4 + 1 + read-only + + + RX_FULL + Read-only flag indicating the RX FIFO state. + 5 + 1 + read-only + + + TX_EMPTY + Read-only flag indicating the TX FIFO state. + 6 + 1 + read-only + + + TX_FULL + Read-only flag indicating the TX FIFO state. + 7 + 1 + read-only + + + RX_FIFO_CNT + Indicates the number of bytes currently in the RX FIFO. + 8 + 6 + read-only + + + TX_FIFO_CNT + Indicates the number of bytes currently in the TX FIFO. + 16 + 6 + read-only + + + RX_TO + RX Timeout status. + 24 + 1 + read-only + + + + + INT_EN + Interrupt Enable Register. + 0x0C + 32 + + + RX_FRAME_ERROR + Enable for RX Frame Error Interrupt. + 0 + 1 + + + RX_PARITY_ERROR + Enable for RX Parity Error interrupt. + 1 + 1 + + + CTS_CHANGE + Enable for CTS signal change interrupt. + 2 + 1 + + + RX_OVERRUN + Enable for RX FIFO OVerrun interrupt. + 3 + 1 + + + RX_FIFO_THRESH + Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + 4 + 1 + + + TX_FIFO_ALMOST_EMPTY + Enable for interrupt when TX FIFO has only one byte remaining. + 5 + 1 + + + TX_FIFO_THRESH + Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. + 6 + 1 + + + BREAK + Enable for received BREAK character interrupt. + 7 + 1 + + + RX_TIMEOUT + Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). + 8 + 1 + + + LAST_BREAK + Enable for Last break character interrupt. + 9 + 1 + + + + + INT_FL + Interrupt Status Flags. + 0x10 + 32 + oneToClear + + + RX_FRAME_ERROR + FLAG for RX Frame Error Interrupt. + 0 + 1 + + + RX_PARITY_ERROR + FLAG for RX Parity Error interrupt. + 1 + 1 + + + CTS_CHANGE + FLAG for CTS signal change interrupt. + 2 + 1 + + + RX_OVERRUN + FLAG for RX FIFO Overrun interrupt. + 3 + 1 + + + RX_FIFO_THRESH + FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + 4 + 1 + + + TX_FIFO_ALMOST_EMPTY + FLAG for interrupt when TX FIFO has only one byte remaining. + 5 + 1 + + + TX_FIFO_THRESH + FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. + 6 + 1 + + + BREAK + FLAG for received BREAK character interrupt. + 7 + 1 + + + RX_TIMEOUT + FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). + 8 + 1 + + + LAST_BREAK + FLAG for Last break character interrupt. + 9 + 1 + + + + + BAUD0 + Baud rate register. Integer portion. + 0x14 + 32 + + + IBAUD + Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). + 0 + 12 + + + FACTOR + FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR. + 16 + 2 + + + 128 + Baud Factor 128 + 0 + + + 64 + Baud Factor 64 + 1 + + + 32 + Baud Factor 32 + 2 + + + 16 + Baud Factor 16 + 3 + + + + + + + BAUD1 + Baud rate register. Decimal Setting. + 0x18 + 32 + + + DBAUD + Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128. + 0 + 12 + + + + + FIFO + FIFO Data buffer. + 0x1C + 32 + + + FIFO + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + + + DMA + DMA Configuration. + 0x20 + 32 + + + TDMA_EN + TX DMA channel enable. + 0 + 1 + + + dis + DMA is disabled + 0 + + + en + DMA is enabled + 1 + + + + + RXDMA_EN + RX DMA channel enable. + 1 + 1 + + + dis + DMA is disabled + 0 + + + en + DMA is enabled + 1 + + + + + TXDMA_LEVEL + TX threshold for DMA transmission. + 8 + 6 + + + RXDMA_LEVEL + RX threshold for DMA transmission. + 16 + 6 + + + + + TX_FIFO + Transmit FIFO Status register. + 0x24 + 32 + + + DATA + Reading from this field returns the next character available at the + output of the TX FIFO (if one is available, otherwise 00h is returned). + 0 + 7 + + + + + + + + UART1 + UART 1 + 0x40043000 + + UART1 + UART1 IRQ + 15 + + + + + WDT0 + Watchdog Timer 0 + 0x40003000 + + 0x00 + 0x0400 + registers + + + WDT0 + 1 + + + + CTRL + Watchdog Timer Control Register. + 0x00 + 0x7FFFF000 + + + INT_PERIOD + Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 0 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_PERIOD + Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 4 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + WDT_EN + Watchdog Timer Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_FLAG + Watchdog Timer Interrupt Flag. + 9 + 1 + oneToClear + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + INT_EN + Watchdog Timer Interrupt Enable. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_EN + Watchdog Timer Reset Enable. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_FLAG + Watchdog Timer Reset Flag. + 31 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + RST + Watchdog Timer Reset Register. + 0x04 + write-only + + + WDT_RST + Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. + 0 + 8 + + + seq0 + The first value to be written to reset the WDT. + 0x000000A5 + + + seq1 + The second value to be written to reset the WDT. + 0x0000005A + + + + + + + + + + diff --git a/bsp/maxim/libraries/CMSIS/mxc_config.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/mxc_device.h similarity index 69% rename from bsp/maxim/libraries/CMSIS/mxc_config.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/mxc_device.h index ca85378d0e..26fd45058e 100644 --- a/bsp/maxim/libraries/CMSIS/mxc_config.h +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/mxc_device.h @@ -1,8 +1,3 @@ -/** - * @file mxc_config.h - * @brief Top-level include file for device configuration. - */ - /******************************************************************************* * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. * @@ -34,20 +29,44 @@ * property whatsoever. Maxim Integrated Products, Inc. retains all * ownership rights. * - * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ - * $Revision: 36818 $ + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ * ******************************************************************************/ -#ifndef _MXC_CONFIG_H -#define _MXC_CONFIG_H +/** + * @file mxc_device.h + * @brief contains device and revision specific definitions + */ + +#ifndef _MXC_DEVICE_H_ +#define _MXC_DEVICE_H_ + +#include "max32660.h" + +#ifndef TARGET + #error TARGET NOT DEFINED +#endif + +// Create a string definition for the TARGET +#define STRING_ARG(arg) #arg +#define STRING_NAME(name) STRING_ARG(name) +#define TARGET_NAME STRING_NAME(TARGET) + +// Define which revisions of the IP we are using +#ifndef TARGET_REV + #error TARGET_REV NOT DEFINED +#endif + +#if(TARGET_REV == 0x4131) + // A1 + #define MXC_PBM_REV 0 + #define MXC_TMR_REV 0 + #define MXC_UART_REV 1 +#else -#if !defined __GNUC__ -#include "RTE_Components.h" -#endif /* not __GNUC__ */ +#error TARGET_REV NOT SUPPORTED -#include "mxc_device.h" -#include "mxc_errors.h" -#include "mxc_pins.h" +#endif // if(TARGET_REV == ...) -#endif /* _CONFIG_H */ +#endif /* _MXC_DEVICE_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h new file mode 100644 index 0000000000..38c2638192 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h @@ -0,0 +1,273 @@ +/** + * @file pwrseq_regs.h + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _PWRSEQ_REGS_H_ +#define _PWRSEQ_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup pwrseq + * @defgroup pwrseq_registers PWRSEQ_Registers + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @details Power Sequencer / Low Power Control Register. + */ + +/** + * @ingroup pwrseq_registers + * Structure type to access the PWRSEQ Registers. + */ +typedef struct { + __IO uint32_t lp_ctrl; /**< \b 0x00: PWRSEQ LP_CTRL Register */ + __IO uint32_t lp_wakefl; /**< \b 0x04: PWRSEQ LP_WAKEFL Register */ + __IO uint32_t lpwk_en; /**< \b 0x08: PWRSEQ LPWK_EN Register */ + __R uint32_t rsv_0xc_0x3f[13]; + __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ +} mxc_pwrseq_regs_t; + +/* Register offsets for module PWRSEQ */ +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_Register_Offsets Register Offsets + * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. + * @{ + */ + #define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ + #define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ + #define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ + #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ +/**@} end of group pwrseq_registers */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LP_CTRL PWRSEQ_LP_CTRL + * @brief Low Power Control Register. + * @{ + */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */ + #define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */ + #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */ + #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */ + #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */ + #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_EN Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_DIS Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_EN Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_DIS Setting */ + +/**@} end of group PWRSEQ_LP_CTRL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LP_WAKEFL PWRSEQ_LP_WAKEFL + * @brief Low Power Mode Wakeup Flags for GPIO0 + * @{ + */ + #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ + #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */ + +/**@} end of group PWRSEQ_LP_WAKEFL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWK_EN PWRSEQ_LPWK_EN + * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup + * functionality for GPIO0. + * @{ + */ + #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ + #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */ + +/**@} end of group PWRSEQ_LPWK_EN_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD + * @brief Low Power Memory Shutdown Control. + * @{ + */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL Setting */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Setting */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL Setting */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Setting */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL Setting */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Setting */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL Setting */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Setting */ + +/**@} end of group PWRSEQ_LPMEMSD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _PWRSEQ_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h new file mode 100644 index 0000000000..678ed2a4e7 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h @@ -0,0 +1,297 @@ +/** + * @file rtc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _RTC_REGS_H_ +#define _RTC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup rtc + * @defgroup rtc_registers RTC_Registers + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @details Real Time Clock and Alarm. + */ + +/** + * @ingroup rtc_registers + * Structure type to access the RTC Registers. + */ +typedef struct { + __IO uint32_t sec; /**< \b 0x00: RTC SEC Register */ + __IO uint32_t ssec; /**< \b 0x04: RTC SSEC Register */ + __IO uint32_t ras; /**< \b 0x08: RTC RAS Register */ + __IO uint32_t rssa; /**< \b 0x0C: RTC RSSA Register */ + __IO uint32_t ctrl; /**< \b 0x10: RTC CTRL Register */ + __IO uint32_t trim; /**< \b 0x14: RTC TRIM Register */ + __IO uint32_t oscctrl; /**< \b 0x18: RTC OSCCTRL Register */ +} mxc_rtc_regs_t; + +/* Register offsets for module RTC */ +/** + * @ingroup rtc_registers + * @defgroup RTC_Register_Offsets Register Offsets + * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. + * @{ + */ + #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ + #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ + #define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ + #define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ + #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ + #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ + #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ +/**@} end of group rtc_registers */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSEC RTC_SSEC + * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented + * when this register rolls over from 0xFF to 0x00. + * @{ + */ + #define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ + #define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ + +/**@} end of group RTC_SSEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_RAS RTC_RAS + * @brief Time-of-day Alarm. + * @{ + */ + #define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */ + #define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */ + +/**@} end of group RTC_RAS_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_RSSA RTC_RSSA + * @brief RTC sub-second alarm. This register contains the reload value for the sub- + * second alarm. + * @{ + */ + #define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ + #define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ + +/**@} end of group RTC_RSSA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_CTRL RTC_CTRL + * @brief RTC Control Register. + * @{ + */ + #define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */ + #define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */ + #define MXC_V_RTC_CTRL_RTCE_DIS ((uint32_t)0x0UL) /**< CTRL_RTCE_DIS Value */ + #define MXC_S_RTC_CTRL_RTCE_DIS (MXC_V_RTC_CTRL_RTCE_DIS << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_DIS Setting */ + #define MXC_V_RTC_CTRL_RTCE_EN ((uint32_t)0x1UL) /**< CTRL_RTCE_EN Value */ + #define MXC_S_RTC_CTRL_RTCE_EN (MXC_V_RTC_CTRL_RTCE_EN << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_EN Setting */ + + #define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ + #define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ + #define MXC_V_RTC_CTRL_ADE_DIS ((uint32_t)0x0UL) /**< CTRL_ADE_DIS Value */ + #define MXC_S_RTC_CTRL_ADE_DIS (MXC_V_RTC_CTRL_ADE_DIS << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_DIS Setting */ + #define MXC_V_RTC_CTRL_ADE_EN ((uint32_t)0x1UL) /**< CTRL_ADE_EN Value */ + #define MXC_S_RTC_CTRL_ADE_EN (MXC_V_RTC_CTRL_ADE_EN << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_EN Setting */ + + #define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ + #define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ + #define MXC_V_RTC_CTRL_ASE_DIS ((uint32_t)0x0UL) /**< CTRL_ASE_DIS Value */ + #define MXC_S_RTC_CTRL_ASE_DIS (MXC_V_RTC_CTRL_ASE_DIS << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_DIS Setting */ + #define MXC_V_RTC_CTRL_ASE_EN ((uint32_t)0x1UL) /**< CTRL_ASE_EN Value */ + #define MXC_S_RTC_CTRL_ASE_EN (MXC_V_RTC_CTRL_ASE_EN << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_EN Setting */ + + #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ + #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + #define MXC_V_RTC_CTRL_BUSY_IDLE ((uint32_t)0x0UL) /**< CTRL_BUSY_IDLE Value */ + #define MXC_S_RTC_CTRL_BUSY_IDLE (MXC_V_RTC_CTRL_BUSY_IDLE << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_IDLE Setting */ + #define MXC_V_RTC_CTRL_BUSY_BUSY ((uint32_t)0x1UL) /**< CTRL_BUSY_BUSY Value */ + #define MXC_S_RTC_CTRL_BUSY_BUSY (MXC_V_RTC_CTRL_BUSY_BUSY << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_BUSY Setting */ + + #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ + #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + #define MXC_V_RTC_CTRL_RDY_BUSY ((uint32_t)0x0UL) /**< CTRL_RDY_BUSY Value */ + #define MXC_S_RTC_CTRL_RDY_BUSY (MXC_V_RTC_CTRL_RDY_BUSY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_BUSY Setting */ + #define MXC_V_RTC_CTRL_RDY_READY ((uint32_t)0x1UL) /**< CTRL_RDY_READY Value */ + #define MXC_S_RTC_CTRL_RDY_READY (MXC_V_RTC_CTRL_RDY_READY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_READY Setting */ + + #define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ + #define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ + #define MXC_V_RTC_CTRL_RDYE_DIS ((uint32_t)0x0UL) /**< CTRL_RDYE_DIS Value */ + #define MXC_S_RTC_CTRL_RDYE_DIS (MXC_V_RTC_CTRL_RDYE_DIS << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_DIS Setting */ + #define MXC_V_RTC_CTRL_RDYE_EN ((uint32_t)0x1UL) /**< CTRL_RDYE_EN Value */ + #define MXC_S_RTC_CTRL_RDYE_EN (MXC_V_RTC_CTRL_RDYE_EN << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_EN Setting */ + + #define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ + #define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ + #define MXC_V_RTC_CTRL_ALDF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALDF_INACTIVE Value */ + #define MXC_S_RTC_CTRL_ALDF_INACTIVE (MXC_V_RTC_CTRL_ALDF_INACTIVE << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_INACTIVE Setting */ + #define MXC_V_RTC_CTRL_ALDF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALDF_PENDING Value */ + #define MXC_S_RTC_CTRL_ALDF_PENDING (MXC_V_RTC_CTRL_ALDF_PENDING << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_PENDING Setting */ + + #define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ + #define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ + #define MXC_V_RTC_CTRL_ALSF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALSF_INACTIVE Value */ + #define MXC_S_RTC_CTRL_ALSF_INACTIVE (MXC_V_RTC_CTRL_ALSF_INACTIVE << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_INACTIVE Setting */ + #define MXC_V_RTC_CTRL_ALSF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALSF_PENDING Value */ + #define MXC_S_RTC_CTRL_ALSF_PENDING (MXC_V_RTC_CTRL_ALSF_PENDING << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_PENDING Setting */ + + #define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */ + #define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */ + #define MXC_V_RTC_CTRL_SQE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_SQE_INACTIVE Value */ + #define MXC_S_RTC_CTRL_SQE_INACTIVE (MXC_V_RTC_CTRL_SQE_INACTIVE << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_INACTIVE Setting */ + #define MXC_V_RTC_CTRL_SQE_PENDING ((uint32_t)0x1UL) /**< CTRL_SQE_PENDING Value */ + #define MXC_S_RTC_CTRL_SQE_PENDING (MXC_V_RTC_CTRL_SQE_PENDING << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_PENDING Setting */ + + #define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */ + #define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */ + #define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */ + #define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */ + #define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */ + #define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */ + #define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */ + + #define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */ + #define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */ + #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */ + #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */ + + #define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */ + #define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */ + #define MXC_V_RTC_CTRL_WE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_WE_INACTIVE Value */ + #define MXC_S_RTC_CTRL_WE_INACTIVE (MXC_V_RTC_CTRL_WE_INACTIVE << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_INACTIVE Setting */ + #define MXC_V_RTC_CTRL_WE_PENDING ((uint32_t)0x1UL) /**< CTRL_WE_PENDING Value */ + #define MXC_S_RTC_CTRL_WE_PENDING (MXC_V_RTC_CTRL_WE_PENDING << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_PENDING Setting */ + +/**@} end of group RTC_CTRL_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TRIM RTC_TRIM + * @brief RTC Trim Register. + * @{ + */ + #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ + #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ + + #define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */ + #define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */ + +/**@} end of group RTC_TRIM_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_OSCCTRL RTC_OSCCTRL + * @brief RTC Oscillator Control Register. + * @{ + */ + #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */ + #define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ + #define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ + #define MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X ((uint32_t)0x0UL) /**< OSCCTRL_IBIAS_SEL_2X Value */ + #define MXC_S_RTC_OSCCTRL_IBIAS_SEL_2X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_2X Setting */ + #define MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X ((uint32_t)0x1UL) /**< OSCCTRL_IBIAS_SEL_4X Value */ + #define MXC_S_RTC_OSCCTRL_IBIAS_SEL_4X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_4X Setting */ + + #define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ + #define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ + #define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ + #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ + + #define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */ + #define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */ + +/**@} end of group RTC_OSCCTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTC_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h new file mode 100644 index 0000000000..a48d7dc550 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h @@ -0,0 +1,255 @@ +/** + * @file sir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SIR_REGS_H_ +#define _SIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup sir + * @defgroup sir_registers SIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @details System Initialization Registers. + */ + +/** + * @ingroup sir_registers + * Structure type to access the SIR Registers. + */ +typedef struct { + __I uint32_t sistat; /**< \b 0x00: SIR SISTAT Register */ + __I uint32_t erraddr; /**< \b 0x04: SIR ERRADDR Register */ + __R uint32_t rsv_0x8_0xff[62]; + __I uint32_t fstat; /**< \b 0x100: SIR FSTAT Register */ + __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ +} mxc_sir_regs_t; + +/* Register offsets for module SIR */ +/** + * @ingroup sir_registers + * @defgroup SIR_Register_Offsets Register Offsets + * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. + * @{ + */ + #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ + #define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ + #define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: 0x0100 */ + #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ +/**@} end of group sir_registers */ + +/** + * @ingroup sir_registers + * @defgroup SIR_SISTAT SIR_SISTAT + * @brief System Initialization Status Register. + * @{ + */ + #define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */ + #define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */ + #define MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET ((uint32_t)0x0UL) /**< SISTAT_MAGIC_MAGICNOTSET Value */ + #define MXC_S_SIR_SISTAT_MAGIC_MAGICNOTSET (MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICNOTSET Setting */ + #define MXC_V_SIR_SISTAT_MAGIC_MAGICSET ((uint32_t)0x1UL) /**< SISTAT_MAGIC_MAGICSET Value */ + #define MXC_S_SIR_SISTAT_MAGIC_MAGICSET (MXC_V_SIR_SISTAT_MAGIC_MAGICSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICSET Setting */ + + #define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */ + #define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */ + #define MXC_V_SIR_SISTAT_CRCERR_NOERROR ((uint32_t)0x0UL) /**< SISTAT_CRCERR_NOERROR Value */ + #define MXC_S_SIR_SISTAT_CRCERR_NOERROR (MXC_V_SIR_SISTAT_CRCERR_NOERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_NOERROR Setting */ + #define MXC_V_SIR_SISTAT_CRCERR_ERROR ((uint32_t)0x1UL) /**< SISTAT_CRCERR_ERROR Value */ + #define MXC_S_SIR_SISTAT_CRCERR_ERROR (MXC_V_SIR_SISTAT_CRCERR_ERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_ERROR Setting */ + +/**@} end of group SIR_SISTAT_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_ERRADDR SIR_ERRADDR + * @brief Read-only field set by the SIB block if a CRC error occurs during the read of + * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals + * 1). + * @{ + */ + #define MXC_F_SIR_ERRADDR_ERRADDR_POS 0 /**< ERRADDR_ERRADDR Position */ + #define MXC_F_SIR_ERRADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ERRADDR_ERRADDR_POS)) /**< ERRADDR_ERRADDR Mask */ + +/**@} end of group SIR_ERRADDR_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_FSTAT SIR_FSTAT + * @brief funcstat register. + * @{ + */ + #define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ + #define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */ + #define MXC_V_SIR_FSTAT_FPU_NO ((uint32_t)0x0UL) /**< FSTAT_FPU_NO Value */ + #define MXC_S_SIR_FSTAT_FPU_NO (MXC_V_SIR_FSTAT_FPU_NO << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_NO Setting */ + #define MXC_V_SIR_FSTAT_FPU_YES ((uint32_t)0x1UL) /**< FSTAT_FPU_YES Value */ + #define MXC_S_SIR_FSTAT_FPU_YES (MXC_V_SIR_FSTAT_FPU_YES << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_YES Setting */ + + #define MXC_F_SIR_FSTAT_USB_POS 1 /**< FSTAT_USB Position */ + #define MXC_F_SIR_FSTAT_USB ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */ + #define MXC_V_SIR_FSTAT_USB_NO ((uint32_t)0x0UL) /**< FSTAT_USB_NO Value */ + #define MXC_S_SIR_FSTAT_USB_NO (MXC_V_SIR_FSTAT_USB_NO << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_NO Setting */ + #define MXC_V_SIR_FSTAT_USB_YES ((uint32_t)0x1UL) /**< FSTAT_USB_YES Value */ + #define MXC_S_SIR_FSTAT_USB_YES (MXC_V_SIR_FSTAT_USB_YES << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_YES Setting */ + + #define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */ + #define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */ + #define MXC_V_SIR_FSTAT_ADC_NO ((uint32_t)0x0UL) /**< FSTAT_ADC_NO Value */ + #define MXC_S_SIR_FSTAT_ADC_NO (MXC_V_SIR_FSTAT_ADC_NO << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_NO Setting */ + #define MXC_V_SIR_FSTAT_ADC_YES ((uint32_t)0x1UL) /**< FSTAT_ADC_YES Value */ + #define MXC_S_SIR_FSTAT_ADC_YES (MXC_V_SIR_FSTAT_ADC_YES << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_YES Setting */ + + #define MXC_F_SIR_FSTAT_XIP_POS 3 /**< FSTAT_XIP Position */ + #define MXC_F_SIR_FSTAT_XIP ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_XIP_POS)) /**< FSTAT_XIP Mask */ + #define MXC_V_SIR_FSTAT_XIP_NO ((uint32_t)0x0UL) /**< FSTAT_XIP_NO Value */ + #define MXC_S_SIR_FSTAT_XIP_NO (MXC_V_SIR_FSTAT_XIP_NO << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_NO Setting */ + #define MXC_V_SIR_FSTAT_XIP_YES ((uint32_t)0x1UL) /**< FSTAT_XIP_YES Value */ + #define MXC_S_SIR_FSTAT_XIP_YES (MXC_V_SIR_FSTAT_XIP_YES << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_YES Setting */ + + #define MXC_F_SIR_FSTAT_PBM_POS 4 /**< FSTAT_PBM Position */ + #define MXC_F_SIR_FSTAT_PBM ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_PBM_POS)) /**< FSTAT_PBM Mask */ + #define MXC_V_SIR_FSTAT_PBM_NO ((uint32_t)0x0UL) /**< FSTAT_PBM_NO Value */ + #define MXC_S_SIR_FSTAT_PBM_NO (MXC_V_SIR_FSTAT_PBM_NO << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_NO Setting */ + #define MXC_V_SIR_FSTAT_PBM_YES ((uint32_t)0x1UL) /**< FSTAT_PBM_YES Value */ + #define MXC_S_SIR_FSTAT_PBM_YES (MXC_V_SIR_FSTAT_PBM_YES << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_YES Setting */ + + #define MXC_F_SIR_FSTAT_HBC_POS 5 /**< FSTAT_HBC Position */ + #define MXC_F_SIR_FSTAT_HBC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_HBC_POS)) /**< FSTAT_HBC Mask */ + #define MXC_V_SIR_FSTAT_HBC_NO ((uint32_t)0x0UL) /**< FSTAT_HBC_NO Value */ + #define MXC_S_SIR_FSTAT_HBC_NO (MXC_V_SIR_FSTAT_HBC_NO << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_NO Setting */ + #define MXC_V_SIR_FSTAT_HBC_YES ((uint32_t)0x1UL) /**< FSTAT_HBC_YES Value */ + #define MXC_S_SIR_FSTAT_HBC_YES (MXC_V_SIR_FSTAT_HBC_YES << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_YES Setting */ + + #define MXC_F_SIR_FSTAT_SDHC_POS 6 /**< FSTAT_SDHC Position */ + #define MXC_F_SIR_FSTAT_SDHC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SDHC_POS)) /**< FSTAT_SDHC Mask */ + #define MXC_V_SIR_FSTAT_SDHC_NO ((uint32_t)0x0UL) /**< FSTAT_SDHC_NO Value */ + #define MXC_S_SIR_FSTAT_SDHC_NO (MXC_V_SIR_FSTAT_SDHC_NO << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_NO Setting */ + #define MXC_V_SIR_FSTAT_SDHC_YES ((uint32_t)0x1UL) /**< FSTAT_SDHC_YES Value */ + #define MXC_S_SIR_FSTAT_SDHC_YES (MXC_V_SIR_FSTAT_SDHC_YES << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_YES Setting */ + + #define MXC_F_SIR_FSTAT_SMPHR_POS 7 /**< FSTAT_SMPHR Position */ + #define MXC_F_SIR_FSTAT_SMPHR ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */ + #define MXC_V_SIR_FSTAT_SMPHR_NO ((uint32_t)0x0UL) /**< FSTAT_SMPHR_NO Value */ + #define MXC_S_SIR_FSTAT_SMPHR_NO (MXC_V_SIR_FSTAT_SMPHR_NO << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_NO Setting */ + #define MXC_V_SIR_FSTAT_SMPHR_YES ((uint32_t)0x1UL) /**< FSTAT_SMPHR_YES Value */ + #define MXC_S_SIR_FSTAT_SMPHR_YES (MXC_V_SIR_FSTAT_SMPHR_YES << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_YES Setting */ + + #define MXC_F_SIR_FSTAT_SCACHE_POS 8 /**< FSTAT_SCACHE Position */ + #define MXC_F_SIR_FSTAT_SCACHE ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SCACHE_POS)) /**< FSTAT_SCACHE Mask */ + #define MXC_V_SIR_FSTAT_SCACHE_NO ((uint32_t)0x0UL) /**< FSTAT_SCACHE_NO Value */ + #define MXC_S_SIR_FSTAT_SCACHE_NO (MXC_V_SIR_FSTAT_SCACHE_NO << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_NO Setting */ + #define MXC_V_SIR_FSTAT_SCACHE_YES ((uint32_t)0x1UL) /**< FSTAT_SCACHE_YES Value */ + #define MXC_S_SIR_FSTAT_SCACHE_YES (MXC_V_SIR_FSTAT_SCACHE_YES << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_YES Setting */ + +/**@} end of group SIR_FSTAT_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_SFSTAT SIR_SFSTAT + * @brief secfuncstat register. + * @{ + */ + #define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */ + #define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */ + #define MXC_V_SIR_SFSTAT_TRNG_NO ((uint32_t)0x0UL) /**< SFSTAT_TRNG_NO Value */ + #define MXC_S_SIR_SFSTAT_TRNG_NO (MXC_V_SIR_SFSTAT_TRNG_NO << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_NO Setting */ + #define MXC_V_SIR_SFSTAT_TRNG_YES ((uint32_t)0x1UL) /**< SFSTAT_TRNG_YES Value */ + #define MXC_S_SIR_SFSTAT_TRNG_YES (MXC_V_SIR_SFSTAT_TRNG_YES << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_YES Setting */ + + #define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */ + #define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */ + #define MXC_V_SIR_SFSTAT_AES_NO ((uint32_t)0x0UL) /**< SFSTAT_AES_NO Value */ + #define MXC_S_SIR_SFSTAT_AES_NO (MXC_V_SIR_SFSTAT_AES_NO << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_NO Setting */ + #define MXC_V_SIR_SFSTAT_AES_YES ((uint32_t)0x1UL) /**< SFSTAT_AES_YES Value */ + #define MXC_S_SIR_SFSTAT_AES_YES (MXC_V_SIR_SFSTAT_AES_YES << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_YES Setting */ + + #define MXC_F_SIR_SFSTAT_SHA_POS 4 /**< SFSTAT_SHA Position */ + #define MXC_F_SIR_SFSTAT_SHA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHA_POS)) /**< SFSTAT_SHA Mask */ + #define MXC_V_SIR_SFSTAT_SHA_NO ((uint32_t)0x0UL) /**< SFSTAT_SHA_NO Value */ + #define MXC_S_SIR_SFSTAT_SHA_NO (MXC_V_SIR_SFSTAT_SHA_NO << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_NO Setting */ + #define MXC_V_SIR_SFSTAT_SHA_YES ((uint32_t)0x1UL) /**< SFSTAT_SHA_YES Value */ + #define MXC_S_SIR_SFSTAT_SHA_YES (MXC_V_SIR_SFSTAT_SHA_YES << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_YES Setting */ + + #define MXC_F_SIR_SFSTAT_MAA_POS 5 /**< SFSTAT_MAA Position */ + #define MXC_F_SIR_SFSTAT_MAA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_MAA_POS)) /**< SFSTAT_MAA Mask */ + #define MXC_V_SIR_SFSTAT_MAA_NO ((uint32_t)0x0UL) /**< SFSTAT_MAA_NO Value */ + #define MXC_S_SIR_SFSTAT_MAA_NO (MXC_V_SIR_SFSTAT_MAA_NO << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_NO Setting */ + #define MXC_V_SIR_SFSTAT_MAA_YES ((uint32_t)0x1UL) /**< SFSTAT_MAA_YES Value */ + #define MXC_S_SIR_SFSTAT_MAA_YES (MXC_V_SIR_SFSTAT_MAA_YES << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_YES Setting */ + +/**@} end of group SIR_SFSTAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SIR_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/smon_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/smon_regs.h new file mode 100644 index 0000000000..82508d53c3 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/smon_regs.h @@ -0,0 +1,628 @@ +/** + * @file smon_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SMON_REGS_H_ +#define _SMON_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup smon + * @defgroup smon_registers SMON_Registers + * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. + * @details The Security Monitor block used to monitor system threat conditions. + */ + +/** + * @ingroup smon_registers + * Structure type to access the SMON Registers. + */ +typedef struct { + __IO uint32_t extscn; /**< \b 0x00: SMON EXTSCN Register */ + __IO uint32_t intscn; /**< \b 0x04: SMON INTSCN Register */ + __IO uint32_t secalm; /**< \b 0x08: SMON SECALM Register */ + __I uint32_t secdiag; /**< \b 0x0C: SMON SECDIAG Register */ + __I uint32_t dlrtc; /**< \b 0x10: SMON DLRTC Register */ + __R uint32_t rsv_0x14_0x33[8]; + __I uint32_t secst; /**< \b 0x34: SMON SECST Register */ +} mxc_smon_regs_t; + +/* Register offsets for module SMON */ +/** + * @ingroup smon_registers + * @defgroup SMON_Register_Offsets Register Offsets + * @brief SMON Peripheral Register Offsets from the SMON Base Peripheral Address. + * @{ + */ + #define MXC_R_SMON_EXTSCN ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: 0x0000 */ + #define MXC_R_SMON_INTSCN ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: 0x0004 */ + #define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: 0x0008 */ + #define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: 0x000C */ + #define MXC_R_SMON_DLRTC ((uint32_t)0x00000010UL) /**< Offset from SMON Base Address: 0x0010 */ + #define MXC_R_SMON_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: 0x0034 */ +/**@} end of group smon_registers */ + +/** + * @ingroup smon_registers + * @defgroup SMON_EXTSCN SMON_EXTSCN + * @brief External Sensor Control Register. + * @{ + */ + #define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0 /**< EXTSCN_EXTS_EN0 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN0_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN0_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN0_DIS (MXC_V_SMON_EXTSCN_EXTS_EN0_DIS << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN0_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN0_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN0_EN (MXC_V_SMON_EXTSCN_EXTS_EN0_EN << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1 /**< EXTSCN_EXTS_EN1 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN1_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN1_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN1_DIS (MXC_V_SMON_EXTSCN_EXTS_EN1_DIS << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN1_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN1_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN1_EN (MXC_V_SMON_EXTSCN_EXTS_EN1_EN << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2 /**< EXTSCN_EXTS_EN2 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN2_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN2_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN2_DIS (MXC_V_SMON_EXTSCN_EXTS_EN2_DIS << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN2_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN2_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN2_EN (MXC_V_SMON_EXTSCN_EXTS_EN2_EN << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3 /**< EXTSCN_EXTS_EN3 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN3_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN3_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN3_DIS (MXC_V_SMON_EXTSCN_EXTS_EN3_DIS << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN3_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN3_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN3_EN (MXC_V_SMON_EXTSCN_EXTS_EN3_EN << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4 /**< EXTSCN_EXTS_EN4 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN4_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN4_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN4_DIS (MXC_V_SMON_EXTSCN_EXTS_EN4_DIS << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN4_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN4_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN4_EN (MXC_V_SMON_EXTSCN_EXTS_EN4_EN << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5 /**< EXTSCN_EXTS_EN5 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN5_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN5_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN5_DIS (MXC_V_SMON_EXTSCN_EXTS_EN5_DIS << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN5_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN5_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN5_EN (MXC_V_SMON_EXTSCN_EXTS_EN5_EN << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTCNT_POS 16 /**< EXTSCN_EXTCNT Position */ + #define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */ + + #define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21 /**< EXTSCN_EXTFRQ Position */ + #define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_RFU (MXC_V_SMON_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */ + + #define MXC_F_SMON_EXTSCN_DIVCLK_POS 24 /**< EXTSCN_DIVCLK Position */ + #define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */ + + #define MXC_F_SMON_EXTSCN_BUSY_POS 30 /**< EXTSCN_BUSY Position */ + #define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */ + #define MXC_V_SMON_EXTSCN_BUSY_IDLE ((uint32_t)0x0UL) /**< EXTSCN_BUSY_IDLE Value */ + #define MXC_S_SMON_EXTSCN_BUSY_IDLE (MXC_V_SMON_EXTSCN_BUSY_IDLE << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_IDLE Setting */ + #define MXC_V_SMON_EXTSCN_BUSY_BUSY ((uint32_t)0x1UL) /**< EXTSCN_BUSY_BUSY Value */ + #define MXC_S_SMON_EXTSCN_BUSY_BUSY (MXC_V_SMON_EXTSCN_BUSY_BUSY << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_BUSY Setting */ + + #define MXC_F_SMON_EXTSCN_LOCK_POS 31 /**< EXTSCN_LOCK Position */ + #define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */ + #define MXC_V_SMON_EXTSCN_LOCK_UNLOCKED ((uint32_t)0x0UL) /**< EXTSCN_LOCK_UNLOCKED Value */ + #define MXC_S_SMON_EXTSCN_LOCK_UNLOCKED (MXC_V_SMON_EXTSCN_LOCK_UNLOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_UNLOCKED Setting */ + #define MXC_V_SMON_EXTSCN_LOCK_LOCKED ((uint32_t)0x1UL) /**< EXTSCN_LOCK_LOCKED Value */ + #define MXC_S_SMON_EXTSCN_LOCK_LOCKED (MXC_V_SMON_EXTSCN_LOCK_LOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_LOCKED Setting */ + +/**@} end of group SMON_EXTSCN_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_INTSCN SMON_INTSCN + * @brief Internal Sensor Control Register. + * @{ + */ + #define MXC_F_SMON_INTSCN_SHIELD_EN_POS 0 /**< INTSCN_SHIELD_EN Position */ + #define MXC_F_SMON_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */ + #define MXC_V_SMON_INTSCN_SHIELD_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_SHIELD_EN_DIS Value */ + #define MXC_S_SMON_INTSCN_SHIELD_EN_DIS (MXC_V_SMON_INTSCN_SHIELD_EN_DIS << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_DIS Setting */ + #define MXC_V_SMON_INTSCN_SHIELD_EN_EN ((uint32_t)0x1UL) /**< INTSCN_SHIELD_EN_EN Value */ + #define MXC_S_SMON_INTSCN_SHIELD_EN_EN (MXC_V_SMON_INTSCN_SHIELD_EN_EN << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_EN Setting */ + + #define MXC_F_SMON_INTSCN_TEMP_EN_POS 1 /**< INTSCN_TEMP_EN Position */ + #define MXC_F_SMON_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */ + #define MXC_V_SMON_INTSCN_TEMP_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_TEMP_EN_DIS Value */ + #define MXC_S_SMON_INTSCN_TEMP_EN_DIS (MXC_V_SMON_INTSCN_TEMP_EN_DIS << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_DIS Setting */ + #define MXC_V_SMON_INTSCN_TEMP_EN_EN ((uint32_t)0x1UL) /**< INTSCN_TEMP_EN_EN Value */ + #define MXC_S_SMON_INTSCN_TEMP_EN_EN (MXC_V_SMON_INTSCN_TEMP_EN_EN << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VBAT_EN_POS 2 /**< INTSCN_VBAT_EN Position */ + #define MXC_F_SMON_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */ + #define MXC_V_SMON_INTSCN_VBAT_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_VBAT_EN_DIS Value */ + #define MXC_S_SMON_INTSCN_VBAT_EN_DIS (MXC_V_SMON_INTSCN_VBAT_EN_DIS << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VBAT_EN_EN ((uint32_t)0x1UL) /**< INTSCN_VBAT_EN_EN Value */ + #define MXC_S_SMON_INTSCN_VBAT_EN_EN (MXC_V_SMON_INTSCN_VBAT_EN_EN << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_EN Setting */ + + #define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS 16 /**< INTSCN_LOTEMP_SEL Position */ + #define MXC_F_SMON_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */ + #define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C ((uint32_t)0x0UL) /**< INTSCN_LOTEMP_SEL_NEG50C Value */ + #define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG50C (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG50C Setting */ + #define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C ((uint32_t)0x1UL) /**< INTSCN_LOTEMP_SEL_NEG30C Value */ + #define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG30C (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG30C Setting */ + + #define MXC_F_SMON_INTSCN_VCORELOEN_POS 18 /**< INTSCN_VCORELOEN Position */ + #define MXC_F_SMON_INTSCN_VCORELOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCORELOEN_POS)) /**< INTSCN_VCORELOEN Mask */ + #define MXC_V_SMON_INTSCN_VCORELOEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VCORELOEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VCORELOEN_DIS (MXC_V_SMON_INTSCN_VCORELOEN_DIS << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VCORELOEN_EN ((uint32_t)0x1UL) /**< INTSCN_VCORELOEN_EN Value */ + #define MXC_S_SMON_INTSCN_VCORELOEN_EN (MXC_V_SMON_INTSCN_VCORELOEN_EN << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VCOREHIEN_POS 19 /**< INTSCN_VCOREHIEN Position */ + #define MXC_F_SMON_INTSCN_VCOREHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCOREHIEN_POS)) /**< INTSCN_VCOREHIEN Mask */ + #define MXC_V_SMON_INTSCN_VCOREHIEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VCOREHIEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VCOREHIEN_DIS (MXC_V_SMON_INTSCN_VCOREHIEN_DIS << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VCOREHIEN_EN ((uint32_t)0x1UL) /**< INTSCN_VCOREHIEN_EN Value */ + #define MXC_S_SMON_INTSCN_VCOREHIEN_EN (MXC_V_SMON_INTSCN_VCOREHIEN_EN << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VDDLOEN_POS 20 /**< INTSCN_VDDLOEN Position */ + #define MXC_F_SMON_INTSCN_VDDLOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDLOEN_POS)) /**< INTSCN_VDDLOEN Mask */ + #define MXC_V_SMON_INTSCN_VDDLOEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VDDLOEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VDDLOEN_DIS (MXC_V_SMON_INTSCN_VDDLOEN_DIS << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VDDLOEN_EN ((uint32_t)0x1UL) /**< INTSCN_VDDLOEN_EN Value */ + #define MXC_S_SMON_INTSCN_VDDLOEN_EN (MXC_V_SMON_INTSCN_VDDLOEN_EN << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VDDHIEN_POS 21 /**< INTSCN_VDDHIEN Position */ + #define MXC_F_SMON_INTSCN_VDDHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDHIEN_POS)) /**< INTSCN_VDDHIEN Mask */ + #define MXC_V_SMON_INTSCN_VDDHIEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VDDHIEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VDDHIEN_DIS (MXC_V_SMON_INTSCN_VDDHIEN_DIS << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VDDHIEN_EN ((uint32_t)0x1UL) /**< INTSCN_VDDHIEN_EN Value */ + #define MXC_S_SMON_INTSCN_VDDHIEN_EN (MXC_V_SMON_INTSCN_VDDHIEN_EN << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VGLEN_POS 22 /**< INTSCN_VGLEN Position */ + #define MXC_F_SMON_INTSCN_VGLEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VGLEN_POS)) /**< INTSCN_VGLEN Mask */ + #define MXC_V_SMON_INTSCN_VGLEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VGLEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VGLEN_DIS (MXC_V_SMON_INTSCN_VGLEN_DIS << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VGLEN_EN ((uint32_t)0x1UL) /**< INTSCN_VGLEN_EN Value */ + #define MXC_S_SMON_INTSCN_VGLEN_EN (MXC_V_SMON_INTSCN_VGLEN_EN << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_LOCK_POS 31 /**< INTSCN_LOCK Position */ + #define MXC_F_SMON_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */ + #define MXC_V_SMON_INTSCN_LOCK_UNLOCKED ((uint32_t)0x0UL) /**< INTSCN_LOCK_UNLOCKED Value */ + #define MXC_S_SMON_INTSCN_LOCK_UNLOCKED (MXC_V_SMON_INTSCN_LOCK_UNLOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_UNLOCKED Setting */ + #define MXC_V_SMON_INTSCN_LOCK_LOCKED ((uint32_t)0x1UL) /**< INTSCN_LOCK_LOCKED Value */ + #define MXC_S_SMON_INTSCN_LOCK_LOCKED (MXC_V_SMON_INTSCN_LOCK_LOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_LOCKED Setting */ + +/**@} end of group SMON_INTSCN_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_SECALM SMON_SECALM + * @brief Security Alarm Register. + * @{ + */ + #define MXC_F_SMON_SECALM_DRS_POS 0 /**< SECALM_DRS Position */ + #define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */ + #define MXC_V_SMON_SECALM_DRS_COMPLETE ((uint32_t)0x0UL) /**< SECALM_DRS_COMPLETE Value */ + #define MXC_S_SMON_SECALM_DRS_COMPLETE (MXC_V_SMON_SECALM_DRS_COMPLETE << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_COMPLETE Setting */ + #define MXC_V_SMON_SECALM_DRS_START ((uint32_t)0x1UL) /**< SECALM_DRS_START Value */ + #define MXC_S_SMON_SECALM_DRS_START (MXC_V_SMON_SECALM_DRS_START << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_START Setting */ + + #define MXC_F_SMON_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */ + #define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */ + #define MXC_V_SMON_SECALM_KEYWIPE_COMPLETE ((uint32_t)0x0UL) /**< SECALM_KEYWIPE_COMPLETE Value */ + #define MXC_S_SMON_SECALM_KEYWIPE_COMPLETE (MXC_V_SMON_SECALM_KEYWIPE_COMPLETE << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_COMPLETE Setting */ + #define MXC_V_SMON_SECALM_KEYWIPE_START ((uint32_t)0x1UL) /**< SECALM_KEYWIPE_START Value */ + #define MXC_S_SMON_SECALM_KEYWIPE_START (MXC_V_SMON_SECALM_KEYWIPE_START << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_START Setting */ + + #define MXC_F_SMON_SECALM_SHIELDF_POS 2 /**< SECALM_SHIELDF Position */ + #define MXC_F_SMON_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */ + #define MXC_V_SMON_SECALM_SHIELDF_NOEVENT ((uint32_t)0x0UL) /**< SECALM_SHIELDF_NOEVENT Value */ + #define MXC_S_SMON_SECALM_SHIELDF_NOEVENT (MXC_V_SMON_SECALM_SHIELDF_NOEVENT << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_SHIELDF_OCCURRED ((uint32_t)0x1UL) /**< SECALM_SHIELDF_OCCURRED Value */ + #define MXC_S_SMON_SECALM_SHIELDF_OCCURRED (MXC_V_SMON_SECALM_SHIELDF_OCCURRED << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_LOTEMP_POS 3 /**< SECALM_LOTEMP Position */ + #define MXC_F_SMON_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */ + #define MXC_V_SMON_SECALM_LOTEMP_NOEVENT ((uint32_t)0x0UL) /**< SECALM_LOTEMP_NOEVENT Value */ + #define MXC_S_SMON_SECALM_LOTEMP_NOEVENT (MXC_V_SMON_SECALM_LOTEMP_NOEVENT << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_LOTEMP_OCCURRED ((uint32_t)0x1UL) /**< SECALM_LOTEMP_OCCURRED Value */ + #define MXC_S_SMON_SECALM_LOTEMP_OCCURRED (MXC_V_SMON_SECALM_LOTEMP_OCCURRED << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_HITEMP_POS 4 /**< SECALM_HITEMP Position */ + #define MXC_F_SMON_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */ + #define MXC_V_SMON_SECALM_HITEMP_NOEVENT ((uint32_t)0x0UL) /**< SECALM_HITEMP_NOEVENT Value */ + #define MXC_S_SMON_SECALM_HITEMP_NOEVENT (MXC_V_SMON_SECALM_HITEMP_NOEVENT << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_HITEMP_OCCURRED ((uint32_t)0x1UL) /**< SECALM_HITEMP_OCCURRED Value */ + #define MXC_S_SMON_SECALM_HITEMP_OCCURRED (MXC_V_SMON_SECALM_HITEMP_OCCURRED << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_BATLO_POS 5 /**< SECALM_BATLO Position */ + #define MXC_F_SMON_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */ + #define MXC_V_SMON_SECALM_BATLO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_BATLO_NOEVENT Value */ + #define MXC_S_SMON_SECALM_BATLO_NOEVENT (MXC_V_SMON_SECALM_BATLO_NOEVENT << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_BATLO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_BATLO_OCCURRED Value */ + #define MXC_S_SMON_SECALM_BATLO_OCCURRED (MXC_V_SMON_SECALM_BATLO_OCCURRED << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_BATHI_POS 6 /**< SECALM_BATHI Position */ + #define MXC_F_SMON_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */ + #define MXC_V_SMON_SECALM_BATHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_BATHI_NOEVENT Value */ + #define MXC_S_SMON_SECALM_BATHI_NOEVENT (MXC_V_SMON_SECALM_BATHI_NOEVENT << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_BATHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_BATHI_OCCURRED Value */ + #define MXC_S_SMON_SECALM_BATHI_OCCURRED (MXC_V_SMON_SECALM_BATHI_OCCURRED << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTF_POS 7 /**< SECALM_EXTF Position */ + #define MXC_F_SMON_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */ + #define MXC_V_SMON_SECALM_EXTF_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTF_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTF_NOEVENT (MXC_V_SMON_SECALM_EXTF_NOEVENT << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTF_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTF_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTF_OCCURRED (MXC_V_SMON_SECALM_EXTF_OCCURRED << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VDDLO_POS 8 /**< SECALM_VDDLO Position */ + #define MXC_F_SMON_SECALM_VDDLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDLO_POS)) /**< SECALM_VDDLO Mask */ + #define MXC_V_SMON_SECALM_VDDLO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VDDLO_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VDDLO_NOEVENT (MXC_V_SMON_SECALM_VDDLO_NOEVENT << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VDDLO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VDDLO_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VDDLO_OCCURRED (MXC_V_SMON_SECALM_VDDLO_OCCURRED << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VCORELO_POS 9 /**< SECALM_VCORELO Position */ + #define MXC_F_SMON_SECALM_VCORELO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCORELO_POS)) /**< SECALM_VCORELO Mask */ + #define MXC_V_SMON_SECALM_VCORELO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VCORELO_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VCORELO_NOEVENT (MXC_V_SMON_SECALM_VCORELO_NOEVENT << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VCORELO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VCORELO_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VCORELO_OCCURRED (MXC_V_SMON_SECALM_VCORELO_OCCURRED << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VCOREHI_POS 10 /**< SECALM_VCOREHI Position */ + #define MXC_F_SMON_SECALM_VCOREHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_POS)) /**< SECALM_VCOREHI Mask */ + #define MXC_V_SMON_SECALM_VCOREHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VCOREHI_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VCOREHI_NOEVENT (MXC_V_SMON_SECALM_VCOREHI_NOEVENT << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VCOREHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VCOREHI_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VCOREHI_OCCURRED (MXC_V_SMON_SECALM_VCOREHI_OCCURRED << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VDDHI_POS 11 /**< SECALM_VDDHI Position */ + #define MXC_F_SMON_SECALM_VDDHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_POS)) /**< SECALM_VDDHI Mask */ + #define MXC_V_SMON_SECALM_VDDHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VDDHI_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VDDHI_NOEVENT (MXC_V_SMON_SECALM_VDDHI_NOEVENT << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VDDHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VDDHI_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VDDHI_OCCURRED (MXC_V_SMON_SECALM_VDDHI_OCCURRED << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VGL_POS 12 /**< SECALM_VGL Position */ + #define MXC_F_SMON_SECALM_VGL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_POS)) /**< SECALM_VGL Mask */ + #define MXC_V_SMON_SECALM_VGL_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VGL_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VGL_NOEVENT (MXC_V_SMON_SECALM_VGL_NOEVENT << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VGL_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VGL_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VGL_OCCURRED (MXC_V_SMON_SECALM_VGL_OCCURRED << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT0_POS 16 /**< SECALM_EXTSTAT0 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT0_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT0_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT0_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT0_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT1_POS 17 /**< SECALM_EXTSTAT1 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT1_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT1_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT1_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT1_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT2_POS 18 /**< SECALM_EXTSTAT2 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT2_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT2_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT2_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT2_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT3_POS 19 /**< SECALM_EXTSTAT3 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT3_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT3_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT3_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT3_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT4_POS 20 /**< SECALM_EXTSTAT4 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT4_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT4_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT4_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT4_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT5_POS 21 /**< SECALM_EXTSTAT5 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT5_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT5_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT5_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT5_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN0_POS 24 /**< SECALM_EXTSWARN0 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN0_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN0_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN0_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN0_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN1_POS 25 /**< SECALM_EXTSWARN1 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN1_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN1_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN1_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN1_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN2_POS 26 /**< SECALM_EXTSWARN2 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN2_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN2_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN2_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN2_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN3_POS 27 /**< SECALM_EXTSWARN3 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN3_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN3_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN3_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN3_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN4_POS 28 /**< SECALM_EXTSWARN4 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN4_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN4_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN4_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN4_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN5_POS 29 /**< SECALM_EXTSWARN5 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN5_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN5_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN5_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN5_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_OCCURRED Setting */ + +/**@} end of group SMON_SECALM_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_SECDIAG SMON_SECDIAG + * @brief Security Diagnostic Register. + * @{ + */ + #define MXC_F_SMON_SECDIAG_BORF_POS 0 /**< SECDIAG_BORF Position */ + #define MXC_F_SMON_SECDIAG_BORF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BORF_POS)) /**< SECDIAG_BORF Mask */ + #define MXC_V_SMON_SECDIAG_BORF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BORF_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_BORF_NOEVENT (MXC_V_SMON_SECDIAG_BORF_NOEVENT << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_BORF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BORF_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_BORF_OCCURRED (MXC_V_SMON_SECDIAG_BORF_OCCURRED << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_SHIELDF_POS 2 /**< SECDIAG_SHIELDF Position */ + #define MXC_F_SMON_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */ + #define MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_SHIELDF_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_SHIELDF_NOEVENT (MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_SHIELDF_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_SHIELDF_OCCURRED (MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_LOTEMP_POS 3 /**< SECDIAG_LOTEMP Position */ + #define MXC_F_SMON_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */ + #define MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_LOTEMP_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_LOTEMP_NOEVENT (MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_LOTEMP_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_LOTEMP_OCCURRED (MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_HITEMP_POS 4 /**< SECDIAG_HITEMP Position */ + #define MXC_F_SMON_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */ + #define MXC_V_SMON_SECDIAG_HITEMP_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_HITEMP_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_HITEMP_NOEVENT (MXC_V_SMON_SECDIAG_HITEMP_NOEVENT << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_HITEMP_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_HITEMP_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_HITEMP_OCCURRED (MXC_V_SMON_SECDIAG_HITEMP_OCCURRED << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_BATLO_POS 5 /**< SECDIAG_BATLO Position */ + #define MXC_F_SMON_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */ + #define MXC_V_SMON_SECDIAG_BATLO_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BATLO_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_BATLO_NOEVENT (MXC_V_SMON_SECDIAG_BATLO_NOEVENT << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_BATLO_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BATLO_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_BATLO_OCCURRED (MXC_V_SMON_SECDIAG_BATLO_OCCURRED << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_BATHI_POS 6 /**< SECDIAG_BATHI Position */ + #define MXC_F_SMON_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */ + #define MXC_V_SMON_SECDIAG_BATHI_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BATHI_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_BATHI_NOEVENT (MXC_V_SMON_SECDIAG_BATHI_NOEVENT << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_BATHI_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BATHI_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_BATHI_OCCURRED (MXC_V_SMON_SECDIAG_BATHI_OCCURRED << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_DYNF_POS 7 /**< SECDIAG_DYNF Position */ + #define MXC_F_SMON_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */ + #define MXC_V_SMON_SECDIAG_DYNF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_DYNF_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_DYNF_NOEVENT (MXC_V_SMON_SECDIAG_DYNF_NOEVENT << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_DYNF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_DYNF_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_DYNF_OCCURRED (MXC_V_SMON_SECDIAG_DYNF_OCCURRED << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_AESKT_POS 8 /**< SECDIAG_AESKT Position */ + #define MXC_F_SMON_SECDIAG_AESKT ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_POS)) /**< SECDIAG_AESKT Mask */ + #define MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE ((uint32_t)0x0UL) /**< SECDIAG_AESKT_INCOMPLETE Value */ + #define MXC_S_SMON_SECDIAG_AESKT_INCOMPLETE (MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_INCOMPLETE Setting */ + #define MXC_V_SMON_SECDIAG_AESKT_COMPLETE ((uint32_t)0x1UL) /**< SECDIAG_AESKT_COMPLETE Value */ + #define MXC_S_SMON_SECDIAG_AESKT_COMPLETE (MXC_V_SMON_SECDIAG_AESKT_COMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_COMPLETE Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT0_POS 16 /**< SECDIAG_EXTSTAT0 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT0_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT0_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT0_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT0_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT1_POS 17 /**< SECDIAG_EXTSTAT1 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT1_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT1_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT1_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT1_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT2_POS 18 /**< SECDIAG_EXTSTAT2 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT2_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT2_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT2_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT2_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT3_POS 19 /**< SECDIAG_EXTSTAT3 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT3_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT3_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT3_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT3_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT4_POS 20 /**< SECDIAG_EXTSTAT4 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT4_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT4_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT4_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT4_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT5_POS 21 /**< SECDIAG_EXTSTAT5 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT5_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT5_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT5_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT5_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_OCCURRED Setting */ + +/**@} end of group SMON_SECDIAG_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_DLRTC SMON_DLRTC + * @brief DRS Log RTC Value. This register contains the 32 bit value in the RTC second + * register when the last DRS event occurred. + * @{ + */ + #define MXC_F_SMON_DLRTC_DLRTC_POS 0 /**< DLRTC_DLRTC Position */ + #define MXC_F_SMON_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */ + +/**@} end of group SMON_DLRTC_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_SECST SMON_SECST + * @brief Security Monitor Status Register. + * @{ + */ + #define MXC_F_SMON_SECST_EXTSRS_POS 0 /**< SECST_EXTSRS Position */ + #define MXC_F_SMON_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */ + #define MXC_V_SMON_SECST_EXTSRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_EXTSRS_ALLOWED Value */ + #define MXC_S_SMON_SECST_EXTSRS_ALLOWED (MXC_V_SMON_SECST_EXTSRS_ALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_ALLOWED Setting */ + #define MXC_V_SMON_SECST_EXTSRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_EXTSRS_NOTALLOWED Value */ + #define MXC_S_SMON_SECST_EXTSRS_NOTALLOWED (MXC_V_SMON_SECST_EXTSRS_NOTALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_NOTALLOWED Setting */ + + #define MXC_F_SMON_SECST_INTSRS_POS 1 /**< SECST_INTSRS Position */ + #define MXC_F_SMON_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */ + #define MXC_V_SMON_SECST_INTSRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_INTSRS_ALLOWED Value */ + #define MXC_S_SMON_SECST_INTSRS_ALLOWED (MXC_V_SMON_SECST_INTSRS_ALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_ALLOWED Setting */ + #define MXC_V_SMON_SECST_INTSRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_INTSRS_NOTALLOWED Value */ + #define MXC_S_SMON_SECST_INTSRS_NOTALLOWED (MXC_V_SMON_SECST_INTSRS_NOTALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_NOTALLOWED Setting */ + + #define MXC_F_SMON_SECST_SECALRS_POS 2 /**< SECST_SECALRS Position */ + #define MXC_F_SMON_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */ + #define MXC_V_SMON_SECST_SECALRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_SECALRS_ALLOWED Value */ + #define MXC_S_SMON_SECST_SECALRS_ALLOWED (MXC_V_SMON_SECST_SECALRS_ALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_ALLOWED Setting */ + #define MXC_V_SMON_SECST_SECALRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_SECALRS_NOTALLOWED Value */ + #define MXC_S_SMON_SECST_SECALRS_NOTALLOWED (MXC_V_SMON_SECST_SECALRS_NOTALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_NOTALLOWED Setting */ + +/**@} end of group SMON_SECST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SMON_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spi17y_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spi17y_regs.h new file mode 100644 index 0000000000..9f25e1c909 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spi17y_regs.h @@ -0,0 +1,664 @@ +/** + * @file spi17y_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SPI17Y_REGS_H_ +#define _SPI17Y_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spi17y + * @defgroup spi17y_registers SPI17Y_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module. + * @details SPI peripheral. + */ + +/** + * @ingroup spi17y_registers + * Structure type to access the SPI17Y Registers. + */ +typedef struct { + union{ + __IO uint32_t data32; /**< \b 0x00: SPI17Y DATA32 Register */ + __IO uint16_t data16[2]; /**< \b 0x00: SPI17Y DATA16 Register */ + __IO uint8_t data8[4]; /**< \b 0x00: SPI17Y DATA8 Register */ + }; + __IO uint32_t ctrl0; /**< \b 0x04: SPI17Y CTRL0 Register */ + __IO uint32_t ctrl1; /**< \b 0x08: SPI17Y CTRL1 Register */ + __IO uint32_t ctrl2; /**< \b 0x0C: SPI17Y CTRL2 Register */ + __IO uint32_t ss_time; /**< \b 0x10: SPI17Y SS_TIME Register */ + __IO uint32_t clk_cfg; /**< \b 0x14: SPI17Y CLK_CFG Register */ + __R uint32_t rsv_0x18; + __IO uint32_t dma; /**< \b 0x1C: SPI17Y DMA Register */ + __IO uint32_t int_fl; /**< \b 0x20: SPI17Y INT_FL Register */ + __IO uint32_t int_en; /**< \b 0x24: SPI17Y INT_EN Register */ + __IO uint32_t wake_fl; /**< \b 0x28: SPI17Y WAKE_FL Register */ + __IO uint32_t wake_en; /**< \b 0x2C: SPI17Y WAKE_EN Register */ + __I uint32_t stat; /**< \b 0x30: SPI17Y STAT Register */ +} mxc_spi17y_regs_t; + +/* Register offsets for module SPI17Y */ +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_Register_Offsets Register Offsets + * @brief SPI17Y Peripheral Register Offsets from the SPI17Y Base Peripheral Address. + * @{ + */ + #define MXC_R_SPI17Y_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: 0x0000 */ + #define MXC_R_SPI17Y_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: 0x0000 */ + #define MXC_R_SPI17Y_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: 0x0000 */ + #define MXC_R_SPI17Y_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI17Y Base Address: 0x0004 */ + #define MXC_R_SPI17Y_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI17Y Base Address: 0x0008 */ + #define MXC_R_SPI17Y_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI17Y Base Address: 0x000C */ + #define MXC_R_SPI17Y_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI17Y Base Address: 0x0010 */ + #define MXC_R_SPI17Y_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI17Y Base Address: 0x0014 */ + #define MXC_R_SPI17Y_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI17Y Base Address: 0x001C */ + #define MXC_R_SPI17Y_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI17Y Base Address: 0x0020 */ + #define MXC_R_SPI17Y_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI17Y Base Address: 0x0024 */ + #define MXC_R_SPI17Y_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI17Y Base Address: 0x0028 */ + #define MXC_R_SPI17Y_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI17Y Base Address: 0x002C */ + #define MXC_R_SPI17Y_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI17Y Base Address: 0x0030 */ +/**@} end of group spi17y_registers */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_DATA32 SPI17Y_DATA32 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI17Y_DATA32_DATA_POS 0 /**< DATA32_DATA Position */ + #define MXC_F_SPI17Y_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI17Y_DATA32_DATA_POS)) /**< DATA32_DATA Mask */ + +/**@} end of group SPI17Y_DATA32_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_DATA16 SPI17Y_DATA16 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI17Y_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ + #define MXC_F_SPI17Y_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI17Y_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ + +/**@} end of group SPI17Y_DATA16_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_DATA8 SPI17Y_DATA8 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI17Y_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ + #define MXC_F_SPI17Y_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI17Y_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ + +/**@} end of group SPI17Y_DATA8_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_CTRL0 SPI17Y_CTRL0 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI17Y_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ + #define MXC_F_SPI17Y_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ + #define MXC_V_SPI17Y_CTRL0_EN_DIS ((uint32_t)0x0UL) /**< CTRL0_EN_DIS Value */ + #define MXC_S_SPI17Y_CTRL0_EN_DIS (MXC_V_SPI17Y_CTRL0_EN_DIS << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_DIS Setting */ + #define MXC_V_SPI17Y_CTRL0_EN_EN ((uint32_t)0x1UL) /**< CTRL0_EN_EN Value */ + #define MXC_S_SPI17Y_CTRL0_EN_EN (MXC_V_SPI17Y_CTRL0_EN_EN << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_EN Setting */ + + #define MXC_F_SPI17Y_CTRL0_MASTER_POS 1 /**< CTRL0_MASTER Position */ + #define MXC_F_SPI17Y_CTRL0_MASTER ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_MASTER_POS)) /**< CTRL0_MASTER Mask */ + #define MXC_V_SPI17Y_CTRL0_MASTER_DIS ((uint32_t)0x0UL) /**< CTRL0_MASTER_DIS Value */ + #define MXC_S_SPI17Y_CTRL0_MASTER_DIS (MXC_V_SPI17Y_CTRL0_MASTER_DIS << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_DIS Setting */ + #define MXC_V_SPI17Y_CTRL0_MASTER_EN ((uint32_t)0x1UL) /**< CTRL0_MASTER_EN Value */ + #define MXC_S_SPI17Y_CTRL0_MASTER_EN (MXC_V_SPI17Y_CTRL0_MASTER_EN << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_EN Setting */ + + #define MXC_F_SPI17Y_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ + #define MXC_F_SPI17Y_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ + #define MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT ((uint32_t)0x0UL) /**< CTRL0_SS_IO_OUTPUT Value */ + #define MXC_S_SPI17Y_CTRL0_SS_IO_OUTPUT (MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_OUTPUT Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_IO_INPUT ((uint32_t)0x1UL) /**< CTRL0_SS_IO_INPUT Value */ + #define MXC_S_SPI17Y_CTRL0_SS_IO_INPUT (MXC_V_SPI17Y_CTRL0_SS_IO_INPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_INPUT Setting */ + + #define MXC_F_SPI17Y_CTRL0_START_POS 5 /**< CTRL0_START Position */ + #define MXC_F_SPI17Y_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_START_POS)) /**< CTRL0_START Mask */ + #define MXC_V_SPI17Y_CTRL0_START_START ((uint32_t)0x1UL) /**< CTRL0_START_START Value */ + #define MXC_S_SPI17Y_CTRL0_START_START (MXC_V_SPI17Y_CTRL0_START_START << MXC_F_SPI17Y_CTRL0_START_POS) /**< CTRL0_START_START Setting */ + + #define MXC_F_SPI17Y_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ + #define MXC_F_SPI17Y_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ + #define MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT ((uint32_t)0x0UL) /**< CTRL0_SS_CTRL_DEASSERT Value */ + #define MXC_S_SPI17Y_CTRL0_SS_CTRL_DEASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_DEASSERT Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT ((uint32_t)0x1UL) /**< CTRL0_SS_CTRL_ASSERT Value */ + #define MXC_S_SPI17Y_CTRL0_SS_CTRL_ASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_ASSERT Setting */ + + #define MXC_F_SPI17Y_CTRL0_SS_POS 16 /**< CTRL0_SS Position */ + #define MXC_F_SPI17Y_CTRL0_SS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL0_SS_POS)) /**< CTRL0_SS Mask */ + #define MXC_V_SPI17Y_CTRL0_SS_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SS0 Value */ + #define MXC_S_SPI17Y_CTRL0_SS_SS0 (MXC_V_SPI17Y_CTRL0_SS_SS0 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS0 Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SS1 Value */ + #define MXC_S_SPI17Y_CTRL0_SS_SS1 (MXC_V_SPI17Y_CTRL0_SS_SS1 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS1 Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SS2 Value */ + #define MXC_S_SPI17Y_CTRL0_SS_SS2 (MXC_V_SPI17Y_CTRL0_SS_SS2 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS2 Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SS3 Value */ + #define MXC_S_SPI17Y_CTRL0_SS_SS3 (MXC_V_SPI17Y_CTRL0_SS_SS3 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS3 Setting */ + +/**@} end of group SPI17Y_CTRL0_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_CTRL1 SPI17Y_CTRL1 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ + #define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ + + #define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ + #define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ + +/**@} end of group SPI17Y_CTRL1_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_CTRL2 SPI17Y_CTRL2 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI17Y_CTRL2_CPHA_POS 0 /**< CTRL2_CPHA Position */ + #define MXC_F_SPI17Y_CTRL2_CPHA ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */ + #define MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE ((uint32_t)0x0UL) /**< CTRL2_CPHA_RISING_EDGE Value */ + #define MXC_S_SPI17Y_CTRL2_CPHA_RISING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_RISING_EDGE Setting */ + #define MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE ((uint32_t)0x1UL) /**< CTRL2_CPHA_FALLING_EDGE Value */ + #define MXC_S_SPI17Y_CTRL2_CPHA_FALLING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_FALLING_EDGE Setting */ + + #define MXC_F_SPI17Y_CTRL2_CPOL_POS 1 /**< CTRL2_CPOL Position */ + #define MXC_F_SPI17Y_CTRL2_CPOL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */ + #define MXC_V_SPI17Y_CTRL2_CPOL_NORMAL ((uint32_t)0x0UL) /**< CTRL2_CPOL_NORMAL Value */ + #define MXC_S_SPI17Y_CTRL2_CPOL_NORMAL (MXC_V_SPI17Y_CTRL2_CPOL_NORMAL << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_NORMAL Setting */ + #define MXC_V_SPI17Y_CTRL2_CPOL_INVERTED ((uint32_t)0x1UL) /**< CTRL2_CPOL_INVERTED Value */ + #define MXC_S_SPI17Y_CTRL2_CPOL_INVERTED (MXC_V_SPI17Y_CTRL2_CPOL_INVERTED << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_INVERTED Setting */ + + #define MXC_F_SPI17Y_CTRL2_SCLK_INV_POS 4 /**< CTRL2_SCLK_INV Position */ + #define MXC_F_SPI17Y_CTRL2_SCLK_INV ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_SCLK_INV_POS)) /**< CTRL2_SCLK_INV Mask */ + + #define MXC_F_SPI17Y_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ + #define MXC_F_SPI17Y_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ + #define MXC_V_SPI17Y_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ + #define MXC_S_SPI17Y_CTRL2_NUMBITS_0 (MXC_V_SPI17Y_CTRL2_NUMBITS_0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ + + #define MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ + #define MXC_F_SPI17Y_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ + #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ + #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ + #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ + #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ + #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ + #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ + + #define MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ + #define MXC_F_SPI17Y_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ + #define MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS ((uint32_t)0x0UL) /**< CTRL2_THREE_WIRE_DIS Value */ + #define MXC_S_SPI17Y_CTRL2_THREE_WIRE_DIS (MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_DIS Setting */ + #define MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN ((uint32_t)0x1UL) /**< CTRL2_THREE_WIRE_EN Value */ + #define MXC_S_SPI17Y_CTRL2_THREE_WIRE_EN (MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_EN Setting */ + + #define MXC_F_SPI17Y_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ + #define MXC_F_SPI17Y_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ + #define MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ + + #define MXC_F_SPI17Y_CTRL2_SRPOL_POS 24 /**< CTRL2_SRPOL Position */ + #define MXC_F_SPI17Y_CTRL2_SRPOL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SRPOL_POS)) /**< CTRL2_SRPOL Mask */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SRPOL_SR0_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR0_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR0_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SRPOL_SR1_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR1_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR1_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SRPOL_SR2_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR2_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR2_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SRPOL_SR3_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR3_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR3_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH ((uint32_t)0x10UL) /**< CTRL2_SRPOL_SR4_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR4_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR4_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH ((uint32_t)0x20UL) /**< CTRL2_SRPOL_SR5_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR5_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR5_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH ((uint32_t)0x40UL) /**< CTRL2_SRPOL_SR6_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR6_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR6_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH ((uint32_t)0x80UL) /**< CTRL2_SRPOL_SR7_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR7_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR7_HIGH Setting */ + +/**@} end of group SPI17Y_CTRL2_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_SS_TIME SPI17Y_SS_TIME + * @brief Register for controlling SPI peripheral/Slave Select Timing. + * @{ + */ + #define MXC_F_SPI17Y_SS_TIME_PRE_POS 0 /**< SS_TIME_PRE Position */ + #define MXC_F_SPI17Y_SS_TIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_PRE_POS)) /**< SS_TIME_PRE Mask */ + #define MXC_V_SPI17Y_SS_TIME_PRE_256 ((uint32_t)0x0UL) /**< SS_TIME_PRE_256 Value */ + #define MXC_S_SPI17Y_SS_TIME_PRE_256 (MXC_V_SPI17Y_SS_TIME_PRE_256 << MXC_F_SPI17Y_SS_TIME_PRE_POS) /**< SS_TIME_PRE_256 Setting */ + + #define MXC_F_SPI17Y_SS_TIME_POST_POS 8 /**< SS_TIME_POST Position */ + #define MXC_F_SPI17Y_SS_TIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_POST_POS)) /**< SS_TIME_POST Mask */ + #define MXC_V_SPI17Y_SS_TIME_POST_256 ((uint32_t)0x0UL) /**< SS_TIME_POST_256 Value */ + #define MXC_S_SPI17Y_SS_TIME_POST_256 (MXC_V_SPI17Y_SS_TIME_POST_256 << MXC_F_SPI17Y_SS_TIME_POST_POS) /**< SS_TIME_POST_256 Setting */ + + #define MXC_F_SPI17Y_SS_TIME_INACT_POS 16 /**< SS_TIME_INACT Position */ + #define MXC_F_SPI17Y_SS_TIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_INACT_POS)) /**< SS_TIME_INACT Mask */ + #define MXC_V_SPI17Y_SS_TIME_INACT_256 ((uint32_t)0x0UL) /**< SS_TIME_INACT_256 Value */ + #define MXC_S_SPI17Y_SS_TIME_INACT_256 (MXC_V_SPI17Y_SS_TIME_INACT_256 << MXC_F_SPI17Y_SS_TIME_INACT_POS) /**< SS_TIME_INACT_256 Setting */ + +/**@} end of group SPI17Y_SS_TIME_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_CLK_CFG SPI17Y_CLK_CFG + * @brief Register for controlling SPI clock rate. + * @{ + */ + #define MXC_F_SPI17Y_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ + #define MXC_F_SPI17Y_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ + #define MXC_V_SPI17Y_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */ + #define MXC_S_SPI17Y_CLK_CFG_LO_DIS (MXC_V_SPI17Y_CLK_CFG_LO_DIS << MXC_F_SPI17Y_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */ + + #define MXC_F_SPI17Y_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ + #define MXC_F_SPI17Y_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ + #define MXC_V_SPI17Y_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */ + #define MXC_S_SPI17Y_CLK_CFG_HI_DIS (MXC_V_SPI17Y_CLK_CFG_HI_DIS << MXC_F_SPI17Y_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */ + + #define MXC_F_SPI17Y_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ + #define MXC_F_SPI17Y_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI17Y_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ + +/**@} end of group SPI17Y_CLK_CFG_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_DMA SPI17Y_DMA + * @brief Register for controlling DMA. + * @{ + */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ + + #define MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ + #define MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_FIFO_EN_DIS Value */ + #define MXC_S_SPI17Y_DMA_TX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_DIS Setting */ + #define MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_FIFO_EN_EN Value */ + #define MXC_S_SPI17Y_DMA_TX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_EN Setting */ + + #define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ + #define MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_CLEAR Value */ + #define MXC_S_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_CLEAR Setting */ + + #define MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ + + #define MXC_F_SPI17Y_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ + #define MXC_F_SPI17Y_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ + #define MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */ + #define MXC_S_SPI17Y_DMA_TX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */ + #define MXC_V_SPI17Y_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */ + #define MXC_S_SPI17Y_DMA_TX_DMA_EN_EN (MXC_V_SPI17Y_DMA_TX_DMA_EN_EN << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */ + + #define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ + #define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ + + #define MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ + #define MXC_F_SPI17Y_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ + #define MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_FIFO_EN_DIS Value */ + #define MXC_S_SPI17Y_DMA_RX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_DIS Setting */ + #define MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_FIFO_EN_EN Value */ + #define MXC_S_SPI17Y_DMA_RX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_EN Setting */ + + #define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ + #define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ + #define MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_CLEAR Value */ + #define MXC_S_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_CLEAR Setting */ + + #define MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ + #define MXC_F_SPI17Y_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ + + #define MXC_F_SPI17Y_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ + #define MXC_F_SPI17Y_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ + #define MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */ + #define MXC_S_SPI17Y_DMA_RX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */ + #define MXC_V_SPI17Y_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */ + #define MXC_S_SPI17Y_DMA_RX_DMA_EN_EN (MXC_V_SPI17Y_DMA_RX_DMA_EN_EN << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */ + +/**@} end of group SPI17Y_DMA_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_INT_FL SPI17Y_INT_FL + * @brief Register for reading and clearing interrupt flags. All bits are write 1 to + * clear. + * @{ + */ + #define MXC_F_SPI17Y_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */ + #define MXC_F_SPI17Y_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */ + #define MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_THRESH_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS) /**< INT_FL_TX_THRESH_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ + #define MXC_F_SPI17Y_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ + #define MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_EMPTY_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS) /**< INT_FL_TX_EMPTY_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */ + #define MXC_F_SPI17Y_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */ + #define MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_THRESH_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS) /**< INT_FL_RX_THRESH_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ + #define MXC_F_SPI17Y_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ + #define MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_FULL_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_INT_FL_RX_FULL_POS) /**< INT_FL_RX_FULL_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ + #define MXC_F_SPI17Y_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ + #define MXC_V_SPI17Y_INT_FL_SSA_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSA_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_SSA_CLEAR (MXC_V_SPI17Y_INT_FL_SSA_CLEAR << MXC_F_SPI17Y_INT_FL_SSA_POS) /**< INT_FL_SSA_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ + #define MXC_F_SPI17Y_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ + #define MXC_V_SPI17Y_INT_FL_SSD_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSD_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_SSD_CLEAR (MXC_V_SPI17Y_INT_FL_SSD_CLEAR << MXC_F_SPI17Y_INT_FL_SSD_POS) /**< INT_FL_SSD_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ + #define MXC_F_SPI17Y_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ + #define MXC_V_SPI17Y_INT_FL_FAULT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_FAULT_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_FAULT_CLEAR (MXC_V_SPI17Y_INT_FL_FAULT_CLEAR << MXC_F_SPI17Y_INT_FL_FAULT_POS) /**< INT_FL_FAULT_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ + #define MXC_F_SPI17Y_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ + #define MXC_V_SPI17Y_INT_FL_ABORT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_ABORT_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_ABORT_CLEAR (MXC_V_SPI17Y_INT_FL_ABORT_CLEAR << MXC_F_SPI17Y_INT_FL_ABORT_POS) /**< INT_FL_ABORT_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ + #define MXC_F_SPI17Y_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ + #define MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_M_DONE_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_M_DONE_CLEAR (MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR << MXC_F_SPI17Y_INT_FL_M_DONE_POS) /**< INT_FL_M_DONE_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ + #define MXC_F_SPI17Y_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ + #define MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_OVR_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_TX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_TX_OVR_POS) /**< INT_FL_TX_OVR_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ + #define MXC_F_SPI17Y_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ + #define MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_UND_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_TX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_TX_UND_POS) /**< INT_FL_TX_UND_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ + #define MXC_F_SPI17Y_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ + #define MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_RX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ + #define MXC_F_SPI17Y_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ + #define MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_UND_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_RX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_RX_UND_POS) /**< INT_FL_RX_UND_CLEAR Setting */ + +/**@} end of group SPI17Y_INT_FL_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_INT_EN SPI17Y_INT_EN + * @brief Register for enabling interrupts. + * @{ + */ + #define MXC_F_SPI17Y_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */ + #define MXC_F_SPI17Y_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */ + #define MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_THRESH_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_TX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_TX_THRESH_EN Value */ + #define MXC_S_SPI17Y_INT_EN_TX_THRESH_EN (MXC_V_SPI17Y_INT_EN_TX_THRESH_EN << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ + #define MXC_F_SPI17Y_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ + #define MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_EMPTY_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< INT_EN_TX_EMPTY_EN Value */ + #define MXC_S_SPI17Y_INT_EN_TX_EMPTY_EN (MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */ + #define MXC_F_SPI17Y_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */ + #define MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_THRESH_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_RX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_RX_THRESH_EN Value */ + #define MXC_S_SPI17Y_INT_EN_RX_THRESH_EN (MXC_V_SPI17Y_INT_EN_RX_THRESH_EN << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ + #define MXC_F_SPI17Y_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ + #define MXC_V_SPI17Y_INT_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FULL_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_RX_FULL_DIS (MXC_V_SPI17Y_INT_EN_RX_FULL_DIS << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FULL_EN Value */ + #define MXC_S_SPI17Y_INT_EN_RX_FULL_EN (MXC_V_SPI17Y_INT_EN_RX_FULL_EN << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ + #define MXC_F_SPI17Y_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ + #define MXC_V_SPI17Y_INT_EN_SSA_DIS ((uint32_t)0x0UL) /**< INT_EN_SSA_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_SSA_DIS (MXC_V_SPI17Y_INT_EN_SSA_DIS << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_SSA_EN ((uint32_t)0x1UL) /**< INT_EN_SSA_EN Value */ + #define MXC_S_SPI17Y_INT_EN_SSA_EN (MXC_V_SPI17Y_INT_EN_SSA_EN << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ + #define MXC_F_SPI17Y_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ + #define MXC_V_SPI17Y_INT_EN_SSD_DIS ((uint32_t)0x0UL) /**< INT_EN_SSD_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_SSD_DIS (MXC_V_SPI17Y_INT_EN_SSD_DIS << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_SSD_EN ((uint32_t)0x1UL) /**< INT_EN_SSD_EN Value */ + #define MXC_S_SPI17Y_INT_EN_SSD_EN (MXC_V_SPI17Y_INT_EN_SSD_EN << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ + #define MXC_F_SPI17Y_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ + #define MXC_V_SPI17Y_INT_EN_FAULT_DIS ((uint32_t)0x0UL) /**< INT_EN_FAULT_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_FAULT_DIS (MXC_V_SPI17Y_INT_EN_FAULT_DIS << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_FAULT_EN ((uint32_t)0x1UL) /**< INT_EN_FAULT_EN Value */ + #define MXC_S_SPI17Y_INT_EN_FAULT_EN (MXC_V_SPI17Y_INT_EN_FAULT_EN << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ + #define MXC_F_SPI17Y_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ + #define MXC_V_SPI17Y_INT_EN_ABORT_DIS ((uint32_t)0x0UL) /**< INT_EN_ABORT_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_ABORT_DIS (MXC_V_SPI17Y_INT_EN_ABORT_DIS << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_ABORT_EN ((uint32_t)0x1UL) /**< INT_EN_ABORT_EN Value */ + #define MXC_S_SPI17Y_INT_EN_ABORT_EN (MXC_V_SPI17Y_INT_EN_ABORT_EN << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ + #define MXC_F_SPI17Y_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ + #define MXC_V_SPI17Y_INT_EN_M_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN_M_DONE_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_M_DONE_DIS (MXC_V_SPI17Y_INT_EN_M_DONE_DIS << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_M_DONE_EN ((uint32_t)0x1UL) /**< INT_EN_M_DONE_EN Value */ + #define MXC_S_SPI17Y_INT_EN_M_DONE_EN (MXC_V_SPI17Y_INT_EN_M_DONE_EN << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ + #define MXC_F_SPI17Y_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ + #define MXC_V_SPI17Y_INT_EN_TX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_OVR_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_TX_OVR_DIS (MXC_V_SPI17Y_INT_EN_TX_OVR_DIS << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_TX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_TX_OVR_EN Value */ + #define MXC_S_SPI17Y_INT_EN_TX_OVR_EN (MXC_V_SPI17Y_INT_EN_TX_OVR_EN << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ + #define MXC_F_SPI17Y_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ + #define MXC_V_SPI17Y_INT_EN_TX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_UND_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_TX_UND_DIS (MXC_V_SPI17Y_INT_EN_TX_UND_DIS << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_TX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_TX_UND_EN Value */ + #define MXC_S_SPI17Y_INT_EN_TX_UND_EN (MXC_V_SPI17Y_INT_EN_TX_UND_EN << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ + #define MXC_F_SPI17Y_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ + #define MXC_V_SPI17Y_INT_EN_RX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_OVR_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_RX_OVR_DIS (MXC_V_SPI17Y_INT_EN_RX_OVR_DIS << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_RX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_OVR_EN Value */ + #define MXC_S_SPI17Y_INT_EN_RX_OVR_EN (MXC_V_SPI17Y_INT_EN_RX_OVR_EN << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ + #define MXC_F_SPI17Y_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ + #define MXC_V_SPI17Y_INT_EN_RX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_UND_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_RX_UND_DIS (MXC_V_SPI17Y_INT_EN_RX_UND_DIS << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_RX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_RX_UND_EN Value */ + #define MXC_S_SPI17Y_INT_EN_RX_UND_EN (MXC_V_SPI17Y_INT_EN_RX_UND_EN << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_EN Setting */ + +/**@} end of group SPI17Y_INT_EN_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_WAKE_FL SPI17Y_WAKE_FL + * @brief Register for wake up flags. All bits in this register are write 1 to clear. + * @{ + */ + #define MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */ + #define MXC_F_SPI17Y_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */ + #define MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_THRESH_CLEAR Value */ + #define MXC_S_SPI17Y_WAKE_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS) /**< WAKE_FL_TX_THRESH_CLEAR Setting */ + + #define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ + #define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ + #define MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_EMPTY_CLEAR Value */ + #define MXC_S_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS) /**< WAKE_FL_TX_EMPTY_CLEAR Setting */ + + #define MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */ + #define MXC_F_SPI17Y_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */ + #define MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_THRESH_CLEAR Value */ + #define MXC_S_SPI17Y_WAKE_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS) /**< WAKE_FL_RX_THRESH_CLEAR Setting */ + + #define MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ + #define MXC_F_SPI17Y_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ + #define MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_FULL_CLEAR Value */ + #define MXC_S_SPI17Y_WAKE_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS) /**< WAKE_FL_RX_FULL_CLEAR Setting */ + +/**@} end of group SPI17Y_WAKE_FL_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_WAKE_EN SPI17Y_WAKE_EN + * @brief Register for wake up enable. + * @{ + */ + #define MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */ + #define MXC_F_SPI17Y_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */ + #define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_THRESH_DIS Value */ + #define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_DIS Setting */ + #define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_THRESH_EN Value */ + #define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_EN Setting */ + + #define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ + #define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ + #define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_EMPTY_DIS Value */ + #define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_DIS Setting */ + #define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_EMPTY_EN Value */ + #define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_EN (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_EN Setting */ + + #define MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */ + #define MXC_F_SPI17Y_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */ + #define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_THRESH_DIS Value */ + #define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_DIS Setting */ + #define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_THRESH_EN Value */ + #define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_EN Setting */ + + #define MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ + #define MXC_F_SPI17Y_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ + #define MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_FULL_DIS Value */ + #define MXC_S_SPI17Y_WAKE_EN_RX_FULL_DIS (MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_DIS Setting */ + #define MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_FULL_EN Value */ + #define MXC_S_SPI17Y_WAKE_EN_RX_FULL_EN (MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_EN Setting */ + +/**@} end of group SPI17Y_WAKE_EN_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_STAT SPI17Y_STAT + * @brief SPI Status register. + * @{ + */ + #define MXC_F_SPI17Y_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ + #define MXC_F_SPI17Y_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI17Y_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ + #define MXC_V_SPI17Y_STAT_BUSY_NOT ((uint32_t)0x0UL) /**< STAT_BUSY_NOT Value */ + #define MXC_S_SPI17Y_STAT_BUSY_NOT (MXC_V_SPI17Y_STAT_BUSY_NOT << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_NOT Setting */ + #define MXC_V_SPI17Y_STAT_BUSY_ACTIVE ((uint32_t)0x1UL) /**< STAT_BUSY_ACTIVE Value */ + #define MXC_S_SPI17Y_STAT_BUSY_ACTIVE (MXC_V_SPI17Y_STAT_BUSY_ACTIVE << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_ACTIVE Setting */ + +/**@} end of group SPI17Y_STAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPI17Y_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h new file mode 100644 index 0000000000..44ea80f84e --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h @@ -0,0 +1,496 @@ +/** + * @file spimss_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SPIMSS_REGS_H_ +#define _SPIMSS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spimss + * @defgroup spimss_registers SPIMSS_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + * @details Serial Peripheral Interface. + */ + +/** + * @ingroup spimss_registers + * Structure type to access the SPIMSS Registers. + */ +typedef struct { + union{ + __IO uint16_t data16; /**< \b 0x00: SPIMSS DATA16 Register */ + __IO uint8_t data8[2]; /**< \b 0x00: SPIMSS DATA8 Register */ + }; + __R uint16_t rsv_0x2; + __IO uint32_t ctrl; /**< \b 0x04: SPIMSS CTRL Register */ + __IO uint32_t status; /**< \b 0x08: SPIMSS STATUS Register */ + __IO uint32_t mod; /**< \b 0x0C: SPIMSS MOD Register */ + __R uint32_t rsv_0x10; + __IO uint32_t brg; /**< \b 0x14: SPIMSS BRG Register */ + __IO uint32_t dma; /**< \b 0x18: SPIMSS DMA Register */ + __IO uint32_t i2s_ctrl; /**< \b 0x1C: SPIMSS I2S_CTRL Register */ +} mxc_spimss_regs_t; + +/* Register offsets for module SPIMSS */ +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_Register_Offsets Register Offsets + * @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. + * @{ + */ + #define MXC_R_SPIMSS_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: 0x0000 */ + #define MXC_R_SPIMSS_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: 0x0000 */ + #define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: 0x0004 */ + #define MXC_R_SPIMSS_STATUS ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: 0x0008 */ + #define MXC_R_SPIMSS_MOD ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: 0x000C */ + #define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: 0x0014 */ + #define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: 0x0018 */ + #define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: 0x001C */ +/**@} end of group spimss_registers */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DATA16 SPIMSS_DATA16 + * @brief SPI 16-bit Data Access + * @{ + */ + #define MXC_F_SPIMSS_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ + #define MXC_F_SPIMSS_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ + +/**@} end of group SPIMSS_DATA16_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DATA8 SPIMSS_DATA8 + * @brief SPI Data 8-bit access + * @{ + */ + #define MXC_F_SPIMSS_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ + #define MXC_F_SPIMSS_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIMSS_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ + +/**@} end of group SPIMSS_DATA8_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_CTRL SPIMSS_CTRL + * @brief SPI Control Register. + * @{ + */ + #define MXC_F_SPIMSS_CTRL_SPIEN_POS 0 /**< CTRL_SPIEN Position */ + #define MXC_F_SPIMSS_CTRL_SPIEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_SPIEN_POS)) /**< CTRL_SPIEN Mask */ + #define MXC_V_SPIMSS_CTRL_SPIEN_DISABLE ((uint32_t)0x0UL) /**< CTRL_SPIEN_DISABLE Value */ + #define MXC_S_SPIMSS_CTRL_SPIEN_DISABLE (MXC_V_SPIMSS_CTRL_SPIEN_DISABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_DISABLE Setting */ + #define MXC_V_SPIMSS_CTRL_SPIEN_ENABLE ((uint32_t)0x1UL) /**< CTRL_SPIEN_ENABLE Value */ + #define MXC_S_SPIMSS_CTRL_SPIEN_ENABLE (MXC_V_SPIMSS_CTRL_SPIEN_ENABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_ENABLE Setting */ + + #define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */ + #define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */ + #define MXC_V_SPIMSS_CTRL_MMEN_SLAVE ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */ + #define MXC_S_SPIMSS_CTRL_MMEN_SLAVE (MXC_V_SPIMSS_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */ + #define MXC_V_SPIMSS_CTRL_MMEN_MASTER ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */ + #define MXC_S_SPIMSS_CTRL_MMEN_MASTER (MXC_V_SPIMSS_CTRL_MMEN_MASTER << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */ + + #define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */ + #define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */ + #define MXC_V_SPIMSS_CTRL_WOR_DISABLE ((uint32_t)0x0UL) /**< CTRL_WOR_DISABLE Value */ + #define MXC_S_SPIMSS_CTRL_WOR_DISABLE (MXC_V_SPIMSS_CTRL_WOR_DISABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_DISABLE Setting */ + #define MXC_V_SPIMSS_CTRL_WOR_ENABLE ((uint32_t)0x1UL) /**< CTRL_WOR_ENABLE Value */ + #define MXC_S_SPIMSS_CTRL_WOR_ENABLE (MXC_V_SPIMSS_CTRL_WOR_ENABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_ENABLE Setting */ + + #define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */ + #define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */ + #define MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */ + #define MXC_S_SPIMSS_CTRL_CLKPOL_IDLELO (MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */ + #define MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */ + #define MXC_S_SPIMSS_CTRL_CLKPOL_IDLEHI (MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */ + + #define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */ + #define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */ + #define MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */ + #define MXC_S_SPIMSS_CTRL_PHASE_ACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */ + #define MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */ + #define MXC_S_SPIMSS_CTRL_PHASE_INACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */ + + #define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */ + #define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */ + #define MXC_V_SPIMSS_CTRL_BIRQ_DISABLE ((uint32_t)0x0UL) /**< CTRL_BIRQ_DISABLE Value */ + #define MXC_S_SPIMSS_CTRL_BIRQ_DISABLE (MXC_V_SPIMSS_CTRL_BIRQ_DISABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DISABLE Setting */ + #define MXC_V_SPIMSS_CTRL_BIRQ_ENABLE ((uint32_t)0x1UL) /**< CTRL_BIRQ_ENABLE Value */ + #define MXC_S_SPIMSS_CTRL_BIRQ_ENABLE (MXC_V_SPIMSS_CTRL_BIRQ_ENABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_ENABLE Setting */ + + #define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */ + #define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */ + #define MXC_V_SPIMSS_CTRL_STR_COMPLETE ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */ + #define MXC_S_SPIMSS_CTRL_STR_COMPLETE (MXC_V_SPIMSS_CTRL_STR_COMPLETE << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */ + #define MXC_V_SPIMSS_CTRL_STR_START ((uint32_t)0x1UL) /**< CTRL_STR_START Value */ + #define MXC_S_SPIMSS_CTRL_STR_START (MXC_V_SPIMSS_CTRL_STR_START << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_START Setting */ + + #define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */ + #define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */ + #define MXC_V_SPIMSS_CTRL_IRQE_DISABLE ((uint32_t)0x0UL) /**< CTRL_IRQE_DISABLE Value */ + #define MXC_S_SPIMSS_CTRL_IRQE_DISABLE (MXC_V_SPIMSS_CTRL_IRQE_DISABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_DISABLE Setting */ + #define MXC_V_SPIMSS_CTRL_IRQE_ENABLE ((uint32_t)0x1UL) /**< CTRL_IRQE_ENABLE Value */ + #define MXC_S_SPIMSS_CTRL_IRQE_ENABLE (MXC_V_SPIMSS_CTRL_IRQE_ENABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_ENABLE Setting */ + +/**@} end of group SPIMSS_CTRL_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_STATUS SPIMSS_STATUS + * @brief SPI Status Register. + * @{ + */ + #define MXC_F_SPIMSS_STATUS_SLAS_POS 0 /**< STATUS_SLAS Position */ + #define MXC_F_SPIMSS_STATUS_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_SLAS_POS)) /**< STATUS_SLAS Mask */ + #define MXC_V_SPIMSS_STATUS_SLAS_SELECTED ((uint32_t)0x0UL) /**< STATUS_SLAS_SELECTED Value */ + #define MXC_S_SPIMSS_STATUS_SLAS_SELECTED (MXC_V_SPIMSS_STATUS_SLAS_SELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_SELECTED Setting */ + #define MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED ((uint32_t)0x1UL) /**< STATUS_SLAS_NOTSELECTED Value */ + #define MXC_S_SPIMSS_STATUS_SLAS_NOTSELECTED (MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_NOTSELECTED Setting */ + + #define MXC_F_SPIMSS_STATUS_TXST_POS 1 /**< STATUS_TXST Position */ + #define MXC_F_SPIMSS_STATUS_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TXST_POS)) /**< STATUS_TXST Mask */ + #define MXC_V_SPIMSS_STATUS_TXST_IDLE ((uint32_t)0x0UL) /**< STATUS_TXST_IDLE Value */ + #define MXC_S_SPIMSS_STATUS_TXST_IDLE (MXC_V_SPIMSS_STATUS_TXST_IDLE << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_IDLE Setting */ + #define MXC_V_SPIMSS_STATUS_TXST_BUSY ((uint32_t)0x1UL) /**< STATUS_TXST_BUSY Value */ + #define MXC_S_SPIMSS_STATUS_TXST_BUSY (MXC_V_SPIMSS_STATUS_TXST_BUSY << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_BUSY Setting */ + + #define MXC_F_SPIMSS_STATUS_TUND_POS 2 /**< STATUS_TUND Position */ + #define MXC_F_SPIMSS_STATUS_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TUND_POS)) /**< STATUS_TUND Mask */ + #define MXC_V_SPIMSS_STATUS_TUND_NOEVENT ((uint32_t)0x0UL) /**< STATUS_TUND_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_TUND_NOEVENT (MXC_V_SPIMSS_STATUS_TUND_NOEVENT << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_TUND_OCCURRED ((uint32_t)0x1UL) /**< STATUS_TUND_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_TUND_OCCURRED (MXC_V_SPIMSS_STATUS_TUND_OCCURRED << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_ROVR_POS 3 /**< STATUS_ROVR Position */ + #define MXC_F_SPIMSS_STATUS_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ROVR_POS)) /**< STATUS_ROVR Mask */ + #define MXC_V_SPIMSS_STATUS_ROVR_NOEVENT ((uint32_t)0x0UL) /**< STATUS_ROVR_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_ROVR_NOEVENT (MXC_V_SPIMSS_STATUS_ROVR_NOEVENT << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_ROVR_OCCURRED ((uint32_t)0x1UL) /**< STATUS_ROVR_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_ROVR_OCCURRED (MXC_V_SPIMSS_STATUS_ROVR_OCCURRED << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_ABT_POS 4 /**< STATUS_ABT Position */ + #define MXC_F_SPIMSS_STATUS_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ABT_POS)) /**< STATUS_ABT Mask */ + #define MXC_V_SPIMSS_STATUS_ABT_NOEVENT ((uint32_t)0x0UL) /**< STATUS_ABT_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_ABT_NOEVENT (MXC_V_SPIMSS_STATUS_ABT_NOEVENT << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_ABT_OCCURRED ((uint32_t)0x1UL) /**< STATUS_ABT_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_ABT_OCCURRED (MXC_V_SPIMSS_STATUS_ABT_OCCURRED << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_COL_POS 5 /**< STATUS_COL Position */ + #define MXC_F_SPIMSS_STATUS_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_COL_POS)) /**< STATUS_COL Mask */ + #define MXC_V_SPIMSS_STATUS_COL_NOEVENT ((uint32_t)0x0UL) /**< STATUS_COL_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_COL_NOEVENT (MXC_V_SPIMSS_STATUS_COL_NOEVENT << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_COL_OCCURRED ((uint32_t)0x1UL) /**< STATUS_COL_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_COL_OCCURRED (MXC_V_SPIMSS_STATUS_COL_OCCURRED << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_TOVR_POS 6 /**< STATUS_TOVR Position */ + #define MXC_F_SPIMSS_STATUS_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TOVR_POS)) /**< STATUS_TOVR Mask */ + #define MXC_V_SPIMSS_STATUS_TOVR_NOEVENT ((uint32_t)0x0UL) /**< STATUS_TOVR_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_TOVR_NOEVENT (MXC_V_SPIMSS_STATUS_TOVR_NOEVENT << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_TOVR_OCCURRED ((uint32_t)0x1UL) /**< STATUS_TOVR_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_TOVR_OCCURRED (MXC_V_SPIMSS_STATUS_TOVR_OCCURRED << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_IRQ_POS 7 /**< STATUS_IRQ Position */ + #define MXC_F_SPIMSS_STATUS_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_IRQ_POS)) /**< STATUS_IRQ Mask */ + #define MXC_V_SPIMSS_STATUS_IRQ_INACTIVE ((uint32_t)0x0UL) /**< STATUS_IRQ_INACTIVE Value */ + #define MXC_S_SPIMSS_STATUS_IRQ_INACTIVE (MXC_V_SPIMSS_STATUS_IRQ_INACTIVE << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_INACTIVE Setting */ + #define MXC_V_SPIMSS_STATUS_IRQ_PENDING ((uint32_t)0x1UL) /**< STATUS_IRQ_PENDING Value */ + #define MXC_S_SPIMSS_STATUS_IRQ_PENDING (MXC_V_SPIMSS_STATUS_IRQ_PENDING << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_PENDING Setting */ + +/**@} end of group SPIMSS_STATUS_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_MOD SPIMSS_MOD + * @brief SPI Mode Register. + * @{ + */ + #define MXC_F_SPIMSS_MOD_SSV_POS 0 /**< MOD_SSV Position */ + #define MXC_F_SPIMSS_MOD_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSV_POS)) /**< MOD_SSV Mask */ + #define MXC_V_SPIMSS_MOD_SSV_LO ((uint32_t)0x0UL) /**< MOD_SSV_LO Value */ + #define MXC_S_SPIMSS_MOD_SSV_LO (MXC_V_SPIMSS_MOD_SSV_LO << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_LO Setting */ + #define MXC_V_SPIMSS_MOD_SSV_HI ((uint32_t)0x1UL) /**< MOD_SSV_HI Value */ + #define MXC_S_SPIMSS_MOD_SSV_HI (MXC_V_SPIMSS_MOD_SSV_HI << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_HI Setting */ + + #define MXC_F_SPIMSS_MOD_SSIO_POS 1 /**< MOD_SSIO Position */ + #define MXC_F_SPIMSS_MOD_SSIO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSIO_POS)) /**< MOD_SSIO Mask */ + #define MXC_V_SPIMSS_MOD_SSIO_INPUT ((uint32_t)0x0UL) /**< MOD_SSIO_INPUT Value */ + #define MXC_S_SPIMSS_MOD_SSIO_INPUT (MXC_V_SPIMSS_MOD_SSIO_INPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_INPUT Setting */ + #define MXC_V_SPIMSS_MOD_SSIO_OUTPUT ((uint32_t)0x1UL) /**< MOD_SSIO_OUTPUT Value */ + #define MXC_S_SPIMSS_MOD_SSIO_OUTPUT (MXC_V_SPIMSS_MOD_SSIO_OUTPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_OUTPUT Setting */ + + #define MXC_F_SPIMSS_MOD_NUMBITS_POS 2 /**< MOD_NUMBITS Position */ + #define MXC_F_SPIMSS_MOD_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MOD_NUMBITS_POS)) /**< MOD_NUMBITS Mask */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MOD_NUMBITS_BITS16 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS16 (MXC_V_SPIMSS_MOD_NUMBITS_BITS16 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS16 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MOD_NUMBITS_BITS1 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS1 (MXC_V_SPIMSS_MOD_NUMBITS_BITS1 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS1 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MOD_NUMBITS_BITS2 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS2 (MXC_V_SPIMSS_MOD_NUMBITS_BITS2 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS2 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MOD_NUMBITS_BITS3 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS3 (MXC_V_SPIMSS_MOD_NUMBITS_BITS3 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS3 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MOD_NUMBITS_BITS4 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS4 (MXC_V_SPIMSS_MOD_NUMBITS_BITS4 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS4 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MOD_NUMBITS_BITS5 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS5 (MXC_V_SPIMSS_MOD_NUMBITS_BITS5 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS5 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MOD_NUMBITS_BITS6 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS6 (MXC_V_SPIMSS_MOD_NUMBITS_BITS6 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS6 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MOD_NUMBITS_BITS7 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS7 (MXC_V_SPIMSS_MOD_NUMBITS_BITS7 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS7 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MOD_NUMBITS_BITS8 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS8 (MXC_V_SPIMSS_MOD_NUMBITS_BITS8 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS8 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MOD_NUMBITS_BITS9 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS9 (MXC_V_SPIMSS_MOD_NUMBITS_BITS9 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS9 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MOD_NUMBITS_BITS10 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS10 (MXC_V_SPIMSS_MOD_NUMBITS_BITS10 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS10 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MOD_NUMBITS_BITS11 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS11 (MXC_V_SPIMSS_MOD_NUMBITS_BITS11 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS11 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MOD_NUMBITS_BITS12 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS12 (MXC_V_SPIMSS_MOD_NUMBITS_BITS12 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS12 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MOD_NUMBITS_BITS13 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS13 (MXC_V_SPIMSS_MOD_NUMBITS_BITS13 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS13 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MOD_NUMBITS_BITS14 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS14 (MXC_V_SPIMSS_MOD_NUMBITS_BITS14 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS14 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MOD_NUMBITS_BITS15 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS15 (MXC_V_SPIMSS_MOD_NUMBITS_BITS15 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS15 Setting */ + + #define MXC_F_SPIMSS_MOD_TX_LJ_POS 7 /**< MOD_TX_LJ Position */ + #define MXC_F_SPIMSS_MOD_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_TX_LJ_POS)) /**< MOD_TX_LJ Mask */ + #define MXC_V_SPIMSS_MOD_TX_LJ_DISABLE ((uint32_t)0x0UL) /**< MOD_TX_LJ_DISABLE Value */ + #define MXC_S_SPIMSS_MOD_TX_LJ_DISABLE (MXC_V_SPIMSS_MOD_TX_LJ_DISABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_DISABLE Setting */ + #define MXC_V_SPIMSS_MOD_TX_LJ_ENABLE ((uint32_t)0x1UL) /**< MOD_TX_LJ_ENABLE Value */ + #define MXC_S_SPIMSS_MOD_TX_LJ_ENABLE (MXC_V_SPIMSS_MOD_TX_LJ_ENABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_ENABLE Setting */ + + #define MXC_F_SPIMSS_MOD_SSL1_POS 8 /**< MOD_SSL1 Position */ + #define MXC_F_SPIMSS_MOD_SSL1 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL1_POS)) /**< MOD_SSL1 Mask */ + #define MXC_V_SPIMSS_MOD_SSL1_HI ((uint32_t)0x0UL) /**< MOD_SSL1_HI Value */ + #define MXC_S_SPIMSS_MOD_SSL1_HI (MXC_V_SPIMSS_MOD_SSL1_HI << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_HI Setting */ + #define MXC_V_SPIMSS_MOD_SSL1_LO ((uint32_t)0x1UL) /**< MOD_SSL1_LO Value */ + #define MXC_S_SPIMSS_MOD_SSL1_LO (MXC_V_SPIMSS_MOD_SSL1_LO << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_LO Setting */ + + #define MXC_F_SPIMSS_MOD_SSL2_POS 9 /**< MOD_SSL2 Position */ + #define MXC_F_SPIMSS_MOD_SSL2 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL2_POS)) /**< MOD_SSL2 Mask */ + #define MXC_V_SPIMSS_MOD_SSL2_HI ((uint32_t)0x0UL) /**< MOD_SSL2_HI Value */ + #define MXC_S_SPIMSS_MOD_SSL2_HI (MXC_V_SPIMSS_MOD_SSL2_HI << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_HI Setting */ + #define MXC_V_SPIMSS_MOD_SSL2_LO ((uint32_t)0x1UL) /**< MOD_SSL2_LO Value */ + #define MXC_S_SPIMSS_MOD_SSL2_LO (MXC_V_SPIMSS_MOD_SSL2_LO << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_LO Setting */ + + #define MXC_F_SPIMSS_MOD_SSL3_POS 10 /**< MOD_SSL3 Position */ + #define MXC_F_SPIMSS_MOD_SSL3 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL3_POS)) /**< MOD_SSL3 Mask */ + #define MXC_V_SPIMSS_MOD_SSL3_HI ((uint32_t)0x0UL) /**< MOD_SSL3_HI Value */ + #define MXC_S_SPIMSS_MOD_SSL3_HI (MXC_V_SPIMSS_MOD_SSL3_HI << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_HI Setting */ + #define MXC_V_SPIMSS_MOD_SSL3_LO ((uint32_t)0x1UL) /**< MOD_SSL3_LO Value */ + #define MXC_S_SPIMSS_MOD_SSL3_LO (MXC_V_SPIMSS_MOD_SSL3_LO << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_LO Setting */ + +/**@} end of group SPIMSS_MOD_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_BRG SPIMSS_BRG + * @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for + * the SPI Baud Rate Generator. The reload value must be greater than or equal to + * 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by + * 4). + * @{ + */ + #define MXC_F_SPIMSS_BRG_BRG_POS 0 /**< BRG_BRG Position */ + #define MXC_F_SPIMSS_BRG_BRG ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_BRG_POS)) /**< BRG_BRG Mask */ + +/**@} end of group SPIMSS_BRG_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DMA SPIMSS_DMA + * @brief SPI DMA Register. + * @{ + */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Setting */ + + #define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS 4 /**< DMA_TX_FIFO_CLEAR Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE ((uint32_t)0x0UL) /**< DMA_TX_FIFO_CLEAR_COMPLETE Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_COMPLETE Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_START Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_START (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_START Setting */ + + #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ + + #define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ + #define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ + #define MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DISABLE Value */ + #define MXC_S_SPIMSS_DMA_TX_DMA_EN_DISABLE (MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_ENABLE Value */ + #define MXC_S_SPIMSS_DMA_TX_DMA_EN_ENABLE (MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_ENABLE Setting */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Setting */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS 20 /**< DMA_RX_FIFO_CLEAR Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE ((uint32_t)0x0UL) /**< DMA_RX_FIFO_CLEAR_COMPLETE Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_COMPLETE Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_START Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_START (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_START Setting */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ + + #define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ + #define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ + #define MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DISABLE Value */ + #define MXC_S_SPIMSS_DMA_RX_DMA_EN_DISABLE (MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_ENABLE Value */ + #define MXC_S_SPIMSS_DMA_RX_DMA_EN_ENABLE (MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_ENABLE Setting */ + +/**@} end of group SPIMSS_DMA_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL + * @brief I2S Control Register. + * @{ + */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DISABLE Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_DISABLE (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_ENABLE Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_ENABLE (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_ENABLE Setting */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_REPLACED Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_REPLACED Setting */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_HALT Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_HALT Setting */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Setting */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_NORMAL Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_NORMAL Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_REPLACED Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_REPLACED Setting */ + +/**@} end of group SPIMSS_I2S_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPIMSS_REGS_H_ */ diff --git a/bsp/maxim/libraries/CMSIS/system_max32660.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h similarity index 100% rename from bsp/maxim/libraries/CMSIS/system_max32660.h rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h new file mode 100644 index 0000000000..5f74afa463 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h @@ -0,0 +1,233 @@ +/** + * @file tmr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _TMR_REGS_H_ +#define _TMR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup tmr + * @defgroup tmr_registers TMR_Registers + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @details 32-bit reloadable timer that can be used for timing and event counting. + */ + +/** + * @ingroup tmr_registers + * Structure type to access the TMR Registers. + */ +typedef struct { + __IO uint32_t cnt; /**< \b 0x00: TMR CNT Register */ + __IO uint32_t cmp; /**< \b 0x04: TMR CMP Register */ + __IO uint32_t pwm; /**< \b 0x08: TMR PWM Register */ + __IO uint32_t intr; /**< \b 0x0C: TMR INTR Register */ + __IO uint32_t cn; /**< \b 0x10: TMR CN Register */ + __IO uint32_t nolcmp; /**< \b 0x14: TMR NOLCMP Register */ +} mxc_tmr_regs_t; + +/* Register offsets for module TMR */ +/** + * @ingroup tmr_registers + * @defgroup TMR_Register_Offsets Register Offsets + * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. + * @{ + */ + #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ + #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ + #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ + #define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ + #define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ + #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ +/**@} end of group tmr_registers */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_INTR TMR_INTR + * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the + * associated interrupt. + * @{ + */ + #define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */ + #define MXC_F_TMR_INTR_IRQ_CLR ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */ + +/**@} end of group TMR_INTR_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CN TMR_CN + * @brief Timer Control Register. + * @{ + */ + #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ + #define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ + #define MXC_V_TMR_CN_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ + #define MXC_S_TMR_CN_TMODE_ONESHOT (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */ + #define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ + #define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ + #define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ + #define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ + #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ + #define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ + #define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ + #define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ + #define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ + #define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ + #define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */ + #define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ + #define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ + #define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */ + + #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ + #define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ + #define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ + #define MXC_S_TMR_CN_PRES_DIV1 (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */ + #define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */ + #define MXC_S_TMR_CN_PRES_DIV2 (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */ + #define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */ + #define MXC_S_TMR_CN_PRES_DIV4 (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */ + #define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */ + #define MXC_S_TMR_CN_PRES_DIV8 (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */ + #define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */ + #define MXC_S_TMR_CN_PRES_DIV16 (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */ + #define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */ + #define MXC_S_TMR_CN_PRES_DIV32 (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */ + #define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */ + #define MXC_S_TMR_CN_PRES_DIV64 (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */ + #define MXC_V_TMR_CN_PRES_DIV128 ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */ + #define MXC_S_TMR_CN_PRES_DIV128 (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */ + + #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ + #define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ + #define MXC_V_TMR_CN_TPOL_ACTIVEHI ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */ + #define MXC_S_TMR_CN_TPOL_ACTIVEHI (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */ + #define MXC_V_TMR_CN_TPOL_ACTIVELO ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */ + #define MXC_S_TMR_CN_TPOL_ACTIVELO (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */ + + #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ + #define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ + #define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */ + #define MXC_S_TMR_CN_TEN_DIS (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */ + #define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */ + #define MXC_S_TMR_CN_TEN_EN (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting */ + + #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ + #define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ + + #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ + #define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */ + #define MXC_V_TMR_CN_PWMSYNC_DIS ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value */ + #define MXC_S_TMR_CN_PWMSYNC_DIS (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */ + #define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */ + #define MXC_S_TMR_CN_PWMSYNC_EN (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */ + + #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ + #define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */ + #define MXC_V_TMR_CN_NOLHPOL_DIS ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value */ + #define MXC_S_TMR_CN_NOLHPOL_DIS (MXC_V_TMR_CN_NOLHPOL_DIS << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */ + #define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */ + #define MXC_S_TMR_CN_NOLHPOL_EN (MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */ + + #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ + #define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */ + #define MXC_V_TMR_CN_NOLLPOL_DIS ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value */ + #define MXC_S_TMR_CN_NOLLPOL_DIS (MXC_V_TMR_CN_NOLLPOL_DIS << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */ + #define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */ + #define MXC_S_TMR_CN_NOLLPOL_EN (MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */ + + #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ + #define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */ + #define MXC_V_TMR_CN_PWMCKBD_DIS ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value */ + #define MXC_S_TMR_CN_PWMCKBD_DIS (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */ + #define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */ + #define MXC_S_TMR_CN_PWMCKBD_EN (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */ + +/**@} end of group TMR_CN_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_NOLCMP TMR_NOLCMP + * @brief Timer Non-Overlapping Compare Register. + * @{ + */ + #define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ + #define MXC_F_TMR_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ + + #define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ + #define MXC_F_TMR_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ + +/**@} end of group TMR_NOLCMP_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TMR_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h new file mode 100644 index 0000000000..aaa2f5e111 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h @@ -0,0 +1,450 @@ +/** + * @file uart_regs.h + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _UART_REGS_H_ +#define _UART_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup uart + * @defgroup uart_registers UART_Registers + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @details UART + */ + +/** + * @ingroup uart_registers + * Structure type to access the UART Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: UART CTRL Register */ + __IO uint32_t thresh_ctrl; /**< \b 0x04: UART THRESH_CTRL Register */ + __I uint32_t status; /**< \b 0x08: UART STATUS Register */ + __IO uint32_t int_en; /**< \b 0x0C: UART INT_EN Register */ + __IO uint32_t int_fl; /**< \b 0x10: UART INT_FL Register */ + __IO uint32_t baud0; /**< \b 0x14: UART BAUD0 Register */ + __IO uint32_t baud1; /**< \b 0x18: UART BAUD1 Register */ + __IO uint32_t fifo; /**< \b 0x1C: UART FIFO Register */ + __IO uint32_t dma; /**< \b 0x20: UART DMA Register */ + __IO uint32_t tx_fifo; /**< \b 0x24: UART TX_FIFO Register */ +} mxc_uart_regs_t; + +/* Register offsets for module UART */ +/** + * @ingroup uart_registers + * @defgroup UART_Register_Offsets Register Offsets + * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. + * @{ + */ + #define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ + #define MXC_R_UART_THRESH_CTRL ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ + #define MXC_R_UART_STATUS ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ + #define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ + #define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ + #define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ + #define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ + #define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ + #define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ + #define MXC_R_UART_TX_FIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: 0x0024 */ +/**@} end of group uart_registers */ + +/** + * @ingroup uart_registers + * @defgroup UART_CTRL UART_CTRL + * @brief Control Register. + * @{ + */ + #define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ + #define MXC_F_UART_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ + #define MXC_V_UART_CTRL_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */ + #define MXC_S_UART_CTRL_ENABLE_DIS (MXC_V_UART_CTRL_ENABLE_DIS << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */ + #define MXC_V_UART_CTRL_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value */ + #define MXC_S_UART_CTRL_ENABLE_EN (MXC_V_UART_CTRL_ENABLE_EN << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */ + + #define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */ + #define MXC_F_UART_CTRL_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */ + #define MXC_V_UART_CTRL_PARITY_EN_DIS ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */ + #define MXC_S_UART_CTRL_PARITY_EN_DIS (MXC_V_UART_CTRL_PARITY_EN_DIS << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */ + #define MXC_V_UART_CTRL_PARITY_EN_EN ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */ + #define MXC_S_UART_CTRL_PARITY_EN_EN (MXC_V_UART_CTRL_PARITY_EN_EN << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */ + + #define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */ + #define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */ + #define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */ + #define MXC_S_UART_CTRL_PARITY_EVEN (MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */ + #define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */ + #define MXC_S_UART_CTRL_PARITY_ODD (MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */ + #define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */ + #define MXC_S_UART_CTRL_PARITY_MARK (MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */ + #define MXC_V_UART_CTRL_PARITY_SPACE ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */ + #define MXC_S_UART_CTRL_PARITY_SPACE (MXC_V_UART_CTRL_PARITY_SPACE << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */ + + #define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */ + #define MXC_F_UART_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */ + #define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */ + #define MXC_S_UART_CTRL_PARMD_1 (MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */ + #define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */ + #define MXC_S_UART_CTRL_PARMD_0 (MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */ + + #define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */ + #define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ + + #define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */ + #define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ + + #define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */ + #define MXC_F_UART_CTRL_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */ + #define MXC_V_UART_CTRL_BITACC_FRAME ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */ + #define MXC_S_UART_CTRL_BITACC_FRAME (MXC_V_UART_CTRL_BITACC_FRAME << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */ + #define MXC_V_UART_CTRL_BITACC_BIT ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */ + #define MXC_S_UART_CTRL_BITACC_BIT (MXC_V_UART_CTRL_BITACC_BIT << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */ + + #define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */ + #define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ + #define MXC_V_UART_CTRL_CHAR_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ + #define MXC_S_UART_CTRL_CHAR_SIZE_5 (MXC_V_UART_CTRL_CHAR_SIZE_5 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */ + #define MXC_V_UART_CTRL_CHAR_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ + #define MXC_S_UART_CTRL_CHAR_SIZE_6 (MXC_V_UART_CTRL_CHAR_SIZE_6 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */ + #define MXC_V_UART_CTRL_CHAR_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ + #define MXC_S_UART_CTRL_CHAR_SIZE_7 (MXC_V_UART_CTRL_CHAR_SIZE_7 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */ + #define MXC_V_UART_CTRL_CHAR_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ + #define MXC_S_UART_CTRL_CHAR_SIZE_8 (MXC_V_UART_CTRL_CHAR_SIZE_8 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */ + + #define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */ + #define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ + #define MXC_V_UART_CTRL_STOPBITS_1 ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */ + #define MXC_S_UART_CTRL_STOPBITS_1 (MXC_V_UART_CTRL_STOPBITS_1 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */ + #define MXC_V_UART_CTRL_STOPBITS_1_5 ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */ + #define MXC_S_UART_CTRL_STOPBITS_1_5 (MXC_V_UART_CTRL_STOPBITS_1_5 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */ + + #define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */ + #define MXC_F_UART_CTRL_FLOW_CTRL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */ + #define MXC_V_UART_CTRL_FLOW_CTRL_EN ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */ + #define MXC_S_UART_CTRL_FLOW_CTRL_EN (MXC_V_UART_CTRL_FLOW_CTRL_EN << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */ + #define MXC_V_UART_CTRL_FLOW_CTRL_DIS ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */ + #define MXC_S_UART_CTRL_FLOW_CTRL_DIS (MXC_V_UART_CTRL_FLOW_CTRL_DIS << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */ + + #define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */ + #define MXC_F_UART_CTRL_FLOW_POL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */ + #define MXC_V_UART_CTRL_FLOW_POL_0 ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */ + #define MXC_S_UART_CTRL_FLOW_POL_0 (MXC_V_UART_CTRL_FLOW_POL_0 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */ + #define MXC_V_UART_CTRL_FLOW_POL_1 ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */ + #define MXC_S_UART_CTRL_FLOW_POL_1 (MXC_V_UART_CTRL_FLOW_POL_1 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */ + + #define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */ + #define MXC_F_UART_CTRL_NULL_MODEM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM Mask */ + #define MXC_V_UART_CTRL_NULL_MODEM_DIS ((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */ + #define MXC_S_UART_CTRL_NULL_MODEM_DIS (MXC_V_UART_CTRL_NULL_MODEM_DIS << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting */ + #define MXC_V_UART_CTRL_NULL_MODEM_EN ((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */ + #define MXC_S_UART_CTRL_NULL_MODEM_EN (MXC_V_UART_CTRL_NULL_MODEM_EN << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */ + + #define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */ + #define MXC_F_UART_CTRL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask */ + #define MXC_V_UART_CTRL_BREAK_DIS ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value */ + #define MXC_S_UART_CTRL_BREAK_DIS (MXC_V_UART_CTRL_BREAK_DIS << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */ + #define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */ + #define MXC_S_UART_CTRL_BREAK_EN (MXC_V_UART_CTRL_BREAK_EN << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */ + + #define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */ + #define MXC_F_UART_CTRL_CLKSEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ + #define MXC_V_UART_CTRL_CLKSEL_SYSTEM ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */ + #define MXC_S_UART_CTRL_CLKSEL_SYSTEM (MXC_V_UART_CTRL_CLKSEL_SYSTEM << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */ + #define MXC_V_UART_CTRL_CLKSEL_ALTERNATE ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */ + #define MXC_S_UART_CTRL_CLKSEL_ALTERNATE (MXC_V_UART_CTRL_CLKSEL_ALTERNATE << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */ + + #define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */ + #define MXC_F_UART_CTRL_RX_TO ((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */ + +/**@} end of group UART_CTRL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_THRESH_CTRL UART_THRESH_CTRL + * @brief Threshold Control register. + * @{ + */ + #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */ + #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< THRESH_CTRL_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */ + #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< THRESH_CTRL_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */ + #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< THRESH_CTRL_RTS_FIFO_THRESH Mask */ + +/**@} end of group UART_THRESH_CTRL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_STATUS UART_STATUS + * @brief Status Register. + * @{ + */ + #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ + #define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ + + #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ + #define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ + + #define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */ + #define MXC_F_UART_STATUS_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */ + + #define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */ + #define MXC_F_UART_STATUS_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */ + + #define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */ + #define MXC_F_UART_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ + + #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ + #define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + + #define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */ + #define MXC_F_UART_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ + + #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ + #define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + + #define MXC_F_UART_STATUS_RX_FIFO_CNT_POS 8 /**< STATUS_RX_FIFO_CNT Position */ + #define MXC_F_UART_STATUS_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */ + + #define MXC_F_UART_STATUS_TX_FIFO_CNT_POS 16 /**< STATUS_TX_FIFO_CNT Position */ + #define MXC_F_UART_STATUS_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */ + + #define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */ + #define MXC_F_UART_STATUS_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */ + +/**@} end of group UART_STATUS_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INT_EN UART_INT_EN + * @brief Interrupt Enable Register. + * @{ + */ + #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ + #define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ + + #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ + #define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ + + #define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */ + #define MXC_F_UART_INT_EN_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE Mask */ + + #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ + #define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ + + #define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS 4 /**< INT_EN_RX_FIFO_THRESH Position */ + #define MXC_F_UART_INT_EN_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */ + #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */ + + #define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS 6 /**< INT_EN_TX_FIFO_THRESH Position */ + #define MXC_F_UART_INT_EN_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< INT_EN_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ + #define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ + + #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */ + #define MXC_F_UART_INT_EN_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT Mask */ + + #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ + #define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ + +/**@} end of group UART_INT_EN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INT_FL UART_INT_FL + * @brief Interrupt Status Flags. + * @{ + */ + #define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS 0 /**< INT_FL_RX_FRAME_ERROR Position */ + #define MXC_F_UART_INT_FL_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */ + + #define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS 1 /**< INT_FL_RX_PARITY_ERROR Position */ + #define MXC_F_UART_INT_FL_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */ + + #define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */ + #define MXC_F_UART_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */ + + #define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */ + #define MXC_F_UART_INT_FL_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */ + + #define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS 4 /**< INT_FL_RX_FIFO_THRESH Position */ + #define MXC_F_UART_INT_FL_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */ + #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */ + + #define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS 6 /**< INT_FL_TX_FIFO_THRESH Position */ + #define MXC_F_UART_INT_FL_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< INT_FL_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ + #define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ + + #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */ + #define MXC_F_UART_INT_FL_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT Mask */ + + #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ + #define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ + +/**@} end of group UART_INT_FL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_BAUD0 UART_BAUD0 + * @brief Baud rate register. Integer portion. + * @{ + */ + #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ + #define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ + + #define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */ + #define MXC_F_UART_BAUD0_FACTOR ((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */ + #define MXC_V_UART_BAUD0_FACTOR_128 ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */ + #define MXC_S_UART_BAUD0_FACTOR_128 (MXC_V_UART_BAUD0_FACTOR_128 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */ + #define MXC_V_UART_BAUD0_FACTOR_64 ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */ + #define MXC_S_UART_BAUD0_FACTOR_64 (MXC_V_UART_BAUD0_FACTOR_64 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */ + #define MXC_V_UART_BAUD0_FACTOR_32 ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */ + #define MXC_S_UART_BAUD0_FACTOR_32 (MXC_V_UART_BAUD0_FACTOR_32 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */ + #define MXC_V_UART_BAUD0_FACTOR_16 ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */ + #define MXC_S_UART_BAUD0_FACTOR_16 (MXC_V_UART_BAUD0_FACTOR_16 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */ + +/**@} end of group UART_BAUD0_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_BAUD1 UART_BAUD1 + * @brief Baud rate register. Decimal Setting. + * @{ + */ + #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ + #define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ + +/**@} end of group UART_BAUD1_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_FIFO UART_FIFO + * @brief FIFO Data buffer. + * @{ + */ + #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ + #define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ + +/**@} end of group UART_FIFO_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_DMA UART_DMA + * @brief DMA Configuration. + * @{ + */ + #define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */ + #define MXC_F_UART_DMA_TDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */ + #define MXC_V_UART_DMA_TDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */ + #define MXC_S_UART_DMA_TDMA_EN_DIS (MXC_V_UART_DMA_TDMA_EN_DIS << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */ + #define MXC_V_UART_DMA_TDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value */ + #define MXC_S_UART_DMA_TDMA_EN_EN (MXC_V_UART_DMA_TDMA_EN_EN << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */ + + #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ + #define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ + #define MXC_V_UART_DMA_RXDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */ + #define MXC_S_UART_DMA_RXDMA_EN_DIS (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */ + #define MXC_V_UART_DMA_RXDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */ + #define MXC_S_UART_DMA_RXDMA_EN_EN (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */ + + #define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */ + #define MXC_F_UART_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */ + + #define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */ + #define MXC_F_UART_DMA_RXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */ + +/**@} end of group UART_DMA_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_TX_FIFO UART_TX_FIFO + * @brief Transmit FIFO Status register. + * @{ + */ + #define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */ + #define MXC_F_UART_TX_FIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */ + +/**@} end of group UART_TX_FIFO_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _UART_REGS_H_ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h new file mode 100644 index 0000000000..e993307874 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h @@ -0,0 +1,236 @@ +/** + * @file wdt_regs.h + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _WDT_REGS_H_ +#define _WDT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup wdt + * @defgroup wdt_registers WDT_Registers + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @details Watchdog Timer 0 + */ + +/** + * @ingroup wdt_registers + * Structure type to access the WDT Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: WDT CTRL Register */ + __O uint32_t rst; /**< \b 0x04: WDT RST Register */ +} mxc_wdt_regs_t; + +/* Register offsets for module WDT */ +/** + * @ingroup wdt_registers + * @defgroup WDT_Register_Offsets Register Offsets + * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. + * @{ + */ + #define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ + #define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ +/**@} end of group wdt_registers */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CTRL WDT_CTRL + * @brief Watchdog Timer Control Register. + * @{ + */ + #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ + #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */ + + #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ + #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */ + + #define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ + #define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ + #define MXC_V_WDT_CTRL_WDT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */ + #define MXC_S_WDT_CTRL_WDT_EN_DIS (MXC_V_WDT_CTRL_WDT_EN_DIS << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */ + #define MXC_V_WDT_CTRL_WDT_EN_EN ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value */ + #define MXC_S_WDT_CTRL_WDT_EN_EN (MXC_V_WDT_CTRL_WDT_EN_EN << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */ + + #define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ + #define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ + #define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE ((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */ + #define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE (MXC_V_WDT_CTRL_INT_FLAG_INACTIVE << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting */ + #define MXC_V_WDT_CTRL_INT_FLAG_PENDING ((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */ + #define MXC_S_WDT_CTRL_INT_FLAG_PENDING (MXC_V_WDT_CTRL_INT_FLAG_PENDING << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */ + + #define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ + #define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ + #define MXC_V_WDT_CTRL_INT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */ + #define MXC_S_WDT_CTRL_INT_EN_DIS (MXC_V_WDT_CTRL_INT_EN_DIS << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */ + #define MXC_V_WDT_CTRL_INT_EN_EN ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value */ + #define MXC_S_WDT_CTRL_INT_EN_EN (MXC_V_WDT_CTRL_INT_EN_EN << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */ + + #define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ + #define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ + #define MXC_V_WDT_CTRL_RST_EN_DIS ((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */ + #define MXC_S_WDT_CTRL_RST_EN_DIS (MXC_V_WDT_CTRL_RST_EN_DIS << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */ + #define MXC_V_WDT_CTRL_RST_EN_EN ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value */ + #define MXC_S_WDT_CTRL_RST_EN_EN (MXC_V_WDT_CTRL_RST_EN_EN << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */ + + #define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ + #define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ + #define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT ((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */ + #define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */ + #define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED ((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */ + #define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED (MXC_V_WDT_CTRL_RST_FLAG_OCCURRED << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting */ + +/**@} end of group WDT_CTRL_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_RST WDT_RST + * @brief Watchdog Timer Reset Register. + * @{ + */ + #define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ + #define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ + #define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ + #define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ + #define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ + #define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ + +/**@} end of group WDT_RST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_REGS_H_ */ diff --git a/bsp/maxim/libraries/CMSIS/startup_max32660.s b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s similarity index 100% rename from bsp/maxim/libraries/CMSIS/startup_max32660.s rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/gcc.mk b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/gcc.mk new file mode 100644 index 0000000000..9732a10288 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/gcc.mk @@ -0,0 +1,391 @@ +################################################################################ + # Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + # + # Permission is hereby granted, free of charge, to any person obtaining a + # copy of this software and associated documentation files (the "Software"), + # to deal in the Software without restriction, including without limitation + # the rights to use, copy, modify, merge, publish, distribute, sublicense, + # and/or sell copies of the Software, and to permit persons to whom the + # Software is furnished to do so, subject to the following conditions: + # + # The above copyright notice and this permission notice shall be included + # in all copies or substantial portions of the Software. + # + # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + # IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + # OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + # OTHER DEALINGS IN THE SOFTWARE. + # + # Except as contained in this notice, the name of Maxim Integrated + # Products, Inc. shall not be used except as stated in the Maxim Integrated + # Products, Inc. Branding Policy. + # + # The mere transfer of this software does not imply any licenses + # of trade secrets, proprietary technology, copyrights, patents, + # trademarks, maskwork rights, or any other form of intellectual + # property whatsoever. Maxim Integrated Products, Inc. retains all + # ownership rights. + # + # $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + # $Revision: 40072 $ + # + ############################################################################### + +# The build directory +ifeq "$(BUILD_DIR)" "" +BUILD_DIR=$(CURDIR)/build +endif + +# Create output object file names +SRCS_NOPATH := $(foreach NAME,$(SRCS),$(basename $(notdir $(NAME))).c) +OBJS_NOPATH := $(SRCS_NOPATH:.c=.o) +OBJS := $(OBJS_NOPATH:%.o=$(BUILD_DIR)/%.o) + +################################################################################ +# Goals + +# The default goal, which causes the example to be built. +.DEFAULT_GOAL := +.PHONY: all +all: mkbuildir +all: ${BUILD_DIR}/${PROJECT}.elf + +# Goal to build for release without debug +.PHONY: release +release: mkbuildir +release: ${BUILD_DIR}/${PROJECT}.elf +release: ${BUILD_DIR}/${PROJECT}.srec +release: ${BUILD_DIR}/${PROJECT}.hex +release: ${BUILD_DIR}/${PROJECT}.bin +release: ${BUILD_DIR}/${PROJECT}.dasm + +# The goal to build as a library +.PHONY: lib +lib: mkbuildir +lib: ${BUILD_DIR}/${PROJECT}.a + +# The goal to create the target directory. +.PHONY: mkbuildir +mkbuildir: + @mkdir -p ${BUILD_DIR} + +# The goal to clean out all the build products. +.PHONY: clean +clean: + @rm -rf ${BUILD_DIR} ${wildcard *~} + +${BUILD_DIR}/${PROJECT}.elf: ${LIBS} ${OBJS} ${LINKERFILE} +${BUILD_DIR}/${PROJECT}.a: ${OBJS} + +# Create a goal to exercise the library build dependencies +.PHONY: FORCE +FORCE: + +# Include the automatically generated dependency files. +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${BUILD_DIR}/*.d} __dummy__ +endif + +################################################################################ +# Get the operating system name. If this is Cygwin, the .d files will be +# munged to convert c: into /cygdrive/c so that "make" will be happy with the +# auto-generated dependencies. Also if this is Cygwin, file paths for ARM GCC +# will be converted from /cygdrive/c to C:. +################################################################################ +ifneq ($(findstring CYGWIN, ${shell uname -s}), ) +CYGWIN=True +endif + +# Get the prefix for the tools to use. +ifeq "$(TOOL_DIR)" "" +PREFIX=arm-none-eabi +else +PREFIX=$(TOOL_DIR)/arm-none-eabi +endif + +# The command for calling the compiler. +CC=${PREFIX}-gcc +CXX=${PREFIX}-g++ + +# Discover if we are using GCC > 4.8.0 +GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f1 -d.` \> 4) +ifeq "$(GCCVERSIONGTEQ4)" "0" +GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f1 -d.` \>= 4) +ifeq "$(GCCVERSIONGTEQ4)" "1" +GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f2 -d.` \>= 8) +endif + +endif + +# The flags passed to the assembler. +AFLAGS=-mthumb \ + -mcpu=cortex-m4 \ + -MD +ifneq "$(HEAP_SIZE)" "" +AFLAGS+=-D__HEAP_SIZE=$(HEAP_SIZE) +endif +ifneq "$(STACK_SIZE)" "" +AFLAGS+=-D__STACK_SIZE=$(STACK_SIZE) +endif +AFLAGS+=$(PROJ_AFLAGS) + +ifeq "$(MXC_OPTIMIZE_CFLAGS)" "" +# Default is optimize for size +MXC_OPTIMIZE_CFLAGS = -Os +endif + +# The flags passed to the compiler. +# fno-isolate-erroneous-paths-dereference disables the check for pointers with the value of 0 +# add this below when arm-none-eabi-gcc version is past 4.8 -fno-isolate-erroneous-paths-dereference \ + +CFLAGS=-mthumb \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wa,-mimplicit-it=thumb \ + $(MXC_OPTIMIZE_CFLAGS) \ + -fsingle-precision-constant \ + -ffunction-sections \ + -fdata-sections \ + -MD \ + -Wall \ + -Wdouble-promotion \ + -Wno-format \ + -c + +# The flags passed to the C++ compiler. +CXXFLAGS= \ + -mthumb \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Wa,-mimplicit-it=thumb \ + $(MXC_OPTIMIZE_CFLAGS) \ + -ffunction-sections \ + -fdata-sections \ + -MD \ + -Wall \ + -Wno-format \ + -fno-rtti \ + -fno-exceptions \ + -std=c++11 \ + -c + +# On GCC version > 4.8.0 use the -fno-isolate-erroneous-paths-dereference flag +ifeq "$(GCCVERSIONGTEQ4)" "1" +CFLAGS += -fno-isolate-erroneous-paths-dereference +endif + +ifneq "$(TARGET)" "" +# Turn TARGET into a number for use within source files (e.g. MAX32650 -> 32650) +CFLAGS+=-DTARGET=$(shell echo $(TARGET) | tr -d '[:alpha:]') +CXXFLAGS+=-DTARGET=$(shell echo $(TARGET) | tr -d '[:alpha:]') +endif + +ifneq "$(TARGET_REV)" "" +CFLAGS+=-DTARGET_REV=$(TARGET_REV) +CXXFLAGS+=-DTARGET_REV=$(TARGET_REV) +endif + +# Exclude debug for 'release' builds +ifneq (${MAKECMDGOALS},release) +ifneq (${DEBUG},0) +CFLAGS+=-g3 -ggdb -DDEBUG +endif +endif + +CFLAGS+=$(PROJ_CFLAGS) +CXXFLAGS+=$(PROJ_CFLAGS) + +# The command for calling the library archiver. +AR=${PREFIX}-ar + +# The command for calling the linker. +LD=${PREFIX}-gcc + +# The flags passed to the linker. +LDFLAGS=-mthumb \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -Xlinker --gc-sections \ + -Xlinker -Map -Xlinker ${BUILD_DIR}/$(PROJECT).map +LDFLAGS+=$(PROJ_LDFLAGS) + +# Include math library +STD_LIBS=-lc -lm + +# Determine if any C++ files are in the project sources, and add libraries as appropriate +ifneq "$(findstring cpp, ${SRCS})" "" +STD_LIBS+=-lsupc++ -lstdc++ +endif + +# Finally, resolve any newlib system calls with libnosys +STD_LIBS+=-lnosys + +PROJ_LIBS:=$(addprefix -l, $(PROJ_LIBS)) + +# The command for extracting images from the linked executables. +OBJCOPY=${PREFIX}-objcopy +OBJDUMP=${PREFIX}-objdump + +ifeq "$(CYGWIN)" "True" +fixpath=$(shell echo $(1) | sed -r 's/\/cygdrive\/([A-Na-n])/\U\1:/g' ) +else +fixpath=$(1) +endif + +# Add the include file paths to AFLAGS and CFLAGS. +AFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))} +CFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))} +CXXFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))} +LDFLAGS+=${patsubst %,-L%,$(call fixpath,$(LIBPATH))} + +################################################################################ +# The rule for building the object file from each C source file. +${BUILD_DIR}/%.o: %.c + @if [ 'x${ECLIPSE}' != x ]; \ + then \ + echo ${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}) | sed 's/-I\/\(.\)\//-I\1:\//g' ; \ + elif [ 'x${VERBOSE}' != x ]; \ + then \ + echo ${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}); \ + else \ + echo " CC ${<}"; \ + fi + @${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}) +ifeq "$(CYGWIN)" "True" + @sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d} +endif + +# The rule to build an object file from a C++ source file +${BUILD_DIR}/%.o: %.cpp + @if [ 'x${ECLIPSE}' != x ]; \ + then \ + echo ${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}) | sed 's/-I\/\(.\)\//-I\1:\//g' ; \ + elif [ 'x${VERBOSE}' != x ]; \ + then \ + echo ${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}); \ + else \ + echo " CXX ${<}"; \ + fi + @${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}) +ifeq "$(CYGWIN)" "True" + @sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d} +endif + +# The rule for building the object file from each assembly source file. +${BUILD_DIR}/%.o: %.S + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " AS ${<}"; \ + else \ + echo ${CC} ${AFLAGS} -o $(call fixpath,${@}) -c $(call fixpath,${<}); \ + fi + @${CC} ${AFLAGS} -o $(call fixpath,${@}) -c $(call fixpath,${<}) +ifeq "$(CYGWIN)" "True" + @sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d} +endif + +# The rule for creating an object library. +${BUILD_DIR}/%.a: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " AR ${@}"; \ + else \ + echo ${AR} -cr $(call fixpath,${@}) $(call fixpath,${^}); \ + fi + @${AR} -cr $(call fixpath,${@}) $(call fixpath,${^}) + +# The rule for linking the application. +${BUILD_DIR}/%.elf: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " LD ${@} ${LNK_SCP}"; \ + else \ + echo ${LD} -T $(call fixpath,${LINKERFILE}) \ + --entry ${ENTRY} \ + $(call fixpath,${LDFLAGS}) \ + -o $(call fixpath,${@}) \ + $(call fixpath,$(filter %.o, ${^})) \ + -Xlinker --start-group \ + $(call fixpath,$(filter %.a, ${^})) \ + ${PROJ_LIBS} \ + ${STD_LIBS} \ + -Xlinker --end-group; \ + fi; \ + ${LD} -T $(call fixpath,${LINKERFILE}) \ + --entry ${ENTRY} \ + $(call fixpath,${LDFLAGS}) \ + -o $(call fixpath,${@}) \ + $(call fixpath,$(filter %.o, ${^})) \ + -Xlinker --start-group \ + $(call fixpath,$(filter %.a, ${^})) \ + ${PROJ_LIBS} \ + ${STD_LIBS} \ + -Xlinker --end-group + +# Create S-Record output file +%.srec: %.elf + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo "Creating ${@}"; \ + else \ + echo ${OBJCOPY} -O srec $(call fixpath,${<}) $(call fixpath,${@}); \ + fi + @$(OBJCOPY) -O srec $< $(call fixpath,${@}) + +# Create Intex Hex output file +%.hex: %.elf + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo "Creating ${@}"; \ + else \ + echo ${OBJCOPY} -O ihex $(call fixpath,${<}) $(call fixpath,${@}); \ + fi + @$(OBJCOPY) -O ihex $< $(call fixpath,${@}) + +# Create binary output file +%.bin: %.elf + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo "Creating ${@}"; \ + else \ + echo ${OBJCOPY} -O binary $(call fixpath,${<}) $(call fixpath,${@}); \ + fi + @$(OBJCOPY) -O binary $< $(call fixpath,${@}) + +# Create disassembly file +%.dasm: %.elf + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo "Creating ${@}"; \ + else \ + echo $(OBJDUMP) -S $(call fixpath,${<}) $(call fixpath,${@}); \ + fi + @$(OBJDUMP) -S $< > $(call fixpath,${@}) + +################################################################################ +.PHONY: debug +debug: + @echo CYGWIN = ${CYGWIN} + @echo + @echo BUILD_DIR = ${BUILD_DIR} + @echo + @echo SRCS = ${SRCS} + @echo + @echo SRCS_NOPATH = ${SRCS_NOPATH} + @echo + @echo OBJS_NOPATH = ${OBJS_NOPATH} + @echo + @echo OBJS = ${OBJS} + @echo + @echo LIBS = ${LIBS} + @echo + @echo VPATH = ${VPATH} + @echo + @echo IPATH = ${IPATH} + diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.ld b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.ld new file mode 100644 index 0000000000..6716ab4c24 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.ld @@ -0,0 +1,131 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +MEMORY { + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/periphdriver.mk b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.mk similarity index 59% rename from bsp/maxim/libraries/MAX32660PeriphDriver/periphdriver.mk rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.mk index e2f257354e..7c919de6da 100644 --- a/bsp/maxim/libraries/MAX32660PeriphDriver/periphdriver.mk +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.mk @@ -34,44 +34,50 @@ # ############################################################################### -################################################################################ -# This file can be included in a project makefile to build the library for the -# project. -################################################################################ - -ifeq "$(PERIPH_DRIVER_DIR)" "" -$(error "PERIPH_DRIVER_DIR must be specified") +ifeq "$(CMSIS_ROOT)" "" +$(error CMSIS_ROOT must be specified) endif -# Specify the build directory if not defined by the project +# The build directory ifeq "$(BUILD_DIR)" "" -PERIPH_DRIVER_BUILD_DIR=$(CURDIR)/build/PeriphDriver -else -PERIPH_DRIVER_BUILD_DIR=$(BUILD_DIR)/PeriphDriver +BUILD_DIR=$(CURDIR)/build endif -# Export paths needed by the peripheral driver makefile. Since the makefile to -# build the library will execute in a different directory, paths must be -# specified absolutely -PERIPH_DRIVER_BUILD_DIR := ${abspath ${PERIPH_DRIVER_BUILD_DIR}} -export TOOL_DIR := ${abspath ${TOOL_DIR}} -export CMSIS_ROOT := ${abspath ${CMSIS_ROOT}} +ifeq "$(STARTUPFILE)" "" +STARTUPFILE=startup_max32660.S +endif + +ifeq "$(LINKERFILE)" "" +LINKERFILE=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC/max32660.ld +endif -# Export other variables needed by the peripheral driver makefile -export TARGET -export COMPILER -export TARGET_MAKEFILE -export PROJ_CFLAGS -export PROJ_LDFLAGS -export MXC_OPTIMIZE_CFLAGS +ifeq "$(ENTRY)" "" +ENTRY=Reset_Handler +endif + +# Default TARGET_REVISION +# "A1" in ASCII +ifeq "$(TARGET_REV)" "" +TARGET_REV=0x4131 +endif + +# Add target specific CMSIS source files +ifneq (${MAKECMDGOALS},lib) +SRCS += ${STARTUPFILE} +SRCS += heap.c +SRCS += system_max32660.c +endif -# Add to library list -LIBS += ${PERIPH_DRIVER_BUILD_DIR}/PeriphDriver.a +# Add target specific CMSIS source directories +VPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC +VPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source -# Add to include directory list -IPATH += ${PERIPH_DRIVER_DIR}/Include +# Add target specific CMSIS include directories +IPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Include +IPATH+=$(CMSIS_ROOT)/Include -# Add rule to build the Driver Library -${PERIPH_DRIVER_BUILD_DIR}/PeriphDriver.a: FORCE - $(MAKE) -C ${PERIPH_DRIVER_DIR} lib BUILD_DIR=${PERIPH_DRIVER_BUILD_DIR} +# Add directory with linker include file +LIBPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC +# Include the rules and goals for building +include $(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC/gcc.mk diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator.ld b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator.ld new file mode 100644 index 0000000000..d9c2577dc5 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator.ld @@ -0,0 +1,131 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +MEMORY { + FLASH (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000 +} + +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator_ram.ld b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator_ram.ld new file mode 100644 index 0000000000..e0b6e00460 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator_ram.ld @@ -0,0 +1,132 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +MEMORY { + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000 +} + +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > SRAM + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > SRAM + + .data : + { + _data = ALIGN(., 4); + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + *(.flashprog*) /* Flash program */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>SRAM + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_ram.ld b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_ram.ld new file mode 100644 index 0000000000..06b06a1373 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_ram.ld @@ -0,0 +1,132 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +MEMORY { + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000 +} + +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + *(.flashprog*) /* Flash program */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > SRAM + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > SRAM + + .data : + { + _data = ALIGN(., 4); + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>SRAM + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_sbl.ld b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_sbl.ld new file mode 100644 index 0000000000..20efe97e77 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_sbl.ld @@ -0,0 +1,271 @@ +/******************************************************************************* + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +MEMORY { + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* 256kB "FLASH" */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000 +} + +OUTPUT_FORMAT ("elf32-littlearm") +ENTRY(Reset_Handler) +EXTERN(__start_c main __stack __section_end_heap) + +SECTIONS { + + /* SRAM start/stop addresses used during startup (PreInit(), preinit.S) to initialize ECCEN register + * and initial Error correcting state. (SEC-DED) */ + __sram_ecc_initialize_start = ORIGIN(SRAM); + __sram_ecc_initialize_stop = (ORIGIN(SRAM) + LENGTH(SRAM)); + + .text : ALIGN(0x100) + { + _text = .; + __section_load_nvic = .; + KEEP(*(.isr_vector)) + __section_load_nvic_end = .; + + KEEP(*startup*(.text)) + *(.text*) /* program code */ + *(.flashprog*) /* Flash program */ + KEEP(*(.init)) + KEEP(*(.fini)) + *(.rodata*) /* read-only data: "const" */ + KEEP(*(.iota_rom_params)) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + __section_nvic_size = __section_load_nvic_end - __section_load_nvic; + __section_nvic_start = ORIGIN(SRAM); + __section_nvic_end = __section_nvic_start + __section_nvic_size; + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > FLASH + + .data __section_nvic_end : ALIGN(0x10) + { + _data = ALIGN(., 4); + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + __section_end_data = .; + + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + /** Info block/OTP reserved area */ + __virtual_otp_size = 0x400; + __virtual_end_otp = ORIGIN(FLASH) + LENGTH(FLASH); + __virtual_start_otp = __virtual_end_otp - __virtual_otp_size; + + + /** Free area to program application */ + __virtual_start_iota = ALIGN(__load_data,0x10); + __virtual_end_iota = __virtual_start_otp; + __virtual_iota_size = __virtual_end_iota - __virtual_start_iota; + + /** Work buffer */ + .iota_work __virtual_start_iota : + { + . += __virtual_iota_size; + } + + /** OTP area */ + .iota_otp __virtual_start_otp : + { + . += __virtual_otp_size; + } + + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + + /* Stack and Heap */ + .heap (NOLOAD) : ALIGN(0x80) + { + __section_start_heap = .; + *(.heap*) + __section_end_heap = .; + + } > SRAM + + __section_start_heap_va = __section_start_heap; + __section_end_heap_va = __section_start_heap_va + SIZEOF(.heap); + + .stack __section_end_heap : ALIGN(0x80) + { + __section_start_stack = .; + *(.stack*) + _stack = .; + __section_end_stack = .; + + } > SRAM + __stack_va = __stack; + + PROVIDE(__stack = _stack); + + /* ======================================================================== */ + /** RAM for STP and SCP **/ + __section_protocol_ram_end = (ORIGIN(SRAM) + LENGTH(SRAM)); + __region_end_ram = (ORIGIN(SRAM) + LENGTH(SRAM)); + + /** Cryptography work buffer */ + .iota_work.sh __section_end_stack : ALIGN(0x10) + { + KEEP(*(.iota_work.sh)) + } >SRAM=0 + + __iota_work_sh_start = LOADADDR(.iota_work.sh); + __iota_work_sh_end = LOADADDR(.iota_work.sh) + SIZEOF(.iota_work.sh); + __iota_work_sh_size = SIZEOF(.iota_work.sh); + + /** Configuration Management work buffer */ + .iota_work.cm __iota_work_sh_end : ALIGN(0x10) + { + KEEP(*(.iota_work.cm)) + } >SRAM=0 + + __iota_work_cm_start = LOADADDR(.iota_work.cm); + __iota_work_cm_end = LOADADDR(.iota_work.cm) + SIZEOF(.iota_work.cm); + __iota_work_cm_size = SIZEOF(.iota_work.cm); + + /** RCE Signature check work buffer */ + .iota_work.rce __iota_work_cm_end : ALIGN(0x10) + { + KEEP(*(.iota_work.rce)) + + } >SRAM=0 + + __iota_work_rce_start = LOADADDR(.iota_work.rce); + __iota_work_rce_end = LOADADDR(.iota_work.rce) + SIZEOF(.iota_work.rce); + __iota_work_rce_size = SIZEOF(.iota_work.rce); + + /* ======================================================================== */ + + /** STP Application, SCP Applet memory areas */ + .protocol_ram.stack __iota_work_rce_end : ALIGN(0x10) + { + __section_protocol_start = .; + /** Stack dedicated to STP/SCP application matter if needed */ + __section_start_stp_stack = .; + KEEP(*(.protocol_ram.stack)) + /* . += __stack_size_stp;*/ + __stack_stp = .; + + } >SRAM + __section_end_stp_stack = .; + + .protocol_ram.bss __section_end_stp_stack : ALIGN(0x10) + { + *stp_*(.bss .bss.* .gnu.linkonce.b.*) + + } >SRAM + + __section_start_bss_stp = LOADADDR(.protocol_ram.bss); + __section_end_bss_stp = LOADADDR(.protocol_ram.bss) + SIZEOF(.protocol_ram.bss); + __section_bss_stp_size = SIZEOF(.protocol_ram.bss); + + .protocol_ram __section_end_bss_stp : ALIGN(0x10) + { + /** Code part */ + KEEP(*stp_*(.data .data.* .gnu.linkonce.d.*)) + KEEP(*(.protocol_ram)) + + } >SRAM + __section_protocol_end = ALIGN(0x10); + __scp_applet_area_size = __section_protocol_ram_end - __section_protocol_end; + + /** Lasting free internal SRAM space */ + .iota_scp_applet __section_protocol_end : ALIGN(0x10) + { + __scp_applet_start = .; + . += __scp_applet_area_size; + __scp_applet_end = .; + + } >SRAM + + __section_scp_start = LOADADDR(.protocol_ram); + __section_scp_stop = LOADADDR(.iota_scp_applet) + SIZEOF(.iota_scp_applet); + + __section_bss_size_stp = __section_end_bss_stp - __section_start_bss_stp; + __section_stp_size = SIZEOF(.protocol_ram.stack) + SIZEOF(.protocol_ram.bss) + SIZEOF(.protocol_ram); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S new file mode 100644 index 0000000000..c7ca195d79 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S @@ -0,0 +1,314 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Device-specific Interrupts */ + .long PF_IRQHandler /* 0x10 0x0040 16: Power Fail */ + .long WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */ + .long RSV00_IRQHandler /* 0x12 0x0048 18: RSV00 */ + .long RTC_IRQHandler /* 0x13 0x004C 19: RTC */ + .long RSV1_IRQHandler /* 0x14 0x0050 20: RSV1 */ + .long TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */ + .long TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */ + .long TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */ + .long RSV02_IRQHandler /* 0x18 0x0060 24: RSV02 */ + .long RSV03_IRQHandler /* 0x19 0x0064 25: RSV03 */ + .long RSV04_IRQHandler /* 0x1A 0x0068 26: RSV04 */ + .long RSV05_IRQHandler /* 0x1B 0x006C 27: RSV05 */ + .long RSV06_IRQHandler /* 0x1C 0x0070 28: RSV06 */ + .long I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */ + .long UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */ + .long UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */ + .long SPI0_IRQHandler /* 0x20 0x0080 32: SPIY17 */ + .long SPI1_IRQHandler /* 0x21 0x0084 33: SPIMSS */ + .long RSV07_IRQHandler /* 0x22 0x0088 34: RSV07 */ + .long RSV08_IRQHandler /* 0x23 0x008C 35: RSV08 */ + .long RSV09_IRQHandler /* 0x24 0x0090 36: RSV09 */ + .long RSV10_IRQHandler /* 0x25 0x0094 37: RSV10 */ + .long RSV11_IRQHandler /* 0x26 0x0098 38: RSV11 */ + .long FLC_IRQHandler /* 0x27 0x009C 39: FLC */ + .long GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */ + .long RSV12_IRQHandler /* 0x29 0x00A4 41: RSV12 */ + .long RSV13_IRQHandler /* 0x2A 0x00A8 42: RSV13 */ + .long RSV14_IRQHandler /* 0x2B 0x00AC 43: RSV14 */ + .long DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */ + .long DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */ + .long DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */ + .long DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */ + .long RSV15_IRQHandler /* 0x30 0x00C0 48: RSV15 */ + .long RSV16_IRQHandler /* 0x31 0x00C4 49: RSV16 */ + .long RSV17_IRQHandler /* 0x32 0x00C8 50: RSV17 */ + .long RSV18_IRQHandler /* 0x33 0x00CC 51: RSV18 */ + .long I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */ + .long RSV19_IRQHandler /* 0x35 0x00D4 53: RSV19 */ + .long RSV20_IRQHandler /* 0x36 0x00D8 54: RSV20 */ + .long RSV21_IRQHandler /* 0x37 0x00DC 55: RSV21 */ + .long RSV22_IRQHandler /* 0x38 0x00E0 56: RSV22 */ + .long RSV23_IRQHandler /* 0x39 0x00E4 57: RSV23 */ + .long RSV24_IRQHandler /* 0x3A 0x00E8 58: RSV24 */ + .long RSV25_IRQHandler /* 0x3B 0x00EC 59: RSV25 */ + .long RSV26_IRQHandler /* 0x3C 0x00F0 60: RSV26 */ + .long RSV27_IRQHandler /* 0x3D 0x00F4 61: RSV27 */ + .long RSV28_IRQHandler /* 0x3E 0x00F8 62: RSV28 */ + .long RSV29_IRQHandler /* 0x3F 0x00FC 63: RSV29 */ + .long RSV30_IRQHandler /* 0x40 0x0100 64: RSV30 */ + .long RSV31_IRQHandler /* 0x41 0x0104 65: RSV31 */ + .long RSV32_IRQHandler /* 0x42 0x0108 66: RSV32 */ + .long RSV33_IRQHandler /* 0x43 0x010C 67: RSV33 */ + .long RSV34_IRQHandler /* 0x44 0x0110 68: RSV34 */ + .long RSV35_IRQHandler /* 0x45 0x0114 69: RSV35 */ + .long GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */ + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =__StackTop + mov sp, r0 + + /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ + ldr r0, =PreInit + blx r0 + cbnz r0, .SKIPRAMINIT + +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __load_data: Where data sections are saved. + * _data /_edata: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__load_data + ldr r2, =_data + ldr r3, =_edata + +#if 0 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +/* + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * _bss : start of BSS section. Must align to 4 + * _ebss : end of BSS section. Must align to 4 + */ + ldr r1, =_bss + ldr r2, =_ebss + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 + +.SKIPRAMINIT: + + /* Perform system initialization after RAM initialization */ + ldr r0, =SystemInit + blx r0 + + /* This must be called to walk the constructor array for static C++ objects */ + /* Note: The linker file must have .data symbols for __X_array_start and __X_array_end */ + /* where X is {preinit, init, fini} */ + ldr r0, =__libc_init_array + blx r0 + + /* Transfer control to users main program */ + ldr r0, =main + blx r0 + +.SPIN: + /* spin if main ever returns. */ + bl .SPIN + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + /* SysTick_Handler is defined in mxc_delay.c */ + def_irq_handler Default_Handler + + /* Device-specific Interrupts */ + def_irq_handler PF_IRQHandler /* 0x10 0x0040 16: Power Fail */ + def_irq_handler WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */ + def_irq_handler RSV00_IRQHandler /* 0x12 0x0048 18: RSV00 */ + def_irq_handler RTC_IRQHandler /* 0x13 0x004C 19: RTC */ + def_irq_handler RSV1_IRQHandler /* 0x14 0x0050 20: RSV1 */ + def_irq_handler TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */ + def_irq_handler TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */ + def_irq_handler TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */ + def_irq_handler RSV02_IRQHandler /* 0x18 0x0060 24: RSV02 */ + def_irq_handler RSV03_IRQHandler /* 0x19 0x0064 25: RSV03 */ + def_irq_handler RSV04_IRQHandler /* 0x1A 0x0068 26: RSV04 */ + def_irq_handler RSV05_IRQHandler /* 0x1B 0x006C 27: RSV05 */ + def_irq_handler RSV06_IRQHandler /* 0x1C 0x0070 28: RSV06 */ + def_irq_handler I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */ + def_irq_handler UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */ + def_irq_handler UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */ + def_irq_handler SPI0_IRQHandler /* 0x20 0x0080 32: SPIY17 */ + def_irq_handler SPI1_IRQHandler /* 0x21 0x0084 33: SPIMSS */ + def_irq_handler RSV07_IRQHandler /* 0x22 0x0088 34: RSV07 */ + def_irq_handler RSV08_IRQHandler /* 0x23 0x008C 35: RSV08 */ + def_irq_handler RSV09_IRQHandler /* 0x24 0x0090 36: RSV09 */ + def_irq_handler RSV10_IRQHandler /* 0x25 0x0094 37: RSV10 */ + def_irq_handler RSV11_IRQHandler /* 0x26 0x0098 38: RSV11 */ + def_irq_handler FLC_IRQHandler /* 0x27 0x009C 39: FLC */ + def_irq_handler GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */ + def_irq_handler RSV12_IRQHandler /* 0x29 0x00A4 41: RSV12 */ + def_irq_handler RSV13_IRQHandler /* 0x2A 0x00A8 42: RSV13 */ + def_irq_handler RSV14_IRQHandler /* 0x2B 0x00AC 43: RSV14 */ + def_irq_handler DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */ + def_irq_handler DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */ + def_irq_handler DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */ + def_irq_handler DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */ + def_irq_handler RSV15_IRQHandler /* 0x30 0x00C0 48: RSV15 */ + def_irq_handler RSV16_IRQHandler /* 0x31 0x00C4 49: RSV16 */ + def_irq_handler RSV17_IRQHandler /* 0x32 0x00C8 50: RSV17 */ + def_irq_handler RSV18_IRQHandler /* 0x33 0x00CC 51: RSV18 */ + def_irq_handler I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */ + def_irq_handler RSV19_IRQHandler /* 0x35 0x00D4 53: RSV19 */ + def_irq_handler RSV20_IRQHandler /* 0x36 0x00D8 54: RSV20 */ + def_irq_handler RSV21_IRQHandler /* 0x37 0x00DC 55: RSV21 */ + def_irq_handler RSV22_IRQHandler /* 0x38 0x00E0 56: RSV22 */ + def_irq_handler RSV23_IRQHandler /* 0x39 0x00E4 57: RSV23 */ + def_irq_handler RSV24_IRQHandler /* 0x3A 0x00E8 58: RSV24 */ + def_irq_handler RSV25_IRQHandler /* 0x3B 0x00EC 59: RSV25 */ + def_irq_handler RSV26_IRQHandler /* 0x3C 0x00F0 60: RSV26 */ + def_irq_handler RSV27_IRQHandler /* 0x3D 0x00F4 61: RSV27 */ + def_irq_handler RSV28_IRQHandler /* 0x3E 0x00F8 62: RSV28 */ + def_irq_handler RSV29_IRQHandler /* 0x3F 0x00FC 63: RSV29 */ + def_irq_handler RSV30_IRQHandler /* 0x40 0x0100 64: RSV30 */ + def_irq_handler RSV31_IRQHandler /* 0x41 0x0104 65: RSV31 */ + def_irq_handler RSV32_IRQHandler /* 0x42 0x0108 66: RSV32 */ + def_irq_handler RSV33_IRQHandler /* 0x43 0x010C 67: RSV33 */ + def_irq_handler RSV34_IRQHandler /* 0x44 0x0110 68: RSV34 */ + def_irq_handler RSV35_IRQHandler /* 0x45 0x0114 69: RSV35 */ + def_irq_handler GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */ + + .end diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/cmain.s b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/cmain.s new file mode 100644 index 0000000000..00dab914e2 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/cmain.s @@ -0,0 +1,79 @@ +/************************************************** + * + * Part two of the system initialization code, contains C-level + * initialization, thumb-2 only variant. + * + * Copyright 2006 IAR Systems. All rights reserved. + * + * $Revision: 36818 $ + * + **************************************************/ + + +; -------------------------------------------------- +; Module ?cmain, C-level initialization. +; + + + SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2) + SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2) + + SECTION .text:CODE:NOROOT(2) + + PUBLIC __cmain + ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world... + PUBLIC ?main + EXTWEAK __iar_data_init3 + EXTWEAK __iar_argc_argv + EXTERN __low_level_init + EXTERN __call_ctors + EXTERN SystemInit + EXTERN main + EXTERN exit + + THUMB +__cmain: +?main: + +; Initialize segments. +; __segment_init and __low_level_init are assumed to use the same +; instruction set and to be reachable by BL from the ICODE segment +; (it is safest to link them in segment ICODE). + + FUNCALL __cmain, __low_level_init + bl __low_level_init + cmp r0,#0 + beq ?l1 + + FUNCALL __cmain, __iar_data_init3 + bl __iar_data_init3 + +?l1: + REQUIRE ?l3 + + SECTION .text:CODE:NOROOT(2) + + PUBLIC _main + PUBLIC _call_main + THUMB + +__iar_init$$done: ; Copy initialization is done + +?l3: +_call_main: +; Static Initialization is complete. Call the SystemInit function to +; set up the device and system. + FUNCALL __cmain, SystemInit + BL SystemInit + MOVS r0,#0 ; No parameters + + FUNCALL __cmain, __iar_argc_argv + BL __iar_argc_argv ; Maybe setup command line + + FUNCALL __cmain, main + BL main +_main: + FUNCALL __cmain, exit + BL exit + + END diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/low_level_init.c b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/low_level_init.c new file mode 100644 index 0000000000..73c13ee148 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/low_level_init.c @@ -0,0 +1,50 @@ +/* ************************************************* + * + * This module contains the function `__low_level_init', a function + * that is called before the `main' function of the program. Normally + * low-level initializations - such as setting the prefered interrupt + * level or setting the watchdog - can be performed here. + * + * Note that this function is called before the data segments are + * initialized, this means that this function cannot rely on the + * values of global or static variables. + * + * When this function returns zero, the startup code will inhibit the + * initialization of the data segments. The result is faster startup, + * the drawback is that neither global nor static data will be + * initialized. + * + * Copyright 1999-2004 IAR Systems. All rights reserved. + * + * $Revision: 36818 $ + * + ************************************************* */ + +#ifdef __cplusplus +extern "C" { +#endif + +extern int PreInit(void); + +#pragma language=extended + +__interwork int __low_level_init(void); + +__interwork int __low_level_init(void) +{ + /*====================================*/ + /* Initialize hardware. */ + /* AND */ + /* Choose if segment initialization */ + /* should be done or not. */ + /* Return: 0 to omit seg_init */ + /* 1 to run seg_init */ + /*====================================*/ + return !PreInit(); // See system_max32660.c +} + +#pragma language=default + +#ifdef __cplusplus +} +#endif diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/startup_max32660.s b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/startup_max32660.s new file mode 100644 index 0000000000..83405f8b97 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/startup_max32660.s @@ -0,0 +1,480 @@ +;******************************************************************************* +;* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. +;* +;* Permission is hereby granted, free of charge, to any person obtaining a +;* copy of this software and associated documentation files (the "Software"), +;* to deal in the Software without restriction, including without limitation +;* the rights to use, copy, modify, merge, publish, distribute, sublicense, +;* and/or sell copies of the Software, and to permit persons to whom the +;* Software is furnished to do so, subject to the following conditions: +;* +;* The above copyright notice and this permission notice shall be included +;* in all copies or substantial portions of the Software. +;* +;* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +;* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +;* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +;* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +;* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +;* OTHER DEALINGS IN THE SOFTWARE. +;* +;* Except as contained in this notice, the name of Maxim Integrated +;* Products, Inc. shall not be used except as stated in the Maxim Integrated +;* Products, Inc. Branding Policy. +;* +;* The mere transfer of this software does not imply any licenses +;* of trade secrets, proprietary technology, copyrights, patents, +;* trademarks, maskwork rights, or any other form of intellectual +;* property whatsoever. Maxim Integrated Products, Inc. retains all +;* ownership rights. +;* +;* Description : MAX32660 device vector table for IAR EWARM toolchain. +;* - Sets the initial SP +;* - Sets the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, all set as PUBWEAK. User may override any ISR +;* defined as PUBWEAK. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + ; EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __isr_vector + PUBLIC __vector_table_modify + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA +__vector_table +__isr_vector + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_modify + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; MAX32660 Device-specific Interrupts + DCD PF_IRQHandler ; /* 0x10 0x0040 16: Power Fail */ + DCD WDT0_IRQHandler ; /* 0x11 0x0044 17: Watchdog 0 */ + DCD RSV00_IRQHandler ; /* 0x12 0x0048 18: RSV00 */ + DCD RTC_IRQHandler ; /* 0x13 0x004C 19: RTC */ + DCD RSV1_IRQHandler ; /* 0x14 0x0050 20: RSV1 */ + DCD TMR0_IRQHandler ; /* 0x15 0x0054 21: Timer 0 */ + DCD TMR1_IRQHandler ; /* 0x16 0x0058 22: Timer 1 */ + DCD TMR2_IRQHandler ; /* 0x17 0x005C 23: Timer 2 */ + DCD RSV02_IRQHandler ; /* 0x18 0x0060 24: RSV02 */ + DCD RSV03_IRQHandler ; /* 0x19 0x0064 25: RSV03 */ + DCD RSV04_IRQHandler ; /* 0x1A 0x0068 26: RSV04 */ + DCD RSV05_IRQHandler ; /* 0x1B 0x006C 27: RSV05 */ + DCD RSV06_IRQHandler ; /* 0x1C 0x0070 28: RSV06 */ + DCD I2C0_IRQHandler ; /* 0x1D 0x0074 29: I2C0 */ + DCD UART0_IRQHandler ; /* 0x1E 0x0078 30: UART 0 */ + DCD UART1_IRQHandler ; /* 0x1F 0x007C 31: UART 1 */ + DCD SPI0_IRQHandler ; /* 0x20 0x0080 32: SPI0 */ + DCD SPI1_IRQHandler ; /* 0x21 0x0084 33: SPI1 */ + DCD RSV07_IRQHandler ; /* 0x22 0x0088 34: RSV07 */ + DCD RSV08_IRQHandler ; /* 0x23 0x008C 35: RSV08 */ + DCD RSV09_IRQHandler ; /* 0x24 0x0090 36: RSV09 */ + DCD RSV10_IRQHandler ; /* 0x25 0x0094 37: RSV10 */ + DCD RSV11_IRQHandler ; /* 0x26 0x0098 38: RSV11 */ + DCD FLC_IRQHandler ; /* 0x27 0x009C 39: FLC */ + DCD GPIO0_IRQHandler ; /* 0x28 0x00A0 40: GPIO0 */ + DCD RSV12_IRQHandler ; /* 0x29 0x00A4 41: RSV12 */ + DCD RSV13_IRQHandler ; /* 0x2A 0x00A8 42: RSV13 */ + DCD RSV14_IRQHandler ; /* 0x2B 0x00AC 43: RSV14 */ + DCD DMA0_IRQHandler ; /* 0x2C 0x00B0 44: DMA0 */ + DCD DMA1_IRQHandler ; /* 0x2D 0x00B4 45: DMA1 */ + DCD DMA2_IRQHandler ; /* 0x2E 0x00B8 46: DMA2 */ + DCD DMA3_IRQHandler ; /* 0x2F 0x00BC 47: DMA3 */ + DCD RSV15_IRQHandler ; /* 0x30 0x00C0 48: RSV15 */ + DCD RSV16_IRQHandler ; /* 0x31 0x00C4 49: RSV16 */ + DCD RSV17_IRQHandler ; /* 0x32 0x00C8 50: RSV17 */ + DCD RSV18_IRQHandler ; /* 0x33 0x00CC 51: RSV18 */ + DCD I2C1_IRQHandler ; /* 0x34 0x00D0 52: I2C1 */ + DCD RSV19_IRQHandler ; /* 0x35 0x00D4 53: RSV19 */ + DCD RSV20_IRQHandler ; /* 0x36 0x00D8 54: RSV20 */ + DCD RSV21_IRQHandler ; /* 0x37 0x00DC 55: RSV21 */ + DCD RSV22_IRQHandler ; /* 0x38 0x00E0 56: RSV22 */ + DCD RSV23_IRQHandler ; /* 0x39 0x00E4 57: RSV23 */ + DCD RSV24_IRQHandler ; /* 0x3A 0x00E8 58: RSV24 */ + DCD RSV25_IRQHandler ; /* 0x3B 0x00EC 59: RSV25 */ + DCD RSV26_IRQHandler ; /* 0x3C 0x00F0 60: RSV26 */ + DCD RSV27_IRQHandler ; /* 0x3D 0x00F4 61: RSV27 */ + DCD RSV28_IRQHandler ; /* 0x3E 0x00F8 62: RSV28 */ + DCD RSV29_IRQHandler ; /* 0x3F 0x00FC 63: RSV29 */ + DCD RSV30_IRQHandler ; /* 0x40 0x0100 64: RSV30 */ + DCD RSV31_IRQHandler ; /* 0x41 0x0104 65: RSV31 */ + DCD RSV32_IRQHandler ; /* 0x42 0x0108 66: RSV32 */ + DCD RSV33_IRQHandler ; /* 0x43 0x010C 67: RSV33 */ + DCD RSV34_IRQHandler ; /* 0x44 0x0110 68: RSV34 */ + DCD RSV35_IRQHandler ; /* 0x45 0x0114 69: RSV35 */ + DCD GPIOWAKE_IRQHandler ; /* 0x46 0x0118 70: GPIO Wakeup */ + ; Continue this pattern when vectors are eventually assigned by hardware + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + ; IAR: PreInit is called from low_level_init.c + ; IAR: SystemInit is called from cmain.s + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + +; SysTick Handler is defined in mxc_delay.c +; PUBWEAK SysTick_Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +; SysTick_Handler +; B SysTick_Handler + + PUBWEAK PF_IRQHandler ; /* 0x10 0x0040 16: Power Fail */ + SECTION .text:CODE:REORDER:NOROOT(1) +PF_IRQHandler + B PF_IRQHandler + + PUBWEAK WDT0_IRQHandler ; /* 0x11 0x0044 17: Watchdog 0 */ + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_IRQHandler + B WDT0_IRQHandler + + PUBWEAK RSV00_IRQHandler ; /* 0x12 0x0048 18: RSV00 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV00_IRQHandler + B RSV00_IRQHandler + + PUBWEAK RTC_IRQHandler ; /* 0x13 0x004C 19: RTC */ + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK RSV1_IRQHandler ; /* 0x14 0x0050 20: RSV1 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV1_IRQHandler + B RSV1_IRQHandler + + PUBWEAK TMR0_IRQHandler ; /* 0x15 0x0054 21: Timer 0 */ + SECTION .text:CODE:REORDER:NOROOT(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + PUBWEAK TMR1_IRQHandler ; /* 0x16 0x0058 22: Timer 1 */ + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + PUBWEAK TMR2_IRQHandler ; /* 0x17 0x005C 23: Timer 2 */ + SECTION .text:CODE:REORDER:NOROOT(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK RSV02_IRQHandler ; /* 0x18 0x0060 24: RSV02 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV02_IRQHandler + B RSV02_IRQHandler + + PUBWEAK RSV03_IRQHandler ; /* 0x19 0x0064 25: RSV03 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV03_IRQHandler + B RSV03_IRQHandler + + PUBWEAK RSV04_IRQHandler ; /* 0x1A 0x0068 26: RSV04 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV04_IRQHandler + B RSV04_IRQHandler + + PUBWEAK RSV05_IRQHandler ; /* 0x1B 0x006C 27: RSV05 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV05_IRQHandler + B RSV05_IRQHandler + + PUBWEAK RSV06_IRQHandler ; /* 0x1C 0x0070 28: RSV06 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV06_IRQHandler + B RSV06_IRQHandler + + PUBWEAK I2C0_IRQHandler ; /* 0x1D 0x0074 29: I2C0 */ + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK UART0_IRQHandler ; /* 0x1E 0x0078 30: UART 0 */ + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK UART1_IRQHandler ; /* 0x1F 0x007C 31: UART 1 */ + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK SPI0_IRQHandler ; /* 0x20 0x0080 32: SPI0 */ + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler ; /* 0x21 0x0084 33: SPI1 */ + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK RSV07_IRQHandler ; /* 0x22 0x0088 34: RSV07 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV07_IRQHandler + B RSV07_IRQHandler + + PUBWEAK RSV08_IRQHandler ; /* 0x23 0x008C 35: RSV08 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV08_IRQHandler + B RSV08_IRQHandler + + PUBWEAK RSV09_IRQHandler ; /* 0x24 0x0090 36: RSV09 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV09_IRQHandler + B RSV09_IRQHandler + + PUBWEAK RSV10_IRQHandler ; /* 0x25 0x0094 37: RSV10 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV10_IRQHandler + B RSV10_IRQHandler + + PUBWEAK RSV11_IRQHandler ; /* 0x26 0x0098 38: RSV11 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV11_IRQHandler + B RSV11_IRQHandler + + PUBWEAK FLC_IRQHandler ; /* 0x27 0x009C 39: FLC */ + SECTION .text:CODE:REORDER:NOROOT(1) +FLC_IRQHandler + B FLC_IRQHandler + + PUBWEAK GPIO0_IRQHandler ; /* 0x28 0x00A0 40: GPIO0 */ + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO0_IRQHandler + B GPIO0_IRQHandler + + PUBWEAK RSV12_IRQHandler ; /* 0x29 0x00A4 41: RSV12 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV12_IRQHandler + B RSV12_IRQHandler + + PUBWEAK RSV13_IRQHandler ; /* 0x2A 0x00A8 42: RSV13 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV13_IRQHandler + B RSV13_IRQHandler + + PUBWEAK RSV14_IRQHandler ; /* 0x2B 0x00AC 43: RSV14 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV14_IRQHandler + B RSV14_IRQHandler + + PUBWEAK DMA0_IRQHandler ; /* 0x2C 0x00B0 44: DMA0 */ + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_IRQHandler + B DMA0_IRQHandler + + PUBWEAK DMA1_IRQHandler ; /* 0x2D 0x00B4 45: DMA1 */ + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_IRQHandler + B DMA1_IRQHandler + + PUBWEAK DMA2_IRQHandler ; /* 0x2E 0x00B8 46: DMA2 */ + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_IRQHandler + B DMA2_IRQHandler + + PUBWEAK DMA3_IRQHandler ; /* 0x2F 0x00BC 47: DMA3 */ + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_IRQHandler + B DMA3_IRQHandler + + PUBWEAK RSV15_IRQHandler ; /* 0x30 0x00C0 48: RSV15 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV15_IRQHandler + B RSV15_IRQHandler + + PUBWEAK RSV16_IRQHandler ; /* 0x31 0x00C4 49: RSV16 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV16_IRQHandler + B RSV16_IRQHandler + + PUBWEAK RSV17_IRQHandler ; /* 0x32 0x00C8 50: RSV17 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV17_IRQHandler + B RSV17_IRQHandler + + PUBWEAK RSV18_IRQHandler ; /* 0x33 0x00CC 51: RSV18 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV18_IRQHandler + B RSV18_IRQHandler + + PUBWEAK I2C1_IRQHandler ; /* 0x34 0x00D0 52: I2C1 */ + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK RSV19_IRQHandler ; /* 0x35 0x00D4 53: RSV19 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV19_IRQHandler + B RSV19_IRQHandler + + PUBWEAK RSV20_IRQHandler ; /* 0x36 0x00D8 54: RSV20 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV20_IRQHandler + B RSV20_IRQHandler + + PUBWEAK RSV21_IRQHandler ; /* 0x37 0x00DC 55: RSV21 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV21_IRQHandler + B RSV21_IRQHandler + + PUBWEAK RSV22_IRQHandler ; /* 0x38 0x00E0 56: RSV22 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV22_IRQHandler + B RSV22_IRQHandler + + PUBWEAK RSV23_IRQHandler ; /* 0x39 0x00E4 57: RSV23 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV23_IRQHandler + B RSV23_IRQHandler + + PUBWEAK RSV24_IRQHandler ; /* 0x3A 0x00E8 58: RSV24 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV24_IRQHandler + B RSV24_IRQHandler + + PUBWEAK RSV25_IRQHandler ; /* 0x3B 0x00EC 59: RSV25 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV25_IRQHandler + B RSV25_IRQHandler + + PUBWEAK RSV26_IRQHandler ; /* 0x3C 0x00F0 60: RSV26 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV26_IRQHandler + B RSV26_IRQHandler + + PUBWEAK RSV27_IRQHandler ; /* 0x3D 0x00F4 61: RSV27 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV27_IRQHandler + B RSV27_IRQHandler + + PUBWEAK RSV28_IRQHandler ; /* 0x3E 0x00F8 62: RSV28 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV28_IRQHandler + B RSV28_IRQHandler + + PUBWEAK RSV29_IRQHandler ; /* 0x3F 0x00FC 63: RSV29 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV29_IRQHandler + B RSV29_IRQHandler + + PUBWEAK RSV30_IRQHandler ; /* 0x40 0x0100 64: RSV30 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV30_IRQHandler + B RSV30_IRQHandler + + PUBWEAK RSV31_IRQHandler ; /* 0x41 0x0104 65: RSV31 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV31_IRQHandler + B RSV31_IRQHandler + + PUBWEAK RSV32_IRQHandler ; /* 0x42 0x0108 66: RSV32 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV32_IRQHandler + B RSV32_IRQHandler + + PUBWEAK RSV33_IRQHandler ; /* 0x43 0x010C 67: RSV33 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV33_IRQHandler + B RSV33_IRQHandler + + PUBWEAK RSV34_IRQHandler ; /* 0x44 0x0110 68: RSV34 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV34_IRQHandler + B RSV34_IRQHandler + + PUBWEAK RSV35_IRQHandler ; /* 0x45 0x0114 69: RSV35 */ + SECTION .text:CODE:REORDER:NOROOT(1) +RSV35_IRQHandler + B RSV35_IRQHandler + + PUBWEAK GPIOWAKE_IRQHandler ; /* 0x46 0x0118 70: GPIO Wakeup */ + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOWAKE_IRQHandler + B GPIOWAKE_IRQHandler + + + END diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/heap.c b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/heap.c new file mode 100644 index 0000000000..af27605ce9 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/heap.c @@ -0,0 +1,77 @@ + /** + * @file heap.c + * @brief System level setup help + */ + +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include +#include + +/** + * @brief sbrk + * @detail Increase program data space + * @detail Malloc and related functions depend on this + */ + +/* **** declarations **** */ +static char *heap_end = 0; +extern unsigned int __HeapBase; +extern unsigned int __HeapLimit; + +/* **** functions **** */ +caddr_t _sbrk(int incr) +{ + char *prev_heap_end; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + prev_heap_end = heap_end; + + if ((unsigned int)(heap_end + incr) > (unsigned int)&__HeapLimit) { + errno = ENOMEM; + return (caddr_t) -1; + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} + diff --git a/bsp/maxim/libraries/CMSIS/system_max32660.c b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c similarity index 100% rename from bsp/maxim/libraries/CMSIS/system_max32660.c rename to bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/SConscript b/bsp/maxim/libraries/MAX32660PeriphDriver/SConscript new file mode 100644 index 0000000000..fa62f76fb7 --- /dev/null +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/SConscript @@ -0,0 +1,50 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Split(''' +CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c +Source/gpio.c +Source/lp.c +Source/tmr.c +Source/tmr_utils.c +Source/rtc.c +Source/icc.c +Source/mxc_lock.c +Source/mxc_assert.c +Source/mxc_delay.c +Source/mxc_pins.c +Source/mxc_sys.c +Source/nvic_table.c +''') + +if GetDepend(['RT_USING_SERIAL']): + src += ['Source/uart.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['Source/i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['Source/spi.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['Source/rtc.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['Source/wdt.c'] + +path = [cwd + '/CMSIS/Device/Maxim/MAX32660/Include', + cwd + '/CMSIS/Core/Include', + cwd + '/Include'] + +CPPDEFINES = ['TARGET=32660'] +CPPDEFINES += ['TARGET_REV=0x4131'] + + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') -- GitLab